MCIMX6S6AVM08AC

NXP Semiconductors Data Sheet: Technical Data Document Number: IMX6SDLAEC Rev. 9, 11/2018 MCIMX6SxAxxxxxB MCIMX6UxAxxxxxB MCIMX6SxAxxxxxC MCIMX6UxAxxxxxC MCIMX6SxAxxxxxD MCIMX6UxAxxxxxD i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors Package Information Plastic Package BGA Case 2240 21 x 21 mm, 0.8 mm pitch Ordering Information See Table 1 on page 3 1 Introduction The i.MX 6Solo/6DualLite automotive and infotainment processors represent the latest achievement in integrated multimedia-focused products offering high-performance processing with a high degree of functional integration. These processors are designed considering the needs of the growing automotive infotainment, telematics, HMI, and display-based cluster markets. The processors feature advanced implementation of single/dual Arm® Cortex®-A9 core, which operates at speeds of up to 1 GHz. They include 2D and 3D graphics processors, 1080p video processing, and integrated power management. Each processor provides a 32/64-bit DDR3/DDR3L/LPDDR2-800 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth®, GPS, hard drive, displays, and camera sensors. 1 2 3 4 5 6 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 Updated Signal Naming Convention . . . . . . . . . . . .9 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1 Special Signal Considerations . . . . . . . . . . . . . . . .21 3.2 Recommended Connections for Unused Analog Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .23 4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .23 4.2 Power Supplies Requirements and Restrictions . .33 4.3 Integrated LDO Voltage Regulator Parameters . . .34 4.4 PLL’s Electrical Characteristics . . . . . . . . . . . . . . .36 4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .38 4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .39 4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .44 4.8 Output Buffer Impedance Parameters . . . . . . . . . .49 4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .52 4.10 General-Purpose Media Interface (GPMI) Timing .64 4.11 External Peripheral Interface Parameters . . . . . . .72 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .134 5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .134 5.2 Boot Device Interface Allocation . . . . . . . . . . . . .135 Package Information and Contact Assignments . . . . . .136 6.1 Updated Signal Naming Convention . . . . . . . . . .136 6.2 21x21 mm Package Information. . . . . . . . . . . . . .137 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 NXP Reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products Introduction The i.MX 6Solo/6DualLite processors are specifically useful for applications such as: • Automotive navigation and entertainment • Graphics rendering for Human Machine Interfaces (HMI) • High-performance speech processing with large databases • Audio playback • Video processing and display The i.MX 6Solo/6DualLite applications processors feature: • Multilevel memory system—The multilevel memory system of each processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The processors support many types of external memory devices, including DDR3, DDR3L, LPDDR2, NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND, including eMMC up to rev 4.4/4.41. • Smart speed technology—The processors have power management throughout the IC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart speed technology enables the designer to deliver a feature-rich product, requiring levels of power far lower than industry expectations. • Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices by scaling the voltage and frequency to optimize performance. • Multimedia powerhouse—The multimedia performance of each processor is enhanced by a multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, a multi-standard hardware video codec, an image processing unit (IPU), a programmable smart DMA (SDMA) controller, and an asynchronous sample rate converter. • Powerful graphics acceleration—Each processor provides two independent, integrated graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator with a shader and a 2D graphics accelerator. • Interface flexibility—Each processor supports connections to a variety of interfaces: LCD controller for up to two displays (including parallel display, HDMI1.4, MIPI display, and LVDS display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host and other), 10/100/1000 Mbps Gigabit Ethernet controller two CAN ports, ESAI audio interface, and a variety of other popular interfaces (such as UART, I2C, and I2S serial audio, and PCIe-II). • Automotive environment support—Each processor includes interfaces, such as two CAN ports, an MLB150/50 port, an ESAI audio interface, and an asynchronous sample rate converter for multichannel/multisource audio. • Advanced security—The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. The security features are discussed in detail in the i.MX 6Solo/6DualLite Security Reference Manual (IMX6DQ6SDLSRM). • Integrated power management—The processors integrate linear regulators and internally generate voltage levels for different domains. This significantly simplifies system power management structure. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 2 NXP Semiconductors Introduction 1.1 Ordering Information Table 1 provides examples of orderable part numbers covered by this data sheet. Table 1 does not include all possible orderable part numbers. The latest part numbers are available on the web page nxp.com/imx6series. If the desired part number is not listed in Table 1, go to nxp.com/imx6series or contact a NXP representative for details. Table 1. Example Orderable Part Numbers Part Number i.MX6 CPU Solo/ DualLite Options Speed Grade1 Temperature Grade Package MCIMX6U6AVM08AB DualLite With VPU, GPU, MLB, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U6AVM08AC DualLite With VPU, GPU, MLB, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U6AVM08AD DualLite With VPU, GPU, MLB, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U4AVM08AB DualLite With GPU, MLB, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U4AVM08AC DualLite With GPU, MLB, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U4AVM08AD DualLite With VPU, GPU, MLB, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U1AVM08AB DualLite With MLB, no GPU, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U1AVM08AC DualLite With MLB, no GPU, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U1AVM08AD DualLite With MLB, no GPU, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S6AVM08AB Solo With VPU, GPU, MLB, no EPDC 1x Arm Cortex-A9 32-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S6AVM08AC Solo With VPU, GPU, MLB, no EPDC 1x Arm Cortex-A9 32-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S6AVM08AD Solo With VPU, GPU, MLB, no EPDC 1x Arm Cortex-A9 32-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S4AVM08AB Solo With GPU, MLB, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S4AVM08AC Solo With GPU, MLB, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S4AVM08AD Solo With GPU, MLB, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S1AVM08AB Solo With MLB, no GPU, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S1AVM08AC Solo With MLB, no GPU, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 3 Introduction Table 1. Example Orderable Part Numbers (continued) Part Number i.MX6 CPU Solo/ DualLite MCIMX6S1AVM08AD Solo Options Temperature Grade Package 800 MHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U6AVM10AC DualLite With VPU, GPU, MLB, no EPDC 2x Arm Cortex-A9 64-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U6AVM10AD DualLite With VPU, GPU, MLB, no EPDC 2x Arm Cortex-A9 64-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U4AVM10AC DualLite With GPU, MLB, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U4AVM10AD DualLite With GPU, MLB, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U1AVM10AC DualLite With MLB, no GPU, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U1AVM10AD DualLite With MLB, no GPU, no VPU, no EPDC 2x Arm Cortex-A9 64-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S6AVM10AC Solo With VPU, GPU, MLB, no EPDC 1x Arm Cortex-A9 32-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S6AVM10AD Solo With VPU, GPU, MLB, no EPDC 1x Arm Cortex-A9 32-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S4AVM10AC Solo With GPU, MLB, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S4AVM10AD Solo With GPU, MLB, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S1AVM10AC Solo With MLB, no GPU, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S1AVM10AD Solo With MLB, no GPU, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR 1 GHz Automotive 21 mm x 21 mm, 0.8 mm pitch, MAPBGA 1 With MLB, no GPU, no VPU, no EPDC 1x Arm Cortex-A9 32-bit DDR Speed Grade1 For 800 MHz speed grade: If a 24 MHz clock is used (required for USB), then the maximum SoC speed is limited to 792 MHz. For 1 GHz speed grade: If a 24 MHz clock is used (required for USB), then the maximum SoC speed is limited to 996 MHz. Figure 1 describes the part number nomenclature to identify the characteristics of a specific part number (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The primary characteristic that differentiates which data sheet applies to a specific part is the temperature grade (junction) field. The following list describes the correct data sheet to use for a specific part: • The i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors data sheet (IMX6SDLAEC) covers parts listed with an “A (Automotive temp)” • The i.MX 6Solo/6DualLite Applications Processors for Consumer Products data sheet (IMX6SDLCEC) covers parts listed with a “D (Commercial temp)” or “E (Extended Commercial temp)” i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 4 NXP Semiconductors Introduction • The i.MX 6Solo/6DualLite Applications Processors for Industrial Products data sheet (IMX6SDLIEC) covers parts listed with “C (Industrial temp)” For more information go to nxp.com/imx6series or contact a NXP representative for details. MC IMX6 Qualification level MC Prototype Samples PC X @ + VV $$ % A Silicon revision1 A Rev 1.1 B C Mass Production MC Rev 1.2 (Maskset ID: 2N81E) Rev 1.3 (Maskset ID: 3N81E) Special SC Rev 1.4 (Maskset ID: 4N81E) D Fusing % Part # series X i.MX 6DualLite 2x ARM Cortex-A9, 64-bit DDR U i.MX 6Solo 1x ARM Cortex-A9, 32-bit DDR S Default settings A HDCP enabled C Frequency $$ 800 MHz Part differentiator @ Consumer VPU GPU EPDC MLB 8 Industrial VPU GPU – – 7 Automotive VPU GPU – MLB 6 Commercial: 0 to + 95°C D E Temperature Tj + Consumer VPU GPU – MLB 5 Extended commercial: -20 to + 105°C Automotive – GPU – MLB 4 Industrial: -40 to +105°C C Automotive – – – MLB 1 Automotive: -40 to + 125°C A 2 08 1 GHz 3 10 Package type RoHS MAPBGA 21 x 21 0.8mm VM 1. See the nxp.com\imx6series Web page for latest information on the available silicon revision. 2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz. 3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz. Figure 1. Part Number Nomenclature—i.MX 6Solo and 6DualLite Figure 2. Example Part Marking 1.2 Features The i.MX 6Solo/6DualLite processors are based on Arm Cortex-A9 MPCore Platform, which has the following features: • The i.MX 6Solo supports single Arm Cortex-A9 MPCore (with TrustZone) • The i.MX 6DualLite supports dual Arm Cortex-A9 MPCore (with TrustZone) • The core configuration is symmetric, where each core includes: i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 5 Introduction — — — — 32 KByte L1 Instruction Cache 32 KByte L1 Data Cache Private Timer and Watchdog Cortex-A9 NEON MPE (Media Processing Engine) Co-processor The Arm Cortex-A9 MPCore complex includes: • General Interrupt Controller (GIC) with 128 interrupt support • Global Timer • Snoop Control Unit (SCU) • 512 KB unified I/D L2 cache: — Used by one core in i.MX 6Solo — Shared by two cores in i.MX 6DualLite • Two Master AXI bus interfaces output of L2 cache • Frequency of the core (including NEON and L1 cache), as per Table 8. • NEON MPE coprocessor — SIMD Media Processing Architecture — NEON register file with 32x64-bit general-purpose registers — NEON Integer execute pipeline (ALU, Shift, MAC) — NEON dual, single-precision floating point execute pipeline (FADD, FMUL) — NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components: — Boot ROM, including HAB (96 KB) — Internal multimedia / shared, fast access RAM (OCRAM, 128 KB) — Secure/non-secure RAM (16 KB) • External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume, cost effective handheld DRAM, NOR, and NAND Flash memory standards. — 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and DDR3L-800 in i.MX 6Solo; 16/32/64-bit LP-DDR2-800, 16/32/64-bit DDR3-800 and DDR3L-800, supporting DDR interleaving mode for 2x32 LPDDR2-800 in i.MX 6DualLite — 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit. — 16/32-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces. — 16/32-bit PSRAM, Cellular RAM Each i.MX 6Solo/6DualLite processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): • Displays—Total of four interfaces available. Total raw pixel rate of all interfaces is up to 450 Mpixels/sec, 24 bpp. Up to two interfaces may be active in parallel. — One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz) i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 6 NXP Semiconductors Introduction • • • • • — LVDS serial ports—One port up to 165 Mpixels/sec or two ports up to 85 MP/sec (for example, WUXGA at 60 Hz) each — HDMI 1.4 port — MIPI/DSI, two lanes at 1 Gbps Camera sensors: — Two parallel Camera ports (up to 20 bit and up to 240 MHz peak) — MIPI CSI-2 Serial port, supporting from 80 Mbps to 1 Gbps speed per data lane. The CSI-2 Receiver core can manage one clock lane and up to two data lanes. Each i.MX 6Solo/6DualLite processor has two lanes. Expansion cards: — Four MMC/SD/SDIO card ports all supporting: – 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max) – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) USB: — One high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed Phy – Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) Phy Expansion PCI Express port (PCIe) v2.0 one lane — PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration. Miscellaneous IPs and interfaces: — SSI block is capable of supporting audio sample frequencies up to 192 kHz stereo inputs and outputs with I2S mode — ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with 7.1 multi channel outputs — Five UARTs, up to 5.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is due to the SoC IOMUX limitation, since all UART IPs are identical. — Four eCSPI (Enhanced CSPI) — Four I2C, supporting 400 kbps — Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps — Four Pulse Width Modulators (PWM) 1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Solo/6DualLite errata document (IMX6SDLCE). i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 7 Introduction — — — — — — — — System JTAG Controller (SJC) GPIO with interrupt capabilities 8x8 Key Pad Port (KPP) Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx Two Controller Area Network (FlexCAN), 1 Mbps each Two Watchdog timers (WDOG) Audio MUX (AUDMUX) MLB (MediaLB) provides interface to MOST Networks (MOST25, MOST50, MOST150) with the option of DTCP cipher accelerator The i.MX 6Solo/6DualLite processors integrate advanced power management unit and controllers: • Provide PMU, including LDO supplies, for on-chip resources • Use Temperature Sensor for monitoring the die temperature • Support DVFS techniques for low power modes • Use SW State Retention and Power Gating for Arm and MPE • Support various levels of system power modes • Use flexible clock gating control scheme The i.MX 6Solo/6DualLite processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The i.MX 6Solo/6DualLite processors incorporate the following hardware accelerators: • VPU—Video Processing Unit • IPUv3H—Image Processing Unit version 3H • GPU3Dv5—3D Graphics Processing Unit (OpenGL ES 2.0) version 5 • GPU2Dv2—2D Graphics Processing Unit (BitBlt) • ASRC—Asynchronous Sample Rate Converter Security functions are enabled and accelerated by the following hardware: • Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.) • SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features. • CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash engines, 16 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified). • SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy. • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 8 NXP Semiconductors Introduction NOTE The actual feature set depends on the part numbers as described in Table 1, "Example Orderable Part Numbers," on page 3. Functions, such as video hardware acceleration, and 2D and 3D hardware graphics acceleration may not be enabled for specific part numbers. 1.3 Updated Signal Naming Convention The signal names of the i.MX6 series of products have been standardized to better align the signal names within the family and across the documentation. Some of the benefits of these changes are as follows: • The names are unique within the scope of an SoC and within the series of products • Searches will return all occurrences of the named signal • The names are consistent between i.MX 6 series products implementing the same modules • The module instance is incorporated into the signal name This change applies only to signal names. The original ball names have been preserved to prevent the need to change schematics, BSDL models, IBIS models, etc. Throughout this document, the updated signal names are used except where referenced as a ball name (such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to map the signal names used in older documentation to the new standardized naming conventions. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 9 Architectural Overview 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 6Solo/6DualLite processor system. 2.1 Block Diagram Figure 3 shows the functional modules in the i.MX 6Solo/6DualLite processor system. Digital Audio LPDDR2/DDR3 400 MHz (DDR800) NOR Flash PSRAM External Memory I/F GPMI MMDC Battery Ctrl Device 2x Camera Parallel/MIPI Application Processor Domain (AP) EIM Internal RAM 1 (144 KB) Smart DMA (SDMA) TPIU SPBA CTIs SJC Shared Peripherals SSI (3) eCSPI (4) 5xFast-UART ESAI SPDIF Rx/Tx ASRC Security CAAM (16KB Ram) SNVS (SRTC) Crystals & Clock sources 2 Video Proc. Unit (VPU + Cache) 3D Graphics Proc. Unit (GPU3D) 2D Graphics Proc. Unit (GPU2D) MMC/SD eMMC/eSD uSDHC (4) MMC/SD SDXC I2C(4) PWM (4) Modem IC IOMUXC KPP GPIO Keypad CAN(2) 1-Gbps ENET MLB 150 DTCP HSI/MIPI GPT EPIT (2) Temp Monitor OTG PHY1 Host PHY2 WLAN AP Peripherals OCTP_CTRL WDOG (2) Bluetooth DSI/MIPI AUDMUX Timers/Control PLL (8) CCM GPC SRC XTALOSC OSC32K 1 512K L2 cache SCU, Timer PTM’s CTI’s Fuse Box Clock and Reset HDMI MIPI Display 1x/2x A9-Core L1 I/D Cache Timer, WDOG CSU Power Management Unit (LDOs) LDB HDMI 1.4 Display Arm Cortex-A9 MPCore Platform Debug DAP PCIe Bus Audio, Power Mngmnt. CSI2/MIPI 1 / 2 LCD Displays Image Processing Subsystem IPUv3H Boot ROM (96KB) 2xCAN i/f GPS 1 / 2 LVDS (WUXGA+) AXI and AHB Switch Fabric Raw / ONFI 2.2 NAND Flash JTAG (IEEE1149.6) 2xHSIC PHY USB OTG (dev/host) Ethernet 10/100/1000 Mbps USB OTG + 3 HS Ports MLB/Most Network 144 KB RAM including 16 KB RAM inside the CAAM. For i.MX 6Solo, there is only one A9-core platform in the chip; for i.MX 6DualLite, there are two A9-core platforms. Figure 3. i.MX 6Solo/6DualLite System Block Diagram NOTE The numbers in brackets indicate number of module instances. For example, PWM (4) indicates four separate PWM peripherals. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 10 NXP Semiconductors Modules List 3 Modules List The i.MX 6Solo/6DualLite processors contain a variety of digital and analog modules. Table 2 describes these modules in alphabetical order. Table 2. i.MX 6Solo/6DualLite Modules List Block Mnemonic Block Name Subsystem Brief Description APBH-DMA NAND Flash and BCH ECC DMA controller System Control Peripherals Arm Arm Platform Arm The Arm Core Platform includes 1x (Solo) Cortex-A9 core for i.MX 6Solo and 2x (Dual) Cortex-A9 cores for i.MX 6DualLite. It also includes associated sub-blocks, such as the Level 2 Cache Controller, SCU (Snoop Control Unit), GIC (General Interrupt Controller), private timers, watchdog, and CoreSight debug modules. ASRC Asynchronous Sample Rate Converter Multimedia Peripherals The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample rate conversion of up to 10 channels of about -120dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three sampling rate pairs. AUDMUX Digital Audio Mux Multimedia Peripherals The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The AUDMUX has seven ports with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports. BCH40 Binary-BCH ECC Processor System Control Peripherals CAAM Cryptographic accelerator and assurance module Security CAAM is a cryptographic accelerator and assurance module. CAAM implements several encryption and hashing functions, a run-time integrity checker, and a Pseudo Random Number Generator (PRNG). The pseudo random number generator is certified by Cryptographic Algorithm Validation Program (CAVP) of National Institute of Standards and Technology (NIST). Its DRBG validation number is 94 and its SHS validation number is 1455. CAAM also implements a Secure Memory mechanism. In i.MX 6Solo/6DualLite processors, the security memory provided is 16 KB. CCM GPC SRC Clock Control Module, General Power Controller, System Reset Controller Clocks, Resets, and Power Control These modules are responsible for clock and reset distribution in the system, and also for the system power management. CSI MIPI CSI-2 i/f Multimedia Peripherals DMA controller used for GPMI2 operation The BCH40 module provides up to 40-bit ECC for NAND Flash controller (GPMI) The CSI IP provides MIPI CSI-2 standard camera interface port. The CSI-2 interface supports from 80 Mbps to 1 Gbps speed per data lane. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 11 Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description CSU Central Security Unit Security CTI-0 CTI-1 CTI-2 CTI-3 CTI-4 Cross Trigger Interfaces Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from masters attached to CTIs. The CTI module is internal to the Cortex-A9 Core Platform. CTM Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs. The CTM module is internal to the Cortex-A9 Core Platform. DAP Debug Access Port System Control Peripherals The DAP provides real-time access for the debugger without halting the core to: • System memory and peripheral registers • All debug configuration registers The DAP also provides debugger access to JTAG scan chains. The DAP module is internal to the Cortex-A9 Core Platform. DCIC-0 DCIC-1 Display Content Integrity Checker Automotive IP The DCIC provides integrity check on portion(s) of the display. Each i.MX 6Solo/6DualLite processor has two such modules. DSI MIPI DSI i/f Multimedia Peripherals The MIPI DSI IP provides DSI standard display port interface. The DSI interface support 80 Mbps to 1 Gbps speed per data lane. DTCP DTCP Multimedia Peripherals Provides encryption function according to Digital Transmission Content Protection standard for traffic over MLB150. eCSPI1-4 Configurable SPI Connectivity Peripherals Full-duplex enhanced Synchronous Serial Interface. It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals. ENET Ethernet Controller Connectivity Peripherals The Ethernet Media Access Controller (MAC) is designed to support 10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The module has dedicated hardware to support the IEEE 1588 standard. See the ENET chapter of the reference manual for details. The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX 6Solo/6DualLite platform. Note: The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Solo/6DualLite errata document (IMX6SDLCE). i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 12 NXP Semiconductors Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description EPIT-1 EPIT-2 Enhanced Periodic Interrupt Timer Timer Peripherals Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the fly. ESAI Enhanced Serial Audio Interface Connectivity Peripherals The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. All serial transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The network mode is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available. The ESAI has 12 pins for data and clocking connection to external devices. FlexCAN-1 FlexCAN-2 Flexible Controller Area Network Connectivity Peripherals The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the Electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. 512x8 Fuse Box Electrical Fuse Array Security Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security Keys, and many other system parameters. The i.MX 6Solo/6DualLite processors consist of 512x8-bit fuse fox accessible through OCOTP_CTRL interface. GPIO-1 GPIO-2 GPIO-3 GPIO-4 GPIO-5 GPIO-6 GPIO-7 General Purpose I/O Modules System Control Peripherals Used for general purpose input/output to external ICs. Each GPIO module supports 32 bits of I/O. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 13 Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description GPMI General Purpose Media Interface Connectivity Peripherals The GPMI module supports up to 8x NAND devices. 40-bit ECC encryption/decryption for NAND Flash controller (GPMI2). The GPMI supports separate DMA channels per NAND device. GPT General Purpose Timer Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget” mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. GPU3Dv5 Graphics Processing Unit, ver.5 Multimedia Peripherals The GPU3Dv5 provides hardware acceleration for 3D graphics algorithms with sufficient processor power to run desktop quality interactive graphics applications on displays up to HD1080 resolution. The GPU3D provides OpenGL ES 2.0, including extensions, OpenGL ES 1.1, and OpenVG 1.1 GPU2Dv2 Graphics Processing Unit-2D, ver 2 Multimedia Peripherals The GPU2Dv2 provides hardware acceleration for 2D graphics algorithms, such as Bit BLT, stretch BLT, and many other 2D functions. HDMI Tx HDMI Tx i/f Multimedia Peripherals The HDMI module provides HDMI standard i/f port to an HDMI 1.4 compliant display. HSI MIPI HSI i/f Connectivity Peripherals The MIPI HSI provides a standard MIPI interface to the applications processor. I2C-1 I2C-2 I2C-3 I2C-4 I2C Interface Connectivity Peripherals I2C provide serial interface for external devices. Data rates of up to 400 kbps are supported. IOMUXC IOMUX Control System Control Peripherals This module enables flexible IO multiplexing. Each IO pad has default and several alternate functions. The alternate functions are software configurable. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 14 NXP Semiconductors Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description IPUv3H Image Processing Unit, ver.3H Multimedia Peripherals IPUv3H enables connectivity to displays and video sources, relevant processing and synchronization and control capabilities, allowing autonomous operation. The IPUv3H supports concurrent output to two display ports and concurrent input from two camera ports, through the following interfaces: • Parallel Interfaces for both display and camera • Single/dual channel LVDS display interface • HDMI transmitter • MIPI/DSI transmitter • MIPI/CSI-2 receiver The processing includes: • Image conversions: resizing, rotation, inversion, and color space conversion • A high-quality de-interlacing filter • Video/graphics combining • Image enhancement: color adjustment and gamut mapping, gamma correction, and contrast enhancement • Support for display backlight reduction KPP Key Pad Port Connectivity Peripherals KPP Supports 8x8 external key pad matrix. KPP features are: • Open drain design • Glitch suppression circuit design • Multiple keys detection • Standby key press detection LDB LVDS Display Bridge Connectivity Peripherals LVDS Display Bridge is used to connect the IPU (Image Processing Unit) to External LVDS Display Interface. LDB supports two channels; each channel has following signals: • One clock pair • Four data pairs Each signal pair contains LVDS special differential pad (PadP, PadM). MLB150 MediaLB Connectivity / Multimedia Peripherals The MLB interface module provides a link to a MOST® data network, using the standardized MediaLB protocol (up to 6144 fs). The module is backward compatible to MLB-50. MMDC Multi-Mode DDR Controller Connectivity Peripherals DDR Controller has the following features: • Supports 16/32-bit DDR3-800 (LV) or LPDDR2-800 in i.MX 6Solo • Supports 16/32/64-bit DDR3-800 (LV) or LPDDR2-800 in i.MX 6DualLite • Supports 2x32 LPDDR2-800 in i.MX 6DualLite • Supports up to 4 GByte DDR memory space i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 15 Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description OCOTP_CTRL OTP Controller Security The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals, requiring permanent non-volatility. OCRAM On-Chip Memory controller Data Path The On-Chip Memory controller (OCRAM) module is designed as an interface between system’s AXI bus and internal (on-chip) SRAM memory module. In i.MX 6Solo/6DualLite processors, the OCRAM is used for controlling the 128 KB multimedia RAM through a 64-bit AXI bus. OSC32KHz OSC32KHz Clocking PCIe PCI Express 2.0 Connectivity Peripherals PMU Power-Management functions Data Path PWM-1 PWM-2 PWM-3 PWM-4 Pulse Width Modulation Connectivity Peripherals RAM 128 KB Internal RAM Internal Memory Internal RAM, which is accessed through OCRAM memory controller. RAM 16 KB Secure/non-secure RAM Secured Internal Memory Secure/non-secure Internal RAM, interfaced through the CAAM. ROM 96KB Boot ROM Internal Memory Supports secure and regular Boot Modes. Includes read protection on 4K region for content protection. ROMCP ROM Controller with Patch Data Path Generates 32.768 KHz clock from external crystal. The PCIe IP provides PCI Express Gen 2.0 functionality. Integrated power management unit. Used to provide power to various SoC domains. The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound. ROM Controller with ROM Patch support i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 16 NXP Semiconductors Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description SDMA Smart Direct Memory Access System Control Peripherals The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off-loading the various cores in dynamic data routing. It has the following features: • Powered by a 16-bit Instruction-Set micro-RISC engine • Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels • 48 events with total flexibility to trigger any combination of channels • Memory accesses including linear, FIFO, and 2D addressing • Shared peripherals between Arm and SDMA • Very fast Context-Switching with 2-level priority based preemptive multi-tasking • DMA units with auto-flush and prefetch capability • Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address) • DMA ports can handle unit-directional and bi-directional flows (copy mode) • Up to 8-word buffer for configurable burst transfers • Support of byte-swapping and CRC calculations • Library of Scripts and API is available SJC System JTAG Controller System Control Peripherals The SJC provides JTAG interface, which complies with JTAG TAP standards, to internal logic. The i.MX 6Solo/6DualLite processors use JTAG port for production, testing, and system debugging. In addition, the SJC provides BSR (Boundary Scan Register) standard support, which complies with IEEE1149.1 and IEEE1149.6 standards. The JTAG port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The i.MX 6Solo/6DualLite SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration. SNVS Secure Non-Volatile Storage Security Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. SPDIF Sony Philips Digital Interconnect Format Multimedia Peripherals A standard audio file transfer format, developed jointly by the Sony and Phillips corporations. Has Transmitter and Receiver functionality. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 17 Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description SSI-1 SSI-2 SSI-3 I2S/SSI/AC97 Interface Connectivity Peripherals The SSI is a full-duplex synchronous interface, which is used on the AP to provide connectivity with off-chip audio peripherals. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock / frame sync options. The SSI has two pairs of 8x24 FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream that reduces CPU overhead in use cases where two time slots are being used simultaneously. TEMPMON Temperature Monitor System Control Peripherals The Temperature sensor IP is used for detecting die temperature. The temperature read out does not reflect case or ambient temperature. It reflects the temperature in proximity of the sensor location on the die. Temperature distribution may not be uniformly distributed, therefore the read out value may not be the reflection of the temperature value of the entire die. TZASC Trust-Zone Address Space Controller Security The TZASC (TZC-380 by Arm) provides security address region control functions required for intended application. It is used on the path to the DRAM controller. UART-1 UART-2 UART-3 UART-4 UART-5 UART Interface Connectivity Peripherals Each of the UARTv2 modules support the following serial data transmit/receive protocols and configurations: • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) • Programmable baud rates up to 5 Mbps. • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud • IrDA 1.0 support (up to SIR speed of 115200 bps) • Option to operate as 8-pins full UART, DCE, or DTE USBOH3 USB 2.0 High Speed OTG and 3x HS Hosts Connectivity Peripherals USBOH3 contains: • One high-speed OTG module with integrated HS USB PHY • One high-speed Host module with integrated HS USB PHY • Two identical high-speed Host modules connected to HSIC USB ports. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 18 NXP Semiconductors Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description uSDHC-1 uSDHC-2 uSDHC-3 uSDHC-4 SD/MMC and SDXC Enhanced Multi-Media Card / Secure Digital Host Controller Connectivity Peripherals i.MX 6Solo/6DualLite specific SoC characteristics: All four MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. They are: • Conforms to the SD Host Controller Standard Specification version 3.0. • Fully compliant with MMC command/response sets and Physical Layer as defined in the Multimedia Card System Specification, v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC. • Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDHC cards up to 32 GB and SDXC cards up to 2 TB. • Fully compliant with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v3.0 All four ports support: • 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max) • 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) However, the SoC level integration and I/O muxing logic restrict the functionality to the following: • Instances #1 and #2 are primarily intended to serve as external slots or interfaces to on-board SDIO devices. These ports are equipped with “Card detection” and “Write Protection” pads and do not support hardware reset. • Instances #3 and #4 are primarily intended to serve interfaces to embedded MMC memory or interfaces to on-board SDIO devices. These ports do not have “Card detection” and “Write Protection” pads and do support hardware reset. • All ports can work with 1.8 V and 3.3 V cards. There are two completely independent I/O power domains for Ports #1 and #2 in four bit configuration (SD interface). Port #3 is placed in his own independent power domain and port #4 shares power domain with some other interfaces. VDOA VDOA Multimedia Peripherals Video Data Order Adapter (VDOA): used to re-order video data from the “tiled” order used by the VPU to the conventional raster-scan order needed by the IPU. VPU Video Processing Unit Multimedia Peripherals A high-performing video processing unit (VPU), which covers many SD-level and HD-level video decoders and SD-level encoders as a multi-standard video codec engine as well as several important video processing, such as rotation and mirroring. See the i.MX 6Solo/6DualLite Reference Manual (IMX6SDLRM) for complete list of VPU’s decoding/encoding capabilities. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 NXP Semiconductors 19 Modules List Table 2. i.MX 6Solo/6DualLite Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description WDOG-1 Watch Dog Timer Peripherals The Watch Dog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. WDOG-2 (TZ) Watch Dog (TrustZone) Timer Peripherals The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode. Such situation is undesirable as it can compromise the system’s security. Once the TZ WDOG module is activated, it must be serviced by TZ software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode. If it is still not served, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW. WEIM NOR-Flash /PSRAM interface Connectivity Peripherals The WEIM NOR-FLASH / PSRAM provides: • Support 16-bit (in muxed IO mode only) PSRAM memories (sync and async operating modes), at slow frequency • Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow frequency • Multiple chip selects XTALOSC Crystal Oscillator I/F Clocks, Resets, and Power Control The XTALOSC module enables connectivity to external crystal oscillator device. In a typical application use-case, it is used for 24 MHz oscillator to provide USB required frequency. i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 9, 11/2018 20 NXP Semiconductors Modules List 3.1 Special Signal Considerations Table 3 lists special signal considerations for the i.MX 6Solo/6DualLite processors. The signal names are listed in alphabetical order. The package contact assignments can be found in Section 6, “Package Information and Contact Assignments.” Signal descriptions are provided in the i.MX 6Solo/6DualLite Reference Manual (IMX6SDLRM). Table 3. Special Signal Considerations Signal Name Remarks CLK1_P/CLK1_N CLK2_P/CLK2_N Two general purpose differential high speed clock Input/outputs are provided. Any or both of them could be used: • To feed external reference clock to the PLLs and further to the modules inside SoC, for example as alternate reference clock for PCIe, Video/Audio interfaces, etc. • To output internal SoC clock to be used outside the SoC as either reference clock or as a functional clock for peripherals, for example it could be used as an output of the PCIe master clock (root complex use) See the i.MX 6Solo/6DualLite reference manual for details on the respective clock trees. The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard, the maximum frequency range supported is 0...600 MHz. Alternatively one may use single ended signal to drive CLKx_P input. In this case corresponding CLKx_N input should be tied to the constant voltage level equal 1/2 of the input signal swing. Termination should be provided in case of high frequency signals. See LVDS pad electrical specification for further details. After initialization, the CLKx inputs/outputs could be disabled (if not used). If unused any or both of the CLKx_N/P pairs may remain unconnected. XTALOSC_RTC_XTALI/ RTC_XTALO If the user wishes to configure XTALOSC_RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz crystal, (≤100 kΩ ESR, 10 pF load) should be connected between XTALOSC_RTC_XTALI and RTC_XTALO. Remember that the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but relatively weak. Care must be taken to limit parasitic leakage from XTALOSC_RTC_XTALI and RTC_XTALO to either power or ground (>100 MΩ). This will debias the amplifier and cause a reduction of startup margin. Typically XTALOSC_RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V. If it is desired to feed an external low frequency clock into XTALOSC_RTC_XTALI the RTC_XTALO pin must remain unconnected or driven with a complimentary signal. The logic level of this forcing clock must not exceed VDD_SNVS_CAP level and the frequency must be