NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6SXAEC
Rev. 4, 11/2018
MCIMX6XxAxxxxxB
MCIMX6XxAxxxxxC
i.MX 6SoloX Automotive
and Infotainment
Applications Processors
Package Information
Plastic Package
BGA 19 x 19 mm, 0.8 mm pitch
BGA 17 x 17 mm, 0.8 mm pitch
BGA 14 x 14 mm, 0.65 mm pitch
Ordering Information
See Table 1 on page 3
1
Introduction
The i.MX 6SoloX automotive and infotainment
processors represent NXP Semiconductor’s latest
achievement in integrated multimedia-focused products
offering high-performance processing with a high degree
of functional integration. These processors are designed
considering the needs of the growing automotive
infotainment, telematics, HMI, and display-based cluster
markets.
The i.MX 6SoloX processor features NXP’s advanced
implementation of the single Arm® Cortex®-A9 core,
which operates at speeds of up to 800 MHz, in addition
to the Arm Cortex-M4 core, which operates at speeds of
up to 227 MHz. This type of heterogeneous multicore
architecture provides greater levels of system
integration, smart low-power system awareness, and fast
real-time responsiveness. The i.MX 6SoloX includes a
GPU processor capable of supporting 2D and 3D
operations, a wide range of display and connectivity
options, and integrated power management. Each
processor provides a 32-bit
DDR3/DDR3L/LPDDR2-800 memory interface and a
number of other interfaces for connecting peripherals,
1
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 18
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Power Supplies Requirements and Restrictions . . 33
4.3 Integrated LDO Voltage Regulator Parameters . . 34
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 36
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 43
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 46
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 49
4.10 Multi-mode DDR Controller (MMDC). . . . . . . . . . . 61
4.11 General-Purpose Media Interface (GPMI) Timing. 62
4.12 External Peripheral Interface Parameters . . . . . . . 70
4.13 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 119
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 119
5.2 Boot Device Interface Allocation . . . . . . . . . . . . . 121
Package Information and Contact Assignments . . . . . . 129
6.1 i.MX 6SoloX Signal Availability by Package . . . . 129
6.2 Signals with Different States During Reset and After
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3 19x19 mm Package Information . . . . . . . . . . . . . 132
6.4 17x17 mm Package Information . . . . . . . . . . . . . 151
6.5 14x14 mm Package Information . . . . . . . . . . . . . 186
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
NXP Reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products
Introduction
such as WLAN, Bluetooth™, GPS, displays, and camera sensors.
The i.MX 6SoloX processors are specifically useful for applications such as:
• Entry-level infotainment
• Telematics
The features of the i.MX 6SoloX processors include:
• Dual-core architecture with one Arm Cortex-A9 processor plus one Arm Cortex-M4 processor—
Dual-core architecture enables the device to run an open operating system like Linux on the
Cortex-A9 core and an RTOS like MQX™ or FreeRTOS™ on the Cortex-M4 core. The Cortex-M4
core is standard on all i.MX 6SoloX processors.
• Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processors support
many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR
Flash, NAND Flash (MLC and SLC), OneNAND, Quad SPI, and managed NAND, including
eMMC up to rev 4.4/4.41/4.5.
• Smart speed technology—Power management implemented throughout the IC that enables
multimedia features and peripherals to consume minimum power in both active and various low
power modes.
• Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, a programmable
smart DMA (SDMA) controller, and an asynchronous sample rate converter.
• 2x Gigabit Ethernet with AVB—2x 10/100/1000 Mbps Gigabit Ethernet controllers with support
for Audio Video Bridging (AVB) for reliable, high-quality, low-latency multimedia streaming.
• Human-machine interface—Each processor provides a single integrated graphics processing unit
that supports an OpenGL ES 2.0 and OpenVG 1.1 3D and 2D graphics accelerator. In addition,
each processor provides up to two separate display interfaces (parallel display and LVDS display)
and a CMOS sensor interface (parallel).
• Interface flexibility—Each processor supports connections to a variety of interfaces: High-speed
USB on-the-go with PHY, high-speed USB host with PHY, High-Speed Inter-Chip USB, multiple
expansion card ports (high-speed MMC/SDIO host and other), 2 Gigabit Ethernet controllers with
support for Ethernet AVB, PCIe-II, two 12-bit ADC modules with 4 dedicated single-ended inputs,
two CAN ports, ESAI audio interface, and a variety of other popular interfaces (such as UART, I2C,
and I2S serial audio).
• Automotive environment support—Each processor includes interfaces, such as two CAN ports, an
MLB25/50 port, an ESAI audio interface, and an asynchronous sample rate converter for
multichannel/multisource audio.
• Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6SoloX Security
Reference Manual (IMX6XSRM).
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
2
NXP Semiconductors
Introduction
•
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
For a comprehensive list of the i.MX 6SoloX features, see Section 1.2, “Features”.
1.1
Ordering Information
Table 1 provides examples of orderable sample part numbers covered by this data sheet.
Table 1. Ordering Information
Part Number
Options
Mask
Set
Cortex- CortexJunction
Qualification
A9
M4
Temperature
Tier
Speed1 Speed
Range
Package
MCIMX6X1AVO08AB Features not 2N19K
supported:
or
- 2D&3D GPU 3N19K
- PCIe
- LVDS
800
MHz
227
MHz
Automotive
-40 to
+125°C
17x17NP (NP=No PCIe)
Package code “VO”
17mm x 17mm
0.8pitch Map BGA
MCIMX6X1AVO08AC Features not 4N19K
supported:
- 2D&3D GPU
- PCIe
- LVDS
800
MHz
227
MHz
Automotive
-40 to
+125°C
17x17NP (NP=No PCIe)
Package code “VO”
17mm x 17mm
0.8pitch Map BGA
MCIMX6X1AVK08AB Features not 2N19K
or
supported:
- 2D&3D GPU 3N19K
- PCIe
- LVDS
800
MHz
227
MHz
Automotive
-40 to
+125°C
14x14NP (NP=No PCIe)
Package code “VK”
14mm x 14mm
0.65pitch Map BGA
MCIMX6X1AVK08AC Features not 4N19K
supported:
- 2D&3D GPU
- PCIe
- LVDS
800
MHz
227
MHz
Automotive
-40 to
+125°C
14x14NP (NP=No PCIe)
Package code “VK”
14mm x 14mm
0.65pitch Map BGA
MCIMX6X2AVN08AB Features not 2N19K
supported:
or
- 2D&3D GPU 3N19K
- LVDS
800
MHz
227
MHz
Automotive
-40 to
+125°C
17x17WP (WP=With PCIe)
Package code “VN”
17mm x 17mm
0.8pitch Map BGA
MCIMX6X2AVN08AC Features not 4N19K
supported:
- 2D&3D GPU
- LVDS
800
MHz
227
MHz
Automotive
-40 to
+125°C
17x17WP (WP=With PCIe)
Package code “VN”
17mm x 17mm
0.8pitch Map BGA
MCIMX6X4AVM08AB Full-featured
device
2N19K
or
3N19K
800
MHz
227
MHz
Automotive
-40 to
+125°C
19x19
Package code “VM”
19mm x 19mm
0.8pitch Map BGA
MCIMX6X4AVM08AC Full-featured
device
4N19K
800
MHz
227
MHz
Automotive
-40 to
+125°C
19x19
Package code “VM”
19mm x 19mm
0.8pitch Map BGA
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
NXP Semiconductors
3
Introduction
1
If a 24 MHz input clock is used (required for USB), the maximum Cortex-A9 speed for 1 GHz speed grade is limited to 996 MHz
and the maximum Cortex-A9 speed for 800 MHz speed grade is limited to 792 MHz.
Figure 1 describes the part number nomenclature so that the users can identify the characteristics of the
specific part number they have (for example, cores, frequency, temperature grade, fuse options, and silicon
revision). The primary characteristic which describes which data sheet applies to a specific part is the
temperature grade (junction) field.
• The i.MX 6SoloX Automotive and Infotainment Applications Processors data sheet
(IMX6SXAEC) covers parts listed with an “A (Automotive temp)”
• The i.MX 6SoloX Applications Processors for Consumer Products data sheet (IMX6SXCEC)
covers parts listed with a “D (Commercial temp)” or “E (Extended Commercial temp)”
• The i.MX 6SoloX Applications Processors for Industrial Products data sheet (IMX6SXIEC) covers
parts listed with “C (Industrial temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there will be any questions, visit see the web page
nxp.com/imx6series or contact a NXP representative for details.
MC
IMX6
X
@
+
VV
$$
%
A
MC
Silicon Revision1
A
Prototype Samples
PC
Rev 1.2 Production (Maskset 2N19K)
Rev 1.3 Production (Maskset 3N19K)
B
Mass Production
MC
Rev 1.4 Production (Maskset 4N19K)
C
Special
SC
i.MX 6 Family
X
i.MX 6SoloX
X
Qualification Level
Part Differentiator
@
Package
Automotive
GPU
PCIe
LVDS
ADC
ARM Cortex-A9 Frequency
$$
800 MHz
08
1 GHz
10
Y
2x 4ch
Y
Y
Y
Y
2x 4ch
-
Package Type
14x14NP: MAPBGA 14x14 0.65mm
NP = No PCIe
VK
17x17NP: MAPBGA 17x17 0.8mm
NP = No PCIe
VO
17x17WP: MAPBGA 17x17 0.8mm
WP = With PCIe
VN
MAPBGA 19x19 0.8mm
VM
4
Y
Y
-
1x 2ch
-
Ext. Commercial/ Industrial
VO
Y
-
-
2x 4ch
-
Ext. Commercial/ Industrial
VK
Y
-
-
2x 4ch
-
-
Y
-
1x 2ch
Y
-
Y
-
1x 2ch
-
-
-
-
2x 4ch
Y
Ext. Commercial/ Industrial
-
-
-
2x 4ch
-
Automotive
-
-
-
2x 4ch
Y
-
-
-
2x 4ch
-
3
2
VN
Automotive
A
Y
VN
Ext. Commercial/ Industrial
Security Enabled
Y
Ext. Commercial/ Industrial
Automotive
%
MLB
VM
Ext. Commercial/ Industrial
Fusing
ROHS
VO
1
VK
Ext. Commercial/ Industrial
1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.
Junction Temperature (Tj)
+
Extended Commercial: -20 to + 105C
E
Industrial: -40 to +105C
C
Auto: -40 to + 125C
A
Figure 1. Part Number Nomenclature—i.MX 6SoloX
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
4
NXP Semiconductors
Introduction
1.2
Features
The i.MX 6SoloX processors are based on the Arm Cortex-A9 MPCore™ platform, which has the
following features:
• Supports single Arm Cortex-A9 MPCore processor (with TrustZone)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) coprocessor
The Arm Cortex-A9 MPCore complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 256 KB unified I/D L2 cache:
• Two Master AXI bus interfaces output of L2 cache
• Frequency of the core (including NEON coprocessor and L1 cache), as per Table 10, “Operating
Ranges,” on page 26.
• NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
— 32 double-precision VFPv3 floating point registers
The Arm Cortex-M4 platform:
• Cortex-M4 CPU core
• MPU (Memory Protection Unit)
• FPU (Floating Point Unit)
• 16 KByte Instruction Cache
• 16 KByte Data Cache
• 64 KByte TCM (Tightly-Coupled Memory)
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
— Internal RAM for state retention or general use (OCRAM_S, 16KB)
— Secure/non-secure RAM (32 KB)
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
NXP Semiconductors
5
Introduction
•
External memory interfaces: The i.MX 6SoloX processors support latest, high volume, cost
effective handheld DRAM, NOR, and NAND Flash memory standards.
— 16/32-bit LPDDR2-800, 16/32-bit DDR3-800 and DDR3L-800
— 16-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND and others. BCH ECC up to 62 bits. 16-bit
boot is supported from OneNAND. 8-bit boot is supported from other NAND types.
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
Each i.MX 6SoloX processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Displays—Total three interfaces available.
— Two parallel 24-bit display ports, each up to 1080P at 60 Hz
— LVDS serial port—One port up to 85 MP/sec (for example, WXGA at 60 Hz)
• Camera sensors:
— Two parallel camera ports (up to 24 bit and up to 133 MHz peak)
• Expansion cards:
— Four MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 200 MHz in HS200
mode (200 MB/s max)
• USB:
— Two high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy
— One HS-IC USB (High-Speed Inter-Chip USB) host
• Expansion PCI Express port (PCIe) v2.0 one lane
— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint
operations. Uses x1 PHY configuration.
• Miscellaneous IPs and interfaces:
— Three SSIs and two SAIs supporting up to five I2S or AC97 ports
— Enhanced Serial Audio Interface (ESAI)
— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx
— Audio MUX (AUDMUX)
— Medium Quality Sound (MQS) module provides an opportunity for BOM cost reduction if
high-quality sound is not required
— Six UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– One of the six UARTs (UART1) supports 8-wire while others support 4-wire. This is due to
the SoC IOMUX limitation, since all UART IPs are identical.
— Five eCSPI (Enhanced CSPI)
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
6
NXP Semiconductors
Introduction
— Four I2C
— Two Gigabit Ethernet Controllers (designed to be compatible with IEEE AVB standards and
IEEE Std 1588®), 10/100/1000 Mbps
— Eight Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— Two Quad SPIs
— Two Flexible Controller Area Network (FlexCAN), 1 Mbps each
— Three Watchdog timers (WDOG)
— Up to two 4-channel, 12-bit Analog to Digital Converters (ADC), VM, VO, VK packages
— One 2-channel, 12-bit Analog to Digital Converter (ADC), VN package
— MLB (MediaLB) provides interface to MOST Networks (MOST25, MOST50)
The i.MX 6SoloX processors integrate advanced power management unit and controllers:
• Provide PMU, including LDO supplies, for on-chip resources
• Use Temperature Sensor for monitoring the die temperature
• Support DVFS techniques for low power modes
• Use software state retention and power gating for Arm Cortex-A9 CPU core, the Arm Cortex-M4
CPU core, and the Arm NEON MPE coprocessor.
• Support various levels of system power modes
• Use flexible clock gating control scheme
The i.MX 6SoloX processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption, while having the CPU core relatively free for performing other tasks.
The i.MX 6SoloX processors incorporate the following hardware accelerators:
• GPU—2D (BitBlt) and 3D (OpenGL ES) Graphics Processing Unit
• PXP—PiXel Processing Pipeline for imagine resize, rotation, overlay and CSC. Off loading key
pixel processing operations are required to support the LCD display applications.
• ASRC—Asynchronous Sample Rate Converter
Security functions are enabled and accelerated by the following hardware:
• Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
• CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash
engines, 32 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified).
• SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock
• CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
NXP Semiconductors
7
Introduction
•
A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions, such as display and camera interfaces, connectivity interfaces,
video hardware acceleration, and 2D and 3D hardware graphics acceleration
may not be enabled for specific part numbers.
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
8
NXP Semiconductors
Architectural Overview
2
Architectural Overview
The following subsections provide an architectural overview of the i.MX 6SoloX processor system.
2.1
Block Diagram
Figure 2 shows the functional modules in the i.MX 6SoloX processor system.
LP-DDR2
/ DDR3
Battery Ctrl
Device
ARM Cortex A9
MPCore Platform
External Memory
NAND FLASH
MMDC
Cortex-A9 Core
EIM
GPMI & BCH
NOR FLASH
(Parallel)
Sensors
QSPI (2)
I$ 32KB
D$ 32KB
NEON
PTM
JTAG
(IEEE1149.6)
Debug
Clock & Reset
DAP
PLL (7)
TPIU
CCM
CTIs
GPC
SJC
SRC
SCU & Timer
L2 Cache 256KB
Internal Memory
OCRAM 144KB
NOR FLASH
(Quad SPI)
Temper
Detection
CSU
Fuse Box
SNVS
(SRTC)
AXI and AHB Switch Fabric
CAAM
(32KB RAM)
MMC/SD
eMMC/eSD
MMC/SD
SDXC
XTAL OSC
Timer/Control
32K OSC
WDOG (3)
ROM 96KB
Security
Crystal &
Clock Source
ARM CortexM4
Platform
Cortex-M4 Core
I$ 16KB
D$ 16KB
MPU
FPU
TCM 64KB
RDC
DisplayInterface
SEMAPHORE
Graphics
LVDS (LDB)
3D&2D Graphics
Processing Unit
(GPU)
Camera Interface
uSDHC (4)
EPIT (2)
Temp Monitor
Smart DMA
SDMA
Touch Panel
Control
AUDMUX
UART(5)
eCSPI (1)
SPBA
Keypad
I2C (4)
CSI (2)
OCOTP
IOMUXC
MU
LCDIF
CMOS Sensor
AP Peripherals
PWM (8)
Multi-CoreUnit
LCD Panel
GPT
Shared Peripherals
KPP
eCSPI (4)
GPIO
SPDIF Tx/Rx
Ethernet (2)
SSI ( 3)
ESAI
UART( 1)
ASRC
10/100/1000M
Ethernet x2
MLB/MOST
Network
CAN (2)
USB OTG (2)
USB Host (HSIC)
Image Processing
Pixel Processing Pipeline
(PXP)
WLAN
Modem IC
Digital Audio
Power Management
MLB
LDOs
PCIe
PCIe Bus
USB OTG
(dev/host)
CAN x2
Figure 2. i.MX 6SoloX System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (8) indicates eight separate PWM peripherals.
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
NXP Semiconductors
9
Modules List
3
Modules List
The i.MX 6SoloX processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX 6SoloX Modules List
Block Mnemonic
Block Name
Subsystem
—
Brief Description
ADC1
ADC2
Analog to Digital
Converter
ARM
ARM Platform
Arm
The ARM Core Platform includes 1x Cortex-A9 and 1x
Cortex-M4 cores. It also includes associated sub-blocks,
such as the Level 2 Cache Controller, SCU (Snoop Control
Unit), GIC (General Interrupt Controller), private timers,
watchdog, and CoreSight debug modules.
ASRC
Asynchronous Sample
Rate Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC)
converts the sampling rate of a signal associated to an
input clock into a signal associated to a different output
clock. The ASRC supports concurrent sample rate
conversion of up to 10 channels of about -120dB THD+N.
The sample rate conversion of each channel is associated
to a pair of incoming and outgoing sampling rates. The
ASRC supports up to three sampling rate pairs.
AUDMUX
Digital Audio Mux
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice,
audio, and synchronous data routing between host serial
interfaces (for example, SSI1, SSI2, and SSI3) and
peripheral serial interfaces (audio and voice codecs). The
AUDMUX has seven ports with identical functionality and
programming models. A desired connectivity is achieved
by configuring two or more AUDMUX ports.
BCH
Binary-BCH ECC
Processor
System Control
Peripherals
The BCH module provides up to 62-bit ECC for NAND
Flash controller (GPMI).
CAAM
Cryptographic
accelerator and
assurance module
Security
CAAM is a cryptographic accelerator and assurance
module. CAAM implements several encryption and
hashing functions, a run-time integrity checker, and a
Pseudo Random Number Generator (PRNG). The pseudo
random number generator is certified by Cryptographic
Algorithm Validation Program (CAVP) of National Institute
of Standards and Technology (NIST). Its DRBG validation
number is 94 and its SHS validation number is 1455.
CAAM also implements a Secure Memory mechanism. In
i.MX 6SoloX processors, the security memory provided is
32 KB.
CCM
GPC
SRC
Clock Control Module,
Clocks, Resets,
These modules are responsible for clock and reset
General Power Controller, and Power Control distribution in the system, and also for the system power
System Reset Controller
management.
CSI
Parallel CSI
Multimedia
Peripherals
The ADC is a 12-bit general purpose analog to digital
converter.
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24 bits.
It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB, and
8-bit/10-bit/26-bit Bayer data input.
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Modules List
Table 2. i.MX 6SoloX Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
CSU
Central Security Unit
Security
The Central Security Unit (CSU) is responsible for setting
comprehensive security policy within the i.MX 6SoloX
platform.
CTI
Cross Trigger Interfaces
Debug/Trace
Cross Trigger Interfaces allows cross-triggering based on
inputs from masters attached to CTIs. The CTI module is
internal to the Cortex-A9 Core Platform.
DAP
Debug Access Port
System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
System memory and peripheral registers
All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-A9 Core
Platform.
DBGMON
Debug Monitor
Debug
DBGMON is a real-time debug monitor to record last AXI
transaction before system reset.
eCSPI1
eCSPI2
eCSPI3
eCSPI4
eCSPI5
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface. It is
configurable to support Master/Slave modes, four chip
selects to support multiple peripherals.
EIM
NOR-Flash /PSRAM
interface
Connectivity
Peripherals
The EIM NOR-FLASH / PSRAM provides:
Support 16-bit (in muxed IO mode only) PSRAM memories
(sync and async operating modes), at slow frequency
Support 16-bit (in muxed IO mode only) NOR-Flash
memories, at slow frequency
Multiple chip selects
ENET1
ENET2
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is designed
to support 10/100/1000 Mbps Ethernet/IEEE 802.3
networks. An external transceiver interface and transceiver
function are required to complete the interface to the
media. The module has dedicated hardware to support the
IEEE 1588 standard. See the ENET chapter of the i.MX
6SoloX Applications Processor Reference Manual
(IMX6SXRM) for details.
EPIT1
EPIT2
Enhanced Periodic
Interrupt Timer
Timer Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts
counting after the EPIT is enabled by software. It is capable
of providing precise interrupts at regular intervals with
minimal processor intervention. It has a 12-bit prescaler for
division of input clock frequency to get the required time
setting for the interrupts to occur, and counter value can be
programmed on the fly.
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11
Modules List
Table 2. i.MX 6SoloX Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
ESAI
Enhanced Serial Audio
Interface
Connectivity
Peripherals
The Enhanced Serial Audio Interface (ESAI) provides a
full-duplex serial port for serial communication with a
variety of serial devices, including industry-standard
codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and receiver
sections, each section with its own clock generator. All
serial transfers are synchronized to a clock. Additional
synchronization signals are used to delineate the word
frames. The normal mode of operation is used to transfer
data at a periodic rate, one word per period. The network
mode is also intended for periodic transfers; however, it
supports up to 32 words (time slots) per period. This mode
can be used to build time division multiplexed (TDM)
networks. In contrast, the on-demand mode is intended for
non-periodic transfers of data and to transfer data serially
at high speed when the data becomes available.
The ESAI has 12 pins for data and clocking connection to
external devices.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed to
be used as a vehicle serial data bus, meeting the specific
requirements of this field: real-time processing, reliable
operation in the Electromagnetic interference (EMI)
environment of a vehicle, cost-effectiveness and required
bandwidth. The FlexCAN module is a full implementation
of the CAN protocol specification, Version 2.0 B, which
supports both standard and extended message frames.
Fuse Box
Electrical Fuse Array
Security
Electrical Fuse Array. Enables setup of boot modes,
security levels, security keys, and many other system
parameters.The fuses are accessible through
OCOTP_CTRL interface.
GC400T
Graphics Engine
Multimedia
Peripherals
The GC400T is a graphics engine with separate 2D and 3D
pipelines to provide both 2D and 3D acceleration. It
supports DirectFB and GAL APIs. It supports OpenGL
ES1.1/2.0 and OpenVG 1.1 APIs.
GIC
Global Interrupt
Controller
Arm/Control
The Global Interrupt Controller (GIC) collects interrupt
requests from all i.MX 6SoloX sources and routes them to
the Arm MPCore(s). Each interrupt can be configured as a
normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported. This IP is
part of the Arm Core complex.
GIS
General Interrupt Service Camera, Display,
module
& Graphics
GIS can be used to automate the flow of data from the
camera to the display.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
General Purpose I/O
Modules
Used for general purpose input/output to external ICs.
Each GPIO module supports 32 bits of I/O.
System Control
Peripherals
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Modules List
Table 2. i.MX 6SoloX Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
GPMI
General Purpose
Memory Interface
Connectivity
Peripherals
The GPMI module supports up to 8x NAND devices and
60-bit ECC encryption/decryption for NAND Flash
Controller (GPMI2). GPMI supports separate DMA
channels for each NAND device.
GPT
General Purpose Timer
Timer Peripherals
Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured to
trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of providing
precise interrupts at regular intervals with minimal
processor intervention. The counter has output compare
logic to provide the status and interrupt at comparison.
This timer can be configured to run either with an external
clock or an internal clock.
I2C-1
I2C-2
I2C-3
I2C-4
I2C Interface
Connectivity
Peripherals
I2C provide serial interface for external devices. Data rates
of up to 400 kbps are supported.
IOMUXC
IOMUX Control
System Control
Peripherals
This module enables flexible IO multiplexing. Each IO pad
has default and several alternate functions. The alternate
functions are software configurable.
KPP
Key Pad Port
Connectivity
Peripherals
KPP Supports 8x8 external key pad matrix. KPP features
are:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
LCDIF
LCD Interface
Multimedia
Peripherals
The LCDIF provides display data for external LCD panels
from simple text-only displays to WVGA, 16/18/24 bpp
color TFT panels. The LCDIF supports all of these different
interfaces by providing fully programmable functionality
and sharing register space, FIFOs, and ALU resources at
the same time. The LCDIF supports RGB (DOTCLK)
modes as well as system mode including both VSYNC and
WSYNC modes.
LVDS (LDB)
LVDS Display Bridge
Connectivity
Peripherals
LVDS Display Bridge is used to connect an external LVDS
display interface. LDB supports the following signals:
• One clock pair
• Four data pairs
MLB
MediaLB
Connectivity/
Multimedia
Peripherals
The MLB interface module provides a link to a MOST®
data network, using the standardized MediaLB protocol
(MOST25, MOST 50).
MMDC
Multi-Mode DDR
Controller
Connectivity
Peripherals
DDR Controller supports 16/32-bit LPDDR2-800,
DDR3-800 and DDR3L-800.
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Modules List
Table 2. i.MX 6SoloX Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
MU
Messaging Unit
Interprocessor
Communication &
Synchronization
The MU module supports interprocessor communication
between the Cortex-A9 and Cortex-M4 cores.
OCOTP_CTRL
OTP Controller
Security
The On-Chip OTP controller (OCOTP_CTRL) provides an
interface for reading, programming, and/or overriding
identification and control information stored in on-chip fuse
elements. The module supports electrically-programmable
(eFUSE) polyfuses. The OCOTP_CTRL also provides a
set of volatile software-accessible signals that can be used
for software control of hardware elements, not requiring
non-volatility. The OCOTP_CTRL provides the primary
user-visible mechanism for interfacing with on-chip fuse
elements. Among the uses for the fuses are unique chip
identifiers, mask revision numbers, cryptographic keys,
JTAG secure mode, boot characteristics, and various
control signals, requiring permanent non-volatility.
OCRAM
On-Chip Memory
Controller
Data Path
The On-Chip Memory controller (OCRAM) module is
designed as an interface between system’s AXI bus and
internal (on-chip) SRAM memory module.
OCRAM 128 KB
Internal RAM
Internal Memory
Internal RAM, which is accessed through OCRAM memory
controller.
OCRAM_S 16KB
Secure/nonsecure RAM
Secured Internal
Memory
Secure/nonsecure internal RAM, interfaced through the
CAAM. OCRAM_S can be used by software for state
retention of the CPU and other hardware blocks.
OSC32KHz
OSC32KHz
Clocking
Generates 32.768 KHz clock from external crystal.
PCIe
PCI Express 2.0
Connectivity
Peripherals
The PCIe IP provides PCI Express Gen 2.0 functionality.
PMU
Power-Management
functions
Data Path
Integrated power management unit. Used to provide power
to various SoC domains.
PWM-1
PWM-2
PWM-3
PWM-4
PWM-5
PWM-6
PWM-7
PWM-8
Pulse Width Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter
and is optimized to generate sound from stored sample
audio images and it can also generate tones. It uses 16-bit
resolution and a 4x16 data FIFO to generate sound.
PXP
PiXel Processing Pipeline Display
Peripherals
A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such as
color-space conversion, alpha blending, gamma-mapping,
and rotation. The PXP is enhanced with features
specifically for gray scale applications.
QSPI
Quad Serial Peripheral
Interface
Connectivity
Peripherals
The Quad Serial Peripheral Interface (QuadSPI) block acts
as an interface to one or two external serial flash devices,
each with up to four bidirectional data lines.
ROM 96KB
Boot ROM
Internal Memory
Supports secure and regular boot modes
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Modules List
Table 2. i.MX 6SoloX Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
RDC
Resource Domain
Controller
Multicore
Isolation/Sharing
RDC module supports domain-based access control to
shared resources.
SEMA4
Semaphore
Multicore/Isolation Supports hardware-enforced semaphores.
/Sharing
SEMA42
Semaphore
Multicore/Isolation SEMA42 is similar to SEMA4 with the following key
/Sharing
differences:
SEMA42 increases the number of access domains from 2
to 15
SEMA42 does not have interrupt to indicate semaphore
release
RDC programming model supports the option to require
hardware semaphore for peripherals shared between
domains. Signaling between the SEMA42 and RDC binds
peripherals to semaphore gates within SEMA42.
SAI1
SAI2
—
—
The SAI module provides a synchronous audio interface
(SAI) that supports full duplex serial interfaces with frame
synchronization, such as I2S, AC97, TDM, and codec/DSP
interfaces.
SDMA
Smart Direct Memory
Access
System Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It helps in
maximizing system performance by off-loading the various
cores in dynamic data routing. It has the following features:
Powered by a 16-bit Instruction-Set micro-RISC engine
Multi-channel DMA supporting up to 32 time-division
multiplexed DMA channels
48 events with total flexibility to trigger any combination of
channels
Memory accesses including linear, FIFO, and 2D
addressing
Shared peripherals between ARM and SDMA
Very fast Context-Switching with 2-level priority based
preemptive multi-tasking
DMA units with auto-flush and prefetch capability
Flexible address management for DMA transfers
(increment, decrement, and no address changes on
source and destination address)
DMA ports can handle unit-directional and bi-directional
flows (copy mode)
Up to 8-word buffer for configurable burst transfers for
EMIv2.5
Support of byte-swapping and CRC calculations
Library of Scripts and API is available
i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 4, 11/2018
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15
Modules List
Table 2. i.MX 6SoloX Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SJC
System JTAG Controller
System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX 6SoloX
processors use JTAG port for production, testing, and
system debugging. In addition, the SJC provides BSR
(Boundary Scan Register) standard support, which
complies with IEEE1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX 6SoloX SJC incorporates
three security modes for protecting against unauthorized
accesses. Modes are selected through eFUSE
configuration.
SNVS
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real Time
Clock, Security State Machine, Master Key Control, and
Violation/Tamper Detection and reporting.
SPDIF
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly by
the Sony and Phillips corporations. Has Transmitter and
Receiver functionality.
SSI1
SSI2
SSI3
I2S/SSI/AC97 Interface
Connectivity
Peripherals
The SSI is a full-duplex synchronous interface, which is
used on the AP to provide connectivity with off-chip audio
peripherals. The SSI supports a wide variety of protocols
(SSI normal, SSI network, I2S, and AC-97), bit depths (up
to 24 bits per word), and clock / frame sync options.
The SSI has two pairs of 8x24 FIFOs and hardware
support for an external DMA controller in order to minimize
its impact on system performance. The second pair of
FIFOs provides hardware interleaving of a second audio
stream that reduces CPU overhead in use cases where
two time slots are being used simultaneously.
TEMPMON
Temperature Monitor
System Control
Peripherals
The Temperature sensor IP is used for detecting die
temperature. The temperature read out does not reflect
case or ambient temperature. It reflects the temperature in
proximity of the sensor location on the die. Temperature
distribution may not be uniformly distributed, therefore the
read out value may not be the reflection of the temperature
value of the entire die.
TZASC
Trust-Zone Address
Space Controller
Security
The TZASC (TZC-380 by Arm) provides security address
region control functions required for intended application. It
is used on the path to the DRAM controller.
UART1
UART2
UART3
UART4
UART5
UART6
UART Interface
Connectivity
Peripherals
Each of the UARTv2 modules support the following serial
data transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 5 Mbps.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx
supporting auto-baud
• Option to operate as 8-pins full UART, DCE, or DTE
• UART1/6 support 8-pin, UART2/3/4/5 support 4-pin
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Modules List
Table 2. i.MX 6SoloX Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
uSDHC1
uSDHC2
uSDHC3
uSDHC4
SD/MMC and SDXC
Connectivity
Enhanced Multi-Media
Peripherals
Card / Secure Digital Host
Controller
i.MX 6SoloX specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and are
based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets and
Physical Layer as defined in the Multimedia Card
System Specification, v4.5/4.2/4.3/4.4/4.41/ including
high-capacity (size > 2 GB) cards HC MMC.
• Fully compliant with SD command/response sets and
Physical Layer as defined in the SD Memory Card
Specifications, v3.0 including high-capacity SDHC
cards up to 32 GB.
• Fully compliant with SDIO command/response sets and
interrupt/read-wait mode as defined in the SDIO Card
Specification, Part E1, v3.0.
• Conforms to the SD Host Controller Standard
Specification version 3.0.
All four ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC
cards up to 52 MHz in both SDR and DDR modes (104
MB/s max)
• All ports can work with 1.8 V and 3.3 V cards. Each port
is placed on a separate power domain.
USB
Universal Serial Bus 2.0
Connectivity
Peripherals
USBOH3 contains:
• Two high-speed OTG 2.0 modules with integrated HS
USB PHYs
• One high-speed Host module connected to HSIC USB
port
WDOG1
WDOG3
Watch Dog
Timer Peripherals
The Watch Dog Timer supports two comparison points
during each counting period. Each of the comparison
points is configurable to evoke an interrupt to the Arm core,
and a second point evokes an external event on the WDOG
line.
WDOG2
(TZ)
Watch Dog (TrustZone)
Timer Peripherals
The TrustZone Watchdog (TZ WDOG) timer module
protects against TrustZone starvation by providing a
method of escaping normal mode and forcing a switch to
the TZ mode. TZ starvation is a situation where the normal
OS prevents switching to the TZ mode. Such situation is
undesirable as it can compromise the system’s security.
Once the TZ WDOG module is activated, it must be
serviced by TZ software on a periodic basis. If servicing
does not take place, the timer times out. Upon a time-out,
the TZ WDOG asserts a TZ mapped interrupt that forces
switching to the TZ mode. If it is still not served, the TZ
WDOG asserts a security violation signal to the CSU. The
TZ WDOG module cannot be programmed or deactivated
by a normal mode software.
XTALOSC
Crystal Oscillator
Interface
Clocks, Resets,
The XTALOSC module connects to an external crystal to
and Power Control provide system clocks.
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Modules List
3.1
Special Signal Considerations
Table 3 lists special signal considerations for the i.MX 6SoloX processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are provided in the i.MX 6SoloX Applications Processor Reference
Manual (IMX6SXRM).
Table 3. Special Signal Considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
CCM_CLK2
Two general purpose differential high speed clock Input/outputs are provided.
Any or both of them could be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC, for example
as alternate reference clock for PCIe, Video/Audio interfaces, etc.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals
See the i.MX 6SoloX Applications Processor Reference Manual (IMX6SXRM) for details on the
respective clock trees.
The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard, the
frequency range supported is 0...600 MHz.
Alternatively one may use single ended signal to drive CLKx_P input. In this case corresponding
CLKx_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
See LVDS pad electrical specification for further details.
After initialization, the CLKx inputs/outputs could be disabled (if not used). If unused any or both of
the CLKx_N/P pairs may be left unconnected.
RTC_XTALI/RTC_XTALO If the user needs to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal (≤100 kΩ ESR, 10 pF load), should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 MΩ). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin should
be left unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be
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