NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6ULLIEC
Rev. 1.2, 11/2017
MCIMX6Y0CVM05AA
MCIMX6Y1CVM05AA
MCIMX6Y1CVK05AA
MCIMX6Y2CVM05AA
MCIMX6Y2CVM08AA
MCIMX6Y2CVK08AB
i.MX 6ULL Applications
Processors for Industrial
Products
MCIMX6Y0CVM05AB
MCIMX6Y1CVM05AB
MCIMX6Y1CVK05AB
MCIMX6Y2CVM05AB
MCIMX6Y2CVM08AB
Package Information
Plastic Package
MAPBGA 14 x 14 mm, 0.8 mm pitch
MAPBGA 9 x 9 mm, 0.5 mm pitch
Ordering Information
See Table 1 on page 3
1
i.MX 6ULL Introduction
The i.MX 6ULL processors represent NXP’s latest
achievement in integrated multimedia-focused products
offering high performance processing with a high degree
of functional integration, targeted towards the growing
market of connected devices.
The i.MX 6ULL is a high performance, ultra efficient
processor family with featuring NXP’s advanced
implementation of the single Arm Cortex®-A7 core,
which operates at speeds of up to 792 MHz. i.MX 6ULL
includes integrated power management module that
reduces the complexity of external power supply and
simplifies the power sequencing. Each processor in this
family provides various memory interfaces, including
LPDDR2, DDR3, DDR3L, Raw and Managed NAND
flash, NOR flash, eMMC, Quad SPI, and a wide range of
other interfaces for connecting peripherals, such as
WLAN, Bluetooth™, GPS, displays, and camera
sensors.
© 2016-2017 NXP B.V.
1. i.MX 6ULL Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Special Signal Considerations . . . . . . . . . . . . . . . 18
3.2. Recommended Connections for Unused Analog
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 21
4.2. Power Supplies Requirements and Restrictions . 31
4.3. Integrated LDO Voltage Regulator Parameters . . 32
4.4. PLL’s Electrical Characteristics . . . . . . . . . . . . . . . 34
4.5. On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . 36
4.6. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 40
4.8. Output Buffer Impedance Parameters . . . . . . . . . 43
4.9. System Modules Timing . . . . . . . . . . . . . . . . . . . . 46
4.10. Multi-Mode DDR Controller (MMDC) . . . . . . . . . . 57
4.11. General-Purpose Media Interface (GPMI) Timing 58
4.12. External Peripheral Interface Parameters . . . . . . . 66
4.13. A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5. Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 103
5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 103
5.2. Boot Device Interface Allocation . . . . . . . . . . . . . 104
6. Package Information and Contact Assignments . . . . . 111
6.1. 14 x 14 mm Package Information . . . . . . . . . . . . 111
6.2. 9 x 9 mm Package Information . . . . . . . . . . . . . . 124
7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
i.MX 6ULL Introduction
The i.MX 6ULL processors are specifically useful for applications such as:
• Telematics
• Audio playback
• Connected devices
• IoT Gateway
• Access control panels
• Human Machine Interfaces (HMI)
• Portable medical and health care
• IP phones
• Smart appliances
• eReaders
The features of the i.MX 6ULL processors include:
• Single-core Arm Cortex-A7—The single core A7 provides a cost-effective and power-efficient
solution.
• Multilevel memory system—The multilevel memory system of processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processor supports
many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR
Flash, NAND Flash (MLC and SLC), OneNAND™, Quad SPI, and managed NAND, including
eMMC up to rev 4.4/4.41/4.5.
• Smart speed technology—Power management implemented throughout the IC that enables
multimedia features and peripherals to consume minimum power in both active and various low
power modes.
• Dynamic voltage and frequency scaling—The power efficiency of devices by scaling the voltage
and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of processor is enhanced by a multilevel
cache system, NEON™ MPE (Media Processor Engine) co-processor, a programmable smart
DMA (SDMA) controller, an asynchronous audio sample rate converter, an Electrophoretic
Display (EPD) controller, and a Pixel processing pipeline (PXP) to support 2D image processing,
including color-space conversion, scaling, alpha-blending, and rotation.
• 2x Ethernet interfaces—2x 10/100 Mbps Ethernet controllers.
• Human-machine interface—Each processor supports one digital parallel display interface.
• Interface flexibility—Each processor supports connections to a variety of interfaces: two
high-speed USB on-the-go with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), two 12-bit ADC modules with up to 10 total input channels and two CAN ports.
• Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, AES-128
encryption, SHA-1, SHA-256 HW acceleration engine, and secure software downloads. The
security features are discussed in the i.MX 6ULL Security Reference Manual (IMX6ULLSRM).
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
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NXP Semiconductors
i.MX 6ULL Introduction
•
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
For a comprehensive list of the i.MX 6ULL features, see Section 1.2, “Features"”.
1.1
Ordering Information
Table 1 provides examples of orderable part numbers covered by this data sheet.
Table 1. Ordering Information
Part Number
Feature
Package
Junction
Temperature Tj
(C)
MCIMX6Y0CVM05AA
MCIMX6Y0CVM05AB
Features supports:
• 528 MHz, industrial grade for general purpose
• No security
• No LCD/CSI
• No CAN
• Ethernet x1
• USB OTG x1
• ADC x1
• UART x4
• SAI x1
• No ESAI
• Timer x2
• PWM x4
• I2C x2
• SPI x2
14 x 14 mm, 0.8 pitch
MAPBGA
-40 to +105
MCIMX6Y1CVM05AA
MCIMX6Y1CVM05AB
Features supports:
• 528 MHz, industrial grade for general purpose
• Basic security
• No LCD/CSI
• CAN x1
• Ethernet x1
• USB OTG x2
• ADC x1
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
14 x 14 mm, 0.8 pitch
MAPBGA
-40 to +105
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
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3
i.MX 6ULL Introduction
Table 1. Ordering Information
Part Number
Feature
Package
Junction
Temperature Tj
(C)
MCIMX6Y1CVK05AA
MCIMX6Y1CVK05AB
Features supports:
• 528 MHz, industrial grade for general purpose
• Basic security
• No LCD/CSI
• CAN x1
• Ethernet x1
• USB OTG x2
• ADC x1
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
9 x 9 mm, 0.5 pitch
MAPBGA
-40 to +105
MCIMX6Y2CVM05AA
MCIMX6Y2CVM05AB
Features supports:
• 528 MHz, industrial grade for general purpose
• Basic security
• With LCD/CSI
• CAN x2
• Ethernet x2
• USB OTG x2
• ADC x2
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
14 x 14mm, 0.8 pitch
MAPBGA
-40 to +105
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
4
NXP Semiconductors
i.MX 6ULL Introduction
Table 1. Ordering Information
Part Number
Feature
Package
Junction
Temperature Tj
(C)
MCIMX6Y2CVM08AA
MCIMX6Y2CVM08AB
Features supports:
• 792 MHz, industrial grade for general purpose
• Basic security
• With LCD/CSI
• CAN x2
• Ethernet x2
• USB OTG x2
• ADC x2
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
14 x 14 mm, 0.8 pitch
MAPBGA
-40 to +105
MCIMX6Y2CVK08AB
Features supports:
• 792 MHz, industrial grade for general purpose
• Basic security
• With LCD/CSI
• CAN x2
• Ethernet x2
• USB OTG x2
• ADC x2
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
9 x 9 mm, 0.5 pitch
MAPBGA
-40 to +105
Figure 1 describes the part number nomenclature so that the users can identify the characteristics of the
specific part number they have (for example, cores, frequency, temperature grade, fuse options, and silicon
revision). The primary characteristic which describes which data sheet applies to a specific part is the
temperature grade (junction) field.
• The i.MX 6ULL Applications Processors for Industrial Products Data Sheet (IMX6ULLIEC)
covers parts listed with a “C (Industrial temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there will be any questions, visit the web page
NXP.com/imx6series or contact a NXP representative for details.
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
5
i.MX 6ULL Introduction
MC
IMX6
X
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MC
Silicon Rev
A
Prototype Samples
PC
Rev 1.0 (Mask number: 0N70S)
A
Mass Production
MC
Rev 1.1 (Mask number: 1N70S)
B
Special
SC
Qualification Level
i.MX 6 Family
i.MX 6ULL
X
Y
Part differentiator
@
With EPDC
7
Reserved
6
5
Fuse Option
%
Reserved
A
Arm Cortex-A7 Frequency
$$
528 MHz
05
792 MHz
08
900 MHz
09
4
3
Package Type
General Purpose 2 (Full Feature)
2
MAPBGA 14 x 14 mm, 0.8 pitch
VM
General Purpose 1 (Reduced Feature)
1
MAPBGA 9 x 9 mm, 0.5 pitch
VK
Baseline
0
Junction Temperature (Tj)
+
Consumer: 0 to + 95 °C
D
Industrial: -40 to +105 °C
C
ROHS
Figure 1. Part Number Nomenclature—i.MX 6ULL
1.2
Features
The i.MX 6ULL processors are based on Arm Cortex-A7 MPCore™ Platform, which has the following
features:
• Supports single Arm Cortex-A7 MPCore (with TrustZone) with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Private Timer and Watchdog
— Cortex-A7 NEON Media Processing Engine (MPE) Co-processor
• General Interrupt Controller (GIC) with 128 interrupts support
• Global Timer
• Snoop Control Unit (SCU)
• 128 KB unified I/D L2 cache
• Single Master AXI bus interface output of L2 cache
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
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NXP Semiconductors
i.MX 6ULL Introduction
•
•
Frequency of the core (including Neon and L1 cache), as per Table 10, "Operating Ranges," on
page 24.
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
— 32 double-precision VFPv3 floating point registers
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia/shared, fast access RAM (OCRAM, 128 KB)
• External memory interfaces: The i.MX 6ULL processors support latest, high volume, cost effective
handheld DRAM, NOR, and NAND Flash memory standards.
— 16-bit LP-DDR2-800, 16-bit DDR3-800 and DDR3L-800
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bits.
— 16/8-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
Each i.MX 6ULL processor enables the following interfaces to external devices (some of them are muxed
and not available simultaneously):
• Displays:
— One parallel display port, support max 85 MHz display clock and up to WXGA (1366 x 768)
at 60 Hz
— Support 24-bit, 18-bit, 16-bit, and 8-bit parallel display
— Electrophoretic display controller support direct-driver for E-Ink EPD panel, with up to
2048x1536 resolution at 106 Hz
• Camera sensors:
— One parallel camera port, up to 24 bit and 133.3 MHz pixel clock
— Support 24-bit, 16-bit, 10-bit, and 8-bit input
— Support BT.656 interface
• Expansion cards:
— Two MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
– 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode
(200 MB/s max)
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
7
i.MX 6ULL Introduction
•
•
USB:
— Two high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
Miscellaneous IPs and interfaces:
— Three I2S/SAI/AC97, up to 1.4 Mbps each
— ESAI
— Sony Philips Digital Interface Format (SPDIF), Rx and Tx
— Eight UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– Support RTS/CTS for hardware flow control
— Four eCSPI (Enhanced CSPI), up to 52 Mbps each
— Four I2C, supports 400 kbps
— Two 10/100 Ethernet Controller (IEEE1588 compliant)
— Eight Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— One Quad SPI to connect to serial NOR flash
— Two Flexible Controller Area Network (FlexCAN)
— Three Watchdog timers (WDOG)
— 8-bit/10-bit/12-bit/16-bit camera interface
— Two 12-bit Analog to Digital Converters (ADC) with up to 10 input channels in total
The i.MX 6ULL processors integrate advanced power management unit and controllers:
•
•
•
•
•
•
•
Provide PMU, including LDO supplies, for on-chip resources
Use Temperature Sensor for monitoring the die temperature
Use Voltage Sensor for monitoring the die voltage
Support DVFS techniques for low power modes
Use SW State Retention and Power Gating for Arm and NEON
Support various levels of system power modes
Use flexible clock gating control scheme
The i.MX 6ULL processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6ULL processors incorporate the following hardware accelerators:
• PXP—Pixel Processing Pipeline for image resize, rotation, overlay and CSC. Off loading key pixel
processing operations are required to support the LCD display applications.
• ASRC—Asynchronous Sample Rate Converter
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
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NXP Semiconductors
i.MX 6ULL Introduction
Security functions are enabled and accelerated by the following hardware:
• Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or
blocking the access to the system debug features.
• SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock, both active tamper and
passive tamper detection logic has up to 10 tamper inputs. Voltage monitor, temperature monitor,
and clock frequency monitor protects the secure key storage.
• CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
• A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
AES-128 encryption, SHA-1, and SHA-256 HW acceleration engine, 2048-bit RSA key, version
control mechanism, warm boot, CSU, and TZ initialization.
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions, such as display and camera interfaces, connectivity interfaces.
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
9
Architectural Overview
2
Architectural Overview
The following subsections provide an architectural overview of the i.MX 6ULL processor system.
2.1
Block Diagram
Figure 2 shows the functional modules in the i.MX 6ULL processor system.
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Figure 2. i.MX 6ULL System Block Diagram
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
10
NXP Semiconductors
Modules List
3
Modules List
The i.MX 6ULL processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX 6ULL Modules List
Block Mnemonic
Block Name
Subsystem
ADC1
ADC2
Analog to Digital
Converter
—
The ADC is a 12-bit general purpose analog to digital
converter.
Arm
Arm Platform
Arm
The Arm Core Platform includes 1x Cortex-A7 core. It
also includes associated sub-blocks, such as the Level
2 Cache Controller, SCU (Snoop Control Unit), GIC
(General Interrupt Controller), private timers, watchdog,
and CoreSight debug modules.
ASRC
Asynchronous Sample
Rate Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC)
converts the sampling rate of a signal associated to an
input clock into a signal associated to a different output
clock. The ASRC supports concurrent sample rate
conversion of up to 10 channels of about -120dB
THD+N. The sample rate conversion of each channel is
associated to a pair of incoming and outgoing sampling
rates. The ASRC supports up to three sampling rate
pairs.
BCH
Binary-BCH ECC
Processor
System Control
Peripherals
CCM
GPC
SRC
Brief Description
The BCH module provides up to 40-bit ECC
encryption/decryption for NAND Flash controller
(GPMI)
Clock Control Module, Clocks, Resets, and These modules are responsible for clock and reset
General Power Controller,
Power Control
distribution in the system, and also for the system power
System Reset Controller
management.
CSI
Parallel CSI
Multimedia
Peripherals
CSU
Central Security Unit
Security
DAP
Debug Access Port
System Control
Peripherals
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
6ULL platform.
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-A7
Core Platform.
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
11
Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
DCP
Data co-processor
Security
This module provides support for general encryption
and hashing functions typically used for security
functions. Because its basic job is moving data from
memory to memory, it also incorporates a memory-copy
(memcopy) function for both debugging and as a more
efficient method of copying data between memory
blocks than the DMA-based approach.
eCSPI1
eCSPI2
eCSPI3
eCSPI4
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface,
with data rate up to 52 Mbit/s. It is configurable to
support Master/Slave modes, four chip selects to
support multiple peripherals.
EIM
NOR-Flash /PSRAM
interface
Connectivity
Peripherals
The EIM NOR-FLASH / PSRAM provides:
• Support 16-bit (in muxed IO mode only) PSRAM
memories (sync and async operating modes), at
slow frequency
• Support 16-bit (in muxed IO mode only) NOR-Flash
memories, at slow frequency
• Multiple chip selects
ENET1
ENET2
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
EPDC
Electrophoretic Display
Controller
Multimedia
Peripherals
The EPDC is a feature-rich, low power, and high
performance direct-drive active matrix EPD controller. It
is specially designed to drive E-INKTM EPD panels,
supporting a wide variety of TFT backplanes.
EPIT1
EPIT2
Enhanced Periodic
Interrupt Timer
Timer Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts
counting after the EPIT is enabled by software. It is
capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a
12-bit prescaler for division of input clock frequency to
get the required time setting for the interrupts to occur,
and counter value can be programmed on the fly.
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
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NXP Semiconductors
Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
ESAI
Enhanced Serial Audio
Interface
Connectivity
Peripherals
The Enhanced Serial Audio Interface (ESAI) provides a
full-duplex serial port for serial communication with a
variety of serial devices, including industry-standard
codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and
receiver sections, each section with its own clock
generator. All serial transfers are synchronized to a
clock. Additional synchronization signals are used to
delineate the word frames. The normal mode of
operation is used to transfer data at a periodic rate, one
word per period. The network mode is also intended for
periodic transfers; however, it supports up to 32 words
(time slots) per period. This mode can be used to build
time division multiplexed (TDM) networks. In contrast,
the on-demand mode is intended for non-periodic
transfers of data and to transfer data serially at high
speed when the data becomes available.
The ESAI has 12 pins for data and clocking connection
to external devices.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports 32 bits of I/O.
GPMI
General Purpose
Memory Interface
Connectivity
Peripherals
The GPMI module supports up to 8x NAND devices and
40-bit ECC encryption/decryption for NAND Flash
Controller (GPMI2). GPMI supports separate DMA
channels for each NAND device.
GPT1
GPT2
General Purpose Timer
Timer peripherals
Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
LCDIF
LCD interface
Connectivity
peripherals
The LCDIF is a general purpose display controller used
to drive a wide range of display devices varying in size
and capability. The LCDIF is designed to support dumb
(synchronous 24-bit Parallel RGB interface) and smart
(asynchronous parallel MPU interface) LCD devices.
MQS
Medium Quality Sound
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
Pulse Width Modulation
Connectivity
peripherals
The pulse-width modulator (PWM) has a 16-bit counter
and is optimized to generate sound from stored sample
audio images and it can also generate tones. It uses
16-bit resolution and a 4x16 data FIFO to generate
sound.
PXP
Pixel Processing Pipeline Display peripherals A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending,
gamma-mapping, and rotation. The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications, allowing it to interface with the integrated
EPD.
RNGB
Random Number
Generator
Security
Random number generating module.
QSPI
Quad SPI
Connectivity
peripherals
Quad SPI module acts as an interface to external serial
flash devices. This module contains the following
features:
• Flexible sequence engine to support various flash
vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of
operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash
devices
• Multi-master access with priority and flexible and
configurable buffer for each master
SAI1
SAI2
SAI3
—
—
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SDMA
Smart Direct Memory
Access
System Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It
helps in maximizing system performance by off-loading
the various cores in dynamic data routing. It has the
following features:
• Powered by a 16-bit Instruction-Set micro-RISC
engine
• Multi-channel DMA supporting up to 32 time-division
multiplexed DMA channels
• 48 events with total flexibility to trigger any
combination of channels
• Memory accesses including linear, FIFO, and 2D
addressing
• Shared peripherals between Arm and SDMA
• Very fast Context-Switching with 2-level priority
based preemptive multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers
(increment, decrement, and no address changes on
source and destination address)
• DMA ports can handle unit-directional and
bi-directional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers
for EMIv2.5
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SJC
System JTAG Controller
System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX 6ULL
processors use JTAG port for production, testing, and
system debugging. In addition, the SJC provides BSR
(Boundary Scan Register) standard support, which
complies with IEEE1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX 6ULL SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
SPDIF
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
System Counter
—
—
The system counter module is a programmable system
counter which provides a shared time base to the
Cortex A series cores as part of Arm’s generic timer
architecture. It is intended for use in application where
the counter is always powered on and supports
multiple, unrelated clocks.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
TSC
Touch Screen
Touch Controller
TZASC
Trust-Zone Address
Space Controller
Security
The TZASC (TZC-380 by Arm) provides security
address region control functions required for intended
application. It is used on the path to the DRAM
controller.
UART1
UART2
UART3
UART4
UART5
UART6
UART7
UART8
UART Interface
Connectivity
Peripherals
Each of the UARTv2 module supports the following
serial data transmit/receive protocols and
configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 5 Mbps.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx
supporting auto-baud
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
Peripherals
i.MX 6ULL specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia Card
System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
However, the SoC level integration and I/O muxing logic
restrict the functionality to the following:
• Instances #1 and #2 are primarily intended to serve
as interfaces to on-board peripherals. These ports
are equipped with “Card detection” and “Write
Protection” pads and do not support hardware reset.
• All ports can work with 1.8 V and 3.3 V cards. There
are two completely independent I/O power domains
for Ports #1 and #2 in four bit configuration (SD
interface).
With touch controller to support 4-wire and 5-wire
resistive touch panel.
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Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
USB
Universal Serial Bus 2.0
Connectivity
Peripherals
USBO2 (USB OTG1 and USB OTG2) contains:
• Two high-speed OTG 2.0 modules with integrated
HS USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
WDOG1
WDOG3
Watch Dog
Timer Peripherals
The Watch Dog Timer supports two comparison points
during each counting period. Each of the comparison
points is configurable to evoke an interrupt to the Arm
core, and a second point evokes an external event on
the WDOG line.
WDOG2
(TZ)
Watch Dog (TrustZone)
Timer Peripherals
The TrustZone Watchdog (TZ WDOG) timer module
protects against TrustZone starvation by providing a
method of escaping normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. Such
situation is undesirable as it can compromise the
system’s security. Once the TZ WDOG module is
activated, it must be serviced by TZ software on a
periodic basis. If servicing does not take place, the timer
times out. Upon a time-out, the TZ WDOG asserts a TZ
mapped interrupt that forces switching to the TZ mode.
If it is still not served, the TZ WDOG asserts a security
violation signal to the CSU. The TZ WDOG module
cannot be programmed or deactivated by a normal
mode SW.
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Modules List
3.1
Special Signal Considerations
Table 3 lists special signal considerations for the i.MX 6ULL processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments".” Signal descriptions are provided in the i.MX 6ULL Reference Manual (IMX6ULLRM).
Table 3. Special Signal Considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
One general purpose differential high speed clock Input/output is provided.
It can be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals.
See the i.MX 6ULL Reference Manual (IMX6ULLRM) for details on the respective clock trees.
Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding
CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
After initialization, the CLK1 input/output can be disabled (if not used). If unused, either or both of
the CLK1_N/P pairs may remain unconnected.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin should
be remain unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be @
/&'Q&RQWURO6LJQDOV
/
/
/
/
Figure 50. LCD Timing
Table 60. LCD Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
tCLK(LCD)
—
150
MHz
L1
LCD pixel clock frequency
L2
LCD pixel clock high (falling edge capture)
tCLKH(LCD)
3
—
ns
L3
LCD pixel clock low (rising edge capture)
tCLKL(LCD)
3
—
ns
L4
LCD pixel clock high to data valid (falling edge capture)
td(CLKH-DV)
-1
1
ns
L5
LCD pixel clock low to data valid (rising edge capture)
td(CLKL-DV)
-1
1
ns
L6
LCD pixel clock high to control signal valid (falling edge capture)
td(CLKH-CTRLV)
-1
1
ns
L7
LCD pixel clock low to control signal valid (rising edge capture)
td(CLKL-CTRLV)
-1
1
ns
4.12.9.1
LCDIF Signal Mapping
Table 61 lists the details about the mapping signals.
Table 61. LCD Timing Parameters
Pin name
8-bit DOTCLK LCD
IF
16-bit DOTCLK LCD
IF
18-bit DOTCLK LCD
IF
24-bit DOTCLK LCD
IF
8-bit DVI LCD
IF
LCD_RS
—
—
—
—
CCIR_CLK
LCD_VSYNC*
(Two options)
LCD_VSYNC
LCD_VSYNC
LCD_VSYNC
LCD_VSYNC
—
LCD_HSYNC
LCD_HSYNC
LCD_HSYNC
LCD_HSYNC
LCD_HSYNC
—
LCD_DOTCLK
LCD_DOTCLK
LCD_DOTCLK
LCD_DOTCLK
LCD_DOTCLK
—
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Table 61. LCD Timing Parameters (continued)
LCD_ENABLE
LCD_ENABLE
LCD_ENABLE
LCD_ENABLE
LCD_ENABLE
—
LCD_D23
—
—
—
R[7]
—
LCD_D22
—
—
—
R[6]
—
LCD_D21
—
—
—
R[5]
—
LCD_D20
—
—
—
R[4]
—
LCD_D19
—
—
—
R[3]
—
LCD_D18
—
—
—
R[2]
—
LCD_D17
—
—
R[5]
R[1]
—
LCD_D16
—
—
R[4]
R[0]
—
LCD_D15 /
VSYNC*
—
R[4]
R[3]
G[7]
—
LCD_D14 /
HSYNC**
—
R[3]
R[2]
G[6]
—
LCD_D13 /
LCD_DOTCLK
**
—
R21]
R[1]
G[5]
—
LCD_D12 /
ENABLE**
—
R[1]
R[0]
G[4]
—
LCD_D11
—
R[0]
G[5]
G[3]
—
LCD_D10
—
G[5]
G[4]
G[2]
—
LCD_D9
—
G[4]
G[3]
G[1]
—
LCD_D8
—
G[3]
G[2]
G[0]
—
LCD_D8
—
G[3]
G[2]
G[0]
—
LCD_D7
R[2]
G[2]
G[1]
B[7]
Y/C[7]
LCD_D6
R[1]
G[1]
G[0]
B[6]
Y/C[6]
LCD_D5
R[0]
G[0]
B[5]
B[5]
Y/C[5]
LCD_D4
G[2]
B[4]
B[4]
B[4]
Y/C[4]
LCD_D3
G[1]
B[3]
B[3]
B[3]
Y/C[3]
LCD_D2
G[0]
B[2]
B[2]
B[2]
Y/C[2]
LCD_D1
B[1]
B[1]
B[1]
B[1]
Y/C[1]
LCD_D0
B[0]
B[0]
B[0]
B[0]
Y/C[0]
LCD_RESET
LCD_RESET
LCD_RESET
LCD_RESET
LCD_RESET
—
LCD_BUSY /
LCD_VSYNC
LCD_BUSY (or
optional
LCD_VSYNC)
LCD_BUSY (or
optional LCD_VSYNC)
LCD_BUSY (or
optional
LCD_VSYNC)
LCD_BUSY (or
optional
LCD_VSYNC)
—
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4.12.10 QUAD SPI (QSPI) Timing Parameters
Measurement conditions are with 35 pF load on SCK and SIO pins and input slew rate of 1 V/ns.
4.12.10.1 SDR Mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$> @
Figure 51. QuadSPI Input/Read Timing (SDR mode with internal sampling)
Table 62. QuadSPI Input Timing (SDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
Setup time for incoming data
8.67
—
ns
TIH
Hold time requirement for incoming data
0
—
ns
463,[B6&/.
463,[B'$7$> @
7,6
7,+
7,6
7,+
463,[B'46
Figure 52. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Table 63. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
Setup time for incoming data
2
—
ns
TIH
Hold time requirement for incoming data
1
—
ns
•
NOTE
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
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•
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
463,[B6&/.
7&66
7&6+
7&.
463,[B&6
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 53. QuadSPI Output/Write Timing (SDR mode)
Table 64. QuadSPI Output/Write Timing (SDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
Output data valid time
—
2
ns
TDHO
Output data hold time
-0.5
—
ns
TCK
SCK clock period
10
—
ns
TCSS
Chip select output setup time
3
—
SCK cycle(s)
TCSH
Chip select output hold time
3
—
SCK cycle(s)
NOTE
Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the default
value of 3 are shown on the timing. Please refer to the i.MX 6ULL Reference
Manual (IMX6ULLRM) for more details.
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4.12.10.2 DDR Mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$> @
Figure 54. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Table 65. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
Setup time for incoming data
8.67
—
ns
TIH
Hold time requirement for incoming data
0
—
ns
463,[B6&/.
463,[B'$7$> @
7,6
7,+
7,6
7,+
463,[B'46
Figure 55. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Table 66. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
Setup time for incoming data
2
—
ns
TIH
Hold time requirement for incoming data
1
—
ns
•
NOTE
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
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•
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
463,[B6&/.
7&66
7&.
7&6+
463,[B&6
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 56. QuadSPI Output/Write Timing (DDR mode)
Table 67. QuadSPI Output/Write Timing (DDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
Output data valid time
—
(0.25 x TSCLK) + 2
ns
TDHO
Output data hold time
(0.25 x TSCLK) - 0.5
—
ns
TCK
SCK clock period
20
—
ns
TCSS
Chip select output setup time
3
—
SCK cycle(s)
TCSH
Chip select output hold time
3
—
SCK cycle(s)
NOTE
Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the default
value of 3 are shown on the timing. Please refer to the i.MX 6ULL Reference
Manual (IMX6ULLRM) for more details.
4.12.11 SAI/I2S Switching Specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 68. Master Mode SAI Timing
Num
Characteristic
Min
Max
Unit
S1
SAI_MCLK cycle time
2 x tsys
—
ns
S2
SAI_MCLK pulse width high/low
40%
60%
MCLK period
S3
SAI_BCLK cycle time
4 x tsys
—
ns
S4
SAI_BCLK pulse width high/low
40%
60%
BCLK period
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Table 68. Master Mode SAI Timing (continued)
Num
Characteristic
Min
Max
Unit
S5
SAI_BCLK to SAI_FS output valid
—
15
ns
S6
SAI_BCLK to SAI_FS output invalid
0
—
ns
S7
SAI_BCLK to SAI_TXD valid
—
15
ns
S8
SAI_BCLK to SAI_TXD invalid
0
—
ns
S9
SAI_RXD/SAI_FS input setup before SAI_BCLK
15
—
ns
S10
SAI_RXD/SAI_FS input hold after SAI_BCLK
0
—
ns
Figure 57. SAI Timing — Master Modes
Table 69. Master Mode SAI Timing
Num
Characteristic
Min
Max
Unit
S11
SAI_BCLK cycle time (input)
4 x tsys
—
ns
S12
SAI_BCLK pulse width high/low (input)
40%
60%
BCLK period
S13
SAI_FS input setup before SAI_BCLK
10
—
ns
S14
SAI_FA input hold after SAI_BCLK
2
—
ns
S15
SAI_BCLK to SAI_TXD/SAI_FS output valid
—
20
ns
S16
SAI_BCLK to SAI_TXD/SAI_FS output invalid
0
—
ns
S17
SAI_RXD setup before SAI_BCLK
10
—
ns
S18
SAI_RXD hold after SAI_BCLK
2
—
ns
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Figure 58. SAI Timing — Slave Modes
4.12.12 SCAN JTAG Controller (SJC) Timing Parameters
Figure 59 depicts the SJC test clock input timing. Figure 60 depicts the SJC boundary scan timing.
Figure 61 depicts the SJC test access port. Signal parameters are listed in Table 70.
SJ1
SJ2
JTAG_TCK
(Input)
VM
VIH
SJ2
VM
VIL
SJ3
SJ3
Figure 59. Test Clock Input Timing Diagram
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JTAG_TCK
(Input)
VIH
VIL
SJ4
Data
Inputs
SJ5
Input Data Valid
SJ6
Data
Outputs
Output Data Valid
SJ7
Data
Outputs
SJ6
Data
Outputs
Output Data Valid
Figure 60. Boundary Scan (JTAG) Timing Diagram
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JTAG_TCK
(Input)
VIH
VIL
SJ8
JTAG_TDI
JTAG_TMS
(Input)
SJ9
Input Data Valid
SJ10
JTAG_TDO
(Output)
Output Data Valid
SJ11
JTAG_TDO
(Output)
SJ10
JTAG_TDO
(Output)
Output Data Valid
Figure 61. Test Access Port Timing Diagram
JTAG_TCK
(Input)
JTAG_TRST_B
(Input)
SJ13
SJ12
Figure 62. JTAG_TRST_B Timing Diagram
Table 70. JTAG Timing
All Frequencies
Parameter1,2
ID
Unit
Min
Max
0.001
22
MHz
45
—
ns
22.5
—
ns
SJ0
JTAG_TCK frequency of operation 1/(3•TDC)1
SJ1
JTAG_TCK cycle time in crystal mode
SJ2
JTAG_TCK clock pulse width measured at VM2
SJ3
JTAG_TCK rise and fall times
—
3
ns
SJ4
Boundary scan input data set-up time
5
—
ns
SJ5
Boundary scan input data hold time
24
—
ns
SJ6
JTAG_TCK low to output data valid
—
40
ns
SJ7
JTAG_TCK low to output high impedance
—
40
ns
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Table 70. JTAG Timing (continued)
All Frequencies
Parameter1,2
ID
1
2
Unit
Min
Max
SJ8
JTAG_TMS, JTAG_TDI data set-up time
5
—
ns
SJ9
JTAG_TMS, JTAG_TDI data hold time
25
—
ns
SJ10
JTAG_TCK low to JTAG_TDO data valid
—
44
ns
SJ11
JTAG_TCK low to JTAG_TDO high impedance
—
44
ns
SJ12
JTAG_TRST_B assert time
100
—
ns
SJ13
JTAG_TRST_B set-up time to JTAG_TCK low
40
—
ns
TDC = target frequency of SJC
VM = mid-point voltage
4.12.13 SPDIF Timing Parameters
The Sony/Philips Digital Interface Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 71, Figure 63, and Figure 64 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 71. SPDIF Timing Parameters
Timing Parameter Range
Characteristics
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
SPDIF_OUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIF_OUT1 output (Load = 30pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
Modulating Rx clock (SPDIF_SR_CLK) period
srckp
40.0
—
ns
SPDIF_SR_CLK high period
srckph
16.0
—
ns
SPDIF_SR_CLK low period
srckpl
16.0
—
ns
Modulating Tx clock (SPDIF_ST_CLK) period
stclkp
40.0
—
ns
SPDIF_ST_CLK high period
stclkph
16.0
—
ns
SPDIF_ST_CLK low period
stclkpl
16.0
—
ns
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srckp
srckpl
srckph
SPDIF_SR_CLK
VM
VM
(Output)
Figure 63. SPDIF_SR_CLK Timing Diagram
stclkp
stclkpl
SPDIF_ST_CLK
stclkph
VM
VM
(Input)
Figure 64. SPDIF_ST_CLK Timing Diagram
4.12.14 UART I/O Configuration and Timing Parameters
4.12.14.1 UART RS-232 Serial Mode Timing
The following sections describe the electrical information of the UART module in the RS-232 mode.
4.12.14.1.1 UART Transmitter
Figure 65 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 72 lists the UART RS-232 serial mode transmits timing characteristics.
UA1
UARTx_TX_DATA
(output)
Possible
Parity
Bit
UA1
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
Next
Start
Bit
UA1
UA1
Figure 65. UART RS-232 Serial Mode Transmit Timing Diagram
Table 72. RS-232 Serial Mode Transmit Timing Parameters
ID
UA1
1
2
Parameter
Transmit Bit Time
Symbol
Min
Max
Unit
tTbit
1/Fbaud_rate1 - Tref_clk2
1/Fbaud_rate + Tref_clk
—
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
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4.12.14.1.2 UART Receiver
Figure 66 depicts the RS-232 serial mode receives timing with 8 data bit/1 stop bit format. Table 73 lists
serial mode receive timing characteristics.
UA2
UARTx_RX_DATA
(output)
Start
Bit
Possible
Parity
Bit
UA2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Next
Start
Bit
Par Bit STOP
BIT
UA2
UA2
Figure 66. UART RS-232 Serial Mode Receive Timing Diagram
Table 73. RS-232 Serial Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 - 1/(16
x Fbaud_rate)
1/Fbaud_rate +
1/(16 x Fbaud_rate)
—
1
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.12.14.1.3 UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
UART IrDA Mode Transmitter
Figure 67 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 74 lists
the transmit timing characteristics.
UA3
UA4
UA3
UA3
UA3
RGMII_TXD
(output)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Possible
Parity
Bit
Bit 7
STOP
BIT
Figure 67. UART IrDA Mode Transmit Timing Diagram
Table 74. IrDA Mode Transmit Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA3
Transmit Bit Time in IrDA mode
tTIRbit
1/Fbaud_rate1 Tref_clk2
1/Fbaud_rate + Tref_clk
—
UA4
Transmit IR Pulse Duration
tTIRpulse
(3/16) x (1/Fbaud_rate) (3/16) x (1/Fbaud_rate)
- Tref_clk
+ Tref_clk
—
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1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
UART IrDA Mode Receiver
Figure 68 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 75 lists the
receive timing characteristics.
UA5
UA6
UA5
UA5
UA5
RGMII_RXD
(input)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Possible
Parity
Bit
Bit 7
STOP
BIT
Figure 68. UART IrDA Mode Receive Timing Diagram
Table 75. IrDA Mode Receive Timing Parameters
ID
Parameter
UA5
Receive Bit Time1 in IrDA mode
UA6
Receive IR Pulse Duration
Symbol
Min
Max
Unit
tRIRbit
1/Fbaud_rate2 - 1/(16
x Fbaud_rate)
1/Fbaud_rate + 1/(16 x
Fbaud_rate)
—
tRIRpulse
1.41 s
(5/16) x (1/Fbaud_rate)
—
1
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.12.15 USB PHY Parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG with the following amendments.
• USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
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•
•
•
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
— Portable device only
4.13
A/D converter
The following subsections provide information about A/D converter.
4.13.1
12-bit ADC electrical characteristics
4.13.1.1
12-bit ADC operating conditions
Table 76. 12-bit ADC Operating Conditions
Characteristic
Supply voltage
Conditions
Symb
Typ1
Min
Max
Unit
Comment
Absolute
VDDAD
3.0
-
3.6
V
—
Delta to VDD
(VDD-VDDAD)2
VDDAD
-100
0
100
mV
—
Ground voltage
Delta to VSS
(VSS-VSSAD)
VSSAD
-100
0
100
mV
—
Ref Voltage High
—
VREFH
1.13
VDDAD
VDDAD
V
—
Ref Voltage Low
—
VREFL
VSSAD
VSSAD
VSSAD
V
—
Input Voltage
—
VADIN
VREFL
—
VREFH
V
—
Input Capacitance
8/10/12 bit modes
CADIN
—
1.5
2
pF
—
Input Resistance
ADLPC=0, ADHSC=1
RADIN
—
5
7
kohms
—
ADLPC=0, ADHSC=0
—
12.5
15
kohms
—
ADLPC=1, ADHSC=0
—
25
30
kohms
—
RAS
12 bit mode fADCK =
40MHz ADLSMP=0,
ADSTS=10, ADHSC=1
—
—
1
kohms
Tsamp=150
ns
Analog Source
Resistance
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
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Table 76. 12-bit ADC Operating Conditions (continued)
Characteristic
Conditions
ADC Conversion Clock
Frequency
ADLPC=0, ADHSC=1
12 bit mode
Symb
fADCK
Typ1
Min
Max
Unit
Comment
4
—
40
MHz
—
ADLPC=0, ADHSC=0
12 bit mode
4
—
30
MHz
—
ADLPC=1, ADHSC=0
12 bit mode
4
—
20
MHz
—
1
Typical values assume VDDAD = 3.0 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
DC potential differences
Figure 69. 12-bit ADC Input Impedance Equivalency Diagram
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Electrical Characteristics
4.13.1.1.1
12-bit ADC characteristics
Table 77. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic
[L:] Supply Current
Conditions1
ADLPC=1,
ADHSC=0
Symb
IDDAD
Typ2
Min
—
250
ADLPC=0,
ADHSC=0
350
ADLPC=0,
ADHSC=1
400
Max
Unit
Comment
—
µA
ADLSMP=0
ADSTS=10 ADCO=1
[L:] Supply Current
Stop, Reset, Module
Off
IDDAD
—
0.01
0.8
µA
—
ADC Asynchronous
Clock Source
ADHSC=0
fADACK
—
10
—
MHz
tADACK = 1/fADACK
—
20
—
—
2
—
cycles
—
Sample Cycles
ADHSC=1
ADLSMP=0,
ADSTS=00
Csamp
ADLSMP=0,
ADSTS=01
4
ADLSMP=0,
ADSTS=10
6
ADLSMP=0,
ADSTS=11
8
ADLSMP=1,
ADSTS=00
12
ADLSMP=1,
ADSTS=01
16
ADLSMP=1,
ADSTS=10
20
ADLSMP=1,
ADSTS=11
24
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Table 77. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
Conversion Cycles
Conversion Time
[P:][C:] Total
Unadjusted Error
[P:][C:] Differential
Non-Linearity
Conditions1
ADLSMP=0
ADSTS=00
Symb
Cconv
Typ2
Min
—
28
ADLSMP=0
ADSTS=01
30
ADLSMP=0
ADSTS=10
32
ADLSMP=0
ADSTS=11
34
ADLSMP=1
ADSTS=00
38
ADLSMP=1
ADSTS=01
42
ADLSMP=1
ADSTS=10
46
ADLSMP=1,
ADSTS=11
50
ADLSMP=0
ADSTS=00
Tconv
—
0.7
ADLSMP=0
ADSTS=01
0.75
ADLSMP=0
ADSTS=10
0.8
ADLSMP=0
ADSTS=11
0.85
ADLSMP=1
ADSTS=00
0.95
ADLSMP=1
ADSTS=01
1.05
ADLSMP=1
ADSTS=10
1.15
ADLSMP=1,
ADSTS=11
1.25
12 bit mode
Comment
cycles
—
—
µs
Fadc=40 MHz
LSB
1 LSB =
(VREFH VREFL)/2
N
—
LSB
—
4.5
—
10 bit mode
—
2
—
8 bit mode
—
1.5
—
—
1
—
10bit mode
—
0.5
—
8 bit mode
—
0.2
—
DNL
Unit
—
—
12 bit mode
TUE
Max
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Table 77. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
[P:][C:] Integral
Non-Linearity
Conditions1
12 bit mode
Zero-Scale Error
Typ2
Max
2.6
—
10bit mode
—
0.8
—
8 bit mode
—
0.3
—
—
-0.3
—
10bit mode
—
-0.15
—
8 bit mode
—
-0.15
—
—
-2.5
—
10bit mode
—
-0.6
—
8 bit mode
—
-0.3
—
10.7
—
12 bit mode
INL
Min
—
12 bit mode
Full-Scale Error
Symb
EZS
EFS
[L:] Effective Number 12 bit mode
of Bits
ENOB
10.1
[L:] Signal to Noise
plus Distortion
SINAD
SINAD = 6.02 x ENOB + 1.76
1
2
See ENOB
Unit
Comment
LSB
—
LSB
—
LSB
—
Bits
—
dB
—
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE
The ADC electrical spec would be met with the calibration enabled
configuration.
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Boot Mode Configuration
5
Boot Mode Configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot Mode Configuration Pins
Table 78 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX 6ULL Fuse
Map document and the System Boot chapter in i.MX 6ULL Reference Manual (IMX6ULLRM).
Table 78. Fuses and Associated Pins Used for Boot
Pin
Direction at reset
eFuse name
Details
BOOT_MODE0
Input with 100 K pull-down
N/A
Boot mode selection
BOOT_MODE1
Input with 100 K pull-down
N/A
Boot mode selection
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Boot Mode Configuration
Table 78. Fuses and Associated Pins Used for Boot (continued)
Pin
5.2
Direction at reset
eFuse name
LCD_DATA00
Input with 100 K pull-down
BT_CFG1[0]
LCD_DATA01
Input with 100 K pull-down
BT_CFG1[1]
LCD_DATA02
Input with 100 K pull-down
BT_CFG1[2]
LCD_DATA03
Input with 100 K pull-down
BT_CFG1[3]
LCD_DATA04
Input with 100 K pull-down
BT_CFG1[4]
LCD_DATA05
Input with 100 K pull-down
BT_CFG1[5]
LCD_DATA06
Input with 100 K pull-down
BT_CFG1[6]
LCD_DATA07
Input with 100 K pull-down
BT_CFG1[7]
LCD_DATA08
Input with 100 K pull-down
BT_CFG2[0]
LCD_DATA09
Input with 100 K pull-down
BT_CFG2[1]
LCD_DATA10
Input with 100 K pull-down
BT_CFG2[2]
LCD_DATA11
Input with 100 K pull-down
BT_CFG2[3]
LCD_DATA12
Input with 100 K pull-down
BT_CFG2[4]
LCD_DATA13
Input with 100 K pull-down
BT_CFG2[5]
LCD_DATA14
Input with 100 K pull-down
BT_CFG2[6]
LCD_DATA15
Input with 100 K pull-down
BT_CFG2[7]
LCD_DATA16
Input with 100 K pull-down
BT_CFG4[0]
LCD_DATA17
Input with 100 K pull-down
BT_CFG4[1]
LCD_DATA18
Input with 100 K pull-down
BT_CFG4[2]
LCD_DATA19
Input with 100 K pull-down
BT_CFG4[3]
LCD_DATA20
Input with 100 K pull-down
BT_CFG4[4]
LCD_DATA21
Input with 100 K pull-down
BT_CFG4[5]
LCD_DATA22
Input with 100 K pull-down
BT_CFG4[6]
LCD_DATA23
Input with 100 K pull-down
BT_CFG4[7]
Details
Boot Options, Pin value overrides
fuse settings for BT_FUSE_SEL =
‘0’. Signal Configuration as Fuse
Override Input at Power Up.
These are special I/O lines that
control the boot up configuration
during product development. In
production, the boot configuration
can be controlled by fuses.
Boot Device Interface Allocation
The following tables list the interfaces that can be used by the boot process in accordance with the
specific boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC
allocation, which are configured during boot when appropriate.
Table 79. QSPI Boot trough QSPI
Ball Name
Signal Name
Mux
Mode
Common
Quad
Mode
NAND_WP_B
qspi.A_SCLK
Alt2
Yes
Yes
NAND_DQS
qspi.A_SS0_B
Alt2
Yes
Yes
+ Port A
DQS
+ Port A
CS1
+ Port
B
+ Port B
DQS
+ Port B
CS1
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Table 79. QSPI Boot trough QSPI (continued)
NAND_READY_B
qspi.A_DATA[0]
Alt2
Yes
Yes
NAND_CE0_B
qspi.A_DATA[1]
Alt2
Yes
Yes
NAND_CE1_B
qspi.A_DATA[2]
Alt2
Yes
Yes
NAND_CLE
qspi.A_DATA[3]
Alt2
Yes
Yes
NAND_DATA05
qspi.B_DATA[3]
Alt2
Yes
NAND_DATA04
qspi.B_DATA[2]
Alt2
Yes
NAND_DATA03
qspi.B_DATA[1]
Alt2
Yes
NAND_DATA02
qspi.B_DATA[0]
Alt2
Yes
NAND_WE_B
qspi.B_SS0_B
Alt2
Yes
NAND_RE_B
qspi.B_SCLK
Alt2
Yes
NAND_DATA07
qspi.A_SS1_B
Alt2
NAND_ALE
qspi.A_DQS
Alt2
NAND_DATA00
qspi.B_SS1_B
Alt2
NAND_DATA01
qspi.B_DQS
Alt2
Yes
Yes
Yes
Yes
Table 80. SPI Boot through ECSPI1
Ball Name
Signal Name
Mux
Mode
Common
CSI_DATA07
ecspi1.MISO
Alt 3
Yes
CSI_DATA06
ecspi1.MOSI
Alt 3
Yes
CSI_DATA04
ecspi1.SCLK
Alt 3
Yes
CSI_DATA05
ecspi1.SS0
Alt 3
LCD_DATA05
ecspi1.SS1
Alt 8
LCD_DATA06
ecspi1.SS2
Alt 8
LCD_DATA07
ecspi1.SS3
Alt 8
BOOT_CFG4 BOOT_CFG4 BOOT_CFG4 BOOT_CFG4
[5:4]=00b
[5:4]=01b
[5:4]=10b
[5:4]=11b
Yes
Yes
Yes
Yes
Table 81. SPI Boot through ECSPI2
Ball Name
Signal Name
Mux Mode
Common
CSI_DATA03
ecspi2.MISO
Alt 3
Yes
CSI_DATA02
ecspi2.MOSI
Alt 3
Yes
CSI_DATA00
ecspi2.SCLK
Alt 3
Yes
CSI_DATA01
ecspi2.SS0
Alt 3
LCD_HSYNC
ecspi2.SS1
Alt 8
BOOT_CFG
4[5:4]=00b
BOOT_CFG4 BOOT_CFG4 BOOT_CFG4
[5:4]=01b
[5:4]=10b
[5:4]=11b
Yes
Yes
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Table 81. SPI Boot through ECSPI2 (continued)
LCD_VSYNC
ecspi2.SS2
Alt 8
LCD_RESET
ecspi2.SS3
Alt 8
Yes
Yes
Table 82. SPI Boot through ECSPI3
Ball Name
Signal Name
Mux
Mode
Common
UART2_RTS_B
ecspi3.MISO
Alt 8
Yes
UART2_CTS_B
ecspi3.MOSI
Alt 8
Yes
UART2_RX_DATA
ecspi3.SCLK
Alt 8
Yes
UART2_TX_DATA
ecspi3.SS0
Alt 8
NAND_ALE
ecspi3.SS1
Alt 8
NAND_RE_B
ecspi3.SS2
Alt 8
NAND_WE_B
ecspi3.SS3
Alt 8
BOOT_CFG4 BOOT_CFG4[ BOOT_CFG4[ BOOT_CFG4
[5:4]=00b
5:4]=01b
5:4]=10b
[5:4]=11b
Yes
Yes
Yes
Yes
Table 83. SPI Boot through ECSPI4
Ball Name
Signal Name
Mux
Mode
Common
ENET2_TX_CLK
ecspi4.MISO
Alt 3
Yes
ENET2_TX_EN
ecspi4.MOSI
Alt 3
Yes
ENET2_TX_DATA1
ecspi4.SCLK
Alt 3
Yes
ENET2_RX_ER
ecspi4.SS0
Alt 3
NAND_DATA01
ecspi4.SS1
Alt 8
NAND_DATA02
ecspi4.SS2
Alt 8
NAND_DATA03
ecspi4.SS3
Alt 8
BOOT_CFG4 BOOT_CFG4[ BOOT_CFG4[
[5:4]=00b
5:4]=01b
5:4]=10b
BOOT_CFG
4[5:4]=11b
Yes
Yes
Yes
Yes
Table 84. NAND Boot through GPMI
Ball Name
Signal Name
Mux Mode
Common
NAND_CLE
rawnand.CLE
Alt 0
Yes
NAND_ALE
rawnand.ALE
Alt 0
Yes
NAND_WP_B
rawnand.WP_B
Alt 0
Yes
NAND_READY_B
rawnand.READY_B
Alt 0
Yes
NAND_CE0_B
rawnand.CE0_B
Alt 0
Yes
NAND_CE1_B
rawnand.CE1_B
Alt 0
NAND_RE_B
rawnand.RE_B
Alt 0
BOOT_CFG1[3:2]=
01b
BOOT_CFG1[3:2]=
10b
Yes
Yes
Yes
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Boot Mode Configuration
Table 84. NAND Boot through GPMI (continued)
BOOT_CFG1[3:2]=
01b
BOOT_CFG1[3:2]=
10b
Ball Name
Signal Name
Mux Mode
Common
NAND_WE_B
rawnand.WE_B
Alt 0
Yes
NAND_DATA00
rawnand.DATA00
Alt 0
Yes
NAND_DATA01
rawnand.DATA01
Alt 0
Yes
NAND_DATA02
rawnand.DATA02
Alt 0
Yes
NAND_DATA03
rawnand.DATA03
Alt 0
Yes
NAND_DATA04
rawnand.DATA04
Alt 0
Yes
NAND_DATA05
rawnand.DATA05
Alt 0
Yes
NAND_DATA06
rawnand.DATA06
Alt 0
Yes
NAND_DATA07
rawnand.DATA07
Alt 0
Yes
NAND_DQS
rawnand.DQS
Alt 0
Yes
CSI_MCLK
rawnand.CE2_B
Alt 2
Yes
CSI_PIXCLK
rawnand.CE3_B
Alt 2
Yes
Table 85. SD/MMC Boot through USDHC1
1
Ball Name
Signal Name
Mux
Mode
UART1_RTS_B
usdhc1.CD_B
Alt 2
SD1_CLK
usdhc1.CLK
Alt 0
Yes
SD1_CMD
usdhc1.CMD
Alt 0
Yes
SD1_DATA0
usdhc1.DATA0
Alt 0
Yes
SD1_DATA1
usdhc1.DATA1
Alt 0
Yes
Yes
SD1_DATA2
usdhc1.DATA2
Alt 0
Yes
Yes
SD1_DATA3
usdhc1.DATA3
Alt 0
NAND_READY_B
usdhc1.DATA4
Alt 1
Yes
NAND_CE0_B
usdhc1.DATA5
Alt 1
Yes
NAND_CE1_B
usdhc1.DATA6
Alt 1
Yes
NAND_CLE
usdhc1.DATA7
Alt 1
Yes
GPIO1_IO09
GPIO1_IO091
Alt 5
Yes
GPIO1_IO05
usdhc1.VSELECT
Alt 4
Yes
Common
4-bit
8-bit
BOOT_CFG1[1]=1
(SD Power Cycle)
SDMMC
MFG
mode
Yes
Yes
The Boot ROM uses GPIO1_IO09 to implement SD1_RESET_B.
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Boot Mode Configuration
Table 86. SD/MMC Boot through USDHC2
1
Ball Name
Signal Name
Mux Mode
Commo
n
NAND_RE_B
usdhc2.CLK
Alt 1
Yes
NAND_WE_B
usdhc2.CMD
Alt 1
Yes
NAND_DATA00
usdhc2.DATA0
Alt 1
Yes
NAND_DATA01
usdhc2.DATA1
NAND_DATA02
BOOT_CFG1[1]=1
(SD Power Cycle)
4-bit
8-bit
Alt 1
Yes
Yes
usdhc2.DATA2
Alt 1
Yes
Yes
NAND_DATA03
usdhc2.DATA3
Alt 1
NAND_DATA04
usdhc2.DATA4
Alt 1
Yes
NAND_DATA05
usdhc2.DATA5
Alt 1
Yes
NAND_DATA06
usdhc2.DATA6
Alt 1
Yes
NAND_DATA07
usdhc2.DATA7
Alt 1
Yes
NAND_ALE
NAND_ALE1
Alt 5
Yes
GPIO1_IO08
usdhc2.VSELECT
Alt 4
Yes
Yes
The Boot ROM uses NAND_ALE to implement SD2_RESET_B.
Table 87. NOR/OneNAND Boot through EIM
Ball Name
Signal Name
Mux Mode
Common
CSI_DATA00
weim.AD[0]
Alt 4
Yes
CSI_DATA01
weim.AD[1]
Alt 4
Yes
CSI_DATA02
weim.AD[2]
Alt 4
Yes
CSI_DATA03
weim.AD[3]
Alt 4
Yes
CSI_DATA04
weim.AD[4]
Alt 4
Yes
CSI_DATA05
weim.AD[5]
Alt 4
Yes
CSI_DATA06
weim.AD[6]
Alt 4
Yes
CSI_DATA07
weim.AD[7]
Alt 4
Yes
NAND_DATA00
weim.AD[8]
Alt 4
Yes
NAND_DATA01
weim.AD[9]
Alt 4
Yes
NAND_DATA02
weim.AD[10]
Alt 4
Yes
NAND_DATA03
weim.AD[11]
Alt 4
Yes
NAND_DATA04
weim.AD[12]
Alt 4
Yes
NAND_DATA05
weim.AD[13]
Alt 4
Yes
NAND_DATA06
weim.AD[14]
Alt 4
Yes
ADL16
Non-Mux
AD16 Mux
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Table 87. NOR/OneNAND Boot through EIM (continued)
ADL16
Non-Mux
AD16 Mux
Alt 4
Yes
Yes
weim.ADDR[17]
Alt 4
Yes
Yes
NAND_CE1_B
weim.ADDR[18]
Alt 4
Yes
Yes
SD1_CMD
weim.ADDR[19]
Alt 4
Yes
Yes
SD1_CLK
weim.ADDR[20]
Alt 4
Yes
Yes
SD1_DATA0
weim.ADDR[21]
Alt 4
Yes
Yes
SD1_DATA1
weim.ADDR[22]
Alt 4
Yes
Yes
SD1_DATA2
weim.ADDR[23]
Alt 4
Yes
Yes
SD1_DATA3
weim.ADDR[24]
Alt 4
Yes
Yes
ENET2_RXER
weim.ADDR[25]
Alt 4
Yes
Yes
ENET2_CRS_DV
weim.ADDR[26]
Alt 4
Yes
Yes
CSI_MCLK
weim.CS0_B
Alt 4
LCD_DATA08
weim.DATA[0]
Alt 4
Yes
LCD_DATA09
weim.DATA[1]
Alt 4
Yes
LCD_DATA10
weim.DATA[2]
Alt 4
Yes
LCD_DATA11
weim.DATA[3]
Alt 4
Yes
LCD_DATA12
weim.DATA[4]
Alt 4
Yes
LCD_DATA13
weim.DATA[5]
Alt 4
Yes
LCD_DATA14
weim.DATA[6]
Alt 4
Yes
LCD_DATA15
weim.DATA[7]
Alt 4
Yes
LCD_DATA16
weim.DATA[8]
Alt 4
Yes
LCD_DATA17
weim.DATA[9]
Alt 4
Yes
LCD_DATA18
weim.DATA[10]
Alt 4
Yes
LCD_DATA19
weim.DATA[11]
Alt 4
Yes
LCD_DATA20
weim.DATA[12]
Alt 4
Yes
LCD_DATA21
weim.DATA[13]
Alt 4
Yes
LCD_DATA22
weim.DATA[14]
Alt 4
Yes
LCD_DATA23
weim.DATA[15]
Alt 4
Yes
NAND_RE_B
weim.EB_B[0]
Alt 4
Yes
Yes
NAND_WE_B
weim.EB_B[1]
Alt 4
Yes
Yes
CSI_HSYNC
weim.LBA_B
Alt 4
Ball Name
Signal Name
Mux Mode
Common
NAND_DATA07
weim.AD[15]
Alt 4
Yes
NAND_CLE
weim.ADDR[16]
NAND_ALE
Yes
Yes
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Boot Mode Configuration
Table 87. NOR/OneNAND Boot through EIM (continued)
Ball Name
Signal Name
Mux Mode
Common
CSI_PIXCLK
weim.OE
Alt 4
Yes
CSI_VSYNC
weim.RW
Alt 4
Yes
ADL16
Non-Mux
AD16 Mux
Table 88. Serial Download through UART1
Ball Name
Signal Name
Mux Mode
Common
UART1_TX_DATA
uart1.TX_DATA
Alt 0
Yes
UART1_RX_DATA
uart1.RX_DATA
Alt 0
Yes
Table 89. Serial Download through UART2
Ball Name
Signal Name
Mux Mode
Common
UART2_TX_DATA
uart2.TX_DATA
Alt 0
Yes
UART2_RX_DATA
uart2.RX_DATA
Alt 0
Yes
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Package Information and Contact Assignments
6
Package Information and Contact Assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
6.1.1
14 x 14 mm Package Information
14 x 14 mm, 0.8 mm Pitch, Ball Matrix
Figure 70 shows the top, bottom, and side views of the 14 x 14 mm BGA package.
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Package Information and Contact Assignments
Figure 70. 14 x 14 mm BGA, Case x Package Top, Bottom, and Side Views
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Package Information and Contact Assignments
6.1.2
14 x 14 mm Supplies Contact Assignments and Functional Contact
Assignments
Table 90 shows the device connection list for ground, sense, and reference contact signals.
Table 90. 14x14 mm Supplies Contact Assignment
Supply Rail Name
Ball(s) Position(s)
Remark
ADC_VREFH
M13
—
DRAM_VREF
P4
—
GPANIO
R13
—
NGND_KEL0
M12
—
NVCC_CSI
F4
—
NVCC_DRAM
G6, H6, J6, K6, L6, M6
—
NVCC_DRAM_2P5
N6
—
NVCC_ENET
F13
—
NVCC_GPIO
J13
—
NVCC_LCD
E13
—
NVCC_NAND
E7
—
NVCC_PLL
P13
—
NVCC_SD1
C4
—
NVCC_UART
H13
—
VDD_ARM_CAP
G9, G10, G11, H11
—
VDD_HIGH_CAP
R14, R15
—
VDD_HIGH_IN
N13
—
VDD_SNVS_CAP
N12
—
VDD_SNVS_IN
P12
—
VDD_SOC_CAP
G8, H8, J8, J11, K8, K11, L8, L9, L10, L11
—
VDD_SOC_IN
H9, H10, J9, J10, K9, 10
—
VDD_USB_CAP
R12
—
VDDA_ADC_3P3
L13
—
VSS
A1, A17, C3, C7, C11, C15, E8, E11, F6, F7, F8, F9, F10,F11, F12, G3, G5, G7,
G12, G15, H7, H12, J5, J7, J12, K7, K12, L3, L7, L12, M7, M8, M9, M10, M11,
N3, N5, R3, R5, R7, R11, R16, R17, T14, U1, U14, U17
—
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Package Information and Contact Assignments
Table 91 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package.
Table 91. 14 x 14 mm Functional Contact Assignments
Out of Reset Condition
14x14
Ball
Power
Group
Ball
Type
BOOT_MODE0
T10
VDD_SNVS_IN
BOOT_MODE1
U10
CCM_CLK1_N
Ball Name
Default
Mode
Default
Function
Input/
Output
GPIO
ALT5
GPIO5_IO10
Input
100 k
pull-down
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO11
Input
100 k
pull-down
P16
VDD_HIGH_CAP
CCM
—
CCM_CLK1_N
—
—
CCM_CLK1_P
P17
VDD_HIGH_CAP
CCM
—
CCM_CLK1_P
—
—
CCM_PMIC_STBY_REQ
U9
VDD_SNVS_IN
CCM
ALT0
CCM_PMIC_VSTBY_REQ
Output
—
CSI_DATA00
E4
NVCC_CSI
GPIO
ALT5
GPIO4_IO21
Input
Keeper
CSI_DATA01
E3
NVCC_CSI
GPIO
ALT5
GPIO4_IO22
Input
Keeper
CSI_DATA02
E2
NVCC_CSI
GPIO
ALT5
GPIO4_IO23
Input
Keeper
CSI_DATA03
E1
NVCC_CSI
GPIO
ALT5
GPIO4_IO24
Input
Keeper
CSI_DATA04
D4
NVCC_CSI
GPIO
ALT5
GPIO4_IO25
Input
Keeper
CSI_DATA05
D3
NVCC_CSI
GPIO
ALT5
GPIO4_IO26
Input
Keeper
CSI_DATA06
D2
NVCC_CSI
GPIO
ALT5
GPIO4_IO27
Input
Keeper
CSI_DATA07
D1
NVCC_CSI
GPIO
ALT5
GPIO4_IO28
Input
Keeper
CSI_HSYNC
F3
NVCC_CSI
GPIO
ALT5
GPIO4_IO20
Input
Keeper
CSI_MCLK
F5
NVCC_CSI
GPIO
ALT5
GPIO4_IO17
Input
Keeper
CSI_PIXCLK
E5
NVCC_CSI
GPIO
ALT5
GPIO4_IO18
Input
Keeper
CSI_VSYNC
F2
NVCC_CSI
GPIO
ALT5
GPIO4_IO19
Input
Keeper
DRAM_ADDR00
L5
NVCC_DRAM
MMDC
ALT0
DRAM_ADDR00
Output
100 k
pull-up
DRAM_ADDR01
H2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR01
Output
100 k
pull-up
DRAM_ADDR02
K1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR02
Output
100 k
pull-up
DRAM_ADDR03
M2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR03
Output
100 k
pull-up
DRAM_ADDR04
K4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR04
Output
100 k
pull-up
DRAM_ADDR05
L1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR05
Output
100 k
pull-up
DRAM_ADDR06
G2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR06
Output
100 k
pull-up
Value
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Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
DRAM_ADDR07
H4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR07
Output
100 k
pull-up
DRAM_ADDR08
J4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR08
Output
100 k
pull-up
DRAM_ADDR09
L2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR09
Output
100 k
pull-up
DRAM_ADDR10
M4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR10
Output
100 k
pull-up
DRAM_ADDR11
K3
NVCC_DRAM
DDR
ALT0
DRAM_ADDR11
Output
100 k
pull-up
DRAM_ADDR12
L4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR12
Output
100 k
pull-up
DRAM_ADDR13
H3
NVCC_DRAM
DDR
ALT0
DRAM_ADDR13
Output
100 k
pull-up
DRAM_ADDR14
G1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR14
Output
100 k
pull-up
DRAM_ADDR15
K5
NVCC_DRAM
DDR
ALT0
DRAM_ADDR15
Output
100 k
pull-up
DRAM_CAS_B
J2
NVCC_DRAM
DDR
ALT0
DRAM_CAS_B
Output
100 k
pull-up
DRAM_CS0_B
N2
NVCC_DRAM
DDR
ALT0
DRAM_CS0_B
Output
100 k
pull-up
DRAM_CS1_B
H5
NVCC_DRAM
DDR
ALT0
DRAM_CS1_B
Output
100 k
pull-up
DRAM_DATA00
T4
NVCC_DRAM
DDR
ALT0
DRAM_DATA00
Input
100 k
pull-up
DRAM_DATA01
U6
NVCC_DRAM
DDR
ALT0
DRAM_DATA01
Input
100 k
pull-up
DRAM_DATA02
T6
NVCC_DRAM
DDR
ALT0
DRAM_DATA02
Input
100 k
pull-up
DRAM_DATA03
U7
NVCC_DRAM
DDR
ALT0
DRAM_DATA03
Input
100 k
pull-up
DRAM_DATA04
U8
NVCC_DRAM
DDR
ALT0
DRAM_DATA04
Input
100 k
pull-up
DRAM_DATA05
T8
NVCC_DRAM
DDR
ALT0
DRAM_DATA05
Input
100 k
pull-up
DRAM_DATA06
T5
NVCC_DRAM
DDR
ALT0
DRAM_DATA06
Input
100 k
pull-up
DRAM_DATA07
U4
NVCC_DRAM
DDR
ALT0
DRAM_DATA07
Input
100 k
pull-up
DRAM_DATA08
U2
NVCC_DRAM
DDR
ALT0
DRAM_DATA08
Input
100 k
pull-up
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Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
DRAM_DATA09
U3
NVCC_DRAM
DDR
ALT0
DRAM_DATA09
Input
100 k
pull-up
DRAM_DATA10
U5
NVCC_DRAM
DDR
ALT0
DRAM_DATA10
Input
100 k
pull-up
DRAM_DATA11
R4
NVCC_DRAM
DDR
ALT0
DRAM_DATA11
Input
100 k
pull-up
DRAM_DATA12
P5
NVCC_DRAM
DDR
ALT0
DRAM_DATA12
Input
100 k
pull-up
DRAM_DATA13
P3
NVCC_DRAM
DDR
ALT0
DRAM_DATA13
Input
100 k
pull-up
DRAM_DATA14
R2
NVCC_DRAM
DDR
ALT0
DRAM_DATA14
Input
100 k
pull-up
DRAM_DATA15
R1
NVCC_DRAM
DDR
ALT0
DRAM_DATA15
Input
100 k
pull-up
DRAM_DQM0
T7
NVCC_DRAM
DDR
ALT0
DRAM_DQM0
Output
100 k
pull-up
DRAM_DQM1
T3
NVCC_DRAM
DDR
ALT0
DRAM_DQM1
Output
100 k
pull-up
DRAM_ODT0
N1
NVCC_DRAM
DDR
ALT0
DRAM_ODT0
Output
100 k
pull-down
DRAM_ODT1
F1
NVCC_DRAM
DDR
ALT0
DRAM_ODT1
Output
100 k
pull-down
DRAM_RAS_B
M5
NVCC_DRAM
DDR
ALT0
DRAM_RAS_B
Output
100 k
pull-up
DRAM_RESET
G4
NVCC_DRAM
DDR
ALT0
DRAM_RESET
Output
100 k
pull-down
DRAM_SDBA0
M1
NVCC_DRAM
DDR
ALT0
DRAM_SDBA0
Output
100 k
pull-up
DRAM_SDBA1
H1
NVCC_DRAM
DDR
ALT0
DRAM_SDBA1
Output
100 k
pull-up
DRAM_SDBA2
K2
NVCC_DRAM
DDR
ALT0
DRAM_SDBA2
Output
100 k
pull-up
DRAM_SDCKE0
M3
NVCC_DRAM
DDR
ALT0
DRAM_SDCKE0
Output
100 k
pull-down
DRAM_SDCKE1
J3
NVCC_DRAM
DDR
ALT0
DRAM_SDCKE1
Output
100 k
pull-down
DRAM_SDCLK0_N
P2
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDCLK0_N
Input
100 k
pull-up
DRAM_SDCLK0_P
P1
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDCLK0_P
Input
100 k
pull-up
DRAM_SDQS0_N
P7
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDQS0_N
Input
100 k
pull-down
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Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
DRAM_SDQS0_P
P6
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDQS0_P
Input
100 k
pull-down
DRAM_SDQS1_N
T2
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDQS1_N
Input
100 k
pull-down
DRAM_SDQS1_P
T1
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDQS1_P
Input
100 k
pull-down
DRAM_SDWE_B
J1
NVCC_DRAM
DDR
ALT0
DRAM_SDWE_B
Output
100 k
pull-up
DRAM_ZQPAD
N4
NVCC_DRAM
GPIO
—
DRAM_ZQPAD
Input
Keeper
ENET1_RX_DATA0
F16
NVCC_ENET
GPIO
ALT5
GPIO2_IO0
Input
Keeper
ENET1_RX_DATA1
E17
NVCC_ENET
GPIO
ALT5
GPIO2_IO1
Input
Keeper
ENET1_RX_EN
E16
NVCC_ENET
GPIO
ALT5
GPIO2_IO2
Input
Keeper
ENET1_RX_ER
D15
NVCC_ENET
GPIO
ALT5
GPIO2_IO7
Input
Keeper
ENET1_TX_CLK
F14
NVCC_ENET
GPIO
ALT5
GPIO2_IO6
Input
Keeper
ENET1_TX_DATA0
E15
NVCC_ENET
GPIO
ALT5
GPIO2_IO3
Input
Keeper
ENET1_TX_DATA1
E14
NVCC_ENET
GPIO
ALT5
GPIO2_IO4
Input
Keeper
ENET1_TX_EN
F15
NVCC_ENET
GPIO
ALT5
GPIO2_IO5
Input
Keeper
ENET2_RX_DATA0
C17
NVCC_ENET
GPIO
ALT5
GPIO2_IO8
Input
Keeper
ENET2_RX_DATA1
C16
NVCC_ENET
GPIO
ALT5
GPIO2_IO9
Input
Keeper
ENET2_RX_EN
B17
NVCC_ENET
GPIO
ALT5
GPIO2_IO10
Input
Keeper
ENET2_RX_ER
D16
NVCC_ENET
GPIO
ALT5
GPIO2_IO15
Input
Keeper
ENET2_TX_CLK
D17
NVCC_ENET
GPIO
ALT5
GPIO2_IO14
Input
Keeper
ENET2_TX_DATA0
A15
NVCC_ENET
GPIO
ALT5
GPIO2_IO11
Input
Keeper
ENET2_TX_DATA1
A16
NVCC_ENET
GPIO
ALT5
GPIO2_IO12
Input
Keeper
ENET2_TX_EN
B15
NVCC_ENET
GPIO
ALT5
GPIO2_IO13
Input
Keeper
GPIO1_IO00
K13
NVCC_GPIO
GPIO
ALT5
GPIO1_IO00
Input
Keeper
GPIO1_IO01
L15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO01
Input
Keeper
GPIO1_IO02
L14
NVCC_GPIO
GPIO
ALT5
GPIO1_IO02
Input
Keeper
GPIO1_IO03
L17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO03
Input
Keeper
GPIO1_IO04
M16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO04
Input
Keeper
GPIO1_IO05
M17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO05
Input
Keeper
GPIO1_IO06
K17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO06
Input
Keeper
GPIO1_IO07
L16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO07
Input
Keeper
GPIO1_IO08
N17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO08
Input
Keeper
GPIO1_IO09
M15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO09
Input
Keeper
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
117
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
JTAG_MOD
P15
NVCC_GPIO
SJC
ALT0
SJC_MOD
Input
100 k
pull-up
JTAG_TCK
M14
NVCC_GPIO
SJC
ALT0
SJC_TCK
Input
47 k
pull-up
JTAG_TDI
N16
NVCC_GPIO
SJC
ALT0
SJC_TDI
Input
47 k
pull-up
JTAG_TDO
N15
NVCC_GPIO
SJC
ALT0
SJC_TDO
Output
Keeper
JTAG_TMS
P14
NVCC_GPIO
SJC
ALT0
SJC_TMS
Input
47 k
pull-up
JTAG_TRST_B
N14
NVCC_GPIO
SJC
ALT0
SJC_TRSTB
Input
47 k
pull-up
LCD_CLK
A8
NVCC_LCD
GPIO
ALT5
GPIO3_IO0
Input
Keeper
LCD_DATA00
B9
NVCC_LCD
GPIO
ALT5
GPIO3_IO5
Input
Keeper
LCD_DATA01
A9
NVCC_LCD
GPIO
ALT5
GPIO3_IO6
Input
Keeper
LCD_DATA02
E10
NVCC_LCD
GPIO
ALT5
GPIO3_IO7
Input
Keeper
LCD_DATA03
D10
NVCC_LCD
GPIO
ALT5
GPIO3_IO8
Input
Keeper
LCD_DATA04
C10
NVCC_LCD
GPIO
ALT5
GPIO3_IO9
Input
Keeper
LCD_DATA05
B10
NVCC_LCD
GPIO
ALT5
GPIO3_IO10
Input
Keeper
LCD_DATA06
A10
NVCC_LCD
GPIO
ALT5
GPIO3_IO11
Input
Keeper
LCD_DATA07
D11
NVCC_LCD
GPIO
ALT5
GPIO3_IO12
Input
Keeper
LCD_DATA08
B11
NVCC_LCD
GPIO
ALT5
GPIO3_IO13
Input
Keeper
LCD_DATA09
A11
NVCC_LCD
GPIO
ALT5
GPIO3_IO14
Input
Keeper
LCD_DATA10
E12
NVCC_LCD
GPIO
ALT5
GPIO3_IO15
Input
Keeper
LCD_DATA11
D12
NVCC_LCD
GPIO
ALT5
GPIO3_IO16
Input
Keeper
LCD_DATA12
C12
NVCC_LCD
GPIO
ALT5
GPIO3_IO17
Input
Keeper
LCD_DATA13
B12
NVCC_LCD
GPIO
ALT5
GPIO3_IO18
Input
Keeper
LCD_DATA14
A12
NVCC_LCD
GPIO
ALT5
GPIO3_IO19
Input
Keeper
LCD_DATA15
D13
NVCC_LCD
GPIO
ALT5
GPIO3_IO20
Input
Keeper
LCD_DATA16
C13
NVCC_LCD
GPIO
ALT5
GPIO3_IO21
Input
Keeper
LCD_DATA17
B13
NVCC_LCD
GPIO
ALT5
GPIO3_IO22
Input
Keeper
LCD_DATA18
A13
NVCC_LCD
GPIO
ALT5
GPIO3_IO23
Input
Keeper
LCD_DATA19
D14
NVCC_LCD
GPIO
ALT5
GPIO3_IO24
Input
Keeper
LCD_DATA20
C14
NVCC_LCD
GPIO
ALT5
GPIO3_IO25
Input
Keeper
LCD_DATA21
B14
NVCC_LCD
GPIO
ALT5
GPIO3_IO26
Input
Keeper
LCD_DATA22
A14
NVCC_LCD
GPIO
ALT5
GPIO3_IO27
Input
Keeper
LCD_DATA23
B16
NVCC_LCD
GPIO
ALT5
GPIO3_IO28
Input
Keeper
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
118
NXP Semiconductors
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
LCD_ENABLE
B8
NVCC_LCD
GPIO
ALT5
GPIO3_IO1
Input
Keeper
LCD_HSYNC
D9
NVCC_LCD
GPIO
ALT5
GPIO3_IO2
Input
Keeper
LCD_RESET
E9
NVCC_LCD
GPIO
ALT5
GPIO3_IO4
Input
Keeper
LCD_VSYNC
C9
NVCC_LCD
GPIO
ALT5
GPIO3_IO3
Input
Keeper
NAND_ALE
B4
NVCC_NAND
GPIO
ALT5
GPIO4_IO10
Input
Keeper
NAND_CE0_B
C5
NVCC_NAND
GPIO
ALT5
GPIO4_IO13
Input
Keeper
NAND_CE1_B
B5
NVCC_NAND
GPIO
ALT5
GPIO4_IO14
Input
Keeper
NAND_CLE
A4
NVCC_NAND
GPIO
ALT5
GPIO4_IO15
Input
Keeper
NAND_DATA00
D7
NVCC_NAND
GPIO
ALT5
GPIO4_IO2
Input
Keeper
NAND_DATA01
B7
NVCC_NAND
GPIO
ALT5
GPIO4_IO3
Input
Keeper
NAND_DATA02
A7
NVCC_NAND
GPIO
ALT5
GPIO4_IO4
Input
Keeper
NAND_DATA03
D6
NVCC_NAND
GPIO
ALT5
GPIO4_IO5
Input
Keeper
NAND_DATA04
C6
NVCC_NAND
GPIO
ALT5
GPIO4_IO6
Input
Keeper
NAND_DATA05
B6
NVCC_NAND
GPIO
ALT5
GPIO4_IO7
Input
Keeper
NAND_DATA06
A6
NVCC_NAND
GPIO
ALT5
GPIO4_IO8
Input
Keeper
NAND_DATA07
A5
NVCC_NAND
GPIO
ALT5
GPIO4_IO9
Input
Keeper
NAND_DQS
E6
NVCC_NAND
GPIO
ALT5
GPIO4_IO16
Input
Keeper
NAND_RE_B
D8
NVCC_NAND
GPIO
ALT5
GPIO4_IO0
Input
Keeper
NAND_READY_B
A3
NVCC_NAND
GPIO
ALT5
GPIO4_IO12
Input
Keeper
NAND_WE_B
C8
NVCC_NAND
GPIO
ALT5
GPIO4_IO1
Input
Keeper
NAND_WP_B
D5
NVCC_NAND
GPIO
ALT5
GPIO4_IO11
Input
Keeper
ONOFF
R8
VDD_SNVS_IN
SRC
ALT0
SRC_RESET_B
Input
100 k
pull-up
POR_B
P8
VDD_SNVS_IN
SRC
ALT0
SRC_POR_B
Input
100 k
pull-up
RTC_XTALI
T11
VDD_SNVS_CAP ANALO
G
—
RTC_XTALI
—
—
RTC_XTALO
U11
VDD_SNVS_CAP ANALO
G
—
RTC_XTALO
—
—
SD1_CLK
C1
NVCC_SD
GPIO
ALT5
GPIO2_IO17
Input
Keeper
SD1_CMD
C2
NVCC_SD
GPIO
ALT5
GPIO2_IO16
Input
Keeper
SD1_DATA0
B3
NVCC_SD
GPIO
ALT5
GPIO2_IO18
Input
Keeper
SD1_DATA1
B2
NVCC_SD
GPIO
ALT5
GPIO2_IO19
Input
Keeper
SD1_DATA2
B1
NVCC_SD
GPIO
ALT5
GPIO2_IO20
Input
Keeper
SD1_DATA3
A2
NVCC_SD
GPIO
ALT5
GPIO2_IO21
Input
Keeper
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
119
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
SNVS_PMIC_ON_REQ
T9
VDD_SNVS_IN
GPIO
ALT0
SNVS_PMIC_ON_REQ
Output
100 k
pull-up
SNVS_TAMPER0
R10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO00/SNVS_TAMPE
R01
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER1
R9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO01/SNVS_TAMPE
R11
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER2
P11
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO02/SNVS_TAMPE
R21
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER3
P10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO03/SNVS_TAMPE
R31
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER4
P9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO04/SNVS_TAMPE
R41
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER5
N8
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO05/SNVS_TAMPE
R51
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER6
N11
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO06/SNVS_TAMPE
R61
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER7
N10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO07/SNVS_TAMPE
R71
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER8
N9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO08/SNVS_TAMPE
R81
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER9
R6
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO09/SNVS_TAMPE
R91
Input
Keeper/N
ot
connecte
d1,2
TEST_MODE
N7
VDD_SNVS_IN
TCU
ALT0
TCU_TEST_MODE
Input
Keeper
UART1_CTS_B
K15
NVCC_UART
GPIO
ALT5
GPIO1_IO18
Input
Keeper
UART1_RTS_B
J14
NVCC_UART
GPIO
ALT5
GPIO1_IO19
Input
Keeper
UART1_RX_DATA
K16
NVCC_UART
GPIO
ALT5
GPIO1_IO17
Input
Keeper
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
120
NXP Semiconductors
Package Information and Contact Assignments
Table 91. 14 x 14 mm Functional Contact Assignments (continued)
UART1_TX_DATA
K14
NVCC_UART
GPIO
ALT5
GPIO1_IO16
Input
Keeper
UART2_CTS_B
J15
NVCC_UART
GPIO
ALT5
GPIO1_IO22
Input
Keeper
UART2_RTS_B
H14
NVCC_UART
GPIO
ALT5
GPIO1_IO23
Input
Keeper
UART2_RX_DATA
J16
NVCC_UART
GPIO
ALT5
GPIO1_IO21
Input
Keeper
UART2_TX_DATA
J17
NVCC_UART
GPIO
ALT5
GPIO1_IO20
Input
Keeper
UART3_CTS_B
H15
NVCC_UART
GPIO
ALT5
GPIO1_IO26
Input
Keeper
UART3_RTS_B
G14
NVCC_UART
GPIO
ALT5
GPIO1_IO27
Input
Keeper
UART3_RX_DATA
H16
NVCC_UART
GPIO
ALT5
GPIO1_IO25
Input
Keeper
UART3_TX_DATA
H17
NVCC_UART
GPIO
ALT5
GPIO1_IO24
Input
Keeper
UART4_RX_DATA
G16
NVCC_UART
GPIO
ALT5
GPIO1_IO29
Input
Keeper
UART4_TX_DATA
G17
NVCC_UART
GPIO
ALT5
GPIO1_IO28
Input
Keeper
UART5_RX_DATA
G13
NVCC_UART
GPIO
ALT5
GPIO1_IO31
Input
Keeper
UART5_TX_DATA
F17
NVCC_UART
GPIO
ALT5
GPIO1_IO30
Input
Keeper
USB_OTG1_CHD_B
U16
OPEN DRAIN
GPIO
—
USB_OTG1_CHD_B
—
—
USB_OTG1_DN
T15
VDD_USB_CAP
ANALO
G
—
USB_OTG1_DN
—
—
USB_OTG1_DP
U15
VDD_USB_CAP
ANALO
G
—
USB_OTG1_DP
—
—
USB_OTG1_VBUS
T12
USB_VBUS
VBUS
POWE
R
—
USB_OTG1_VBUS
—
—
USB_OTG2_DN
T13
VDD_USB_CAP
ANALO
G
—
USB_OTG2_DN
—
—
USB_OTG2_DP
U13
VDD_USB_CAP
ANALO
G
—
USB_OTG2_DP
—
—
USB_OTG2_VBUS
U12
USB_VBUS
VBUS
POWE
R
—
USB_OTG2_VBUS
—
—
XTALI
T16
NVCC_PLL
ANALO
G
—
XTALI
—
—
XTALO
T17
NVCC_PLL
ANALO
G
—
XTALO
—
—
1
SNVS_TAMPER0 to SNVS_TAMPER9 can be configured as GPIO or tamper detection pin, it is depending on the fuse setting
TAMPER_PIN_DISABLE[1:0]. When the pad is configured as GPIO, the value is keeper out of reset.
2 SNVS_TAMPER0 to SNVS_TAMPER9 is input unconnected in the following conditions.
—SNVS low power mode when configured as GPIO
—Tamper functions are not used when configured as TAMPER detection pins
It is required to connect external 1M Ohm pull-up or pull-down resistors to the pad to avoid the undesired leakage under two
conditions above.
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
121
122
5
6
7
8
9
10
11
12
13
14
NAND_CLE
NAND_DATA07
NAND_DATA06
NAND_DATA02
LCD_CLK
LCD_DATA01
LCD_DATA06
LCD_DATA09
LCD_DATA14
LCD_DATA18
LCD_DATA22
NAND_ALE
NAND_CE1_B
NAND_DATA05
NAND_DATA01
LCD_ENABLE
LCD_DATA00
LCD_DATA05
LCD_DATA08
LCD_DATA13
LCD_DATA17
LCD_DATA21
NVCC_SD1
NAND_CE0_B
NAND_DATA04
VSS
NAND_WE_B
LCD_VSYNC
LCD_DATA04
VSS
LCD_DATA12
LCD_DATA16
LCD_DATA20
CSI_DATA04
NAND_WP_B
NAND_DATA03
NAND_DATA00
NAND_RE_B
LCD_HSYNC
LCD_DATA03
LCD_DATA07
LCD_DATA11
LCD_DATA15
LCD_DATA19
CSI_DATA00
CSI_PIXCLK
NAND_DQS
NVCC_NAND
VSS
LCD_RESET
LCD_DATA02
VSS
LCD_DATA10
NVCC_LCD
ENET1_TX_DATA1
ENET1_TX_DATA0 ENET1_RX_ER
NVCC_CSI
CSI_MCLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NVCC_ENET
ENET1_TX_CLK
ENET1_TX_EN
DRAM_RESET
VSS
NVCC_DRAM
VSS
VDD_SOC_CAP
VDD_ARM_CAP
VDD_ARM_CAP
VDD_ARM_CAP
VSS
UART5_RX_DATA
UART3_RTS_B
VSS
G
UART4_TX_DATA
F
UART5_TX_DATA
ENET2_RX_ER ENET2_RX_DATA1
LCD_DATA23
E
D
C
B
ENET1_RX_DATA1 ENET2_TX_CLK ENET2_RX_DATA0 ENET2_RX_EN
ENET1_RX_EN
4
NAND_READY_B
SD1_DATA0
VSS
CSI_DATA05
CSI_DATA01
CSI_HSYNC
VSS
UART4_RX_DATA ENET1_RX_DATA0
3
SD1_DATA3
SD1_DATA1
SD1_CMD
CSI_DATA06
CSI_DATA02
CSI_VSYNC
DRAM_ADDR06
A
VSS
17
ENET2_TX_DATA1 16
ENET2_TX_EN ENET2_TX_DATA0 15
2
VSS
SD1_DATA2
SD1_CLK
CSI_DATA07
CSI_DATA03
DRAM_ODT1
DRAM_ADDR14
VSS
1
A
B
C
D
E
F
6.1.3
G
Package Information and Contact Assignments
14 x 14 mm, 0.8 mm Pitch, Ball Map
Table 92 shows the 14 x 14 mm, 0.8 mm pitch ball map for the i.MX 6ULL.
Table 92. 14 x 14 mm, 0.8 mm Pitch, Ball Map
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
NXP Semiconductors
DRAM_ADDR13
DRAM_ADDR07
DRAM_CS1_B
NVCC_DRAM
DRAM_SDCKE1
DRAM_ADDR08
VSS
NVCC_DRAM
DRAM_ADDR11
DRAM_ADDR04
DRAM_ADDR15
NVCC_DRAM
DRAM_ADDR10 DRAM_ADDR12
DRAM_ADDR00
NVCC_DRAM
DRAM_RAS_B
NVCC_DRAM
VSS
DRAM_ZQPAD
VSS
DRAM_DATA13
DRAM_VREF
DRAM_DATA12
VDD_SOC_IN
VDD_SOC_IN
VDD_ARM_CAP
VSS
NVCC_UART
UART2_RTS_B
UART3_CTS_B
VDD_SOC_IN
VDD_SOC_IN
VDD_SOC_CAP
VSS
NVCC_GPIO
UART1_RTS_B
UART2_CTS_B
VDD_SOC_IN
VDD_SOC_CAP
VSS
GPIO1_IO00
UART1_TX_DATA
UART1_CTS_B
UART1_RX_DATA UART2_RX_DATA UART3_RX_DATA
UART2_TX_DATA UART3_TX_DATA
VDD_SOC_IN
GPIO1_IO06
K
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VSS
VDDA_ADC_3P3
GPIO1_IO02
GPIO1_IO01
GPIO1_IO07
GPIO1_IO03
L
VSS
VSS
VSS
NGND_KEL0
ADC_VREFH
JTAG_TCK
GPIO1_IO09
GPIO1_IO04
GPIO1_IO05
M
SNVS_TAMPER8
SNVS_TAMPER7
SNVS_TAMPER6
VDD_SNVS_CAP
VDD_HIGH_IN
JTAG_TRST_B
JTAG_TDO
JTAG_TDI
GPIO1_IO08
N
SNVS_TAMPER4
SNVS_TAMPER3
SNVS_TAMPER2
VDD_SNVS_IN
NVCC_PLL
JTAG_TMS
JTAG_MOD
CCM_CLK1_N
CCM_CLK1_P
P
H
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VSS
SNVS_TAMPER5
POR_B
J
VSS
VSS
VSS
VSS
VSS
TEST_MODE
DRAM_SDQS0_N
DRAM_SDQS0_P NVCC_DRAM_2P5
DRAM_ADDR01
DRAM_CAS_B
DRAM_SDBA2
DRAM_ADDR03 DRAM_ADDR09
DRAM_CS0_B
DRAM_SDCLK0_N
VSS
DRAM_SDBA1
DRAM_SDWE_B
DRAM_ADDR02
DRAM_ADDR05
DRAM_SDBA0
DRAM_ODT0
DRAM_SDCLK0_P
DRAM_SDCKE0
H
J
K
L
M
N
P
Package Information and Contact Assignments
Table 92. 14 x 14 mm, 0.8 mm Pitch, Ball Map (continued)
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
123
6.2
6.2.1
124
DRAM_DATA15
DRAM_DATA14
VSS
DRAM_DATA11
VSS
SNVS_TAMPER9
VSS
ONOFF
DRAM_SDQS1_P
DRAM_SDQS1_N
DRAM_DQM1
DRAM_DATA00
DRAM_DATA06
DRAM_DATA02
DRAM_DQM0
DRAM_DATA05
VSS
DRAM_DATA08
DRAM_DATA09
DRAM_DATA07
DRAM_DATA10
DRAM_DATA01
DRAM_DATA03
DRAM_DATA04
1
2
3
4
5
6
7
8
GPANAIO
VDD_HIGH_CAP
VDD_HIGH_CAP
VSS
VSS
USB_OTG2_DN
VSS
USB_OTG1_DN
XTALI
XTALO
USB_OTG2_DP
VSS
USB_OTG1_DP
USB_OTG1_CHD_B
VSS
13
14
15
16
17
R
VDD_USB_CAP
USB_OTG1_VBUS
USB_OTG2_VBUS
12
T
VSS
RTC_XTALI
RTC_XTALO
11
U
SNVS_TAMPER0
BOOT_MODE0
BOOT_MODE1
10
9 CCM_PMIC_STBY_REQ SNVS_PMIC_ON_REQ SNVS_TAMPER1
R
T
U
Package Information and Contact Assignments
Table 92. 14 x 14 mm, 0.8 mm Pitch, Ball Map (continued)
9 x 9 mm Package Information
9 x 9 mm, 0.5 mm Pitch, Ball Matrix
Figure 71 shows the top, bottom, and side views of the 9 x 9 mm BGA package.
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
Package Information and Contact Assignments
Figure 71. 9 x 9 mm BGA, Case x Package Top, Bottom, and Side Views
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
125
Package Information and Contact Assignments
6.2.2
9 x 9 mm Supplies Contact Assignments and Functional Contact
Assignments
Table 93 shows the device connection list for ground, sense, and reference contact signals.
Table 93. 9 x 9 mm Supplies Contact Assignment
Supply Rail Name
Ball(s) Position(s)
Remark
ADC_VREFH
N13
—
DRAM_VREF
T1
—
GPANAIO
T11
—
NGND_KEL0
M10
—
NVCC_CSI
E5
—
NVCC_DRAM
G5, L5, M5, N6
—
NVCC_DRAM_2P5
K6
—
NVCC_ENET
G13
—
NVCC_GPIO
M13
—
NVCC_LCD
E13
—
NVCC_NAND
E11
—
NVCC_PLL
T13
—
NVCC_SD1
E7
—
NVCC_UART
L13
—
VDD_ARM_CAP
G9, G10, G11, H9, H10, H11
—
VDD_HIGH_CAP
U11
—
VDD_HIGH_IN
U15
—
VDD_SNVS_CAP
N12
—
VDD_SNVS_IN
P12
—
VDD_SOC_CAP
G7, G8, H7, H8, J7, J8, K7, K8, L7, L8
—
VDD_SOC_IN
J9, J10, J11, K9, K10, K11, L9, L10, L11
—
VDD_USB_CAP
N11
—
VDDA_ADC_3P3
T17
—
VSS
A2, A7, A12, A17, B1, C15, F1, F3, F8, F10, F17, H6, H12, J3, J15, K12, M1, M3,
M8, M17, R3, R9, R12, R15, U1, U6, U13, U17
—
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126
NXP Semiconductors
Package Information and Contact Assignments
Table 94 shows an alpha-sorted list of functional contact assignments for the 9 x 9 mm package.
Table 94. 9 x 9 mm Functional Contact Assignments
Out of Reset Condition
9x9
Ball
Power
Group
Ball
Type
BOOT_MODE0
T8
VDD_SNVS_IN
BOOT_MODE1
U8
CCM_CLK1_N
Ball Name
Default
Mode
Default
Function
Input/
Output
GPIO
ALT5
GPIO5_IO10
Input
100 k
pull-down
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO11
Input
100 k
pull-down
U16
VDD_HIGH_CAP
LVDS
—
CCM_CLK1_N
—
—
CCM_CLK1_P
T16
VDD_HIGH_CAP
LVDS
—
CCM_CLK1_P
—
—
CCM_PMIC_STBY_REQ
U7
VDD_SNVS_IN
GPIO
ALT0
CCM_PMIC_VSTBY_REQ
Output
—
CSI_DATA00
C3
NVCC_CSI
GPIO
ALT5
GPIO4_IO21
Input
Keeper
CSI_DATA01
D4
NVCC_CSI
GPIO
ALT5
GPIO4_IO22
Input
Keeper
CSI_DATA02
B2
NVCC_CSI
GPIO
ALT5
GPIO4_IO23
Input
Keeper
CSI_DATA03
D1
NVCC_CSI
GPIO
ALT5
GPIO4_IO24
Input
Keeper
CSI_DATA04
C4
NVCC_CSI
GPIO
ALT5
GPIO4_IO25
Input
Keeper
CSI_DATA05
B3
NVCC_CSI
GPIO
ALT5
GPIO4_IO26
Input
Keeper
CSI_DATA06
A3
NVCC_CSI
GPIO
ALT5
GPIO4_IO27
Input
Keeper
CSI_DATA07
C2
NVCC_CSI
GPIO
ALT5
GPIO4_IO28
Input
Keeper
CSI_HSYNC
D2
NVCC_CSI
GPIO
ALT5
GPIO4_IO20
Input
Keeper
CSI_MCLK
C1
NVCC_CSI
GPIO
ALT5
GPIO4_IO17
Input
Keeper
CSI_PIXCLK
D5
NVCC_CSI
GPIO
ALT5
GPIO4_IO18
Input
Keeper
CSI_VSYNC
D3
NVCC_CSI
GPIO
ALT5
GPIO4_IO19
Input
Keeper
DRAM_ADDR00
G1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR00
Output
100 k
pull-up
DRAM_ADDR01
G2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR01
Output
100 k
pull-up
DRAM_ADDR02
H1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR02
Output
100 k
pull-up
DRAM_ADDR03
J2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR03
Output
100 k
pull-up
DRAM_ADDR04
M4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR04
Output
100 k
pull-up
DRAM_ADDR05
H2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR05
Output
100 k
pull-up
DRAM_ADDR06
E4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR06
Output
100 k
pull-up
Value
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
127
Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
DRAM_ADDR07
J4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR07
Output
100 k
pull-up
DRAM_ADDR08
J5
NVCC_DRAM
DDR
ALT0
DRAM_ADDR08
Output
100 k
pull-up
DRAM_ADDR09
J1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR09
Output
100 k
pull-up
DRAM_ADDR10
M2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR10
Output
100 k
pull-up
DRAM_ADDR11
K5
NVCC_DRAM
DDR
ALT0
DRAM_ADDR11
Output
100 k
pull-up
DRAM_ADDR12
L3
NVCC_DRAM
DDR
ALT0
DRAM_ADDR12
Output
100 k
pull-up
DRAM_ADDR13
H4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR13
Output
100 k
pull-up
DRAM_ADDR14
E3
NVCC_DRAM
DDR
ALT0
DRAM_ADDR14
Output
100 k
pull-up
DRAM_ADDR15
E2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR15
Output
100 k
pull-up
DRAM_CAS_B
G4
NVCC_DRAM
DDR
ALT0
DRAM_CAS_B
Output
100 k
pull-up
DRAM_CS0_B
L1
NVCC_DRAM
DDR
ALT0
DRAM_CS0_B
Output
100 k
pull-up
DRAM_CS1_B
H5
NVCC_DRAM
DDR
ALT0
DRAM_CS1_B
Output
100 k
pull-up
DRAM_DATA00
T3
NVCC_DRAM
DDR
ALT0
DRAM_DATA00
Input
100 k
pull-up
DRAM_DATA01
N5
NVCC_DRAM
DDR
ALT0
DRAM_DATA01
Input
100 k
pull-up
DRAM_DATA02
T4
NVCC_DRAM
DDR
ALT0
DRAM_DATA02
Input
100 k
pull-up
DRAM_DATA03
T5
NVCC_DRAM
DDR
ALT0
DRAM_DATA03
Input
100 k
pull-up
DRAM_DATA04
U5
NVCC_DRAM
DDR
ALT0
DRAM_DATA04
Input
100 k
pull-up
DRAM_DATA05
T6
NVCC_DRAM
DDR
ALT0
DRAM_DATA05
Input
100 k
pull-up
DRAM_DATA06
R4
NVCC_DRAM
DDR
ALT0
DRAM_DATA06
Input
100 k
pull-up
DRAM_DATA07
U3
NVCC_DRAM
DDR
ALT0
DRAM_DATA07
Input
100 k
pull-up
DRAM_DATA08
P1
NVCC_DRAM
DDR
ALT0
DRAM_DATA08
Input
100 k
pull-up
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
128
NXP Semiconductors
Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
DRAM_DATA09
U2
NVCC_DRAM
DDR
ALT0
DRAM_DATA09
Input
100 k
pull-up
DRAM_DATA10
P3
NVCC_DRAM
DDR
ALT0
DRAM_DATA10
Input
100 k
pull-up
DRAM_DATA11
R2
NVCC_DRAM
DDR
ALT0
DRAM_DATA11
Input
100 k
pull-up
DRAM_DATA12
P4
NVCC_DRAM
DDR
ALT0
DRAM_DATA12
Input
100 k
pull-up
DRAM_DATA13
N2
NVCC_DRAM
DDR
ALT0
DRAM_DATA13
Input
100 k
pull-up
DRAM_DATA14
N1
NVCC_DRAM
DDR
ALT0
DRAM_DATA14
Input
100 k
pull-up
DRAM_DATA15
P2
NVCC_DRAM
DDR
ALT0
DRAM_DATA15
Input
100 k
pull-up
DRAM_DQM0
U4
NVCC_DRAM
DDR
ALT0
DRAM_DQM0
Output
100 k
pull-up
DRAM_DQM1
R1
NVCC_DRAM
DDR
ALT0
DRAM_DQM1
Output
100 k
pull-up
DRAM_ODT0
K2
NVCC_DRAM
DDR
ALT0
DRAM_ODT0
Output
100 k
pull-down
DRAM_ODT1
E1
NVCC_DRAM
DDR
ALT0
DRAM_ODT1
Output
100 k
pull-down
DRAM_RAS_B
L4
NVCC_DRAM
DDR
ALT0
DRAM_RAS_B
Output
100 k
pull-up
DRAM_RESET
F2
NVCC_DRAM
DDR
ALT0
DRAM_RESET
Output
100 k
pull-down
DRAM_SDBA0
H3
NVCC_DRAM
DDR
ALT0
DRAM_SDBA0
Output
100 k
pull-up
DRAM_SDBA1
F5
NVCC_DRAM
DDR
ALT0
DRAM_SDBA1
Output
100 k
pull-up
DRAM_SDBA2
G3
NVCC_DRAM
DDR
ALT0
DRAM_SDBA2
Output
100 k
pull-up
DRAM_SDCKE0
L2
NVCC_DRAM
DDR
ALT0
DRAM_SDCKE0
Output
100 k
pull-down
DRAM_SDCKE1
K1
NVCC_DRAM
DDR
ALT0
DRAM_SDCKE1
Output
100 k
pull-down
DRAM_SDCLK0_N
K4
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDCLK0_N
Input
100 k
pull-up
DRAM_SDCLK0_P
K3
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDCLK0_P
Input
100 k
pull-up
DRAM_SDQS0_N
R5
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDQS0_N
Input
100 k
pull-down
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
129
Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
DRAM_SDQS0_P
P5
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDQS0_P
Input
100 k
pull-down
DRAM_SDQS1_N
N4
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDQS1_P
Input
100 k
pull-down
DRAM_SDQS1_P
N3
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDQS1_N
Input
100 k
pull-down
DRAM_SDWE_B
F4
NVCC_DRAM
DDR
ALT0
DRAM_SDWE_B
Output
100 k
pull-up
DRAM_ZQPAD
T2
NVCC_DRAM
GPIO
—
DRAM_ZQPAD
Input
Keeper
ENET1_RX_DATA0
G17
NVCC_ENET
GPIO
ALT5
GPIO2_IO0
Input
Keeper
ENET1_RX_DATA1
F16
NVCC_ENET
GPIO
ALT5
GPIO2_IO1
Input
Keeper
ENET1_RX_EN
G16
NVCC_ENET
GPIO
ALT5
GPIO2_IO2
Input
Keeper
ENET1_RX_ER
G14
NVCC_ENET
GPIO
ALT5
GPIO2_IO7
Input
Keeper
ENET1_TX_CLK
G15
NVCC_ENET
GPIO
ALT5
GPIO2_IO6
Input
Keeper
ENET1_TX_DATA0
E16
NVCC_ENET
GPIO
ALT5
GPIO2_IO3
Input
Keeper
ENET1_TX_DATA1
F13
NVCC_ENET
GPIO
ALT5
GPIO2_IO4
Input
Keeper
ENET1_TX_EN
F15
NVCC_ENET
GPIO
ALT5
GPIO2_IO5
Input
Keeper
ENET2_RX_DATA0
E17
NVCC_ENET
GPIO
ALT5
GPIO2_IO8
Input
Keeper
ENET2_RX_DATA1
D17
NVCC_ENET
GPIO
ALT5
GPIO2_IO9
Input
Keeper
ENET2_RX_EN
D16
NVCC_ENET
GPIO
ALT5
GPIO2_IO10
Input
Keeper
ENET2_RX_ER
H13
NVCC_ENET
GPIO
ALT5
GPIO2_IO15
Input
Keeper
ENET2_TX_CLK
H14
NVCC_ENET
GPIO
ALT5
GPIO2_IO14
Input
Keeper
ENET2_TX_DATA0
E14
NVCC_ENET
GPIO
ALT5
GPIO2_IO11
Input
Keeper
ENET2_TX_DATA1
F14
NVCC_ENET
GPIO
ALT5
GPIO2_IO12
Input
Keeper
ENET2_TX_EN
E15
NVCC_ENET
GPIO
ALT5
GPIO2_IO13
Input
Keeper
GPIO1_IO00
M14
NVCC_GPIO
GPIO
ALT5
GPIO1_IO00
Input
Keeper
GPIO1_IO01
M15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO01
Input
Keeper
GPIO1_IO02
M16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO02
Input
Keeper
GPIO1_IO03
N16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO03
Input
Keeper
GPIO1_IO04
N17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO04
Input
Keeper
GPIO1_IO05
P15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO05
Input
Keeper
GPIO1_IO06
N15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO06
Input
Keeper
GPIO1_IO07
N14
NVCC_GPIO
GPIO
ALT5
GPIO1_IO07
Input
Keeper
GPIO1_IO08
P14
NVCC_GPIO
GPIO
ALT5
GPIO1_IO08
Input
Keeper
GPIO1_IO09
P16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO09
Input
Keeper
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
130
NXP Semiconductors
Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
JTAG_MOD
R13
NVCC_GPIO
SJC
ALT0
SJC_MOD
Input
100 k
pull-up
JTAG_TCK
R17
NVCC_GPIO
SJC
ALT0
SJC_TCK
Input
47 k
pull-up
JTAG_TDI
P17
NVCC_GPIO
SJC
ALT0
SJC_TDI
Input
47 k
pull-up
JTAG_TDO
R16
NVCC_GPIO
SJC
ALT0
SJC_TDO
Output
Keeper
JTAG_TMS
R14
NVCC_GPIO
SJC
ALT0
SJC_TMS
Input
47 k
pull-up
JTAG_TRST_B
P13
NVCC_GPIO
SJC
ALT0
SJC_TRSTB
Input
47 k
pull-up
LCD_CLK
C11
NVCC_LCD
GPIO
ALT5
GPIO3_IO0
Input
Keeper
LCD_DATA00
D11
NVCC_LCD
GPIO
ALT5
GPIO3_IO5
Input
Keeper
LCD_DATA01
B12
NVCC_LCD
GPIO
ALT5
GPIO3_IO6
Input
Keeper
LCD_DATA02
D10
NVCC_LCD
GPIO
ALT5
GPIO3_IO7
Input
Keeper
LCD_DATA03
B11
NVCC_LCD
GPIO
ALT5
GPIO3_IO8
Input
Keeper
LCD_DATA04
A11
NVCC_LCD
GPIO
ALT5
GPIO3_IO9
Input
Keeper
LCD_DATA05
D12
NVCC_LCD
GPIO
ALT5
GPIO3_IO10
Input
Keeper
LCD_DATA06
D13
NVCC_LCD
GPIO
ALT5
GPIO3_IO11
Input
Keeper
LCD_DATA07
C12
NVCC_LCD
GPIO
ALT5
GPIO3_IO12
Input
Keeper
LCD_DATA08
B13
NVCC_LCD
GPIO
ALT5
GPIO3_IO13
Input
Keeper
LCD_DATA09
A13
NVCC_LCD
GPIO
ALT5
GPIO3_IO14
Input
Keeper
LCD_DATA10
D14
NVCC_LCD
GPIO
ALT5
GPIO3_IO15
Input
Keeper
LCD_DATA11
C13
NVCC_LCD
GPIO
ALT5
GPIO3_IO16
Input
Keeper
LCD_DATA12
C14
NVCC_LCD
GPIO
ALT5
GPIO3_IO17
Input
Keeper
LCD_DATA13
A14
NVCC_LCD
GPIO
ALT5
GPIO3_IO18
Input
Keeper
LCD_DATA14
B14
NVCC_LCD
GPIO
ALT5
GPIO3_IO19
Input
Keeper
LCD_DATA15
A16
NVCC_LCD
GPIO
ALT5
GPIO3_IO20
Input
Keeper
LCD_DATA16
A15
NVCC_LCD
GPIO
ALT5
GPIO3_IO21
Input
Keeper
LCD_DATA17
D15
NVCC_LCD
GPIO
ALT5
GPIO3_IO22
Input
Keeper
LCD_DATA18
B15
NVCC_LCD
GPIO
ALT5
GPIO3_IO23
Input
Keeper
LCD_DATA19
E12
NVCC_LCD
GPIO
ALT5
GPIO3_IO24
Input
Keeper
LCD_DATA20
B17
NVCC_LCD
GPIO
ALT5
GPIO3_IO25
Input
Keeper
LCD_DATA21
C16
NVCC_LCD
GPIO
ALT5
GPIO3_IO26
Input
Keeper
LCD_DATA22
B16
NVCC_LCD
GPIO
ALT5
GPIO3_IO27
Input
Keeper
LCD_DATA23
C17
NVCC_LCD
GPIO
ALT5
GPIO3_IO28
Input
Keeper
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
131
Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
LCD_ENABLE
A10
NVCC_LCD
GPIO
ALT5
GPIO3_IO1
Input
Keeper
LCD_HSYNC
B10
NVCC_LCD
GPIO
ALT5
GPIO3_IO2
Input
Keeper
LCD_RESET
E10
NVCC_LCD
GPIO
ALT5
GPIO3_IO4
Input
Keeper
LCD_VSYNC
C10
NVCC_LCD
GPIO
ALT5
GPIO3_IO3
Input
Keeper
NAND_ALE
D8
NVCC_NAND
GPIO
ALT5
GPIO4_IO10
Input
Keeper
NAND_CE0_B
E8
NVCC_NAND
GPIO
ALT5
GPIO4_IO13
Input
Keeper
NAND_CE1_B
B6
NVCC_NAND
GPIO
ALT5
GPIO4_IO14
Input
Keeper
NAND_CLE
B7
NVCC_NAND
GPIO
ALT5
GPIO4_IO15
Input
Keeper
NAND_DATA00
D7
NVCC_NAND
GPIO
ALT5
GPIO4_IO2
Input
Keeper
NAND_DATA01
A9
NVCC_NAND
GPIO
ALT5
GPIO4_IO3
Input
Keeper
NAND_DATA02
C9
NVCC_NAND
GPIO
ALT5
GPIO4_IO4
Input
Keeper
NAND_DATA03
C7
NVCC_NAND
GPIO
ALT5
GPIO4_IO5
Input
Keeper
NAND_DATA04
C8
NVCC_NAND
GPIO
ALT5
GPIO4_IO6
Input
Keeper
NAND_DATA05
A6
NVCC_NAND
GPIO
ALT5
GPIO4_IO7
Input
Keeper
NAND_DATA06
B9
NVCC_NAND
GPIO
ALT5
GPIO4_IO8
Input
Keeper
NAND_DATA07
B8
NVCC_NAND
GPIO
ALT5
GPIO4_IO9
Input
Keeper
NAND_DQS
E6
NVCC_NAND
GPIO
ALT5
GPIO4_IO16
Input
Keeper
NAND_RE_B
D9
NVCC_NAND
GPIO
ALT5
GPIO4_IO0
Input
Keeper
NAND_READY_B
E9
NVCC_NAND
GPIO
ALT5
GPIO4_IO12
Input
Keeper
NAND_WE_B
A8
NVCC_NAND
GPIO
ALT5
GPIO4_IO1
Input
Keeper
NAND_WP_B
D6
NVCC_NAND
GPIO
ALT5
GPIO4_IO11
Input
Keeper
ONOFF
R6
VDD_SNVS_IN
SRC
ALT0
SRC_RESET_B
Input
100 k
pull-up
POR_B
R10
VDD_SNVS_IN
SRC
ALT0
SRC_POR_B
Input
100 k
pull-up
RTC_XTALI
T12
VDD_SNVS_CA
P
ANAL
OG
—
RTC_XTALI
—
—
RTC_XTALO
U12
VDD_SNVS_CA
P
ANAL
OG
—
RTC_XTALO
—
—
SD1_CLK
C5
NVCC_SD
GPIO
ALT5
GPIO2_IO17
Input
Keeper
SD1_CMD
C6
NVCC_SD
GPIO
ALT5
GPIO2_IO16
Input
Keeper
SD1_DATA0
A5
NVCC_SD
GPIO
ALT5
GPIO2_IO18
Input
Keeper
SD1_DATA1
A4
NVCC_SD
GPIO
ALT5
GPIO2_IO19
Input
Keeper
SD1_DATA2
B5
NVCC_SD
GPIO
ALT5
GPIO2_IO20
Input
Keeper
SD1_DATA3
B4
NVCC_SD
GPIO
ALT5
GPIO2_IO21
Input
Keeper
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
132
NXP Semiconductors
Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
SNVS_PMIC_ON_REQ
T7
VDD_SNVS_IN
GPIO
ALT0
SNVS_PMIC_ON_REQ
Output
100 k
pull-up
SNVS_TAMPER0
R8
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO00/SNVS_TAMPE
R01
Input
Keeper1,
SNVS_TAMPER1
P6
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO01/SNVS_TAMPE
R11
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER2
N10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO02/SNVS_TAMPE
R21
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER3
P10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO03/SNVS_TAMPE
R31
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER4
P7
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO04/SNVS_TAMPE
R41
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER5
P8
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO05/SNVS_TAMPE
R51
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER6
R7
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO06/SNVS_TAMPE
R61
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER7
N9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO07/SNVS_TAMPE
R71
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER8
N8
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO08/SNVS_TAMPE
R81
Input
Keeper/N
ot
connecte
d1,2
SNVS_TAMPER9
P9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO09/SNVS_TAMPE
R91
Input
Keeper/N
ot
connecte
d1,2
TEST_MODE
N7
VDD_SNVS_IN
TCU
ALT0
TCU_TEST_MODE
Input
Keeper
UART1_CTS_B
L14
NVCC_UART
GPIO
ALT5
GPIO1_IO18
Input
Keeper
UART1_RTS_B
K14
NVCC_UART
GPIO
ALT5
GPIO1_IO19
Input
Keeper
UART1_RX_DATA
L17
NVCC_UART
GPIO
ALT5
GPIO1_IO17
Input
Keeper
UART1_TX_DATA
L15
NVCC_UART
GPIO
ALT5
GPIO1_IO16
Input
Keeper
2
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
133
Package Information and Contact Assignments
Table 94. 9 x 9 mm Functional Contact Assignments (continued)
UART2_CTS_B
J17
NVCC_UART
GPIO
ALT5
GPIO1_IO22
Input
Keeper
UART2_RTS_B
J14
NVCC_UART
GPIO
ALT5
GPIO1_IO23
Input
Keeper
UART2_RX_DATA
K16
NVCC_UART
GPIO
ALT5
GPIO1_IO21
Input
Keeper
UART2_TX_DATA
L16
NVCC_UART
GPIO
ALT5
GPIO1_IO20
Input
Keeper
UART3_CTS_B
H16
NVCC_UART
GPIO
ALT5
GPIO1_IO26
Input
Keeper
UART3_RTS_B
H15
NVCC_UART
GPIO
ALT5
GPIO1_IO27
Input
Keeper
UART3_RX_DATA
K15
NVCC_UART
GPIO
ALT5
GPIO1_IO25
Input
Keeper
UART3_TX_DATA
K17
NVCC_UART
GPIO
ALT5
GPIO1_IO24
Input
Keeper
UART4_RX_DATA
H17
NVCC_UART
GPIO
ALT5
GPIO1_IO29
Input
Keeper
UART4_TX_DATA
J16
NVCC_UART
GPIO
ALT5
GPIO1_IO28
Input
Keeper
UART5_RX_DATA
J13
NVCC_UART
GPIO
ALT5
GPIO1_IO31
Input
Keeper
UART5_TX_DATA
K13
NVCC_UART
GPIO
ALT5
GPIO1_IO30
Input
Keeper
USB_OTG1_CHD_B
T15
OPEN DRAIN
GPIO
—
USB_OTG1_CHD_B
—
—
USB_OTG1_DN
R11
VDD_USB_CAP
ANAL
OG
—
USB_OTG1_DN
—
—
USB_OTG1_DP
P11
VDD_USB_CAP
ANAL
OG
—
USB_OTG1_DP
—
—
USB_OTG1_VBUS
T9
USB_VBUS
VBUS
POWE
R
—
USB_OTG1_VBUS
—
—
USB_OTG2_DN
T10
VDD_USB_CAP
ANAL
OG
—
USB_OTG2_DN
—
—
USB_OTG2_DP
U10
VDD_USB_CAP
ANAL
OG
—
USB_OTG2_DP
—
—
USB_OTG2_VBUS
U9
USB_VBUS
VBUS
POWE
R
—
USB_OTG2_VBUS
—
—
XTALI
T14
NVCC_PLL
ANAL
OG
—
XTALI
—
—
XTALO
U14
NVCC_PLL
ANAL
OG
—
XTALO
—
—
1
SNVS_TAMPER0 to SNVS_TAMPER9 can be configured as GPIO or tamper detection pin, it is depending on the fuse setting
TAMPER_PIN_DISABLE[1:0]. When the pad is configured as GPIO, the value is keeper out of reset.
2 SNVS_TAMPER0 to SNVS_TAMPER9 is input unconnected in the following conditions.
—SNVS low power mode when configured as GPIO
—Tamper functions are not used when configured as TAMPER detection pins
It is required to connect external 1M Ohm pull-up or pull-down resistors to the pad to avoid the undesired leakage under two
conditions above.
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
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NXP Semiconductors
LCD_ENABLE 10
11
12
13
14
15
16
17
LCD_DATA04
VSS
LCD_DATA09
LCD_DATA13
LCD_DATA16
LCD_DATA15
VSS
LCD_HSYNC
LCD_DATA03
LCD_DATA01
LCD_DATA08
LCD_DATA14
LCD_DATA18
LCD_DATA22
LCD_DATA20
LCD_VSYNC
LCD_CLK
LCD_DATA07
LCD_DATA11
LCD_DATA12
VSS
LCD_DATA21
LCD_DATA23
LCD_DATA02
LCD_DATA00
LCD_DATA05
LCD_DATA06
LCD_DATA10
LCD_DATA17
ENET2_RX_EN
LCD_RESET
NVCC_NAND
LCD_DATA19
NVCC_LCD
ENET2_TX_EN
VSS
F
G
E
D
ENET2_RX_DATA0 ENET2_RX_DATA1
ENET1_RX_DATA1 ENET1_TX_DATA0
ENET1_TX_EN
ENET2_TX_DATA1 ENET2_TX_DATA0
ENET1_TX_DATA1
VSS
ENET1_RX_DATA0
ENET1_RX_EN
ENET1_TX_CLK
ENET1_RX_ER
NVCC_ENET
VDD_ARM_CAP
VDD_ARM_CAP
C
NAND_DATA02 NAND_DATA06 NAND_DATA01 9
NAND_RE_B
NAND_READY_B
VDD_ARM_CAP
B
A
8
NAND_DATA04 NAND_DATA07
NAND_ALE
NAND_CE0_B
VDD_SOC_CAP
NAND_WEB
NAND_DATA03
NAND_DATA00
NVCC_SD1
VSS
NAND_CE1_B NAND_DATA05 6
SD1_CMD
NAND_WP_B
NAND_DQS
7
5
SD1_DATA0
SD1_DATA2
SD1_CLK
CSI_PIXCLK
NVCC_CSI
DRAM_SDBA1
NVCC_DRAM
VSS
4
SD1_DATA1
SD1_DATA3
CSI_DATA04
CSI_DATA01
DRAM_ADDR06
DRAM_SDWE_B
DRAM_CAS_B
NAND_CLE
3
CSI_DATA06
CSI_DATA05
CSI_DATA00
CSI_VSYNC
DRAM_ADDR14
VSS
DRAM_SDBA2
VDD_SOC_CAP
2
VSS
CSI_DATA02
CSI_DATA07
CSI_HSYNC
DRAM_ADDR15
DRAM_RESET
DRAM_ADDR01
1
VSS
CSI_MCLK
CSI_DATA03
DRAM_ODT1
VSS
DRAM_ADDR00
A
B
C
D
E
F
6.2.3
G
Package Information and Contact Assignments
9 x 9 mm, 0.5 mm Pitch, Ball Map
Table 95 shows the 9 x 9 mm, 0.5 mm pitch ball map for the i.MX 6ULL.
Table 95. 9x9 mm, 0.5 mm Pitch, Ball Map
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
135
136
VSS
GPIO1_IO04
JTAG_TDI
M
GPIO1_IO02
GPIO1_IO03
GPIO1_IO09
N
GPIO_IO01
GPIO1_IO06
GPIO1_IO05
P
UART1_CTS_B
GPIO1_IO00
GPIO1_IO07
GPIO1_IO08
UART1_RTS_B
L
K
J
UART2_CTS_B
H
UART4_RX_DATA
UART3_CTS_B
UART3_RTS_B
VSS
UART2_RX_DATA UART4_TX_DATA
UART1_RX_DATA UART3_TX_DATA
UART2_TX-DATA
ENET2_TX_CLK
ENET2_RX_ER
UART2_RTS_B
UART5_TX_DATA UART5_RX_DATA
UART1_TX_DATA UART3_RX_DATA
NVCC_UART
NVCC_GPIO
ADC_VREFH
JTAG_TRST_B
VSS
VDD_ARM_CAP
VDD_SOC_IN
VDD_SOC_IN
VDD_SOC_IN
VSS
VDD_ARM_CAP
VDD_SOC_IN
VDD_SOC_IN
VDD_SOC_IN
VDD_SNVS_CAP
VDD_ARM_CAP
VDD_SOC_IN
VDD_SOC_IN
VDD_SOC_IN
VDD_SNVS_IN
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VDD_USB_CAP
NGND_KEL0
VSS
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VSS
VDD_SOC_CAP
USB_OTG1_DP
SNVS_TAMPER3 SNVS_DAMPER2
SNVS_TAMPER9 SNVS_TAMPER7
SNVS_TAMPER5 SNVS_TAMPER8
TEST_MODE
SNVS_TAMPER4
NVCC_DRAM_2P5
DRAM_CSI_B
DRAM_ADDR08
DRAM_ADDR11
NVCC_DRAM
NVCC_DRAM
DRAM_ADDR13
DRAM_ADDR07
DRAM_SDCLK0_N
DRAM_RAS_B
DRAM_SDQS1_N DRAM_ADDR04
DRAM_DATA12
SNVS_TAMPER1
DRAM_SDBA0
VSS
DRAM_SDCLK0_P
DRAM_ADDR12
VSS
DRAM_SDQS1_P
DRAM_DATA10
NVCC_DRAM
DRAM_ADDR05
DRAM_ADDR03
DRAM_ODT0
DRAM_SDCKE0
DRAM_ADDR10
DRAM_DATA13
DRAM_DATA15
DRAM_DATA01
DRAM_ADDR02
DRAM_ADDR09
DRAM_SDCKE1
DRAM_CS0_B
VSS
DRAM_DATA14
DRAM_DATA08
DRAM_SDQS0_P
H
J
K
L
M
N
P
Package Information and Contact Assignments
Table 95. 9x9 mm, 0.5 mm Pitch, Ball Map (continued)
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
NXP Semiconductors
NXP Semiconductors
DRAM_DM1
DRAM_DATA11
VSS
DRAM_DATA06
DRAM_SDQS0_N
ONOFF
DRAM_VREF
DRAM_ZQPAD
DRAM_DATA00
DRAM_DATA02
DRAM_DATA03
DRAM_DATA05
VSS
DRAM_DATA09
DRAM_DATA07
DRAM_DQM0
DRAM_DATA04
VSS
1
2
3
4
5
6
SNVS_TAMPER0
VSS
POR_B
USB_OTG1_DN
VSS
JTAG_MOD
JTAG_TMS
VSS
JTAG_TDO
JTAG_TCK
R
BOOT_MODE0
USB_OTG1_VBUS
USB_OTG2_DN
GPANAIO
RTC_XTALI
NVCC_PLL
XTALI
USB_OTG1_CHD_B
CCM_CLK1_P
VDDA_ADC_3P3
T
BOOT_MODE1
USB_OTG2_VBUS
USB_OTG2_DP
VDD_HIGH_CAP
RTC_XTALO
VSS
XTALO
VDD_HIGH_IN
CCM_CLK1_N
VSS
U
8
9
10
11
12
13
14
15
16
17
7 CCM_PMIC_STBY_REQ SNVS_PMIC_ON_REQ SNVS_TAMPER6
R
T
U
Package Information and Contact Assignments
Table 95. 9x9 mm, 0.5 mm Pitch, Ball Map (continued)
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
137
Revision History
7
Revision History
Table 96 provides a revision history for this data sheet.
Table 96. i.MX 6ULL Data Sheet Document Revision History
Rev.
Number
Date
Substantive Change(s)
1.2
11/2017
• Updated the part numbers and added a new part number (MCIMX6Y2CVK08AB) in the Table 1,
"Ordering Information"
• Updated the silicon revision number in the Figure 1, "Part Number Nomenclature—i.MX 6ULL"
• Updated the GPIO1_IO09 signal name in the Table 85, "SD/MMC Boot through USDHC1" and added
a footnote
• Updated the NAND_ALE signal name in the Table 86, "SD/MMC Boot through USDHC2" and added
a footnote
1.1
05/2017
•
•
•
•
•
•
•
•
•
•
Changed terminology from “floating” to “not connected”
Changed the LV-DDR3 to DDR3L in the Section 1.2, “Features"
Added a footnote regarding maximum voltage allowance in the Table 7, "Absolute Maximum Ratings"
Updated the minimum value of VDD_SOC_CAP in the Low Power Run Mode: LDO Enabled from the
Table 10, "Operating Ranges"
Removed the LPSR mode in the Section 4.1.6, “Power Modes"
Removed a note in the Section 4.2.1, “Power-Up Sequence"
Replaced the MMDC compatible information with a cross reference in the Section 4.6.3, “DDR I/O DC
Parameters" and Section 4.7.2, “DDR I/O AC Parameters"
Removed the Section 4.9.4, “DDR SDRAM Specific Parameters (DDR3 and LPDDR2)”
Added a new Section 4.10, “Multi-Mode DDR Controller (MMDC)"
Changed SD3 min to 1.7 ns in the Table 51, "eMMC4.4/4.41 Interface Timing Specification"
1
02/2017
• Added a new part number in the Table 1, "Ordering Information"
• Updated the Part differentiator number 3 to Reserved, removed 300 MHz from frequency, and added
792 MHz in the Figure 1, "Part Number Nomenclature—i.MX 6ULL"
• Updated the DDR I/O supply voltage and added a table not in the Table 7, "Absolute Maximum
Ratings"
• Updated Table 10, "Operating Ranges"
• Added Max. current for VDD_SOC_IN at 792 MHz in the Table 13, "Maximum Supply Currents"
• Updated the LDO_2P5 of the LOW POWER IDLE: LDO Bypassed row in the Table 15, "Low Power
Mode Current and Power Consumption" and the VDD_SOC_IN supply voltage for LDO enable mode
• Updated the Figure 18, "Asynchronous A/D Muxed Write Access"
• Added a new Section 4.12.9.1, “LCDIF Signal Mapping"
• Added a note in the Section 4.2.1, “Power-Up Sequence"
• Updated VDD_HIGH_CAP pin assignment in the Table 90, "14x14 mm Supplies Contact Assignment"
• Updated VDD_HIGH_CAP pin in the Table 92, "14 x 14 mm, 0.8 mm Pitch, Ball Map"
0
09/2016
• Initial public release
i.MX 6ULL Applications Processors for Industrial Products, Rev. 1.2, 11/2017
138
NXP Semiconductors
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Document Number: IMX6ULLIEC
Rev. 1.2
11/2017
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