MCZ33789BAER2

Freescale Semiconductor Advance Information Document Number: MC33789 Rev. 4.0, 9/2014 Airbag System Basis Chip (SBC) with Power Supply and PSI5 Sensor Interface 33789 AUTO RESTRAINT The 33789, a SafeAssure SMARTMOS solution, is a mixed signal IC for airbag safety applications. The 33789 provides a cost effective and flexible system IC solution across the range of airbag partitions used in cars and other vehicles. The 33789 connects to the 12 V vehicle battery and supplies the multiple voltages of a typical airbag system. The 33789 can detect switched input states, communicate with both local and remote crash sensors. It offers an industry standard interface (SPI) and four PSI5 master interfaces. The 33789 has a AE SUFFIX (PB-FREE) dedicated safing state machine that complements the airbag’s MCU hardware/ EXPOSED PAD software safing approach. Also included are a diagnostic - self protection 98ASA10763D capability and a programmable analog interface accessible by the system MCU. 64-PIN LQFP The 33789 is well suited for use in low to high end airbag systems by allowing the designer to scale a design for the number of firing loops needed while providing enhanced safety and system reliability. Applications Features • Airbag safety • Designed to operate 5.2 V  VPWR  20 V, up to a 40 V transient • Safing state machine with programmable sensing thresholds • Two configurable high-side/low-side drivers with PWM capability • Four PSI5 satellite sensor master interfaces • Self-protected and diagnostic capability • Watchdog and system Power ON Reset (POR) • Supports complete airbag system power supply architecture, including system power mode control, supplies for squib firing (33 V), satellite sensors (6.3 V), and local ECU sensors and ECU logic circuits (5.0 V) • Nine configurable switch input monitors for simple switch and Hall- effect sensor interfaces with internal power supply • 16-bit SPI interface • LIN 2.1 physical layer interface 33789 VBAT IN1 IN2 9 Input Monitors IN8 IN9 LIN PSI5_1 4 Satellite Sensor Interfaces Wake Up WAKE BSTSW 33 V VBST VER PSI5_2 PSI5_3 VBAT VPWR ERSW PSI5_4 VPWR OUT1_D OUT1_S 5.0 V X/Y Axis Accel. Sensor Sensor SPI 5.0 V VFIRE_x SQB_H1 SQB_H1 BUCKSW VBUCK VCCDRI SPI 5.0 V Energy Storage 9.0 V 5.0 V Output Squib Driver 1 VCC SQB_L1 5.0 V SPI_A VDD AIN SQB_L1 AOUT ARM RESET RESET SPI_B MCU Squib Driver 2 FEN_1 FEN_2 Squib Driver SPI RESET SPI 2 ARM_X and ARM_Y for Squib Driver 2 FENs Figure 1. 33789 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010-2014. All rights reserved. Cross-coupled Squib Connections ORDERABLE PARTS ORDERABLE PARTS This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. Table 1. Orderable Part Variations Part Number MCZ33789BAE Notes Temperature (TA) (1) -40 °C to 125 °C Package 64 LQFP EP Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. 33789 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM SI Power Mode Control SPI Interface SO SCK VREF WAKE VPWR CS BSTSW CS_A CS_B CS_C Boost Converter SPI Monitor DISARM VBST Safing A_SENSOR ARM BSTGND BSTCOMP1 BSTCOMP2 Safing Logic ASST Configurable Drivers OUT1_D OUT1_S VER Energy Reserve Control SCRAP ERSW VERDIAG OUT2_D VBUCK OUT2_S CLK PSI5 Satellite Sensor Interfaces SATSYNC PSI5_1 PSI5_2 BUCKSW Buck Converter BUCKGND VBUCK_R BUCKCOMP1 BUCKCOMP2 PSI5_3 PSI5_4 CPC1 GND_PSI IN1 Analog Multiplexer IN2 IN3 Quad Bias Voltage Regulator CPC2 Sync Supply VSYNC CPGND IN4 IN5 IN6 IN7 Linear Regulator & Watchdog IN8 IN9 Analog Multiplexer AOUT VREF LIN Interface Power Supply I/O Monitor GNDA VCC VDD RESET PPT Analog Multiplexer Driver Output OUTx Monitor VCCDRI VSS TXD LIN RXD GND_LIN Figure 2. 33789 Simplified Internal Block Diagram 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS VERDIAG BUCKGND BUCKSW VBST ERSW BSTGND BSTSW VER WAKE VPWR VSYNC CPC2 CPC1 CPGND Transparent Top View VBUCK_R VBUCK PIN CONNECTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ASST 1 48 BUCKCOMP1 CS_C 2 47 BUCKCOMP2 CS_B 3 46 BSTCOMP1 CS_A 4 45 BSTCOMP2 SCRAP 5 44 VDD PSI5_1 6 43 VSS PSI5_2 7 42 VCC PSI5_3 8 41 GNDA PSI5_4 9 40 VCCDRI GND_PSI 10 39 DISARM SO 11 38 ARM SI 12 37 RESET SCK 13 36 AOUT CLK 14 35 RXD CS 15 34 TXD SATSYNC 16 33 A_SENSOR IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 GND_LIN LIN OUT1_D OUT1_S PPT OUT2_S OUT2_D 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. 33789 Pin Connections A functional description of each pin can be found in the Functional Pin Description section beginning on page 26. Table 2. 33789 Pin Definitions Pin Number Pin Name Pin Function Formal Name 1 ASST Input Analog Sensor Self-test 2 CS_C Input Chip Select C Active low SPI monitor chip select input dedicated for on-board sensor C. 3 CS_B Input Chip Select B Active low SPI monitor chip select input dedicated for on-board sensor B 4 CS_A Input Chip Select A Active low SPI monitor chip select input dedicated for on-board sensor A 5 SCRAP Input Scrap 6 PSI5_1 Input/Output PSI5 Interface 1 PSI5 standard interface 1 as satellite sensor channel 1 7 PSI5_2 Input/Output PSI5 Interface 2 PSI5 standard interface 2 as satellite sensor channel 2 8 PSI5_3 Input/Output PSI5 Interface 3 PSI5 standard interface 3 as satellite sensor channel 3 9 PSI5_4 Input/Output PSI5 Interface 4 PSI5 standard interface 4 as satellite sensor channel 4 10 GND_PSI Ground PSI Ground 11 SO Output SPI Data Out 12 SI Input SPI Data In SPI data input 13 SCK Input SPI Clock SPI clock input 14 CLK Input Satellite Sensor Clock 15 CS Input SPI Chip Select Definition Active high input to initiate analog sensor self-test Scrap command input Dedicated ground point for PSI5 sensor SPI data output Clock input for the PSI5 sensor interface(s) running in synchronous operation mode Active low SPI chip select input from MCU, also used for satellite channels on SPI monitor 33789 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 2. 33789 Pin Definitions (continued) Pin Number Pin Name Pin Function Formal Name 16 SATSYNC Input Satellite Sync-pulse Trigger Satsync command input from MCU to trigger PSI5 Sync-pulse 17 OUT2_D Output Output Driver2 Drain Drain pin of the configurable driver2 outputs 18 OUT2_S Output Output Driver2 Source 19 PPT Input Production Programming and Testing 20 OUT1_S Output Output Driver1 Source 21 OUT1_D Output Output Driver1 Drain 22 LIN Input/output LIN Interface LIN interface. It can be configured as a bi-directional pin which represents the singlewire bus transmitter and receiver 23 GND_LIN Ground LIN Ground Dedicated ground point for a bi-directional pin which represents the single-wire bus transmitter and receiver 24 IN9 Input Input Monitor Port 9 Port 9 of input monitor for DC sensor 25 IN8 Input Input Monitor Port 8 Port 8 of input monitor for DC sensor 26 IN7 Input Input Monitor Port 7 Port 7 of input monitor for DC sensor 27 IN6 Input Input Monitor Port 6 Port 6 of input monitor for DC sensor 28 IN5 Input Input Monitor Port 5 Port 5 of input monitor for DC sensor 29 IN4 Input Input Monitor Port 4 Port 4 of input monitor for DC sensor 30 IN3 Input Input Monitor Port 3 Port 3 of input monitor for DC sensor 31 IN2 Input Input Monitor Port 2 Port 2 of input monitor for DC sensor 32 IN1 Input Input Monitor Port 1 Port 1 of input monitor for DC sensor 33 A_SENSOR Input Analog Sensor Input Analog sensor input for safing 34 TXD Input Data Input from UART Logic-level data input from MCU UART transmitter for LIN/K-line 35 RXD Output Data Output to UART Logic-level data output to MCU UART receiver for LIN/K-line 36 AOUT Output Analog Output 37 RESET Output Reset 38 ARM Output Arm Enable Active high safing enable signal to squib driver 39 DISARM Output Arm Disable Active low safing enable signal to squib driver 40 VCCDRI Output VCC Bypass Transistor Drive 41 GNDA Ground Analog Ground 42 VCC Input VCC Input 43 VSS Ground Digital Ground 44 VDD Output Digital Power Supply Output 45 BSTCOMP2 Input Boost Compensation pin2 Connection 2 to the boost converter compensation network 46 BSTCOMP1 Input Boost Compensation pin1 Connection 1 to the boost converter compensation network 47 BUCKCOM P2 Input Buck Compensation pin2 Connection 2 to the buck converter compensation network 48 BUCKCOM P1 Input Buck Compensation pin1 Connection 1 to the buck converter compensation network Definition Source pin of the configurable driver2 outputs Active high input to enable test-mode for production programming and testing. Not for application Source pin of the configurable driver1 outputs Drain pin of the configurable driver1 outputs Analog output to send MCU scaled, multiplexed and buffered analog signals for diagnosis Active low reset output Linear regulator drive output to control an external PNP transistor for 5.0 V VCC output Analog ground 5.0 V VCC input for monitoring and internal supply Digital ground 2.5 V linear regulator output for output capacitor connection. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 5 PIN CONNECTIONS Table 2. 33789 Pin Definitions (continued) Pin Number Pin Name Pin Function Formal Name 49 VERDIAG Input Energy Reserve Diagnosis 50 BUCKGND Ground Buck Converter Ground 51 BUCKSW Output Buck Switch 52 VBST Input Boost Voltage Input 53 ERSW Output Energy Reserve Switch Storage driver output to control the energy reserve capacitor charging 54 BSTGND Ground Boost Converter Ground Ground return of the boost converter, buck switch ground 55 BSTSW Output Boost Switch 56 VER Input Energy Reserve Voltage 57 WAKE Input Wake-up 58 VPWR Input Power Supply 59 VSYNC Input/output Sensor Sync Power Supply 60 CPC2 Output Charge Pump Capacitor Pin2 Charge pump capacitor pin2 61 CPC1 Output Charge Pump Capacitor Pin1 Charge pump capacitor pin1 62 CPGND Ground Charge Pump Ground 63 VBUCK_R Input Buck Converter Redundant Input 64 VBUCK Input Buck Converter Input Definition AC coupled energy reserve diagnostic input Ground return of the buck converter, buck switch ground Buck switch driver output to connect buck inductor Boost voltage input for boost loop feedback and source of buck converter, same voltage as boost output Boost switch driver output to connect boost inductor Energy reserve voltage input for the storage capacitor charge control and energy reserve monitor Wake-up signal input to start-up boost and buck converters Battery voltage power supply input Satellite sensor sync voltage supply charge/discharge connection Charge pump ground Redundant buck converter input to supply current for charge pump Buck converter input for buck loop feedback and current source of charge pump 33789 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit Supply Input Voltage VPWR -0.3 to 40 V Wake-up Input Voltage VWAKE -16 to 40 V Supply Voltage - 1 VBST, VBSTSW, VBUCKSW, VERSW, VER -0.3 to 40 V Supply Voltage - 2 VSYNC, VCPC2 -0.3 to 20 V Supply Voltage - 3 VCPC1, VBUCK, VBUCK_R, VCCDRI -0.3 to 10 V Supply Voltage - 4 VERDIAG -0.3 to 7 V Supply Voltage - 5 VCC -0.3 to 5.5 V Supply Voltage - 6 VDD, VBSTCOMP1, VBSTCOMP2, VBUCKCOMP1, VBUCKCOMP2 -0.3 to 3 V ELECTRICAL RATINGS LIN Interface Voltage VLIN -27 to 40 V I/O Voltage - 1 VOUT1_D, VOUT1_S, VOUT2_D, VOUT2_S -1 to 40 V I/O Voltage - 2 VIN1 ~ VIN9, VPSI5_1 ~ VPSI5_4 -1 to 20 V I/O Voltage - 3 VARM, VDISARM, VPPT -0.3 to 10 V I/O Voltage - 4 VA_SENSOR, VAOUT, VASST, VSCRAP, VRESET, VTXD, VRXD, VSI, VSO, VSCK, VCLK, VCS, VCS_A, VCS_B, VCS_C, VSATSYNC -0.3 to 5.5 V VSS, VGND_LIN, VCPGND, VGND_PSI -0.3 to 0.3 V GND Shift LIN Bus Voltage(2) Normal Operation (DC) Transient (Coupled Through 1.0 nF Capacitor, according to ISO7637-2 & ISO7637-3) (See Table 4 and Figure 4) - Pulse 1 (test up to the limit for Damage - Class C(1)) - Pulse 2a (test up to the limit for Damage - Class C(1)) - Pulse 3a (test up to the limit for Damage - Class C(1)) - Pulse 3b (test up to the limit for Damage - Class C(1)) VBUS(SS) -27 to 40 VBUS(S1) -100 VBUS(S2A) +75 VBUS(S3A) -150 VBUS(S3B) +100 V Notes 1. Class C: At least one function of the transceiver stops working properly during the test, and will return to the proper operation automatically when the exposure to the disturbance has ended. No physical damage of the IC occurs. 2. The LIN bus voltage is applied on the LIN pin as VLIN during tests. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ESD Capability AECQ100 Human Body Model - JESD22/A114(3) All pins VESD1-1 Charge Device Model - JESD22/C101(3) Corner pins VCCDRI pin All other pins VESD2-1 VESD2-2 VESD2-3 ± 2.0 k ± 750 ± 400 V ±500 Additional for LIN Conformance Contact Discharge, Unpowered(4) LIN pin without capacitor LIN pin with 220 pF capacitor LIN pin with 220 pF capacitor and indirect ESD coupling (according to ISO10605 - Annex F) VLIN_ESD1-1 VLIN_ESD1-2 VLIN_ESD1-3 ± 6.0 k ± 6.0 k ± 8.0 k THERMAL RATINGS Operating Temperature Junction Temperature Case (Exposed Pad) Temperature TJ TC -40 to 150 -40 to 125 °C TSTG -65 to +150 °C TPPRT Note 6 °C Junction to Ambient (Natural Convection) JA 26 °C/W Junction to Case (Exposed Pad) JC 1.5 °C/W Storage Temperature Peak Package Reflow Temperature During (6) Reflow(5), THERMAL RESISTANCE Notes 3. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM) (CZAP = 4.0 pF). 4. According to “Hardware Requirements for LIN, CAN, and Flexray Interfaces in Automotive Applications” specification Rev. 1.1/December 2, 2009 (CZAP = 150 pF, RZAP = 330 ). 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 6. 33789 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 4. Limits / Maximum Test Voltage for LIN Pin Transient Immunity Tests Test Pulse VS [V] Pulse Repetition Frequency [Hz] (1/T1) Test Duration [min] Ri [W] Remarks 1 -100 2 10 10 t2 = 0s 2a +75 2 10 2 3a -150 10 10 50 3b +100 10 10 50 Notes 7. VSUP is applied on the VPWR pin as a test condition. The I/V characteristic and leakage of the pin is performed before and after the test. The supply pins and LIN must pass the VS voltage level specified in Table 4 without damage. The failure validation during test is evaluated at RxD. Tests perform in Normal mode on LIN (Failure on RxD), VSUP (Failure on LIN)(7). The voltage level found is for information only. Failure criteria on RxD in Normal Mode: 0.9 V and 7.5 µs DUT 1.0 nF LIN Transient Pulse Generator (Note) GND DUT GND Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,. Figure 4. Test Circuit for Transient Test Pulses (LIN) 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics Characteristics noted under conditions 7.0 V  VSUP(8)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes POWER MANAGEMENT VPWR Power Supply Input Voltage Normal Operation 5.2 - 20 VWAKE_TH Wake-up Threshold Voltage Normal VPWR Range 0.3* VPWR 0.5* VPWR 0.7* VPWR V V RWAKE Wake-up Input Internal Pull-down Resistance 120 200 320 VBST Boost Converter Output Voltage Normal VPWR Range, 0  IBST  Max. IBST 31.6 33.3 35 Boost Overvoltage Threshold 36 38 40 V VBST_OV_CLMP Boost Overvoltage Clamping Boost operating with active clamping 40 43 46 V VBST_OV_HYS Boost Overvoltage Hysteresis 2.2 2.6 3.0 V Low VPWR as Boost Undervoltage Lockout Threshold and IGNSTAT Detect Threshold 4.7 4.95 5.2 V Boost Undervoltage Hysteresis 0.3 0.5 0.8 V - - 550 m VBST_OV VBST_UV VBST_UV_HYS k V RBSTSW_ON Boost Switch Transistor On Resistance IBSTSW_LMT Boost Switch Current Limit 1.3 1.5 1.8 A TSW_SHDN Power Switch Thermal Shutdown 155 175 195 °C TSW_HYST Power Switch Thermal Shutdown Hysteresis 15 - 30 °C ESRCERM Energy Reserve Capacitor ESR Measurement Range 200 - 600 m - CER ESR Measurement Tolerance -50 - 50 m - CER Capacitance Measurement Tolerance -15 - 15 % CER Charge Transistor On Resistance 3.0 10 14  CER Charge Transistor Overcurrent Shutdown Threshold 400 550 800 mA CER Discharge Transistor On Resistance 2.0 5.5 8.0  CER Discharge Transistor Overcurrent Shutdown Threshold 350 450 800 mA ERSW Pin Leakage Current - - 250 nA IVER_LEAK VER Pin Leakage Current - - 200 µA VER_RESD CER Residual Voltage after 10 s Discharge - - 2.5 V Buck Converter Output Voltage 10 V  VBST  40 V, 100 mA  IBUCK  IBUCK_C 8.73 9.0 9.27 V Buck Converter Output Overvoltage Shutdown Threshold 9.6 10 10.8 V Low VBST as Buck Converter Start-up Threshold 13.5 15.5 17.5 V - - 460 mVPP RERSW_CH_ON IERSW_CH_SHDN RERSW_DISCH_ON IERSW_DISCH_SHDN IERSW_LEAK VBUCK VBUCK_OV_SHDN VBUCK_UV VBUCK_RIPL Buck Converter Output Ripple Voltage 6.0 V  VPRW 40 V, 100 mA IBUCK IBUCK_C Notes 8. VSUP is applied on the VPWR pin as a test condition. 33789 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(8)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Buck Converter Output Current Capability 400 - - mA - 5.0 4.0 8.0 6.0 mV Buck High-side Switch Current Limit 500 800 1100 mA Sync Supply Output Voltage 6.0 V  VPRW  40 V 15 - 2x VBUCK V - - 300 mVPP Sync Supply Output Current Capability 20 - - mA Sync Switch Overcurrent Protection Limit 65 - 150 mA Notes POWER MANAGEMENT (CONTINUED) IBUCK_C Buck Converter Load Regulation VBUCK_LOAD IBUCKSW_HS_LMT VSYNC VSYNC_RIPL ISYNC_C ISYNC_OC IBUCK = 100 mA, IBUCK = 100 mA IBUCK = 300 mA, IBUCK = 100 mA Sync Supply Output Ripple Voltage 6.0 V  VPRW  40 V VCC VCC Supply Output Voltage 6.0 V  VBUCK  9.5 V, 0  ICC  200 mA 4.85 5.0 5.15 V - VCC Supply Line Regulation VPWR-AC = 200 mVPP, f PWR-AC  500 kHz 20 - - dB - - 10 mV - 5.0 20 mVPP 9.0 13.5 22 mA VCC_NOISE VCC Supply Load Regulation ICC-DC = 0.8* ICC_MAX, ICC = 50 mA VCC Supply Noise Voltage IVCCDRI_LMT VCC Base Driver Current Limit TA = 25°C, Temperature coefficient = 300 ppm/ °C (typ.) VBUCK_VCC Minimum VBUCK Voltage for VCC Operation - - 6.0 V Minimum VBST Voltage for VCC Operation - - 7.0 V VDD Supply Voltage - 2.5 - V VBST_VCC VDD RESET AND WATCHDOG VRESET_H Reset Output High IRESET = -2.0 mA VCC - 0.4 - VCC VRESET_L Reset Output Low IRESET = 2.0 mA 0.0 - 0.4 V V VCC_OP Rising VCC Threshold for Reset Operation - - 1.5 V VCC_OV VCC Overvoltage for Reset 5.2 - 5.5 V VCC_UV VCC Undervoltage for Reset 4.5 - 4.80 V VCC Voltage Monitor Threshold Hysteresis 30 - - mV VDD_OV VDD Overvoltage for Reset 2.7 - 3.0 V VDD_UV VDD Undervoltage for Reset 1.85 1.90 2.10 V 0.3 - 0.8 V VCC_VM_HYS GNDA to GND_LIN Voltage Difference to Activate Open GNDA VGNDA_GND_LIN_TH Detection 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(8)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SATELLITE SENSOR INTERFACE ISAT_BUS_SUP_Q Satellite Bus Supply Quiescent Current - - 2.2 mA ISAT_BUS_SUP Satellite Bus Supply Operation Current - - 4.0 mA ISAT_SYNC_SUP_Q Sync Supply Quiescent Current - - 1.0 mA ISAT_SYNC_SUP Sync Supply Operation Current - - 1.0 mA ISAT_VCC_Q Satellite Logic Supply Quiescent Current - - 1.0 mA ISAT_VCC Satellite Logic Supply Operation Current - - 3.0 mA VSAT_OUT Satellite Interface DC Output Operation Voltage 0  ISAT_OUT  65 mA 5.8 6.3 6.7 - - 0.5 30 20 - - dB - - 200 mVPP 10 - 12 V VSAT_OUT + 4.3 - VSAT_OUT + 5.5 V VSAT_OUT_DIS PSRRSAT_BUS_SUP VSAT_RIPL Satellite Interface DC Output Disable Voltage ISAT_OUT = 0 mA Satellite Interface Ripple Rejection from Bus Supply 50 kHz  fRIPL  280 kHz 280 kHz  fRIPL  560 kHz Satellite Interface Ripple Voltage due to Current Modulation (typical application configuration) VSAT_SYNC_ABS Sync Pulse Absolute Voltage VSAT_SYNC_STEP Sync Pulse Voltage Step V V VSATSYNC_L SATSYNC Input Low Voltage -0.3 - 1.0 V VSATSYNC_H SATSYNC Input High Voltage 2.0 - VCC+0.3 V SATSYNC Input Pull-down Current 10 - 50 µA Satellite Interface Operational Current Range 0.0 - 65 mA Satellite Interface Pull-down Current Limit 27 - 60 mA Satellite Interface Overcurrent Limit 70 - 120 mA Minimum Satellite Quiescent Current Adaptation Level 1.9 - 3.8 mA ISAT_Q_RANGE_MAX Maximum Satellite Quiescent Current Adaptation Level 35 - 50 mA Satellite Quiescent Current for Single Satellite Synchronous Satsync-steered Mode 4.0 - 18.5 mA ISAT_Q_DUAL Satellite Quiescent Current for Dual Satellite Synchronous Satsync-steered Mode 8.0 - 26.5 mA ISAT_Q_TOTAL Total Bus Quiescent Current Synchronous TDM Mode 4.0 - 35 mA -10 -6.0 - 10 6.0 % 20 - 30 mA ISATSYNC_PULLDN ISAT ISAT_PD_LIM ISAT_OC ISAT_Q_RANGE_MIN ISAT_Q_SINGLE ISAT_MOD Satellite Quiescent Current Detect Accuracy 4.0 mA = Current Threshold = 14 mA 14 mA = Current Threshold = 35 mA Satellite Sensor Modulation Current ISAT_TH_RANGE Satellite Data Comparator Current Threshold Range 15.75 - 48.25 mA ISAT_TH_OFS Satellite Data Comparator Threshold Current Offset 11.25 12.5 13.75 mA ISAT_TH_HYST Satellite Data Detection Current Threshold Hysteresis 2.0 - 3.5 mA 33789 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(8)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SYNC PULSE LIMITS FOR SYNCHRONOUS TDM MODE (SEE Figure 5. SYNCHRONOUS TDM MODE SYNC PULSE TIMING) Vt0 Sync Slope Reference Voltage Vt2 Sync Signal Sustain Voltage - 0.5 - V 4.3 - 5.5 V DC Sensor Supply Regulator Current Limit 30 - 55 mA Current Difference Between the Regulator Overcurrent Detection Threshold and the Regulator Current Limit IDCREG_OC_DIFF = IDCREG_LMT - IDCREG_OC 1.0 9.0 18 V1 Regulated Output Voltage 1 1.35 1.5 1.73 V V2 Regulated Output Voltage 2 2.25 2.5 2.75 V V3 Regulated Output Voltage 3 4.5 5.0 5.5 V V4 Regulated Output Voltage 4 5.85 6.5 7.15 V - - 25 % DC SENSOR INTERFACE IDCREG_LMT IDCREG_OC_DIFF - Output Voltage Overshoot When Changing the Setting Measured as Percentage of the Voltage Step RDCREG_FBK Regulator Feedback Load Resistance 100 200 300 k ThDCREG_SD Regulator Thermal Shutdown Temperature 155 175 195 °C ThDCREG_HYS Regulator Thermal Shutdown Hysteresis 15 - 30 °C INx Load Capacitance 12.5 - 220 nF KCONV DC Sensor Interface Current to Voltage Conversion Factor (See Figure 21) IINx: 2.5 mA ~ 25 mA 0.163 0.177 0.190 VCONV_NLIN DC Sensor Interface Current to Voltage Conversion Nonlinearity - - 20 mVRMS 0.0 0.0 0.0 0.0 28 29 33 38 50 55 60 65 mV - - 1.0 V -110 -85 -30 µA CINx VINx_I_OFS VINx_OFS IINx_PULLDN Current Measurement Output Offset Voltage IINx = 0, CINx = 0.22 nF, RINx = 1.0 M V1 = 1.5 V V2 = 2.5 V V3 = 5.0 V V4 = 6.5 V INx Pin Offset Voltage Voltage Source not Enable and IINx = 0 INx Active Pull-down Current 2.0 V  VINx  7.15 V and INx is not selected (9) mA V/mA Notes 9. IDCREG_OC is the regulator overcurrent detection threshold to trigger the regulator switch between a voltage source and a current source. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(8)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes ANALOG OUTPUT VAOUT Analog Output Voltage GND - VCC V Analog Buffer Offset -20 - 20 mV A Analog Output Buffer Gain For Output Voltage Monitors For DC Sensor Interface INx Voltage Monitors 0.99 0.48 1.0 0.5 1.01 0.52 K1 Scale Factor of Pin VBST Monitor VBST  35 V 8.0 8.5 9.1 K2 Scale Factor of Pin VER Monitor VER  35 V 8.0 8.5 9.1 K3 Scale Factor of Pin VERDIAG Monitor 4.5 5.0 5.5 K4 Scale Factor of Pin VBUCK Monitor VBUCK  10 V 2.6 2.8 2.9 K5 Scale Factor of Pin VSYNC Monitor VSYNC  20 V 4.5 5.0 5.5 K6 Scale Factor of Pin VPWR Monitor VPWR  20 V 5.2 5.6 5.9 K7 Scale Factor of Pin OUTx_D Monitor 5.2 5.6 5.9 K8 Scale Factor of Pin OUTx_S Monitor 5.2 5.6 5.9 VAOUT_OFS CONFIGURABLE DRIVERS VOUTx_S_ON_HS Drain-Source On Voltage in High-side Driver Configuration VOUTx_D = 18 V, IOUTx_S = 70 mA VOUTx_D – 0.5 - VOUTx_D V VOUTx_D_ON_LS Drain-Source On Voltage in Low-side Driver Configuration VOUTx_S = 0 V, IOUTx_D = 70 mA VOUTx_S - VOUTx_S + 0.5 V IOUTx_S_LMT High-side Driver Current Limit VOUTx_D = 18 V, VOUTx_S = 0 V 70 - 110 mA IOUTx_D_LMT Low-side Driver Current Limit VOUTx_D = 18 V, VOUTx_S = 0 V -110 - -70 mA ThOUTx_SD Driver Thermal Shutdown Temperature 155 175 195 °C ThOUTx_HYS Driver Thermal Shutdown Hysteresis 15 - 30 °C -1.0 45 - 1.0 100 µA -1.0 -100 - 1.0 -45 µA 0.4 x VPWR - 0.6 x VPWR V -1.0 50 - 1.0 100 µA IOUTx_D_LEAK_GND Drain Leakage to GND VRESET = 0 V, or in Sleep Mode, VOUTx_D = 0 V IOUTx_D_LEAK_BAT Drain Leakage to Battery VRESET = 0 V, VOUTx_D = VPWR VOUTx_D_OPEN IOUTx_S_LEAK_GND VRESET = 5 V, VPWR = 18 V, Driver Off, VOUTx_D = 0 V VRESET = 5.0 V, VPWR =18 V, Driver Off, VOUTx_D = 18 V Open Drain Voltage VRESET = 5.0 V, Driver Off Source Leakage to GND VRESET = 0 V, or in Sleep Mode, VOUTx_S = 0 V VRESET = 5.0 V, VPWR = 18 V, Driver Off, VOUTx_S = 0 V 33789 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(8)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit 0.0 -100 - 300 -50 µA Open Source Voltage VRESET = 5.0 V, Driver Off 0.4 x VPWR - 0.6 x VPWR V VTH_2/3 2/3 VPWR Comparator Threshold for Diagnostics 6.0 V  VPWR  18 V 0.6 x VPWR 0.666 x VPWR 0.734 x VPWR V VTH_1/3 1/3 VPWR Comparator Threshold for Diagnostics 6.0 V  VPWR  18 V 0.266 x VPWR 0.333 x VPWR 0.4 x VPWR V DOUTx PWM Duty Cycle Fixed Frequency = 128 Hz, Increment step = 1.6% 0.0 - 100 % Notes CONFIGURABLE DRIVERS (CONTINUED) IOUTx_S_LEAK_BAT VOUTx_S_OPEN Source Leakage to Battery VRESET = 0 V, VOUTx_S = VPWR VRESET = 5.0 V, VPWR = 18 V, Driver Off, VOUTx_S = 18 V GENERAL LOGIC INPUTS: CS, CS_X, SCK, SI, ASST, SCRAP, CLK VLGIN_H Logic Input High 2.0 - VCC + 0.3 V VLGIN_L Logic Input Low -0.3 - 1.0 V 10 - 50 µA -2.0 - 5.0 µA ILGIN_PULLUP ILGIN_LEAK Logic Input Pull-up Current For CS: VLGIN = VCS  2.0 V For others: VLGIN  4.5 V Logic Input Leakage VLGIN = VDD SPI (OTHERS) AND SPI MONITOR INTERFACE VSO_L SO Voltage Low ISO = 0.5 mA - - 0.4 V VSO_H SO Voltage High ISO = -0.2 mA VCC - 0.4 - VCC V ANALOG SENSOR INPUT VIN_ANA Analog Sensor Input Voltage 0.0 - VCC V IIN_ANA Analog Sensor Input Pull-down Current 2.0 - 8.0 µA ARM ENABLE / DISABLE OUTPUTS VARM_H ARM / DISARM Output High VCC - 0.4 - VCC V VARM_L ARM / DISARM Output Low 0.0 - 0.4 V ARM / DISARM Output High-impedance Leakage -2.0 - 2.0 µA PPT Input Pull-down Resistance 100 230 400 k PPT Input Test Mode Enable Threshold 4.0 4.5 5.0 V IARM_LEAK PRODUCTION PROGRAM AND TEST INPUT RPPT_IN VPPT_TEST 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(8)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes LIN TRANSCEIVER LOGIC INTERFACE VRXD_OL RXD Output Low Level Voltage IRXD_IN  1.5 mA sinking current 0.0 — 0.9 VRXD_OH RXD Output High Level Voltage IRXD_OUT  250 A source current 4.25 — 5.25 V V VTXD_IL TXD Input Low Level Voltage — — 0.8 V VTXD_IH TXD Input High Level Voltage 2.0 — — V TXD Input Threshold Voltage Hysteresis 100 300 600 mV TXD Pull-up Current Source 1.0 V < VTXD < 3.5 V - 60 - 35 - 20 VTXD_IN_HYST ITXD_PULLUP A LIN TRANSCEIVER PHYSICAL LAYER (14),(12) VBAT Operating Voltage Range 8.0 – 18 V VSUP Operating Supply Voltage Range 7.0 – 18 V Supply Voltage Range (within which the device is not destroyed) -0.3 – 40 V 40 90 200 -1.0 – – – – 20 -1.0 – 1.0 VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V – – VBUSDOM Receiver Dominant State – VBUSREC Receiver Recessive State VBUS_CNT Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VSUP_NON_OP IBUS_LIM Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V IBUS_PAS_DOM Input Leakage Current at the Receiver Driver off; VBUS = 0 V; VBAT = 12 V IBUS_PAS_REC Leakage Output Current to GND Driver Off; 8.0 V VBAT  18 V; 8.0 V VBUS  18 V; VBUS  VBAT; IBUS_NO_GND Control Unit Disconnected from Ground GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V IBUSNO_BAT VHYS VBUS VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) mA mA µA mA (11) 100 µA (13) – 0.4* VSUP V 0.6* VSUP – – V 0.475* VSUP 0.5* VSUP 0.525* VSUP V – – 0.175* VSUP V VSERDIODE Voltage Drop at the Serial Diode in Pull-up Path 0.4 – 1.0 V VSHIFT_BAT VBAT_SHIFT 0.0 – 11.5% VBAT VSHIFT_GND GND_SHIFT 0.0 – 11.5% VBAT VUVL, VUVH LIN Undervoltage Threshold (positive and negative) 5.9 – 6.7 V – 100 – mV VUVHYST LIN Undervoltage Hysteresis (VUVL - VUVH) (10) 33789 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(8)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes LIN TRANSCEIVER PHYSICAL LAYER (CONTINUED) (14),(12) VBUSWU LIN Wake-up Threshold from Sleep Mode – 4.3 5.0 V RSLAVE LIN Pull-up Resistor to VSUP 20 40 60 k Notes 10. Voltage range at the battery level, including the reverse battery diode. 11. Loss of local ground must not affect communication in the residual network. 12. In this LIN Physical Layer EC section, use VSUP to represent VPWR and use VBUS to represent VLIN, in order to be consistent with the LIN Protocol Specification, and other Freescale LIN product specifications. 13. Node has to sustain the current that can flow under this condition. The bus must remain operational under this condition. 14. Guaranteed by design. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 7.0 V  VSUP(15)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes POWER MANAGEMENT tBSTSW Boost Switch Transistor Switching Time 20 50 150 ns tSYNCSW Sync Switch Transistor Switching Time 10 - 250 ns tVCC_RISE VCC Voltage Rise Time From 0.1xVCC to 0.9xVCC 200 - 1800 µs tVCC_VM_REJ VCC Voltage Monitor Deglitch Filter Time 45 50 55 µs tVCC_VM_RST VCC Voltage Monitor Reset Time Delay 10 - 15 ms tWDW_MIN Watchdog Refresh Window Lower Limit 275 - 400 µs tWDW_MAX Watchdog Refresh Window Upper Limit 650 - 900 µs - Reset Pin Activation Time for Watchdog Error 0.7 - 1.0 ms fBST/BUCK Boost and Buck Regulators Switch Frequency Low Speed Frequency High Speed Frequency 133 232 140 245 147 258 kHz fSYNC_CP Sync Supply Charge Pump Switch Frequency - 160 - kHz 3.92 3.98 4.00 4.00 4.08 4.02 MHz 118.75 125 131.25 kHz 45 47 - 55 53 % (16) SATELLITE SENSOR INTERFACE PSI5 fCLK Satellite Interface Input Clock Frequency Synchronous SATSYNC-steered mode Synchronous TDM mode fSAT Satellite bit Rate Operation Range DSAT_IMOD Satellite Sensor Current Modulation Duty Cycle Synchronous SATSYNC-steered mode Synchronous TDM mode tSAT_IMOD_FR Satellite Sensor Current Signal Rising and Falling Time From 10% to 90% of Modulation Amplitude 0.5 - 1.0 µs SRSAT_IMOD Satellite Sensor Current Signal Slew Rate 16 - 48 mA/µs tSAT_SYNC_FR Sync Pulse Rising and Falling Time 3.0 4.0 6.0 µs tSAT_IQ_FLT Satellite Quiescent Current Sampling Filter Time Constant - 60 - µs tSAT_IQ_DET Satellite Quiescent Current Out of Range Detection Time 3/fCLK - 4/fCLK µs tSAT_OC_DET Satellite Current Overcurrent Detection Time - 512 - µs 3.5 - 4.0 ms tSAT_OC_SDDEL Satellite Interface Overcurrent Shutdown Delay tSATSYNC_PER = 500 µs, tSAT_OC_DET = 512 µs tSAT_TH_DEL_ Satellite Data Detection Delay Difference Between Rising Edge and Falling Edge - - 250 ns tSAT_IQ_INIT_DEL Initial Satellite Quiescent Current Measurement Delay - 10 - ms tSAT_IQ_INIT_DUR Initial Satellite Quiescent Current Measurement Duration - 35 - ms Notes 15. VSUP is applied on the VPWR pin as a test condition. 16. The switching frequency used for the Boost and Buck supplies is selectable via the SPI with a LIN_CONFIG command at either a low-speed or high-speed switching mode. 33789 18 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(15)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SATELLITE SENSOR INTERFACE PSI5 (CONTINUED) tSAT_IQ_ DEL Satellite Quiescent Current Measurement Delay - 5.0 - µs tSAT_IQ _DUR Satellite Quiescent Current Measurement Duration - 3.0 - µs Satellite Quiescent Current Measurement Delay with No Bus Activity - 120 - µs tSAT_IQ_ DEL_NA SYNC PULSE LIMITS FOR SYNCHRONOUS TDM MODE (SEE Figure 5, Synchronous TDM Mode Sync Pulse Timing) t0 Reference Time Base - 0.0 - µs t1 Sync Signal Earliest Start - -3.0 - µs t2 Sync Signal Sustain Start 0 7.0 - µs - Sync Rising Slope Slew Rate 0.43 - 1.5 V/µs - Sync Falling Slope Slew Rate -1.5 - - V/µs t3 Sync Signal Sustain Time - 16 - µs t4 Sync Discharge Time Limit - 35 - µs 44 - - µs tSLOT1_START Start of First Sensor Data Word (Remaining discharge current < 2.0 mA) SATELLITE TIMING LIMITS FOR SYNCHRONOUS TDM MODE (SEE Figure 6, Synchronous TDM Mode Satellite Interface Timing) tSYNC tSATSYNC_WIDTH Sync Pulse Period 495 500 505 µs Satsync Input Pulse Width 40 - - µs tSLOT1_START Slot1 Start Time (relative to t0) - 44 - µs tSLOT2_START Slot2Start Time (relative to t0) - 181.3 - µs tSLOT3_START Slot3 Start Time (relative to t0) - 328.9 - µs tSLOT3_END Slot3 End Time (relative to t0) - 492 - µs -2.1 - 2.1 µs tEMC Timing Variation Margin SATELLITE TIMING LIMITS FOR SYNCHRONOUS SATSYNC-STEERED MODE (SEE Figure 7, Synchronous Satsync-Steered Mode Satellite Interface Timing) PSI5_x Activation Time from Rising Edge of Chip Select (1) 1.0 - 10 µs tSATSYNC_PER Satsync Period (2) 167 -  µs tSATSYNC_PH1 Satsync Phase 1 Time (3) - 200 - µs tSATSYNC_PH0 Satsync Phase 0 Time (4) - 170 - µs 250 - 750 ns tSAT_ACT tSATSYNC_S_DEL Satsync Sampling Delay Time (5) (1/ FSAT_CLK to 3/ FSAT_CLK) tSAT_SYNC_WIDTH Sync Pulse Width (6) - 32 34 µs Channel Stagger Time (7) (16/ FSAT_CLK) - 4.0 - µs tSAT_STAGGER tSAT_SYNC_GEN_DEL SYNC Pulse Generation Delay (8) - - 2.5 µs tSAT_SYNC_BLANK Sync Blanking Time (Decoder disabled) (9) - 69 - µs tSAT_PHASE_BLANK Phase Transition Blanking Time (Manchester Decoder disabled) (10) - 10 - µs 81.48 - 156.5 µs tSAT_MSG Message Time (11) 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP(15)  18 V, - 40 C  TA  125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes DC SENSOR INTERFACE AND ANALOG OUTPUT tMEAS DC Sensor Measurement Duration 0.5 - 2.0 ms tDCREG_SET Supply Regulator Setting Time VINx = 90% x V4 = 90% x 6.5 V, - - 70 µs |dVInx/dt| Regulator Output Switch Slew Rate 0.08 5.0 7.0 V/µs - - 40 70 135 190 210 mV/µs - 248 - µs tAOUT_SETL IInx = 20 mA, CInx = 10 nF Analog Output Settling Time CL = 0.22 nF, RL = 1.0 M AOUT = 90% final value AOUT = 99% final value µs CONFIGURABLE DRIVERS |dVOUTx/dt| tLATCH_DELAY Driver Output Switching Slew Rate Control 6.0 V < VOUTx