MCZ33903B5EK

Analog, Mixed-Signal and Power Management MC33903/4/5 System Basis Chip Gen2 with High Speed CAN and LIN Interface Overview The MC33903/4/5 is the second generation family of System Basis Chips, which combine several features and enhance present module designs. The device works as an advanced power management unit for the MCU and additional integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostics, protection, and fail safe operation mode. The SBC may include one or two LIN 2.1/J2602-2 interfaces with LIN master terminal outputs. It includes wake-up input pins than can also be configured as output drivers for flexibility. This device implements multiple Low Power modes with very low-current consumption. In addition, the device is part of a family concept where pin compatibility, among the various devices with and without LIN interfaces, adds versatility to module design. The MC33903/4/5 also implements an innovative and advanced fail-safe state machine and concept solution. This family of devices are supported by an enablement ecosystem that includes an evaluation board, software interface, EMC/ESD conformance reports and training material that allows a faster time to market and eases your designs. MC33903/4/5 Block Diagram MCU Voltage Regulator (VDD) Internal CAN Regulator (VCAN) Legend Low Power Modes SPI Adv W/D Flexible (I/O) 33903 33903S 33903D Secured State Machine CAN High Speed 33904 33905S Power Sharing (VDD BALLAST) 33905D Ballast Regulator (VAUX) LIN 1 LIN 2 Power Management Scalability • MCU power supply (VDD): 5.0 or 3.3 V / 150 mA (power split option for scalable needs - up to 300 mA) • 5.0 or 3.3 V voltage regulator (VAUX) for auxiliary loads • Dedicated 5.0 V voltage regulator (5 V CAN) for High Speed CAN Functional Safety • Innovative cranking pulse management during VDD low • Fail safe & configurable state machine • Enhanced protections and diagnostics Energy Savings • Ultra low power modes (typ 15 µA with VDD off) • Innovative Wake-up management and cyclic sense capability Robust Physical Layers • Certification to LIN 2.1, J2602-2, and ISO11898-2-5 standards • Successfully certified for stringent EMC, ISO, and ESD standards Easy to Use • Ecosystem to lower development time and simplify access • Debug mode to save time during application development Flexibility & Compatibility: • Selectable parameters (RST time, W/D type, VDD under-voltage threshold, VAUX 3.3 or 5.0 V) • 1 or 2 LIN options (33903S, 33905S and 33903D, 33905D) • Scalable (I/O pins configurable as wake-up inputs or output LIN master terminations) IDEAL COMPANION CHIP FOR MCU IN BODY, SAFETY, AND POWERTRAIN APPLICATIONS Segment Applications Proposed FSL MCU Body Body Controller S12x, MPC560x Gateway Seat Module Door Module Lighting Control Module S12x, MPC560x, S08x Column Module HVAC Cluster Safety & Chassis Seat Belt Pre-tensioner Electric Parking Brake S12x, MPC560x Steering Power Train Fuel Pump Water Pump S12x, S08x Glow Plug Engine Management Low End S12x, MPC563x Key Characteristics Parameter Characterization MCU Linear VREG (LDO) 5.0 / 3.3 V Output Current (300 mA for 33903D/S, 33904, 33905D/S with optional external PNP implementation) Bus Output CAN 33903D/S, 33905D/S only LIN Data Rate CAN 40 kB/s – 1.0 MB/s LIN 10.4 kB/s – 20 kB/s (100 kB/s in fast mode) Low Power VDD OFF/ VDD ON Current 15/25 µA ESD - Module Level (CAN and LIN) ±8000 V Operating Voltage 5.5 - 28 V Maximum Input Voltage 27 VDC, 40 V (Load Dump) Operating Temperature -40 °C