Freescale Semiconductor
Technical Data
Document Number: MC33989
Rev. 15.0, 6/2013
System Basis Chip with
High Speed CAN Transceiver
33989
The 33989 is a monolithic integrated circuit combining many
functions used by microcontrollers (MCU) found in automotive Engine
Control Units (ECUs). The device incorporates functions such as: two
voltage regulators, four high-voltage (wake-up) inputs, a 1.0 Mbaud
capable CAN physical interface, an SPI interface to the MCU and
VSUP monitoring and fault detection circuitry. The 33989 also
provides reset control in conjunction with VSUP monitoring and the
watchdog timer features. Also, an Interrupt can be generated, for the
MCU, based on CAN bus activity as well as mode changes.
SYSTEM BASIS CHIP
WITH HIGH SPEED CAN
Features
• VDD1: Low drop voltage regulator, current limitation,
overtemperature detection, monitoring, and reset function
• VDD1: Total current capability 200 mA
• V2: Tracking function of VDD1 regulator. Control circuitry for external
bipolar ballast transistor for high flexibility in choice of peripheral
voltage and current supply
• Low stand-by current consumption in Stop and Sleep modes
• High speed 1.0 MBaud CAN physical interface
• Four external high voltage wake-up inputs associated with HS1
VBAT switch
• 150 mA output current capability for HS1 VBAT switch allowing drive
of external switches pull-up resistors or relays
• VSUP failure detection
• 40 V maximum transient voltage
VDD1
ORDERING INFORMATION
Device
MC33989PEG/R2
Temperature
Range (TA)
Package
- 40 to 125 °C
28 SOICW
VPWR
33989
5.0 V
EG SUFFIX (PB-FREE)
98ASB42345B
28-PIN SOICW
VSUP
V2
GND
MCU
RST
INT
CS
SCLK
MOSI
MISO
SPI
CS
SCLK
MOSI
MISO
TX
RX
V2CTRL
V2
HS1
L0
L1
L2
L3
WD
Local Module Supply
Wake-Up Inputs
Safe Circuits
CANH
Twisted
CANL
Pair
Figure 1. MC33989 Simplified Application Diagram
*This document contains certain information on a product under development.
Freescale reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007 - 2013. All rights reserved.
CAN Bus
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
V2CTRL
VSUP Monitor Dual
Voltage Regulator
VDD1 Monitor
VSUP
V2
VDD1
HS1 Control
HS1
L0
L1
Programmable
Wake-Up Inputs
Oscillator
INT
Interrupt
Watchdog
Reset
WD
RST
Mode Control
L2
CS
L3
RX
CAN H
High Speed
1.0 MB/s CAN
Physical
Interface
SCLK
SPI
Interface
TX
MOSI
MISO
V2
GND
CAN L
Figure 2. 33989 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
RX
TX
VDD1
RST
INT
GND
GND
GND
GND
V2
V2CTRL
VSUP
HS1
L0
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
WD
CS
MOSI
MISO
SCLK
GND
GND
GND
GND
CANL
CANH
L3
L2
L1
Figure 3. 33989 Pin Connections
Table 1. 33989 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
1
RX
Output
Receive Data
CAN bus receive data output pin.
2
TX
Input
Transmit Data
CAN bus transmit data input pin.
3
VDD1
Power
Output
Voltage Digital Drain
One
5.0 V regulator output pin. Supply pin for the MCU.
This is the device reset output pin whose main function is to reset the
MCU. This pin has an internal pullup current source to VDD.
4
RST
Output
Reset
5
INT
Output
Interrupt
This output is asserted LOW when an enabled interrupt condition occurs.
The output is a push-pull structure.
6–9
20–23
GND
Ground
Ground
These device ground pins are internally connected to the package lead
frame to provide a 33989-to-PCB thermal path.
10
V2
Input
Voltage Source Two
Sense input for the V2 regulator using an external series pass transistor.
V2 is also the internal supply for the CAN transceiver.
11
V2CTRL
Power
Voltage Control
Output drive source for the V2 regulator connected to the external series
pass transistor.
Output
12
VSUP
Power
Voltage Supply
Supply input pin for the 33989.
13
HS1
Output
High Side One
Output of the internal high side switch. The output current is internally
limited to 150 mA.
14–17
L0:L3
Input
Level 0: 3
Inputs from external switches or from logic circuitry.
22
CANH
Output
CAN High
CAN high output pin.
23
CANL
Output
CAN Low
CAN low output pin.
24
SCLK
Input
System Clock
25
MISO
Output
Master In/Slave Out
SPI data sent to the MCU by the 33989. When CS is HIGH, the pin is in
the high-impedance state.
26
MOSI
Input
Master Out/Slave In
SPI data received by the 33989.
27
CS
Input
Chip Select
The CS input pin is used with the SPI bus to select the 33989.
28
WD
Output
Watch Dog
The WD output pin is asserted LOW if the software watchdog is not
correctly triggered.
Clock input pin for the serial peripheral interface (SPI).
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Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Continuous (Steady-state)
VSUP
-0.3 to 27
Transient Voltage (Load Dump)
VSUP
-0.3 to 40
VLOG
-0.3 to VDD1 + 0.3
V
I
Internally Limited
A
Voltage
V
-0.3 to VSUP + 0.3
V
Output Current
I
Internally Limited
A
VESDH
- 4.0 to 4.0
ELECTRICAL RATINGS
Power Supply Voltage at VSUP
V
Logic Signals (RX, TX, MOSI, MISO, CS, SCLK, RST, WD, and INT)
Output Current VDD1
HS1
ESD Voltage, Human Body Model (1)
kV
HS1, L0, L1, L2, L3
All Other Pins
-2.0 to 2.0
ESD Voltage Machine Model
VESDM
All Pins Except CANH and CANL
V
±200
L0, L1, L2, L3
VWUDC
DC Input Voltage
-0.3 to 40
V
DC Input Current
-2.0 to 2.0
mA
Transient Input Voltage with External Component (2)
-100 to 100
V
VCANH/L
-27 to 40
V
ICANH/L
200
mA
VTRH/L
40
V
VTRH/L
-40 to 40
V
V
-0.5 to 6.0
V
ESD Voltage (HBM 100 pF, 1.5 k) CANL, CANH
VESDCH
-4.0 to 4.0
KV
ESD Voltage Machine Model
VESDCM
CANL and CANH Continuous Voltage
CANL and CANH Continuous Current
CANH and CANL Transient Voltage (Load Dump)
CANH and CANL Transient Voltage
(5)
Logic Inputs (TX and RX)
CANH and CANL
(4)
V
-200 to 200
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, 1.5 k), the Machine Model (MM) (CZAP = 200 pF,
RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
2.
3.
4.
According to ISO 7637 specification. See Table 6, page 24.
Load Dump test according to ISO 7637 part 1.
Transient test according to ISO 7637 part 1, pulses 1, 2, 3a, and 3b according to schematic in Table 17, page 37.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Operating Junction Temperature
TJ
-40 to 150
C
Storage Temperature
TS
-55 to 165
C
TA
-40 to 125
C
RJ/P
20
C/W
TPPRT
Note 7.
°C
THERMAL RATINGS
Ambient Temperature
Thermal Resistance Junction to GND Pins
(5)
Peak Package Reflow Temperature During Reflow
(6) (7)
,
Notes
5. Ground pins 6, 7, 8, 9, 20, 21, 22, and 23
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP
5.5
—
18
V
4.5
—
5.5
18
—
27
POWER INPUT (VSUP)
Nominal DC Supply Voltage Range
Extended DC Voltage Range 1
VSUPEX1
Reduced Functionality (8)
Extended DC Voltage Range 2 (9)
VSUPEX2
Input Voltage During Load Dump
VSUPLD
Load Dump Situation
—
40
VSUPJS
Jump Start Situation
V
—
Supply Current in Standby Mode (10) (11)
(10)
Supply Current in Sleep Mode (10) (11)
mA
—
42
45
—
42.5
45
mA
ISUP(SLEEP1)
VDD1 and V2 OFF, VSUP < 12 V, Oscillator Running
Sleep-Disable State
(12)
CAN in
Supply Current in Sleep Mode (10) (11)
µA
—
72
105
—
57
90
—
100
150
—
135
210
ISUP(SLEEP2)
VDD1 and V2 OFF, VSUP < 12 V, Oscillator Not Running (12) CAN in
Sleep-Disable State
Supply Current in Sleep Mode (10) (11)
µA
ISUP(SLEEP3)
VDD1 and V2 OFF, VSUP > 12 V, Oscillator Running (12) CAN in
Sleep-Disable State
Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (10) (11)
(12)
VDD1 ON, VSUP < 12 V, Oscillator Not Running
Sleep-Disable State
(12)
µA
ISUP(STOP1)
CAN in
Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (11)
µA
ISUP(STOP2)
CAN in
Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (10) (11)
µA
—
130
210
—
160
230
1.5
3.0
4.0
ISUP(STOP3)
VDD1 ON, VSUP > 12 V, Oscillator Running (12) CAN in
Sleep-Disable State
BATFAIL Flag Internal Threshold
27
ISUP(NORM)
IOUT at VDD1 = 40 mA CAN recessive or Sleep-Disable State
VDD1 ON, VSUP < 12 V, Oscillator Running
Sleep-Disable State
—
ISUP(STDBY)
IOUT at VDD1 = 40 mA CAN recessive or Sleep-Disable State
VBF
V
V
—
Input Voltage During Jump Start
Supply Current in Normal Mode
V
µA
V
Notes
8. VDD1 > 4.0 V, Reset high, logic pin high level reduced, device is functional.
9.
10.
11.
12.
Device is fully functional. All functions are operating. All modes available and operating. Watchdog, HS1 turn ON turn OFF, CAN cell
operating, L0:L3 inputs operating, SPI read/write operation. Overtemperature may occur.
Current measured at the VSUP pin.
With CAN cell in Sleep-Disable state. If CAN cell is Sleep-Enabled for wake-up, an additional 60 µA must be added to specified value.
Oscillator running means Forced Wake-up or Cyclic Sense of Software Watchdog is Stop mode are not activated.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
BATFAIL Flag Hysteresis (13)
Battery Fall Early Warning Threshold
Symbol
Min
Typ
Max
Unit
VBF(HYS)
—
1.0
—
V
BFEW
In Normal and Standby Mode
5.3
Battery Fall Early Warning Hysteresis
In Normal and Standby Mode
POWER OUTPUT (VDD1)
V
5.8
6.3
BFEWH
(13)
V
0.1
0.2
0.3
4.9
5.0
5.1
(14)
VDD1 Output Voltage
VDD1OUT
IDD1 from 2.0 to 200 mA TAMB -40 to 125 °C, 5.5 V < VSUP < 27 V
VDD1 Output Voltage
V
VDD1OUT2
IDD1 from 2.0 to 200 mA, 4.5 V < VSUP < 5.5 V
Dropout Voltage
V
4.0
—
—
—
0.2
0.5
VDD1DRP
IDD1 = 200 mA
Dropout Voltage, Limited Output Current
V
VDD1DRP2
IDD1 = 50 mA, 4.5 V < VSUP
IDD1 Output Current
V
—
0.1
0.25
200
285
350
160
—
200
125
—
160
20
—
40
4.5
4.6
4.7
4.1
4.2
4.3
1.0
—
—
IDD1
Internally Limited
Junction Thermal Shutdown
mA
TSD
Normal or Standby Modes
Junction Overtemperature Pre-warning
°C
TPW
VDDTEMP Bit Set
Temperature Threshold Difference
TSD - TPW
Reset Threshold 1
°C
RSTTH1
Selectable by SPI. Default Value After Reset.
Reset Threshold 2
V
RSTTH2
Selectable by SPI
VDD1 Range for Reset Active
VDDR
Reset Delay Time
V
tD
Measured at 50% of Reset Signal
—
4.0
Line Regulation (C at VDD1 = 47 µF Tantal)
LR1
LR2
Load Regulation (C at VDD1 = 47 µF Tantal)
VSUP = 13.5 V, 1 = -100 mA Not Tested
mV
5.0
25
10
25
25
75
mV
LD
1.0 mA < IIDD < 200 mA
mV
—
Thermal Stability
µs
—
5.5 < VSUP < 27 V, IDD = 10 mA
THERMS
(15)
V
30
—
9.0 V VSUP < 18, IDD = 10 mA
Line Regulation (C at VDD1 = 47 µF Tantal)
°C
mV
—
30
50
Notes
13. With CAN cell in Sleep-Disable state. If CAN cell is Sleep-Enabled for wake-up, an additional 60 µA must be added to specified value.
14. IDD1 is the total regulator output current. VDD specification with external capacitor. Stability requirement: C > 47 µF ESR < 1.3
(tantalum capacitor). In reset, normal request, normal and standby modes. Measure with C = 47 µF Tantalum.
15. Guaranteed by design; however, it is not production tested.
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
4.75
5.00
5.25
4.75
5.00
5.25
IDD1SWU
10
17
25
mA
IDD1DGLT
40
55
75
µs
Reset Threshold
RSTSTOP1
4.5
4.6
4.7
V
Reset Threshold
RSTSTOP2
4.1
4.2
4.3
V
—
5.0
25
—
15
75
—
—
200
POWER OUTPUT (VDD1) IN STOP MODE (16)
VDD1 Output Voltage
VDDSTOP
IDD1 < = 2.0 mA
VDD1 Output Voltage
VDDSTOP2
IDD1 < = 10 mA
IDD1 Stop Output Current to Wake-up SBC
IDD1 Overcurrent to Wake-up Deglitcher Time
(17)
Line Regulation (C at VDD1 = 47 µF Tantal)
Load Regulation (C at VDD1 = 47 µF Tantal)
TRACKING VOLTAGE REGULATOR (V2)
VDDst-cap
V2
I2 from 2.0 to 200 mA, 5.5 V < VSUP < 27 V
I2 Output Current (for information only)
0.99
1.0
1.01
200
—
—
0.0
—
10
3.75
4.0
4.25
0.0
—
1.0
VDD1-0.9
—
VDD1
-2.0
—
2.0
mA
12CTRL
Worst Case at TJ = 125 °C
V2LTH
mA
V
(20)
Low Level Output Voltage
VOL
IOUT = 1.5 mA
High Level Output Voltage
Tri-Stated MISO Leakage Current
V
VOH
IOUT = 250 µA
0 V < VMISO < VDD
µF
VDD1
I2
Depending Upon External Ballast Transistor
V2LOW Flag Threshold
mV
(19)
V2 Output Voltage (C at V2 = 10 µF Tantal)
V2 Control Drive Current Capability
mV
LDS
1.0 mA < IDD < 10 mA
Max Decoupling Capacitor at VDD1 Pin, in Stop Mode(18)
V
LRS
5.5 V < VSUP < 27 V, IDD = 2.0 mA
LOGIC OUTPUT PIN (MISO)
V
V
IHZ
µA
Notes
16. If stop mode is used, the capacitor connected at VDD pin should not exceed the maximum specified by the “VDDST-CAP” parameter.
17.
18.
19.
20.
If capacitor value is exceeded, upon entering stop mode, VDD output current may exceed the IDDSWU and prevent the device to stay in
stop mode.
Guaranteed by design; however, it is not production tested.
Guaranteed by design.
V2 specification with external capacitor
- Stability requirement: C > 42 µF and ESR < 1.3 (Tantalum capacitor), external resistor between base and emitter required
- Measurement conditions: Ballast transistor MJD32C, C = 10 µF Tantalum, 2.2 k resistor between base and emitter of ballast transistor
Push/Pull structure with tri-state condition CS high.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
High Level Input Voltage
VIH
0.7 VDD1
—
VDD1 + 0.3
V
Low Level Input Voltage
VIL
-0.3
—
0.3 VDD1
V
High Level Input Current on CS
LIH
-100
—
-20
µA
Low Level Input Current on CS
LIL
-100
—
-20
µA
MOSI and SCLK Input Current
LN
-10
—
10
µA
-300
-250
-150
0.0
—
0.9
0.0
—
0.9
2.3
—
5.0
3.0
3.4
4.0
0.0
—
0.9
VOH
VDD1-0.9
—
VDD1
V
Low Level Output Voltage (I0 = 1.5 mA)
VOL
0.0
—
0.9
V
High Level Output Voltage (I0 = 250 µA)
VOH
VDD1-0.9
—
VDD1
V
—
2.0
2.5
LOGIC INPUT PINS (MOSI, SCLK, CS)
RESET PIN (RST)
(21)
High Level Output Current
IOH
0 < VOUT < 0.7 VDD
Low Level Output Voltage (I0 = 1.5 mA)
VOL
5.5 V < VSUP < 27 V
Low Level Output Voltage (I0 = 0 µA
Reset Duration After VDD1 High
RSTDUR
mA
ms
(22)
Low Level Output Voltage (I0 = 1.5 mA)
VOL
1.0 V < VSUP < 27 V
High Level Output Voltage (I0 = 250 µA)
INTERRUPT PIN (INT)
V
IPDW
V > 0.9 V
WATCHDOG OUTPUT PIN (WD)
V
VOL
1.0 V < VSUP < 5.5 V
Reset Pull-down Current
µA
V
(22)
HIGH SIDE OUTPUT PIN (HS1)
RDSON at TJ = 25 °C, and IOUT - 150 mA
RDSON at TA = 125 °C, and IOUT - 150 mA
RON125
VSUP > 9.0 V
RDSON at TA = 125 °C, and IOUT - 120 mA
RON25
VSUP > 9.0 V
—
—
4.5
—
3.5
5.5
RON125-2
5.5 < VSUP < 9.0 V
Output Current Limitation
LLIM
160
—
500
mA
HS1 Overtemperature Shutdown
OVT
155
—
190
°C
LLEAK
—
—
10
µA
-1.5
—
-0.3
HS1 Leakage Current
Output Clamp Voltage at IOUT = -10 mA
No Inductive Load Drive Capability
VCL
V
Notes
21. Push/Pull structure with tri-state condition CS high.
22. Output pin only. Supply from VDD1. Structure switch to ground with pull-up current source.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
5.5 V < VSUP < 6.0 V
2.0
2.5
3.0
6.0 V < VSUP < 18 V
2.5
3.0
3.6
18 V < VSUP < 27 V
2.7
3.2
3.7
5.5 V < VSUP < 6.0 V
2.7
3.3
3.8
6.0 V < VSUP < 18 V
3.0
4.0
4.6
18 V < VSUP < 27 V
3.5
4.2
4.7
Unit
LOGIC INPUTS (L0:L3)
Negative Switching Threshold
Positive Switching Threshold
Hysteresis
VTHN
VTHP
V
VHYS
5.5 V < VSUP < 27 V
Input Current
V
V
0.6
—
1.3
-10
—
10
—
1.5
3.0
—
2.0
6.0
—
55
70
—
—
1.0
LIN
-0.2 V < VIN < 40 V
µA
CAN SUPPLY (V2)
Supply Current Cell
IRES
Recessive State
Supply Current Cell
IDOM
Dominant State without Bus Load
Supply Current Cell, CAN in Sleep State Wake-up Enable
V2 Regulator OFF (23)
mA
ISLEEP
V2 Regulator OFF
Supply Current Cell, CAN in Sleep State Wake-up Disable
mA
µA
IDIS
µA
Notes
23. Push/Pull structure.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VCM
-27
—
40
Unit
CANH AND CANL
Bus Pins Common Mode Voltage
Differential Input Voltage (Common Mode Between -3.0 and 7.0 V)
VCANH-VCANL
Recessive State at RXD
—
—
500
Dominant State at RXD
900
—
—
Differential Input Hysteresis (RXD)
V
mV
VHYS
100
—
—
mV
Input Resistance
RIN
5.0
—
100
K
Differential Input Resistance
RIND
10
—
100
K
ICANUP
—
—
1.5
mA
TXD Dominant State
VCANHD
2.75
—
4.5
TXD Recessive State
VCANHR
—
—
3.0
TXD Dominant State
VCANLD
0.5
—
2.25
TXD Recessive State
VCANLR
2.0
—
—
TXD Dominant State
VDIFFD
1.5
—
3.0
V
TXD Recessive State
VDIFFR
—
—
100
mV
CANH
ICANH
—
—
-35
CANL
ICANL
35
Overtemperature Shutdown
TSHUT
160
180°C
—
CANL Overcurrent Detection
ICANL/OC
60
—
200
-200
—
-60
Unpowered Node Input Current
CANH Output Voltage
V
CANL Output Voltage
V
Differential Output Voltage
CANH AND CANL
Output Current Capability (Dominant State)
mA
Error Reported in CANR
CANH Overcurrent Detection
mA
ICANH/OC
Error Reported in CANR
°C
mA
TX AND RX
TX Input High Voltage
VIH
0.7 VDD
—
VDD + 0.4
V
TX Input Low Voltage
VILP
-0.4
—
0.3 VDD
V
TX High Level Input Current, VTX = VDD
LIH
-10
—
10
µA
TX Low Level Input Current, VTX = 0 V
LIL
-100
-50
-20
µA
RX Output Voltage High, IRX = 250 µA
VOH
VDD-1
—
—
V
RX Output Voltage Low, IRX = 1.0 mA
VOL
—
—
0.5
V
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V VSUP 18 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
FREQ
0.25
—
4.0
MHz
DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO)
SPI Operation Frequency
SCLK Clock Period
tPCLK
250
—
N/A
ns
SCLK Clock High Time
tWSCLKH
125
—
N/A
ns
SCLK Clock Low Time
tWSCLKH
125
—
N/A
ns
Falling Edge of CS to Rising Edge of SCLK
tLEAD
100
—
N/A
ns
Falling Edge of SCLK to Rising Edge of CS
tLAG
100
—
N/A
ns
MOSI to Falling Edge of SCLK
tSISU
40
—
N/A
ns
Falling Edge of SCLK to MOSI
tSIH
40
—
N/A
ns
MISO Rise Time (CL = 220 pF)
tRSO
—
25
50
ns
MISO Fall Time (CL = 220 pF)
tFSO
—
25
50
ns
—
—
50
—
—
50
—
—
50
18
—
34
Time from Falling or Rising Edges of CS to:
MISO Low-impedance
tSOEN
tSODIS
MISO High-impedance
Time from Rising Edge of SCLK to MISO Data Valid
ns
tVALID
0.2 V1 = = 0.8 V1, CL = 200 pF
ns
STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WD, INT)
Delay Between CS Low to High Transition (End of SPI Stop Command) and
Stop Mode Activation Detected by V2 OFF (24)
Interrupt Low Level Duration
tCSSTOP
tINT
SBC in Stop Mode
µs
7.0
Internal Oscillator Frequency
All Modes Except Sleep and Stop
10
13
OSCF1
(24)
Internal Low Power Oscillator Frequency
Sleep and Stop Modes
µs
Normal and Standby Modes
100
—
8.58
9.75
10.92
39.6
45
50.4
88
100
112
308
350
392
-12
—
12
kHz
ms
ms
ms
WD4
Normal and Standby Modes
Watchdog Period Accuracy
—
WD3
Normal and Standby Modes
Watchdog Period 4
—
WD2
Normal and Standby Modes
Watchdog Period 3
100
WD1
Normal and Standby Modes
Watchdog Period 2
—
OSCF2
(24)
Watchdog Period 1
kHz
ms
f1ACC
%
Notes
24. Guaranteed by design; however it is not production tested.
33989
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 7.0 V VSUP 18 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Normal Request Mode Timeout
Typ
Max
308
350
392
6.82
9.75
12.7
31.5
45
58.5
70
100
130
245
350
455
-30
—
30
3.22
4.6
5.98
NRTOUT
Normal Request Modes
Watchdog Period 1 - Stop
Watchdog Period 2 - Stop
ms
WD2STOP
Stop Mode
Watchdog Period 3 - Stop
ms
WD3STOP
Stop Mode
Watchdog Period 4 - Stop
ms
WD4STOP
Stop Mode
Stop Mode Watchdog Period Accuracy
ms
f2ACC
Stop Mode
Cyclic Sense/FWU Timing 1
%
CSFWU1
Sleep and Stop Modes
Cyclic Sense/FWU Timing 2
ms
CSFWU2
Sleep and Stop Modes
ms
6.47
Cyclic Sense/FWU Timing 3
9.25
12
CSFWU3
Sleep and Stop Modes
Cyclic Sense/FWU Timing 4
ms
12.9
18.5
24
25.9
37
48.1
51.8
74
96.2
66.8
95.5
124
134
191
248
271
388
504
200
350
500
-30
—
30
tSHSON
—
—
22
µs
tSHSOFF
—
—
22
µs
9.0
—
22
CSFWU4
Sleep and Stop Modes
Cyclic Sense/FWU Timing 5
ms
CSFWU5
Sleep and Stop Modes
Cyclic Sense/FWU Timing 6
ms
CSFWU6
Sleep and Stop Modes
Cyclic Sense/FWU Timing 7
ms
CSFWU7
Sleep and Stop Modes
Cyclic Sense/FWU Timing 8
ms
CSFWU8
Sleep and Stop Modes
Cyclic Sense ON Time
ms
tON
Sleep and Stop Modes Threshold and Condition to be Added
Cyclic Sense/FWU Timing Accuracy
µs
tACC
Sleep and Stop Modes
Delay Between SPI Command and HS1 Turn ON (25)
Delay Between SPI Command and HS1 Turn OFF
(25)
(25)
Normal Mode
%
tSV2ON
Standby Mode
Delay Between SPI and V2 Turn OFF (25)
Unit
ms
WD1STOP
Stop Mode
Delay Between SPI and V2 Turn ON
Min
µs
tSV2OFF
µs
9.0
—
22
Notes
25. Delay starts at falling edge of clock cycle #8 of the SPI command and start of Turn ON or Turn OFF of HS1 or V2.
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 7.0 V VSUP 18 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Delay Between Normal Request and Normal Mode After WD Trigger Command
tSNR2N
Normal Request Mode
Delay Between SPI and CAN Normal Mode
SBC Normal Mode
35
70
—
—
10
µs
µs
—
10
µs
15
40
90
tWSPI
tS1STSPI
Unit
µs
tWCS
SBC in Stop Mode
Delay Between INT Pulse and First SPI Command Accepted
15
—
SBC in Stop Mode
Delay Between CS Wake-up (CS Low to High) and First Accepted API
Command
Max
tSCANS
(26)
Delay Between CS Wake-up (CS Low to High) and SBC Normal Request Mode
(VDD1 on and Reset High)
Typ
tSCANN
SBC Normal Mode (26)
Delay Between SPI and CAN Normal Mode
Min
µs
90
—
20
—
In Stop Mode After Wake-up
N/A
µs
N/A
INPUT TERMINNALS (L0, L1, L2, AND L3)
Wake-up Filter Time
tWUF
8.0
20
38
µs
tDOUT
200
360
520
µs
Slew Rate 3
70
140
210
Slew Rate 2
80
155
225
Slew Rate 1
100
180
255
Slew Rate 0
110
220
310
Slew Rate 3
20
65
110
Slew Rate 2
40
80
150
Slew Rate 1
60
120
200
Slew Rate 0
100
160
300
30
80
140
CAN MODULE-SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL)
Dominant State Timeout
Propagation Loop Delay TX to RX, Recessive to Dominant
Propagation Delay TX to CAN
tLRD
ns
tTRD
Propagation Delay CAN to RX, Recessive to Dominant
tRRD
Propagation Loop Delay TX to RX, Dominant to Recessive
tLDR
ns
ns
Slew Rate 3
70
120
170
Slew Rate 2
90
135
180
Slew Rate 1
100
160
220
Slew Rate 0
130
200
260
Propagation Delay TX to CAN
tTDR
ns
Slew Rate 3
60
110
130
Slew Rate 2
65
120
150
Slew Rate 1
75
150
200
Slew Rate 0
90
190
300
20
40
60
Propagation Delay CAN to RX, Dominant to Recessive
tRDR
ns
Notes
26. Guaranteed by design; however, it is not production tested.
33989
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 7.0 V VSUP 18 V, - 40C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Slew Rate 3
tSL3
4.0
19
40
Slew Rate 2
tSL2
3.0
13.5
20
tSL1
2.0
8.0
15
tSL0
1.0
5.0
10
Non Differential Slew Rate (CANL or CANH)
V/µs
Slew Rate 1
Slew Rate 0
CANH
Pulse Width
Filter
CANL
Unit
WU Receiver
Pulse OK
Latch
Counter
RST
RST
Narrow
Pulse
+
WU
OUT
Timeout
Timeout
Generator
Standby
Figure 4. Wake-up Block Diagram
The block diagram in Figure 4 illustrates how the wake-up signal is generated. First the CAN signal is detected by a low
consumption receiver (WU receiver). Then the signal passes through a pulse width filter, which discards the undesired pulses.
The pulse must have a width bigger than 0.5 µs and smaller than 500 µs to be accepted. When a pulse is discarded the pulse
counter is reset and no wake signal is generated, otherwise when a pulse is accepted the pulse counter is incremental and after
three pulses the wake signal is asserted.
1nF
LX
10 k
GND
Transient Pulse
Generator
(Note)
GND
Note: Waveform in accordance to
ISO 7637 part1, test pulses 1, 2, 3a and 3b.
Figure 5. Transient Test Pulse for L0:L3 Inputs
Each one of the pulses must be spaced by no more than 500 µs. In that case, the pulse counter is reset and no wake signal
is generated. This is accomplished by the wake timeout generator. The wake-up cycle is completed (and the wake flag reset)
when the CAN interface is brought to CAN Normal mode.
The wake-up capability of the CAN can be disabled, refer to SPI interface and register section, CAN register.
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
1.0 nF
CANH
Transient Pulse
Generator
(Note)
CANL
GND
1.0 nF
GND
Note: Waveform in accordance to
ISO 7637 part1, test pulses 1, 2, 3a and 3b.
Figure 6. Transient Test Pulses for CANH/CANL
TX
TTRD
2.0 V
0.8 V
TTDR
TLRD
TX
VDIFF
0.9 V
2.0 V
0.5 V
VDIFF = VCANH - VCANL
0.8 V
TLDR
2.0 V
RX
TRDR
0.9 V
VDIFF
TRRD
0.8 V
RX
0.5 V
2.0 V
0.8 V
Figure 7. Transceiver AC Characteristics
33989
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
tPCLK
CS
tWCLKH
tLEAD
tLAG
SCLK
tWCLKL
tSISU
MOSI
Undefined
tSIH
Di 0
Don’t Care
Di 8
Don’t Care
tVALID
tSODIS
tSOEN
MISO
Do 0
Do 8
Notes:
Incoming data at MOSI pin is sampled by the SBC at SCLK falling edge.
Outgoing data at MISO pin is set by the SBC at SCLK rising edge (after tVALID delay time).
Figure 8. SPI Timing Characteristics
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
•
•
•
•
•
The 33989 is an integrated circuit dedicated to automotive applications. Its functions include:
One full protected voltage regulator with 200 mA total output current capability available at the VDD1 external pin
Driver for an external path transistor for the V2 regulator function
Reset, programmable watchdog function, interrupt, and four operational modes
Programmable wake-up input and Cyclic Sense wake-up
CAN high speed physical interface
FUNCTIONAL PIN DESCRIPTION
RECEIVE AND TRANSMIT DATA (RXD AND TXD)
The RX and TX pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol
handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is
HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive).
VOLTAGE DIGITAL DRAIN ONE (VDD1)
The VDD1 pin is the output pin of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against
overcurrent and overtemperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator
temperature exceeds 130 °C typical. When the temperature exceeds the overtemperature shutdown (170 °C typical), the
regulator is turned off.
VDD1 includes an undervoltage reset circuitry, which sets the RST pin LOW when VDD1 is below the undervoltage reset
threshold.
RESET (RST)
The Reset pin RST is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device
is not in reset mode. RST includes an internal pull-up current source. When RST is LOW, the sink current capability is limited,
allowing RST to be shorted to 5.0 V for software debug or software download purposes.
INTERRUPT (INT)
The Interrupt pin INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR).
When an interrupt occurs, INT stays LOW until the interrupt source is cleared.
INT output also reports a wake-up event by a 10 s typical pulse when the device is in Stop mode.
VOLTAGE SOURCE TWO (V2)
The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0 V
supply of the internal CAN interface. It is possible to connect V2 to an external 5.0 V regulator or to the VDD1 output when no
external series pass transistor is used. In this case, the V2CTRL pin must be left open.
VOLTAGE SOURCE 2 CONTROL (V2CTRL)
The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor.
VOLTAGE SUPPLY (VSUP)
The VSUP pin is the battery supply input of the device.
HIGH-SIDE ONE (HS1)
The HS1 pin is the internal high side driver output. It is internally protected against overcurrent and overtemperature.
LEVEL 0-3 INPUTS (L0:L3)
The L0:L3 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be
read by SPI. These inputs can be used as wake-up events for the SBC when operating in the Sleep or Stop mode.
33989
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL)
The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TX input level, and the state
of CANH and CANL is reported through RX output. A 60 termination resistor is connected between CANH and CANL pins.
SYSTEM CLOCK (SCLK)
SCLK is the System Clock input pin of the serial peripheral interface.
MASTER IN SLAVE OUT (MISO)
MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through
the MISO pin.
MASTER OUT SLAVE IN (MOSI)
MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through
this pin.
CHIP SELECT (CS)
CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected.
WATCHDOG (WD)
The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered.
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
DEVICE SUPPLY
The device is supplied from the battery line through the VSUP pin. An external diode is required to protect against negative
transients and reverse battery. It can operate from 4.5 V and under the jump start condition at 27 Vdc. This pin sustains standard
automotive voltage conditions such as load dump at 40 V. When VSUP falls below 3.0 V typical the 33989 detects it and stores
the information into the SPI register in a bit called BATFAIL. This detection is available in all operation modes.
The device incorporates a battery early warning function, providing a maskable interrupt when the VSUP voltage is below 6.0
V typical. A hysteresis is included. Operation is only in Normal and Standby modes. VSUP low is reported in the Input/Output
Register (IOR).
VDD1 VOLTAGE REGULATOR
The VDD1 Regulator is a 5.0 V output voltage with output current capability up to 200 mA. It includes a voltage monitoring
circuitry associated with a reset function. The VDD1 regulator is fully protected against overcurrent and short-circuit. It has over
temperature detection warning flags (bit VDDTEMP in MCR and interrupt registers), and overtemperature shutdown with
hysteresis.
V2 REGULATOR
V2 Regulator circuitry is designed to drive an external path transistor increasing output current flexibility. Two pins are used
to achieve the flexibility. Those pins are V2 and V2 control. The output voltage is 5.0 V and is realized by a tracking function of
the VDD1 regulator. The recommended ballast transistor is MJD32C. Other transistors can be used; however, depending upon
the PNP gain an external resistor-capacitor network might be connected. The V2 is the supply input for the CAN cell. The state
of V2 is reported in the IOR (bit V2LOW set to 1 if V2 is below 4.5 V typical).
HS1 VBAT SWITCH OUTPUT
The HS1 output is a 2.0 typical switch from the VSUP pin. It allows the supply of external switches and their associated pullup or pull-down circuitry, in conjunction with the wake-up input pins, for example. Output current is limited to 200 mA and HS1 is
protected against short-circuit and has an overtemperature shutdown (bit HS1OT in IOR and bit HS1OT-V2LOW in INT register).
The HS1 output is controlled from the internal register and the SPI. Because of an internal timer, it can be activated at regular
intervals in Sleep and Stop modes. It can also be permanently turned on in Normal or Standby modes to drive loads or supply
peripheral components. No internal clamping protection circuit is implemented, thus a dedicated external protection circuit is
required in case of inductive load drive.
BATTERY FALL EARLY WARNING
Refer to the discussion under the heading: Device Supply.
INTERNAL CLOCK
The device has an internal clock used to generate all timings (Reset, Watchdog, Cyclic Wake-up, Filtering Time, etc.). Two
oscillators are implemented. A high accuracy (±12 percent) used in Normal Request, Normal and Standby modes, and a low
accuracy (±30 percent) used in Sleep and Stop modes.
OPERATIONAL MODES
FUNCTIONAL MODES
The device has four primary operation modes:
1. Standby mode
2. Normal mode
3. Stop mode
4. Sleep mode
All modes are controlled by the SPI. An additional temporary mode called Normal Request mode is automatically accessed
by the device after reset or wake-up from Stop mode. A Reset (RST) mode is also implemented. Special modes and configuration
are possible for debug and program MCU flash memory.
33989
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
STANDBY MODE
Only regulator 1 is ON. Regulator 2 is turned OFF by disabling the V2 control pin. Only the wake-up capability of the CAN
interface is available. Other functions available are wake-up input reading through SPI and HS1 activation. The Watchdog is
running.
NORMAL MODE
In this mode, both regulators are ON. This corresponds to the normal application operation. All functions are available in this
mode (Watchdog, wake-up input reading through SPI, HS1 activation, CAN communication). The software Watchdog is running
and must be periodically cleared through SPI.
STOP MODE
Regulator 2 is turned OFF by disabling the V2 control pin. The regulator 1 is activated in a special low power mode, allowing
to deliver few mA. The objective is to maintain the MCU of the application supplied while it is turned into power saving condition
(i.e Stop or Wait modes). In Stop mode the device supply current from VBAT is very low.
When the application is in Stop mode (both MCU and SBC), the application can wake-up from the SBC side (for example:
cyclic sense, forced wake-up, CAN message, wake-up inputs and overcurrent on VDD1), or the MCU side (key wake-up, etc.).
Stop mode is always selected by the SPI. In Stop mode the software Watchdog can be running or idle depending upon
selection by the SPI (RCR, bit WDSTOP). To clear the watchdog, the SBC must be awakened by a CS pin (SPI wake-up). In
Stop mode, SBC wake-up capability are identical as in Sleep mode. Please refer to Table 5.
SLEEP MODE
Regulators 1 and 2 are OFF. The current from VSUP pin is reduced. In this mode, the device can be awakened internally by
cyclic sense via the wake-up inputs pins and HS1 output, from the forced wake-up function and from the CAN physical interface.
When a wake-up occurs the SBC goes first into reset mode before entering Normal Request mode.
RESET MODE
In this mode, the Reset (RST) pin is low and a timer is running for a time RSTDUR. After this time is elapsed, the SBC enters
Normal Request mode. Reset mode is entered if a reset condition occurs (VDD1 low, watchdog timeout or watchdog trigger in a
closed window).
NORMAL REQUEST MODE
This is a temporary mode automatically accessed by the device after the reset mode, or after the SBC wake-up from
Stop mode. After wake-up from the Sleep mode or after the device power-up, the SBC enters the Reset mode before entering
the Normal Request mode. After a wake-up from the Stop mode, the SBC enters Normal Request mode directly.
In Normal Request mode the VDD1 regulator is ON, V2 is OFF, the reset pin is high. As soon as the device enters the Normal
Request mode an internal 350 ms timer is started. During these 350 ms the microcontroller of the application must address the
SBC via the SPI, configuring the Watchdog register. This is the condition for the SBC to stop the 350 ms timer and to go into the
Normal or Standby mode and to set the watchdog timer according to configuration.
NORMAL REQUEST ENTERED AND NO WD CONFIGURATION OCCURS
In case the Normal Request mode is entered after SBC power-up, or after a wake-up from Stop mode, and if no WD
configuration occurs while the SBC is in Normal Request mode, the SBC goes to Reset mode after the 350 ms time period is
expired before again going into Normal Request mode. If no WD configuration is achieved, the SBC alternatively goes from
Normal Request into reset, then Normal Request modes etc.
In case the Normal Request mode is entered after a wake-up from Sleep mode, and if no WD configuration occurs while the
SBC is in Normal Request mode, the SBC goes back to Sleep mode.
APPLICATION WAKE-UP FROM SBC SIDE
When an application is in Stop mode, it can wake-up from the SBC side. When a wake-up is detected by the SBC (for example,
CAN, Wake-up input, etc.) the SBC turns itself into Normal Request mode and generates an interrupt pulse at the INT pin.
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
APPLICATION WAKE-UP FROM MCU SIDE
When application is in Stop mode, the wake-up event may come from the MCU side. In this case the MCU signals to the SBC
by a low to high transition on the CS pin. Then the SBC goes into Normal Request mode and generates an interrupt pulse at the
INT pin.
STOP MODE CURRENT MONITOR
If the VDD1 output current exceed an internal threshold (IDD1SWU), the SBC goes automatically into Normal Request mode and
generates an interrupt at the INT pin. The interrupt is not maskable and the interrupt register will has no flag set.
INTERRUPT GENERATION WHEN WAKE-UP FROM STOP MODE
When the SBC wakes up from Stop mode, it first enters the Normal Request mode before generating a pulse (10 µs typical)
on the INT pin. These interrupts are not maskable, and the wake-up event can be read through the SPI registers (CANWU bit in
Reset Control Register (RCR) and LCTRx bit in Wake-up Register (WUR). In case of wake-up from Stop mode over current or
from forced wake-up, no bit is set. After the INT pulse the SBC accept SPI command after a time delay (tS1STSPI parameter).
SOFTWARE WATCHDOG IN STOP MODE
If Watchdog is enabled, the MCU has to wake-up independently of the SBC before the end of the SBC watchdog time. In order
to do this, the MCU must signal the wake-up to the SBC through the SPI wake-up (CS activation). The SBC then wakes up and
jumps into the Normal Request mode. MCU has to configured the SBC to go to either Normal or Standby mode. The MCU can
then decide to go back again to Stop mode.
When there is no MCU wake-up occurring within the watchdog timing, the SBC activates the Reset pin, jumping into the
Normal Request mode. The MCU can then be initialized.
STOP MODE ENTER COMMAND
Stop mode is entered at the end of the SPI message, and at the rising edge of the CS. Please refer to the t CSSTOP data in the
Dynamic Electrical Characteristics.
Once Stop mode is entered the SBC could wake-up from the V1 regulator overcurrent detection. In order to allow time for the
MCU to complete the last CPU instruction, allowing the MCU to enter its low power mode, a deglitcher time of typical 40 µs is
implemented.
Figure 9 indicates the operation to enter Stop mode.
SPI Stop/ Sleep Command
SPI CS
tCSSTOP
SBC in Normal or Stand-by mode
IDD1DGLT
SBC in Stop mode
no IDD1 over I wake-up
SBC in Stop mode
with IDD1over I wake-up
Figure 9. Operation Entering Stop Mode
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
SOFTWARE WATCHDOG (SELECTABLE WINDOW OR TIMEOUT WATCHDOG)
Software watchdog uses in the SBC Normal and Standby modes is to monitor MCU. The Watchdog can be either window or
timeout. This is selectable by SPI (register TIM1, bit WDW). Default is window watchdog. The period for the watchdog is
selectable from the SPI from 10 ms to 350 ms (register TIM1, bits WDT0 and WDT1). When the window watchdog is selected,
the closed window is the first part of the selected period, and the open window is the second part of the period. Refer to the SPI
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
TIM register description. Watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the
closed window will generate a reset. Watchdog is cleared through SPI by addressing the TIM1 register.
RESET PIN DESCRIPTION
A reset output is necessary and available to reset the microcontroller. Modes 1 and 2 are available for the reset pin (please
refer to Table 5 for reset pin operation).
Reset causes when SBC is in mode 1:
• VDD1 falling out of range — If VDD1 falls below the reset threshold (parameter RSTTH), the RST pin is pulled low until VDD1
returns to the normal voltage.
• Power-on reset — At device power-on or at device wake-up from Sleep mode, the reset is maintained low until VDD1 is within
its operation range.
Watchdog timeout — If watchdog is not cleared, the SBC will pull the reset pin low for the duration of the reset time (parameter
RSTDUR).
Table 5. Reset and Watchdog Output Operation
Events
Mode
WD Output
Reset Output
1 or 2 (Safe Mode)
Low to High
Low to High
VDD1 Normal Watchdog Properly Triggered
1
High
High
VDD1 < RSTTH
1
High
Low
Watchdog Timeout Reached
1
Low (Note)
Low
VDD1 Normal Watchdog Properly Triggered
2 (Safe Mode)
High
High
VDD1 < RSTTH
2 (Safe Mode)
High
Low
Watchdog Timeout Reached
2 (Safe Mode)
Low (Note)
High
Devices Power-up
Notes
27. WD stays low until the Watchdog register is properly addressed through SPI.
In Mode 2, the reset pin is not activated in case of Watchdog timeout. Please refer to Table 6 for more detail.
For debug purposes at 25 °C, the Reset pin can be shorted to 5.0 V because of its internal limited current drive capability.
RESET AND WATCHDOG OPERATION: MODES1 AND 2
Watchdog and Reset functions have two modes of operation:
1. Mode 1
2. Mode 2 (also called Safe mode)
These modes are independent of the SBC modes (Normal, Standby, Sleep, and Stop). Modes 1 and 2 selection is achieved
through the SPI (register MCR, bit SAFE). Default mode after reset is Mode 1.
Table 5 provides Reset and Watchdog output mode
of operation. Two modes (modes 1 and 2) are available and can be selected through the SPI Safe bit. Default operation, after
reset or power-up, is Mode 1.
In both modes reset is active at device power-up and wake-up.
• In mode 1–Reset is activated in case of VDD1 fall or watchdog not triggered. WD output is active low as soon as reset goes
low. It remains low as long as the watchdog is not properly re-activated by the SPI.
• In mode 2–(Safe mode) Reset is not activated in case of watchdog fault. WD output has the same behavior as in mode 1–The
Watchdog output pin is a push-pull structure driving external components of the application for signal instance of an MCU
wrong operation.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
Table 6. Table of Operation
Mode
Voltage Regulator
HS1 Switch
Normal
Request
VDD1:ON
V2:OFF
HS1:OFF
Normal
VDD1:ON
V2:ON
HS1:Controllable
Wake-up
Capabilities
(if enabled)
—
—
Reset Pin
INT
Software
Watchdog
CAN Cell
Low for Reset-DUR
Time, then High
—
—
—
Normally High
Active Low if WD or
VDD1 undervoltage
occurs (and mode 1
selected)
If Enabled, Signal
Failure (VDD1 PreWarning Temp,
CAN, HS1)
Running
Tx/Rx
Running
Low Power
Standby
VDD1:ON
V2:OFF
HS1:Controllable
—
Same as Normal
Mode
Same as Normal
Mode
Stop
VDD1:ON
(Limited Current
Capability)
V2:OFF
HS1:OFF or Cyclic
CAN
SPI
L0:L3
Cyclic Sense
Forced Wake-up
IDD1 Over Current
Normally High
Signal SBC Wakeup and
IDD > IDD1S/WU
(Not Maskable)
(28)
Sleep
Active Low if WD
(29)
or VDD1
Undervoltage
Occurs
Not Active
Running if Enabled
Low Power
Not Running if
Wake-up Capability
Disabled
if Enabled
VDD1:OFF
V2:OFF
HS1:OFF or Cyclic
CAN
SPI
L0:L3
Cyclic Sense
Forced Wake-up
Low
Not Running
Low Power
Debug
Normal
Same as Normal
—
Normally High
Active Low if VDD1
Undervoltage
Occurs
Same as Normal
Not Running
Same as Normal
Debug
Standby
Same as Standby
—
Normally High
Active Low if VDD1
Undervoltage
Occurs
Same as Standby
Not Running
Same as Standby
Stop Debug
Same as Stop
Same as Stop
Normally High
Active Low if VDD1
Undervoltage
Occurs
Same as Stop
Not Running
Same as Stop
Flash
Programming
Forced Externally
—
Not Operating
Not Operating
Not Operating
Not Operating
Wake-up Capability
if Enabled
Notes
28. Always enable.
29. If enabled.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
Watchdog Timeout
VDD1
RST
WD
MODE 1
Watchdog
Period
SPI
WD Clear
SPI CS
MODE 2
RST
WD
Watchdog Register
Addressed
Figure 10. Reset and Watchdog Functions Diagram in Modes 1 and 2
WAKE-UP CAPABILITIES
Several wake-up capabilities are available for the device when it is in Sleep, or Stop modes. When a wake-up has occurred,
the wake-up event is stored into the WUR or CAN registers. The MCU can then access to the wake-up source. The wake-up
options are able to be selected through the SPI while the device is in Normal or Standby mode and prior to entering low power
mode (Sleep or Stop mode). When a wake-up occurs from sleep mode the device activates VDD1. It generates an interrupt if
wake-up occurs from Stop mode.
WAKE-UP FROM WAKE-UP INPUTS (L0:L3) WITHOUT CYCLIC SENSE
The wake-up lines are dedicated to sense external switch states and if changes occur to wake-up the MCU (in Sleep or Stop
modes). The wake-up pins are able to handle 40 V DC. The internal threshold is 3.0 V typical and these inputs can be used as
an input port expander. The wake-up inputs state are read through SPI (register WUR).
In order to select and activate direct wake-up from the LX inputs, the WUR register must be configured with the appropriate
level sensitivity. Additionally, the LPC register must be configured with 0x0 data (bits LX2HS1and HS1AUTO are set at 0).
Level sensitivity is selected by WUR register. Level sensitivity is configured by a pair of Lx inputs: L0 and L1 level sensitivity
are configured together while L2 and L3 are configured together.
CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0, L1, L2, L3)
The SBC can wake-up upon state change of one of the four wake-up input lines (L0, L1, L2 and L3) while the external pull-up
or pull down resistor of the switches associated to the wake-up input lines are biased with HS1 VSUP switch. The HS1 switch is
activated in Sleep or Stop modes from an internal timer. Cyclic Sense and Forced Wake-up are exclusive. If Cyclic Sense is
enabled the forced wake-up can not be enabled.
In order to select and activate the cyclic sense wake-up from the Lx inputs the WUR register must be configured with the
appropriate level sensitivity, and the LPC register must be configured with 1xx1 data (bit LX2HS1 set at 1 and bit HS1AUTO set
at 1). The wake-up mode selection (direct or cyclic sense) is valid for all 4 wake-up inputs.
FORCED WAKE-UP
The SBC can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and Forced wakeup are exclusive. If Forced wake-up is enabled (FWU bit set to 1 in LPC register) the Cyclic Sense can not be enabled.
CAN INTERFACE WAKE-UP
The device incorporates a high-speed 1MBaud CAN physical interface. Its electrical parameters for the CANL, CANH, RX and
TX pins are compatible with ISO 11898 specification (IS0 11898: 1993(E)). The control of the CAN physical interface operation
is accomplished through the SPI. CAN modes are independent of the SBC operation modes.
The device can wake-up from a CAN message if the CAN wake-up is enabled. Please refer to the CAN module description
for detail of wake-up detection.
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Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
SPI WAKE-UP
The device can wake-up by the CS pin in Sleep or Stop modes. Wake-up is detected by the CS pin transition from low to a
high level. In Stop mode, this corresponds with the condition where the MCU and SBC are in Stop mode; and when the
application wake-up event comes through the MCU.
DEVICE POWER-UP, SBC WAKE-UP
After device or system power-up, or after the SBC wakes up from Sleep mode, it enters into Reset mode prior to moving into
Normal Request mode.
DEBUG MODE: HARDWARE AND SOFTWARE DEBUG WITH THE SBC
When the SBC is mounted on the same printed circuit board as the microcontroller it supplies, both application software and
SBC dedicated routine must be debugged. The following features allow debug of the software by allowing the possibility of
disabling the SBC internal software Watchdog timer.
DEVICE POWER-UP, RESET PIN CONNECTED TO VDD1
At SBC power-up the VDD1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs
every 350 ms. In order to allow software debug and avoid MCU reset, the Reset pin can be connected directly to VDD1 by a
jumper.
DEBUG MODES WITH SOFTWARE WATCHDOG DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY
AND STOP DEBUG)
The Watchdog software can be disabled through SPI. To avoid unwanted watchdog disable while limiting the risk of disabling
Watchdog during SBC normal operation, the watchdog disable must be achieved the following sequence:
• Step 1–Power down the SBC
• Step 2–Power-up the SBC (The BATFAIL bit is set, allowing the SBC to enter Normal Request mode)
• Step 3–Write to TIM1 register allowing SBC entering Normal mode
• Step 4–Write to MCR register with data 0000, enabling the Debug mode. Complete SPI byte: 000 1 0000
• Step 5–Write to MCR register normal debug (0001x101)
• Step 6–To leave the Debug mode, write 0000 to MCR register
While in Debug mode, the SBC can be used without having to clear the WD on a regular basis to facilitate software and
hardware debug.
At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350 ms time
period of the Normal Request mode. If this step is not accomplished in a timely manner, the SBC will go into Reset mode, entering
Normal Request again.
When the SBC is in Debug mode, and set in Stop Debug or Sleep Debug, when a wake-up occurs the SBC enters Normal
Request mode for a time period of 350 ms. To avoid the SBC generating a reset (enter Reset mode) the desired next Debug
mode (Normal Debug or Standby Debug) should be configured within the 350 ms time period of the Normal Request mode. For
details, please refer to State Machine in Debug mode, Figure 16.
To avoid entering Debug mode after a power-up, first read BATFAIL bit (MCR read) and write 0000 into MCR. Figure 15
illustrates the Debug mode enter.
VSUP
VDD1
Batfail
TIM1(Step 3)
MCR (Step5)
MCR (Step6)
SPI
MCR(Step4)
Debug Mode
SPI: Read Batfail
SBC in Debug Mode, No WD
SBC Not in Debug Mode and WD ON
Figure 11. Debug Mode Enter
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
MCU FLASH PROGRAMMING CONFIGURATION
To download software into the application memory (MCU EEPROM or Flash) the SBC capabilities allows the VDD1 to be forced
by an external power supply to 5.0 V; the reset and WD outputs by external signal sources are forced to zero or 5.0 V, both
without damage. This allows, for example, supply of the complete application board by external power supply, applying the
correct signal to reset pins. No function of the SBC is operating.
Due to pass transistor from VDD1 to VSUP, supplying the device from VDD1 pin biases the VSUP pin. Therefore, VSUP should
not be forced to a value above 5.0 V. The Reset pin is periodically pulled low for RSTDUR time (3.4 ms typical) before being pulled
to VDD1 for 350 ms typical. During the time reset is low, the reset pin sinks 5.0 mA maximum (LPDW parameter).
VDD1
VSUP (Open or > 5.0 V
SBC
RST
MCU = Flash
Programming Bus
WD
External supply and sources applied to VDD1, RST,
and WD test points on application circuit board.
Figure 12. Simplified Schematic for Flash Programming
PACKAGE AND THERMAL CONSIDERATION
The device is proposed in a standard surface mount SOIC28 package. In order to improve the thermal performances of the
SOIC28 package, eight pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board.
Table 6 describes the SBC operation modes. Normal, Stand-by, and Stop Debug modes are entered through special
sequence described in the Debug mode paragraph.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
WD: Timeout OR VDD1 Low
WD:
Reset Counter (3.4
ms) Expired
&
Nostop
SPI: Stand-by
& WD Trigger
2
Reset
Timeout
Normal
1
Stand-by
3
Stop
WD: Timeout OR VDD1 Low
SPI: Stop & CS
Low to High
Transition
Normal
1
Wake-up
(VDD1 High Temperature OR (VDD11 Low > 100ms & VSUP >BFew)) & Nostop &!BATFAIL
1
2
3
4
Nostop & SPI:
Sleep & CS Low
2
1
SPI: Normal
er
V
DD
1L
ow
(3
0)
SPI: Stand-by
O
R
SP
to I: S
H to
ig p
h &
Tr C
an S
si L o
tio w
n
ut
Wake-up
eo
4
g
rig
:T
D
Power
Down
Ti
m
VDD1 Low OR WD:
Timeout 350 ms
&!Nostop
W
SBC
Power-
W
D:
Nostop & SPI: Sleep &
CS Low to High
1
Sleep
denotes priority
STATE MACHINE DESCRIPTION:
30. Nostop = Nostop bit = 1
31. ! Nostop = Nostop bit = 0
32. BATFAIL = Batfail bit = 1
33. ! BATFAIL = Batfail bit = 0
34. VDD1 Over Temperature = VDD1 thermal shutdown occurs
35.
VDD1 low = VDD1 below reset threshold
36.
VDD1 low >100 ms = VDD1 below reset threshold for more than 100 ms
37.
38.
WD: Trigger = TIM1 register write operation.
VSUP > BFew = VSUP > Battery Fall Early Warning (6.1 V typical)
39.
WD: Timeout = TIM1 register not written before WD timeout period expired, or WD written in incorrect time window if window WD
selected (except stop mode). In Normal Request mode timeout is 355 ms p2.2 (350 ms p3) ms.
SPI: Sleep = SPI write command to MCR register, data sleep
SPI: Stop = SPI write command to MCR register, data stop
SPI: Normal = SPI write command to MCR register, data normal
SPI: Stand-by = SPI write command to MCR register, data stand-by
40.
41.
42.
43.
Figure 13. State Machine (Not Valid in Debug Modes)
Notes These two SPI commands must be sent consecutively in this sequence.
30. If WD activated.
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FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
Power-Up
Behavior after power-up if no trigger appears
Behavior after reset of BATFAIL if no trigger appears
Reset
Normal
Request
Yes
No
Trigger
Batfail
No
No
No Stop
Yes
Sleep
Yes
Normal
Figure 14. Behavior at SBC Power-up
WD: Timeout 350 ms
Reset Counter
(3.4 ms) Expired
Power
Down
Reset
WD: Trigger
Normal Request
Normal
SPI: MCR (0000) & Normal Debug
SPI: MCR (0000) & Standby Debug
Normal Debug
Stand-by Debug
Figure 15. Transitions to Enter Debug Modes
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Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
WD: Timeout 350 ms
igg
e
R
r
R
R
y
or
db
:N
ma
lD
St
an
SP
I
Normal
D
eb
ug
Standby
&!BATFAILNOSTOP
& SPI: Sleep
: Tr
Sleep
SPI: Normal Debug
SPI: Stop Debug & CS Low to
High Transition
SPI: Stop
Stop Debug
WD
R
Wake-up
Reset
eb
E
ug
SP
I:
R
SPI: Stand-by &
WD: Trigger
W
ak
eup
R
Reset Counter
(3.4 ms) Expired
Normal Request
Stand-by
Wake-up
E
SPI:
Stop (1)
Stand-by Debug
SPI: Standby Debug
Normal Debug
SPI: Normal Debug
R
R
(1) If Stop mode entered, it is entered without watchdog, no matter the WDSTOP bit.
(E) Debug mode entry point (Step 5 of the Debug mode entering sequence).
(R) Represents transitions to Reset mode due to VDD1 low.
Figure 16. Simplified State Machine in Debug Modes
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
Table 7 illustrates a register, an 8-bit SPI. The first three bits are used to identify the internal SBC register address. Bit four is
a read/write bit. The last four bits are Data Send from MCU to SBC, or read back from SBC to MCU.
There is no significance during write operation state of MISO.
During read operation only the final four bits of MISO have a meaning (content of the accessed register).
The following tables describe the SPI register list, and register bit meaning.
Registers reset value is also described along with the reset condition. Reset condition is the condition causing the bit to be set
at the reset value.
Table 7. Data Format Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A2
A1
A0
R/W
D3
D2
D1
D0
Read operation: R/W Bit = 0
Write operation: R/W Bit = 1
Possible reset conditions include:
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Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SBC Reset:
Power-On Reset POR
SBC Mode Transition: NR2R - Normal Request to Reset Mode
NR2N - Normal Request to Normal Mode
NR2STB - Normal Request to Standby
Mode
N2R - Normal to Reset Mode
STB2R - Standby to Reset Mode
STO2R - Stop to Reset Mode
STO2NR - Stop to Normal Request
SBC Mode:
RESET - SBC in Reset Mode
Table 8. List of Registers
Name
Address
Description
MCR
$000
Mode Control Register
Comment and Use
Write: Control of Normal, Standby, Sleep, Stop, Debug Modes
Read: BATFAIL flag and other status bits and flags
RCR
$001
Reset Control Register
Write: Configuration for reset voltage level, Safe bit, Stop mode
Read: CAN wake-up and CAN failure status bits
CAN
$010
CAN Control Register
Write: CAN module control: TX/RX and Sleep modes, slope control, wake
enable/disable
Read: CAN wake-up and CAN failure status bits
IOR
$011
I/O Control Register
Write: HS1 (High Side switch) control in Normal and Standby mode
Read: HS1 over temp bit, VSUP and V2 Low status
WUR
TIM
$100
$101
Wake-up Input
Register
Write: Control of wake-up input polarity
Timing Register
Write: TIM1, Watchdog timing control, window, or Timeout mode
Read: Wake-up input and real time LX input state
Write: TIM2, Cyclic sense and force wake-up timing selection
LPC
$110
Low Power Mode
Control Register
Write: Control HS1 periodic activation in Sleep and Stop modes, force
wake-up
INT
$111
Interrupt Register
Write: Interrupt source configuration
Read: INT source
NOTE: For SPI Operation
In case a low pulse is asserted by the device on the RST output pin during a SPI message,
the SPI message can be corrupted. An RST low pulse is asserted in 2 cases:
Case 1: W/D refresh issue: The MCU does not perform the SPI watchdog refresh command
before the expiration of the timeout (in Normal mode or Normal Request mode and if the
“Timeout watchdog” option is selected), or the SPI watchdog refresh command is performed
in the closed window (in Normal mode and if “Window watchdog” option is selected).
Case 2: VDD undervoltage condition: VDD falls below the VDD undervoltage threshold.
Message corruption means that the targeted register address can be changed, and another
register is written. Table 9 shows the various cases and impacts on SPI register address:
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31
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 9. Possible Corrupted Registers In Case of RST Pulse During SPI Communication
Resulting Written register
Target
written
register
Register
MCR
RCR
CAN
IOR
Address
$000
$001
$010
$011
Register
Address
CAN
$010
IOR
$011
WUR
$100
TIM1/2
$101
LPC
$110
INTR
$111
X
X
X
X
X
X
X
X
Four registers can be corrupted: MCR, RCR, CAN, and IOR registers. As examples:
•
write to CAN register can end up as write to MCR register, or
•
write to TIM1 register can end up as write to RCR register
To avoid the previously described behavior, it is recommended to write into the MCR, RCR,
CAN, and IOR registers with the expected configuration, after each RST assertion.
In the application, a RST low pulse leads to an MCU reset and a software restart. By
applying this recommendation, all registers will be written with the expected configuration.
Mode Control Register (MCR)
Table 10 provides Mode Control Register data.
Table 10. MCR Register
MCR
D3
D2
D1
D0
W
—
MCTR2
MCTR1
MCTR0
R
BATFAIL (31)
VDDTEMP
GFAIL
WDRST
Reset Value
—
0
0
0
Reset Condition
—
POR, RESET
POR, RESET
POR, RESET
$000B
Notes
31. Bit BATFAIL cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0 V.
Table 11. MCR Control Bits
MCTR2
MCTR1
MCTR0
SBC Mode
Description
0
0
0
Enter/Exit Debug Mode
To enter/exit Debug Mode, refer to detail
Debug Mode: Hardware and Software Debug...
0
0
1
Normal
—
0
1
0
Standby
—
0
1
1
Stop, Watchdog OFF (32)
0
1
1
1
0
0
Stop, Watchdog ON
Sleep (33)
(32)
—
—
—
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 11. MCR Control Bits
1
0
1
Normal
1
1
0
Standby
1
1
1
Stop
No watchdog running, Debug Mode
Notes
32. Watchdog ON or OFF depends on RCR bit D3.
33. Before entering Sleep mode, bit BATFAIL in MCR must be previously cleared (MCR read operation), and bit NOSTOP in RCR must be
previously set to 1.
Table 12. MCR Status Bits
Status Bits
GFAIL
BATFAIL
VDDTEMP
WDRST
Description
Logic OR of CAN Failure (TXF Permanent Dominant, or CAN Over Current or CAN thermal), or HS1
Overtemperature, or V2 Low
Battery Fail Flag (set when VSUP < 3.0 V)
Temperature Pre-warning on VDD (latched)
Watchdog Reset Occurred
Reset Control Register (RCR)
Table 13 provides Reset Control Register data while Table 14 outlines the RCR Control Bits, and Table 15 provides RCR
Status Bits data.
Table 13. RCR Register
RCR
D3
D2
D1
D0
WDSTOP
NOSTOP
SAFE
RSTTH
Reset Value
1
0
0
0
Reset Condition
POR,RST,
STO2NR
POR, NR2N NR2STB
POR
POR
$001B
W
R
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 14. RCR Control Bits
SAFE
WD Pin
Reset Pin
0
0
0=>1
1
1
Condition
Device Power-Up
1
0
1
V1 Normal, WD Properly Triggered
1
0
1
0
1
1
1
0
0
0
1
V1 Drops Below RSTTH
WD Timeout
1
Table 15. RCR Status Bits
Status Bits
Bit Value
WDSTOP
0
No Watchdog in Stop Mode
1
Watchdog Runs in Stop Mode
0
Device Cannot Enter Sleep Mode
1
Sleep Mode Allowed, Device Can Enter Sleep Mode
0
Reset Threshold 1 Selected (typ 4.6 V)
1
Reset Threshold 2 Selected (typ 4.2 V)
NOSTOP
RSTTH
Description
CAN Register (CAN)
Table 16 provides control of the high-speed CAN module, mode, slew rate, and wake-up.
Table 16. CAN Register
CAN
D3
D2
D1
D0
W
—
SC1
SC0
MODE
R
CANWU
TXF
CUR
THERM
Reset Value
—
0
0
0
Reset Condition
—
POR
POR
POR
$010B
High Speed CAN Transceiver Modes
The mode bit (D0) controls the state of the CAN module, Normal or Sleep modes. See Table 17. SC0 bit (D1) defines the slew
rate when the CAN module is in Normal mode, and controls the wake-up option (wake-up enable or disable) when the CAN
module is in Sleep mode. CAN module modes (Normal and Sleep) are independent of the SBC modes. Please see Table 18.
Table 17. CAN High Speed Transceiver Modes
SC1
SC0
MODE
CAN Mode
0
0
0
CAN Normal, Slew Rate 0
0
1
0
CAN Normal, Slew Rate 1
1
0
0
CAN Normal, Slew Rate 2
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 17. CAN High Speed Transceiver Modes
1
1
0
CAN Normal, Slew Rate 3
x
1
1
CAN Sleep and CAN Wake-up Disable
x
0
1
CAN Sleep and CAN Wake-up Enable
Table 18. CAN Status Bits
Status Bits
Description
CANWU
CAN Wake-up Occurred
TXF
Permanent Dominant TX
CUR(1)
CAN Transceiver in Current Limitation
THERM
CAN Transceiver in Thermal Shutdown
Error bits are latched in the CAN registers. Bit (1) CUR is set to 1 when the CAN interface is programmed into CAN NORMAL
for the first time after V2 turn ON. To clear the CUR bit, follow this procedure:
• Turn V2 ON (SBC in Normal mode and V2 above V2 threshold) the CAN interface must be set into CAN Sleep
• Return to CAN NORMAL
Input/Output Control Register (IOR)
Table 19 provides data about HS1 control in Normal and Standby modes, while Table 20 provides control bit data.
Table 19. IOR Register
IOR
D3
D2
D1
D0
W
—
HS1ON
—
—
R
V2LOW
HS1OT
VSUPLOW
DEBUG
Reset Value
—
0
—
—
Reset Condition
—
POR
—
—
$011B
Table 20. IOR Control Bits
HS1ON
HS1 State
0
HS1 OFF, in Normal and Standby Modes
1
HS1 ON, in Normal and Standby Modes
When HS1 is turned OFF due to an over temperature condition, it can be turned ON again by setting the appropriate control
bit to 1. Error bits are latched in the Input/Output Registers (IOR). See Table 21.
Table 21. IOR Status Bits
Status Bit
Description
V2LOW
V2 Below 4.0 V
HS1OT
High Side 1 Overtemperature
VSUPLOW
DEBUG
VSUP Below 6.1 V
If Set, SBC Accepts Command to go to Debug Modes (No WD)
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Wake-up Input Register (WUR)
The local wake-up inputs, L0, L1, L2, and L3 can be used in both Normal and Standby modes as port expander, as well as
and for waking up the SBC in Sleep or Stop modes. See Table 22.
Table 22. WUR Register
WUR
$100B
D3
D2
D1
D0
W
LCTR3
LCTR2
LCTR1
LCTR0
R
L3WU
L2WU
L1WU
L0WU
0
0
0
Reset Value
0
Reset Condition
POR, NR2R, N2R, STB2R, STO2R
The wake-up inputs can be configured separately, while L0 and L1 are configured together. Bits L2 and L3 are configured
together. See Table 23.
Table 23. WUR Control Bits
LCTR3
LCTR2
LCTR1
LCTR0
L0/L1 Config
L2/L3 Config
x
x
0
0
Inputs Disabled
—
x
x
0
1
High Level Sensitive
x
x
1
0
Low Level Sensitive
x
x
1
1
Both Level Sensitive
0
0
x
x
—
0
1
x
x
High Level Sensitive
1
0
x
x
Low Level Sensitive
1
1
x
x
Both Level Sensitive
Inputs Disabled
Table 24 provides Status bits data.
Table 24. WUR Status Bits
Status Bit
L3WU
Description
Wake-up Occurred (Sleep/Stop Modes), Logic State on Lx (Standby/Normal Modes)
L2WU
L1WU
L0WU
Notes: Status bits have two functions. After SBC wake-up, they indicate the wake-up source (Example: L2WU set at 1 if wake-up source is L2
input). After SBC wake and once the WUR has been read, status bits indicates the real time state of the LX inputs (1 mean LX is above
threshold, 0 means that LX input is below threshold).
If, after a wake-up from LX input, a WD timeout occurs before the first reading of the WUR register, the LXxWU bits are reset. This can occur
only if SBC was in Stop mode.
Timing Register (TIM1/2)
This register is composed of two registers:
1. TIM1–controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0.
Please see Table 25.
2. TIM2–is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is read
operation it is not allowed in either TIM1 or TIM2 registers. Please see Table 27.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 25. TIM1 Register
TMI1
D3
D2
D1
D0
W
0
WDW
WDT1
WDT0
R
—
—
—
—
Reset Value
—
0
0
0
Reset Condition
—
POR, RST
POR, RST
POR, RST
$101B
Table 26. TIM1 Control Bits
WDW
WDT1
WDT0
Timing (ms)
Parameter
0
0
0
10
Watchdog Period 1
0
0
1
45
Watchdog Period 2
0
1
0
100
Watchdog Period 3
0
1
1
350
Watchdog Period 4
1
0
0
10
Watchdog Period 1
1
0
1
45
Watchdog Period 2
1
1
0
100
Watchdog Period 3
1
1
1
350
Watchdog Period 4
WD Timing x 50%
No Window Watchdog
Window Watchdog Enabled (Window
Length is Half the Watchdog Timing)
WD Timing x 50%
Watchdog Period
(WD Timing Selected by TIM1 Bit WDW=1)
Figure 17. Window Watchdog
Window Open
for Watchdog Clear
Watchdog Period
(WD Timing Selected by TIM1 Bit WDW=1)
Figure 18. Timeout Watchdog
Table 27. TIM2 Register
TMI2
D3
D2
D1
D0
W
1
CSP2
CSP1
CSP0
R
—
—
—
—
Reset Value
—
0
0
0
Reset Condition
—
POR, RST
POR, RST
POR, RST
$101B
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Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 28. TIM1 Control Bits
CSP2
CSP1
CSP0
Cyclic Sense Timing (ms)
Parameter
0
0
0
5
Cyclic Sense/FWU Timing 1
0
0
1
10
Cyclic Sense/FWU Timing 2
0
1
0
20
Cyclic Sense/FWU Timing 3
0
1
1
40
Cyclic Sense/FWU Timing 4
1
0
0
75
Cyclic Sense/FWU Timing 5
1
0
1
100
Cyclic Sense/FWU Timing 6
1
1
0
200
Cyclic Sense/FWU Timing 7
1
1
1
400
Cyclic Sense/FWU Timing 8
Cyclic Sense on Time
HS1 ON
HS1
Cyclic Sense Timing, Off Time
10 µs
HS1 OFF
Lx Sampling Point
Sample
t
Figure 19. HS1 Operation when Cyclic Sense is Selected
Low Power Mode Control Register (LPC)
This register controls:
• The state of HS1 in Stop and Sleep mode (HS1 permanently off or HS1 cyclic)
• Enable or disable the forced wake-up function (SBC automatic wake-up after time spend in Sleep or Stop modes, time is
defined by the TIM2 register)
• Enable or disable the sense of the wake-up inputs (Lx) at sampling point of the Cyclic Sense period (LX2HS1 bit).
Table 29. LPC Register
LPC
D3
D2
D1
D0
W
LX2HS1
FWU
—
HS1AUTO
R
—
—
—
—
Reset Value
0
0
—
0
Reset Condition
POR, NR2R
N2R,STB2RSTO2R
POR, NR2R
N2R,STB2RSTO2R
—
POR, NR2R
N2R,STB2RSTO2R
$110B
Refer to the Cyclic Sense Wake-up discussion for details of the LPC register setup required for proper Cyclic Sense or direct
wake-up operation.
Table 30. LX2HS1 Control Bits
LX2HS1
Wake-up Inputs Supplied by HS1
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 30. LX2HS1 Control Bits
0
No
1
Yes, Lx Inputs Sensed at Sampling Point
Table 31. HS1AUTO Control Bits
HS1AUTO
Auto Timing HS1 in Sleep and Stop Modes
0
OFF
1
ON, HS1 Cyclic, Period Defined in TIM2 Register
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Interrupt Register (INT)
This register allows masking or enabling the interrupt source. A read operation informs about the interrupt source.
Table 32. INT Register
INT
D3
D2
D1
D0
W
VSUPLOW
HS1OT-V2LOW
VDDTEMP
CANF
R
VSUPLOW
HS1OT
VDDTEMP
CANF
Reset Value
0
0
0
0
Reset Condition
POR, RST
POR, RST
POR, RST
POR, RST
$111B
Table 33. INT Control Bits
Control Bit
CANF
VDDTEMP
HS1OT - V2LOW
VSUPLOW
Description
Mask Bit for CAN Failures
Mask Bit for VDD Medium Temperature (Pre-warning)
Mask Bit for HS1 Overtemperature AND V2 Below 4.0 V
Mask Bit for VSUP Below 6.1 V
When the mask bit is set, INT pin goes low if the appropriate condition occurs.
Table 34. INT Status Bits
Status Bit
CANF
VDDTEMP
HS1OT
VSUPLOW
Description
CAN Failure
VDD Medium Temperature (pre-warning)
HS1 Overtemperature
VSUP Below 6.1 V
If HS1OT - V2LOW interrupt is only selected (only bit D2 set in INT register), reading INT register bit D2 leads to two possibilities:
1. Bit D2 = 1: INT source is HS1OT
2. Bit D2 = 0: INT source is V2LOW
HS1OT and V2LOW bits status are available in IOR.
Upon a wake-up condition from Stop mode due to overcurrent detection (IDD1SW-U1 or IDD1S-WU2), an INT pulse is generated;
however, INT register content remains at 0000 (not bit set into the INT register).
The status bit of the INT register content is a copy of the IOR and CAN registers status content. To clear the INT register bit
the IOR and/or CAN register must be cleared (read register). Once this operation is done at IOR and CAN register the INT register
is updated.
Errors bits are latched in the CAN register and IOR.
33989
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
MC33989, SBC High Speed Typical Application Schematic
VBAT
Q1
V2
R6
D1
Vsup monitor
VSUP
Rp
R1
to L0
C1
C2
HS1
control
HS1
L0
Rp
R2
SW2
Programmable
wake-up input
L1
to L1
Mode control
Oscillator
V2
C7
V2
1Mbit/s CAN
Physical Interface
C3
C4
MOSI
SCLK
MISO
SPI Interface
CANL
C5
RST
L2
L3
C10
Vdd1
INT
WD
Int
Watchdog
Reset
CANH
MCU
CS
TX
RX
GND
SW3
R3
to L2
Rd
SW4
V2
5V/200mA
Vdd1 Monitor
C6
SW1
V2CTRL
Dual Voltage Regulator
Internal
Module
Supply
C8
Safe Circuitry
Clamp(1)
R4
to L3
Rd
C9
Connector
Detail of CAN standard termination schematic
(not split termination)
CANH (SBC)
CANH
CH
L1
CANL
R5
120 ohms
CANL (SBC)
Component values:
D1:
Q1: MJD32C
R1,R2,R3,R4: 10k
R5: 120
Rp, Rd:
R6: 2.2k
C1: 10uF
C2: 100nF
C3: 47uF
C4: 100nF
C5: 47uF tantal
C6,C7,C8,C9,C10: 100nF
CL, CH: 220 pF
CL
CAN Connector
Detail of CAN split termination schematic
CANH (SBC)
R6, 60 ohms
CANH
L1
CH
R7, 60 ohms
CANL (SBC)
CANL
CAN Connector
CL
CS
Figure 20. Typical Application Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
41
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
SUPPLEMENTAL APPLICATION NOTES
MC33989 - GENERAL INFORMATION
MC33989 device supply on page 43
Voltage Regulator on page 43
Failure on VDD1, Watchdog, Reset, INT Pins on page 45
WAKE-UP TIMINGS - SLEEP MODE
LX Wakes up SBC from Sleep Mode on page 47
CAN Wake-up on page 47
LX with Cyclic Sense on page 47
WAKE UP TIMING: STOP MODE
LX Wake-up on page 48
CAN Wake-up on page 48
CS Wake-up on page 48
Overcurrent Wake-up on page 49
LX with Cyclic Sense on page 49
MC33989 CAN INTERFACE
Block Diagram on page 50
CAN Interface Supply on page 50
Main Operation Modes Description on page 50
CAN Driver Operation in Normal Mode on page 50
CAN Mode versus SBC Modes on page 52
How to Test the MC33989 CAN Interface on page 52
CAN LOW POWER MODE AND WAKE-UP
Low Power Mode on page 53
Wake-up on page 53
FAILURE ON V2 SUPPLY, CAN BUS LINES, AND TX PIN
V2LOW on page 55
TX Permanent Dominant on page 55
CAN Driver Overtemperature: on page 56
33989
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
Overcurrent Detection: on page 56
Protection on page 56
Current in Case of Bus Short Conditions on page 56
SOFTWARE ASPECTS
Introduction on page 58
How to Enter in Normal Mode After a Power-Up on page 58
How to Change CAN Slew Rate on page 59
How to Set the CAN Interface in Sleep Mode on page 59
How to Control HS1 Output on page 59
How to Configure Wake-up Before Going in Low Power Mode on page 59
Disable all Wake-up on page 60
How to Enter in Sleep Mode on page 60
How to Enter in Stop Mode with Watchdog on page 61
How to Enter in Stop Mode without Watchdog on page 61
How to Recognize and Distinguish the Wake-up Source on page 62
How to Use the Interrupt Function on page 63
Recognition and Recovery on page 63
How to Distinguish Between V2LOW and HS1 Overtemperature on page 63
GENERAL INFORMATION
The parameters given in the application section are for information only. Reference the electrical tables beginning on page 4
for actual operating parameters.
MC33989 device supply
The MC33989 is supplied from the battery line. A serial diode is necessary to protect the device against negative transient
pulses and from reverse battery situation. This is illustrated in the device typical application schematic.
Voltage Regulator
The MC33989 contains two 5.0 V regulators: The V1 regulator, fully integrated and protected, and the V2 regulator which
operates with an external ballast transistor. This is illustrated in the following device typical application schematic.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
43
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
Q1
Auxiliary 5V
C5
R1
C1
V2CTRL V2
C2 VSUP
WD
C6
Components list:
C1: 22uF, C2: 100nF
C3: >10uF
C4: 100nF
C5: >10uF
C6: 100nF
R1: 2.2k
Rt: 60 - 120
Rp0 to Rp3: 22k
Rs0 to Rs3: 22 k
CL0 to CL3: 10nF
Q1: MJD32C
Safe circuitry
VDD1
HS1
Rp0
S0
Rs0
L0
L1
L2
L3
CL0
C3
MC33989
Rt
CANL
VDD
RST
INT
INT
CS
MISO
MOSI
SCK
TX
RX
CANH
CAN bus
C4
RST
MCU
SPI
CAN
GND
GND
Figure 21. Device Typical Application Schematic
V1 Regulator
The V1 regulator is 5.0 V output, 2% accuracy with current capability of 200 mA max. It requires external decoupling and
stabilizing capacitors. The minimum recommended value are:
• C4: 100 nF
• C3: 10 F < C3 < 22 F, esr < 1.0 ohms. 22 F < C3 < 47 F, esr < 5.0 ohms. C3 > = 47 F, esr < 10 ohms
V2 Regulator: Operation with External Ballast Transistor
The V2 regulator is a tracking regulator of the V1 output. Its accuracy relative to V1 is ±1%. It requires external decoupling and
stabilizing capacitors. The recommended value are: 22 F esr < 5.0 ohms, and 47 F esr < 10 ohms.
The V2 pin has two functions: sense input for the V2 regulator and 5.0 V power supply input to the CAN interface. Ballast
transistor selection: PNP or PMOS transistors can be used. A resistor between base and emitter (or source and drain) is
necessary to ensure proper operation and optimized performances. Recommended bipolar transistor is MJD32C.
V2 Regulator: Operation without Ballast Transistor
The external ballast transistor is optional. If the application does not requires more than the maximum output current capability
of the V1 regulator, then the ballast transistor can be omitted. The thermal aspects must be analyzed as well.
The electrical connections are shown in Figure 22.
no connect
C1
C2
V2CTRL
VSUP
V2
MC33989 VDD1
Partial View
RST
C3
C4
RST
VDD
Components list:
C1: 22uF, C2: 100nF
C3: >10uF
C4: 100nF
MCU
partial view
Figure 22. V2 Regulator Operation
33989
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
Failure on VDD1, Watchdog, Reset, INT Pins
The paragraphs below describe the behavior of the device and of the INT, RST, and WD pins at power up and under failure
of VDD1.
Power Up and SBC Entering Normal Operation
After a power-up the SBC enters in Normal request mode (CAN interface is in TX/RX mode): VDD1 is on, V2 is off. After 350 ms
if no watchdog is written (no TIM1 register write) a reset occurs, and the SBC returns to normal request mode.During this
sequence WD is active (low level).
Once watchdog is written the SBC goes to normal mode: VDD1 is still on and V2 turns on, WD is no longer active and the reset
pin is high. If the watchdog is not refreshed, the SBC generates a reset and returns to Normal request mode.
Write Watchdog each X ms
VDD1
No Watchdog is written
SPI (CS)
WD
350 ms
RST
INT
SBC in
RESET
mode
SBC in Normal request
mode
SBC in Normal
mode
SBC in Normal
request mode
SBC in Normal
mode
Reset every 350 ms
Figure 23. Power Up and SBC Entering Normal Operation
Power Up and VDD1 Going Low with Stop Mode as Default Low Power Mode Selected
The first part of the following figure is identical to the above. If VDD1 is pulled below the VDD1 undervoltage reset (typ 4.6 V)
for instance by an overcurrent or short-circuit (ex short to 4.0 V), and if a low power mode previously selected was stop mode,
the SBC enters reset mode (reset pin is active). The pin WD stays high, but the high level (VOH) follows the VDD1 level. The
interrupt pin goes low.
When the VDD1 overload condition is removed, the SBC restarts in Normal request mode.
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
Write Watchdog
each X ms
VDD1
No problem on
Watchdog period
SPI (CS)
350 ms
WD
350 ms
RST
INT
SBC in
RESET
mode
SBC in Normal request
mode
SBC in Normal
mode
SBC in Reset
mode
SBC in Normal
Request mode
Reset every 350 ms
Figure 24. Power Up and VDD1 Going Low with Stop Mode as Default Low Power Mode Selected
Power Up and VDD1 Going Low with Sleep Mode as Default Low Power Mode Selected
The first part of the graph is the same as the previous figure. If VDD1 is pulled below the VDD1 undervoltage reset (typ 4.6 V)
for instance by an overcurrent or short-circuit (ex short to 4.0 V), and if the low power mode previously selected was sleep mode
and if the BATFAIL flag has been cleared, the SBC enters reset mode for a time period of 100 ms. The pin WD stays high, but
the high level (VOH) follows the VDD1 level.The reset and interrupt pins are low. After the 100 ms, the SBC goes into Sleep mode.
VDD1 and V2 are off (The following figure is an example where VDD1 is shorted to 4.0 V, and after 100 ms the SBC enters sleep
mode.
Write Watchdog
each X ms
VDD1
SPI (CS)
WD
No problem on
Watchdog period
100 ms
350 ms
RST
INT
S B C in
RESET
m ode
S B C in N o rm a l re q u e s t
m ode
Reset every 350 ms
S B C in N o rm a l
m ode
S B C in S le e p m o d e
S B C in R e s e t
m ode
(B A T F A IL fla g
m u s t b e c le a re d )
Figure 25. Power up and VDD1 Going Low with Sleep Mode as Default Low Power Mode Selected
WAKE-UP TIMINGS — SLEEP MODE
The paragraphs below describe the wake-up events from Sleep mode, and the sequence of the signals at the SBC level. The
wake-up time described is the time from the wake-up event to the SBC reset pin release. The wake-up time is the sum of several
timings: wake-up signal detection, VDD1 regulator start-up and decoupling capacitor charge, and reset time. At the end of the
reset time, the reset pin goes from low to high and the MCU is ready to start software operations.
33989
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
LX Wakes up SBC from Sleep Mode
Below is the case where the SBC is in sleep mode and is awaked by LX positive edge.
LX
VDD1
RST
t1
t3
t2
Figure 26. SBC in Sleep Mode
• T1 (LX high level to VDD1 turn on): typ 100 µs.
• T2: VDD1 rising time is dependent on the capacitor and the load connected to VDD1. It can be approximated by the capacitor
charging time with the regulator output current limitation: T2 = (C x U)/I. With C = 100 mF, IDD1 = 200 mA min., U = 5.0 V
so T2 = 2.5 ms).
• T3 (VDD1>RST-TH (4.6 V by default) to reset high): parameter Rest dur: 4.0 ms max.
• The total time is 6.6 ms in this example.
CAN Wake-up
The following case describes the signal for CAN wake-up. Refer to page 53 for more details on CAN wake-up signals and the
TCAN analysis.
CAN
VDD1
RESET
RST
t2
t1
tCAN
t3
Figure 27. CAN Wake-up
• T1(third valid CAN dominant pulse to VDD1 turn on): typ 80 µs.
• T2 and T3 identical to page 42 above
• The total time is 6.58 ms in this example.
LX with Cyclic Sense
The case below is a description of the wake-up by LX input associated with the cyclic sense function.
LX
HS1
VDD1
RESET
RST
t1
t2
t3
t4
Figure 28. Wake-up by LX Input
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Analog Integrated Circuit Device Data
Freescale Semiconductor
47
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
• T1: Is dependent on the selected cyclic sense timing in the TIM2 register (5.0 to 400 ms). LX is sampled
• 10 µs before the end of cyclic sense on time. If the LX correct wake-up level happens just after the sample point, the wakeup will be detected at the next HS1 activation and a complete period is lost.
• T2: It is the same time as LX to VDD1 turn on: typ 100 µs
• T3 & T4: same as page 42
• The total time is 11.5 ms (for a cyclic sense total time of 5.0 ms) in this example.
WAKE-UP TIMING: STOP MODE
The following paragraphs describe the wake-up events from stop mode, and the sequence of the signals at the SBC level. The
wake-up time described is the time from the wake-up event to the SBC INT pin. The wake-up time is the sum of several timings:
wake-up signal detection, the INT pulse, and a minimum delay between INT and SBC ready to operate. At the end of the wakeup time, the SBC is ready to operate, however the MCU might have already been in a restart operation.
LX Wake-up
Below is the case where the SBC is in stop mode and is awakened by an LX positive edge
• T1(L0 high level to INT pulse): typ 100 µs.
• The total time is 133 µs in this case.
L0
INT
t1
tINT + tS-1STSPI (33μs max)
Wake-up signalled to MCU.
SBC ready to accept SPI command.
Figure 29. Lx Wake-up
CAN Wake-up
The case below describes the signal for CAN wake-up. Refer to page 53 for more details on CAN wake-up signals and the
TCAN analysis.
CAN
INT
tCAN
t1
tINT + tS-1STSPI (33μs max)
Wake-up signalled to MCU.
SBC ready to accept SPI command.
Figure 30. CAN Wake-up
• TCAN: refer to page 53 for more details.
• T1: Third pulse on CAN to INT pulse: typ 80 µs.
• The total time is 113 µs in this case.
CS Wake-up
The figure below describes the wake up from a CS signal transition, while the SBC is in Stop mode.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
CS
INT
tINT + tS-1STSPI (33μs max)
T1
Wake-up signalled to MCU.
SBC ready to accept SPI command.
Figure 31. CS Wake-up
• T1: CS rising edge to INT pulse: typ 60 µs.
• The total time is 133 µs in this case.
Overcurrent Wake-up
The following figure describes the signal when an overcurrent is detected at VDD1. A VDD1 overcurrent condition will lead to a
wake-up from Stop mode.
IDD1S-WU
(17 mA typ)
IDD1 current
INT
t1
t2
tINT + tS-1STSPI (33μs max)
Wake-up signalled to MCU.
SBC ready to accept SPI command.
Figure 32. Overcurrent Wake-up
• T1:VDD1 output current deglitcher time:IDD1-DGLT: typ 55 µs
• T2: Overcurrent detected to SBC wake-up (INT pulse) = typ 60 µs
• The total time is 148 µs in this case.
LX with Cyclic Sense
LX
HS1
INT
t1
t2
tINT + tS-1STSPI (33μs max)
Wake-up signalled to MCU.
SBC ready to accept SPI command.
Figure 33. LX with Cyclic Sense
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
• T1: Is dependent on the selected cyclic sense timing in the TIM2 register (5.0 to 400 ms). LX is sampled 10 µs before the
end of cyclic sense on time. If the LX correct wake-up level happens just after sample point, the wake-up will be detected
at the next HS1 activation and a complete period is lost.
• T2: It is the same than Lx to INT pulse: typ 100 µs
• The total time is around 5.13 ms (for a cyclic sense total time of 5.0 ms) in the above example.
MC33989 CAN INTERFACE
This section is a detailed description of the CAN interface of the MC33989.
Block Diagram
Figure 34 is a simplified block diagram of the CAN interface of the MC33989.
V2
V2
V2
SPI control
TX
Driver
QH
CANH
V2
CANH line
Differential
receiver
RX
2.5V
Bus termination (60 ohms)
CAN L line
V2
CANL
Driver
QL
SPI control
VSUP
Internal
wake-up
signal
Wake-up
pattern
recognition
Wake-up
receiver
SPI control
Figure 34. 33989 CAN Interface
CAN Interface Supply
The supply voltage for the CAN driver is the V2 pin. The CAN interface also has a supply path from the battery line, through
the pin VSUP. This path is used in CAN sleep mode to allow wake-up detection.
During CAN communication (transmission and reception) the CAN interface current is sourced from the V2 pin. During a CAN
low power mode, the current is sourced from the VSUP pin.
Main Operation Modes Description
The CAN interface of the MC33989 has two main operation modes: Normal mode and sleep mode. The modes are controlled
by the SPI command.
In normal mode, used for communication, four different slew rates are available for the user.
In sleep mode, the user has the option to enable or disable the remote CAN wake-up capability.
CAN Driver Operation in Normal Mode
When the CAN interface of the MC33989 is in Normal mode, the driver has two states: recessive or dominant. The driver state
is controlled by the TX pin. The bus state is reported through the RX pin.
When TX is high, the driver is set in a recessive state, CANH and CANL lines are biased to the voltage set at V2 divided by
2, approx. 2.5 V.
When TX is low, the bus is set into dominant state: the CANL and CANH drivers are active. CANL is pulled to gnd, CANH is
pulled high toward 5.0 V (the voltage at V2).
The RX pin reports the bus state: the CANH minus the CANL voltage is compared versus an internal threshold (a few hundred
mV). If “CANH minus CANL” is below the threshold, the bus is recessive and RX is set high.
33989
50
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
If “CANH minus CANL” is above the threshold, the bus is dominant and RX is set low. This is illustrated in Figure 36.
TX
CANH-DOM
CANH
CANH-REC
2.5V
CANH-CANL
CANL-REC
2.5V
CANL
CANL-DOM
RX
Figure 35. CAN Driver Operation in Normal Mode
TX and RX Pins
The TX pin has an internal pull up to V2. The state of TX depends on the V2 status. RX is a push-pull structure, supplied by
V2. When V2 is set at 5.0 V, and CAN is in normal mode, RX reports the bus status. When V2 is off RX is low.
Normal Mode and Slew Rate Selection
The slew rate selection is done via the SPI. Four slew rates are available. The slew rate affects the recessive to dominant and
dominant to recessive transitions. This affect is also the delay time from the TX pin to the bus, and from the bus to RX. The loop
time is thus affected by the slew rate selection.
The following figure is an illustration of the slew rate on CANH, CANL, TX and RX.
CAN signal with slew rate 0 selected
CAN signal with slew rate 3 selected
R=60 ohms, CL = CH = 100pF
Figure 36. Normal Mode and Slew Rate Selection
Minimum Baud Rate
As TX permanent dominant is detected after TDOUT (min 200 µs), a minimum Baud rate is required in order to get good
behavior: once TX permanent dominant is detected the CAN driver is off.
The maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag).
200 µs/12 = 16.7 µs. The minimum Baud rate is 1/6.7 µs = 60 KB.
Termination
The MC33989 supports the two main types of bus termination:
• Differential termination resistors between CANH and CANL lines.
• Split termination concept, with mid point of the differential termination connected to gnd through a capacitor.
33989
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
CANH
CAN bus
CANH
CAN bus
MC33989
(partial drawing)
RT
CANL
RT /2
MC33989
(partial drawing)
RT /2
TX
RX
CANL
Gnd
Differential termination concept
TX
RX
Gnd
Split termination concept
Figure 37. Bus Termination
CAN Mode versus SBC Modes
The table below indicates the CAN interface modes versus the SBC modes as well as the status of TX, RX and the CAN bus
pins.
Table 35. CAN vs SBC Modes
CAN mode
V2
voltage
TX
RX
CANH/CANL
(disconnected
from other
nodes)
Unpowered
0V
LOW
LOW
Floating to gnd
YES
0V
LOW
LOW
Floating to gnd
Normal request (with ballast)
YES
0V
LOW
LOW
Floating to gnd
Normal
YES
Normal Slew rate
0,1,2,3
5.0 V
Internal pull-up
to V2.
Report bus state
High if bus
recessive, Low if
dominant
Bus recessive
CANH = CANL =
2.5 V
Normal
YES
Sleep mode
5.0 V
5.0 V
5.0 V
Floating to gnd
Standby with external ballast
YES
Normal or sleep
0V
LOW
LOW
Floating to gnd
Standby without external
ballast, V2 connected to V1
NO
Normal
5.0 V
Same as
normal mode
Same as normal
mode
Same as normal
mode
Standby without external
ballast, V2 connected to V1
NO
Sleep
5.0 V
5V
5V
Floating to gnd
Sleep
—
Sleep
0V
LOW
LOW
Floating to gnd
Stop
—
Sleep
0V
LOW
LOW
Floating to gnd
External
ballast
for V2
Unpowered
YES
Reset (with ballast)
SBC mode
How to Test the MC33989 CAN Interface
The CAN interface can be easily set up and tested. MC33989 can be connected as in the following figure. V2 is connected to
V1. The device is supplied with nominal supply (12 V at VSUP input pin). After power on, reset the device, enter normal request
mode, and the CAN interface is set in normal mode, slew rate 0. TX can be driven by a signal generator. RX will report the bus
state. The figure below is a simple test schematic.
33989
52
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
V2CTRL V2
VSUP
C1
C2
WD
V1
HS1
RST
RESET
C3
C4
Components list:
C1: 22uF, C2: 100nF
C3: >10uF
C4: 100nF
Rt: 60 ohms
MC33989
L0
L1
L2
L3
CANH
INT
CS
MISO
MOSI
SCK
TX
CANL
CANH
CAN bus
RT
CANL
GND
Signal generator
F
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