MFR4200MAE40R

MFR4200 Data Sheet FlexRay Communication Controllers MFR4200 Rev. 1 12/2006 freescale.com MFR4200 Data Sheet MFR4200 Rev. 1 12/2006 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify that you have the latest information available, refer to http://www.freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level Page Number(s) 08/2005 0 Initial release. N/A 12/2006 1 Updated the following sections to remove information relating to clock quality check block: A.3.1.1, “POR” A.3.1.2, “LVR” A.3.1.3, “External Reset” Table A-11 Table A-12 Updated Figure B-1, Figure B-2, and Figure B-3 with latest drawings to comply with Jedec specifications. Applied latest version of back page. 231 231 231 231 232 Description 239, 240, 241 MFR4200 Data Sheet, Rev. 1 4 Freescale Semiconductor Introduction Device Overview MFR4200 FlexRay Communication Controller Dual Output Voltage Regulator (VREG3V3V2) Clocks and Reset Generator Oscillator (OSCV2) Electrical Characteristics Package Information Printed Circuit Board Layout Recommendations MFR4200 Protocol Implementation Document Index of Registers MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 5 MFR4200 Data Sheet, Rev. 1 6 Freescale Semiconductor Contents Section Number Title Page Chapter 1 Introduction 1.1 1.2 1.3 1.4 Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 2 Device Overview 2.1 2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1.2 Implementation Details and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1.5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.1.6 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.1 System Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.2 Pin Functions and Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.2 Recommended Pullup/down Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.3 Host Controller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.4 External Output Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.4.5 MFR4200 Connection to FlexRay Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.4.6 Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 7 Section Number Title Page Chapter 3 MFR4200 FlexRay Communication Controller 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1.1 MFR4200 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1.2 MFR4200 Implementation Parameters and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.2 Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3 Message Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.3.1 Message Buffer Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.3.2 Message Buffer Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 3.3.3 Message Buffer Slot Status Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.3.4 Message ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.3.5 NMVector Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.3.6 Data[0:31] — Data Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.4 Message Buffer Control, Configuration, Status and Filtering Register Set . . . . . . . . . . . . . . . . . 150 3.4.1 Message Buffer Control, Configuration and Status Register . . . . . . . . . . . . . . . . . . . . . 150 3.4.2 Message Buffer Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.4.3 Receive FIFO Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 3.5 Message Buffer Handling and Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.5.2 Buffer Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.5.3 Active Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.5.4 Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 3.5.5 Buffer Reconfiguration in the Normal State of Operation . . . . . . . . . . . . . . . . . . . . . . . 172 3.5.6 Message Buffer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.6 Receive FIFO Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.7 Host Controller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.7.1 MFR4200 Asynchronous Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.7.2 MFR4200 HCS12 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3.8 External 4/10 MHz Output Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.9 Communication Controller States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.9.1 Hard Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.9.2 Configuration State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 3.9.3 Diagnosis Stop State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 3.9.4 Normal Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.9.5 Normal Passive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.10 Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 3.10.1 Debug Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 3.10.2 Debug Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.10.3 Debug Port Function Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 MFR4200 Data Sheet, Rev. 1 8 Freescale Semiconductor Section Number Title Page Chapter 4 Dual Output Voltage Regulator (VREG3V3V2) 4.1 4.2 4.3 4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.2.1 VDDR, VSSR — Regulator Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.2.2 VDDA, VSSA — Regulator Reference Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.2.3 VDD, VSS — Regulator Output1 (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.2.4 VDDOSC, VSSOSC — Regulator Output2 (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.2.5 VREGEN — Optional Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.3.1 REG — Regulator Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.3.2 Full-performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.3.3 POR — Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.3.4 LVR — Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.3.5 CTRL — Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.4.1 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.4.2 Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Chapter 5 Clocks and Reset Generator 5.1 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.2.1 MFR4200 Pins Relevant to the CRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.2.2 Reset Generation and CLKOUT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Chapter 6 Oscillator (OSCV2) 6.1 6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.2.1 VDDOSC and VSSOSC — OSC Operating Voltage, OSC Ground . . . . . . . . . . . . . . . . . . 217 6.2.2 EXTAL and XTAL — Clock/Crystal Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 9 Section Number Title Page Appendix A Electrical Characteristics A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 A.2 Voltage Regulator (VREG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 A.2.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 A.2.2 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 A.2.3 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 A.3 Reset and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 A.3.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 A.3.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 A.4 AMI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 A.5 HCS12 Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Appendix B Package Information B.1 64-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Appendix C Printed Circuit Board Layout Recommendations Appendix C MFR4200 Protocol Implementation Document C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 C.1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 C.1.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 C.1.3 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 C.2 Overall Protocol State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 C.3 Coding and Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 C.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 C.3.2 NRZ Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 C.3.3 NRZ Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 MFR4200 Data Sheet, Rev. 1 10 Freescale Semiconductor Section Number C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 Title Page C.3.4 Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Frame and Symbol Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Wakeup, Startup, and Reintegration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 C.7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 C.7.2 Cluster Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 C.7.3 Communication Startup and Reintegration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 C.8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 C.8.2 Time Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 C.8.3 Synchronization Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 C.8.4 Clock Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 C.8.5 Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 C.8.6 Correction Term Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 C.8.7 Clock Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 C.8.8 Sync Frame Configuration Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Controller Host Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Device Specific Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Bus Guardian Schedule Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 System Parameters and Configuration Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 C.12.1 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 C.12.2 Configuration Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Appendix D Index of Registers MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 11 Section Number Title Page MFR4200 Data Sheet, Rev. 1 12 Freescale Semiconductor List of Figures Figure Number Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 3-18. Figure 3-19. Figure 3-20. Figure 3-21. Title Page Order Part Number Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MFR4200 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Assignments for MFR4200 in 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pierce Oscillator Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CLKOUT Generation During Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CLKOUT Generation during Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 CLKOUT Generation During External Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Example: Connecting a FlexRay Optical/Electrical PHY to the MFR4200. . . . . . . . . . . 50 Example: Connecting an RS485 PHY to the MFR4200. . . . . . . . . . . . . . . . . . . . . . . . . . 50 Key to Register Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Module Version Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Module Version Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Magic Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Module Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Module Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Host Interface Pins Drive Strength Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Physical Layer Pins Drive Strength Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Host Interface Pins Pullup/down Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Host Interface Pins Pullup/down Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Physical Layer Pins Pullup/down Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Physical Layer Pins Pullup/down Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Voltage Regulator Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Bit Duration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Delay Compensation Channel A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Delay Compensation Channel B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Cluster Drift Damping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Sync Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Nominal Macrotick Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Microticks Per Cycle Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Microticks Per Cycle High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 13 Figure Number Figure 3-22. Figure 3-23. Figure 3-24. Figure 3-25. Figure 3-26. Figure 3-27. Figure 3-28. Figure 3-29. Figure 3-30. Figure 3-31. Figure 3-32. Figure 3-33. Figure 3-34. Figure 3-35. Figure 3-36. Figure 3-37. Figure 3-38. Figure 3-39. Figure 3-40. Figure 3-41. Figure 3-42. Figure 3-43. Figure 3-44. Figure 3-45. Figure 3-46. Figure 3-47. Figure 3-48. Figure 3-49. Figure 3-50. Figure 3-51. Figure 3-52. Figure 3-53. Figure 3-54. Figure 3-55. Figure 3-56. Title Page Static Slot Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Number of Static Slots Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Static Payload Length Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Minislot Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Minislot Action Point Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Static Slot Action Point Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Latest Dynamic Transmission Start Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Maximum Payload Length Dynamic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Symbol Window Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Network Idle Time Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Cycle Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Cycle Length Deviation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 External Offset Correction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 External Rate Correction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 External Correction Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Maximum Offset Correction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Maximum Rate Correction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Coldstart Maximum Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Transmit Start Sequence Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Network Management Vector Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Sync Frame Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Sync Frame Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Bus Guardian Tick Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Delay Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Debug Port Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Start of Offset Correction Cycle Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Idle Detection Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Symbol Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Wakeup Mechanism Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Wakeup Symbol TX Idle Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Wakeup Symbol TX Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Listen Timeout With Noise Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Protocol State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Current Cycle Counter Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Current Macrotick Counter Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MFR4200 Data Sheet, Rev. 1 14 Freescale Semiconductor Figure Number Figure 3-57. Figure 3-58. Figure 3-59. Figure 3-60. Figure 3-61. Figure 3-62. Figure 3-63. Figure 3-64. Figure 3-65. Figure 3-66. Figure 3-67. Figure 3-68. Figure 3-69. Figure 3-70. Figure 3-71. Figure 3-72. Figure 3-73. Figure 3-74. Figure 3-75. Figure 3-76. Figure 3-77. Figure 3-78. Figure 3-79. Figure 3-80. Figure 3-81. Figure 3-82. Figure 3-83. Figure 3-84. Figure 3-85. Figure 3-86. Figure 3-87. Figure 3-88. Figure 3-89. Figure 3-90. Figure 3-91. Title Page Offset Correction Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Rate Correction Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Global Network Management Vector n Register, n = [0:5] . . . . . . . . . . . . . . . . . . . . . . . 96 Symbol Window Status Channel A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Symbol Window Status Channel B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Bus Guardian Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Startup Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Odd Cycles Without Clock Correction Fatal Register . . . . . . . . . . . . . . . . . 101 Maximum Odd Cycles Without Clock Correction Passive Register . . . . . . . . . . . . . . . 101 Channel Status Error Counter n Register, n = [0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Interrupt Enable Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Slot Status Selection n Register, n = [0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Slot Status Counter n Register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Slot Status Counter Condition n Register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Slot Status Counter Incrementation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Slot Status Counter Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Receive Buffer Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Transmit Buffer Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 CHI Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Clock Correction Failed Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Error Handling Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Interrupt Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Startup Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Slot Status n Register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Odd Sync Frame ID n Register, n = [0:15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Even Sync Frame ID n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Odd Measurement Channel A n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Odd Measurement Channel B n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Even Measurement Channel A n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Even Measurement Channel B n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Even Measurement Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Odd Measurement Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 FIFO Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Message Buffer Control, Configuration and Status n Register, n = [0:58] . . . . . . . . . . 126 Active Transmit Buffer Frame ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 15 Figure Number Title Page Figure 3-92. Figure 3-93. Figure 3-94. Figure 3-95. Figure 3-96. Figure 3-97. Figure 3-98. Figure 3-99. Figure 3-100. Figure 3-101. Figure 3-102. Figure 3-103. Figure 3-104. Figure 3-105. Figure 3-106. Figure 3-107. Figure 3-108. Figure 3-109. Figure 3-110. Figure 3-111. Figure 3-112. Figure 3-113. Figure 3-114. Figure 3-115. Figure 3-116. Figure 3-117. Figure 3-118. Figure 3-119. Figure 3-120. Figure 3-121. Figure 3-122. Figure 3-123. Active Transmit Buffer Cycle Counter and Payload Length Register . . . . . . . . . . . . . . 127 Active Transmit Buffer Header CRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Active Transmit Buffer Data n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Active Transmit Buffer Message Buffer Slot Status Vector Register . . . . . . . . . . . . . . 128 Active Receive Buffer Frame ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Active Receive Buffer Cycle Counter and Payload Length Register . . . . . . . . . . . . . . . 129 Active Receive Buffer Header CRC Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Active Receive Buffer Data n Register, n = [0:15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Active Receive Buffer Message Buffer Slot Status Vector Register . . . . . . . . . . . . . . . 131 Active FIFO Buffer Frame ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Active FIFO Buffer Cycle Counter and Payload Length Register . . . . . . . . . . . . . . . . . 132 Active FIFO Buffer Header CRC Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Active FIFO Buffer Data n Register, n = [0:15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Active FIFO Buffer Message Buffer Slot Status Vector Register . . . . . . . . . . . . . . . . . 133 Sync Frame Acceptance Filter Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Sync Frame Acceptance Filter Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Sync Frame Rejection Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Cycle Counter Filter n Register, n = [0:58] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 FIFO Acceptance Filter Message ID Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 FIFO Acceptance Filter Message ID Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 FIFO Acceptance/Rejection Filter Channel Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 FIFO Rejection Filter Frame ID Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 FIFO Rejection Filter Frame ID Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Timer Interrupt Configuration Register 0 Cycle Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Timer Interrupt Configuration Register 0 Macrotick Offset . . . . . . . . . . . . . . . . . . . . . 140 Timer Interrupt Configuration Register 1 Cycle Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Timer Interrupt Configuration Register 1 High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Transmit Message Buffer Slot Status Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Receive and Receive FIFO Message Buffer Slot Status Vector. . . . . . . . . . . . . . . . . . . 147 BUFCSnR of a Receive Message Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 BUFCSnR of a Transmit Message Single Buffer for the Dynamic Segment. . . . . . . . . 150 BUFCSnR of a Host Part Transmit Message Buffer of a Double Tx Buffer for the Dynamic Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 3-124. BUFCSnR of a Host Part Transmit Message Buffer of a Double Tx Buffer for the Static Segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 MFR4200 Data Sheet, Rev. 1 16 Freescale Semiconductor Figure Number Title Page Figure 3-125. BUFCSnR of a Single Transmit Message Buffer for the Static Segment . . . . . . . . . . . 151 Figure 3-126. BUFCSnR of a CC Part Transmit Message Buffer of a Double Tx Buffer for Dynamic and Static Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 3-127. BUFCSnR of FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 3-128. CCFnR, Transmit and Receive Message Buffer Filter Registers . . . . . . . . . . . . . . . . . . 158 Figure 3-129. CCFnR, CC Part Buffer of a Double Transmit Message Buffer Filter Registers. . . . . . 158 Figure 3-130. CCFnR, FIFO Buffer Filter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 3-131. Buffer Control, Configuration, Status/Filtering Register Set for Transmit/Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 3-132. Buffer Control, Configuration, Status/Filtering Register Set for Receive FIFO Buffers 163 Figure 3-133. Buffer Busy Bit Timing for a Transmit Message Buffer . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 3-134. Example of a Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure 3-135. Transition Scheme Between Different Buffer Types Depending on Operational Mode of CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 3-136. Operations During a Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 3-137. Operations with a Single Transmit Message Buffer during an Event Type of Transmission for a Static Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Figure 3-138. Double Transmit Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Figure 3-139. Doubled Buffer Data Collection with State Driven Transmit Operation . . . . . . . . . . . . 184 Figure 3-140. Doubled Buffer Data collection with Event Driven Transmit Operation . . . . . . . . . . . . 185 Figure 3-141. FIFO Status (Empty, Not Empty, Overrun) — Example of FIFO with Three Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Figure 3-142. Connecting MFR4200 to MPC5xx Using the AMI (Example) . . . . . . . . . . . . . . . . . . . 190 Figure 3-143. Connecting MFR4200 to MAC71xx Using the AMI (Example) . . . . . . . . . . . . . . . . . . 191 Figure 3-144. Connecting MFR4200 to DSP56F83x (Hawk) Using the AMI (Example) . . . . . . . . . . 191 Figure 3-145. FlexRay CC to HCS12 Device Connection with HCS12 EBI Paged Mode Support. . . 193 Figure 3-146. FlexRay CC to HCS12 Device Connection with HCS12 EBI Unpaged Mode Support 194 Figure 3-147. HCS12 interface Address Decoding and Internal CS Signal Generation . . . . . . . . . . . . 195 Figure 3-148. Timing Diagram of CC State Transition from Configuration State to Normal State . . . 200 Figure 3-149. Start of Communication Cycle and Start of Offset Correction Functions Timing . . . . . 204 Figure 3-150. Timing for Debug Functions with Three EXTAL or CC_CLK Clock Cycles of High State (Logic “1“) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 3-151. Slot Start in Static Segment Function Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 4-1. VREG3V3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Figure 5-1. Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 5-2. Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 5-3. External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 17 Figure Number Figure A-1. Figure A-2. Figure A-3. Figure A-4. Figure A-5. Figure B-1. Figure B-2. Figure B-3. Figure C-1. Figure C-1. Figure C-2. Figure C-3. Figure C-4. Title Page Voltage Regulator — Chip Power-up and Voltage Drops (not scaled) . . . . . . . . . . . . . 230 AMI Interface Read and Write Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 AMI Interface Write-after-Read Transactions Timing Diagram . . . . . . . . . . . . . . . . . . 234 AMI Interface Read-after-Write Transactions Timing Diagram . . . . . . . . . . . . . . . . . . 234 HCS12 Interface Read/write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 64-pin LQFP Mechanical Dimensions (Case No. 840K) (Page 1). . . . . . . . . . . . . . . . . 239 64-pin LQFP Mechanical Dimensions (Case No. 840K) (Page 2). . . . . . . . . . . . . . . . . 240 64-pin LQFP Mechanical Dimensions (Case No. 840K) (Page 3). . . . . . . . . . . . . . . . . 241 Recommended PCB Layout (64-pin LQFP) for Standard Pierce Oscillator Mode . . . . 244 Protocol Operation Control (POC) - 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Protocol Operation Control (POC) - 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 POC — Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 POC — Passive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 MFR4200 Data Sheet, Rev. 1 18 Freescale Semiconductor List of Tables Table Number Title Page Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Notational Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interface Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clockout Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Bus Driver Type Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Voltage Regulator VDDR Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Functions and Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MFR4200 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Recommended Pullup/down Resistor Values for IF_SEL[0:1] and CLK_S[0:1] Inputs . . 46 Register Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Bus Driver Type Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Encoding of Debug Port Control Fields CNTRL[7:4] and CNTRL[3:0] . . . . . . . . . . . . . . 88 CC State Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Mapping between Receive Message Buffer Payload Bytes and GNMVnR Registers . . . . 96 Channel Configuration for SSCCnR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Error Handling Level Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Mapping between SSSnR and SSnR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 FIFO Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 FIFO Channel Filtering Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Receive Message Buffer Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Receive FIFO Message Buffer Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Transmit Message Buffer Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Mapping between Buffer Layout and Active Receive/Transmit/FIFO Message Buffers. 143 Channel Filtering Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 CC Buffer Fields Accessibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Double Transmit Message Buffer Data Collection with State Driven Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 3-18. Double Transmit Message Buffer Data Collection with Event Driven Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 3-19. FlexRay CC MCU Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 3-20. AMI Interface Signals and Pins Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 19 Table Number Table 3-21. Table 3-22. Table 3-23. Table 4-1. Table 4-2. Table 5-1. Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table A-9. Table A-10. Table A-11. Table A-12. Table A-13. Table A-14. Table C-1. Title Page HCS12 Interface Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 CLKOUT Frequency Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Debug Port Functions Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 VREG3V3V2 — Signal Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 VREG3V3V2 — Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 MFR4200 Pins Relevant to the CRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 ESD and Latch-up Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 ESD and Latch-up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Thermal Package Simulation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 5V I/O Characteristics (VDD5 = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 3.3V I/O Characteristics (VDD5 = 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Voltage Regulator - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Voltage Regulator Recommended Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 AMI Interface AC Switching Characteristics over the Operating Range . . . . . . . . . . . . 235 HCS12 Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 MFR4200 Data Sheet, Rev. 1 20 Freescale Semiconductor Chapter 1 Introduction This data sheet provides information on a system that includes the MFR4200 FlexRay Communication Controller Module. 1.1 Audience This data sheet is intended for application and system hardware developers who wish to develop products for the FlexRay MFR4200. It is assumed that the reader understands FlexRay protocol functionality and microcontroller system design. 1.2 Additional Reading For additional reading that provides background to, or supplements, the information in this manual: • Appendix C, “MFR4200 Protocol Implementation Document” • For more information about the FlexRay protocol, refer to the following document: — FlexRay Communications System Protocol Specification V1.1, FlexRay Consortium, 2004. • For more information about Philips Bus Guardian and Bus Driver devices, refer to the following documents: — FlexRay Electrical Physical Layer Specification, v1.5, FlexRay Consortium, 2004, — FlexRay Bus Guardian Preliminary Functional Specification, v1.9, FlexRay Consortium, June 2004. • For more information about RS485 transceivers: — About the MAX3078 transceiver (IDLE state coded as “1”) http://pdfserv.maxim-ic.com/en/ds/MAX3070E-MAX3079E.pdf — About the MAX3485 transceiver (IDLE state coded as “0”) http://pdfserv.maxim-ic.com/en/ds/MAX3483-MAX3491.pdf • For more information about the Power PC interface, refer to the Freescale products section at www.freescale.com. • For more information about M9HCS12 Family devices and M9HCS12 programming, refer to the Freescale Products section at www.freescale.com. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 21 Introduction 1.3 Terminology Table 1-1. Acronyms and Abbreviations Term Meaning AMI Asynchronous memory interface BG Bus guardian CC Communication controller (an alternative term for the MFR4200) ceil Function ceil(x) returns the nearest integer greater than or equal to x Cycle length in µT The actual length of a cycle in µT for the ideal controller (± 0 ppm) EBI External bus interface FSS Frame start sequence Host The FlexRay CC host MCU LSB Less/least significant bit MCU Microcontroller MSB More/most significant bit MT Macrotick µT Microtick NIT Network idle time PHY Physical interface PS FlexRay Communications System Protocol Specification PWD Protocol working document RX Reception TCU Time control unit TX Transmission TDMA Time division multiplex access Table 1-2. Notational Conventions active-high Names of signals that are active-high are shown in upper case text, without a ‘#’ symbol at the end. Active-high signals are asserted (active) when they are high and negated when they are low. active-low A ‘#’ symbol at the end of a signal name indicates that the signal is active-low. An active-low signal is asserted (active) when it is at the logic low level and is negated when it is at the logic high level. asserted A signal that is asserted is in its active logic state. An active-low signal changes from high to low when asserted; an active-high signal changes from low to high when asserted. negated A signal that is negated is in its inactive logic state. An active-low signal changes from low tohigh when negated; an active-high signal changes fromhigh to low when negated. set To set a bit means to establish logic level one on the bit. clear To clear a bit means to establish logic level zero on the bit. MFR4200 Data Sheet, Rev. 1 22 Freescale Semiconductor Part Number Coding Table 1-2. Notational Conventions (continued) 0x0F The prefix “0x” denotes a hexadecimal number. 0b0011 The prefix “0x” denotes a binary number. x In certain contexts, such as a signal encoding, this indicates “don’t care”. For example, if a field is binary encoded 0bx001, the state of the first bit is “don’t care”. == Used in equations, this symbol signifies comparison. 1.4 Part Number Coding P FR 4200 M PB 40 Speed Option 40 = 40 MHz Package Option PB = 64-pin LQFP AE = 64-pin Lead Free / Halide Free LQFP Temperature Option M = -40oC to +125oC Device Title Controller Family Qualification P = Engineering Sample M = Qualified part Figure 1-1. Order Part Number Coding MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 23 Introduction MFR4200 Data Sheet, Rev. 1 24 Freescale Semiconductor Introduction Chapter 2 Device Overview 2.1 Introduction The FlexRay Communication Controller MFR4200 implements the FlexRay protocol in accordance with Appendix C, “MFR4200 Protocol Implementation Document”. This appendix refers to FlexRay Communications System Protocol Specification V1.1 for most protocol mechanisms, and complements the protocol specification where necessary. The controller host interface (CHI) of the FlexRay Communication Controller MFR4200 is implemented in accordance with Chapter 3, “MFR4200 FlexRay Communication Controller”. 2.1.1 Features The following list of features is not comprehensive, but is a selection of the most important features. Detailed descriptions of the protocol and the CHI features are provided in the following. • Chapter 3, “MFR4200 FlexRay Communication Controller” • Appendix C, “MFR4200 Protocol Implementation Document” The most important features are: • Bit rate up to a maximum of 10 Mbit/sec on each of two channels. • 59 message buffers, each with a payload of up to 32 bytes of data. • FlexRay frames with up to 254 payload data bytes. Padding is used for FlexRay payload data that exceeds the 32-byte data size boundary. • One configurable receive FIFO. • Each message buffer configurable as a receive message buffer, or as a transmit message buffer (single or double), or as part of the receive FIFO. • Two receive shadow message buffers available to each channel. • Message buffer configurable with state or event semantics. • Flexible error signaling mechanism providing eight configurable counters, slot status indicators and interrupts. • Internal measured time difference values used for clock synchronization can be read via the CHI. • The status of up to four slots can be observed independently of the communication controller receive buffers. • The host accesses all message buffers by means of three active message buffers (active transmit message buffer, active message receive buffer, and active receive FIFO buffer) in the CHI. • Configurable message filtering based on frame ID, cycle counter, and channel, for transmit and receive message buffers. • Configurable message filtering based on frame ID, channel, and message ID, for the receive FIFO. • Duration of the communication cycle configurable in microticks. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 25 Device Overview 2.1.2 • • • • • • • Implementation Details and Constraints The MFR4200 provides two hardware selectable host interfaces: — HCS12 interface, for direct connection to Freescale’s HCS12 family of microcontrollers. The HCS12 interface clock signal used to synchronize data transfer can run at a maximum rate of 8 MHz. — Asynchronous memory interface (AMI), for asynchronous connection to microcontrollers. Internal 40 MHz quartz oscillator. Internal voltage regulator for the digital logic and the oscillator. Hardware selectable clock output to drive external host devices: Disabled/4/10/40 MHz. Maskable interrupt sources available over one interrupt output line. Glueless electrical physical layer interface compatible with dedicated FlexRay physical layer. Industry standard RS485 physical layer device can be used with additional glue logic. Two pins have multiplexed strobe functions. NOTE Refer to Chapter 3, “MFR4200 FlexRay Communication Controller” for more implementation details and constraints. 2.1.3 Modes of Operation NOTE This section depicts only the MFR4200 device modes, not the FlexRay protocol operating modes of the MFR4200 FlexRay module. Refer to Chapter 3, “MFR4200 FlexRay Communication Controller for more information on the FlexRay module operating modes. Only one user mode is available on the MFR4200 — normal operating mode. In normal operating mode, the selections described below are possible. 2.1.3.1 Interface Selection The external interface is selected by means of the IF_SEL[0:1] pins, as shown in Table 2-1. Table 2-1. Interface Selection Pin Interface IF_SEL0 IF_SEL1 0 0 Reserved 0 1 HCS12 synchronous interface 1 0 Asynchronous Memory Interface 1 1 Reserved MFR4200 Data Sheet, Rev. 1 26 Freescale Semiconductor Introduction NOTE As the IF_SEL[0:1] signals share pins with physical layer interface signals, the interface type must be selected using either pullup or pulldown resistors. IF_SEL[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. Refer to Chapter 5, “Clocks and Reset Generator” for more information. 2.1.3.2 Clockout Selection The CLK_S[0:1] pins select the CLKOUT pin output clock frequency or disable the output clock. Table 2-2. Clockout Selection Pin CLKOUT Function CLK_S0 CLK_S1 0 0 4 MHz output 1 0 10 MHz output 0 1 40 MHz output 1 1 Disabled (CLKOUT output is “0”) NOTE As CLK_S[0:1] signals share pins with physical layer interface signals, the CLKOUT function must be selected using either pullup or pulldown resistors. CLK_S[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. Refer to Chapter 5, “Clocks and Reset Generator for more information. 2.1.3.3 Bus Driver Type Selection The SCM[0:1] bits of the MCR0 register (see Chapter 3, “MFR4200 FlexRay Communication Controller) select the bus driver type. Table 2-3. Bus Driver Type Selection 1 Driver Type SCM1 SCM0 RS485 (IDLE state coded as ’0’)1 0 0 Optical/Electrical PHY 0 1 Reserved 1 0 RS485 (IDLE state coded as ’1’)1 1 1 Refer to Section 1.2, “Additional Reading” for more information on RS485. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 27 Device Overview NOTE It is not possible to mix in a cluster or per channel: • • 2.1.3.4 Different RS485; RS485 and Optical/Electrical PHY. Internal VREG Enable/Disable Selection Table 2-4. Voltage Regulator VDDR Connection 1 2.1.4 VDDR Description Supplied with VDD51 Internal Voltage Regulator enabled Tied to ground Internal Voltage Regulator disabled Refer to Section A.1.7, “Operating Conditions” for the VDD5 Block Diagram Figure 2-1 shows a block diagram of the MFR4200 device. MFR4200 Data Sheet, Rev. 1 28 Freescale Semiconductor Introduction VDDR VSSR VDDA Voltage Regulator VDD2_5 VSSA VSS2_5 RESET# XTAL EXTAL/CC_CLK VDDOSC VSSOSC Clock and Reset Generation Module Oscillator A1/XADDR19 D1/PAD14 A2/XADDR18 A3/XADDR17 D2/PAD13 D0/PAD15 D3/PAD12 A4/XADDR16 A5/XADDR15 A6/XADDR14 HCS12 Interface Asynchronous Memory Interface D4/PAD11 D5/PAD10 A7/ACS0 D6/PAD9 A8/ACS1 A9/ACS2 OE#/ACS3 ACS4 D7/PAD8 D8/PAD7 D9/PAD6 D10/PAD5 ACS5 WE#/RW_CC# D11/PAD4 D12/PAD3 CE#/LSTRB D13/PAD2 Host Interface ECLK_CC D14/PAD1 INT_CC# D15/PAD0 RXD_BG1/RXD1_485 Receiver Channel A BGE1 RXD_BG2/RXD2_485 Receiver Channel B BGE2 TXD_BG1/TXD1_485/IF_SEL1 Transmitter Channel A TXEN1#/ TXE1_485# TXD_BG2/TXD2_485 Transmitter Channel B TXEN2#/ TXE2_485# MT/CLK_S1 TCU ARM/DBG1/CLK_S0 BGT/DBG2/IF_SEL0 CLKOUT CLKOUT/TM0 Debug Strobe External Clock Generator TEST Supply Pins VREG input analog VDDA VSSA VREG input VDDR VSSR Internal Logic Oscillator VDD2_5 VDDOSC VSS2_5 VSSOSC I/O Driver VDDX[1..4] VSSX[1..4] Figure 2-1. MFR4200 Block Diagram MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 29 Device Overview 2.1.5 Memory Map Table 2-5 shows the device memory map of the MFR4200 after a hard reset. Table 2-5. Device Memory Map Address (Hex) Module Size (bytes) 0x000–0x018 General Control Registers 26 0x01A–0x01E Acceptance Filter Registers 6 0x024–0x04A General Control Registers 40 0x04C–0x082 Slot Status Registers 56 0x084–0x0FE General Control Registers 124 0x100–0x126 Active Receive FIFO Buffer 40 0x128–0x13E Reserved, read-only location 24 0x140–0x166 Active Receive Message Buffer 40 0x168–0x17E Reserved, read-only location 24 0x180–0x1A6 Active Transmit Message Buffer 40 0x1A8–0x1FE Reserved, read-only location 88 0x200–0x2FE Buffer Control, Configuration and Status Registers, Cycle Counter Filters Registers 256 0x300–0x31E Reserved, read-only location 32 0x320–0x3FE General Status Registers 224 The FlexRay block defines the MFR4200 address memory map. Refer to Chapter 3, “MFR4200 FlexRay Communication Controller for the detailed register map. MFR4200 Data Sheet, Rev. 1 30 Freescale Semiconductor Signal Descriptions 2.1.6 Part ID Assignments The part ID is located in two 16-bit registers, MVR0 and MVR1, at addresses 0x002 and 0x098 (see Chapter 3, “MFR4200 FlexRay Communication Controller). This read-only value is a unique part ID for each revision of the chip. Table 2-6 shows the assigned part ID number. Table 2-6. Assigned Part ID Numbers Part ID1 Device 1 Mask Set Number MVR0 MVR1 MFR4200 0L60X 0x9042 0x0000 MFR4200 1L60X 0x9042 0x0001 The coding is as follows (see also the MVR0 and MVR1 register descriptions in Chapter 3, “MFR4200 FlexRay Communication Controller): MVR0: Bit 15-12: Major release of the FlexRay block in the MFR4200 device Bit 11-08: Minor release of the FlexRay block in the MFR4200 device Bit 07-00: Device Part ID1 MVR1: Bit 15-08: Device Part ID2. Bit 07-04: Major release of the MFR4200 device. Bit 03-00: Minor release of the MFR4200 device. 2.2 Signal Descriptions This section describes the signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and a detailed discussion of each signal. 2.2.1 System Pinout The MFR4200 is available in a 64-pin low profile quad flat package (LQFP). Most pins perform two or more functions, as described in Section 2.2.2, “Pin Functions and Signal Properties”. Figure 2-2 shows the pin assignments. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 31 Device Overview D5/PAD10 D4/PAD11 D3/PAD12 VDDX3 VSSX3 ECLK_CC D2/PAD13 VDDA VSSA 58 57 56 55 54 53 52 51 50 49 61 D6/PAD9 62 59 D7/PAD8 63 60 D8/PAD7 64 VSS2_5 CLKOUT VDD2_5 INT_CC# TEST 1 48 MT/CLK_S12 D9/PAD6 2 47 ARM/DBG11/CLK_S02 D10/PAD5 3 46 BGE2 D11/PAD4 4 45 TXD_BG2/TXD2_485 D12/PAD3 5 44 TXEN2#TXE2_485# D13/PAD2 6 43 RXD_BG2/RXD2_485 D14/PAD1 7 42 BGE1 VDDX1 8 41 TXD_BG1/TXD1_485/IF_SEL12 VSSX4 WE#/RW_CC BGT/DBG21/IF_SEL02 CE#/LSTRB 32 30 ACS4 31 29 OE#/ACS3 RXD_BG1/RXD1_485 28 33 VDDOSC 16 27 RESET# XTAL ACS5 26 34 25 15 EXTAL/CC_CLK VDDX4 A5/XADDR15 24 35 VSSOSC 14 A9/ACS2 TXEN1#/TXE1_485# A4/XADDR16 23 VDDX2 36 A8/ACS1 37 13 22 12 A3/XADDR17 21 A2/XADDR18 VDDR VSSX2 20 38 VSSR 11 A7/ACS0 D0/PAD15 A1/XADDR19 19 D1/PAD14 39 A6/XADDR14 40 18 9 10 17 VSSX1 D15/PAD0 Notes: 1 One of the following internal signals can be output through the DBG1 or DBG2 pin: PCS, SSS, RAGFB, MSS, DSSB, SFB, RCFB, SCC, RAGFA, MTS, SOC, DSSA, SFA, RCFA. (See Table 3-3 and Table 3-23.) 2 CLK_S[1:0] and IF_SEL[1:0] are inputs during the internal reset sequence, and are latched by the internal reset signal level. Figure 2-2. Pin Assignments for MFR4200 in 64-pin LQFP 2.2.2 Pin Functions and Signal Properties Table 2-7 provides a summary of all pin functions and signal properties shown in Figure 2-2. MFR4200 Data Sheet, Rev. 1 32 Freescale Semiconductor Signal Descriptions Table 2-7. Pin Functions and Signal Properties Pin Pin1 N Function1 Pin1 Pin1 Function2 Function3 Powered by In/ Out Pin type2,3 Re set Functional Description Host Interface Pins 11 A1 XADDR19 - VDDX I PC - AMI address bus / HCS12 expanded address lines. A1= LSB of the AMI address bus. 12 A2 XADDR18 - VDDX I PC - AMI address bus / HCS12 expanded address lines. 13 A3 XADDR17 - VDDX I PC - AMI address bus / HCS12 expanded address lines. 14 A4 XADDR16 - VDDX I PC - AMI address bus / HCS12 expanded address lines. 15 A5 XADDR15 - VDDX I PC - AMI address bus / HCS12 expanded address lines. 17 A6 XADDR14 - VDDX I PC - AMI address bus / HCS12 expanded address lines. XADDR14 = LSB of the HCS12 expanded address lines 18 A7 ACS0 - VDDX I PC - AMI address bus / HCS12 address select inputs. 21 A8 ACS1 - VDDX I PC - AMI address bus / HCS12 address select inputs. 22 A9 ACS2 - VDDX I PC - AMI address bus / HCS12 address select inputs. 27 OE#4 ACS3 - VDDX I PC - AMI read output enable signal / HCS12 address select input. 28 ACS4 - - VDDX I PC - HCS12 address select inputs. 34 ACS5 - - VDDX I PC - HCS12 address select inputs. MSB of the address select inputs. 10 D15 PAD0 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. PAD0 is the LSB of the HCS12 address/data bus. 7 D14 PAD1 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 6 D13 PAD2 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 5 D12 PAD3 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 4 D11 PAD4 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 3 D10 PAD5 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 2 D9 PAD6 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 33 Device Overview Table 2-7. Pin Functions and Signal Properties (continued) Pin Pin1 N Function1 Pin1 Pin1 Function2 Function3 Powered by In/ Out Pin type2,3 Re set Functional Description 62 D8 PAD7 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 61 D7 PAD8 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 58 D6 PAD9 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 57 D5 PAD10 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 56 D4 PAD11 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 55 D3 PAD12 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 51 D2 PAD13 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 40 D1 PAD14 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. 39 D0 PAD15 - VDDX I/O Z/DC/PC Z AMI data bus / HCS12 multiplexed address/data bus. D0 is the LSB of the AMI data bus 29 CE# LSTRB - VDDX I PC - AMI chip select signal / HCS12 low-byte strobe signal 30 WE# RW_CC# - VDDX I PC - AMI write enable signal/ HCS12 read/write select signal 52 ECLK_CC - - VDDX I PC - HCS12 clock input Physical Layer Interface 32 BGT DBG2 IF_SEL0 VDDX I/O DC/PD - Bus Guardian Tick / Debug strobe point signal 2/Host interface selection 0 48 MT CLK_S1 - VDDX I/O DC/PD - Bus Guardian Macrotick/Controller clock output select signal 1 47 ARM DBG1 CLK_S0 VDDX I/O DC/PD - Bus Guardian ARM signal / Debug strobe point signal1/Controller clock output select signal 0 33 RXD_BG1 RXD2_485 - VDDX I PC - PHY Data receiver input / RS485 Data receiver input 43 RXD_BG2 RXD2_485 - VDDX I PC - PHY Data receiver input / RS485 Data receiver input 36 TXEN1# TXE1_485# - VDDX O DC 1 Transmit enable for PHY / Transmit enable for RS485 44 TXEN2# TXE2_485# - VDDX O DC 1 Transmit enable for PHY / Transmit enable for RS485 MFR4200 Data Sheet, Rev. 1 34 Freescale Semiconductor Signal Descriptions Table 2-7. Pin Functions and Signal Properties (continued) Pin Pin1 N Function1 Pin1 Pin1 Function2 Function3 41 TXD_BG1 TXD1_485 45 TXD_BG2 42 46 Powered by In/ Out Pin type2,3 Re set IF_SEL1 VDDX I/O DC/PD - PHY Data transmitter output / RS485 Data transmitter output / Host interface selection 1 TXD2_485 - VDDX O DC 0 PHY Data transmitter output / RS485 Data transmitter output BGEN1 - - VDDX I PC - Bus Guardian Enable monitor input BGEN2 - - VDDX I PC - Bus Guardian Enable monitor input - Controller clock output selectable as disabled or 4/10/40 MHz Functional Description Clock Signals 63 CLKOUT - - VDDX I/O DC Others 16 RESET# - - VDDX I - - Hardware reset input 64 INT_CC# - - VDDX O OD/DC 1 Controller interrupt output 1 TEST - - VDDX I - - Must be tied to logic low in application. Oscillator 24 EXTAL CC_CLK - 25 XTAL - - VDDOSC I - - Crystal driver / External clock pin I - - Crystal driver pin Supply/Bypass Filter pins 8 VDDX1 - - - - - - Supply voltage, I/O 37 VDDX2 - - - - - - Supply voltage, I/O 54 VDDX3 - - - - - - Supply voltage, I/O 35 VDDX4 - - - - - - Supply voltage, I/O 9 VSSX1 - - - - - - Supply voltage ground, I/O 38 VSSX2 - - - - - - Supply voltage ground, I/O 53 VSSX3 - - - - - - Supply voltage ground, I/O 31 VSSX4 - - - - - - Supply voltage ground, I/O 20 VDDR - - - - - - Supply voltage, supply to pin drivers and internal voltage regulator 19 VSSR - - - - - - Supply voltage ground, ground to pin drivers and internal voltage regulator 50 VDDA - - - - - - Supply analog voltage 49 VSSA - - - - - - Supply analog voltage ground 59 VDD2_5,4 - - - - - - Core voltage power supply output (nominally 2.5V) 60 VSS2_54 - - - - - - Core voltage ground output MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 35 Device Overview Table 2-7. Pin Functions and Signal Properties (continued) Pin Pin1 N Function1 Pin1 Pin1 Function2 Function3 Powered by In/ Out Pin type2,3 Re set Functional Description 26 VDDOSC4 - - - - - - Oscillator voltage power supply output (nominally 2.5 V) 23 VSSOSC4 - - - - - - Oscillator voltage ground output 1 # – signal is active-low. PC (Pullup/down Controlled) – Register controlled internal weak pullup/down for a pin in input mode. Refer to the following sections for more information: – Section 3.2.3.2.5, “Host Interface Pins Pullup/down Enable Register (HIPPER)” – Section 3.2.3.2.6, “Host Interface Pins Pullup/down Control Register (HIPPCR)” – Section 3.2.3.2.7, “Physical Layer Pins Pullup/down Enable Register (PLPPER)” – Section 3.2.3.2.8, “Physical Layer Pins Pullup/down Control Register (PLPPCR)” PD (Pull Down) – Internal weak pulldown for a pin in input mode. DC (Drive strength Controlled) – Register controlled drive strength for a pin in the output mode. Refer to the following for more information: – Section 3.2.3.2.3, “Host Interface and Physical Layer Pins Drive Strength Register (HIPDSR)” – Section 3.2.3.2.4, “Physical Layer Pins Drive Strength Register (PLPDSR)” Z – Three-stated pin. OD (Open Drain) – Output pin with open drain. 3 Reset state: – All pins with the PC option have pullup/down resistors disabled. – All pins with the DC option have full drive strength. 4 No load allowed except for bypass capacitors. 2 2.2.3 2.2.3.1 Detailed Signal Descriptions A[1:6]/XADDR[19:14] — AMI Address Bus, HCS12 Expanded Address Inputs A[1:6]/XADDR[19:14] are general purpose input pins. Their function is selected by the IF_SEL[0:1] pins. Refer to Section 3.7, “Host Controller Interfaces” for more information. The pins can be configured to enable or disable either pullup or pulldown resistors on the pins. (See Section 3.2.3.2.5, “Host Interface Pins Pullup/down Enable Register (HIPPER)” and Section 3.2.3.2.6, “Host Interface Pins Pullup/down Control Register (HIPPCR)”.) A[1:6] are AMI interface address signals. A1 is the LSB of the AMI address bus. XADDR[19:14] are HCS12 interface expanded address lines. XADDR14 is the LSB of the HCS12 interface expanded address lines. 2.2.3.2 A[7:9]/ACS[0:2] — AMI Address Bus, HCS12 Expanded Address Inputs A[7:9]/ACS[0:2] are general purpose input pins. Their function is selected by the IF_SEL[0:1] pins. Refer to Section 3.7, “Host Controller Interfaces” for more information. The pins can be configured to enable or disable either pullup or pulldown resistors on the pins. MFR4200 Data Sheet, Rev. 1 36 Freescale Semiconductor Signal Descriptions A[7:9] are AMI interface address signals. ACS[0:2] are HCS12 interface address select signals. 2.2.3.3 OE#/ACS3 — AMI Read Output Enable, HCS12 Address Select Input. OE#/ACS3 is a general purpose input pin. Its function is selected by the IF_SEL[0:1] pins. Refer to Section 3.7, “Host Controller Interfaces” for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. OE# is the AMI interface output enable signal. This signal controls MFR4200 data output and the state of three-stated data pins D[15:0] during host read operations. ACS3 is an HCS12 interface address select signal. 2.2.3.4 ACS[4:5] — HCS12 Address Select Inputs ACS[4:5] are general purpose input pins.Their function is selected by the IF_SEL[0:1] pins. Refer to Section 3.7, “Host Controller Interfaces” for more information. The pins can be configured to enable or disable either pullup or pulldown resistors on the pins. ACS[4:5] are HCS12 interface address select signals. ACS5 is the MSB of the address select inputs. 2.2.3.5 D[15:0]/PAD[0:15] — AMI Data Bus, HCS12 Multiplexed Address/Data Bus D[15:0]/PAD[0:15] are general purpose input or output pins. Their functions are selected by the IF_SEL[0:1] pins. Refer to Section 3.7, “Host Controller Interfaces” for more information. These pins can be configured to provide either high or reduced output drive, and also to enable or disable either pullup or pulldown resistors on the pins. D[15:0] are data signals of the AMI interface. D0 is the LSB of the AMI data bus. PAD[0:15] are HCS12 interface multiplexed address/data signals in the HCS12 Host interface mode of operation. PAD0 is the LSB of the HCS12 address/data bus. 2.2.3.6 CE#/LSTRB — AMI Chip Select, HCS12 Low-byte Strobe The function of this pin is selected by IF_SEL[0:1] pins. Section 3.7, “Host Controller Interfaces” for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. CE# is an AMI interface transfer size input signal. It indicates the size of the requested data transfer in the current bus cycle. LSTRB is an HCS12 interface low-byte strobe input signal. It indicates the type of bus access. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 37 Device Overview 2.2.3.7 WE#/RW_CC# — AMI Write Enable, HCS12 Read/Write Select The function of this pin is selected by IF_SEL[0:1] pins. Refer to Section 3.7, “Host Controller Interfaces” for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. WE# is an AMI interface write select signal. It strobes the valid data provided by the host on the D[15:0] pins during write operations to the MFR4200 memory. RW_CC# is an HCS12 interface read/write input signal. It indicates the direction of data transfer for a transaction. 2.2.3.8 ECLK_CC — HCS12 Clock Input ECLK_CC is the HCS12 interface clock input signal. The input clock frequency can be up to 8 MHz in the HCS12 mode of the external interface block. The pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. 2.2.3.9 BGT/DBG2/IF_SEL0 — Bus Guardian Tick, Debug Strobe Point 2, Host Interface Selection 0 BGT is a bus guardian tick clock output signal provided from the CC. If a Bus Guardian device is not used in an application, this pin may be left open. BGT is active, irrespective of which physical layer is selected. If the RS485 Driver type is selected, this pin is not used. This signal should be connected to the bus guardian on each channel. The pin can be configured to provide either high or reduced output drive. DBG2 is debug strobe point output 2. The function output on this pin is selected by the debug port control register. Refer to Section 3.10, “Debug Port” for more information. IF_SEL0 is the CC external interface selection input signal. Refer to Table 2-1 for the selection coding. NOTE The IF_SEL[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. While the IF_SEL0 value is being latched, the output drive control is disabled and the internal pulldown resistor is connected to the pin. As the IF_SEL[0:1] signals share pins with Physical Layer Interface signals, pullup/down devices must be used for selection. Recommended pullup/down resistor values for the IF_SEL[0:1] inputs are given in Section 2.4.2, “Recommended Pullup/down Resistor Values”. 2.2.3.10 MT/CLK_S1 — Bus Guardian Macrotick, Clock Output Select 1 MT is a Bus Guardian macrotick output signal from the CC. If a bus guardian device is not used in an application, this pin may be left open. MFR4200 Data Sheet, Rev. 1 38 Freescale Semiconductor Signal Descriptions MT is active, irrespective of which physical layer is selected. If the RS485 driver type is selected, this pin is not used. This signal should be connected to the Bus Guardians on each channel. The pin can be configured to provide either high or reduced output drive. CLK_S1 is the CLKOUT clock frequency selection input signal. See Table 2-2. NOTE CLK_S[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. While the CLK_S1 value is being latched, the output drive control is disabled and the internal pulldown resistor is connected to the pin. As CLK_S[0:1] signals share pins with Physical Layer Interface signals, pullup/down devices must be used for the selection. Recommended pullup/down resistor values for the CLK_S[0:1] inputs are given in Section 2.4.2, “Recommended Pullup/down Resistor Values”. 2.2.3.11 ARM/DBG1/CLK_S0 — Bus Guardian ARM, Debug Strobe Point 1, Clock Output Select 0 ARM is an output signal from the CC to a bus guardian. If a bus guardian device is not used in an application, this pin may be left open. ARM is active, irrespective of which physical layer is selected. If the RS485 driver type is selected, this pin is not used. This signal should be connected to the bus guardian on each channel. The pin can be configured to provide either high or reduced output drive. DBG1 is the debug strobe point output 1. The function output on this pin is selected by the debug port control register. Refer to Section 3.10, “Debug Port” for more information. CLK_S0 is the CLKOUT clock frequency selection input signal. See Table 2-2. NOTE CLK_S[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. While the CLK_S0 value is being latched, the output drive control is disabled and the internal pulldown resistor is connected to the pin. As CLK_S[0:1] signals share pins with Physical Layer Interface signals, pullup/down devices must be used for selection. Recommended pullup/down resistor values for the CLK_S[0:1] inputs are given in the Section 2.4.2, “Recommended Pullup/down Resistor Values”. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 39 Device Overview 2.2.3.12 RXD_BG[1:2]/RXD[1:2]_485 — PHY Received Data, RS485 Received Data The function of this pin is selected by the SCM[0:1] bits in the MCR0 register. Refer to Section 3.2.3.2.1, “Module Configuration Register 0 (MCR0)” for more information. The pins can be configured to enable or disable either pullup or pulldown resistors on the pins. RXD_BG[1:2] are bus driver receive data input signals if the FlexRay Optical/Electrical PHY is configured: • RXD_BG1 is the input to the CC from Physical Layer Channel 1. • RXD_BG2 is the input to the CC from Physical Layer Channel 2. RXD[1:2]_485 are bus driver receive data input signals if the RS485 Driver type is configured: • RXD1_485 is the input to the CC from Physical Layer Channel 1 • RXD2_485 is the input to the CC from Physical Layer Channel 2. 2.2.3.13 TXEN[1:2]#/TXE[1:2]_485# — PHY Transmit Enable, RS485 Transmit Enable TXEN[1:2]# are bus driver transmit enable output signals if the FlexRay Optical/Electrical PHY is configured: • TXEN1# is the output of the CC to Physical Layer Channel 1 • TXEN2# is the output of the CC to Physical Layer Channel 2. TXE[1:2]_485# are Bus Driver Transmit Enable output signals if the RS485 Driver type is configured: • TXE1_485# is the output of the CC to the Physical Layer Channel 1. • TXE2_485# is the output of the CC to the Physical Layer Channel 2. Refer to Figure 2-10 for an example RS485 bus driver connection using external glue logic. The pins can be configured to provide either high or reduced output drive. 2.2.3.14 TXD_BG1/TXD1_485/ IF_SEL1 — PHY Transmit Data 1, RS485 Transmit Data 1, Host Interface Selection 1 The function of this pin is selected by the SCM[0:1] bits in the MCR0 register. Refer to Section 3.2.3.2.1, “Module Configuration Register 0 (MCR0)” for more information. The pins can be configured to provide either high or reduced output drive. TXD_BG[1:2] are bus driver transmit data output signals if the FlexRay Optical/Electrical PHY is configured: • TXD_BG1 is the output of the CC to Physical Layer Channel 1 • TXD_BG2 is the output of the CC to Physical Layer Channel 2. TXD[1:2]_485 are bus driver transmit data output signals if the RS485 Driver type is configured: • TXD1_485 is the output of the CC to Physical Layer Channel 1. • TXD2_485 is the output of the CC to Physical Layer Channel 2. MFR4200 Data Sheet, Rev. 1 40 Freescale Semiconductor Signal Descriptions IF_SEL1 is the CC external interface selection input signal. Refer to Table 2-1 for the selection coding. NOTE IF_SEL[0:1] signals are inputs during the internal reset sequence and are latched by the internal reset signal level. While the IF_SEL1 level is being latched, the output drive control is disabled and the internal pulldown resistor is connected to the pin. As IF_SEL[0:1] signals share pins with Physical Layer Interface signals, pullup/down devices must be used for the selection. Recommended pullup/down resistor values for the IF_SEL[0:1] inputs are given in Section 2.4.2, “Recommended Pullup/down Resistor Values”. 2.2.3.15 TXD_BG2/TXD2_485 — PHY Transmit Data 2, RS485 Transmit Data 2 The function of this pin is selected by the SCM[0:1] bits in the MCR0 register. Refer to Section 3.2.3.2.1, “Module Configuration Register 0 (MCR0)” for more information. TXD_BG[1:2] are bus driver transmit data output signals if the FlexRay Optical/Electrical PHY is configured: • TXD_BG1 is the output of the CC to Physical Layer Channel 1. • TXD_BG2 is the output of the CC to Physical Layer Channel 2. TXD[1:2]_485 are bus driver transmit data output signals if the RS485 Driver type is configured: • TXD1_485 is the output of the CC to the Physical Layer Channel 1. • TXD2_485 is the output of the CC to the Physical Layer Channel 2. 2.2.3.16 BGEN[1:2] — Bus Guardian Enable The CC monitors the schedule of Bus Guardians operations by checking the BGEN[1:2] input signals provided by Bus Guardians: BGEN1 is the input from the Physical Layer Channel 1 to the CC. BGEN2 is the input from the Physical Layer Channel 2 to the CC. If the RS485 Driver type is configured, the BGEN[1:2] inputs are not used and may be left open, but it is recommended to connect these pins to the logic "0" or logic "1" level either by enabling either pullup or pulldown resistors or by using external components. The pins can be configured to enable or disable either pullup or pulldown resistors on the pins. 2.2.3.17 CLKOUT — Clock Output CLKOUT is an external continuous clock output signal. The frequency of CLKOUT is selected by the CLK_S[0:1] pins. The CLKOUT signal is always active after power-up of the CC, in all CC states including the hard reset state. The pin can be configured to provide either high or reduced output drive. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 41 Device Overview As the CLKOUT signal can be disabled during internal resets, refer to Section 2.4.4, “External Output Clock” for more information on CLKOUT generation during external hard and internal resets. 2.2.3.18 RESET# — External Reset RESET# is an active-low control signal that acts as an input to initialize the CC to a known startup state. 2.2.3.19 INT_CC# — Interrupt Output INT_CC# is an AMI and HCS12 interfaces interrupt request output signal. The CC may request a service routine from the host to run. The interrupt is indicated by the logic level: it is asserted if the INT_CC# outputs a logic "0" and negated if it outputs a logic "1". The pin can be configured to provide either high or reduced output drive. 2.2.3.20 TEST The TEST pin must be tied to VSS in all applications. 2.2.3.21 EXTAL/CC_CLK — Crystal Driver, External Clock Pin This pin can act as a crystal driver pin (EXTAL) or as an external clock input pin (CC_CLK). On reset, the device clock is derived from the input frequency on this pin. Refer to Figure 2-3 for Pierce oscillator connections and and Figure 2-4 for external clock connections. See also Chapter 6, “Oscillator (OSCV2)”. 2.2.3.22 XTAL — Crystal Driver Pin XTAL is a crystal driver pin. Refer to Figure 2-3 for Pierce oscillator connections and and Figure 2-4 for external clock connections. See also Chapter 6, “Oscillator (OSCV2)”. MFR4200 C1 EXTAL Rb Rs Q C2 XTAL Where: • • • • • Q = 40 MHz crystal Rb is in the range 1M - 10 Mohms Rs is a lower value, which can be 0 Ohms C1 = C2 Oscillator supply output capacitor C3 = 220 nF Refer to crystal manufacturer’s product specification for recommended values VDDOSC C3 VSSOSC VSSOSC VSSOSC Figure 2-3. Pierce Oscillator Connections MFR4200 Data Sheet, Rev. 1 42 Freescale Semiconductor Signal Descriptions MFR4200 EXTAL/CC_CLK Clkout Where: G = 40MHz CMOS-compatible External Oscillator (VDDOSC-level) XTAL Not connected (left open) VDDOSC C3 VSSOSC VSSOSC Figure 2-4. External Clock Connections 2.2.4 Power Supply Pins MFR4200 power and ground pins are summarized in Table 2-8 and described below. NOTE All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MFR4200 as possible. Bypass requirements depend on how heavily the MFR4200 pins are loaded. Table 2-8. MFR4200 Power and Ground Connection Summary Pin Number Mnemonic 64-pin LQFP Nominal Voltage VDD2_5 59 2.5V VSS2_5 60 0V VDDR 20 3.3V VSSR 19 0V VDDX[1:4] 8, 37, 54, 35 3.3V VSSX[1:4] 9, 38, 53, 31 0V VDDA 50 3.3V VSSA 49 0V VDDOSC 26 2.5V VSSOSC 23 0V Description Internal power and ground generated by internal regulator External power and ground, supply to supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers. Operating voltage and ground for the internal voltage regulator. Provides operating voltage and ground for the internal oscillator. This allows the supply voltage to the oscillator to be bypassed independently. Internal power and ground generated by internal regulator. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 43 Device Overview 2.2.4.1 VDDX, VSSX — Power and Ground Pins for I/O Drivers External power and ground for I/O drivers. 2.2.4.2 VDDR, VSSR — Power and Ground Pins for I/O Drivers and Internal Voltage Regulator External power and ground for I/O drivers and input to the internal voltage regulator. NOTE The VDDR pin enables the internal 3.3 V to 2.5 V voltage regulator. If this pin is tied to ground, the internal voltage regulator is turned off. 2.2.4.3 VDD2_5, VSS2_5 — Core Power Pins Power is supplied to the MFR4200 core through VDD2_5 and VSS2_5. This 2.5 V supply is derived from the internal voltage regulator. No static load is allowed on these pins. If VDDR is tied to ground, the internal voltage regulator is turned off. NOTE No load is allowed except for bypass capacitors. 2.2.4.4 VDDA, VSSA — Power Supply Pins for VREG VDDA, VSSA are the power supply and ground input pins for the voltage regulator. They also provide the reference voltages for the internal voltage regulator. 2.2.4.5 VDDOSC, VSSOSC — Power Supply Pins for OSC VDDOSC, VSSOSC provide operating voltage and ground for the oscillator. This allows the supply voltage to the oscillator to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator. NOTE No load is allowed except for bypass capacitors. 2.3 System Clock Description The internal Clock and Reset Generator block provides the internal clock signals for the FlexRay block and all other modules. Figure 2-5 shows the clock connections from the CRG to all modules. Refer to Chapter 5, “Clocks and Reset Generator” for detailed information on clock generation. MFR4200 Data Sheet, Rev. 1 44 Freescale Semiconductor System Clock Description Host Interface EXTAL Receiver Channel A CRG oscillator clock XTAL Receiver Channel B Transmitter Channel A Transmitter Channel A TCU Debug Strobe External Clock Generator Figure 2-5. Clock Connections MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 45 Device Overview 2.4 Modes of Operation 2.4.1 Overview The MFR4200 device operates only in one user mode — the normal mode. In normal mode, different host interfaces can be selected, each with its own associated external pin and interface configurations. The device has no low power modes. 2.4.2 Recommended Pullup/down Resistor Values As IF_SEL[0:1] and CLK_S[0:1] signals share pins with physical layer interface signals, pullup/down devices must be used for selection. Recommended pullup/down resistor values for the IF_SEL[0:1] and CLK_S[0:1] inputs are given in Table 2-9. Table 2-9. Recommended Pullup/down Resistor Values for IF_SEL[0:1] and CLK_S[0:1] Inputs 1 IO, Regulator, and Analog Supply Level (VDD5) Pullup Resistor1 Pulldown Resistor1 Units 3.3V 16 47 kOhm 5V 10 47 kOhm The listed values are calculated for the MFR4200 physical layer connection where no internal pullup/down resistors are assumed in the Electrical PHY at the TXD_BG1, BGT, ARM and MT interface lines. If an Electrical PHY device has internal pullup/down resistors connected to those signals, then the external pullup/down resistor values must be recalculated to ensure that VIL requirements for pulldown resistors or VIH requirements for pullup resistors for the chosen VDD5 are met. Refer to Section A.1.9, “I/O Characteristics” for more information on VIL, VIH and VDD5. 2.4.3 Host Controller Interfaces The FlexRay communication controller can be connected to and controlled by microcontrollers with two types of interface. The MCU type is selected by the IF_SEL0 and IF_SEL1 inputs as shown in Section 2.1.3.1, “Interface Selection”. The CC latches the values of the IF_SEL0 and IF_SEL1 signals when it leaves the hard reset state. The CC configures the interface for the type of MCU based on the latched values. The CC latches the values again after it has left the hard reset state (see Section 3.9.1, “Hard Reset State”). NOTE If the CC senses an unsupported mode on its IF_SEL pins, it stops all internal operations, does not perform or respond to any host transactions, stays in configuration mode, and does not integrate into the communication process. The following steps must be taken to select a correct MCU interface mode: 1. IF_SEL0, IF_SEL1 must be set to AMI or to HCS12 mode; 2. The hard reset signal of the CC must be asserted again. MFR4200 Data Sheet, Rev. 1 46 Freescale Semiconductor Modes of Operation 2.4.4 External Output Clock The CC provides a continuous external output clock signal on the CLKOUT pin; this signal can be either disabled or set to a frequency of 4, 10, or 40 MHz. The signal is always active after the power-up of the CC, in all CC states including the hard reset state. The CLKOUT signal is disabled during the internal power-on and low voltage reset procedures (refer to Chapter 5, “Clocks and Reset Generator”, Section A.2.2, “Chip Power-up and Voltage Drops”, and the figures below (Figure 2-6, Figure 2-7, and Figure 2-8) for more information). The CLK_S[1:0] input pins enable/disable the CLKOUT signal and select its output frequency in accordance with the Table 2-2. Figure 2-6 and Figure 2-7 depict the CLKOUT generation during external hard reset and internal resets. Refer to Chapter 5, “Clocks and Reset Generator for more information. VDD POR 1 tUPOSC2 OSC clk output ~16000 3 Internal startup counter 0 ~16000 µT 3 Internal CLK_S[1:0] latches Latching window 3 CLKOUT divider internal reset , the divider is based on a counter Max. count value defined by CLK_S[1:0] latched values CLKOUT divider/counter output CLKOUT output Where: Counter maximum value Counter starts counting Counter is reset Counter does not count Notes: 1 For more information on the POR, refer to A.2.2, “Chip Power-up and Voltage Drops”. 2 For more information on the t UPOSC, refer to A.3, “Reset and Oscillator”. 3 For more information on the Internal Startup Counter, the Internal CLK_S[1:0] latches, and the CLKOUT divider internal reset signals, refer to Chapter 5, “Clocks and Reset Generator. Figure 2-6. CLKOUT Generation During Power-on Reset MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 47 Device Overview LVR 1 ~16000 2 Internal startup counter 0 ~16000 µT 2 Internal CLK_S[1:0] latches Latching window 2 CLKOUT divider internal reset , the divider is based on a counter Max. count value defined by CLK_S[1:0] latched values CLKOUT divider/counter output CLKOUT output Where: Counter maximum value Counter starts counting Counter is reset Counter does not count Notes: 1 For more information about the POR, refer to A.2.2, “Chip Power-up and Voltage Drops. 2 For more information about the Internal Startup Counter, the Internal CLK_S[1:0] latches, and the CLKOUT divider internal reset signals, refer to Chapter 5, “Clocks and Reset Generator. Figure 2-7. CLKOUT Generation during Low Voltage Reset MFR4200 Data Sheet, Rev. 1 48 Freescale Semiconductor Modes of Operation External Reset RESET# pin External reset after 1 internal glitch filter Latching window 2 Internal CLK_S[1:0] latches 10 MHz 4 MHz CLKOUT divider internal reset, the divider is based on a counter CLKOUT divider/counter output CLKOUT output max 8 µT Where: Counter maximum value Counter starts counting CLKOUT stabilization time 3 Counter is reset Counter does not count Notes: 1 Refer to Chapter 5, “Clocks and Reset Generator for more information on the reset glitch filter. 2 For example, running at 10 MHz, then switching to 4 MHz. 3 When the external hard reset signal applied to the RESET# pin is negated, the CLKOUT signal frequency is stabilized after maximum 8 µT. Figure 2-8. CLKOUT Generation During External Hard Reset 2.4.5 MFR4200 Connection to FlexRay Network Figure 2-9 shows an example of connecting a FlexRay Optical/Electrical PHY to the MFR4200. Figure 2-10 shows how to connect the RS485 transceiver to the CC. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 49 Device Overview RXD_BG1 TXD_BG1 TXEN1 BGE1 RXD1 TXD1 Bus Driver 1 TXEN1 BGE1 Bus Guardian 1 MFR4200 MT MT BGT BGT ARM ARM BGE2 RXD_BG2 TXD_BG2 TXEN1 Bus Guardian 2 BGE2 RXD2 Bus Driver 2 TXD2 TXEN2 Figure 2-9. Example: Connecting a FlexRay Optical/Electrical PHY to the MFR4200 RXD1_485 TXD1_485 TXEN1_485 BGE1 MFR4200 RXD1 TXD1 RS485 Transceiver 1 TXEN1 BGE1 Not Connected Inverter MT Not Connected BGT BGT Not Connected ARM ARM MT BGE2 RXD2_485 TXD2_485 TXEN2_485 BGE2 Not Connected Not Connected RXD2 RS485 Transceiver 2 TXD2 TXEN2 Figure 2-10. Example: Connecting an RS485 PHY to the MFR4200 MFR4200 Data Sheet, Rev. 1 50 Freescale Semiconductor Resets and Interrupts NOTE TXENn signals for the FlexRay Optical/Electrical PHY are multiplexed with TXENn_485 signals for the RS485 interfaces. Therefore, additional external inverters are required for these signals in the RS485 mode. 2.4.6 Power Mode No power saving features are implemented in the MFR4200; the device operates only in power mode. 2.5 2.5.1 Resets and Interrupts Overview All possible MFR4200 internal interrupt sources are combined and provided to the host by means of one available interrupt line: INT_CC#. Refer to Chapter 3, “MFR4200 FlexRay Communication Controller” for more information on available interrupt sources. The type of interrupt is level sensitive. MFR4200 has the following resets: • external hard reset input signal RESET#. • internal power-on and low-voltage resets provided by the internal voltage regulator (refer to Chapter 5, “Clocks and Reset Generator” and Chapter 4, “Dual Output Voltage Regulator (VREG3V3V2)” for more information). 2.5.2 Resets When a reset occurs, MFR4200 registers and control bits are changed to known startup states. Refer to the respective module chapters for register reset states for information of the different kind of resets and for register reset states. 2.5.2.1 I/O Pins Refer to Chapter 3, “MFR4200 FlexRay Communication Controller” for configuration of MFR4200 pins out of reset. 2.5.3 Interrupt Sources All interrupt sources available in the MFR4200 are controlled and indicated by the following registers: • Interrupt status register 0 (ISR0) • Interrupt enable register 0 (IER0) • Startup interrupt status register (SISR) • Startup interrupt enable register (SIER) For more information on interrupt sources, refer to Chapter 3, “MFR4200 FlexRay Communication Controller. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 51 Device Overview MFR4200 Data Sheet, Rev. 1 52 Freescale Semiconductor Chapter 3 MFR4200 FlexRay Communication Controller 3.1 Introduction This version of the MFR4200 communication controller block guide supports MFR4200 devices with the mask numbers 0L60X and 1L60X. 3.1.1 MFR4200 Features The MFR4200 provides the following features. • The FlexRay protocol according to FlexRay Protocol Working document (PWD) V1.1, with differences described in the MFR4200 Protocol Implementation Document (PID) • Data rate of up to 10 Mbit/s on each of two channels • FlexRay frames with up to 254 payload bytes (padding is used for FlexRay payload data that exceeds 32-byte data size boundary) • One configurable receive FIFO • Configurable counters, status indicators, and interrupts dedicated to error signalling • Measured value indicators for clock synchronization • The status of up to four slots can be observed independently of CC receive message buffers • Configurable error signaling • Fractional macroticks (MT) supported for clock correction • 59 message buffers, each with up to 32 payload bytes • Message buffers configurable with state or event semantics • Each message buffer can be configured as a receive message buffer, as a transmit message buffer (single or double), or as a part of the receive FIFO • Receive background buffers for each channel • The host accesses all buffers by means of three active message buffers (active transmit message buffer, active receive message buffer and active receive FIFO buffer) • Filtering for frame ID, cycle counter, and channel for receive and transmit message buffers • Filtering for frame ID, channel, and message ID for the receive FIFO • Maskable interrupt sources provided over one interrupt line • Two types of host interface: HCS12 interface and asynchronous memory interfaces • Minislot action point offset is configurable • Static slot action point offset is configurable • Hardware selectable clock output to drive external host devices: disabled/4/10/40 MHz • Electrical physical layer interface compatible with dedicated FlexRay physical layer. Industry standard RS485 physical layer interface also available. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 53 MFR4200 FlexRay Communication Controller 3.1.2 MFR4200 Implementation Parameters and Constraints 3.1.2.1 • • • Implementation Parameters The duration of a microtick (µT) is one CC_CLK period (25 ns at 40 MHz); a microtick starts with a rising edge of CC_CLK. The CC internal initialization procedure lasts for 1025 cycles of the CC_CLK clock; it starts after leaving the hard reset state (see Section 3.9.1, “Hard Reset State”). After the external hard reset signal on the RESET# pin is negated, the CLKOUT signal frequency is stabilized after 8 µT. NOTE Refer to Section 3.8, “External 4/10 MHz Output Clock” for more information on the CLKOUT output. 3.1.2.2 • • • • • • 3.2 3.2.1 Implementation Constraints The maximum external clock frequency is 40 MHz (CC_CLK). Minislot length down to 2 µs (at CC_CLK frequency of 40 MHz) for the dynamic segment. Minislot length is configurable (minimum 2 MT). The maximum communication cycle length is 16 ms. Collision avoidance symbol length is set to 30 bits. The maximum configurable static slot length is 255 MT. Memory Map and Registers Introduction This section describes the memory map, and the content and use of the registers in the host interface module. A memory map of the CC is shown in Table 3-1. The host accesses four types of CC registers: • General control registers • Buffer control, configuration, status and filtering register sets • FIFO acceptance/rejection filter register sets • Fifty-nine (59) configurable message buffers. The host can configure every buffer as a receive message buffer, as a transmit message buffer (single or double), or as a FIFO receive message buffer. All buffers are accessible through three active windows mirrored to the memory map: — One active transmit message buffer — One active receive message buffer — One active FIFO buffer MFR4200 Data Sheet, Rev. 1 54 Freescale Semiconductor Memory Map and Registers NOTE The CC has two shadow receive message buffers per channel (four shadow buffers, in total); these allow reception while the host accesses the receive message buffers. One additional shadow message buffer is used for internal operations. Therefore, only 59 buffers out of 64 are available to the user as message buffers. 3.2.2 Register Map Summary Table 3-1. Register Map Summary Register Description Address (Hex) Address (Dec) Hard Reset (Hex) MNR Magic Number Register 0 0 815 MVR0 Module Version Register 0 2 2 9042 MCR0 Module Configuration Register 0 4 4 8000 MCR1 Module Configuration Register 1 6 6 0 CMCVR Current Macrotick Counter Value Register 8 8 0 CCCVR Current Cycle Counter Value Register 0A 10 0 PSR Protocol State Register 0C 12 0 ISR0 Interrupt Status Register 0 0E 14 0 SISR Startup Interrupt Status Register 10 16 0 CHIER CHI Error Register 12 18 0 IER0 Interrupt Enable Register 0 14 20 0 SIER Startup Interrupt Enable Register 16 22 0 FSIZR FIFO Size Register 18 24 0 FAFCHR FIFO Acceptance/Rejection Filter Channel Register 1A 26 0 FAFMIDVR FIFO Acceptance Filter Message ID Value Register 1C 28 0 FAFMIDMR FIFO Acceptance Filter Message ID Mask Register 1E 30 0 FRFFIDVR FIFO Rejection Filter Frame ID Value Register 20 32 0 FRFFIDMR FIFO Rejection Filter Frame ID Mask Register 22 34 0 RBIVECR Receive Buffer Interrupt Vector Register 24 36 0 TBIVECR Transmit Buffer Interrupt Vector Register 26 38 0 SSCIR Slot Status Counter Incrementation Register 28 40 0 SSCIMR Slot Status Counter Interrupt Mask Register 2A 42 0 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 55 MFR4200 FlexRay Communication Controller Table 3-1. Register Map Summary Register Description Address (Hex) Address (Dec) Hard Reset (Hex) 2C, 2E 44, 46 0 CSECnR Channel Status Error Counter n Register, n=[0:1] TICR0CS Timer Interrupt Configuration Register 0 Cycle Set 30 48 0 TICR0MO Timer Interrupt Configuration Register 0 Macrotick Offset 32 50 0 TICR1CS Timer Interrupt Configuration Register 1 Cycle Set 34 52 0 TICR1MO Timer Interrupt Configuration Register 1 Macrotick Offset 36 54 0 DBPCR Debug Port Control Register 38 56 0 BGSR Bus Guardian Status Register 3A 58 0 DCR Delay Counter Register 3C 60 0 NMVLR Network Management Vector Length Register 3E 62 0 GNMVnR Global Network Management Vector n Register, n=[0:5] GNMV0R=40 GNMV1R=42 GNMV2R=44 GNMV3R=46 GNMV4R=48 GNMV5R=4A GNMV0R=64 GNMV1R=66 GNMV2R=68 GNMV3R=70 GNMV4R=72 GNMV5R=74 0 SSCnR Slot Status Counter n Register, n=[0:7] SSC0R=4C SSC1R=4E SSC2R=50 SSC3R=52 SSC4R=54 SSC5R=56 SSC6R=58 SSC7R=5A SSC0R=76 SSC1R=78 SSC2R=80 SSC3R=82 SSC4R=84 SSC5R=86 SSC6R=88 SSC7R=90 0 SSCCnR Slot Status Counter Condition n Register, n=[0:7] SSCC0R=5C SSCC1R=5E SSCC2R=60 SSCC3R=62 SSCC4R=64 SSCC5R=66 SSCC6R=68 SSCC7R=6A SSCC0R=92 SSCC1R=94 SSCC2R=96 SSCC3R=98 SSCC4R=100 SSCC5R=102 SSCC6R=104 SSCC7R=106 0 SSSnR Slot Status Selection n Register, n=[0:3] SSS0R=6C SSS1R=6E SSS2R=70 SSS3R=72 SSS0R=108 SSS1R=110 SSS2R=112 SSS3R=114 0 MFR4200 Data Sheet, Rev. 1 56 Freescale Semiconductor Memory Map and Registers Table 3-1. Register Map Summary Register Description Address (Hex) Address (Dec) Hard Reset (Hex) SS0R=74 SS1R=76 SS2R=78 SS3R=7A SS4R=7C SS5R=7E SS6R=80 SS7R=82 SS0R=116 SS1R=118 SS2R=120 SS3R=122 SS4R=124 SS5R=126 SS6R=128 SS7R=130 0 SSnR Slot Status n Register, n=[0:7] SWCTRLR Symbol Window Control Register 84 132 0 SWSAR Symbol Window Status channel A Register 86 134 0 SWSBR Symbol Window Status channel B Register 88 136 0 WMCTRLR Wakeup Mechanism Control Register 8A 138 0 NSSR Number of Static Slots Register 8E 142 1 SPLR Static Payload Length Register 90 144 0 MPLDR Maximum Payload Length Dynamic Register 92 146 0 SYNCFR Sync Frame Register 94 148 0 SYNCHR Sync Frame Header Register 96 150 undefined MVR1 Module Version Register 1 98 152 For mask set number: 0L60X – 0; 1L60X – 0001 HIPDSR Host Interface Pins Drive Strength Register 9A 154 0 PLPDSR Physical Layer Pins Drive Strength Register 9C 156 0 HIPPER Host Interface Pins Pullup/down Enable Register 9E 158 0 HIPPCR Host Interface Pins Pullup/down Control Register A0 160 0 PLPPER Physical Layer Pins Pullup/down Enable Register A2 162 0 PLPPCR Physical Layer Pins Pullup/down Control Register A4 164 0 VREGSR Voltage Regulator Status Register A6 166 0 BDR Bit Duration Register A8 168 undefined IDLR Idle Detection Length Register AA 170 undefined NMLR Nominal Macrotick Length Register AC 172 undefined BGTR Bus Guardian Tick Register AE 174 undefined SSLR Static Slot Length Register B0 176 undefined MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 57 MFR4200 FlexRay Communication Controller Table 3-1. Register Map Summary Register Description Address (Hex) Address (Dec) Hard Reset (Hex) CLR Cycle Length Register B2 178 undefined MPCLR Microticks per Cycle Low Register B4 180 undefined MPCHR Microticks per Cycle High Register B6 182 undefined MCLDAR Maximum Cycle Length Deviation Register B8 184 undefined TSSLR Transmit Start Sequence Length Register BA 186 undefined SWCR Symbol Window Configuration Register BC 188 undefined NITCR Network Idle Time Configuration Register BE 190 undefined CSMR Coldstart Maximum Register C0 192 undefined MSFR Maximum Sync Frames Register C2 194 undefined LDTSR Latest Dynamic Transmission Start Register C4 196 undefined MSLR Minislot Length Register C6 198 undefined MSAPOR Minislot Action Point Offset Register C8 200 undefined SSAPOR Static Slot Action Point Offset Register CA 202 undefined MOCWCFR Maximum Odd Cycles Without Clock Correction Fatal Register CC 204 undefined DCAR Delay Compensation Channel A Register D0 208 undefined DCBR Delay Compensation Channel B Register D2 210 undefined LNLR Listen timeout with Noise Length Register D6 214 undefined MOCWCPR Maximum Odd Cycles Without clock Correction Passive Register D8 216 undefined MOCR Maximum Offset Correction Register DA 218 undefined MRCR Maximum Rate Correction Register DC 220 undefined CDDR Cluster Drift Damping Register DE 222 undefined SOCCTR Start of Offset Correction Cycle Time Register E0 224 undefined WUSTXIR Wakeup Symbol TX Idle Register EA 234 0 WUSTXLR Wakeup Symbol TX Low Register EC 236 0 SYNFAFMR Sync Frame Acceptance Filter Mask Register EE 238 undefined SYNFAFVR Sync Frame Acceptance Filter Value Register F0 240 undefined SYNFRFR Sync Frame Rejection Filter Register F2 242 undefined EOCR External Offset Correction Register F4 244 undefined ERCR External Rate Correction Register F6 246 undefined MFR4200 Data Sheet, Rev. 1 58 Freescale Semiconductor Memory Map and Registers Table 3-1. Register Map Summary Register Description Address (Hex) Address (Dec) Hard Reset (Hex) ECCR External Correction Control Register F8 248 undefined AFBFRID Active FIFO Buffer Frame ID Register 100 256 undefined AFBCCPLR Active FIFO Buffer Cycle Counter and Payload Length Register 102 258 undefined AFBCRCR Active FIFO Buffer Header CRC Register 104 260 undefined AFBDATAnR Active FIFO Buffer Data n Register, n=[0:15] AFBMBSSVR Active FIFO Buffer Message Buffer Slot Status Vector Register 126 294 undefined ARBFRID Active Receive Buffer Frame ID Register 140 320 undefined ARBCCPLR Active Receive Buffer Cycle Counter and Payload Length Register 142 322 undefined ARBCRCR Active Receive Buffer Header CRC Register 144 324 undefined ARBDATAnR Active Receive Buffer Data n Register, n=[0:15] ARBDATA0R=146 … ARBDATA15R=164 ARBDATA0R=326 … ARBDATA15R=356 undefined ARBMBSSVR Active Receive Buffer Message Buffer Slot Status Vector Register 166 358 undefined ATBFRID Active Transmit Buffer Frame ID Register 180 384 undefined ATBCCPLR Active Transmit Buffer Cycle Counter and Payload Length Register 182 386 undefined ATBCRCR Active Transmit Buffer Header CRC Register 184 388 undefined ATBDATAnR Active Transmit Buffer Data n Register, n=[0:15] ATBDATA0R=186 … ATBDATA15R=1A4 ATBDATA0R=390 … ATBDATA15R=420 undefined ATBMBSSVR Active Transmit Buffer Message Buffer Slot Status Vector Register 1A6 422 undefined BUFCSnR Message Buffer Control, Configuration and Status n Register, n=[0:58] BUFCS0R=200 BUFCS1R=204 … BUFCS57R=2E4 BUFCS58R=2E8 BUFCS0R=512 BUFCS1R=516 … BUFCS57R=740 BUFCS58R=744 IFLG, IENA, CFG and VALID bits are reset to 0; others are undefined CCFnR Cycle Counter Filter n Register, n=[0:58] CCF0R=202 CCF1R=206 … CCF57R=2E6 CCF58R=2EA. CCF0R=514 CCF1R=518 … CCF57R=742 CCF58R=746 undefined CCFCR Clock Correction Failed Counter Register 326 806 undefined EHLR Error Handling Level Register 328 808 undefined ARFBDATA0R=106 ARFBDATA0R=262 … … ARFBDATA15R=124 ARFBDATA15R=292 undefined MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 59 MFR4200 FlexRay Communication Controller Table 3-1. Register Map Summary Register Description Address (Hex) Address (Dec) Hard Reset (Hex) RCVR Rate Correction Value Register 32A 810 undefined OCVR Offset Correction Value Register 32C 812 undefined EMCR Even Measurement Counter Register 33C 828 undefined OMCR Odd Measurement Counter Register 33E 830 undefined EMAnR Even Measurement channel A n Register, n=[0:15] EMA0R=340 … EMA15R=35E EMA0R=832 … EMA15R=862 undefined EMBnR Even Measurement channel B n Register, n=[0:15] EMB0R=360 … EMB15R=37E EMB0R=864 … EMB15R=894 undefined ESFIDnR Even Sync ID n Register, n=[0:15] EID0R=380 … EID15R=39E EID0R=896 … EID15R=926 undefined OMAnR Odd Measurement channel A n Register, n=[0:15] OMA0R=3A0 … OMA15R=3BE OMA0R=928 … OMA15R=958 undefined OMBnR Odd Measurement channel B n Register, n=[0:15] OMB0R=3C0 … OMB15R=3DE OMB0R=960 … OMB15R=990 undefined OSFIDnR Odd Sync Frame ID n Register, n=[0:15] OSFID0R=3E0 … OSFID15R=3FE OSFID0R=1008 … OSFID15R=1022 undefined 3.2.3 Register Descriptions A condensed overview of all registers is provided in Section 3.2.2, “Register Map Summary” • • • • • NOTE All registers not shown in the CC memory map registers are not implemented in hardware. Any read operation on bits marked as ‘Reserved’ will return an undefined value (either ‘1’ or ‘0’). The host must take care that bits marked as ‘Reserved’ are set to 0 when writing. The reset value indicated for each register is the value that the register has after a hard reset operation. Meaning of the bit field character in the registers layout: – ‘r’ indicates that the bit-field may be read by host – ‘w’ denotes that the bit-field may be updated by host – ‘h’ means that the bit-field is updated by the communication controller MFR4200 Data Sheet, Rev. 1 60 Freescale Semiconductor Memory Map and Registers • Combinations such as ‘rh’, ‘rw’ or ‘rwh’ appear in the text indicating the different access possibilities. An additional asterisk ‘*’ indicates an exceptional behavior, i.e. under which conditions the host is allowed to write a ‘rw’ or ‘rwh’ bit-field, etc. In such cases, refer to the detailed bit-field description. Descriptions of configuration registers specify the possible range of values in square brackets – [,]. • • NOTE The configuration registers’ possible ranges of values, specified in square brackets [ : ], denote only the MFR4200 implementation constraints. Not every configuration supported by the MFR4200 implementation is necessarily a valid configuration of an application network. For more information about configuration constraints, refer to the PWD: Configuration Constraints Notations chapter. A key to the register diagrams is shown in Figure 3-1. Section Number Register Full Name Register Short Name FlexRay Protocol Related Parameter 3.2.3.3.1 Bit Duration Register (BDR) FlexRay Protocol Related Parameter – gdBit Address0xA8 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved BD6 BD5 BD4 BD3 BD2 BD1 BD0 r rw* rw* rw* rw* rw* rw* rw* Register Address Register Reset Value/State Bit Number Bit Access Scheme Bit Name Figure 3-1. Key to Register Diagrams MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 61 MFR4200 FlexRay Communication Controller 3.2.3.1 Controller’s Constants Registers 3.2.3.1.1 Module Version Register 0 (MVR0) Address 0x2 Reset 0x9042 15 14 13 12 11 10 9 8 MJFR3 MJFR2 MJFR1 MJFR0 MINFR3 MINFR2 MINFR1 MINFR0 r r r r r r r r 7 6 5 4 3 2 1 0 PDA7 PDA6 PDA5 PDA4 PDA3 PDA2 PDA1 PDA0 r r r r r r r r Figure 3-2. Module Version Register 0 The read-only MVR0, together with MVR1 (see following section), holds the version number of the implementation. The MVR0 contains the following fields: PDA[0:7] denotes the device PartID1. MINFR[0:3] denotes the minor release of the FlexRay core in the MFR4200 device. MJFR[0:3] denotes the major release of the FlexRay core in the MFR4200 device. 3.2.3.1.2 Module Version Register 1 (MVR1) Address 0x98 Reset Device Mask Set Number Reset Value MFR4200 0L60X 0x0000 MFR4200 1L60X 0x0001 15 14 13 12 11 10 9 8 PDB7 PDB6 PDB5 PDB4 PDB3 PDB2 PDB1 PDB0 r r r r r r r r 7 6 5 4 3 2 1 0 MJMR3 MJMR2 MJMR1 MJMR0 MINMR3 MINMR2 MINMR1 MINMR0 r r r r r r r r Figure 3-3. Module Version Register 1 The read-only MVR1, together with MVR0 (see previous section), holds the version number of the implementation. The MVR1 contains: MFR4200 Data Sheet, Rev. 1 62 Freescale Semiconductor Memory Map and Registers PDB[0:7] denotes the device PartID2. MINMR[0:3] denotes the minor release of the MFR4200 device. MJMR[0:3] denotes the major release of the MFR4200 device. 3.2.3.1.3 Magic Number Register (MNR) Address 0x0 Reset 0x0815 15 14 13 12 11 10 9 8 MN15 MN14 MN13 MN12 MN11 MN10 MN9 MN8 r r r r r r r r 7 6 5 4 3 2 1 0 MN7 MN6 MN5 MN4 MN3 MN2 MN1 MN0 r r r r r r r r Figure 3-4. Magic Number Register This read-only register contains the arbitrary value 0x0815; it is used for endianess and memory map address offset checks. NOTE The MNR contains 0x0000 while the controller is initializing after leaving the hard reset state. Only after this initialization is completed, does it contain the value 0x0815. After the controller leaves the hard reset state, the host must wait until the initialization is completed before reading or writing to the controller. The initialization takes 1025 cycles (CC_CLK) after de-assertion of the hard reset. During the internal initialization procedure time, the host must not access any CC register except MNR (see Section 3.2.3.1.3, “Magic Number Register (MNR)”), which acknowledges the completion of the internal initialization procedure. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 63 MFR4200 FlexRay Communication Controller 3.2.3.2 Configuration Registers 3.2.3.2.1 Module Configuration Register 0 (MCR0) Address 0x4 Reset 0x8000 15 14 13 12 11 10 9 8 CONFIG Reserved Reserved Reserved Reserved Reserved CBE CAE rwh r r r r r rw* rw* 7 6 5 4 3 2 1 0 Reserved ENSYNFF NSYNC SCM1 SCM0 Reserved DIAGSTOP Reserved r rw* rh rw* rw* r rw r Figure 3-5. Module Configuration Register 0 NOTE Setting the CONFIG bit and writing to other bits in this register can be done in separate instructions only. Trying to set CONFIG and change other bits at the same time will change CONFIG only — the other bits will not be changed. Clearing CONFIG and writing to other bits in the MCR0 can be done simultaneously in one instruction. DIAGSTOP — Diagnosis Stop State Bit When this bit is set by the host, the CC immediately enters the Diagnosis Stop state. Any ongoing transmission or reception is aborted, and synchronization with the FlexRay communication bus is lost. When this bit is cleared by the host, the controller enters the configuration state. 1 – The CC is in the Diagnosis Stop state. 0 – The CC is not in the Diagnosis Stop state. SCM0, SCM1 — Serial Communication Mode Bits 0 and 1 These bits define the type of bus driver connected to the controller. It can be written during the configuration state only. Table 3-2. Bus Driver Type Selection Driver type SCM1 SCM0 RS485 (IDLE state coded as “0”) 0 0 Optical/Electrical PHY 0 1 — 1 0 RS485 (IDLE state coded as “1”) 1 1 MFR4200 Data Sheet, Rev. 1 64 Freescale Semiconductor Memory Map and Registers NOTE It is not possible to mix different RS485’s in a cluster or per channel, or to mix RS485 and Optical/Electrical PHY. NSYNC — Node Synchronized This read-only bit is set when the controller enters the normal state in the course of startup or reintegration. The NSYNC is set by the CC in the NIT preceding a transition to normal operation. The NSYNC is cleared by the CC in the NIT, prior to switching to the normal passive state (the ‘yellow’ error state; see Section 3.2.3.6.5, “Error Handling Level Register (EHLR)”) or the Diagnosis Stop state (the ‘red’ error state; see Section 3.2.3.6.5, “Error Handling Level Register (EHLR)”), due to… • …the correction value exceeding MRCR (see Section 3.2.3.3.25, “Maximum Rate Correction Register (MRCR)”) • …the offset correction value exceeding MOCR (see Section 3.2.3.3.24, “Maximum Offset Correction Register (MOCR)”) • …the CCFCR value (see Section 3.2.3.6.4, “Clock Correction Failed Counter Register (CCFCR)”) exceeding MOCWCPR (see Section 3.2.3.5.3, “Maximum Odd Cycles Without clock Correction Passive Register (MOCWCPR)”) or MOCWCFR (see Section 3.2.3.5.2, “Maximum Odd Cycles Without Clock Correction Fatal Register (MOCWCFR)). 1 – Node is synchronized to cluster. 0 – Node is not synchronized to cluster. ENSYNFF — Enable Sync Frame Filters This bit enables/disables acceptance and rejection filtering for sync frames (see Section 3.2.3.8.1, “Sync Frame Acceptance Filter Value Register (SYNFAFVR)”, Section 3.2.3.8.2, “Sync Frame Acceptance Filter Mask Register (SYNFAFMR)” and Section 3.2.3.8.3, “Sync Frame Rejection Filter Register (SYNFRFR)”). 1 – Sync frames are used for the clock synchronization only when they pass the acceptance filter and are not rejected by the rejection filter. 0 – Sync frames are used for the clock synchronization independently of the acceptance and rejection filter. CAE — Channel A Enable This bit enables channel A. It can be written during the configuration state only. 1 – Channel A is enabled. 0 – Channel A is disabled. CBE — Channel B Enable This bit enables channel B. It can be written during the configuration state only. 1 – Channel B is enabled. 0 – Channel B disabled. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 65 MFR4200 FlexRay Communication Controller CONFIG — Configuration State Bit When the host sets this bit, the CC immediately enters the configuration state. The controller aborts any ongoing transmission or reception and abandons synchronization to the FlexRay cluster. When the host clears this bit, the controller resumes normal operation (see Section 3.9.2, “Configuration State”). After a hard reset, the controller automatically enters the configuration state (CONFIG bit set). 1 – Configuration state. 0 – Normal operation. 3.2.3.2.2 Module Configuration Register 1 (MCR1) Address 0x6 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved AYTG ARL CSI r r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 Reserved ECSE BGSMDSE BGSMSWE Reserved MATE Reserved Reserved r rw* rw* rw* r rw* r r Figure 3-6. Module Configuration Register 1 MATE — Media Access Test Enable This flag enables the media access test in the MFR4200 bus guardian (BG) monitor. This flag may be written in the configuration state only. 1 – Media access test is enabled. 0 – Media access test is disabled. BGSMSWE — BG Schedule Monitoring Symbol Window Enable This flag determines the behavior of the MFR4200 bus guardian schedule monitor during the symbol window. It may be written in the configuration state only. 1 – BG is expected to be open during symbol window of the communication cycle. 0 – BG is expected to be closed during symbol window of the communication cycle. BGSMDSE — BG Schedule Monitoring Dynamic Segment Enable This flag determines the behavior of the MFR4200 bus guardian monitor during the dynamic segment of the communication cycle. It may be written in the configuration state only. 1 – BG expected to be open during dynamic segment of the communication cycle. 0 – BG expected to be closed during dynamic segment of the communication cycle. MFR4200 Data Sheet, Rev. 1 66 Freescale Semiconductor Memory Map and Registers ECSE — External Clock Synchronization Enable This configuration flag enables/disables the External Clock Synchronization. It can be written during the configuration state only. 1 – External Clock Synchronization is enabled. 0 – External Clock Synchronization is disabled. CSI — Coldstart Inhibit Mode The node can be prevented from initializing the TDMA communication schedule by setting the CSI bit to ‘1’ in the configuration state. It can be written during the configuration state only. 1 – Node is in Coldstart Inhibit mode. 0 – Node is not in Coldstart Inhibit mode. ARL — Allow Red Level If this bit is set, the transition to the red error handling level (Diagnosis Stop state) due to clock sync errors is allowed. It may be written in the configuration state only. 1 – Error handling level red is allowed (the CC enters the Diagnosis Stop state). 0 – Error handling level red is prohibited (the CC enters the configuration state). AYTG — Allow Yellow to Green If this bit is set, the transition from the yellow error handling level to the green error handling level is allowed. It may be written in the configuration state only. 1 – Transition from yellow to green is allowed. 0 – Transition from yellow to green is prohibited. 3.2.3.2.3 Host Interface and Physical Layer Pins Drive Strength Register (HIPDSR) Address 0x9A Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved INT_CC# CLKOUT ARM/DBG1/ CLK_S0 MT/CLK_S1 BGT/DBG2/ IF_SEL0 PAD[0:15]/ D[15:0] r r rw rw rw rw rw rw Figure 3-7. Host Interface Pins Drive Strength Register This register controls the drive strength of the MFR4200 pins identified in Figure 3-7. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 67 MFR4200 FlexRay Communication Controller 1 – Pin drive strength is partial (see Appendix A.1.9, “I/O Characteristics”). 0 – Pin drive strength is full (see Appendix A.1.9, “I/O Characteristics”). 3.2.3.2.4 Physical Layer Pins Drive Strength Register (PLPDSR) Address 0x9C Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved TXD_BG2/ TXD2_485 TXD_BG1/ TXD1_485/ IF_SEL1 TXEN2#/ TXE2_485# TXEN1#/ TXE1_485# r r r r rw rw rw rw Figure 3-8. Physical Layer Pins Drive Strength Register This register controls the drive strength of the MFR4200 pins identified in Figure 3-8. 1 – Pin drive strength is partial (see Section A.1.9, “I/O Characteristics”). 0 – Pin drive strength is full (see Section A.1.9, “I/O Characteristics”). 3.2.3.2.5 Host Interface Pins Pullup/down Enable Register (HIPPER) Address 0x9E Reset 0x0 15 14 13 12 11 10 9 8 ECLK_CC WE#/ RW_CC# CE#/LSTRB D[15:0]/ PAD[0:15] ACS5 ACS4 OE#/ACS3 A9/ACS2 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 A8/ACS1 A7/ACS0 A6/ XADDR14 A5/ XADDR15 A4/ XADDR16 A3/ XADDR17 A2/ XADDR18 A1/ XADDR19 rw rw rw rw rw rw rw rw Figure 3-9. Host Interface Pins Pullup/down Enable Register This register enables the pullups and pulldowns on MFR4200 pins identified in Figure 3-9. The pullup/down state is controlled by the HIPPCR (see Section 3.2.3.2.6, “Host Interface Pins Pullup/down Control Register (HIPPCR)”). 1 – Pullup/down resistor enabled. MFR4200 Data Sheet, Rev. 1 68 Freescale Semiconductor Memory Map and Registers 0 – Pullup/down resistor disabled. 3.2.3.2.6 Host Interface Pins Pullup/down Control Register (HIPPCR) Address 0xA0 Reset 0x0 15 14 13 12 11 10 9 8 ECLK_CC WE#/ RW_CC# CE#/LSTRB D[15:0]/ PAD[0:15] ACS5 ACS4 OE#/ACS3 A9/ACS2 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 A8/ACS1 A7/ACS0 A6/ XADDR14 A5/ XADDR15 A4/ XADDR16 A3/ XADDR17 A2/ XADDR18 A1/ XADDR19 rw rw rw rw rw rw rw rw Figure 3-10. Host Interface Pins Pullup/down Control Register This register controls the pullups and pulldowns on MFR4200 pins identified in Figure 3-10. These functions can be enabled/disabled by the HIPPER (see Section 3.2.3.2.5, “Host Interface Pins Pullup/down Enable Register (HIPPER)”). 1 – Pullup selected. 0 – Pulldown selected. 3.2.3.2.7 Physical Layer Pins Pullup/down Enable Register (PLPPER) Address 0xA2 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved BGEN2 BGEN1 RXD_BG2/ RXD2_485 RXD_BG1/RX D1_485 r r r r rw rw rw rw Figure 3-11. Physical Layer Pins Pullup/down Enable Register This register enables the pullups and pulldowns on MFR4200 pins identified in Figure 3-11. The pullup/down state is controlled by the PLPPCR (see Section 3.2.3.2.8, “Physical Layer Pins Pullup/down Control Register (PLPPCR)”). 1 – Pullup/down enabled. 0 – Pullup/down disabled. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 69 MFR4200 FlexRay Communication Controller 3.2.3.2.8 Physical Layer Pins Pullup/down Control Register (PLPPCR) Address 0xA4 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved BGEN2 BGEN1 RXD_BG2/ RXD2_485 RXD_BG1/RX D1_485 r r r r rw rw rw rw Figure 3-12. Physical Layer Pins Pullup/down Control Register This register controls the pullups and pulldowns on MFR4200 pins identified in Figure 3-12. These function can be enabled/disabled by the PLPPER (see Section 3.2.3.2.7, “Physical Layer Pins Pullup/down Enable Register (PLPPER)”). 1 – Pullup selected. 0 – Pulldown selected. 3.2.3.2.9 Voltage Regulator Status Register (VREGSR) Address 0xA6 Reset 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Low-voltage Status Power-on Status r r r r r r rwh rwh Figure 3-13. Voltage Regulator Status Register This register indicates the occurrence of internal low-voltage and/or power-on reset events caused by power-on of MFR4200 device or supply voltage disturbances. The Low-voltage Status and Power-on Status bits do not cause an interrupt over the INT_CC# pin; therefore, the host may read this register to check the status. The host clears any status bit in VREGSR by reading VREGSR. The CC sets a status bit in the VREGSR again when it detects the condition for that bit. MFR4200 Data Sheet, Rev. 1 70 Freescale Semiconductor Memory Map and Registers Low-voltage Status, Power-on Status 1 – MFR4200 has been reset internally due to reset conditions sensed by the voltage regulator. 0 – MFR4200 has not been reset internally. NOTE Low-voltage and power-on events generated by the MFR4200 voltage regulator cause the internal MFR4200 reset with the same consequences as in the case of an external hard reset. Therefore, changes to the VREGSR bits can be read by the host only after the MFR4200 leaves the internal reset state. 3.2.3.3 3.2.3.3.1 Control Registers Bit Duration Register (BDR) FlexRay Protocol Related Parameter – gdBit Address 0xA8 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved BD6 BD5 BD4 BD3 BD2 BD1 BD0 r rw* rw* rw* rw* rw* rw* rw* Figure 3-14. Bit Duration Register This register controls the number of microticks per bit. Writing this register is possible only during the configuration state. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 71 MFR4200 FlexRay Communication Controller 3.2.3.3.2 Delay Compensation Channel A Register (DCAR) FlexRay Protocol Related Parameter – pDelayCompensation[A] Address 0xD0 Reset undefined state 15 14 13 12 11 10 9 8 DCA15 DCA14 DCA13 DCA12 DCA11 DCA10 DCA9 DCA8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 DCA7 DCA6 DCA5 DCA4 DCA3 DCA2 DCA1 DCA0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-15. Delay Compensation Channel A Register This register holds the value used to compensate for reception delays on channel A in microticks. The register can be written during the configuration state only. The value of this register must be within the range [0:127]. 3.2.3.3.3 Delay Compensation Channel B Register (DCBR) FlexRay Protocol Related Parameter – pDelayCompensation[B] Address 0xD2 Reset undefined state 15 14 13 12 11 10 9 8 DCB15 DCB14 DCB13 DCB12 DCB11 DCB10 DCB9 DCB8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 DCB7 DCB6 DCB5 DCB4 DCB3 DCB2 DCB1 DCB0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-16. Delay Compensation Channel B Register This register holds the value used to compensate for reception delays on channel B in microticks. The register can be written during the configuration state only. The value of this register must be within the range [0:127]. MFR4200 Data Sheet, Rev. 1 72 Freescale Semiconductor Memory Map and Registers 3.2.3.3.4 Cluster Drift Damping Register (CDDR) FlexRay Protocol Related Parameter – pClusterDriftDamping Address 0xDE Reset undefined state 15 14 13 12 11 10 9 8 CDD15 CDD14 CDD13 CDD12 CDD11 CDD10 CDD9 CDD8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 CDD7 CDD6 CDD5 CDD4 CDD3 CDD2 CDD1 CDD0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-17. Cluster Drift Damping Register This register defines the value used, in clock synchronization, to minimize the accumulation of rounding errors. This register can be written in the configuration state only. The register value is given in microticks and must be within the range [1:15]. 3.2.3.3.5 Maximum Sync Frames Register (MSFR) FlexRay Protocol Related Parameter – gSyncNodeMax Address 0xC2 Reset undefined state 15 14 13 12 11 10 9 8 MSF15 MSF14 MSF13 MSF12 MSF11 MSF10 MSF9 MSF8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 MSF7 MSF6 MSF5 MSF4 MSF3 MSF2 MSF1 MSF0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-18. Maximum Sync Frames Register This register holds the maximum number of sync frames that can be transmitted on either channel in a network, including a node’s own sync frame. The host may modify this register in the configuration state only. The value of this register must be within the range [2:15]. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 73 MFR4200 FlexRay Communication Controller 3.2.3.3.6 Nominal Macrotick Length Register (NMLR) FlexRay Protocol Related Parameter – pMicroPerMacroNom Address 0xAC Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 NML7 NML6 NML5 NML4 NML3 NML2 NML1 NML0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-19. Nominal Macrotick Length Register This register defines the integer number of microticks per nominal macrotick, according to Equation 3-1. NMLR = int (cycle length in µT / CLR) Eqn. 3-1 Writing this register is possible only in the configuration state. 3.2.3.3.7 Microticks Per Cycle Low Register (MPCLR) Address 0xB4 Reset undefined state 15 14 13 12 11 10 9 8 MPCL15 MPCL14 MPCL13 MPCL12 MPCL11 MPCL10 MPCL9 MPCL8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 MPCL7 MPCL6 MPCL5 MPCL4 MPCL3 MPCL2 MPCL1 MPCL0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-20. Microticks Per Cycle Low Register The MPCHR and MPCLR are described in the following section. The MPCLR can be written during the configuration state only. MFR4200 Data Sheet, Rev. 1 74 Freescale Semiconductor Memory Map and Registers 3.2.3.3.8 Microticks Per Cycle High Register (MPCHR) Address 0xB6 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 MPCH7 MPCH6 MPCH5 MPCH4 MPCH3 MPCH2 MPCH1 MPCH0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-21. Microticks Per Cycle High Register The MPCHR and MPCLR define the number of microticks per cycle. Writing these registers is possible only in the configuration state. The relationship between registers MPCHR, MPCLR, and CLR is given by Equation 3-2. MPCHR * 2^16 + MPCLR = (Cycle Length) – k * CLR Eqn. 3-2 Where: • Cycle Length = the length of a communication cycle in microticks • k = 1 [microtick/macrotick] 3.2.3.3.9 Static Slot Length Register (SSLR) FlexRay Protocol Related Parameter – gdStaticSlot Address 0xB0 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 SSL7 SSL6 SSL5 SSL4 SSL3 SSL2 SSL1 SSL0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-22. Static Slot Length Register This register defines the number of macroticks per slot. Writing this register is possible only in the configuration state. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 75 MFR4200 FlexRay Communication Controller 3.2.3.3.10 Number of Static Slots Register (NSSR) FlexRay Protocol Related Parameter – gNumberOfStaticSlots Address 0x8E Reset 0x1 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved NSS10 NSS9 NSS8 r r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 NSS7 NSS6 NSS5 NSS4 NSS3 NSS2 NSS1 NSS0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-23. Number of Static Slots Register This register defines the number of static slots in a cycle. Writing this register is possible only during the configuration state. NOTE The range of possible values for the NSSR is from 0x2 to 0x3FF. This means that at least two static slots must be programmed. 3.2.3.3.11 Static Payload Length Register (SPLR) FlexRay Protocol Related Parameter – gPayloadLengthStatic Address 0x90 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved SPL6 SPL5 SPL4 SPL3 SPL2 SPL1 SPL0 r rw* rw* rw* rw* rw* rw* rw* Figure 3-24. Static Payload Length Register This register defines the maximum data length for static frames in words (1 word = 2 bytes). Writing this register is possible only during the configuration state. MFR4200 Data Sheet, Rev. 1 76 Freescale Semiconductor Memory Map and Registers 3.2.3.3.12 Minislot Length Register (MSLR) FlexRay Protocol Related Parameter – gdMinislot Address 0xC6 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved MSL6 MSL5 MSL4 MSL3 MSL2 MSL1 MSL0 r rw* rw* rw* rw* rw* rw* rw* Figure 3-25. Minislot Length Register This register defines the minislot length in macroticks. The register can be written during the configuration state only. The value of this register must be within the range [2:63]. 3.2.3.3.13 Minislot Action Point Offset Register (MSAPOR) FlexRay Protocol Related Parameter – gdMinislotActionPointOffset Address 0xC8 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved MSAPO3 MSAPO2 MSAPO1 MSAPO0 r r r r rw* rw* rw* rw* Figure 3-26. Minislot Action Point Offset Register This register defines the offset of the action point within the minislot in macroticks. The register can be written during the configuration state only. The value of this register must be within the range [1:15]. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 77 MFR4200 FlexRay Communication Controller 3.2.3.3.14 Static Slot Action Point Offset Register (SSAPOR) FlexRay Protocol Related Parameter – gdActionPointOffset Address 0xCA Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved SSAPO3 SSAPO2 SSAPO1 SSAPO0 r r r r rw* rw* rw* rw* Figure 3-27. Static Slot Action Point Offset Register This register defines the offset of the action point in macroticks. The register can be written only during the configuration state. The value of this register must be within the range [1:15]. 3.2.3.3.15 Latest Dynamic Transmission Start Register (LDTSR) FlexRay Protocol Related Parameter – pLatestTx Address 0xC4 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved LDT13 LDT12 LDT11 LDT10 LDT9 LDT8 r r rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 LDT7 LDT6 LDT5 LDT4 LDT3 LDT2 LDT1 LDT0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-28. Latest Dynamic Transmission Start Register This register defines the cycle time after which dynamic frame transmission can start. If the cycle time is greater than this register’s value, the controller continues an ongoing dynamic frame transmission (started before this point in time) and does not start any new dynamic frame transmissions. The latest dynamic transmission start is expressed in macroticks. The register can be written only in the configuration state. MFR4200 Data Sheet, Rev. 1 78 Freescale Semiconductor Memory Map and Registers 3.2.3.3.16 Maximum Payload Length Dynamic Register (MPLDR) FlexRay Protocol Related Parameter – gMaxPayloadLengthDynamic Address 0x92 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved MPLD6* MPLD5* MPLD4* MPLD3* MPLD2* MPLD1* MPLD0* r rw* rw* rw* rw* rw* rw* rw* Figure 3-29. Maximum Payload Length Dynamic Register This register defines the maximum payload length in the dynamic segment, in terms of words (1 word = 2 bytes). This register can be written only during the configuration state. NOTE The value of the maximum payload length dynamic register is used for checking transmit message buffers (see the MDPLE bit description in Section 3.2.3.6.3, “CHI Error Register (CHIER)” and Section 3.3.2.7, “LEN[6: 0] — Payload Length”). 3.2.3.3.17 Symbol Window Configuration Register (SWCR) FlexRay Protocol Related Parameter – gdSymbolWindow Address 0xBC Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved SWC13 SWC12 SWC11 SWC10 SWC9 SWC8 r r rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 SWC7 SWC6 SWC5 SWC4 SWC3 SWC2 SWC1 SWC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-30. Symbol Window Configuration Register This register defines the cycle time in which the symbol window starts. The cycle time is measured in macroticks. This register may be modified only in the configuration state. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 79 MFR4200 FlexRay Communication Controller 3.2.3.3.18 Network Idle Time Configuration Register (NITCR) FlexRay Protocol Related Parameter – gdNIT Address 0xBE Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved NITC13 NITC12 NITC11 NITC10 NITC9 NITC8 r r rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 NITC7 NITC6 NITC5 NITC4 NITC3 NITC2 NITC1 NITC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-31. Network Idle Time Configuration Register This register defines the cycle time in which the network idle time starts. The cycle time is measured in macroticks. The register may be modified in the configuration state only. This register is related to the SOCCTR register (refer to the note in Section 3.2.3.3.34, “Start of Offset Correction Cycle Time Register (SOCCTR)”). NOTE Since the duration of the NIT must be longer than or equal to ceil ((1300µT + 170µT * MSFR)/NMLR) + 1 [nominal MT], Eqn. 3-3 this register must be configured to, at most CLR - NIT duration [nominal MT] 3.2.3.3.19 Eqn. 3-4 Cycle Length Register (CLR) FlexRay Protocol Related Parameter – gMacroPerCycle Address 0xB2 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved CL13 CL12 CL11 CL10 CL9 CL8 r r rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-32. Cycle Length Register This register defines the number of macroticks per cycle. Writing this register is possible during the configuration state only. The CC uses this register value during startup only. MFR4200 Data Sheet, Rev. 1 80 Freescale Semiconductor Memory Map and Registers 3.2.3.3.20 Maximum Cycle Length Deviation Register (MCLDAR) FlexRay protocol related parameter – gdMaxDrift Address 0xB8 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved MCLDA9 MCLDA8 r r r r r r rw* rw* 7 6 5 4 3 2 1 0 MCLDA7 MCLDA6 MCLDA5 MCLDA4 MCLDA3 MCLDA2 MCLDA1 MCLDA0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-33. Maximum Cycle Length Deviation Register This register defines the number of microticks for a communication cycle of another CC with the maximum deviation of 1500 ppm with respect to the local oscillator. Writing this register is possible only during the configuration state. The value for the MCLDAR is calculated from Equation 3-5: MCLDAR = ceil ( cycle_length[µT] * 1.5*10-3 ) 3.2.3.3.21 Eqn. 3-5 External Offset Correction Register (EOCR) FlexRay Protocol Related Parameter – pExternOffsetCorrection Address 0xF4 Reset undefined state 15 14 13 12 11 10 9 8 EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-34. External Offset Correction Register This register holds the absolute value of the initial external offset correction to be applied, together with the internal clock synchronization value (see Section 3.2.3.3.23, “External Correction Control Register (ECCR)”). The host may write this register during the configuration state only. The register value is expressed in microticks. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 81 MFR4200 FlexRay Communication Controller 3.2.3.3.22 External Rate Correction Register (ERCR) FlexRay Protocol Related Parameter – pExternRateCorrection Address 0xF6 Reset undefined state 15 14 13 12 11 10 9 8 ECR15 ECR14 ECR13 ECR12 ECR11 ECR10 ECR9 ECR8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 ERC7 ERC6 ERC5 ERC4 ERC3 ERC2 ERC1 ERC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-35. External Rate Correction Register This register holds the absolute value of the initial external rate correction to be applied, together with the internal clock synchronization value (see Section 3.2.3.3.23, “External Correction Control Register (ECCR)”). The host may write this register in the configuration state only. The register value is expressed in microticks. 3.2.3.3.23 External Correction Control Register (ECCR) Address 0xF8 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved ERCA ERCE EOCA EOCE r r r r rw rwh rw rwh Figure 3-36. External Correction Control Register NOTE This register must be set before the NIT start of communication cycle x, in order to affect the clock correction in the communication cycle x+1. EOCE — External Offset Correction Enable 0 – External offset correction disabled. 1 – External offset correction enabled. MFR4200 Data Sheet, Rev. 1 82 Freescale Semiconductor Memory Map and Registers NOTE If this bit is set by the host, external offset correction will be performed once during the subsequent double cycle; afterwards, this bit will be cleared automatically by the communication controller. EOCA — External Offset Correction Application 0 – Add external offset correction value. 1 – Subtract external offset correction value. ERCE — External Rate Correction Enable 0 – External rate correction disabled. 1 – External rate correction enabled. NOTE If this bit is set by the host, the external rate correction will be performed once during the subsequent double cycle, and afterwards this bit will be automatically cleared by the communication controller. ERCA — External Rate Correction Application 0 – Add external rate correction. 1 – Subtract external rate correction. 3.2.3.3.24 Maximum Offset Correction Register (MOCR) FlexRay Protocol Related Parameter – pOffsetCorrectionOut Address 0xDA Reset undefined state 15 14 13 12 11 10 9 8 MOC15 MOC14 MOC13 MOC12 MOC11 MOC10 MOC9 MOC8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 MOC7 MOC6 MOC5 MOC4 MOC3 MOC2 MOC1 MOC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-37. Maximum Offset Correction Register This register defines the maximum permitted absolute offset correction value, in microticks, to be applied by the internal clock synchronization algorithms. This register can be written during the configuration state only. The value of this register does not effect the external clock correction value. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 83 MFR4200 FlexRay Communication Controller 3.2.3.3.25 Maximum Rate Correction Register (MRCR) FlexRay Protocol Related Parameter – pRateCorrectionOut Address 0xDC Reset undefined state 15 14 13 12 11 10 9 8 MRC15 MRC14 MRC13 MRC12 MRC11 MRC10 MRC9 MRC8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 MRC7 MRC6 MRC5 MRC4 MRC3 MRC2 MRC1 MRC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-38. Maximum Rate Correction Register This register defines the maximum permitted absolute rate correction value, in microticks, to be applied by the internal clock synchronization algorithms. This register can be written during the configuration state only. The value of this register does not effect the external clock correction value. 3.2.3.3.26 Coldstart Maximum Register (CSMR) FlexRay Protocol Related Parameter – gColdStartAttempts Address 0xC0 Reset undefined state 15 14 13 12 11 10 9 8 CMS15 CMS14 CMS13 CMS12 CMS11 CMS10 CMS9 CMS8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 CSM7 CSM6 CSM5 CSM4 CSM3 CSM2 CSM1 CSM0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-39. Coldstart Maximum Register The value in this register determines the maximum number of coldstart attempts that a coldstarting startup node is allowed to make, when trying to start up the network without receiving a valid response from another node. After this number of coldstart attempts, the CC falls back to the integration listen state and does not perform another coldstart attempt, until the controller enters and leaves the configuration state again. If the register is programmed with the value ‘0’, then the CC is not allowed to start communication. Writing the coldstart maximum register is possible during the configuration state only. The value of this register must be within the range [0:32767]. MFR4200 Data Sheet, Rev. 1 84 Freescale Semiconductor Memory Map and Registers 3.2.3.3.27 Transmit Start Sequence Length Register (TSSLR) FlexRay Protocol Related Parameter – gdTSSTransmitter/pdTSSReceiver Address 0xBA Reset undefined state 15 14 13 12 11 10 9 8 TSSLR7 TSSLR6 TSSLR5 TSSLR4 TSSLR3 TSSLR2 TSSLR1 TSSLR0 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 TSSLT7 TSSLT6 TSSLT5 TSSLT4 TSSLT3 TSSLT2 TSSLT1 TSSLT0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-40. Transmit Start Sequence Length Register The TSSLR defines the length, in bits, of the transmit start sequence on the physical layer. Bits TSSLT[0:7] (LSB) define the nominal length of the transmit start sequence for transmission. Bits TSSLR[8:15] (MSB) define maximum length of the transmit start sequence for reception. Writing is possible only during the configuration state. 3.2.3.3.28 Network Management Vector Length Register (NMVLR) FlexRay Protocol Related Parameter – gNetworkManagementVectorLength Address 0x3E Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved NMVL3 NMVL2 NMVL1 NMVL0 r r r r rw* rw* rw* rw* Figure 3-41. Network Management Vector Length Register This register defines the length, in bytes, of the network management vector (see Section 3.2.3.4.6, “Global Network Management Vector n Register, n = [0:5] (GNMVnR)”). Writing is possible during the configuration state only. The value of this register must be within the range [0:12]. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 85 MFR4200 FlexRay Communication Controller 3.2.3.3.29 Sync Frame Register (SYNCFR) Address 0x94 Reset 0x0 15 14 13 12 11 10 9 8 SUP Reserved Reserved Reserved Reserved SYNCF10 SYNCF9 SYNCF8 rw* r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 SYNCF7 SYNCF6 SYNCF5 SYNCF4 SYNCF3 SYNCF2 SYNCF1 SYNCF0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-42. Sync Frame Register This register contains the identifier of the sync frame to be transmitted. This register can be written during the configuration state only. There is no sync frame to transmit, if this register holds the value 0x0. A hard reset clears the register. SUP — Startup This bit sets the startup frame indicator. It can be written in the configuration state only. 1 – CC is a startup node and has its startup frame indicator set. 0 – CC is not a startup node. 3.2.3.3.30 Sync Frame Header Register (SYNCHR) Address 0x96 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved SYNCRC10 SYNCRC9 SYNCRC8 r r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 SYNCRC7 SYNCRC6 SYNCRC5 SYNCRC4 SYNCRC3 SYNCRC2 SYNCRC1 SYNCRC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-43. Sync Frame Header Register This register contains the header CRC of the sync frame to be transmitted. This register can be written during the configuration state only. MFR4200 Data Sheet, Rev. 1 86 Freescale Semiconductor Memory Map and Registers NOTE The SYNCHR value overwrites the header CRC field of a transmit message buffer that: a) has the same frame ID as the SYNCF[0:10] field of the SYNCFR (see Section 3.2.3.3.29, “Sync Frame Register (SYNCFR)”), and b) was selected by the CC for transmission as a sync message. 3.2.3.3.31 Bus Guardian Tick Register (BGTR) Address 0xAE Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved BGT4 BGT3 BGT2 BGT1 BGT0 r r r rw* rw* rw* rw* rw* Figure 3-44. Bus Guardian Tick Register This register defines the period length of the bus guardian tick to be provided by the CC to the bus guardian. The value BGT[0:4], is expressed in multiples of the CC microtick. Writing this register is possible only during the configuration state. The value of this register must be within the range [2:16]. 3.2.3.3.32 Delay Counter Register (DCR) Address 0x3C Reset 0x0 15 14 13 12 11 10 9 8 DC15 DC14 DC13 DC12 DC11 DC10 DC9 DC8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-45. Delay Counter Register This register specifies the configurable part of the delay between the reset of the CONFIG bit (host writing MCR0.CONFIG) and the point in time when the controller actually leaves the configuration state (see Section 3.9.2, “Configuration State”). The delay is configurable in steps of eight microticks, i.e. the configured value * 8 = delay in microticks Eqn. 3-6 The host may write this register only during the configuration state. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 87 MFR4200 FlexRay Communication Controller 3.2.3.3.33 Debug Port Control Register (DBPCR) Address 0x38 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 CNTRL7 CNTRL6 CNTRL5 CNTRL4 CNTRL3 CNTRL2 CNTRL1 CNTRL0 rw rw rw rw rw rw rw rw Figure 3-46. Debug Port Control Register This register controls the output functions of the BGT and ARM_BG pins of the controller as described in Table 3-3. Bits CNTRL[7:4] determine the functionality of the port BGT pin. Bits CNTRL[3:0] determine the functionality of the port ARM_BG pin. Refer to 3.10, “Debug Port” for a detailed description of the debug functions. NOTE The output function controls of BGT and ARM_BG pins are independent of each other. Therefore, they may be set with equal or different values. Table 3-3. Encoding of Debug Port Control Fields CNTRL[7:4] and CNTRL[3:0] CNTRL[7:4], CNTRL[3:0] Mode of the BGT, Mode of the ARM_BG Signal 0 Normal operation of BGT and ARM_BG – 1 Protocol state change PCS 2 Slot start in static segment SSS 3 Minislot start MSS 4 RxD after glitch filter on channel A 5 Dynamic slot start on channel A 6 Start of frame on channel A 7 Received syntactically correct an semantically valid frame indication on channel A RCFA 8 Start of a communication cycle SCC 9 Macrotick MTS 10 Start of offset correction SOC 11 – 12 RxD after glitch filter on channel B RAGFA DSSA SFA – RAGFB MFR4200 Data Sheet, Rev. 1 88 Freescale Semiconductor Memory Map and Registers Table 3-3. Encoding of Debug Port Control Fields CNTRL[7:4] and CNTRL[3:0] (continued) CNTRL[7:4], CNTRL[3:0] Mode of the BGT, Mode of the ARM_BG Signal 13 Dynamic slot start on channel B 14 Start of frame on channel B 15 Received syntactically correct an semantically valid frame indication on channel B 3.2.3.3.34 DSSB SFB RCFB Start of Offset Correction Cycle Time Register (SOCCTR) FlexRay Protocol Related Parameter – gOffsetCorrectionStart Address 0xE0 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved SOCCT13 SOCCT12 SOCCT11 SOCCT10 SOCCT9 SOCCT8 r r rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 SOCCT7 SOCCT6 SOCCT5 SOCCT4 SOCCT3 SOCCT2 SOCCT1 SOCCT0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-47. Start of Offset Correction Cycle Time Register This register defines the delay time (in multiples of macroticks) after which the offset correction will start. Writing this register is possible only during the configuration state. NOTE The time interval between the start time of the NIT (see NITCR) and the Start of Offset Correction time is used by the CC for clock correction calculations. The minimum interval that must be ensured during NITCR and SOCCTR programming can be calculated from Equation 3-7: Delaymin = ceil(500µT + 110µT*MSFR)/NMLR) + 1 [nominal MT] Eqn. 3-7 Therefore, the SOCCTR value must be: SOCCTR >= NITCR + Delaymin [nominal MT] Eqn. 3-8 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 89 MFR4200 FlexRay Communication Controller 3.2.3.3.35 Idle Detection Length Register (IDLR) FlexRay protocol related parameter – gdDynamicSlotIdlePhase Address 0xAA Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved IDL3 IDL2 IDL1 IDL0 r r r r rw* rw* rw* rw* Figure 3-48. Idle Detection Length Register This register defines the number of minislots used by the CC for checking the duration of the network idle time between two consecutive frames in the dynamic segment. This includes the dynamic slot idle phase. Writing this register is possible only during the configuration state. The value of IDLR depends on the values of the bit duration register (Section 3.2.3.3.1, “Bit Duration Register (BDR)) and the minislot length register (Section 3.2.3.3.12, “Minislot Length Register (MSLR)). It can be calculated using Equation 3-9. IDLR = ceil( (11 * BDR) / (NMLR * MSLR) ). Eqn. 3-9 The value in the register must be in the range [1:15]. 3.2.3.3.36 Symbol Window Control Register (SWCTRLR) Address 0x84 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved CHB CHA Reserved Reserved Reserved Reserved Reserved r rw rw r r r r r Figure 3-49. Symbol Window Control Register This register controls the transmission of symbols in a symbol window of a communication cycle. The register may be modified during the configuration state and during normal operation. CHB and CHA determine whether a symbol will be transmitted on channel B or channel A, respectively. 1 – Symbol transmission enabled. MFR4200 Data Sheet, Rev. 1 90 Freescale Semiconductor Memory Map and Registers 0 – Symbol transmission disabled. 3.2.3.3.37 Wakeup Mechanism Control Register (WMCTRLR) Address 0x8A Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved CHB CHA CNT4 CNT3 CNT2 CNT1 CNT0 r rw* rw* rw* rw* rw* rw* rw* Figure 3-50. Wakeup Mechanism Control Register This register controls the transmission of wakeup symbols. The register may be modified in the configuration state only. CHB and CHA determine whether a wakeup symbol will be transmitted on channel B or channel A, respectively. 1 – Wakeup symbol transmission enabled. 0 – Wakeup symbol transmission disabled. CNT[4:0] determine the number of wakeup symbols to be transmitted. The controller will transmit at least two wakeup symbols if wakeup symbol transmission is enabled. 3.2.3.3.38 Wakeup Symbol TX Idle Register (WUSTXIR) FlexRay protocol related parameter – gdWakeupSymbolTxIdle Address 0xEA Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-51. Wakeup Symbol TX Idle Register This register controls the duration of the idle period of wakeup symbols. Bits CNT[7:0] determine the duration of the idle period in bit durations on the network. The register may be modified in the configuration state only. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 91 MFR4200 FlexRay Communication Controller 3.2.3.3.39 Wakeup Symbol TX Low Register (WUSTXLR) FlexRay protocol related parameter – gdWakeupSymbolTxLow Address 0xEC Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 r r rw* rw* rw* rw* rw* rw* Figure 3-52. Wakeup Symbol TX Low Register This register controls the duration of the low period of wakeup symbols. Bits CNT[5:0] determine the duration of the low period in bit durations on the network. The register may be modified only during the configuration state. 3.2.3.3.40 Listen Timeout With Noise Length Register (LNLR) FlexRay protocol related parameter – gListenNoise Address 0xD6 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved CNT4 CNT3 CNT2 CNT1 CNT0 r r r rw* rw* rw* rw* rw* Figure 3-53. Listen Timeout With Noise Length Register This register controls the duration of the listen timeout with noise. Bits CNT[4:0] determine the duration of the listen timeout as a number of communication cycles. The register may be modified in the configuration state only. MFR4200 Data Sheet, Rev. 1 92 Freescale Semiconductor Memory Map and Registers 3.2.3.4 3.2.3.4.1 Status Registers Protocol State Register (PSR) Address 0x0C Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved PS4 PS3 PS2 PS1 PS0 r r r rh rh rh rh rh Figure 3-54. Protocol State Register This register is used to indicate the internal state of the CC. This register is read-only for the host. A hard reset clears the register. Table 3-4. CC State Coding Code (Decimal) Slot Status Monitoring available Configuration 0 No Initialize Schedule 1 No Normal Active Operation 2 Yes Normal Passive Operation 3 Yes Integration Consistency Check 4 Yes Integration Listen 5 No Coldstart Listen 21 No Integration Coldstart Check 22 Yes Join Coldstart 23 Yes Coldstart Collision Resolution 24 No Coldstart Consistency Check 25 Yes Coldstart Gap 26 No Wakeup 11 No CC State NOTE Refer to note 2 in Section 3.2.3.5.7, “Slot Status Counter n Register, n = [0:7] (SSCnR)” for information on the MFR4200 slot status monitoring mechanisms. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 93 MFR4200 FlexRay Communication Controller 3.2.3.4.2 Current Cycle Counter Value Register (CCCVR) FlexRay protocol related parameter – vCycle Address 0x0A Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved CCCV5 CCCV4 CCCV3 CCCV2 CCCV1 CCCV0 r r rh rh rh rh rh rh Figure 3-55. Current Cycle Counter Value Register This register provides the current cycle counter value (bits CCCV[4:0]). The register is cleared by a hard reset or when leaving the configuration state. If the maximum value is reached, the counter wraps around to zero and continues counting. The current cycle counter value is measured in communication cycles. 3.2.3.4.3 Current Macrotick Counter Value Register (CMCVR) FlexRay protocol related parameter – vMacrotick Address 0x08 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved CMCV13 CMCV12 CMCV11 CMCV10 CMCV9 CMCV8 r r rh rh rh rh rh rh 7 6 5 4 3 2 1 0 CMCV7 CMCV6 CMCV5 CMCV4 CMCV3 CMCV2 CMCV1 CMCV0 rh rh rh rh rh rh rh rh Figure 3-56. Current Macrotick Counter Value Register This register indicates the current cycle time in macroticks (bits CMCV[13:0]. The register is cleared by a hard reset or when leaving the configuration state. The CC increments the register during the cycle, and clears it at the start of a new cycle. MFR4200 Data Sheet, Rev. 1 94 Freescale Semiconductor Memory Map and Registers 3.2.3.4.4 Offset Correction Value Register (OCVR) FlexRay protocol related parameter – vOffsetCorrection Address 0x32C Reset undefined state 15 14 13 12 11 10 9 8 OCV15 OCV14 OCV13 OCV12 OCV11 OCV10 OCV9 OCV8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 OCV7 OCV6 OCV5 OCV4 OCV3 OCV2 OCV1 OCV0 rh rh rh rh rh rh rh rh Figure 3-57. Offset Correction Value Register This read-only register indicates the offset correction value, in microticks, calculated by the clock synchronization algorithm (before external offset correction and before value limitation), at the end of each communication cycle. Data in this register is presented in 2’s complement form. The value in this register is valid after a communication cycle start and until its NIT start. The CC modifies OCVR during the NIT. 3.2.3.4.5 Rate Correction Value Register (RCVR) FlexRay protocol related parameter – vRateCorrection Address 0x32A Reset undefined state 15 14 13 12 11 10 9 8 RCV15 RCV14 RCV13 RCV12 RCV11 RCV10 RCV9 RCV8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 RCV7 RCV6 RCV5 RCV4 RCV3 RCV2 RCV1 RCV0 rh rh rh rh rh rh rh rh Figure 3-58. Rate Correction Value Register This read-only register indicates the rate correction value, in microticks, calculated by the clock synchronization algorithm (before external rate correction and value limitation), at the end of each odd communication cycle. Data in this register is presented in 2’s complement form. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 95 MFR4200 FlexRay Communication Controller 3.2.3.4.6 Global Network Management Vector n Register, n = [0:5] (GNMVnR) Address GNMV0R=0x40, GNMV1R=0x42, GNMV2R=0x44, GNMV3R=0x46, GNMV4R=0x48, GNMV5R=0x4A, Reset 0x0 15 14 13 12 11 10 9 8 GNMV15 GNMV14 GNMV13 GNMV12 GNMV11 GNMV10 GNMV9 GNMV8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 GNMV7 GNMV6 GNMV5 GNMV4 GNMV3 GNMV2 GNMV1 GNMV0 rh rh rh rh rh rh rh rh Figure 3-59. Global Network Management Vector n Register, n = [0:5] These read-only registers hold the global network management vector. The length of the network management vector is configured by means of the NMVLR register (see Section 3.2.3.3.28, “Network Management Vector Length Register (NMVLR)”). The GNMVnR registers are cleared during a hard reset. NOTE If the NMVLR register is programmed with a value less than 12, then the remaining bytes of the GNMVnR registers (which are not used for network management vector accumulating) will remain 0’s. The global network management vector, as presented in the communication cycle x, is the OR-combination of all network management vectors received in the communication cycle x-1. The controller ensures that the value read from GNMV0R is consistent. The mapping between the receive message buffer payload bytes and the GNMVnR registers is shown in Table 3-5. (See also Section , “Receive, receive FIFO, and transmit message buffers are accessible to the host MCU only through the active receive, active transmit, and active receive FIFO buffers.”.) Table 3-5. Mapping between Receive Message Buffer Payload Bytes and GNMVnR Registers GNMVnR Byte NMVectorn GNMV0R MSB NMVector1 LSB NMVector0 MSB NMVector3 LSB NMVector2 GNMV1R … GNMV5R MSB NMVector11 LSB NMVector10 MFR4200 Data Sheet, Rev. 1 96 Freescale Semiconductor Memory Map and Registers 3.2.3.4.7 Symbol Window Status channel A Register (SWSAR) Address 0x86 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved SYMB CH r r r r r r rh rh 7 6 5 4 3 2 1 0 VCE SYNCF NULLF SUPF SERR CERR BVIOL TXCON rh rh rh rh rh rh rh rh Figure 3-60. Symbol Window Status Channel A Register This register holds the symbol window status for channel A. The symbol window status is the same as a regular slot status as described in Section 3.3.3, “Message Buffer Slot Status Vector”, with the addition of the SYMB flag. SYMB — Symbol This flag indicates the reception of a symbol in the symbol window. 0 – No symbol received. 1 – Symbol received. TXCON — TX Conflict This flag indicates transmission conflicts, i.e. indicates that a reception is ongoing when the controller starts transmission. This bit indicates conflicts during transmission in a symbol window. 0 – No transmission conflict detected 1 – Transmission conflict detected Refer to Section 3.3.3, “Message Buffer Slot Status Vector” for a description of the other bits in this register. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 97 MFR4200 FlexRay Communication Controller 3.2.3.4.8 Symbol Window Status Channel B Register (SWSBR) Address 0x88 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved SYMB CH r r r r r r rh rh 7 6 5 4 3 2 1 0 VCE SYNCF NULLF SUPF SERR CERR BVIOL TXCON rh rh rh rh rh rh rh rh Figure 3-61. Symbol Window Status Channel B Register This register holds the symbol window status for channel B. The symbol window status is the same as a regular slot status as described in Section 3.3.3, “Message Buffer Slot Status Vector”, with the addition of the SYMB flag. SYMB — Symbol This flag indicates the reception of a symbol in the symbol window. 0 – No symbol received. 1 – Symbol received. TXCON — TX Conflict This flag indicates transmission conflicts, i.e. indicates that a reception is ongoing when the controller starts transmission. This bit indicates conflicts during transmission in a symbol window. 0 – No transmission conflict detected 1 – Transmission conflict detected Refer to Section 3.3.3, “Message Buffer Slot Status Vector” for a description of the other bits in this register. MFR4200 Data Sheet, Rev. 1 98 Freescale Semiconductor Memory Map and Registers 3.2.3.4.9 Bus Guardian Status Register (BGSR) Address 0x3A Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved BGSME1 BGSME0 BGRR r r r r r rh rh rh Figure 3-62. Bus Guardian Status Register This register holds the bus guardian status. BGRR — Bus Guardian Reset Request Request to the host to reset the bus guardian. 1 – BG reset request. 0 – No BG reset request. BGSME0 – Bus Guardian Schedule Monitoring Error Indication for channel A Indication of a bus guardian schedule monitoring error on channel A. 1 – BGSM error on channel A. 0 – No BGSM error on channel A. BGSME1 — Bus Guardian Schedule Monitoring Error Indication for channel B Indication of a bus guardian schedule monitoring error on channel B. 1 – BGSM error on channel B. 0 – No BGSM error on channel B. NOTE If at least one of the BGSME bits is set, the BGS bit is set in the ISR0 (see Section 3.2.3.6.6, “Interrupt Status Register 0 (ISR0)”), and an interrupt is generated if enabled (see Section 3.2.3.5.5, “Interrupt Enable Register 0 (IER0)”). MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 99 MFR4200 FlexRay Communication Controller 3.2.3.5 3.2.3.5.1 Interrupt and Error Signaling Related Control Registers Startup Interrupt Enable Register (SIER) Address 0x16 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved CDSTPNSIE CDSTPNIE PLFIE CDSTMIE r r r r rw rw rw rw Figure 3-63. Startup Interrupt Enable Register This register holds the interrupt enable flags related to the startup interrupt status register (see Section 3.2.3.6.7, “Startup Interrupt Status Register (SISR)”). The SIER register is cleared during a hard reset. CDSTMIE — Coldstart Max Interrupt Enable 1 – Coldstart max interrupt enabled. 0 – Coldstart max interrupt disabled. PLFIE — Plausibility Failed Interrupt Enable 1 – Plausibility failed interrupt enabled. 0 – Plausibility failed interrupt disabled. CDSTPNIE — Coldstart Path Normal Interrupt Enable 1 – Coldstart path normal interrupt enabled. 0 – Coldstart path normal interrupt disabled. CDSTPNSIE — Coldstart Path Noise Interrupt Enable 1 – Coldstart path noise interrupt enabled. 0 – Coldstart path noise interrupt disabled. CDSTPNSIE — Coldstart Path Noise Interrupt Enable 1 – Coldstart path noise interrupt enabled. 0 – Coldstart path noise interrupt disabled MFR4200 Data Sheet, Rev. 1 100 Freescale Semiconductor Memory Map and Registers 3.2.3.5.2 Maximum Odd Cycles Without Clock Correction Fatal Register (MOCWCFR) FlexRay protocol related parameter – gMaxWithoutClockCorrectionFatal Address 0xCC Reset undefined state 15 14 13 12 11 10 9 8 MCWCF15 MCWCF14 MCWCF14 MCWCF14 MCWCF14 MCWCF14 MCWCF14 MCWCF14 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 MCWCF14 MCWCF14 MCWCF14 MCWCF4 MCWCF3 MCWCF2 MCWCF1 MCWCF0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-64. Maximum Odd Cycles Without Clock Correction Fatal Register This register holds the maximum number of odd communication cycles (double cycles) before a node enters the diagnosis stop state due to missing sync frame pairs (missing rate correction). The register can be written only in the configuration state. If the CCFCV register value equals the MOCWCFR register value, the CC will enter the ‘red’ error state (see Section 3.2.3.6.5, “Error Handling Level Register (EHLR)”), and will signal this to the host by raising an interrupt. According to the protocol specification, the value of this register lies in the range [1:15]; however, the current implementation supports values in the range [1:32767]. 3.2.3.5.3 Maximum Odd Cycles Without clock Correction Passive Register (MOCWCPR) FlexRay protocol related parameter – gMaxWithoutClockCorrectonPassive Address 0xD8 Reset undefined state 15 14 13 12 11 10 9 8 MCWCP15 MCWCP14 MCWCP13 MCWCP12 MCWCP11 MCWCP10 MCWCP9 MCWCP8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 MCWCP7 MCWCP6 MCWCP5 MCWCP4 MCWCP3 MCWCP2 MCWCP1 MCWCP0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-65. Maximum Odd Cycles Without Clock Correction Passive Register This register holds the maximum number of odd communication cycles (double cycles) before a node enters the passive state due to missing sync frame pairs (missing rate correction). The register can be written only in the configuration state. If the CCFCR register value (see Section 3.2.3.6.4, “Clock Correction Failed Counter Register (CCFCR)”) equals the MOCWCPR register value, the CC will enter the ‘yellow’ error state (see Section 3.2.3.6.5, “Error Handling Level Register (EHLR)”), and will signal this to the host by raising an interrupt. According to the protocol specification, MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 101 MFR4200 FlexRay Communication Controller the value of this register lies in the range [1:15]; however, the current implementation supports values in the range [1:32767]. 3.2.3.5.4 Channel Status Error Counter n Register, n = [0:1] (CSECnR) Address 0x2C, 0x2E Reset 0x0 15 14 13 12 11 10 9 8 CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 rh rh rh rh rh rh rh rh Figure 3-66. Channel Status Error Counter n Register, n = [0:1] Channel status error counters CSEC0R and CSEC1R wrap around after they reach the maximum value. These registers are reset when leaving the configuration state. CSEC0R is assigned to channel A of the CC. CSEC1R is assigned to channel B of the CC. The controller generates a slot status vector for: • every static slot • dynamic slots during which the controller receives or transmits a frame • symbol window • network idle time on either channel The controller increments the corresponding channel status error counter once if any slot status error bit (bits 0–3 of the slot status vector) is set. Channel status error counters are independent of other slot status monitoring mechanisms, i.e. message buffers (Section 3.2.3.7, “Message Buffers and FIFO Configuration Related Registers”), slot status registers (Section 3.2.3.6.8, “Slot Status n Register with n = [0:7] (SSnR)”), and slot status counters (Section 3.2.3.5.7, “Slot Status Counter n Register, n = [0:7] (SSCnR)”). • • NOTE To determine the number of errors that occurred during a certain period of time, the host must store intermediate values of the channel status error counters. If a frame exceeds a slot boundary, the controller increments the channel status error counter twice, because a slot boundary violation always affects two slots. MFR4200 Data Sheet, Rev. 1 102 Freescale Semiconductor Memory Map and Registers • 3.2.3.5.5 Refer to Table 3-4 for slot status monitoring availability in different protocol states. Interrupt Enable Register 0 (IER0) Address 0x14 Reset 0x0 15 14 13 12 11 10 9 8 FATALIE CCLRIE MAXSYNCIE EHLCIE MRCEIE SSINTIE BGSIE MOCEIE rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 TIF1IE TIF0IE CYCIE RFOIE RFNEIE CHIERRIE TXIE RXIE rw rw rw rw rw rw rw rw Figure 3-67. Interrupt Enable Register 0 Each bit in the IER0 register enables its corresponding interrupt in the ISR0 register (see Section 3.2.3.6.6, “Interrupt Status Register 0 (ISR0)”). Their meaning is as follows: 0 – The corresponding interrupt is disabled. 1 – The corresponding interrupt enabled. 3.2.3.5.6 Slot Status Selection n Register, n = [0:3] (SSSnR) Address SSS0R=0x6C, SSS1R=0x6E, SSS2R=0x70, SSS3R=0x72 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved ID10 ID9 ID8 r r r r r rw rw rw 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 rw rw rw rw rw rw rw rw Figure 3-68. Slot Status Selection n Register, n = [0:3] This set of n registers selects the static slot IDs for which the status will be provided in the SSnR registers (see Section 3.2.3.6.8, “Slot Status n Register with n = [0:7] (SSnR)”). NOTE SSSnR cannot be used for dynamic slots or minislots. ID[0:10] — Slot Status Slot ID Selection ID[0:10] select the ID of the slot to observe. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 103 MFR4200 FlexRay Communication Controller 3.2.3.5.7 Slot Status Counter n Register, n = [0:7] (SSCnR) Address SSC0R=0x4C, SSC1R=0x4E, SSC2R=0x50, SSC3R=0x52, SSC4R=0x54, SSC5R=0x56, SSC6R=0x58, SSC7R=0x5A Reset 0x0 15 14 13 12 11 10 9 8 CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 rh rh rh rh rh rh rh rh Figure 3-69. Slot Status Counter n Register, n = [0:7] Slot status counters may trigger interrupts via the SSCIR register (see Section 3.2.3.5.9, “Slot Status Counter Incrementation Register (SSCIR)”). These interrupts may be enabled via the SSCIMR register (see Section 3.2.3.5.10, “Slot Status Counter Interrupt Mask Register (SSCIMR)”). Refer to Table 3-4 for slot status monitoring availability in different protocol states. The controller increments the internal slot status counter whenever the slot status provided by the protocol engine fulfills the status condition specified in the corresponding slot status counter condition register SSCCnR. The internal slot status counter is not directly visible to the host. Depending on the value of bit MULTCYC of the corresponding register SSCCnR (see Section 3.2.3.5.8, “Slot Status Counter Condition n Register, n = [0:7] (SSCCnR)”), the controller either clears the internal slot status counter with every cycle start (MULTCYC = 0) or keeps on incrementing continuously (MULTCYC = 1). The host always gets the value of the internal slot status counter for the previous comunication cycle (MULTCYC = 0) or cycles (MULTCYC = 1), when accessing slot status counters SSCnR. Slot status counters do not wraparound. • • • NOTE 1 To clear slot status counter SSCnR, the host must reset bit MULTCYC in the corresponding slot status counter condition register SSCCnR. The controller will then reset the internal slot status counter at the beginning of the following cycle, and the host will get the accumulated value of the internal slot status counter at the end of the following cycle. The controller clears all internal slot status counters when leaving the configuration state. The controller clears an internal slot status counter at the beginning of every cycle, if bit MULTCYC is 0 in the corresponding slot status counter condition register. NOTE 2 The controller provides four independent slot status monitoring mechanisms: MFR4200 Data Sheet, Rev. 1 104 Freescale Semiconductor Memory Map and Registers • • • • • 3.2.3.5.8 Slot status registers SSnR configured via slot status selection registers SSSnR, as described in Section 3.2.3.6.8, “Slot Status n Register with n = [0:7] (SSnR)” and Section 3.2.3.5.6, “Slot Status Selection n Register, n = [0:3] (SSSnR)”. Channel status error counters CSEC0R and CSEC1R, as described in Section 3.2.3.5.4, “Channel Status Error Counter n Register, n = [0:1] (CSECnR)”. Slot status information within message buffers, as described in Section 3.3.3, “Message Buffer Slot Status Vector”. Slot status counter registers SSCnR configured via slot status counter condition registers SSCCnR as described in Section 3.2.3.5.7, “Slot Status Counter n Register, n = [0:7] (SSCnR)” and Section 3.2.3.5.8, “Slot Status Counter Condition n Register, n = [0:7] (SSCCnR)”. Refer to Table 3-4 for slot status monitoring availability in different protocol states. Slot Status Counter Condition n Register, n = [0:7] (SSCCnR) Address SSCC0R=0x5C, SSCC1R=0x5E, SSCC2R=0x60, SSCC3R=0x62, SSCC4R=0x64, SSCC5R=0x66, SSCC6R=0x68, SSCC7R=0x6A Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved CHCFG1 CHCFG0 MULTCYC r r r r r rw rw rw 7 6 5 4 3 2 1 0 VCES SYNCFS NULLFS SUPFS SSCM3 SSCM2 SSCM1 SSCM0 rw rw rw rw rw rw rw rw Figure 3-70. Slot Status Counter Condition n Register, n = [0:7] Each of these registers serves as condition to detect if the corresponding slot status counter (see Section 3.2.3.5.7, “Slot Status Counter n Register, n = [0:7] (SSCnR)”) is to be incremented. SSCMx, x = [0:3] — Slot Status Mask A binary AND operation is performed on this 4-bit vector and the status of each slot-channel tuple that is not booked for transmission in the static part of the communication cycle. If the result is 0, and conditions for null frame selection (NULLS), sync frame selection (SYNCS), startup frame selection (SUPFS), and valid communication element selection (VCES) are not met, the counter will not be incremented for that slot-channel tuple. NULLFS — NULL Frame Selection This register is used to restrict counting to received null frames only. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 105 MFR4200 FlexRay Communication Controller 0 – The slot status counter is incremented independently of the null frame indication bit. 1 – The slot status counter is incremented only when a syntactically correct null frame is received. SYNCFS — SYNC Frame Selection This register can be used to restrict counting to received sync frames only. 0 – The slot status counter can be incremented independently of the sync frame bit. 1 – The slot status counter can be incremented only when a syntactically correct sync frame is received. SUPFS — StartUP Frame Selection This register can be used to restrict counting to received startup frames only. 0 – The slot status counter can be incremented independently of the startup bit. 1 – The slot status counter can be incremented only when a syntactically correct startup frame is received. VCES — Valid Communication Element Selection This register can be used to restrict counting to semantically valid frames only. 0 – The slot status counter can be incremented for semantically valid and invalid frames. 1 – The slot status counter can be incremented only when a semantically valid frame is received. MULTCYC — Multiple Cycle This bit determines if the slot status counter reflects the values of multiple communication cycles or of the previous communication cycle only. Note that MULTCYC may be written during normal operation, but its value must not be modified by the host during the NIT. 0 – The internal slot status counter starts at 0 at the beginning of every communication cycle, and SSCnR reflects the values of the previous communication cycle. 1 – The internal slot status counter is not reset to 0 at the beginning of every communication cycle; this allows counting of specific slot status conditions over several communication cycles. SSCnR reflects the accumulated values counted in previous communication cycles. CHCFG1, CHCFG0 — Channel Configuration These bits determine the channel assignment for slot status counters SSCnR, as defined in Table 3-6. Table 3-6. Channel Configuration for SSCCnR CHCFG1 CHCFG0 Meaning 0 0 Count for channel A 0 1 Count for channel B MFR4200 Data Sheet, Rev. 1 106 Freescale Semiconductor Memory Map and Registers Table 3-6. Channel Configuration for SSCCnR CHCFG1 CHCFG0 Meaning 1 0 Count for both channels only once even if the counting condition is fulfilled for both channels 1 1 Count for both channels independently. If the counting condition is fulfilled for both channels, count twice. NOTE Slot status counting is supported for the static segment only. 3.2.3.5.9 Slot Status Counter Incrementation Register (SSCIR) Address 0x28 Reset 0x0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 SSCIR7 SSCIR6 SSCIR5 SSCIR4 SSCIR3 SSCIR2 SSCIR1 SSCIR0 rwh rwh rwh rwh rwh rwh rwh rwh Figure 3-71. Slot Status Counter Incrementation Register This register contains one bit, SSCIRn, for each slot status counter SSCnR (see Section 3.2.3.5.7, “Slot Status Counter n Register, n = [0:7] (SSCnR)”). Bit SSCIRn is set when the slot status counter SSCnR is incremented. The register is reset on leaving the configuration state. The host may clear individually each bit in register SSCIR by writing a ‘1’ to it. 3.2.3.5.10 Slot Status Counter Interrupt Mask Register (SSCIMR) Address 0x2A Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 SSCIMR7 SSCIMR6 SSCIMR5 SSCIMR4 SSCIMR3 SSCIMR2 SSCIMR1 SSCIMR0 rw rw rw rw rw rw rw rw Figure 3-72. Slot Status Counter Interrupt Mask Register MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 107 MFR4200 FlexRay Communication Controller Via this register, the host may enable individually each bit in the SSCIR (see Section 3.2.3.5.9, “Slot Status Counter Incrementation Register (SSCIR)”) to trigger the interrupt SSINT in the ISR0 (see Section 3.2.3.6.6, “Interrupt Status Register 0 (ISR0)”. 1 – If the corresponding bit in register SSCIR is set, trigger the interrupt SSINT. 0 – Ignore the corresponding bit in register SSCIR; do not trigger an interrupt. 3.2.3.6 3.2.3.6.1 Interrupt and Error Signaling Related Status Registers Receive Buffer Interrupt Vector Register (RBIVECR) Address 0x24 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved RBIVEC5 RBIVEC4 RBIVEC3 RBIVEC2 RBIVEC1 RBIVEC0 r r rh rh rh rh rh rh Figure 3-73. Receive Buffer Interrupt Vector Register This register indicates the lowest numbered receive message buffer that has its interrupt status flag (IFLG) and its interrupt enable (IENA) bits set. The register is cleared by a hard reset or by leaving the configuration state. • • • NOTE After an IFLG has been set or cleared, the CC updates the RBIVECR register after 1 µT. The RBIVECR register contains valid data only if the RXIF bit is set (see Section 3.2.3.6.6, “Interrupt Status Register 0 (ISR0)”). If there are no IFLG bits set for any receive message buffers that have their IENA bit set, then the CC sets the RBIVECR register to 0x0000 (IFLG, IENA — see Section 3.2.3.7.2, “Message Buffer Control, Configuration and Status n Register, n = [0:58] (BUFCSnR)”). MFR4200 Data Sheet, Rev. 1 108 Freescale Semiconductor Memory Map and Registers 3.2.3.6.2 Transmit Buffer Interrupt Vector Register (TBIVECR) Address 0x26 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved TBIVEC5 TBIVEC4 TBIVEC3 TBIVEC2 TBIVEC1 TBIVEC0 r r rh rh rh rh rh rh Figure 3-74. Transmit Buffer Interrupt Vector Register This register indicates the lowest numbered transmit message buffer that has its interrupt status flag (IFLG) and its interrupt enable (IENA) bits set. A hard reset or leaving the configuration state clear the register. • • • 3.2.3.6.3 NOTE After an IFLG has been set or cleared, the CC updates the TBIVECR register after 1 µT. The TBIVECR register contains valid data only if the TXIF bit is set (see Section 3.2.3.6.6, “Interrupt Status Register 0 (ISR0)”). If there are no IFLG bits set for any transmit message buffers that have their IENA bit set, then the CC sets the TBIVECR register to 0x0000 (IFLG, IENA — see Section 3.2.3.7.2, “Message Buffer Control, Configuration and Status n Register, n = [0:58] (BUFCSnR)”). CHI Error Register (CHIER) Address 0x12 Reset 0x0 15 14 13 12 11 10 9 8 ILLADR NMENF NMEFTS SPLME MDPLE BULE EFLE FBLE rwh rwh rwh rwh rwh rwh rwh rwh 7 6 5 4 3 2 1 0 TBLE RBLE Reserved CCPBLE BB Reserved IRE FLE rwh rwh r rwh rwh r rwh rwh Figure 3-75. CHI Error Register This register holds CHI status flags. The host clears any status bit in the CHIER by writing a '1' to it; writing a ‘0’ does not change the bit state. The CC sets a status bit in the CHIER again, when it detects the condition for that bit. If the host and the CC try to write the CHIER register at the same time, the CC write MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 109 MFR4200 FlexRay Communication Controller operation has the higher priority. If the host tries to clear a set error flag in the CHIER register, while the CC at the same time sets this bit, the error flag will remain set. A hard reset clears the register. NOTE When any error is processed by the CC, and indicated in the CHIER register, the CC raises an interrupt, if configured to do so by means of the ISR0 and IER0 bits, and continues operation without changing state. FLE — Frame Lost Error This error occurs if the host has locked a receive message buffer, and two semantically valid frames for that buffer are received during this locked time. The first frame will be lost. 1 – Frame lost error detected. 0 – No frame lost error detected. IRE — Illegal Reconfiguration Error This error appears if the host tries to reconfigure a dynamic transmit message buffer to a static one. The reconfiguration, in that case, is ignored by the CC. 1 – Illegal reconfiguration error detected. 0 – No illegal reconfiguration error detected. BB — Buffer Busy This bit is set if the host tries to lock a message buffer that is locked by the CC for internal operations. The CC, in that case, does not grant access to the message buffer through the locking mechanism. 1 – Buffer busy detected. 0 – No buffer busy detected. Buffer Locking Errors: CCPBLE — CC Part Buffer of a Double Transmit Message Buffer Lock Error This error is raised if the host tries to lock a CC part buffer of a double transmit message buffer. The CC, in that case, does not grant access to the CC part buffer of a double transmit message buffer through the locking mechanism. 1 – CCPBLE detected. 0 – No CCPBLE detected. RBLE — Receive Message Buffers Locking Error This error appears if the host tries to lock more than 1 receive message buffer. The CC in that case does not grant access to the buffer through the locking mechanism. 1 – RBLE detected. MFR4200 Data Sheet, Rev. 1 110 Freescale Semiconductor Memory Map and Registers 0 – No RBLE detected. TBLE — Transmit Message Buffers Locking Error This error appears if the host tries to lock more than one transmit message buffer. The CC, in that case, does not grant access to the buffer through the locking mechanism. 1 – TBLE detected. 0 – No TBLE detected. FBLE — FIFO Message Buffer Lock Error This error appears if the host tries to lock a FIFO message buffer not through message buffer 0. The CC, in that case, does not grant access to the message buffer through the locking mechanism. 1 – FBLE detected. 0 – No FBLE detected. EFLE — Empty FIFO Lock Error This error appears if the host tries to lock an empty FIFO. The CC, in that case, does not grant access to the FIFO through the locking mechanism. 1 – EFLE detected. 0 – No EFLE detected. BULE — Unlocked Message Buffer Lock Error This error appears if the host tries to access an unlocked message buffer through any active message buffer. In that case, the host write operations to an active message buffer are ignored, and read operations return 0’s. 1 – BULE detected. 0 – No BULE detected. Other Error Indicators: MDPLE — Maximum Dynamic Payload Length Exceeded Error This error appears if the payload length written into a dynamic segment transmit message buffer PayloadLength field is greater than the maximum payload length dynamic configured in the maximum payload length dynamic register MPLDR (see Section 3.2.3.3.16, “Maximum Payload Length Dynamic Register (MPLDR)”). In that case, the wrong payload length is ignored. 1 – MDPLE detected. 0 – No MDPLE detected. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 111 MFR4200 FlexRay Communication Controller SPLME — Static Payload Length Mismatch Error This error appears if the payload length written into a static segment transmit message buffer is not equal to the static payload length configured within the static payload length register SPLR (see Section 3.2.3.3.11, “Static Payload Length Register (SPLR)”). In that case, the wrong payload length is ignored. 1 – SPLME detected. 0 – No SPLME detected. NMEFTS — Network Management Error Frame Too Short This error appears if the payload length value of a received message is not big enough to hold the complete configured NM vector. However, the received part of the NM vector is used for the NM vector update (see Section 3.2.3.4.6, “Global Network Management Vector n Register, n = [0:5] (GNMVnR)”). 1 – NMEFTS detected. 0 – No NMEFTS detected. NMENF — Network Management Error Null Frame This error appears if a received message with an NM bit set has a null frame bit set. In that case, the GNMVnR registers are not updated. 1 – NMENF detected. 0 – No NMENF detected. ILLADR — Illegal Address This error appears if the host tries to perform a byte access (a write access, if the HCS12 interface is selected) or an unaligned word access. If the HCS12 interface is selected (see chapter Section 3.7, “Host Controller Interfaces”), and this error appears, the CC presents the data value 0x0000 to the host and indicates an IILADR error. NOTE The address space from 0x0400 to 0x1FFF in the MFR4200 memory map is reserved. Reading this address space results in data 0x0000, while writing does not change the memory. Reading or writing this address space will set the ILLADR bit. 1 – ILLADR detected. 0 – No ILLADR detected. MFR4200 Data Sheet, Rev. 1 112 Freescale Semiconductor Memory Map and Registers 3.2.3.6.4 Clock Correction Failed Counter Register (CCFCR) FlexRay Protocol Related Parameter – vClockCorrectionFailed Address 0x326 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved OWCC3 OWCC2 OWCC1 OWCC0 r r r r rh rh rh rh Figure 3-76. Clock Correction Failed Counter Register This register holds the clock correction failed counter. This counter is reset when a node enters normal active operation. It is incremented by one at the end of any odd communication cycle, when either the missing offset correction error or the missing rate correction error, or both, are active. The counter is reset to zero at the end of an odd communication cycle if neither the offset correction failed error nor the rate correction failed error is active. The counter is not incremented after it reaches the maximum odd communication cycles without clock correction programmed value (see Section 3.2.3.5.2, “Maximum Odd Cycles Without Clock Correction Fatal Register (MOCWCFR)”). The host has read-only access to this register. 3.2.3.6.5 Error Handling Level Register (EHLR) Address 0x328 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved EHL1 EHL0 r r r r r r rh rh Figure 3-77. Error Handling Level Register This register holds the current value of the error handling level. Error handling levels are defined in Table 3-7: MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 113 MFR4200 FlexRay Communication Controller Table 3-7. Error Handling Level Coding 3.2.3.6.6 EHL1 EHL0 Error Handling Level CC state 0 0 Green level Normal Active 0 1 Yellow level Normal Passive 1 0 Red level Diagnosis Stop 1 1 Not used – Interrupt Status Register 0 (ISR0) Address 0x0E Reset 0x0 15 14 13 12 11 10 9 8 FATAL CCLR MAXSYNC EHLC MRCE SSINT BGS MOCE rwh rwh rwh rwh rwh rwh rwh rwh 7 6 5 4 3 2 1 0 TIF1 TIF0 CYCIF RFOIF RFNEIF CHIERRIF TXIF RXIF rwh rwh rwh rwh rwh rwh rwh rwh Figure 3-78. Interrupt Status Register 0 This register indicates the occurrence of interrupt events. Together with IER0 (see Section 3.2.3.5.5, “Interrupt Enable Register 0 (IER0)”), it allows the module to operate in a polled or interrupt driven system. • • • • NOTE The host clears any status bit in the ISR0 by writing a '1' to the bit. Writing a ‘0’ does not change the bit state. The CC sets a status bit of the ISR0 again when it detects the condition for that bit. The host must resolve the conditions causing the RFNEIF, CHIERRIF, TXIF, and RXIF bits to be asserted, as these flags are updated automatically by the CC, depending on conditions related to these flags. If the host does not resolve the conditions that lead to these flags being asserted, the CC ignores the host’s clear operation for these bits and the bits remain asserted. If the host and the CC try to write the ISR0 register at the same time, the CC operation has the higher priority. Every flag has an associated interrupt enable flag in interrupt enable register 0. The ISR0 register is cleared by a hard reset or by leaving the configuration state. MFR4200 Data Sheet, Rev. 1 114 Freescale Semiconductor Memory Map and Registers RXIF — Receive Interrupt Flag This bit is set when any of the enabled (IENAn = 1) receive message buffers or the receive FIFO has successfully received a frame. Sources of this interrupt are set IFLG bits (see Section 3.4.1, “Message Buffer Control, Configuration and Status Register”) of the corresponding message buffers. If RXIE is set (see Section 3.2.3.5.5, “Interrupt Enable Register 0 (IER0)”), a receive interrupt remains pending while the RXIF flag is set. 1 – At least one receive message buffer is full. 0 – All receive message buffers are empty. TXIF — Transmit Interrupt Flag This read-only bit is set when any of the enabled (IENAn = 1) transmit message buffers is empty (IFLG = 1). Sources of this interrupt are set IFLG bits (see Section 3.4.1, “Message Buffer Control, Configuration and Status Register”) of the corresponding message buffers. If TXIE is set (see Section 3.2.3.5.5, “Interrupt Enable Register 0 (IER0)”), an interrupt remains pending while this flag is set. 1 – At least one transmit message buffer is empty. 0 – All transmit message buffers are full. CHIERRIF — CHI Error Interrupt Flag This bit is set when a CHI error is detected. Sources of this interrupt are CHI errors in the CHIER register (see Section 3.2.3.6.3, “CHI Error Register (CHIER)”). If CHIERRIF is set, an interrupt remains pending while this flag is set. 1 – A CHI error was detected. 0 – No CHI error was detected. RFNEIF — Receive FIFO Not Empty Interrupt Flag This bit is set when the receive FIFO is not empty. If enabled, a FIFO not empty interrupt remains pending while this flag is set. The flag will be cleared if the FIFO is empty and message buffer 0 is unlocked. The CC sets this flag when the FIFO is not empty. 1 – Receive FIFO is not empty. 0 – Receive FIFO is empty. RFOIF — Receive FIFO Overrun Interrupt Flag This bit is set when a receive FIFO overrun occurs. If enabled, an interrupt remains pending while this flag is set. 1 – A receive FIFO overrun has been detected. 0 – No receive FIFO overrun has occurred. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 115 MFR4200 FlexRay Communication Controller CYCIF — Cycle Start Interrupt Flag This bit is set when a communication cycle starts. If enabled, an interrupt remains pending while this flag is set. 1 – A communication cycle started. 0 – No communication cycle started. TIF0/TIF1 — Timer Interrupt Flag 0/1 This bit is set when: • the result of the timer 0/1 interrupt calculation, based on the cycle base and repetition fields of the timer interrupt configuration register 0 (see Section 3.2.3.9.1, “Timer Interrupt Configuration Register 0 Cycle Set (TICR0CS)”), matches the current cycle counter value in the CCCV register (see Section 3.2.3.4.2, “Current Cycle Counter Value Register (CCCVR)”); • and the macrotick offset programmed in the timer interrupt configuration register 0 (see Section 3.2.3.9.1, “Timer Interrupt Configuration Register 0 Cycle Set (TICR0CS)”) matches the current macrotick value from CMCVR (see Section 3.2.3.4.3, “Current Macrotick Counter Value Register (CMCVR)”). If enabled, an interrupt remains pending while this flag is set. 1 – Timer 0/1 has reached the limit. 0 – Timer 0/1 has not reached the limit. NOTE After a hard reset, timer interrupt configuration registers are cleared. The CC indicates timers interrupts (ISR0 = 0x00C0) immediately after the hard reset, as the protocol engine provides cycle time and cycle counter values equal to zero during the whole configuration state. No interrupt is indicated to the host, as the interrupt enable register IER0 is also 0 after a hard reset. MOCE — Missing Offset Correction error This bit is set if an insufficient number of measurements is available for offset correction at the end of the communication cycle (even and odd). 1 – Insufficient number of measurements available for offset correction. 0 – Sufficient number of measurements available for offset correction BGS — Bus Guardian Status This bit indicates bus guardian schedule monitoring errors on channel A and/or channel B. The host may read the bus guardian status register BGSR (see Section 3.2.3.4.9, “Bus Guardian Status Register (BGSR)”) to determine on which channel the error occurred. The host may reset BGS by writing a ‘1’. 1 – Bus guardian schedule monitoring error. 0 – No bus guardian schedule monitoring error MFR4200 Data Sheet, Rev. 1 116 Freescale Semiconductor Memory Map and Registers SSINT — Slot Status Interrupt This bit indicates that at least one slot status counter register SSCnR (see Section 3.2.3.5.7, “Slot Status Counter n Register, n = [0:7] (SSCnR)”) that is enabled as an interrupt source via slot status counter interrupt mask register SSCIMR (see Section 3.2.3.5.10, “Slot Status Counter Interrupt Mask Register (SSCIMR)”) has been incremented. 1 – At least one slot status counter that is enabled as an interrupt source has been incremented. 0 – No slot status counter that is enabled as an interrupt source has been incremented. MRCE — Missing Rate Correction error This bit is set if an insufficient number of measurement pairs is available for rate correction at the end of the odd communication cycle. 1 – Insufficient number of measurement pairs available for rate correction 0 – Sufficient number of measurement pairs available for rate correction EHLC — Error Handling Level Changed/ Startup Interrupt detected This signal indicates, to the host, changes to the error handling level. 1 – Error handling level has changed. 0 – Error handling level has not changed. MAXSYNC — Max Sync Frames Detected The controller sets this bit when more than the configured maximum number of sync frames (see Section 3.2.3.3.5, “Maximum Sync Frames Register (MSFR)”) are detected within a single cycle. In this case, the controller is not able to capture all time difference measurements. 1 – More than the configured maximum number of sync frames have been received. 0 – Not more than the configured maximum number of sync frames have been received. CCLR — Clock Correction Limit Reached This bit is set if offset or rate calculation reaches the threshold as configured in registers MOCR and MRCR (see Section 3.2.3.3.24, “Maximum Offset Correction Register (MOCR)” and Section 3.2.3.3.25, “Maximum Rate Correction Register (MRCR)”). 1 – Offset or rate calculation has reached the limit. 0 – Offset and rate correction are within the limit. FATAL — Fatal Error This bit is set if an illegal condition is detected in the protocol state machine; this can be caused by illegal configuration. In this as, the controller goes into the diagnosis stop state immediately. 1 – Fatal error detected. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 117 MFR4200 FlexRay Communication Controller 0 – No fatal error detected. 3.2.3.6.7 Startup Interrupt Status Register (SISR) Address 0x10 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved CDSTPNSIF CDSTPNIF PLFIF CDSTMIF r r r r rwh rwh rwh rwh Figure 3-79. Startup Interrupt Status Register This register holds the interrupt flags related to the startup procedure. All flags are read/write for the host. Each flag has an associated interrupt enable flag in the startup interrupt enable register (see Section 3.2.3.5.1, “Startup Interrupt Enable Register (SIER)”). The SISR register is cleared during a hard reset or when leaving the configuration state. The host clears a status bit in the SISR by writing a '1' to it. Writing a ‘0’ does not change the bit state. The CC sets a status bit in the SISR again when it detects the condition for that bit. If the host and the CC try to access the SISR register at the same time, the CC operation has the higher priority. CDSTMIF — Coldstart Max Interrupt Flag This error signal is set if the maximum number of allowed retries of a coldstarting CC (CSMR programmed value – see Section 3.2.3.3.26, “Coldstart Maximum Register (CSMR)”) is reached. That is, if the CSMR register is programmed with the value N, the CC sets the CDSTMIF bit after the Nth retry has failed. If enabled, an interrupt remains pending while this flag is set. 1 – Coldstart Maximum value has been reached. 0 – Coldstart Maximum value has not been reached. PLFIF — Plausibility Failed Interrupt Flag This error signal is set if the consistency check of the local CC within the startup sequence failed, i.e. the number of received valid startup frames is less than required. If enabled, an interrupt remains pending while this flag is set. 1 – A Plausibility Check of the local CC within the startup sequence failed. 0 – A Plausibility Check of the local CC within the startup sequence did not fail. MFR4200 Data Sheet, Rev. 1 118 Freescale Semiconductor Memory Map and Registers CDSTPNSIF — Coldstart Path Noise Interrupt Flag This signal is set if the CC has entered startup via the coldstart noise path. This indicates that the CC tried to start the network. If enabled, an interrupt remains pending while this flag is set. 1 – The startup has been entered via the coldstart noise path. 0 – The startup has not been entered via the coldstart noise path. CDSTPNIF — Coldstart Path Normal Interrupt Flag This signal is set if the CC has entered the startup via the normal coldstart path. This indicates that the CC tried to start the network. If enabled, an interrupt is pending while this flag is set. 1 – Startup has been entered via the normal coldstart path. 0 – Startup has not been entered via the normal coldstart path. 3.2.3.6.8 Slot Status n Register with n = [0:7] (SSnR) Address SS0R=0x74, SS1R=0x76, SS2R=0x78, SS3R=0x7A, SS4R=0x7C, SS5R=0x7E, SS6R=0x80, SS7R=0x82 Reset 0x0 15 14 13 12 11 10 9 8 VCE_B SYNCF_B NULLF_B SUPF_B SERR_B CERR_B BVIOL_B TXCON_B rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 VCE_A SYNCF_A NULLF_A SUPF_A SERR_A CERR_A BVIOL_A TXCON_A rh rh rh rh rh rh rh rh Figure 3-80. Slot Status n Register, n = [0:7] Each of these registers holds the status of the slot specified in the corresponding slot status selection register SSSnR for both channel A and channel B. The suffices “_A” and “_B” indicate whether the slot status is valid for channel A or channel B, respectively. For a detailed description of the slot status flags, refer to Section 3.3.3, “Message Buffer Slot Status Vector”. The controller provides a pair of slot status registers for each monitored slot with the first register being assigned to even communication cycles, and the second to odd communication cycles, as shown in Table 3-8. The controller clears the slot status registers SSnR (see Section 3.2.3.6.8, “Slot Status n Register with n = [0:7] (SSnR)”) when leaving the configuration state. • • NOTE Refer to Table 3-4 for slot status monitoring availability in different protocol states. The slot status of slot n is updated within the first macrotick of slot n+1. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 119 MFR4200 FlexRay Communication Controller • Empty slots exhibit the slot status 0x00 for both channels, because the slot status registers SSnR do not include the slot status channel bit. Table 3-8. Mapping between SSSnR and SSnR Even communication cycle Slot Status Selection Register 3.2.3.6.9 Odd communication cycle Channel A (low byte) Channel B (high byte) Channel A (low byte) Channel B (high byte) SSS0R SS0R SS0R SS1R SS1R SSS1R SS2R SS2R SS3R SS3R SSS2R SS4R SS4R SS5R SS5R SSS3R SS6R SS6R SS7R SS7R Odd Sync Frame ID n Register, n = [0:15] (OSFIDnR) Address OSFID0R=0x3E0 … OSFID15R=0x3FE Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved ID10 ID9 ID8 r r r r r rh rh rh 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 rh rh rh rh rh rh rh rh Figure 3-81. Odd Sync Frame ID n Register, n = [0:15] These registers hold the frame IDs of all sync frames received in odd communication cycles and used for clock synchronization. The CC does not change the odd ID values from the end of the static part in the odd cycle to the beginning of the NIT in the even communication cycle. NOTE If a CC is configured to send sync frames (see Section 3.2.3.3.29, “Sync Frame Register (SYNCFR)”), the CC will store its sync frame ID in register OSFID0R. MFR4200 Data Sheet, Rev. 1 120 Freescale Semiconductor Memory Map and Registers 3.2.3.6.10 Even Sync Frame ID n Register, n = [0:15] (ESFIDnR) Address EID0R=0x380 … EID15R=0x39E Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved ID10 ID9 ID8 r r r r r rh rh rh 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 rh rh rh rh rh rh rh rh Figure 3-82. Even Sync Frame ID n Register, n = [0:15] These registers hold the slot IDs of all sync frames received in even communication cycles and used for clock synchronization. The CC does not change the even ID values from the end of the static part in the even cycle to the beginning of the NIT in the odd communication cycle. NOTE If a CC is configured to send sync frames (see Section 3.2.3.3.29, “Sync Frame Register (SYNCFR)), each time the CC clears the EMCR or OMCR, it: • • • initializes the ESFID0R (or OSFID0R) with its sync frame ID, increments EMCR or OMCR, initializes EMA0R and EMB0R or OMA0R and EMB0R with the following value: NMLR * SSAPOR – TSSLR * BDR – max(DCAR,DCBR) – 4 3.2.3.6.11 Eqn. 3-10 Odd Measurement Channel A n Register, n = [0:15] (OMAnR) Address OMA0R=0x3A0 … OMA15R=0x3BE Reset undefined state 15 14 13 12 11 10 9 8 OMA15 OMA14 OMA13 OMA12 OMA11 OMA10 OMA9 OMA8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 OMA7 OMA6 OMA5 OMA4 OMA3 OMA2 OMA1 OMA0 rh rh rh rh rh rh rh rh Figure 3-83. Odd Measurement Channel A n Register, n = [0:15] MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 121 MFR4200 FlexRay Communication Controller These registers hold the sync frame arrival time measured in microticks relative to the slot start boundary. Registers OMA0R to OMA15R contain all measurement values from channel A for the odd communication cycle. 3.2.3.6.12 Odd Measurement Channel B n Register, n = 0:15] (OMBnR) Address OMB0R=0x3C0 … OMB15R=0x3DE Reset undefined state 15 14 13 12 11 10 9 8 OMB15 OMB14 OMB13 OMB12 OMB11 OMB10 OMB9 OMB8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 OMB7 OMB6 OMB5 OMB4 OMB3 OMB2 OMB1 OMB0 rh rh rh rh rh rh rh rh Figure 3-84. Odd Measurement Channel B n Register, n = [0:15] These registers hold the sync frame arrival time measured in microticks relative to the slot start boundary. Registers OMB0R to OMB15R contain all measurement values from channel B for the odd communication cycle. 3.2.3.6.13 Even Measurement Channel A n Register, n = [0:15] (EMAnR) Address EMA0R=0x340 … EMA15R=0x35E Reset undefined state 15 14 13 12 11 10 9 8 EMA15 EMA14 EMA13 EMA12 EMA11 EMA10 EMA9 EMA8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 EMA7 EMA6 EMA5 EMA4 EMA3 EMA2 EMA1 EMA0 rh rh rh rh rh rh rh rh Figure 3-85. Even Measurement Channel A n Register, n = [0:15] These registers hold the sync frame arrival time measured in microticks relative to the slot start boundary. Registers EMA[0:15]R contain all measurement values from channel A for the even communication cycle. MFR4200 Data Sheet, Rev. 1 122 Freescale Semiconductor Memory Map and Registers 3.2.3.6.14 Even Measurement Channel B n Register, n = [0:15] (EMBnR) Address EMB0R=0x360 … EMB15R=0x37E Reset undefined state 15 14 13 12 11 10 9 8 EMB15 EMB14 EMB13 EMB12 EMB11 EMB10 EMB9 EMB8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 EMB7 EMB6 EMB5 EMB4 EMB3 EMB2 EMB1 EMB0 rh rh rh rh rh rh rh rh Figure 3-86. Even Measurement Channel B n Register, n = [0:15] These registers hold the sync frame arrival time measured in microticks relative to the slot start boundary. Registers EMB[0:15]R contain all measurement values from channel B for the even communication cycle. NOTE To get the time difference based on the expected time reference point, one must subtract the nominal action point offset in microticks, the frame start sequence length and the delay compensation according to the formula below: Time difference = (EMAnR, EMBnR, OMAnR, or OMBnR) – NMLR * SSAPOR – TSSLR * BDR – max(DCAR,DCBR) – 4 Eqn. 3-11 As the transmission start sequence length is given in bits, it must be converted to µT by multiplying it by the bit duration. As the channel information is not available for the list of sync frame arrival times, the CC standardizes the values based on the channel with the larger delay compensation value; thereby, the frame arrival time is always positive. A sync frame arrival time of 0 in one of the measurement registers denotes an invalid time difference. For example, if, in a given slot, only a sync frame on channel A has been received, the corresponding EMBnR will hold the value 0. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 123 MFR4200 FlexRay Communication Controller 3.2.3.6.15 Even Measurement Counter Register (EMCR) Address 0x33C Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved EMC3 EMC2 EMC1 EMC0 r r r r rh rh rh rh Figure 3-87. Even Measurement Counter Register The EMCR and OMCR are described in the following section. 3.2.3.6.16 Odd Measurement Counter Register (OMCR) Address 0x33E Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved OMC3 OMC2 OMC1 OMC0 r r r r rh rh rh rh Figure 3-88. Odd Measurement Counter Register The EMCR and OMCR hold the number of valid sync frames received during the static segment of an even or odd cycle, respectively. If sync frame filtering is enabled, only sync frames that have passed the sync frame rejection and/or acceptance filters (see Section 3.2.3.8.3, “Sync Frame Rejection Filter Register (SYNFRFR)” and Section 3.2.3.8.1, “Sync Frame Acceptance Filter Value Register (SYNFAFVR)”) are considered. The EMCR and OMCR registers hold the number of valid measurements in the measurement tables (see Section 3.2.3.6.9, “Odd Sync Frame ID n Register, n = [0:15] (OSFIDnR)” and Section 3.2.3.6.11, “Odd Measurement Channel A n Register, n = [0:15] (OMAnR)”). For example, if the value of EMCR is two, then two valid sync frames are available for clock sync calculations; the remaining fourteen values in the measurement table for the even cycle are invalid and may have undefined content. The EMCR and OMCR counters are incremented each time, when a valid sync frame has been received on at least one of the channels. EMCR and OMCR are reset when the CC enters the initialize schedule and coldstart collision resolution states. In the normal active state and the normal passive state, EMCR is reset in the NIT of the odd cycle, and OMCR is reset at the end of the even cycle. If the node is a non sync node, EMCR and OMCR are MFR4200 Data Sheet, Rev. 1 124 Freescale Semiconductor Memory Map and Registers reset to zero. If the node is a sync node, EMCR and OMCR are reset to 1, as a sync node considers its own sync frames as zero values in the measurement tables. 3.2.3.7 3.2.3.7.1 Message Buffers and FIFO Configuration Related Registers FIFO Size Register (FSIZR) Address 0x18 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved FSIZ5 FSIZ4 FSIZ3 FSIZ2 FSIZ1 FSIZ0 r r rw* rw* rw* rw* rw* rw* Figure 3-89. FIFO Size Register This register is used to configure the FIFO. The number of message buffers assigned to the receive FIFO, starting from message buffer 0, can be selected. Writing the FSIZR register is possible only during the configuration state. Table 3-9. FIFO Size FSIZ[5:0] FIFO Size 000000 No FIFO is defined 000001 only message buffer 0 000010 message buffer 0…message buffer 1 000011 message buffer 0…message buffer 2 … … 111001 message buffer 0…message buffer 56 111010 message buffer 0…message buffer 57 others message buffer 0…message buffer 58 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 125 MFR4200 FlexRay Communication Controller 3.2.3.7.2 Message Buffer Control, Configuration and Status n Register, n = [0:58] (BUFCSnR) Address BUFCS0R=0x200, BUFCS1R=0x204, …, BUFCS57R=0x2E4, BUFCS58R=0x2E8. BUFCSnR=0x200 + 0x4*dec2hex(n) Reset IFLG, IENA, CFG and VALID bits are reset to 0, others – in undefined state 15 14 13 12 11 10 9 8 VALID TT CCFE BT DATUPD CHB CHA BUFCMT * * * * * * * * 7 6 5 4 3 2 1 0 Reserved LOCK Reserved Reserved IENA IFLG Reserved CFG r * r r * * r * Figure 3-90. Message Buffer Control, Configuration and Status n Register, n = [0:58] For a description of these registers and the bit access scheme, see Section 3.4.1, “Message Buffer Control, Configuration and Status Register”. 3.2.3.7.3 Active Transmit Buffer Frame ID Register (ATBFRID) Address 0x180 Reset undefined state 15 14 13 12 11 10 9 8 R* PP NFI SYNC STARTUP ID10 ID9 ID8 rw rw* r r r rw* rw* rw* 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-91. Active Transmit Buffer Frame ID Register For a description of this register and the bit access scheme, refer to Section 3.5, “Message Buffer Handling and Operations”. MFR4200 Data Sheet, Rev. 1 126 Freescale Semiconductor Memory Map and Registers 3.2.3.7.4 Active Transmit Buffer Cycle Counter and Payload Length Register (ATBCCPLR) Address 0x182 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved CYCL_CNT5 CYCL_CNT4 CYCL_CNT3 CYCL_CNT2 CYCL_CNT1 CYCL_CNT0 r r r* r* r* r* r* r* 7 6 5 4 3 2 1 0 Reserved LEN6 LEN5 LEN4 LEN3 LEN2 LEN1 LEN0 r rw* rw* rw* rw* rw* rw* rw* Figure 3-92. Active Transmit Buffer Cycle Counter and Payload Length Register NOTE The host may read the CYCL_CNT[5:0] bits but, as those bits are not updated by the CC, they will be in an undefined state. For a description of this register and the bit access scheme, refer to Section 3.5, “Message Buffer Handling and Operations”. 3.2.3.7.5 Active Transmit Buffer Header CRC Register (ATBCRCR) Address 0x184 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved HCRC10 HCRC9 HCRC8 r r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 HCRC7 HCRC6 HCRC5 HCRC4 HCRC3 HCRC2 HCRC1 HCRC0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-93. Active Transmit Buffer Header CRC Register For a description of this register and the bit access scheme, refer to Section 3.5, “Message Buffer Handling and Operations”. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 127 MFR4200 FlexRay Communication Controller 3.2.3.7.6 Active Transmit Buffer Data n Register, n = [0:15] (ATBDATAnR) Address ATBDATA0R=0x186 … ATBDATA15R=0x1A4 Reset undefined state 15 14 13 12 11 10 9 DATA(2n+1)15 DATA(2n+1)14 DATA(2n+1)13 DATA(2n+1)12 DATA(2n+1)11 DATA(2n+1)10 DATA(2n+1)9 8 DATA(2n+1)8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DATA(2n)7 DATA(2n)6 DATA(2n)5 DATA(2n)4 DATA(2n)3 DATA(2n)2 DATA(2n)1 DATA(2n)0 rw rw rw rw rw rw rw rw Figure 3-94. Active Transmit Buffer Data n Register, n = [0:15] For a description of these registers, refer to Section 3.5, “Message Buffer Handling and Operations”. 3.2.3.7.7 Active Transmit Buffer Message Buffer Slot Status Vector Register (ATBMBSSVR) Address 0x1A6 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved CH r r r r r r r r 7 6 5 4 3 2 1 0 VCE SYNCF NULLF SUPF SERR CERR BVIOL TXCON r r r r r r r rh Figure 3-95. Active Transmit Buffer Message Buffer Slot Status Vector Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. MFR4200 Data Sheet, Rev. 1 128 Freescale Semiconductor Memory Map and Registers 3.2.3.7.8 Active Receive Buffer Frame ID Register (ARBFRID) Address 0x140 Reset undefined state 15 14 13 12 11 10 9 8 R* PP NFI SYNC STARTUP ID10 ID9 ID8 rh rh rh rh rh rw* rw* rw* 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-96. Active Receive Buffer Frame ID Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. 3.2.3.7.9 Active Receive Buffer Cycle Counter and Payload Length Register (ARBCCPLR) Address 0x142 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved CYCL_CNT5 CYCL_CNT4 CYCL_CNT3 CYCL_CNT2 CYCL_CNT1 CYCL_CNT0 r r rh rh rh rh rh rh 7 6 5 4 3 2 1 0 Reserved LEN6 LEN5 LEN4 LEN3 LEN2 LEN1 LEN0 r rh rh rh rh rh rh rh Figure 3-97. Active Receive Buffer Cycle Counter and Payload Length Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 129 MFR4200 FlexRay Communication Controller 3.2.3.7.10 Active Receive Buffer Header CRC Register (ARBCRCR) Address 0x144 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved HCRC10 HCRC9 HCRC8 r r r r r rh rh rh 7 6 5 4 3 2 1 0 HCRC7 HCRC6 HCRC5 HCRC4 HCRC3 HCRC2 HCRC1 HCRC0 rh rh rh rh rh rh rh rh Figure 3-98. Active Receive Buffer Header CRC Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. 3.2.3.7.11 Active Receive Buffer Data n Register, n = [0:15] (ARBDATAnR) Address ARBDATA0R=0x146 … ARBDATA15R=0x164 Reset undefined state 15 14 13 12 11 10 9 DATA(2n+1)15 DATA(2n+1)14 DATA(2n+1)13 DATA(2n+1)12 DATA(2n+1)11 DATA(2n+1)10 DATA(2n+1)9 8 DATA(2n+1)8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 DATA(2n)7 DATA(2n)6 DATA(2n)5 DATA(2n)4 DATA(2n)3 DATA(2n)2 DATA(2n)1 DATA(2n)0 rh rh rh rh rh rh rh rh Figure 3-99. Active Receive Buffer Data n Register, n = [0:15] For a description of these registers, refer to Section 3.5, “Message Buffer Handling and Operations”. MFR4200 Data Sheet, Rev. 1 130 Freescale Semiconductor Memory Map and Registers 3.2.3.7.12 Active Receive Buffer Message Buffer Slot Status Vector Register (ARBMBSSVR) Address 0x166 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved CH r r r r r r r r 7 6 5 4 3 2 1 0 VCE SYNCF NULLF SUPF SERR CERR BVIOL TXCON rh rh rh rh rh rh rh r Figure 3-100. Active Receive Buffer Message Buffer Slot Status Vector Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. 3.2.3.7.13 Active FIFO Buffer Frame ID Register (AFBFRID) Address 0x100 Reset undefined state 15 14 13 12 11 10 9 8 R* PP NFI SYNC STARTUP ID10 ID9 ID8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 rh rh rh rh rh rh rh rh Figure 3-101. Active FIFO Buffer Frame ID Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 131 MFR4200 FlexRay Communication Controller 3.2.3.7.14 Active FIFO Buffer Cycle Counter and Payload Length Register (AFBCCPLR) Address 0x102 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved CYCL_CNT5 CYCL_CNT4 CYCL_CNT3 CYCL_CNT2 CYCL_CNT1 CYCL_CNT0 r r rh rh rh rh rh rh 7 6 5 4 3 2 1 0 Reserved LEN6 LEN5 LEN4 LEN3 LEN2 LEN1 LEN0 r rh rh rh rh rh rh rh Figure 3-102. Active FIFO Buffer Cycle Counter and Payload Length Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. 3.2.3.7.15 Active FIFO Buffer Header CRC Register (AFBCRCR) Address 0x104 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved HCRC10 HCRC9 HCRC8 r r r r r rh rh rh 7 6 5 4 3 2 1 0 HCRC7 HCRC6 HCRC5 HCRC4 HCRC3 HCRC2 HCRC1 HCRC0 rh rh rh rh rh rh rh rh Figure 3-103. Active FIFO Buffer Header CRC Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. MFR4200 Data Sheet, Rev. 1 132 Freescale Semiconductor Memory Map and Registers 3.2.3.7.16 Active FIFO Buffer Data n Register, n = [0:15] (AFBDATAnR) Address ARFBDATA0R=0x106 … ARFBDATA15R=0x124 Reset undefined state 15 14 13 12 11 10 9 DATA(2n+1)15 DATA(2n+1)14 DATA(2n+1)13 DATA(2n+1)12 DATA(2n+1)11 DATA(2n+1)10 DATA(2n+1)9 8 DATA(2n+1)8 rh rh rh rh rh rh rh rh 7 6 5 4 3 2 1 0 DATA(2n)7 DATA(2n)6 DATA(2n)5 DATA(2n)4 DATA(2n)3 DATA(2n)2 DATA(2n)1 DATA(2n)0 rh rh rh rh rh rh rh rh Figure 3-104. Active FIFO Buffer Data n Register, n = [0:15] For a description of these registers, refer to Section 3.5, “Message Buffer Handling and Operations”. 3.2.3.7.17 Active FIFO Buffer Message Buffer Slot Status Vector Register (AFBMBSSVR) Address 0x126 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved CH r r r r r r r r 7 6 5 4 3 2 1 0 VCE SYNCF NULLF SUPF SERR CERR BVIOL TXCON rh rh rh rh rh rh rh r Figure 3-105. Active FIFO Buffer Message Buffer Slot Status Vector Register For a description of this register, refer to Section 3.5, “Message Buffer Handling and Operations”. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 133 MFR4200 FlexRay Communication Controller 3.2.3.8 3.2.3.8.1 Filtering Related Registers Sync Frame Acceptance Filter Value Register (SYNFAFVR) Address 0xF0 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved SYNFAFV10 SYNFAFV9 SYNFAFV8 r r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 SYNFAFV7 SYNFAFV6 SYNFAFV5 SYNFAFV4 SYNFAFV3 SYNFAFV2 SYNFAFV1 SYNFAFV0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-106. Sync Frame Acceptance Filter Value Register If ENSYNFF bit is set (see Section 3.2.3.2.1, “Module Configuration Register 0 (MCR0)”), every valid sync frame with the identifier ID must fulfill the following condition before its arrival time measurement values can be used for the clock synchronization. An identifier is accepted when: ( NOT((ID XOR SynFAFV) AND SynFAFM) AND NOT(ID == SynFRF) ) == TRUE Eqn. 3-12 This register may be written only in the configuration state. 3.2.3.8.2 Sync Frame Acceptance Filter Mask Register (SYNFAFMR) Address 0xEE Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved SYNFAFM10 SYNFAFM9 SYNFAFM8 r r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 SYNFAFM7 SYNFAFM6 SYNFAFM5 SYNFAFM4 SYNFAFM3 SYNFAFM2 SYNFAFM1 SYNFAFM0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-107. Sync Frame Acceptance Filter Mask Register SYNFAFM[10:0] 0 – This bit position is “don't care” for acceptance. 1 – This bit of the identifier must be identical to the corresponding bit in the acceptance value, for it to be accepted by the sync frame acceptance filter. This register may be written only in the configuration state. MFR4200 Data Sheet, Rev. 1 134 Freescale Semiconductor Memory Map and Registers 3.2.3.8.3 Sync Frame Rejection Filter Register (SYNFRFR) Address 0xF2 Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved SYNFRF10 SYNFRF9 SYNFRF8 r r r r r rw rw rw 7 6 5 4 3 2 1 0 SYNFRF7 SYNFRF6 SYNFRF5 SYNFRF4 SYNFRF3 SYNFRF2 SYNFRF1 SYNFRF0 rw rw rw rw rw rw rw rw Figure 3-108. Sync Frame Rejection Filter Register If the ENSYNFF bit is set (see Section 3.2.3.2.1, “Module Configuration Register 0 (MCR0)”), this register is used to identify a sync frame ID whose arrival time measurement values are to be rejected for clock synchronization. Note that this register can be written at any time by the host, unlike SYNFAFMR and SYNFAFVR (see Section 3.2.3.8.2, “Sync Frame Acceptance Filter Mask Register (SYNFAFMR)” and Section 3.2.3.8.1, “Sync Frame Acceptance Filter Value Register (SYNFAFVR)”). NOTE To ensure correct operation of the CC, the host should update this register only during the NIT. 3.2.3.8.4 Cycle Counter Filter n Register, n = [0:58] (CCFnR) Address CCF0R=0x202, CCF1R=0x206, …, CCF57R=0x2E6, CCF58R=0x2EA. CCFnR=0x202 + 0x4*dec2hex(n) Reset undefined state 15 14 13 12 11 10 9 8 Reserved Reserved CCM5 CCM4 CCM3 CCM2 CCM1 CCM0 r r rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 Reserved Reserved CCV5 CCV4 CCV3 CCV2 CCV1 CCV0 r r rw* rw* rw* rw* rw* rw* Figure 3-109. Cycle Counter Filter n Register, n = [0:58] Each cycle counter filter register is related to an appropriate message buffer: CCF0R to message buffer 0, CCF1R to message buffer 1, … , CCF58R to message buffer 58. (For more information, refer to Section , “Receive, receive FIFO, and transmit message buffers are accessible to the host MCU only through the active receive, active transmit, and active receive FIFO buffers.”). MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 135 MFR4200 FlexRay Communication Controller CCV[0:5] — Cycle Count Value n Bit[0:5] These bits determine the cycle count value to be used for the cycle filtering. CCM[0:5] — Cycle Count Mask n Bit[0:5] These bits define the mask used in the filtering process. 0 – This bit of the cycle counter is not used for filtering. 1 – This bit of the cycle counter is used for filtering. For a description of the read and write character of each bit-field, refer to Section 3.4.1, “Message Buffer Control, Configuration and Status Register” and Section 3.4.2, “Message Buffer Filter Registers”. 3.2.3.8.5 FIFO Acceptance Filter Message ID Value Register (FAFMIDVR) Address 0x1C Reset 0x0 15 14 13 12 11 10 9 8 FMDAFV15 FMDAFV14 FMDAFV13 FMDAFV12 FMDAFV11 FMDAFV10 FMDAFV9 FMDAFV8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 FMDAFV7 FMDAFV6 FMDAFV5 FMDAFV4 FMDAFV3 FMDAFV2 FMDAFV1 FMDAFV0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-110. FIFO Acceptance Filter Message ID Value Register FMDAFV[0:15] These bit-fields define the FIFO message ID filter value, for comparison with the message ID field of received frames. It defines the acceptable pattern value of the message ID to be received. These bits may be written only in the configuration state. 3.2.3.8.6 FIFO Acceptance Filter Message ID Mask Register (FAFMIDMR) Address 0x1E Reset 0x0 15 14 13 12 11 10 9 8 FMDAFM15 FMDAFM14 FMDAFM13 FMDAFM12 FMDAFM11 FMDAFM10 FMDAFM9 FMDAFM8 rw* rw* rw* rw* rw* rw* rw* rw* 7 6 5 4 3 2 1 0 FMDAFM7 FMDAFM6 FMDAFM5 FMDAFM4 FMDAFM3 FMDAFM2 FMDAFM1 FMDAFM0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-111. FIFO Acceptance Filter Message ID Mask Register MFR4200 Data Sheet, Rev. 1 136 Freescale Semiconductor Memory Map and Registers FMDAFM[0:15] These bit-fields define the mask for the FIFO message ID filter. 0 – This bit in the message ID field of a received frame is not considered for acceptance filtering. 1 – This bit in the message ID field of a received frame is used for the acceptance filtering. These bits may be written only in the configuration state. 3.2.3.8.7 FIFO Acceptance/Rejection Filter Channel Register (FAFCHR) Address 0x1A Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved r r r r r r r r 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved FCHBAFV FCHAAFV r r r r r r rw* rw* Figure 3-112. FIFO Acceptance/Rejection Filter Channel Register FCHAAFV, FCHBAFV These are FIFO channel filtering value bits. They define the channel from which the received frame will be accepted or rejected. These bits may be written only in the configuration state. Table 3-10. FIFO Channel Filtering Configuration Receive message buffer Store valid Rx frame FCHAAFV FCHBAFV 1 1 Frame received on both channels are accepted or rejected 1 0 Frame received on channel A is accepted or rejected 0 1 Frame received on channel B is accepted or rejected 0 0 Ignore frame MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 137 MFR4200 FlexRay Communication Controller 3.2.3.8.8 FIFO Rejection Filter Frame ID Value Register (FRFFIDVR) Address 0x20 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved FFIDRFV10 FFIDRFV9 FFIDRFV8 r r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 FFIDRFV7 FFIDRFV6 FFIDRFV5 FFIDRFV4 FFIDRFV3 FFIDRFV2 FFIDRFV1 FFIDRFV0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-113. FIFO Rejection Filter Frame ID Value Register FFIDRFV[0:10] This field contains the FIFO frame ID rejection filter value, for comparison with frame ID fields of received frames. It defines the acceptable pattern value of the frame ID to be rejected. These bits may be written only in the configuration state. 3.2.3.8.9 FIFO Rejection Filter Frame ID Mask Register (FRFFIDMR) Address 0x22 Reset 0x0 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved FFIDRFM10 FFIDRFM9 FFIDRFM8 r r r r r rw* rw* rw* 7 6 5 4 3 2 1 0 FFIDRFM7 FFIDRFM6 FFIDRFM5 FFIDRFM4 FFIDRFM3 FFIDRFM2 FFIDRFM1 FFIDRFM0 rw* rw* rw* rw* rw* rw* rw* rw* Figure 3-114. FIFO Rejection Filter Frame ID Mask Register FFIDRFM[0:10] These bit-fields indicate the mask for the FIFO Rejection frame ID filter. 0 – This bit of the internal slot ID (when a frame was received) is not considered for the rejection filtering. 1 – This bit of the internal slot ID (when a frame was received) is used for the rejection filtering. These bits may be written only in the configuration state. MFR4200 Data Sheet, Rev. 1 138 Freescale Semiconductor Memory Map and Registers 3.2.3.9 Timer Related Registers The CC provides two timers with timer interrupt configuration registers for setting interrupts for specific points of global time. Each timer contains two parameters: 1. Cycle Set: A 9-bit register is used to specify in which set of communication cycles the interrupt will occur. It consists of two fields, the base cycle [b] and the cycle repetition [c]. The set of cycle numbers where the interrupt is to generated is determined from these two fields using the formula: b + n*2^c (n = 0, 1, 2, …) Eqn. 3-13 where: — b is a 6-bit cycle number used to identify the initial value for generating the cycle set. — c is a 3-bit value used to determine a constant repetition factor to be added to the base cycle (c = 0 … 6) — b must be smaller than 2^c: b VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the CC is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1. Absolute Maximum Ratings1 Num Rating Symbol Min Max Unit 1 I/O, Regulator and Analog Supply Voltage VDD5 -0.3 6.5 V 2 Digital Logic Supply Voltage 2 VDD -0.3 3.0 V VDDOSC -0.3 3.0 V 2 3 Oscillator Supply Voltage 4 Voltage difference VDDX to VDDR and VDDA ΔVDDX -0.3 0.3 V 5 Voltage difference VSSX to VSSR and VSSA ΔVSSX -0.3 0.3 V 6 Digital I/O Input Voltage VIN -0.3 6.5 V 7 EXTAL, XTAL inputs VILV -0.3 3.0 V 8 Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 I -25 +25 mA 9 Instantaneous Maximum Current Single pin limit for EXTAL, XTAL4 IDL -25 +25 mA 10 Operating Temperature Range (packaged) TA -40 +125 oC 11 Operating Temperature Range (junction) TJ -40 +150 oC 12 Storage Temperature Range Tstg – 65 155 °C D 1 Beyond absolute maximum ratings device might be damaged. The device contains an internal voltage regulator to generate the logic and OSC supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3 All digital I/O pins are internally clamped to V SSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4 Those pins are internally clamped to V SSOSC and VDDOSC. 2 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 221 Electrical Characteristics A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2. ESD and Latch-up Test Conditions Model Human Body Machine Latch-up Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Number of Pulse per pin positive negative - 3 3 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Number of Pulse per pin positive negative - 3 3 Minimum input voltage limit - -2.5 V Maximum input voltage limit - 7.5 V Table A-3. ESD and Latch-up Protection Characteristics Num C Rating Symbol Min Max Unit 1 T Human Body Model (HBM) VHBM 2000 - V 2 T Machine Model (MM) VMM 200 - V 3 T Charge Device Model (CDM) VCDM 500 - V 4 T Latch-up Current at TA = 125°C positive negative ILAT +100 -100 - T Latch-up Current at TA = 27°C positive negative ILAT 5 mA - mA +200 -200 MFR4200 Data Sheet, Rev. 1 222 Freescale Semiconductor General A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4. Operating Conditions Rating Oscillator and Quartz frequency Symbol Min Typ Max Unit fOSC - 40.000 40.000 MHz Quartz overtone Fundamental Frequency Quartz frequency stability at TJ fSTB -1500 300 1500 ppm Voltage difference VDDX to VDDR and VDDA DVDDX -0.1 0 0.1 V Voltage difference VSSX to VSSR and VSSA DVSSX -0.1 0 0.1 V I/O, Regulator and Analog Supply VDD5 2.97 3.3 5.5 V VDD 2.25 2.5 2.75 V VDDOSC 2.25 2.5 2.75 V Digital Logic Supply Voltage1 Oscillator Supply Voltage1 Operating Junction Temperature Range TJ -40 - 140 oC Operating Ambient Temperature Range2 TJ -40 27 125 oC 1 2 The device contains an internal voltage regulator to generate the logic and OSC supply out of the I/O supply. Refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” for more information about the relation between ambient temperature TA and device junction temperature TJ. A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D • Θ JA ) Eqn. A-1 TJ = Junction Temperature [°C] TA = Ambient Temperature [°C] PD = Total Chip Power Dissipation [W] ΘJA = Package Thermal Resistance [°C/W] The total power dissipation can be calculated from: MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 223 Electrical Characteristics P D = P INT + P IO Eqn. A-2 PINT = Chip Internal Power Dissipation [W] Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD ⋅ V DD + I DDOSC ⋅ V DDOSC + I DDA ⋅ V DDA P IO = ∑ R DSON ⋅ I IO i Eqn. A-3 2 Eqn. A-4 i PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ------------ ; I OL for outputs driven low Eqn. A-5 respectively V DD5 – V OH R DSON = ------------------------------------ ; for outputs driven high I OH Eqn. A-6 2. Internal voltage regulator enabled P INT = I DDR ⋅V DDR +I DDA ⋅V Eqn. A-7 DDA IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. P IO = ∑ RDSON ⋅ IIOi 2 Eqn. A-8 i PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. MFR4200 Data Sheet, Rev. 1 224 Freescale Semiconductor General Table A-5. Thermal Package Simulation Details Num 1 2 3 4 5 6 Rating Symbol Value Unit 1 Junction to Ambient LQFP64, single sided PCB1,2, Natural Convection RθJA 67 o C/W 2 Junction to Ambient LQFP64, double sided PCB with 2 internal planes1,3, Natural Convection RθJMA 52 o C/W 3 Junction to Ambient LQFP64 (@200 ft/min), single sided PCB1,3 RθJMA 60 o C/W RθJMA 48 o C/W 4 Junction to Ambient LQFP64 (@200 ft/min), double sided PCB with 2 internal planes1,3 5 Junction to Board LQFP644 RθJB 34 o C/W 6 Junction to Case LQFP645 RθJC 17 o C/W 7 Junction to Package Top LQFP646, Natural Convection ΨJT 3 o C/W Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and EIA/JEDEC Standard 51-2 with the single layer horizontal PC Board according to EIA/JEDEC Standard 51-3 Per EIA/JEDEC Standard 51-6 with the four layer horizontal PC Board (double-sided PCB with two internal planes) according to EIA/JEDEC Standard 51-7 Thermal resistance between the die and the printed circuit board per EIA/JEDEC Standard 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per EIA/JEDEC Standard 51-2. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 225 Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all 3.3V I/O pins. All parameters are not always applicable, e.g. not all pins feature pullup/pulldown resistances. Table A-6. 5V I/O Characteristics (VDD5 = 5V) Conditions are shown in Figure A-4, unless otherwise noted. Num C 1 P Symbol Min Typ Max Unit Input High Voltage VIH 0.65*VDD5 - - V T Input High Voltage VIH - - VDD5+0.3 V P Input Low Voltage VIL - - 0.35*VDD5 V T Input Low Voltage VIL VSS5-0.3 - - V 3 C Input Hysteresis VHYS - 250 - mV 4 P High Impedance (Off-state) Leakage Current VIN=VDD or VSS, all input/output and output pins IIN -2.5 - +2.5 uA 5 P Output High Voltage (pins in output mode) @50% Partial Drive IOH = -2mA VOH VDD5-0.8 - - V 6 P Output High Voltage (pins in output mode) @100% Full Drive IOH = -10mA VOH VDD5-0.8 - - V 7 P Output Low Voltage (pins in output mode) @50% Partial Drive IOL = +2mA VOL - - 0.8 V 8 P Output Low Voltage (pins in output mode) @100% Full Drive IOL = +10mA VOL - - 0.8 V 9 P Internal Pullup Device Current, tested at VIL Max IPUL - - -130 uA 10 P Internal Pullup Device Current, tested at VIH Min. IPUH -10 - - uA 11 P Internal Pulldown Device Current, tested at VIH Min. IPDH - - 130 uA 12 P Internal Pulldown Device Current, tested at VIL Max IPDL 10 - - uA 13 d Input Capacitance (input, input/output pins) CIN - 7 - pF 14 T Injection Current1 2 15 1 P Rating mA Single Pin Limit IICS -2.5 - 2.5 Total Device Limit. Sum of all injected currents IICP -25 - 25 Load Capacitance 50% Partial Drive 100% Full Drive CL - - pF 25 50 Refer to Section A.1.4, “Current Injection”, for more information. MFR4200 Data Sheet, Rev. 1 226 Freescale Semiconductor General Table A-7. 3.3V I/O Characteristics (VDD5 = 3.3V) Conditions are VDDX=3.3V +/-10% Temperature from -40oC to +140oC, unless otherwise noted Num C 1 P Symbol Min Typ Max Unit Input High Voltage VIH 0.65*VDD5 - - V T Input High Voltage VIH - - VDD5+0.3 V P Input Low Voltage VIL - - 0.35*VDD5 V T Input Low Voltage VIL VSS5-0.3 - - V 3 C Input Hysteresis VHYS - 250 - mV 4 P High Impedance (Off-state) Leakage Current VIN=VDD or VSS, all input/output and output pins IIN -2.5 - +2.5 uA 5 P Output High Voltage (pins in output mode) @50% Partial Drive IOH = -0.75mA VOH VDD5-0.4 - - V 6 P Output High Voltage (pins in output mode) @100% Full Drive IOH = -4.5mA VOH VDD5-0.4 - - V 7 P Output Low Voltage (pins in output mode) @50% Partial Drive IOL = +0.9mA VOL - - 0.4 V 8 P Output Low Voltage (pins in output mode) @100% Full Drive IOL = +5.5mA VOL - - 0.4 V 9 P Internal Pullup Device Current, tested at VIL Max IPUL - - -60 uA 10 P Internal Pullup Device Current, tested at VIH Min. IPUH -6 - - uA 11 P Internal Pulldown Device Current, tested at VIH Min. IPDH - - 60 uA 12 P Internal Pulldown Device Current, tested at VIL Max IPDL 6 - - uA 13 D Input Capacitance (input, input/output pins) CIN - 7 - pF 14 T Injection Current1 2 15 1 P Rating mA Single Pin Limit IICS -2.5 - 2.5 Total Device Limit. Sum of all injected currents IICP -25 - 25 Load Capacitance 50% Partial Drive 100% Full Drive CL - - pF 25 50 Refer to Section A.1.4, “Current Injection” for more information. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 227 Electrical Characteristics A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured with internal voltage regulator enabled and a 40 MHz oscillator in standard Pierce mode. Production testing is performed using a square wave signal at the EXTAL input. Table A-8. Supply Current Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 Rating P Run supply currents Internal regulator enabled Symbol Min Typ Max Unit IDD5 - - 49.901 mA 25°C - - 50.563 70°C - - TBD 85°C - - TBD 100°C - - TBD 105°C - - TBD 120°C - - TBD 125°C - - TBD 140°C - - 51.047 -40°C MFR4200 Data Sheet, Rev. 1 228 Freescale Semiconductor Voltage Regulator (VREG) A.2 Voltage Regulator (VREG) A.2.1 Operating Conditions Table A-9. Voltage Regulator - Operating Conditions Conditions are shown in Table A-4 unless otherwise noted Num C 1 P Input Voltages 2 P Regulator Current Shutdown Mode 3 P 4 5 6 P P C Characteristic Symbol Min Typical Max Unit VVDDR,A 2.97 — 5.5 V IREG — TBD 40 μA Output Voltage Core Full Performance Mode Shutdown Mode VDD 2.45 — 2.5 —1 2.75 — V V Output Voltage OSC Full Performance Mode Shutdown Mode VDDOSC 2.35 — 2.5 —2 2.75 — V V Low Voltage Reset3 Assert Level VLVRA 2.25 — — V Power-on Reset4 Assert Level Deassert Level VPORA VPORD 0.97 — — — — 2.05 V V 1 High Impedance Output High Impedance Output 3 Monitors VDD, always active 4 Monitors VDD, always active 2 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 229 Electrical Characteristics A.2.2 Chip Power-up and Voltage Drops Voltage regulator sub modules POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-1. V VDD VLVRD VLVRA VPORD t POR LVR Figure A-1. Voltage Regulator — Chip Power-up and Voltage Drops (not scaled) A.2.3 Output Loads A.2.3.1 Resistive Loads On-chip voltage regulator intended to supply the internal logic and oscillator circuits allows no external DC loads. A.2.3.2 Capacitive Loads The capacitive loads are specified in Table A-10. Ceramic capacitors with X7R dielectricum are required Table A-10. Voltage Regulator Recommended Capacitive Loads Num Characteristic 1 VDD external capacitive load 3 VDDOSC external capacitive load Symbol Min Typical Max Unit CDDext 200 440 12000 nF CDDOSCext 90 220 5000 nF MFR4200 Data Sheet, Rev. 1 230 Freescale Semiconductor Reset and Oscillator A.3 Reset and Oscillator This section summarizes the electrical characteristics of the various startup scenarios for the Oscillator. A.3.1 Startup Table A-11 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the MFR4200 Clock and Reset Generator (CRG) Block User Guide. Table A-11. Startup Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 T POR release level VPORR - - 2.07 V 2 T POR assert level VPORA 0.97 - - V 3 D Reset input pulse width, minimum input time PWRSTL 2 - - tosc A.3.1.1 POR The release level VPORR (see Table A-9) and the assert level VPORA (see Table A-9) are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator is started. A.3.1.2 LVR The assert level VLVRA (see Table A-9) is derived from the VDD Supply. After releasing the LVR reset, the oscillator is started. A.3.1.3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CC starts operations, if there was an oscillation before reset. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 231 Electrical Characteristics A.3.2 Oscillator The device features an internal Pierce oscillator. The device does not have a clock monitor. Table A-12. Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 Rating Symbol Min Typ Max Unit 1 C Crystal oscillator range (Pierce) 1 fOSC 0.5 - 40 MHz 2 P Startup Current iOSC 100 - - μA 6 P External square wave input frequency fEXT 0.5 - 50 MHz 7 D External square wave pulse width low tEXTL 9.5 - - ns 8 D External square wave pulse width high tEXTH 9.5 - - ns 9 D External square wave rise time tEXTR - - 1 ns 10 D External square wave fall time tEXTF - - 1 ns 11 D Input Capacitance (EXTAL, XTAL pins) CIN - 7 - pF 12 C DC Operating Bias in Pierce mode on EXTAL Pin VDCBIAS - TBD - V Depending on the crystal a damping series resistor might be necessary A.4 AMI Interface Timing Diagram The CC AMI Interface read/write timing diagram is shown on the Figure A-2. • Writing to the device is accomplished when Chip Enable(CE#) and Write Enable (WE#) inputs are low (asserted). • Reading from the device is accomplished when Chip Enable (CE#) and Output Enable (OE#) are low (asserted) while the Write Enable (WE#) is high (negated). • The input/output pins (D[15:0]) are in a high-impedance state when the device is not selected (CE# is high), the outputs are disabled (OE# is high) or during a write operation (CE# is low, WE# is low). MFR4200 Data Sheet, Rev. 1 232 Freescale Semiconductor AMI Interface Timing Diagram tRC tACE tOEH CE# tSAR A[9..1] tHAR ADDRESS valid tDOE tHOE tLOE OE# tHZOE tLZOE D[15..0] High-Z DATA valid High-Z “1” WE# READ CYCLE tWC tSCE tCEWE CE# tSAW A[9..1] tHAW ADDRESS valid tPWE tWEH WE# High-Z D[15..0] High-Z DATA valid tSD tHD “1” OE# WRITE CYCLE Figure A-2. AMI Interface Read and Write Timing Diagrams MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 233 Electrical Characteristics tOEWE CE# A[9..1] ADDRESS valid ADDRESS valid “1” OE# D[15..0] High-Z High-Z DATA valid WE# DATA valid HighZ “1” WRITE CYCLE READ CYCLE Figure A-3. AMI Interface Write-after-Read Transactions Timing Diagram tWEOE CE# A[9..1] ADDRESS valid ADDRESS valid “1” WE# D[15..0] OE# HighZ DATA valid High-Z DATA valid High-Z “1” WRITE CYCLE READ CYCLE Figure A-4. AMI Interface Read-after-Write Transactions Timing Diagram MFR4200 Data Sheet, Rev. 1 234 Freescale Semiconductor AMI Interface Timing Diagram Table A-13. AMI Interface AC Switching Characteristics over the Operating Range Characteristic Symbol Min Max Unit Read Cycle Read Time Cycle tRC 155 - ns Address Setup Read tSAR 5 - ns Address Hold Read tHAR 50 - ns OE# LOW to Data valid tDOE - 145 ns OE# high time tHOE 30 - ns OE# low time tLOE 150 - ns OE# LOW to Low-Z tLZOE 20 - ns OE# HIGH to High-Z tHZOE - 15 ns OE# HIGH to CE# HIGH tOEH 0 - ns WE# HIGH to OE# LOW tWEOE 80 - ns Write Cycle Write Time Cycle tWC 50 - ns Address Setup Write tSAW 30 - ns Address Hold Write tHAW 5 - ns CE# LOW to Write End tSCE 50 - ns Data Set-up to Write End tSD 30 - ns Data Hold from Write End tHD 5 - ns WE# Pulse Width tPWE 30 - ns WE# high time tWEH 55 - ns Write End to CE# high tCEWE 30 - ns OE# HIGH to WE# LOW tOEWE 15 - ns MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 235 Electrical Characteristics A.5 HCS12 Interface Timing Diagram The HCS12 device external bus is synchronous with clock frequency up to 8 MHz. Signals are sampled on the both ECLK# edges (see Figure A-5). The HCS12 host addresses the CC as a slow memory device. Due to that the HCS12 ECLK external clock signal must be stretched. In the MFR4200 the output ECLK clock must be stretched by 3 periods of the HCS12 internal bus-rate clock. The CC HCS12 Interface read/write timing diagram is shown in Figure A-5. For more information regarding the HCS12 and HCS12 programming, refer to the HCS12 V1.5 core user guide, available at http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12CPU15UG.pdf. 1 2 ECLK 3 (x)Addr/Data (write) data 4 5 (x)addr 7 6 data 8 9 R/W 10 (x)Addr/Data (read) 11 data 12 13 (x)addr 14 15 data ACS ACS 20 21 22 LSTRB Figure A-5. HCS12 Interface Read/write Timing Diagram MFR4200 Data Sheet, Rev. 1 236 Freescale Semiconductor HCS12 Interface Timing Diagram Table A-14. HCS12 Interface Timing Parameters Units Restriction1 - ns CC - - ns CC 11 - - ns HCS12 - - - 7 ns HCS12 ECLK rise to write data invalid 3/CC_CLK {75}-[4] - - ns CC 6(4) Write data hold time - 2 - - ns HCS12 7 RW delay time - - - 7 ns HCS12 8 RW valid time to ECLK rise - 14 - - ns HCS12 9 RW hold time - 2 - - ns HCS12 10 Data hold to address - 2 - - ns HCS12 12 Multiplexed address hold time - 2 - - ns HCS12 13 ECLK high access time (ECLK high to Read Data valid) 2/CC_CLK {50} 3/CC_CLK {75} ns CC 14 Read data setup time - 13 - - ns HCS12 15 Read data hold time - 0 - - ns HCS12 20 Low strobe delay time - - - 7 ns HCS12 21 Low strobe valid to ECLK rise - 14 - - ns HCS12 22 Low strobe hold time - 2 - - ns HCS12 Num Rating Min Max 1 Pulse width, ECLK Low 1/CC_CLK {25}2 3 - 2 Pulse width, ECLK High 4/CC_CLK {100}+[14] 3,11 Address valid time to E rise4 - 4 Write data delay time 5 1 Column Restriction: - CC limitation by the Communication Controller but complies to HCS12. - HCS12 limitation because of HCS12 specification. 2 { .. } - values in ns if the CC_CLK = 40 MHz. 3 If the parameter is not met then ECLK signal deassertion cannot be sampled and the write/read window cannot be calculated. 4 (X)Addr and LSTRB are taken over by the controller with the rising edge of the ECLK. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 237 Electrical Characteristics MFR4200 Data Sheet, Rev. 1 238 Freescale Semiconductor 64-pin LQFP package Appendix B Package Information B.1 64-pin LQFP package Figure B-1. 64-pin LQFP Mechanical Dimensions (Case No. 840F-02) (Page 1) MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 239 Package Information Figure B-2. 64-pin LQFP Mechanical Dimensions (Case No. 840F-02) (Page 2) MFR4200 Data Sheet, Rev. 1 240 Freescale Semiconductor 64-pin LQFP package Figure B-3. 64-pin LQFP Mechanical Dimensions (Case No. 840F-02) (Page 3) MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 241 Package Information MFR4200 Data Sheet, Rev. 1 242 Freescale Semiconductor 64-pin LQFP package Appendix C Printed Circuit Board Layout Recommendations The PCB must be laid out carefully to ensure proper operation of the voltage regulator and the CC. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (Cd). • The central point of the ground star should be the VSSR pin. • Low-ohmic low-inductance connections should be used between VSSX and VSSR. • VSSOSC must be directly connected to VSSR. • Traces of VSSOSC, EXTAL and XTAL must be kept as short as possible. Occupied board area for C1, C2, C3 and Q should be as small as possible. • Other signals or supply lines should not be routed under the area occupied by C1, C2, C3, and Q and the connection area of the CC. • The central power input should be fed in at the VDDA/VSSA pins. Figure C-1 shows a recommended PCB layout (64-pin LQFP) for standard Pierce oscillator mode, while Table C-1 provides suggested values for the external components. Table C-1. Suggested External Component Values Component Purpose Type Value C1 OSC load cap ceramic X7R 2pF C2 OSC load cap ceramic X7R 2pF C3 VDDOSC filter cap ceramic X7R 100– 220nF C4 VDDA filter cap ceramic X7R 100– 220nF Cd VDDR, VDDX filter cap ceramic X7R/tantalum 100– 220nF Cload VDD2_5 filter cap ceramic X7R 100– 220nF RB OSC res 1 MOhm RS OSC res 0 Ohm (i.e. short-circuit_ Q Quartz NDK NX8045GA 40 MHz MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 243 Printed Circuit Board Layout Recommendations Figure C-1. Recommended PCB Layout (64-pin LQFP) for Standard Pierce Oscillator Mode MFR4200 Data Sheet, Rev. 1 244 Freescale Semiconductor Appendix C MFR4200 Protocol Implementation Document C.1 C.1.1 Introduction Purpose This document is an appendix to the MFR4200 FlexRay Microcontroller data sheet (MFR4200V2). It describes the FlexRay protocol implementation in the MFR4200. C.1.2 Structure This appendix follows the structure of the FlexRay Communications System Protocol Specification V1.1 (PS V1.1). Each section explains whether the implementation in the MFR4200 is identical to the PS V1.1 or is realized with an intermediate solution. Where only the section headline is provided, the implementation is compliant with the PS V1.1. C.1.3 References 1. FlexRay Communications System Protocol Specification V1.1 (intermediate consortium baseline) (PS V1.1/PWD) 2. MFR4200 FlexRay Microcontroller Data Sheet (MFR4200V2) MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 245 MFR4200 Protocol Implementation Document C.2 Overall Protocol State Machine The MFR4200 implements the overall protocol state machine according to PS V1.1/PWD, with differences presented below. Protocol Operation Control (POC) initiate hardware CONFIG host: wakeup WAKEUP host: config complete take over config data CODEC on A (INIT), CODEC on B (INIT), FSP control on A (INIT), FSP control on B (INIT), MAS control on A (INIT), MAS control on B (INIT), CSP control (INIT) reset status information STARTUP pSyncSlot ? CODEC on A (NORMAL), CODEC on B (NORMAL), FSP control on A (GO), FSP control on B (GO), MAS control on A (ALL), MAS control on B (ALL), CSP control (SYNC) =0 else vClockCorrectionFailedCounter:=0 CODEC on A (NORMAL), CODEC on B (NORMAL), FSP control on A (GO), FSP control on B (GO), MAS control on A (ALL), MAS control on B (ALL), CSP control (NOSYNC) NORMAL_ACTIVE Figure C-1. Protocol Operation Control (POC) - 1 MFR4200 Data Sheet, Rev. 1 246 Freescale Semiconductor Overall Protocol State Machine not implemented for FPGA V8.x NORMAL_ACTIVE, NORMAL_PASSIVE * low voltage hardware reset activated transmitter off cycle start (zCycleCounter) - * * (freeze) host: config host: freeze internal error transmitter off transmitter off CONFIG FREEZE red state host: config CONFIG Figure C-2. Protocol Operation Control (POC) - 2 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 247 MFR4200 Protocol Implementation Document vClockCorrectionFailed:=0 NORMAL_ACTIVE ClockSyncState(zClockState, zStartupPairs, zRefPair) even zCycleCounter ? odd SUCCESSFUL zClockState ? LIMIT_REACHED MISSING_RATE vClockCorrectionFailed := vClockCorrectionFailed + 1 vClockCorrectionFailed ? >= gMaxWithoutClockCorrectionFatal else vClockCorrectionFailed ? else >= gMaxWithoutClockCorrectionPassive false NORMAL_PASSIVE CODEC on A (NORMAL), CODEC on B (NORMAL), FSP control on A (GO), FSP control on B (GO), MAS control on A (NOCE), MAS control on B (NOCE), CSP control (NOSYNC) pAllowFreezeDueToClock ? true CODEC on A (INIT), CODEC on B (INIT), FSP control on A (INIT), FSP control on B (INIT), MAS control on A (INIT), MAS control on B (INIT), CSP control (INIT) READY Figure C-3. POC — Normal Operation MFR4200 Data Sheet, Rev. 1 248 Freescale Semiconductor Coding and Decoding NORMAL_PASSIVE ClockSyncState(zClockState, StartupPairs, zRefPair) even zCycleCounter ? odd MISSING_RATE zClockState ? SUCCESSFUL LIMIT_REACHED vClockCorrectionFailed ? < gMaxWithoutClockCorrectionFatal vClockCorrectionFailed := 0 else pAllowPassiveToFreeze ? true vClockCorrectionFailed := vClockCorrectionFailed + 1; vClockCorrectionFailed ? false >1 zStartupNodes? else =1 pStartupNode? < gMaxWithoutClockCorrectionFatal false pAllowFreezeDueToClock ? false true true CODEC on A (INIT), CODEC on B (INIT), FSP control on A (INIT), FSP control on B (INIT), MAS control on A (INIT), MAS control on B (INIT), CSP control (INIT) pSyncSlot ? =0 else FREEZE CODEC on A (NORMAL), CODEC on B (NORMAL), FSP control on A (GO), FSP control on B (GO), MAS control on A (ALL), MAS control on B (ALL), CSP control (SYNC) NORMAL_ACTIVE CODEC on A (NORMAL), CODEC on B (NORMAL), FSP control on A (GO), FSP control on B (GO), MAS control on A (ALL), MAS control on B (ALL), CSP control (NOSYNC) Figure C-4. POC — Passive Operation C.3 Coding and Decoding The implementation is compliant with PS V1.1, with the exception that the wakeup symbol is not detected. C.3.1 Overview The implementation is compliant with PS V1.1. C.3.2 NRZ Coding The implementation is compliant with PS V1.1. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 249 MFR4200 Protocol Implementation Document C.3.3 NRZ Decoding The implementation is compliant with PS V1.1. C.3.3.1 NFZ Decoding Principles The implementation is compliant with PS V1.1. C.3.3.2 Frame Decoding The implementation is compliant with PS V1.1. C.3.3.3 Symbol Decoding The implementation is compliant with PS V1.1. C.3.3.3.1 Collision Resolution Symbol The implementation is compliant with PS V1.1. C.3.3.3.2 Wakeup Symbol MFR4200 can generate a wakeup symbol in accordance with Section C.3.2, “NRZ Coding”. However, the implementation does not recognize a wakeup symbol. See also Section C.7.2, “Cluster Wakeup”. C.3.3.4 Decoding Error The implementation is compliant with PS V1.1. C.3.4 Signal Integrity The implementation is compliant with PS V1.1. C.4 Frame Format The implementation is compliant with PS V1.1. NOTE The semantic of the null frame bit has been inverted compared with previous implementations, to be compliant with PS V1.1. C.5 Media Access Control The implementation is compliant with PS V1.1. NOTE Due to the implementation, there is a lower boundary gdNIT (see Section 3.2.3.3.18, “Network Idle Time Configuration Register (NITCR). MFR4200 Data Sheet, Rev. 1 250 Freescale Semiconductor Frame and Symbol Processing C.6 Frame and Symbol Processing The implementation is compliant with PS V1.1, with the following exceptions. • STUP is not indicated to the host. • Data received during startup is not provided to the host. C.7 C.7.1 Wakeup, Startup, and Reintegration Introduction The implementation is compliant with PS V1.1. C.7.2 Cluster Wakeup The functionality of the wakeup is implemented in part only. The controller can generate wakeup symbols on configurable channels and repeat them for a configurable number of times in accordance with WAKEUP SEND. WAKEUP LISTEN is not implemented. After completing WAKEUP SEND, the controller returns to the CONFIG state. C.7.3 Communication Startup and Reintegration Clearing the coldstart inhibit bit after leaving 'PC_RESET' is not supported in MFR4200. This applies for the following subsections. C.7.3.1 Definitions and Properties The implementation is compliant with PS V1.1. C.7.3.2 Principle of Operation The implementation is compliant with PS V1.1. C.7.3.3 Coldstart Inhibit Mode The implementation is compliant with PS V1.1. C.7.3.4 Startup State Diagram The implementation is compliant with PS V1.1. However, the protocol state indicated in the host interface is incorrect for a short time, in the following case: When the node has unsuccessfully performed a coldstart, and the number of remaining coldstart attempts is 0, the host interface indicates that the controller has entered the coldstart listen state, and will change to the integration listen state only after approximately one macrotick. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 251 MFR4200 Protocol Implementation Document Moreover, in Figure 7-6 (PS V1.1), and in similar drawings for nodes B and C, the state Initialize schedule lasts until the end of the communication cycle, rather than changing in the middle of the cycle. C.8 C.8.1 Clock Synchronization Introduction The implementation is compliant with PS V1.1. C.8.2 Time Representation The implementation is compliant with PS V1.1. C.8.3 Synchronization Process Figure 8-3 (PS V1.1): In MFR4200 the measurement tables are initialized during the NIT (before cycle start, rather than after the cycle start). The entries for the even cycle are initialized in the NIT of the odd cycle. Likewise, the measurements of the odd cycle are initialized in the NIT of the even cycle. C.8.4 Clock Startup The implementation is compliant with PS V1.1. C.8.5 Time Measurement The implementation is compliant with PS V1.1. However, note that the clock sync measurement values indicated in the host interface are different from the example shown in Figure 8-8 (PS V1.1). C.8.5.1 Data Structure The implementation is compliant with PS V1.1. C.8.5.2 Initialization In MFR4200, the table for the odd cycle measurements is initialized in the NIT of the even cycle, and vice versa, rather than after the beginning of the even cycle. C.8.6 Correction Term Calculation Figure 8-13 (PS V1.1): MFR4200 differs slightly from this description. Startup frames are counted on a per channel basis, with one counter for each channel, rather than one counter for both channels. For evaluation, the maximum is taken, rather than counting a startup frame on either channel with a single counter. Moreover, in MFR4200, the check of vOffsetCorrection is performed before the external offset correction, rather than after external offset correction. MFR4200 Data Sheet, Rev. 1 252 Freescale Semiconductor Controller Host Interface Figure 8-14 (PS V1.1): In MFR4200 the check of vRateCorrection is performed before the external offset correction rather than after external rate correction. C.8.7 Clock Correction Figure 8-15 (PS V1.1): The implementation in MFR4200 is compliant with the red text in the middle of the diagram. Moreover, when macrotick counting is reset, the host interface indication of vMacrotick is immediately reset to 0, as soon as the macrotick counting is reset; however, internally, the macrotick generation continues for a short time in accordance with the specification. C.8.8 Sync Frame Configuration Rules Table 8-3 (PS V1.1): MFR4200 supports up to 16 sync frames, rather than 15. C.9 Controller Host Interface The implementation of the host interface is compliant with the specification in PS V1.1. The implementation supports the following features: • Message filtering — Frame ID filtering — Cycle counter filtering — Channel filtering — Message ID filtering (FIFO only) • Message FIFO (receive FIFO) • Timer • Error signalling • Host interrupts — Timer interrupt — Error signaling interrupt • Network management vector C.10 Device Specific Power Modes MFR4200 supports supervision of voltage levels, and performs a reset when the supply voltage drops below a boundary specified in Chapter 5, “Clocks and Reset Generator. A low power mode or sleep mode is not supported. C.11 Bus Guardian Schedule Monitoring The implementation is compliant with PS V1.1. MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 253 MFR4200 Protocol Implementation Document C.12 C.12.1 System Parameters and Configuration Constraints System Parameters System parameters are used primarily for the protocol description and are not protocol mechanisms. Therefore, they are almost transparent to the user in the MFR4200 implementation. The only difference from PS V1.1 that is relevant to the user is as follows. • cSyncNodeMax is fixed at 16. NOTE Parameters relating to unsupported features are not mentioned here. C.12.2 Configuration Constraints The implementation requires most of the constraints specified in PS V1.1 to be fulfilled. Exceptions are bit rate configuration and bit sample clock frequency, which are configurable in a wider range than described in PS V1.1. NOTE However, while fulfilling these configuration constraints is necessary, it is not sufficient for a valid configuration. MFR4200 Data Sheet, Rev. 1 254 Freescale Semiconductor Appendix D Index of Registers A Active FIFO Buffer Cycle Counter and Payload Length Register (AFBCCPLR) 132 Active FIFO Buffer Data n Register (AFBDATAnR) 133 Active FIFO Buffer Frame ID Register (AFBFRID) 131 Active FIFO Buffer Header CRC Register (AFBCRCR) 132 Active FIFO Buffer Message Buffer Slot Status Vector Register (AFBMBSSVR) 133 Active Receive Buffer Cycle Counter and Payload Lenth Register (ARBCCPLR) 129 Active Receive Buffer Data n Register (ARBDATAnR) 130 Active Receive Buffer Frame ID Register (ARBFRID) 129 Active Receive Buffer Header CRC Register (ARBCRCR) 130 Active Receive Buffer Message Buffer Slot Status Vector Register (ARBMBSSVR) 131 Active Transmit Buffer Cycle Counter and Payload Length Register (ATBCCPLR) 127 Active Transmit Buffer Data n Register (ATBDATAnR) 128 Active Transmit Buffer Frame ID Register (ATBFRID) 126 Active Transmit Buffer Header CRC Register (ATBCRCR) 127 Active Transmit Buffer Message Buffer Slot Status Vector Register (ATBMBSSVR) 128 B Bit Duration Register (BDR) 71 Buffer Control, Configuration and Status n Register (BUFCSnR) 126 Bus Guardian Status Register (BGSR) 99 Bus Guardian Tick Register (BGTR) 87 C Channel Status Error Counter n Register (CSECnR) 102 CHI Error Register (CHIER) 109 Clock Correction Failed Counter Register (CCFCR) 113 Cluster Drift Damping Register (CDDR) 73 Cold Start Maximum Register (CSMR) 84 Current Cycle Counter Value Register (CCCVR) 94 Current Macrotick Counter Value Register (CMCVR) 94 Cycle Counter Filter n Register (CCFnR) 135 Cycle Length Register (CLR) 80 D Debug Port Control Register (DBPCR) 88 Delay Compensation Channel A Register (DCAR) 72 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 255 Index of Registers Delay Compensation Channel B Register (DCBR) 72 Delay Counter Register (DCR) 87 E Error Handling Level Register (EHLR) 113 Even Measurement channel A n Register (EMAnR) 122 Even Measurement channel B n Register (EMBnR) 123 Even Measurement Counter Register (EMCR) 124 Even Sync Frame ID n Register (ESFIDnR) 121 External Correction Control Register (ECCR) 82 External Offset Correction Register (EOCR) 81 External Rate Correction Register (ERCR) 82 F FIFO Acceptance Filter Message ID Mask Register (FAFMIDMR) 136 FIFO Acceptance Filter Message ID Value Register (FAFMIDVR) 136 FIFO Acceptance/Rejection Filter Channel Register (FAFCHR) 137 FIFO Rejection Filter Frame ID Mask Register (FRFFIDMR) 138 FIFO Rejection Filter Frame ID Value Register (FRFFIDVR) 138 FIFO Size Register (FSIZR) 125 G Global Network Management Vector n Register (GNMVnR) 96 H Host Interface and Physical Layer Pins Drive Strength Register (HIPDSR) 67 Host Interface Pins PullUp/Down Control Register (HIPPCR) 69 Host Interface Pins PullUp/Down Enable Register (HIPPER) 68 I Idle Detection Length Register (IDLR) 90 Interrupt Enable Register 0 (IER0) 103 Interrupt Status Register 0 (ISR0) 114 L Latest Dynamic Transmission Start Register (LDTSR) 78 Listen timeout with Noise Length Register (LNLR) 92 MFR4200 Data Sheet, Rev. 1 256 Freescale Semiconductor M Magic Number Register (MNR) 63 Maximum Cycle Length Deviation Register (MCLDAR) 81 Maximum Odd Cycles Without Clock Correction Fatal Register (MOCWCFR) 101 Maximum Odd Cycles Without clock Correction Passive Register (MOCWCPR) 101 Maximum Offset Correction Register (MOCR) 83 Maximum Payload Length Dynamic Register (MPLDR) 79 Maximum Rate Correction Register (MRCR) 84 Maximum Sync Frames Register (MSFR) 73 Microticks per Cycle High Register (MPCHR) 75 Microticks per Cycle Low Register (MPCLR) 74 Minislot Action Point Offset Register (MSAPOR) 77 Minislot Length Register (MSLR) 77 Module Configuration Register 0 (MCR0) 64 Module Configuration Register 1 (MCR1) 66 Module Version Register 0 (MVR0) 62 Module Version Register 1 (MVR1) 62 N Network Idle Time Configuration Register (NITCR) 80 Network Management Vector Length Register (NMVLR) 85 Nominal Macrotick Length Register (NMLR) 74 Number of Static Slots Register (NSSR) 76 O Odd Measurement channel A n Register (OMAnR) 121 Odd Measurement channel B n Register (OMBnR) 122 Odd Measurement Counter Register (OMCR) 124 Odd Sync Frame ID n Register (OSFIDnR) 120 Offset Correction Value Register (OCVR) 95 P Physical Layer Pins Drive Strength Register (PLPDSR) 68 Physical Layer Pins PullUp/Down Control Register (PLPPCR) 70 Physical Layer Pins PullUp/Down Enable Register (PLPPER) 69 Protocol State Register (PSR) 93 R Rate Correction Value Register (RCVR) 95 Receive Buffer Interrupt Vector Register (RBIVECR) 108 MFR4200 Data Sheet, Rev. 1 Freescale Semiconductor 257 Index of Registers S Slot Status Counter Condition n Register (SSCCnR) 105 Slot Status Counter Incrementation Register (SSCIR) 107 Slot Status Counter Interrupt Mask Register (SSCIMR) 107 Slot Status Counter n Register (SSCnR) 104 Slot Status n Register (SSnR) 119 Slot Status Selection n Register (SSSnR) 103 Start of Offset Correction Cycle Time Register (SOCCTR) 89 Startup Interrupt Enable Register (SIER) 100 Startup Interrupt Status Register (SISR) 118 Static Payload Length Register (SPLR) 76 Static Slot Action Point Offset Register (SSAPOR) 78 Static Slot Length Register (SSLR) 75 Symbol Window Configuration Register (SWCR) 79 Symbol Window Control Register (SWCTRLR) 90 Symbol Window Status channel A Register (SWSAR) 97 Symbol Window Status channel B Register (SWSBR) 98 Sync Frame Acceptance Filter Mask Register (SYNFAFMR) 134 Sync Frame Acceptance Filter Value Register (SYNFAFVR) 134 Sync Frame Header Register (SYNCHR) 86 Sync Frame Register (SYNCFR) 86 Sync Frame Rejection Filter Register (SYNFRFR) 135 T Timer Interrupt Configuration Register 0 Cycle Set (TICR0CS) 139 Timer Interrupt Configuration Register 0 Macrotick Offset (TICR0MO) 140 Timer Interrupt Configuration Register 1 Cycle Set (TICR1CS) 140 Timer Interrupt Configuration Register 1 Macrotick Offset (TICR1MO) 141 Transmit Buffer Interrupt Vector Register (TBIVECR) 109 Transmit Start Sequence Length Register (TSSLR) 85 V Voltage Regulator Status Register (VREGSR) 70 W Wakeup Mechanism Control Register (WMCTRLR) 91 Wakeup Symbol TX Idle Register (WUSTXIR) 91 Wakeup Symbol TX Low Register (WUSTXLR) 92 MFR4200 Data Sheet, Rev. 1 258 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MFR4200 Rev. 1 12/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. 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