MFRC630
MFRC630 and MFRC630 plus: High-performance frontend for
MIFARE and NTAG products
Rev. 5.1 — 23 June 2021
227551
1
Product data sheet
COMPANY PUBLIC
General description
MFRC630 and MFRC630 plus, the high-performance frontend for MIFARE and NTAG
products.
The MFRC630 multi-protocol NFC frontend IC supports the following operating modes:
• Read/write mode supporting ISO/IEC 14443A and MIFARE Classic
• Read/write mode supporting NTAG
The MFRC630’s internal transmitter is able to drive a reader/writer antenna designed
to communicate with ISO/IEC 14443A and MIFARE Cassic IC-based cards and
transponders without additional active circuitry. The digital module manages the complete
ISO/IEC 14443A framing and error detection functionality (parity and CRC).
The MFRC630 supports MIFARE Classic with 1K memory, MIFARE Classic with 4K
memory, MIFARE Ultralight, MIFARE Ultralight C, MIFARE Plus and MIFARE DESFire
products. The MFRC630 supports higher transfer speeds of the MIFARE product family
of up to 848 kbit/s in both directions.
The following host interfaces are supported:
• Serial Peripheral Interface (SPI)
• Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)
2
• I C-bus interface (two versions are implemented: I2C and I2CL)
The MFRC630 supports the connection of a secure access module (SAM). A dedicated
2
separate I C interface is implemented for a connection of the SAM. The SAM can be
used for high secure key storage and acts as a very performant crypto coprocessor. A
dedicated SAM is available for connection to the MFRC630.
In this document the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based
contactless card.
MFRC630
NXP Semiconductors
MFRC630 and MFRC630 plus: High-performance frontend for MIFARE and NTAG products
2
Features and benefits
• High-performance multi-protocol NFC frontend for transfer speed up to 848 kbit/s
• Supports ISO/IEC 14443 A, MIFARE Classic and NTAG
• Supports MIFARE Classic product encryption by hardware in read/write mode
Allows reading cards based on MIFARE Ultralight, MIFARE Classic with 1 kB memory ,
MIFARE Classic with 4 kB memory, MIFARE DESFire EV1, MIFARE DESFire EV2 and
MIFARE Plus ICs
• Low-power card detection
• Antenna connection with minimum number of external components
• Supported host interfaces:
– SPI up to 10 Mbit/s
2
– I C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus
– RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage
supply
2
• Separate I C-bus interface for connection of a secure access module (SAM)
• FIFO buffer with size of 512 byte for highest transaction performance
• Flexible and efficient power saving modes including hard power down, standby and
low-power card detection
• Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz crystal
• 3 V to 5.5 V power supply (MFRC63002)
2.5 V to 5.5 V power supply (MFRC63003)
• Up to 8 free programmable input/output pins
• Typical operating distance in read/write mode for communication to a ISO/IEC 14443A
and MIFARE Classic card up to 12 cm, depending on the antenna size and tuning. The
version MFRC63003 offers a more flexible configuration for Low-Power Card detection
compared to the MFRC63002 with the new register LPCD_OPTIONS. In addition, the
MFRC63003 offers new additional settings for the Load Protocol which fit very well to
smaller antennas. The MFRC63003 is therefore the recommended version for new
designs.
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Applications
• Industrial
• Access control
• Gaming
MFRC630
Product data sheet
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MFRC630 and MFRC630 plus: High-performance frontend for MIFARE and NTAG products
4
Quick reference data
Table 1. Quick reference data MFRC63002HN
Symbol
Parameter
VDD
supply voltage
VDD(PVDD)
PVDD supply voltage
VDD(TVDD)
TVDD supply voltage
Conditions
[1]
Typ
Max
Unit
3.0
5.0
5.5
V
3.0
5.0
VDD
V
3.0
5.0
5.5
V
-
8
40
nA
Ipd
power-down current
IDD
supply current
-
17
20
mA
IDD(TVDD)
TVDD supply current
-
100
250
mA
Tamb
operating ambient temperature
-25
+25
+85
°C
Tstg
storage temperature
-55
+25
+125
°C
Min
Typ
Max
Unit
2.5
5.0
5.5
V
2.5
5.0
VDD
V
2.5
5.0
5.5
V
-
8
40
nA
-
17
20
mA
recommended operation
-
180
350
mA
absolute limiting value
-
-
500
mA
[1]
[2]
PDOWN pin pulled HIGH
[2]
Min
no supply voltage applied
VDD(PVDD) must always be the same or lower voltage than VDD.
Ipd is the sum of all supply currents
Table 2. Quick reference data MFRC63003HN
Symbol
Parameter
VDD
supply voltage
VDD(PVDD)
PVDD supply voltage
VDD(TVDD)
TVDD supply voltage
Ipd
power-down current
IDD
supply current
IDD(TVDD)
TVDD supply current
Conditions
[1]
PDOWN pin pulled HIGH
[2]
Tamb
operating ambient temperature device mounted on PCB which
allows sufficient heat dissipation for
the actual power dissipation of the
device
-40
+25
+105
°C
Tstg
storage temperature
-55
+25
+125
°C
[1]
[2]
no supply voltage applied
VDD(PVDD) must always be the same or lower voltage than VDD.
Ipd is the sum of all supply currents
MFRC630
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MFRC630
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Ordering information
Table 3. Ordering information
Type number
Package
MFRC63001HN/T/R
[1]
MFRC63002HN/TRAYB
[2]
MFRC63002HN/TRAYBM
MFRC63002HN/T/R
[4]
MFRC66302HN,151
[2]
[2]
MFRC63003HN/TRAYB
[1]
MFRC63003HN/T/R
[1]
[2]
[3]
[4]
[3]
Name
Description
Version
HVQFN32
plastic thermal enhanced very thin quad flat package; no SOT617-1
leads; MSL2, 32 terminals + 1 central ground; body 5 × 5
× 0.85 mm
plastic thermal enhanced very thin quad flat package; no
leads; MSL1, 32 terminals + 1 central ground; body 5 × 5
× 0.85 mm
plastic thermal enhanced very thin quad flat package; no
leads; MSL2, 32 terminals + 1 central ground; body 5 × 5
× 0.85 mm, wettable flanks
Delivered on reel with 6000 pieces; MOQ (Minimum order quantity) : 6000 pcs
Delivered in one tray, MOQ (Minimum order quantity) : 490 pcs
Delivered in five trays: MOQ 5x490 pcs
Delivered on reel with 6000 pieces
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Block diagram
The analog interface handles the modulation and demodulation of the antenna signals for
the contactless interface.
The contactless UART manages the protocol dependency of the contactless interface
settings managed by the host.
The FIFO buffer ensures fast and convenient data transfer between host and the
contactless UART.
The register bank contains the settings for the analog and digital functionality.
REGISTER BANK
ANTENNA
ANALOG
INTERFACE
CONTACTLESS
UART
FIFO
BUFFER
SERIAL UART
SPI
I2C-BUS
HOST
001aaj627
Figure 1. Simplified block diagram of the MFRC630
MFRC630
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25 PVDD
26 IFSEL0/OUT4
27 IFSEL1/OUT5
28 IF0
29 IF1
30 IF2
terminal 1
index area
31 IF3
32 IRQ
Pinning information
TDO/OUT0
1
TDI/OUT1
2
24 SDA
TMS/OUT2
3
TCK/OUT3
4
SIGIN/OUT7
5
SIGOUT
6
19 XTAL1
DVDD
7
18 TVDD
VDD
8
17 TX1
(1)
23 SCL
22 CLKOUT/OUT6
21 PDOWN
TVSS 16
20 XTAL2
TX2 15
VMID 14
RXN 13
RXP 12
AUX2 11
AVDD
9
heatsink
AUX1 10
7
001aam004
Transparent top view
1. VSS - heatsink connection
Figure 2. Pinning configuration HVQFN32 (SOT617-1)
7.1 Pin description
Table 4. Pin description
Pin
Symbol
Type
Description
1
TDO / OUT0
O
test data output for boundary scan interface / general purpose output 0
2
TDI / OUT1
I
test data input boundary scan interface / general purpose output 1
3
TMS / OUT2
I
test mode select boundary scan interface / general purpose output 2
4
TCK / OUT3
I
test clock boundary scan interface / general purpose output 3
5
SIGIN /OUT7
I/O
Contactless communication interface output. / general purpose output 7
6
SIGOUT
O
Contactless communication interface input.
7
DVDD
PWR
digital power supply buffer
8
VDD
PWR
power supply
9
AVDD
PWR
analog power supply buffer
10
AUX1
O
auxiliary outputs: Pin is used for analog test signal
11
AUX2
O
auxiliary outputs: Pin is used for analog test signal
12
RXP
I
receiver input pin for the received RF signal.
13
RXN
I
receiver input pin for the received RF signal.
14
VMID
PWR
internal receiver reference voltage
15
TX2
O
transmitter 2: delivers the modulated 13.56 MHz carrier
16
TVSS
PWR
transmitter ground, supplies the output stage of TX1, TX2
17
TX1
O
transmitter 1: delivers the modulated 13.56 MHz carrier
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[1]
[1]
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Table 4. Pin description...continued
Pin
Symbol
Type
Description
18
TVDD
PWR
transmitter voltage supply
19
XTAL1
I
crystal oscillator input: Input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz)
20
XTAL2
O
crystal oscillator output: output of the inverting amplifier of the oscillator
21
PDOWN
I
Power Down (RESET)
22
CLKOUT / OUT6
O
clock output / general purpose output 6
23
SCL
O
Serial Clock line
24
SDA
I/O
Serial Data Line
25
PVDD
PWR
pad power supply
26
IFSEL0 / OUT4
I
host interface selection 0 / general purpose output 4
27
IFSEL1 / OUT5
I
host interface selection 1 / general purpose output 5
28
IF0
I/O
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
2
2
I C, I C-L
29
IF1
I/O
interface pin, multifunction pin: Can be assigned to host interface SPI, I C, I C-L
30
IF2
I/O
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
2
2
I C, I C-L
31
IF3
I/O
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
2
2
I C, I C-L
32
IRQ
O
interrupt request: output to signal an interrupt event
33
VSS
PWR
ground and heat sink connection
[1]
2
2
This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.
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Functional description
SAM interface
I2C,
LOGICAL
SDA
SCL
FIFO
512 Bytes
EEPROM
8 kByte
SPI
host interfaces
RESET
LOGIC
IFSEL1
IFSEL0
PDOWN
I2 C
IF0
REGISTERS
IF1
UART
IF2
STATEMACHINES
IF3
SPI
TCK
TDI
TMS
TDO
ANALOGUE FRONT-END
BOUNDARY
SCAN
VOLTAGE
REGULATOR
3/5 V =>
1.8 V
DVDD
VOLTAGE
REGULATOR
3/5 V =>
1.8 V
AVDD
POR
RNG
VDD
VSS
PVDD
TVDD
TVSS
AVDD
DVDD
TIMER0..3
INTERRUPT
CONTROLLER
IRQ
TIMER4
(WAKE-UP
TIMER)
TX
CODEC
CRC
SIGIN/
SIGOUT
CONTROL
SIGIN
RX
DECOD
CLCOPRO
SIGPRO
SIGOUT
ADC
LFO
PLL
RX
TX
OSC
RXP
VMID RXN
TX2
TX1
CLKOUT
AUX1
XTAL2
XTAL1
AUX2
001aam005
Figure 3. Detailed block diagram of the MFRC630
8.1 Interrupt controller
The interrupt controller handles the enabling/disabling of interrupt requests. All of the
interrupts can be configured by firmware. Additionally, the firmware has possibilities to
trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0
and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En
and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt
controller registers is implemented.
The MFRC630 indicates certain events by setting bit IRQ in the register Status1Reg and
additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the
host using its interrupt handling capabilities. This allows the implementation of efficient
host software.
Table 4. shows the available interrupt bits, the corresponding source and the condition
for its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, in
register IRQ1 indicate an interrupt set by the timer unit. The setting is done if the timer
underflows.
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The TxIRQ bit in register IRQ0 indicates that the transmission is finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit sets the interrupt bit automatically.
The bit RxIRQ in register IRQ0 indicates an interrupt when the end of the received data is
detected.
The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of the
command register changes to idle.
The register WaterLevel defines both - minimum and maximum warning levels - counting
from top and from bottom of the FIFO by a single value.
The bit HiAlertIRQ in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that
means the FIFO data number has reached the top level as configured by the register
WaterLevel and bit WaterLevelExtBit.
The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that
means the FIFO data number has reached the bottom level as configured by the register
WaterLevel.
The bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART
during receive. This is indicated by any bit set to logic 1 in register Error.
The bit LPCDIRQ in register IRQ0 indicates a card detected.
The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcarrier by the
contactless UART during receiving.
The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt
source when enabled.
Table 5. Interrupt sources
MFRC630
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Interrupt bit
Interrupt source
Is set automatically, when
Timer0IRQ
Timer Unit
the timer register T0 CounterVal underflows
Timer1IRQ
Timer Unit
the timer register T1 CounterVal underflows
Timer2IRQ
Timer Unit
the timer register T2 CounterVal underflows
Timer3IRQ
Timer Unit
the timer register T3 CounterVal underflows
TxIRQ
Transmitter
a transmitted data stream ends
RxIRQ
Receiver
a received data stream ends
IdleIRQ
Command Register
a command execution finishes
HiAlertIRQ
FIFO-buffer pointer
the FIFO data number has reached the top level as
configured by the register WaterLevel
LoAlertIRQ
FIFO-buffer pointer
the FIFO data number has reached the bottom level as
configured by the register WaterLevel
ErrIRQ
contactless UART
a communication error had been detected
LPCDIRQ
LPCD
a card was detected when in low-power card detection
mode
RxSOFIRQ
Receiver
detection of a SOF or a subcarrier
GlobalIRQ
all interrupt sources
will be set if another interrupt request source is set
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8.2 Timer module
Timer module overview
The MFRC630 implements five timers. Four timers -Timer0 to Timer3 - have an input
clock that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived
from the 27.12 MHz quartz) or to be the underflow event of the fifth Timer (Timer4). Each
timer implements a counter register which is 16 bit wide. A reload value for the counter
is defined in a range of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo.
The fifth timer Timer4 is intended to be used as a wakeup timer and is connected to the
internal LFO (Low Frequency Oscillator) as input clock source.
The TControl register allows the global start and stop of each of the four timers Timer0
to Timer3. Additionally, this register indicates if one of the timers is running or stopped.
Each of the five timers implements an individual configuration register set defining timer
reload value (e.g. T0ReloadHi,T0ReloadLo), the timer value (e.g. T0CounterValHi,
T0CounterValLo) and the conditions which define start, stop and clockfrequency (e.g.
T0Control).
The external host may use these timers to manage timing relevant tasks. The timer unit
may be used in one of the following configurations:
•
•
•
•
•
Time-out counter
Watch-dog counter
Stop watch
Programmable one-shot timer
Periodical trigger
The timer unit can be used to measure the time interval between two events or to
indicate that a specific event has occurred after an elapsed time. The timer register
content is modified by the timer unit, which can be used to generate an interrupt to allow
an host to react on this event.
The counter value of the timer is available in the registers T(x)CounterValHi,
T(x)CounterValLo. The content of these registers is decremented at each timer clock.
If the counter value has reached a value of 0000h and the interrupts are enabled for this
specific timer, an interrupt will be generated as soon as the next clock is received.
If enabled, the timer event can be indicated on the pin IRQ (interrupt request). The bit
Timer(x)IRQ can be set and reset by the host controller. Depending on the configuration,
the timer will stop counting at 0000h or restart with the value loaded from registers
T(x)ReloadHi, T(x)ReloadLo.
The counting of the timer is indicated by bit TControl.T(x)Running.
The timer can be started by setting bits TControl.T(x)Running and
TControl.T(x)StartStopNow or stopped by setting the bits TControl.T(x)StartStopNow and
clearing TControl.T(x)Running.
Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start, this can be useful
if dedicated protocol requirements need to be fulfilled.
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8.2.1 Timer modes
8.2.1.1 Time-Out- and Watch-Dog-Counter
Having configured the timer by setting register T(x)ReloadValue and starting the counting
of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit
decrements the T(x)CounterValue Register beginning with the configured start event. If
the configured stop event occurs before the Timer(x) underflows (e.g. a bit is received
from the card), the timer unit stops (no interrupt is generated).
If no stop event occurs, the timer unit continues to decrement the counter registers
until the content is zero and generates a timer interrupt request at the next clock cycle.
This allows to indicate to a host that the event did not occur during the configured time
interval.
8.2.1.2 Wake-up timer
The wake-up Timer4 allows to wakeup the system from standby after a predefined time.
The system can be configured in such a way that it is entering the standby mode again in
case no card had been detected.
This functionality can be used to implement a low-power card detection (LPCD). For
the low-power card detection it is recommended to set T4Control.T4AutoWakeUp and
T4Control.T4AutoRestart, to activate the Timer4 and automatically set the system
in standby. The internal low frequency oscillator (LFO) is then used as input clock
for this Timer4. If a card is detected the host-communication can be started. If bit
T4Control.T4AutoWakeUp is not set, the MFRC630 will not enter the standby mode
again in case no card is detected but stays fully powered.
8.2.1.3 Stop watch
The elapsed time between a configured start- and stop event may be measured by the
MFRC630 timer unit. By setting the registers T(x)ReloadValueHi, T(x)reloadValueLo the
timer starts to decrement as soon as activated. If the configured stop event occurs, the
timers stops decrementing. The elapsed time between start and stop event can then be
calculated by the host dependent on the timer interval TTimer:
(1)
If an underflow occurred which can be identified by evaluating the corresponding IRQ bit,
the performed time measurement according to the formula above is not correct.
8.2.1.4 Programmable one-shot timer
The host configures the interrupt and the timer, starts the timer and waits for the interrupt
event on pin IRQ. After the configured time the interrupt request will be raised.
8.2.1.5 Periodical trigger
If the bit T(x)Control.T(x)AutoRestart is set and the interrupt is activated, an interrupt
request will be indicated periodically after every elapsed timer period.
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8.3 Contactless interface unit
The contactless interface unit of the MFRC630 supports the following read/write
operating modes:
• ISO/IEC14443 type A and MIFARE Classic
BATTERY/POWER SUPPLY
READER IC
ISO/IEC 14443 A CARD
MICROCONTROLLER
reader/writer
001aal996
Figure 4. Read/write mode
A typical system using the MFRC630 is using a microcontroller to implement the higher
levels of the contactless communication protocol and a power supply (battery or external
supply).
8.3.1 Communication mode for ISO/IEC 14443 type A and for MIFARE Classic
The physical level of the communication is shown in Figure 5.
(1)
ISO/IEC 14443 A
READER
(2)
ISO/IEC 14443 A CARD
001aam268
1. Reader to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s
2. Card to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106
kbit/s to 848 kbit/s
Figure 5. Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE
Classic
The physical parameters are described in Table 5.
Table 6. Communication overview for ISO/IEC 14443 type A and read/write mode for MIFARE Classic
Communication
direction
Signal type
Reader to card
(send data from the
MFRC630 to a card)
fc = 13.56 MHz
Card to reader
(MFRC630 receives
data from a card)
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Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
reader side
modulation
100 % ASK
100% ASK
100% ASK
100% ASK
bit encoding
modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
bit rate [kbit/s]
fc / 128
fc / 64
fc / 32
fc / 16
card side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
fc / 16
fc / 16
fc / 16
fc / 16
bit encoding
Manchester
encoding
BPSK
BPSK
BPSK
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The MFRC630 connection to a host is required to manage the complete ISO/IEC 14443
type A and MIFARE Classic communication protocol. Figure 6 shows the data coding and
framing according to ISO/IEC 14443 type A and MIFARE Classic.
ISO/IEC 14443 A framing at 106 kBd
start
8-bit data
8-bit data
8-bit data
odd
parity
start bit is 1
odd
parity
odd
parity
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
start
even
parity
8-bit data
8-bit data
8-bit data
odd
parity
start bit is 0
odd
parity
burst of 32
subcarrier clocks
even parity at the
end of the frame
001aak585
Figure 6. Data coding and framing according to ISO/IEC 14443 A
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part
3 and handles parity generation internally according to the transfer speed.
8.4 Host interfaces
8.4.1 Host interface configuration
2
2
The MFRC630 supports direct interfacing of various hosts as the SPI, I C, I CL and
serial UART interface type. The MFRC630 resets its interface and checks the current
host interface type automatically having performed a power-up or resuming from power
down. The MFRC630 identifies the host interface by the means of the logic levels on
the control pins after the Cold Reset Phase. This is done by a combination of fixed
pin connections.The following table shows the possible configurations defined by
IFSEL1,IFSEL0:
Table 7. Connection scheme for detecting the different interface types
MFRC630
Product data sheet
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2
2
Pin
Pin Symbol
UART
SPI
I C
I C-L
28
IF0
RX
MOSI
ADR1
ADR1
29
IF1
n.c.
SCK
SCL
SCL
30
IF2
TX
MISO
ADR2
SDA
31
IF3
PAD_VDD
NSS
SDA
ADR2
26
IFSEL0
VSS
VSS
PAD_VDD
PAD_VDD
27
IFSEL1
VSS
PAD_VDD
VSS
PAD_VDD
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8.4.2 SPI interface
8.4.2.1 General
READER IC
SCK
IF1
MOSI
IF0
MISO
IF2
NSS
IF3
001aal998
Figure 7. Connection to host with SPI
The MFRC630 acts as a slave during the SPI communication. The SPI clock SCK has to
be generated by the master. Data communication from the master to the slave uses the
Line MOSI. Line MISO is used to send data back from the MFRC630 to the master.
A serial peripheral interface (SPI compatible) is supported to enable high speed
communication to a host. The implemented SPI compatible interface is according to a
standard SPI interface. The SPI compatible interface can handle data speed of up to
10 Mbit/s. In the communication with a host MFRC630 acts as a slave receiving data
from the external host for register settings and to send and receive data relevant for the
communication on the RF interface.
NSS (Not Slave Select) enables or disables the SPI interface. When NSS is logical high,
the interface is disabled and reset. Between every SPI command the NSS must go to
logical high to be able to start the next command read or write.
On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI
line shall be stable on rising edge of the clock line (SCK) and is allowed to change on
falling edge. The same is valid for the MISO line. Data is provided by the MFRC630 on
the falling edge and is stable on the rising edge.The polarity of the clock is low at SPI
idle.
8.4.2.2 Read data
To read out data from the MFRC630 by using the SPI compatible interface the following
byte order has to be used.
The first byte that is sent defines the mode (LSB bit) and the address.
Table 8. Byte Order for MOSI and MISO
byte 0
byte 1
byte 2
byte 3 to n-1 byte n
byte n+1
MOSI
address 0
address 1
address 2
……..
address n
00h
MISO
X
data 0
data 1
……..
data n - 1
data n
Remark: The Most Significant Bit (MSB) has to be sent first.
8.4.2.3 Write data
To write data to the MFRC630 using the SPI interface the following byte order has to
be used. It is possible to write more than one byte by sending a single address byte
(see.8.5.2.4).
MFRC630
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The first send byte defines both, the mode itself and the address byte.
Table 9. Byte Order for MOSI and MISO
byte 0
byte 1
byte 2
3 to n-1
byte n
byte n + 1
MOSI
address 0
data 0
data 1
……..
data n - 1
data n
MISO
X
X
X
……..
X
X
Remark: The Most Significant Bit (MSB) has to be sent first.
8.4.2.4 Address byte
The address byte has to fulfil the following format:
The LSB bit of the first byte defines the used mode. To read data from the MFRC630 the
LSB bit is set to logic 1. To write data to the MFRC630 the LSB bit has to be cleared. The
bits 6 to 0 define the address byte.
NOTE: When writing the sequence [address byte][data0][data1][data2]..., [data0] is
written to address [address byte], [data1] is written to address [address byte + 1] and
[data2] is written to [address byte + 2].
Exception: This auto increment of the address byte is not performed if data is written to
the FIFO address
Table 10. Address byte 0 register; address MOSI
7
6
5
4
3
2
1
0
address 6
address 5
address 4
address 3
address 2
address 1
address 0
1 (read)
0 (write)
MSB
LSB
8.4.2.5 Timing Specification SPI
The timing condition for SPI interface is as follows:
Table 11. Timing conditions SPI
MFRC630
Product data sheet
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Symbol
Parameter
Min
Typ
Max
Unit
tSCKL
SCK LOW time
50
-
-
ns
tSCKH
SCK HIGH time
50
-
-
ns
th(SCKH-D)
SCK HIGH to data input hold time
25
-
-
ns
tsu(D-SCKH)
data input to SCK HIGH set-up time
25
-
-
ns
th(SCKL-Q)
SCK LOW to data output hold time
-
-
25
ns
t(SCKL-NSSH)
SCK LOW to NSS HIGH time
0
-
-
ns
tNSSH
NSS HIGH time
50
-
-
ns
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tNSSH
tSCKL
tSCKH
tSCKL
SCK
th(SCKL-Q)
tsu(D-SCKH)
th(SCKH-D)
MOSI
MSB
LSB
MISO
MSB
LSB
t(SCKL-NSSH)
NSS
aaa-016093
Figure 8. Connection to host with SPI
Remark: To send more bytes in one data stream the NSS signal must be LOW during
the send process. To send more than one data stream the NSS signal must be HIGH
between each data stream.
8.4.3 RS232 interface
8.4.3.1 Selection of the transfer speeds
The internal UART interface is compatible to a RS232 serial interface. The levels
supplied to the pins are between VSS and PVDD. To achieve full compatibility of the
voltage levels to the RS232 specification, a RS232 level shifter is required.
Table 12 "Selectable transfer speeds" describes examples for different transfer speeds
and relevant register settings. The resulting transfer speed error is less than 1.5 % for all
described transfer speeds. The default transfer speed is 115.2 kbit/s.
To change the transfer speed, the host controller has to write a value for the new transfer
speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set
the transfer speed in the SerialSpeedReg.
Table 11 "Settings of BR_T0 and BR_T1" describes the settings of BR_T0 and BR_T1.
Table 12. Settings of BR_T0 and BR_T1
BR_T0
0
1
2
3
4
5
6
7
factor BR_T0
1
1
2
4
8
16
32
64
range BR_T1
1 to 32
33 to 64
33 to 64
33 to 64
33 to 64
33 to 64
33 to 64
33 to 64
Table 13. Selectable transfer speeds
Transfer speed (kbit/s)
Serial SpeedReg
Transfer speed accuracy (%)
(Hex.)
MFRC630
Product data sheet
COMPANY PUBLIC
7.2
FA
-0.25
9.6
EB
0.32
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Table 13. Selectable transfer speeds...continued
Transfer speed (kbit/s)
Serial SpeedReg
Transfer speed accuracy (%)
(Hex.)
14.4
DA
-0.25
19.2
CB
0.32
38.4
AB
0.32
57.6
9A
-0.25
115.2
7A
-0.25
128
74
-0.06
230.4
5A
-0.25
460.8
3A
-0.25
921.6
1C
1.45
1228.8
15
0.32
The selectable transfer speeds as shown are calculated according to the following
formulas:
if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
(BR_T0 - 1)
if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2
Remark: Transfer speeds above 1228.8 kBits/s are not supported.
8.4.3.2 Framing
Table 14. UART framing
Bit
Length
Value
Start bit (Sa)
1 bit
0
Data bits
8 bit
Data
Stop bit (So)
1 bit
1
Remark: For data and address bytes the LSB bit has to be sent first. No parity bit is
used during transmission.
Read data: To read out data using the UART interface the flow described below has to
be used. The first send byte defines both the mode itself and the address.The Trigger on
pin IF3 has to be set, otherwise no read of data is possible.
Table 15. Byte Order to Read Data
MFRC630
Product data sheet
COMPANY PUBLIC
Mode
byte 0
byte 1
RX
address
-
TX
-
data 0
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ADDRESS
RX
Sa
A0
A1
A2
A3
A4
A5
A6
RD/
NWR
So
DATA
TX
Sa
D0
D1
D2
D3
D4
D5
D6
D7
So
001aam298
Figure 9. Example for UART Read
Write data:
To write data to the MFRC630 using the UART interface the following sequence has to
be used.
The first send byte defines both, the mode itself and the address.
Table 16. Byte Order to Write Data
Mode
byte 0
byte 1
RX
address 0
data 0
TX
address 0
ADDRESS
RX
Sa
A0
A1
A2
A3
A4
DATA
A5
A6
RD/
NWR
So
Sa
D0
RD/
NWR
So
D1
D2
D3
D4
D5
D6
D7
So
ADDRESS
TX
Sa
A0
A1
A2
A3
A4
A5
A6
001aam299
Figure 10. Example diagram for a UART write
Remark: Data can be sent before address is received.
2
8.4.4 I C-bus interface
8.4.4.1 General
2
An Inter IC (I C) bus interface is supported to enable a low cost, low pin count serial bus
2
interface to the host. The implemented I C interface is mainly implemented according the
2
NXP Semiconductors I C interface specification, rev. 3.0, June 2007. The MFRC630 can
MFRC630
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act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode
plus.
2
The following features defined by the NXP Semiconductors I C interface specification,
rev. 3.0, June 2007 are not supported:
• The MFRC630 I2C interface does not stretch the clock
• The MFRC630 I2C interface does not support the general call. This means that the
MFRC630 does not support a software reset
• The MFRC630 does not support the I2C device ID
• The implemented interface can only act in slave mode. Therefore no clock generation
and access arbitration is implemented in the MFRC630.
• High speed mode is not supported by the MFRC630
PULL-UP
NETWORK
PULL-UP
NETWORK
MICROCONTROLLER
READER IC
SDA
SCL
001aam000
2
Figure 11. I C-bus interface
The voltage level on the I2C pins is not allowed to be higher than PVDD.
SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.
2
Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the I Cbus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in the
fast mode+.
2
2
If the I C interface is selected, a spike suppression according to the I C interface
specification on SCL and SDA is automatically activated.
2
For timing requirements refer to Table 196 "I C-bus timing in fast mode and fast mode
plus"
2
8.4.4.2 I C Data validity
Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state
or LOW state of the data line shall only change when the clock signal on SCL is LOW.
SDA
SCL
data line stable;
data valid
change
of data
allowed
001aam300
2
Figure 12. Bit transfer on the I C-bus.
2
8.4.4.3 I C START and STOP conditions
2
To handle the data transfer on the I C-bus, unique START (S) and STOP (P) conditions
are defined.
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A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL
is HIGH.
A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is
HIGH.
The master always generates the START and STOP conditions. The bus is considered to
be busy after the START condition. The bus is considered to be free again a certain time
after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.
In this respect, the START (S) and repeated START (Sr) conditions are functionally
identical. Therefore, the S symbol will be used as a generic term to represent both the
START and repeated START (Sr) conditions.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
001aam301
Figure 13. START and STOP conditions
2
8.4.4.4 I C byte format
Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB
first, see Figure 13 "START and STOP conditions". The number of transmitted bytes
during one data transfer is unrestricted but shall fulfil the read/write cycle format.
2
8.4.4.5 I C Acknowledge
An acknowledge at the end of one data byte is mandatory. The acknowledge-related
clock pulse is generated by the master. The transmitter of data, either master or slave,
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull
down the SDA line during the acknowledge clock pulse so that it remains stable LOW
during the HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not
generating an acknowledge on the last byte that was clocked out by the slave. The slavetransmitter shall release the data line to allow the master to generate a STOP (P) or
repeated START (Sr) condition.
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DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVERER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
001aam302
2
Figure 14. Acknowledge on the I C- bus
P
MSB
acknowledgement
signal from slave
acknowledgement
signal from receiver
Sr
byte complete,
interrupt within slave
clock line held low while
interrupts are serviced
S
or
Sr
1
2
7
8
9
1
2
3-8
ACK
9
ACK
Sr
or
P
001aam303
2
Figure 15. Data transfer on the I C- bus
2
8.4.4.6 I C 7-bit addressing
2
During the I C-bus addressing procedure, the first byte after the START condition is used
to determine which slave will be selected by the master.
2
Alternatively the I C address can be configured in the EEPROM. Several address
numbers are reserved for this purpose. During device configuration, the designer has to
ensure, that no collision with these reserved addresses in the system is possible. Check
2
the corresponding I C specification for a complete list of reserved addresses.
For all MFRC630 devices the upper 5 bits of the device bus address are reserved by
NXP and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address
2
can be freely configured by the customer in order to prevent collisions with other I C
2
devices by using the interface pins (refer to Table 6) or the value of the I C address
EEPROM register (refer to Table 28).
MSB
Bit 6
LSB
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
slave address
Bit 0
R/W
001aam304
Figure 16. First byte following the START procedure
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2
8.4.4.7 I C-register write access
2
To write data from the host controller via I C to a specific register of the MFRC630 the
following frame format shall be used.
The read/write bit shall be set to logic 0.
2
The first byte of a frame indicates the device address according to the I C rules. The
second byte indicates the register address followed by up to n-data bytes. In case the
address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register
address. This enables for example a fast FIFO access.
2
8.4.4.8 I C-register read access
To read out data from a specific register address of the MFRC630 the host controller
shall use the procedure:
First a write access to the specific register address has to be performed as indicated in
the following frame:
2
The first byte of a frame indicates the device address according to the I C rules. The
second byte indicates the register address. No data bytes are added.
The read/write bit shall be logic 0.
Having performed this write access, the read access starts. The host sends the device
address of the MFRC630. As an answer to this device address the MFRC630 responds
with the content of the addressed register. In one frame n-data bytes could be read
using the same register address. The address pointing to the register is incremented
automatically (exception: FIFO register address is not incremented automatically).
This enables a fast transfer of register content. The address pointer is incremented
automatically and data is read from the locations [address], [address+1], [address+2]...
[address+(n-1)]
In order to support a fast FIFO data transfer, the address pointer is not incremented
automatically in case the address is pointing to the FIFO.
The read/write bit shall be set to logic 1.
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Write Cycle
I2C slave address
A7-A0
SA
0
(W)
Ack
Frontend IC register
address A6-A0
0
Ack
DATA
[7..0]
[0..n]
Ack
SO
Read Cycle
I2C slave address
A7-A0
SA
0
(W)
Ack
0
Frontend IC register
address A6-A0
Ack
SO
Optional, if the previous access was on the same register address
0..n
1
(R)
I2C slave address
A7-A0
SA
Ack
[0..n]
sent by master
DATA
[7..0]
Ack
DATA
[7..0]
Nack
SO
sent by slave
001aam305
Figure 17. Register read and write access
2
8.4.4.9 I CL-bus interface
The MFRC630 provides an additional interface option for connection of a SAM. This
2
logical interface fulfills the I C specification, but the rise/fall timings will not be compliant
2
2
to the I C standard. The I CL interface uses standard I/O pads, and the communication
speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of
2
I C. The SCL levels are generated by the host in push/pull mode. The MFRC630 does
not stretch the clock. During the high period of SCL the status of the line is maintained by
a bus keeper.
The address is 01010xxb, where the last two bits of the address can be defined by the
application. The definition of this bits can be done by two options. With a pin, where the
higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the
EEPROM configuration in Section 7.7.
2
Table 17. Timing parameter I CL
MFRC630
Product data sheet
COMPANY PUBLIC
Parameter
Min
Max
Unit
fSCL
0
5
MHz
tHD;STA
80
-
ns
tLOW
100
-
ns
tHIGH
100
-
ns
tSU;SDA
80
-
ns
tHD;DAT
0
50
ns
tSU;DAT
0
20
ns
tSU;STO
80
-
ns
tBUF
200
-
ns
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2
The pull-up resistor is not required for the I CL interface. Instead, a on chip buskeeper
2
is implemented in the MFRC630 for SDA of the I CL interface. This protocol is intended
to be used for a point to point connection of devices over a short distance and does
not support a bus capability.The driver of the pin must force the line to the desired
logic voltage. To avoid that two drivers are pushing the line at the same time following
regulations must be fulfilled:
SCL: As there is no clock stretching, the SCL is always under control of the Master.
SDA: The SDA line is shared between master and slave. Therefore the master and the
slave must have the control over the own driver enable line of the SDA pin. The following
rules must be followed:
• In the idle phase the SDA line is driven high by the master
• In the time between start and stop condition the SDA line is driven by master or slave
when SCL is low. If SCL is high the SDA line is not driven by any device
• To keep the value on the SDA line a on chip buskeeper structure is implemented for the
line
8.4.5 SAM interface
8.4.5.1 SAM functionality
The MFRC630 implements a dedicated I2C or SPI interface to integrate a MIFARE SAM
(Secure Access Module) in a very convenient way into applications (e.g. a proximity
reader).
The SAM can be connected to the microcontroller to operate like a cryptographic coprocessor. For any cryptographic task, the microcontroller requests a operation from the
SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface to
the connected reader IC.
The MIFARE SAM supports a optimized method to integrate the SAM in a very efficient
way to reduce the protocol overhead. In this system configuration, the SAM is integrated
between the microprocessor and the reader IC, connected by one interface to the reader
IC and by another interface to the microcontroller. In this application the microcontroller
accesses the SAM using the T=1 protocol and the SAM accesses the reader IC using
an I2C interface. The I2C SAM address is always defined by EEPROM register.
Default value is 0101100. As the SAM is directly communicating with reader IC, the
communication overhead is reduced. In this configuration, a performance boost of up to
40% can be achieved for a transaction time.
The MIFARE SAM supports applications using MIFARE product-based cards. For multi
application purposes an architecture connecting the microcontroller additionally directly
to the reader IC is recommended. This is possible by connecting the MFRC630 on
one interface (SAM Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/
T1AR1070) and by connecting the microcontroller to the S2C or SPI interface.
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T=1
µC
SAM
AV2.6
I2C
READER
IC
I2C
Reader
aaa-002963
Figure 18. I2C interface enables convenient MIFARE SAM integration
8.4.5.2 SAM connection
The MFRC630 provides an interface to connect a SAM dedicated to the MFRC630. Both
2
2
interface options of the MFRC630, I C, I CL or SPI can be used for this purpose. The
interface option of the SAM itself is configured by a host command sent from the host to
the SAM.
2
The I CL interface is intended to be used as connection between two IC’s over a short
2
distance. The protocol fulfills the I C specification, but does support a single device
connected to the bus only.
The SPI block for SAM connection is identical with the SPI host interface block.
The pins used for the SAM SPI are described in Table 17.
Table 18. SPI SAM connection
SPI functionality
PIN
MISO
SDA2
SCL
SCL2
MOSI
IFSEL1
NSS
IFSEL0
8.4.6 Boundary scan interface
The MFRC630 provides a boundary scan interface according to the IEEE 1149.1. This
interface allows to test interconnections without using physical test probes. This is done
by test cells, assigned to each pin, which override the functionality of this pin.
To be able to program the test cells, the following commands are supported:
Table 19. Boundary scan command
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Value
(decimal)
Command
Parameter in
Parameter out
0
bypass
-
-
1
preload
data (24)
-
1
sample
-
data (24)
2
ID code (default)
-
data (32)
3
USER code
-
data (32)
4
Clamp
-
-
5
HIGH Z
-
-
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Table 19. Boundary scan command...continued
Value
(decimal)
Command
Parameter in
Parameter out
7
extest
data (24)
data (24)
8
interface on/off
interface (1)
-
9
register access read
address (7)
data (8)
10
register access write
address (7) - data (8)
-
The Standard IEEE 1149.1 describes the four basic blocks necessary to use this
interface: Test Access Port (TAP), TAP controller, TAP instruction register, TAP data
register;
8.4.6.1 Interface signals
The boundary scan interface implements a four line interface between the chip and the
environment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test
Data Input (TDI) and one output Test Data Output (TDO). TCK and TMS are broadcast
signals, TDI to TDO generate a serial line called Scan path.
Advantage of this technique is that independent of the numbers of boundary scan
devices the complete path can be handled with four signal lines.
The signals TCK, TMS are directly connected with the boundary scan controller. Because
these signals are responsible for the mode of the chip, all boundary scan devices in one
scan path will be in the same boundary scan mode.
8.4.6.2 Test Clock (TCK)
The TCK pin is the input clock for the module. If this clock is provided, the test logic
is able to operate independent of any other system clocks. In addition, it ensures that
multiple boundary scan controllers that are daisy-chained together can synchronously
communicate serial test data between components. During normal operation, TCK
is driven by a free-running clock. When necessary, TCK can be stopped at 0 or 1 for
extended periods of time. While TCK is stopped at 0 or 1, the state of the boundary scan
controller does not change and data in the Instruction and Data Registers is not lost.
The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking
occurs if the pin is not driven from an external source.
8.4.6.3 Test Mode Select (TMS)
The TMS pin selects the next state of the boundary scan controller. TMS is sampled on
the rising edge of TCK. Depending on the current boundary scan state and the sampled
value of TMS, the next state is entered. Because the TMS pin is sampled on the rising
edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the
falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the boundary scan controller
state machine to the Test-Logic-Reset state. When the boundary scan controller enters
the Test-Logic-Reset state, the Instruction Register (IR) resets to the default instruction,
IDCODE. Therefore, this sequence can be used as a reset mechanism.
The internal pull-up resistor on the TMS pin is enabled.
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8.4.6.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains.
TDI is sampled on the rising edge of TCK and, depending on the current TAP state and
the current instruction, presents this data to the proper shift register chain. Because the
TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TDI to change on the falling edge of TCK.
The internal pull-up resistor on the TDI pin is enabled.
8.4.6.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the
DR chains. The value of TDO depends on the current TAP state, the current instruction,
and the data in the chain being accessed. In order to save power when the port is not
being used, the TDO pin is placed in an inactive drive state when not actively shifting out
data. Because TDO can be connected to the TDI of another controller in a daisy-chain
configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the
falling edge of TCK.
8.4.6.6 Data register
According to the IEEE1149.1 standard there are two types of data register defined:
bypass and boundary scan
The bypass register enable the possibility to bypass a device when part of the scan
path.Serial data is allowed to be transferred through a device from the TDI pin to the
TDO pin without affecting the operation of the device.
The boundary scan register is the scan-chain of the boundary cells. The size of this
register is dependent on the command.
8.4.6.7 Boundary scan cell
The boundary scan cell opens the possibility to control a hardware pin independent of its
normal use case. Basically the cell can only do one of the following: control, output and
input.
TDI
TAP
TCK
IC2
LOGIC
Boundary scan cell
LOGIC
IC1
TDO
TDI
TMS
TDO
TAP
TCK
TMS
001aam306
Figure 19. Boundary scan cell path structure
8.4.6.8 Boundary scan path
This chapter shows the boundary scan path of the MFRC630.
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Table 20. Boundary scan path of the MFRC630
Number (decimal)
Cell
Port
Function
23
BC_1
-
Control
22
BC_8
CLKOUT
Bidir
21
BC_1
-
Control
20
BC_8
SCL2
Bidir
19
BC_1
-
Control
18
BC_8
SDA2
Bidir
17
BC_1
-
Control
16
BC_8
IFSEL0
Bidir
15
BC_1
-
Control
14
BC_8
IFSEL1
Bidir
13
BC_1
-
Control
12
BC_8
IF0
Bidir
11
BC_1
-
Control
10
BC_8
IF1
Bidir
9
BC_1
-
Control
8
BC_8
IF2
Bidir
7
BC_1
IF2
Output2
6
BC_4
IF3
Input
5
BC_1
-
Control
4
BC_8
IRQ
Bidir
3
BC_1
-
Control
2
BC_8
SIGIN
Bidir
1
BC_1
-
Control
0
BC_8
SIGOUT
Bidir
Refer to the CLRC663 BSDL file.
8.4.6.9 Boundary Scan Description Language (BSDL)
All of the boundary scan devices have a unique boundary structure which is necessary to
know for operating the device. Important components of this language are:
•
•
•
•
•
available test bus signal
compliance pins
command register
data register
boundary scan structure (number and types of the cells, their function and the
connection to the pins.)
2
The MFRC630 is using the cell BC_8 for the IO-Lines. The I C Pin is using a BC_4 cell.
For all pad enable lines the cell BC1 is used.
The manufacturer's identification is 02Bh.
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•
•
•
•
attribute IDCODEISTER of MFRC630: entity is "0001" and -- version
"0011110010000010b" and -- part number (3C82h)
"00000010101b" and -- manufacturer (02Bh)
"1b"; -- mandatory
The user code data is coded as followed:
• product ID (3 bytes)
• version
These four bytes are stored as the first four bytes in the EEPROM.
8.4.6.10 Non-IEEE1149.1 commands
Interface on/off
With this command the host/SAM interface can be deactivated and the Read and Write
command of the boundary scan interface is activated. (Data = 1). With Update-DR the
value is taken over.
Register Access Read
At Capture-DR the actual address is read and stored in the DR. Shifting the DR is shifting
in a new address. With Update-DR this address is taken over into the actual address.
Register Access Write
At the Capture-DR the address and the data is taken over from the DR. The data is
copied into the internal register at the given address.
8.5
Buffer
8.5.1 Overview
An 512 × 8-bit FIFO buffer is implemented in the MFRC630. It buffers the input and
output data stream between the host and the internal state machine of the MFRC630.
Thus, it is possible to handle data streams with lengths of up to 512 bytes without taking
timing constraints into account. The FIFO can also be limited to a size of 255 byte. In
this case all the parameters (FIFO length, Watermark...) require a single byte only for
definition. In case of a 512 byte FIFO length the definition of this values requires 2 bytes.
8.5.2 Accessing the FIFO buffer
When the μ-Controller starts a command, the MFRC630 may, while the command is in
progress, access the FIFO-buffer according to that command. Physically only one FIFObuffer is implemented, which can be used in input and output direction. Therefore the μController has to take care, not to access the FIFO buffer in a way that corrupts the FIFO
data.
8.5.3 Controlling the FIFO buffer
Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might be
reset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits
are set to logic 0, the actually stored bytes are not accessible any more and the FIFO
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buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1)
again.
8.5.4 Status Information about the FIFO buffer
The host may obtain the following data about the FIFO-buffers status:
• Number of bytes already stored in the FIFO-buffer. Writing increments, reading
decrements the FIFO level: FIFOLength in register FIFOLength (and FIFOControl
Register in 512 byte mode)
• Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according
to the value of the water level in register WaterLevel (Register 02h bit [2], Register 03h
bit[7:0])
• Warning, that the FIFO-buffer is almost empty: LoAlert in register FIFOControl
according to the value of the water level in register WaterLevel (Register 02h bit [2],
Register 03h bit[7:0])
• FIFOOvl bit indicates, that bytes were written to the FIFO buffer although it was already
full: ErrIRQ in register IRQ0.
WaterLevel is one single value defining both HiAlert (counting from the FIFO top) and
LoAlert (counting from the FIFO bottom). The MFRC630 can generate an interrupt signal
if:
• LoAlertIRQEn in register IRQ0En is set to logic 1 it will activate pin IRQ when LoAlert in
the register FIFOControl changes to 1.
• HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert in
the register FIFOControl changes to 1.
The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register
WaterLevel) or less can be stored in the FIFO-buffer. It is generated according to the
following equation:
(2)
The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or less
are actually stored in the FIFO-buffer. It is generated according to the following equation:
(3)
8.6 Analog interface and contactless UART
8.6.1 General
The integrated contactless UART supports the external host online with framing and
error checking of the protocol requirements up to 848 kbit/s. An external circuit can be
connected to the communication interface pins SIGIN and SIGOUT to modulate and
demodulate the data.
The contactless UART handles the protocol requirements for the communication
schemes in co-operation with the host. The protocol handling itself generates bit- and
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byte-oriented framing and handles error detection like Parity and CRC according to the
different contactless communication schemes.
The size, the tuning of the antenna, and the supply voltage of the output drivers have an
impact on the achievable field strength. The operating distance between reader and card
depends additionally on the type of card used.
8.6.2 TX transmitter
The signal delivered on pin TX1 and pin TX2 is the 13.56 MHz carrier modulated by an
envelope signal for energy and data transmission. It can be used to drive an antenna
directly, using a few passive components for matching and filtering, see Section 13
"Application information". The signal on TX1 and TX2 can be configured by the register
DrvMode, see Section 9.9.1 "DrvMode".
The modulation index can be set by the TxAmp.
Following figure shows the general relations during modulation
influenced by set_clk_mode
envelope
TX ASK100
TX ASK10
(1)
(2)
time
1: Defined by set_cw_amplitude.
2: Defined by set_residual_carrier.
001aan355
Figure 20. General dependences of modulation
Note: When changing the continuous carrier amplitude, the residual carrier amplitude
also changes, while the modulation index remains the same.
The registers Section 8.8 and Section 8.10 control the data rate, the framing during
transmission and the setting of the antenna driver to support the requirements at the
different specified modes and transfer speeds.
Table 21. Settings for TX1 and TX2
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TxClkMode
(binary)
Tx1 and TX2 output
Remarks
000
High impedance
-
001
0
output pulled to 0 in any case
010
1
output pulled to 1 in any case
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Table 21. Settings for TX1 and TX2...continued
TxClkMode
(binary)
Tx1 and TX2 output
Remarks
110
RF high side push
open drain, only high side (push) MOS supplied
with clock, clock parity defined by invtx; low
side MOS is off
101
RF low side pull
open drain, only low side (pull) MOS supplied
with clock, clock parity defined by invtx; high
side MOS is off
111
13.56 MHz clock derived
from 27.12 MHz quartz
divided by 2
push/pull Operation, clock polarity defined by
invtx; setting for 10% modulation
Register TXamp and the bits for set_residual_carrier define the modulation index:
Table 22. Setting residual carrier and modulation index by
TXamp.set_residual_carrier
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set_residual_carrier (decimal) residual carrier [%]
modulation index [%]
0
99
0.5
1
98
1.0
2
96
2.0
3
94
3.1
4
91
4.7
5
89
5.8
6
87
7.0
7
86
7.5
8
85
8.1
9
84
8.7
10
83
9.3
11
82
9.9
12
81
10.5
13
80
11.1
14
79
11.7
15
78
12.4
16
77
13.0
17
76
13.6
18
75
14.3
19
74
14.9
20
72
16.3
21
70
17.6
22
68
19.0
23
65
21.2
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Table 22. Setting residual carrier and modulation index by
TXamp.set_residual_carrier...continued
set_residual_carrier (decimal) residual carrier [%]
modulation index [%]
24
60
25.0
25
55
29.0
26
50
33.3
27
45
37.9
28
40
42.9
29
35
48.1
30
30
53.8
31
25
60.0
Note: At VDD(TVDD) 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)
The framing is implemented with 1 startbit, 8 databits and 1 stop bit. A parity bit is not
used. Transfer speeds above 1228,8 kbit/s are not supported.
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Table 161. SerialSpeed register (address3Bh); reset value: 7Ah
Bit
7
6
5
4
3
2
Symbol
BR_T0
BR_T1
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Table 162. SerialSpeed bits
Bit
Symbol
Description
7 to 5 BR_T0
BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)
4 to 0 BR_T1
BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)
Table 163. RS232 speed settings
Transfer speed (kbit/s)
SerialSpeed register content (Hex.)
7,2
FA
9,6
EB
14,4
DA
19,2
CB
38,4
AB
57,6
9A
115,2
7A
128,0
74
230,4
5A
460,8
3A
921,6
1C
1228,8
15
9.14.2 LFO_Trimm
Table 164. LFO_Trim register (address 3Ch)
Bit
7
6
5
4
3
Symbol
LFO_trimm
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Table 165. LFO_Trim bits
Bit
Symbol
Description
7 to 0
LFO_trimm
Trimm value. Refer to Section 8.8.3
Note: If the trimm value is increased, the frequency of the oscillator
decreases.
9.14.3 PLL_Ctrl Register
The PLL_Ctrl register implements the control register for the IntegerN PLL. Two stages
exist to create the ClkOut signal from the 27,12MHz input. In the first stage the 27,12Mhz
input signal is multiplied by the value defined in PLLDiv_FB and divided by two, and the
second stage divides this frequency by the value defined by PLLDIV_Out.
Table 166. PLL_Ctrl register (address3Dh)
Bit
7
6
5
4
3
2
1
0
Symbol
ClkOutSel
ClkOut_En
PLL_PD
PLLDiv_FB
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Table 167. PLL_Ctrl register bits
Bit
Symbol
Description
7 to 4
CLkOutSel
•
•
•
•
•
•
•
•
•
•
•
•
•
3
ClkOut_En
Enables the clock at Pin CLKOUT
2
PLL_PD
PLL power down
1-0
PLLDiv_FB
PLL feedback divider (see table 174)
0h - pin CLKOUT is used as I/O
1h - pin CLKOUT shows the output of the analog PLL
2h - pin CLKOUT is hold on 0
3h - pin CLKOUT is hold on 1
4h - pin CLKOUT shows 27.12 MHz from the crystal
5h - pin CLKOUT shows 13.56 MHz derived from the crystal
6h - pin CLKOUT shows 6.78 MHz derived from the crystal
7h - pin CLKOUT shows 3.39 MHz derived from the crystal
8h - pin CLKOUT is toggled by the Timer0 overflow
9h - pin CLKOUT is toggled by the Timer1 overflow
Ah - pin CLKOUT is toggled by the Timer2 overflow
Bh - pin CLKOUT is toggled by the Timer3 overflow
Ch...Fh - RFU
Table 168. Setting of feedback divider PLLDiv_FB [1:0]
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Bit 1
Bit 0
Division
0
0
23 (VCO frequency 312Mhz)
0
1
27 (VCO frequency 366MHz)
1
0
28 (VCO frequency 380Mhz)
1
1
23 (VCO frequency 312Mhz)
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9.14.4 PLLDiv_Out
Table 169. PLLDiv_Out register (address 3Eh)
Bit
7
6
5
4
3
Symbol
PLLDiv_Out
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0
Table 170. PLLDiv_Out bits
Bit
Symbol
Description
7 to 0
PLLDiv_Out
PLL output divider factor; Refer to Section 7.8.2
Table 171. Setting for the output divider ratio PLLDiv_Out [7:0]
Value
Division
0
RFU
1
RFU
2
RFU
3
RFU
4
RFU
5
RFU
6
RFU
7
RFU
8
8
9
9
10
10
...
...
253
253
254
254
255
255
9.15 Low-power card detection configuration registers
The LPCD registers contain the settings for the low-power card detection. The setting
for LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers
LPCD_QMin, LPCD_QMax and LPCD_IMin each.
9.15.1 LPCD_QMin
Table 172. LPCD_QMin register (address 3Fh)
Bit
Symbol
7
6
LPCD_IMax.5
LPCD_IMax.4
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4
3
2
1
0
LPCD_QMin
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Table 172. LPCD_QMin register (address 3Fh)...continued
Bit
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6
5
r/w
r/w
4
3
2
1
0
r/w
Table 173. LPCD_QMin bits
Bit
Symbol
Description
7, 6
LPCD_IMax
Defines the highest two bits of the higher border for the LPCD. If the
measurement value of the I channel is higher than LPCD_IMax, a
LPCD interrupt request is indicated by bit IRQ0.LPCDIRQ.
5 to 0
LPCD_QMin
Defines the lower border for the LPCD. If the measurement value of
the Q channel is higher than LPCD_QMin, a LPCDinterrupt request is
indicated by bit IRQ0.LPCDIRQ.
9.15.2 LPCD_QMax
Table 174. LPCD_QMax register (address 40h)
Bit
7
6
5
4
3
2
Symbol
LPCD_IMax.3
LPCD_IMax.2
LPCD_QMax
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Table 175. LPCD_QMax bits
Bit
Symbol
Description
7
LPCD_IMax.3
Defines the bit 3 of the high border for the LPCD. If the
measurement value of the I channel is higher than LPCD IMax, a
LPCD IRQ is raised.
6
LPCD_IMax.2
Defines the bit 2 of the high border for the LPCD. If the
measurement value of the I channel is higher than LPCD IMax, a
LPCD IRQ is raised.
5 to 0
LPCD_QMax
Defines the high border for the LPCD. If the measurement value of
the Q channel is higher than LPCD QMax, a LPCD IRQ is raised.
9.15.3 LPCD_IMin
Table 176. LPCD_IMin register (address 41h)
Bit
7
6
Symbol
LPCD_IMax.1
LPCD_IMax.0
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5
4
3
2
1
0
LPCD_IMin
r/w
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Table 177. LPCD_IMin bits
Bit
Symbol
Description
7 to 6
LPCD_IMax
Defines lowest two bits of the higher border for the low-power card
detection (LPCD). If the measurement value of the I channel is higher
than LPCD IMax, a LPCD IRQ is raised.
5 to 0
LPCD_IMin
Defines the lower border for the ow power card detection. If the
measurement value of the I channel is lower than LPCD IMin, a LPCD
IRQ is raised.
9.15.4 LPCD_Result_I
Table 178. LPCD_Result_I register (address 42h)
Bit
7
6
5
4
3
2
Symbol
RFU-
RFU-
LPCD_Result_I
Access
rights
-
-
r
1
0
Table 179. LPCD_I_Result bits
Bit
Symbol
Description
7 to 6
RFU
-
5 to 0
LPCD_Result_I Shows the result of the last low-power card detection (I-Channel).
9.15.5 LPCD_Result_Q
Table 180. LPCD_Result_Q register (address 43h)
Bit
Symbol
7
6
RFU
LPCD_
IRQ_Clr
LPCD_Reslult_Q
r/w
r
Access
rights
5
4
3
2
1
0
Table 181. LPCD_Q_Result bits
Bit
Symbol
Description
7
RFU
-
6
LPCD_IRQ_Clr
If set no LPCD IRQ is raised any more until the next low-power
card detection procedure. Can be used by software to clear the
interrupt source.
5 to 0
LPCD_Result_Q
Shows the result of the last ow power card detection (Q-Channel).
9.15.6 LPCD_Options
This register is available on the MFRC63003 only. For silicon version MFRC63002 this
register on address 3AH is RFU.
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Table 182. LPCD_Options register (address 3Ah)
Bit
7
6
Symbol
5
4
RFU
-
3
2
1
0
LPCD_TX_HIGH
LPCD_FILTER
LPCD_Q_
UNSTABLE
LPCD_I_UNSTABLE
r/w
r/w
r
r
Access
rights
Table 183. LPCD_Options
Bit
Symbol
Description
7 to 4
RFU
-
3
LPCD_TX_HIGH
If set, the TX-driver will be the same as VTVDD during LPCD. This will allow for
a better LPCD detection range (higher transmitter output voltage) at the cost of
a higher current consumption. If this bit is cleared, the output voltage at the TX
drivers will be = TVDD- 0.4V. If this bit is set, the output voltage at the TX drivers
will be = VTVDD.
2
LPCD_FILTER
If set, The LPCD decision is based on the result of a filter which allows to
remove noise from the evaluated signal in I and Q channel. Enabling LPCD_
FILTER allows compensating for noisy conditions at the cost of a longer RF-ON
time required for sampling. The total maximum LPCD sampling time is 4.72us.
1
LPCD_Q_UNSTABLE
If bit 2 of this register is set, bit 1 indicates that the Q-channel ADC value was
changing during the LPCD measuring time. Note: Only valid if LPCD_FILTER (bit
2) = 1. This information can be used by the host application for configuration of
e.g. the threshold LPCD_QMax or inverting the TX drivers.
0
LPCD_I_UNSTABLE
If bit 2 of this register is set, bit 0 Indicates that the I-channel ADC value was
changing during the LPCD measuring time. Note: Only valid if LPCD_FILTER
(bit2) = 1. This information can be used by the host application for configuration
of e.g. the threshold LPCD_IMax or inverting the TX drivers.
9.16 Pin configuration
9.16.1 PadEn
Table 184. PadEn register (address 44h)
Bit
7
6
5
4
3
2
1
0
Symbol
SIGIN_
EN / OUT7
CLKOUT_
EN / OUT6
IFSEL1_
EN / OUT5
IFSEL0_
EN / OUT4
TCK_EN /
OUT 3
TMS_EN /
OUT2
TDI_EN /
OUT1
TDO_EN /
OUT0
Access
rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Table 185. PadEn bits
MFRC630
Product data sheet
COMPANY PUBLIC
Bit
Symbol
Description
7
SIGIN_EN / OUT7
Enables the output functionality on SIGIN (pin 5). The pin is
then used as output.
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Table 185. PadEn bits...continued
Bit
Symbol
Description
6
CLKOUT_EN / OUT6
Enables the output functionality of the CLKOUT (pin 22). The
pin is then used as output. The CLKOUT function is switched
off.
5
IFSEL1_EN / OUT5
Enables the output functionality of the IFSEL1 (pin 27). The
pin is then used as output.
4
IFSEL0_EN / OUT4
Enables the output functionality of the IFSEL0 (pin 26). The
pin is then used as output.
3
TCK_EN / OUT3
Enables the output functionality of the TCK (pin 4) of the
boundary scan interface. The pin is then used as output. If
the boundary scan is activated in EEPROM, this bit has no
function.
2
TMS_EN / OUT2
Enables the output functionality of the TMS (pin 2) of the
boundary scan interface. The pin is then used as output. If
the boundary scan is activated in EEPROM, this bit has no
function.
1
TDI_EN / OUT1
Enables the output functionality of the TDI (pin 1) of the
boundary scan interface. The pin is then used as output. If
the boundary scan is activated in EEPROM, this bit has no
function.
0
TDO_EN / OUT0
Enables the output functionality of the TDO(pin 3) of the
boundary scan interface. The pin is then used as output. If
the boundary scan is activated in EEPROM, this bit has no
function.
9.16.2 PadOut
Table 186. PadOut register (address 45h)
Bit
7
6
5
Symbol
SIGIN_OUT
CLKOUT_OUT
Access
rights
r/w
r/w
4
3
2
IFSEL1_OUT IFSEL0_OUT TCK_OUT TMS_OUT
r/w
r/w
r/w
r/w
1
0
TDI_OUT
TDO_OUT
r/w
r/w
Table 187. PadOut bits
MFRC630
Product data sheet
COMPANY PUBLIC
Bit
Symbol
Description
7
SIGIN_OUT
Output buffer of the SIGIN pin
6
CLKOUT_OUT
Output buffer of the CLKOUT pin
5
IFSEL1_OUT
Output buffer of the IFSEL1 pin
4
IFSEL0_OUT
Output buffer of the IFSEL0 pin
3
TCK_OUT
Output buffer of the TCK pin
2
TMS_OUT
Output buffer of the TMS pin
1
TDI_OUT
Output buffer of the TDI pin
0
TDO_OUT
Output buffer of the TDO pin
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9.16.3 PadIn
Table 188. PadIn register (address 46h)
Bit
7
6
5
4
3
2
1
0
Symbol
SIGIN_IN
CLKOUT_IN
IFSEL1_IN
IFSEL0_IN
TCK_IN
TMS_IN
TDI_IN
TDO_IN
Access
rights
r
r
r
r
r
r
r
r
2
1
0
Table 189. PadIn bits
Bit
Symbol
Description
7
SIGIN_IN
Input buffer of the SIGIN pin
6
CLKOUT_IN
Input buffer of the CLKOUT pin
5
IFSEL1_IN
Input buffer of the IFSEL1 pin
4
IFSEL0_IN
Input buffer of the IFSEL0 pin
3
TCK_IN
Input buffer of the TCK pin
2
TMS_IN
Input buffer of the TMS pin
1
TDI_IN
Input buffer of the TDI pin
0
TDO_IN
Input buffer of the TDO pin
9.16.4 SigOut
Table 190. SigOut register (address 47h)
Bit
7
6
5
4
3
Symbol
Pad
Speed
RFU
SigOutSel
Access
rights
r/w
-
r/w
Table 191. SigOut bits
MFRC630
Product data sheet
COMPANY PUBLIC
Bit
Symbol
Description
7
PadSpeed
If set, the I/O pins are supporting a fast switching mode.The fast mode
for the I/O’s will increase the peak current consumption of the device,
especially if multiple I/Os are switching at the same time. The power
supply needs to be designed to deliver this peak currents.
6 to 4
RFU
-
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Table 191. SigOut bits...continued
Bit
Symbol
Description
3 to 0
SIGOutSel
0h, 1h - The pin SIGOUT is 3-state
2h - The pin SIGOUT is 0
3h - The pin SIGOUT is 1
4h - The pin SIGOUT shows the TX-envelope
5h - The pin SIGOUT shows the TX-active signal
6h - The pin SIGOUT shows the S3C (generic) signal
7h - The pin SIGOUT shows the RX-envelope
(only valid for ISO/IEC 14443A, 106 kBd)
8h - The pin SIGOUT shows the RX-active signal
9h - The pin SIGOUT shows the RX-bit signal
0Ah ...0Fh: RFU
9.17 Version register
9.17.1 Version
Table 192. Version register (address 7Fh)
Bit
7
6
5
4
3
2
1
Symbol
Version
SubVersion
Access
rights
r
r
0
Table 193. Version bits
MFRC630
Product data sheet
COMPANY PUBLIC
Bit
Symbol
Description
7 to 4
Version
Includes the version of the MFRC630 silicon.
MFRC63002: 0x1
MFRC63003: 0x1
3 to 0
SubVersion
Includes the subversion of the MFRC630 silicon.
MFRC63002: 0x8
MFRC63003: 0xA
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10 Limiting values
Table 194. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
-0.5
+ 6.0
V
VDD(PVDD)
PVDD supply voltage
-0.5
+ 6.0
V
VDD(TVDD)
TVDD supply voltage
-0.5
+ 6.0
V
IDD(TVDD)
TVDD supply current
MFRC63001, MFRC63002
-
250
mA
MFRC63003
-
500
mA
Vi(RXP)
input voltage on pin RXP
-0.5
+ 2.0
V
Vi(RXN)
input voltage on pin RXN
-0.5
+ 2.0
V
Ptot
total power dissipation
-
1125
mW
-2000
2000
V
-500
500
V
-
+150
°C
-55
+150
°C
VESD
per package
electrostatic discharge voltage human body model (HBM)
1500 Ω, 100 pF
[1]
charge device model (CDM)
Tj(max)
maximum junction
temperature
Tstg
storage temperature
[1]
[2]
;
[2]
no supply voltage applied
According to ANSI/ESDA/JEDEC JS-001.
According to ANSI/ESDA/JEDEC JS-002.
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11 Recommended operating conditions
Exposure of the device to other conditions than specified in the Recommended Operating
Conditions section for extended periods may affect device reliability.
Electrical parameters (minimum, typical and maximum) of the device are guaranteed only
when it is used within the recommended operating conditions.
Table 195. Operating conditions MFRC63001, MFRC63002
Symbol
Parameter
VDD
supply voltage
Conditions
[1]
Min
Typ
Max
Unit
3.0
5.0
5.5
V
3.0
5.0
5.5
V
VDD(TVDD)
TVDD supply voltage
VDD(PVDD)
PVDD supply voltage
all host interfaces
3.0
5.0
5.5
V
Tj(max)
maximum junction
temperature
-
-
-
+125
°C
Tamb
operating ambient
temperature
in still air with exposed pin soldered on a 4
layer JEDEC PCB
-25
+25
+85
°C
Tstg
storage temperature
no supply voltage applied, relative humidity
45...75%
-45
+25
+125
°C
Min
Typ
Max
Unit
2.5
5.0
5.5
V
2.5
5.0
5.5
V
all host interfaces except I2C interface
2.5
5.0
5.5
V
all host interfaces incl. I2C interface
3.0
5.0
5.5
V
[1]
VDD(PVDD) must always be the same or lower than VDD.
Table 196. Operating conditions CLRC63003
Symbol
Parameter
VDD
supply voltage
VDD(TVDD)
TVDD supply voltage
VDD(PVDD)
PVDD supply voltage
Conditions
[1]
Tj(max)
maximum junction
temperature
-
-
-
+125
°C
Tamb
operating ambient
temperature
HVQFN32 package, in still air with exposed
pin soldered on a 4 layer JEDEC PCB
-40
+25
+105
°C
VFBGA36 package, in still air with exposed
pin soldered on a 4 layer JEDEC PCB
-40
+25
+85
°C
no supply voltage applied, relative humidity
45...75%
-45
+25
+125
°C
Tstg
[1]
storage temperature
VDD(PVDD) must always be the same or lower than VDD.
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12 Thermal characteristics
Table 197. Thermal characteristics
Symbol
Parameter
Conditions
Package
Rth(j-a)
thermal resistance from junction to
ambient
in still air with exposed pin soldered on a 4
layer JEDEC PCB
HVQFN32 40
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Unit
K/W
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13 Characteristics
Table 198. Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD = AVDD+DVDD; modem
on (transmitter and
receiver are switched on)
-
17
20
mA
IDD = AVDD+DVDD; modem
off (transmitter and
receiver are switched off)
-
0.45
0.5
mA
Current consumption
IDD
supply current
IDD(PVDD)
PVDD supply current
no load on digital pins,
leakage current only
-
0.5
5
μA
IDD(TVDD)
TVDD supply current
MFRC63001HN,
MFRC63002HN
-
100
250
mA
MFRC66303HN
-
250
350
mA
ambient temp = +25 °C
-
40
400
nA
ambient temp = -40°C...
+85°C
-
1.5
2.1
μA
MFRC63003: ambient
temp = +105 °C
-
3.5
5.2
μA
ambient temp = 25 °C,
IVDD+ITVDD+ IPVDD
-
3
6
μA
ambient temp = -40°C...
+105°C, Istby = IVDD+ITVDD+
IPVDD
-
5.25
26
-
3.3
6.3
μA
LPCD_TX_HIGH = 0,
-
12
-
μA
LPCD_TX_HIGH = 1
-
23
-
LPCD_TX_HIGH = 0;
TVDD=5.0 V
T=25C;
-
10
-
μs
LPCD_TX_HIGH = 1;
TVDD=5.0 V; T=25C
-
50
-
μs
Ipd
Istby
power-down current
standby current
ILPCD(sleep) LPCD sleep current
All OUTx pins floating
All OUTx pins floating
All OUTx pins floating
LFO active, no RF field on,
ambient temp = 25 °C
ILPCD(average)LPCD average current
tRFON
RF-on time during LPCD
[1]
All OUTx pins floating,
TxLoad = 50 ohms.
LPCD_FILTER = 0; Rfon
duration = 10 us, RF-off
duration 300ms; VTVDD =
3.0V; Tamb = 25°C; ILPCD =
IVDD+ITVDD+ IPVDD
Buffer capacitors on AVDD,DVDD
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Table 198. Characteristics...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CL
external buffer capacitor
AVDD
220
470
-
nF
CL
external buffer capacitor
DVDD
220
470
-
nF
0.0
50
500
nA
0.3 x VDD(PVDD)
V
I/O pin characteristics SIGIN/OUT7, SIGOUT, CLKOUT/OUT6,
IFSEL0/OUT4, IFSEL1/OUT5, TCK/OUT3, TMS/OUT2, TDI/
OUT1, TDO/OUT0, IRQ, IF0, IF1, IF2, SCL2, SDA2
ILI
input leakage current
output disabled
VIL
low-level input voltage
-0.5
-
VIH
high-level input voltage
0.7 x
VDD(PVDD)
VDD(PVDD)VDD(PVDD) + 0.5 V
VOL
low-level output voltage
0.0
0.0
VOH
high-level output voltage
Ci
input capacitance
If pins are used as output
OUTx, IOH = 4 mA driving
current for each pin
0.4
V
VDD(PVDD)-0.4 VDD(PVDD)VDD(PVDD)
V
0.0
2.5
4.5
pF
0.4
V
Pin characteristics PDOWN
VIL
low-level input voltage
0.0
0.0
VIH
high-level input voltage
0.6 x VPVDD
VDD(PVDD)VDD(PVDD)
V
50
72
120
KΩ
Pull-up resistance for TCK, TMS, TDI, IF2
Rpu
pull-up resistance
Pin characteristics AUX 1, AUX 2
Vo
output voltage
0.0
-
1.8
V
CL
load capacitance
0.0
-
400
pF
Pin characteristics RXP, RXN
Vp
input voltage
0
1.65
1.8
V
Ci
input capacitance
2
3.5
5
pF
Vmod(pp)
modulation voltage
-
2.5
-
mV
Vss(TVSS)
-
VDD(TVDD)
V
MFRC63002: T=25°C,
VDD(TVDD) = 5.0V
-
1.5
-
Ω
MFRC63003: T=25°C,
VDD(TVDD) = 5.0V
-
1.2
-
Ω
configured to 27.12 MHz
-
27.12
-
MHz
-
50
-
%
-
1.0
-
V
Vmod(pp) = Vi(pp)(max) - Vi(pp)
(min)
Pins TX1 and TX2
Vo
output voltage
Ro
output resistance
Clock frequency Pin CLKOUT
fclk
clock frequency
δclk
clock duty cycle
Crystal connection XTAL1, XTAL2
Vo(p-p)
peak-to-peak output
voltage
MFRC630
Product data sheet
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pin XTAL1
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Table 198. Characteristics...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vi
input voltage
pin XTAL1
0.0
-
1.8
V
Ci
input capacitance
pin XTAL1
-
3
-
pF
ISO/IEC14443 compliancy
27.12-14kHz
27.12
27.12+14kHz
MHz
Crystal requirements
fxtal
crystal frequency
ESR
equivalent series
resistance
-
50
100
Ω
CL
load capacitance
-
10
-
pF
Pxtal
crystal power dissipation
-
50
100
μW
-
2
100
nA
-
+0.3 VDD(PVDD)
V
2
Input characteristics I/O Pin Characteristics IF3-SDA in I C configuration
ILI
input leakage current
VIL
LOW-level input voltage
-0.5
VIH
HIGH-level input voltage
0.7 VDD(PVDD) -
VDD(PVDD) + 0.5 V
VOL
LOW-level output voltage IOL = 3 mA
-
-
0.3
V
IOL
LOW-level output current
VOL = 0.4 V; Standard
mode, Fast mode
4
-
-
mA
VOL = 0.6 V; Standard
mode, Fast mode
6
-
-
mA
Standard mode, Fast
mode, CL < 400 pF
-
-
250
ns
Fast mode +; CL < 550 pF
-
-
120
ns
tf(o)
output fall time
output disabled
tSP
pulse width of spikes that
must be suppressed by
the input filter
0
-
50
ns
Ci
input capacitance
-
3.5
5
pF
CL
load capacitance
Standard mode
-
-
400
pF
Fast mode
-
-
550
pF
-
-
year
-
-
cycle
tEER
EEPROM data retention
time
Tamb = +55 °C
10
NEEC
EEPROM endurance
(number of programming
cycles)
under all operating
conditions
5 x 10
[1]
5
Ipd is the total current for all supplies.
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Vmod
Vi(p-p)(max)
VMID
Vi(p-p)(min)
13.56 MHz
carrier
0V
001aak012
Figure 29. Pin RX input voltage
13.1 Timing characteristics
Table 199. SPI timing characteristics
Symbol
Parameter
tSCKL
Conditions
Min
Typ
Max
Unit
SCK LOW time
50
-
-
ns
tSCKH
SCK HIGH time
50
-
-
ns
th(SCKH-D)
SCK HIGH to data input hold SCK to changing
time
MOSI
25
-
-
ns
tsu(D-SCKH) data input to SCK HIGH setup time
changing MOSI to
SCK
25
-
-
ns
th(SCKL-Q)
SCK LOW to data output
hold time
SCK to changing
MISO
-
-
25
ns
t(SCKL-
SCK LOW to NSS HIGH time
0
-
-
ns
50
-
-
ns
NSSH)
tNSSH
NSS HIGH time
before
communication
Remark: To send more bytes in one data stream the NSS signal must be LOW during
the send process. To send more than one data stream the NSS signal must be HIGH
between each data stream.
2
Table 200. I C-bus timing in fast mode and fast mode plus
Symbol
MFRC630
Product data sheet
COMPANY PUBLIC
Parameter
Conditions
Fast mode
Fast mode
Plus
Unit
Min
Max
Min
Max
0
400
0
1000 kHz
after this period, the 600
first clock pulse is
generated
-
260
-
ns
fSCL
SCL clock frequency
tHD;STA
hold time (repeated) START
condition
tSU;STA
set-up time for a repeated
START condition
600
-
260
-
ns
tSU;STO
set-up time for STOP
condition
600
-
260
-
ns
tLOW
LOW period of the SCL clock
1300 -
500
-
ns
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2
Table 200. I C-bus timing in fast mode and fast mode plus...continued
Symbol
Parameter
Conditions
Fast mode
Fast mode
Plus
Min
Max
Min
Max
Unit
tHIGH
HIGH period of the SCL clock
600
-
260
-
ns
tHD;DAT
data hold time
0
900
-
450
ns
tSU;DAT
data set-up time
100
-
-
-
ns
tr
rise time
SCL signal
20
300
-
120
ns
tf
fall time
SCL signal
20
300
-
120
ns
tr
rise time
SDA and SCL
signals
20
300
-
120
ns
tf
fall time
SDA and SCL
signals
20
300
-
120
ns
tBUF
bus free time between a
STOP and START condition
1.3
-
0.5
-
μs
SDA
tf
tSU;DAT
tLOW
tSP
tf
tr
tHD;STA
tBUF
SCL
tr
tHD;STA
S
tHIGH
tHD;DAT
tSU;STO
tSU;STA
Sr
P
S
001aaj635
2
Figure 30. Timing for fast and standard mode devices on the I C-bus
MFRC630
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14 Application information
A typical application diagram using a complementary antenna connection to the
MFRC630 is shown in Figure 31.
The antenna tuning and RF part matching is described in the application note [1] and [2].
VDD
PVDD
TVDD
25
18
8
AVDD
9
13
14
PDOWN
MICROPROCESSOR
host
interface
IRQ
DVDD
21
28-31
17
READER IC
16
32
15
CRXN
RXN
VMID
R1 C
vmid
TX1
R2
C1
L0
TVSS
TX2
Ra
C0
C2
C0
C2
Ra
antenna
Lant
L0
C1
14
7
12
33
VSS
19
RXP
20
XTAL1
XTAL2
R3
R4
CRXP
27.12 MHz
001aam269
Figure 31. Typical application antenna circuit diagram
14.1 Antenna design description
The matching circuit for the antenna consists of an EMC low pass filter (L0 and C0), a
matching circuitry (C1 and C2), and a receiving circuits (R1 = R3, R2 = R4, C3 = C5
and C4 = C6;), and the antenna itself. The receiving circuit component values needs to
be designed for operation with the MFRC630. A reuse of dedicated antenna designs
done for other products without adaptation of component values will result in degraded
performance.
14.1.1 EMC low pass filter
The MIFARE product-based system operates at a frequency of 13.56 MHz. This
frequency is derived from a quartz oscillator to clock the MFRC630 and is also the
basis for driving the antenna with the 13.56 MHz energy carrier. This will not only
cause emitted power at 13.56 MHz but will also emit power at higher harmonics. The
international EMC regulations define the amplitude of the emitted power in a broad
frequency range. Thus, an appropriate filtering of the output signal is necessary to fulfil
these regulations.
Remark: The PCB layout has a major influence on the overall performance of the filter.
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14.1.2 Antenna matching
Due to the impedance transformation of the given low pass filter, the antenna coil has to
be matched to a certain impedance. The matching elements C1 and C2 can be estimated
and have to be fine tuned depending on the design of the antenna coil.
The correct impedance matching is important to provide the optimum performance.
The overall quality factor has to be considered to guarantee a proper ISO/IEC 14443
communication scheme. Environmental influences have to be considered as well as
common EMC design rules.
For details refer to the NXP application notes.
14.1.3 Receiving circuit
The internal receiving concept of the MFRC630 makes use both side-bands of the subcarrier load modulation of the card response via a differential receiving concept (RXP,
RXN). No external filtering is required.
It is recommended to use the internally generated VMID potential as the input potential
of pin RX. This DC voltage level of VMID has to be coupled to the Rx-pins via R2 and
R4. To provide a stable DC reference voltage capacitances C4, C6 has to be connected
between VMID and ground. Refer to Figure 31
Considering the (AC) voltage limits at the Rx-pins the AC voltage divider of R1 + C3 and
R2 as well as R3 + C5 and R4 has to be designed. Depending on the antenna coil design
and the impedance matching the voltage at the antenna coil varies from antenna design
to antenna design. Therefore the recommended way to design the receiving circuit is to
use the given values for R1(= R3), R2 (= R4), and C3 (= C5) from the above mentioned
application note, and adjust the voltage at the RX-pins by varying R1(= R3) within the
given limits.
Remark: R2 and R4 are AC-wise connected to ground (via C4 and C6).
14.1.4 Antenna coil
The precise calculation of the antenna coils’ inductance is not practicable but the
inductance can be estimated using the following formula. We recommend designing an
antenna either with a circular or rectangular shape.
(4)
• I1 - Length in cm of one turn of the conductor loop
• D1 - Diameter of the wire or width of the PCB conductor respectively
• K - Antenna shape factor (K = 1,07 for circular antennas and K = 1,47 for square
antennas)
• L1 - Inductance in nH
• N1 - Number of turns
• Ln: Natural logarithm function
The actual values of the antenna inductance, resistance, and capacitance at 13.56
MHz depend on various parameters such as:
MFRC630
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MFRC630
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•
•
•
•
•
antenna construction (Type of PCB)
thickness of conductor
distance between the windings
shielding layer
metal or ferrite in the near environment
Therefore a measurement of those parameters under real life conditions, or at least a
rough measurement and a tuning procedure is highly recommended to guarantee a
reasonable performance. For details refer to the above mentioned application notes.
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MFRC630
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15 Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
B
D
SOT617-1
A
terminal 1
index area
A
E
A1
c
detail X
C
e1
e
1/2 e
16
L
y
y1 C
v M C A B
w M C
b
9
17
8
e
e2
Eh
1/2 e
1
terminal 1
index area
24
32
25
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
3.5
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT617-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
Figure 32. Package outline SOT617-1 (HVQFN32)
MFRC630
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MFRC630
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Detailed package information can be found at http://www.nxp.com/package/
SOT617-1.html.
MFRC630
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16 Handling information
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.
MFRC630
Product data sheet
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MFRC630
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17 Packing information
Moisture Sensitivity Level (MSL) evaluation has been performed according to SNWFQ-225B rev.04/07/07 (JEDEC J-STD-020C).
An MSL corresponds to a certain out-of-bag time (or floor life). If semiconductor
packages are removed from their sealed dry-bags and not soldered within their out-ofbag time, they must be baked prior to reflow soldering, in order to remove any moisture
that might have soaked into the package.
For MSL3:
168h out-of-pack floor life at maximum ambient temperature, conditions < 30°C / 60 %
RH.
For MSL2:
• 1 year out-of-pack floor life at maximum ambient temperature, conditions < 30°C / 60 %
RH.
For MSL1:
• No out-of-pack floor live spec. required. Conditions: