FS5600
Automotive buck regulator and controller with voltage
monitors and watchdog timer
Rev. 3 — 2 August 2022
1
Product data sheet
General Description
The FS5600 integrates a battery connected DC-DC controller with external FETs
and a battery connected DC-DC converter with internal FETs. It also offers functional
safety features such as independent voltage monitors, windowed watchdog timer, I/O
monitoring via ERRMON and FCCU, and built-in self-test.
2
Features and Benefits
• 2 x High-Voltage Buck Converters:
– Buck Controller - External FETs - 900 mA gate drive - up to 15 A load capability
– Buck Regulator - Internal FETs - 3 A+ load capability
– ±2 % Output Accuracy
– 250 kHz to 3 MHz switching frequency
• High-efficiency PFM mode
• Safety Features:
– Available in Enhanced ASIL B, ASIL B, and QM variations
– 2 internal and up to 4 high-accuracy external voltage monitors
– Windowed Watchdog Timer
– ERRMON and FCCU monitoring
– 2 x PGOOD and 1 x FS0B outputs
– ABIST and LBIST for latest failure check
• GPIOs for seamless operation with PF PMICs
• Rated from –40 °C to 150 °C TJ
• 32-Ld 5 mm x 5 mm QFN
• AEC-Q100 Grade-1 Qualified
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
2.1 Overview
FS5600 Functional Block Diagram
SW1 - Buck Regulator
Up to 36 V Input
> 3 A Load Current
1.8 V to 8.0 V Output
Internal FET
SW2 - Buck Controller
Up to 36 V Input
Up to 15 A Load
1.8 V to 7.2 V Output
External FET
4x VMON
2x PGOOD
ABIST
LBIST
Clock Sync
FS0B
Watchdog
I2C
Spread
Spectrum
OTP
Memory
3x GPIO
Thermal
Shutdown
Frequency
Tuning
aaa-037150
Figure 1. FS5600 Functional block diagram
3
Applications
QM to ASIL D automotive applications such as:
•
•
•
•
•
•
•
Infotainment / Cluster / Driver Awareness
Telematics
V2X
Radar
Vision
ADAS
Sensor fusion
Additional safety mechanisms may be needed for ASIL D compliance in the system level.
FS5600 is developed to meet ASIL B requirements.
4
Ordering Information
The FS5600 is offered in QM, ASIL B, and Enhanced ASIL B versions. The Enhanced
ASIL B version features a Challenger Watchdog and Logic BIST (LBIST) which may
be used to achieve ASIL D functional safety at the system level. Additional safety
mechanisms may be needed at the system level for ASIL D compliance.
Table 1. Device options
Feature
QM Version
ASIL B Version
Enhanced ASIL B
Version
SW1 – Integrated FET buck converter
Yes
Yes
Yes
SW2 – External FET buck controller
Yes
Yes
Yes
GPOs for system sequence control
Yes
Yes
Yes
PGOOD1 and PGOOD2 output
Yes
Yes
Yes
Windowed Watchdog Timer
No
Yes (Simple)
Yes (Challenger)
FS5600
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FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
Table 1. Device options...continued
Feature
QM Version
ASIL B Version
Enhanced ASIL B
Version
4 External Voltage Monitors (VMON)
No
Yes
Yes
ERRMON Monitoring (muxed with VMON)
No
Yes
Yes
FCCU Monitoring (muxed with VMON)
No
Yes
Yes
FS0B output
No
Yes
Yes
ABIST
No
Yes
Yes
LBIST
No
No
Yes
No
Yes
Yes
2
I C CRC
Table 2. Ordering information
Part number
Safety
grade
OTP ID
SW1
SW2
Package drawing
MFS5600AMMA0ES Automotive
QM
A0 – Non-programmed
—
—
SOT617-24(SC)
MFS5600AMBA0ES Automotive
ASIL B
A0 – Non-programmed
—
—
SOT617-24(SC)
MFS5600AMEA0ES Automotive
Enhanced
ASIL B
A0 – Non-programmed
—
—
SOT617-24(SC)
MFS5600AVMA0EP Industrial
QM
A0 – Non-programmed
—
—
SOT617-24
MFS5600AMMA7ES Automotive
QM
https://www.nxp.com/
MFS5600A7ES-OTPReport
5.0 V
3.3 V
SOT617-24(SC)
450 kHz 450 kHz
MFS5600AMMA8ES Automotive
QM
https://www.nxp.com/
MFS5600A8ES-OTPReport
3.3 V
5.0 V
SOT617-24(SC)
450 kHz 450 kHz
FS5600
Product data sheet
Target
market
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FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
SW2GLS
SW2CSN
SW2CSP
SW2COMP
SW2BOOT
SW2GHS
SW2LX
SW1BOOT
EN1
SW1GND(EPAD)
SW1LX
FS5600 Internal Block Diagram
SW1IN
5
SW1FB
EN2
SW1
BUCK REGULATOR
VIN
SW2
BUCK CONTROLLER
SW2FB
LDO/
SWITCH
VCC
BIAS_IN
VCC OV/UV
MONITOR
VDIG
VDIG OV/UV
MONITOR
GPIO1
I/O
Buffers
VMON2
MONITORING
BANDGAP
VOLTAGE
MONITORS
VMON3
VMON4
SW1FB
SW2FB
OTP MEMORY
(CRC/ECC)
GPIO3
SYNCIN/MODE
VMON1
LBIST
SCL
GPIO2
20 MHz & 100 kHz
CLOCKS; PLL
FS5600 LOGIC
Regulator Control
State Machine
Functional Safety
VDDIO
SDA
MAIN BANDGAP
AND CURRENT
REFERENCE
V1P6 LDO
BANDGAP
COMPARATOR
THERMAL
SHUTDOWN
OUTPUT
BUFFERS
(MONITORED)
PGOOD1
PGOOD2
FS0B
ABIST
aaa-037151
Figure 2. FS5600 internal block diagram
6
Regulator Input Configurations
Input to SW1 and SW2 may be applied directly from a reverse protected automotive
battery, or from the output of the other regulator as shown below. Ensure that Enable for
the regulator goes high after its input is stable for proper soft-start operation.
From reverse
protected battery
From reverse protected
battery or SW2OUT
VIN
From reverse protected
battery or SW1OUT
SW1IN
Ext FET IN
FS5600
Q1
SW1OUT
SW2OUT
Q2
SW1 Int FET
SW2 Ext FET
aaa-039552
Figure 3. Regulator input options
FS5600
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FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
7
Pinout and Pin Description
SW1FB
PGOOD1
PGOOD2
VDIG
BIAS_IN
VCC
MODE/SYNCIN
VIN
The FS5600 is offered in a 32-Ld 5 mm x 5 mm WF-QFN package.
32 31 30 29 28 27 26 25
VDDIO
1
24 NA
SCL
2
23 EN1
SDA
3
22 EN2
GPIO1/VDDOTP
4
SW2COMP
5
21 SW1LX
EPAD
20 SW1LX
SW2FB
6
19 SW1IN
SW2CSN
7
18 SW1IN
SW2CSP
8
17 SW1BOOT
GPO3
GPO2
NA
NA
PGOOD2
PGOOD1
SW1FB
SW2BOOT
VDIG
SW2GHS
SW2LX
SW2GLS
9 10 11 12 13 14 15 16
aaa-037152
Figure 4. QM version pinout
BIAS_IN
VCC
MODE/SYNCIN
VIN
32 31 30 29 28 27 26 25
VDDIO
1
24 FS0B
SCL
2
23 EN1
SDA
3
22 EN2
GPIO1/VDDOTP
4
SW2COMP
5
SW2FB
6
19 SW1IN
SW2CSN
7
18 SW1IN
SW2CSP
8
21 SW1LX
EPAD
20 SW1LX
17 SW1BOOT
VMON1
VMON2
VMON3/GPIO2
SW2BOOT
VMON4/GPIO3
SW2GHS
SW2LX
SW2GLS
9 10 11 12 13 14 15 16
aaa-037153
Figure 5. ASIL B, and enhanced ASIL B version pinout
FS5600
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NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
Table 3. Pin description
Absolute
maximum
voltage rating
Pin
number
Pin name
Description
1
VDDIO
I C I/O driver supply. Connect to 1.8 V or 3.3 V on
–0.3 V to 5.5 V
the board. Bypass with 0.1 µF capacitor.
2
SCL
I C clock line. Pullup to VDDIO on board.
2
Connection if not
used
Connect to VCC
2
–0.3 V to 5.5 V
Connect to ground
2
3
SDA
I C data line. Pullup to VDDIO on board.
–0.3 V to 5.5 V
Connect to ground
4
GPIO1/VDDOTP
General-purpose input/output pin. Used as
VDDOTP during development.
–0.3 V to 10 V
Connect to ground
5
SW2COMP
SW2 compensation pin. Connect to external
compensation network.
–0.3 V to 5.5 V
Connect to ground
6
SW2FB
SW2 output voltage feedback. Use external or
internal resistor divider for SW2 outputs ≤ 5.5 V.
–0.3 V to 7.5 V
Use external resistor divider for SW2 outputs > 5.5
V.
Connect to ground
7
SW2CSN
SW2 current sense feedback (-ve). Route
differentially with SW2CSP to sense circuitry.
–0.3 V to 7.5 V
Connect to ground
8
SW2CSP
SW2 current sense feedback (+ve). Route
differentially with SW2CSN to sense circuitry.
–0.3 V to 7.5 V
Connect to ground
9
SW2GLS
SW2 low side MOSFET gate output. Connect to
gate of external low side MOSFET.
–0.3 V to 5.5 V
Leave floating
10
SW2LX
SW2 switching node. High side gate drive return
path. Route parallel to SW2GHS trace on the
board.
–0.3 V to 40 V
Leave floating
11
SW2GHS
SW2 high side MOSFET gate output. Connect to
gate of external high side MOSFET.
–0.3 V to (SW2
BOOT + 0.3 V)
Leave floating
12
SW2BOOT
SW2 bootstrap pin. Connect bootstrap capacitor
between SW2BOOT and SW2LX.
–0.3 V to VSW2LX
Leave floating
+6V
13
VMON4/GPIO3
(GPO3 for QM
version)
General-purpose input/output pin. Also selectable
as voltage monitoring input via OTP. Only general- –0.3 V to 5.5 V
purpose output (GPO3) available in QM version.
Connect to ground
14
VMON3/GPIO2
(GPO2 for QM
version)
General-purpose input/output pin. Also selectable
as voltage monitoring input via OTP. Only general- –0.3 V to 5.5 V
purpose output (GPO2) available in QM version.
Connect to ground
15
VMON2
(NA for QM
version)
Voltage Monitor 2 input. Not available in QM
version. Connect to ground for QM version.
–0.3 V to 5.5 V
Connect to ground
16
VMON1
(NA for QM
version)
Voltage Monitor 1 input. Not available in QM
version. Connect to ground for QM version.
–0.3 V to 10 V
Connect to ground
17
SW1BOOT
SW1 bootstrap pin. Connect bootstrap capacitor
between SW1BOOT and SW1LX.
–0.3 V to VSW1LX
Leave floating
+6V
18, 19
SW1IN
SW1 input voltage. Bypass with at least 10 µF
capacitor for both pins together.
–0.3 V to 40 V
Connect to VIN
20, 21
SW1LX
SW1 switching node. Connect to inductor.
–0.3 V to 40 V
Leave floating
22
EN2
SW2 enable input pin.
–0.3 V to 40 V
Connect to ground
FS5600
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FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
Table 3. Pin description...continued
Pin
number
Pin name
Description
Absolute
maximum
voltage rating
Connection if not
used
23
EN1
SW1 enable input pin.
–0.3 V to 40 V
Connect to ground
24
FS0B
(NA for QM
version)
Fail-Safe Output pin. Open drain.
Connect to ground for QM version.
–0.3 V to 40 V
Connect to ground
25
SW1FB
SW1 output voltage feedback. Use external or
internal resistor divider for SW1 outputs ≤ 5.5 V.
–0.3 V to 7 V
Use external resistor divider for SW1 outputs > 5.5
V.
Connect to ground
26
PGOOD1
PGOOD1 output from monitoring of selected
voltage monitors. Open-drain.
–0.3 V to 5.5 V
Connect to ground
27
PGOOD2
PGOOD2 output from monitoring of selected
voltage monitors. Open-drain.
–0.3 V to 5.5 V
Connect to ground
28
VDIG
Output of internal regulator for powering logic.
Bypass with 2.2 µF capacitor. No external loading
permitted.
–0.3 V to 2.0 V
N/A
29
BIAS_IN
Input pin for external bias supply. Bypass with 1
µF capacitor. Connect to external bias supply <
5.5 V.
–0.3 V to 5.5 V
Connect to ground
30
VCC
VCC regulator/switch output. Bypass with 10
µF capacitor. No external loading permitted.
Nominally regulated at 4.7 V in the absence of
BIAS_IN.
–0.3 V to 5.5 V
N/A
31
MODE/SYNCIN
Selectable via OTP to be used for external clock
synchronization or to select between PFM and
PWM modes of operation.
–0.3 V to 5.5 V
Connect to ground
32
VIN
Input to internal circuitry. Connect to battery input. –0.3 V to 40 V
N/A
—
EPAD
Connect to ground with sufficient number of
thermal vias.
N/A
FS5600
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NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
8
ESD Ratings
Table 4. ESD ratings
Symbol
Rating
Min
[1][2]
Human Body Model – all pins
VESD
[1]
[2]
[3]
[4]
Unit
±2000
[3][2]
Charge Device Model – All pins
±500
GUN discharged contact test – 2 kΩ/150 pF; 2 kΩ/300 pF; 300 Ω/150 pF –
[4]
Global pins
±8000
V
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model (CDM),
Robotic (CZAP = 4.0 pF)
In accordance with AEC-Q-100 Rev H
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model (CDM),
Robotic (CZAP = 4.0 pF
In accordance with IEC61000-4-2 and ISO10605.2008
Caution
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
Caution
This is an ESD sensitive device, improper handling can cause permanent damage to the part.
9
Thermal Characteristics
Table 5. Temperature range
Symbol
Description (Rating)
Min
Max
Unit
TA
Ambient Operating Temperature Range (Automotive)
–40
125
°C
TA
Ambient Operating Temperature Range (Industrial)
–40
105
°C
TJ
Operating Junction Temperature Range
–40
150
°C
TPPRT
Peak package reflow temperature
—
260
°C
TST
Storage Temperature Range
–55
150
°C
Table 6. QFN32 thermal resistance and package dissipation ratings
Rating
Board Type
Symbol
Value
Unit
Junction to Ambient Thermal Resistance
JESD51-9, 2s2p
RθJA
36.3
°C/W
Junction-to-Top of Package Thermal Characterization
[1]
Parameter
JESD51-9, 2s2p
ΨJT
4.5
°C/W
Junction to Ambient Thermal Resistance
Customized, 2s4p
RθJA
31.7
°C/W
Junction-to-Top of Package Thermal Characterization
[1]
Parameter
Customized, 2s4p
ΨJT
4.4
°C/W
[1]
[1]
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Automotive buck regulator and controller with voltage monitors and watchdog timer
Table 6. QFN32 thermal resistance and package dissipation ratings...continued
Rating
Board Type
Symbol
Value
Unit
Junction to Ambient Thermal Resistance
Customized, 2s6p
RθJA
29.4
°C/W
Junction-to-Top of Package Thermal Characterization
[1]
Parameter
Customized, 2s6p
ΨJT
4.4
°C/W
[1]
[1]
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal
performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in
an application-specific environment. Normal practice assumes uniform heating on the die. When higher power density occurs in localized areas, there are
significant hot spots on the die.
10 Device Level Electrical Parameters
All parameters are specified at TA = –40 °C to 125 °C, VIN = 14 V, ENx = 12 V,
VCC = 5.0 V, No Load on regulators, Fsw = 450 kHz, typical external component values,
unless otherwise noted. Typical values are specified at 25 °C, unless otherwise noted.
Table 7. Device level electrical parameters
Parameter
Symbol Min
Typ
Max
Unit
VIN Rising Threshold
(minimum VIN for FS5600 to turn on)
VIN_r
—
—
5.7
V
VIN and SW1/2IN recommended operating voltage (after crossing VIN
VIN_r).
BIAS_IN = 5 V powers VCC
2.7
—
36
V
VIN and SW1/2IN recommended operating voltage (after crossing VIN
VIN_r).
[1]
BIAS_IN = 0 V.
4.4
—
36
V
Quiescent Current (non-switching), SW1 & SW2 in PFM.
BIAS_IN connected to 5 V. ULPM Mode.
Current measured at VIN
Current measured at BIAS_IN
Iq1
—
—
µA
Quiescent Current (non-switching), SW1 in PFM. SW2 disabled.
BIAS_IN connected to 5 V. ULPM Mode.
Current measured at VIN
Current measured at BIAS_IN
Iq2
—
µA
Quiescent Current (non-switching), SW2 in PFM. SW1 disabled.
BIAS_IN connected to 5 V. ULPM Mode.
Current measured at VIN
Current measured at BIAS_IN
Iq3
—
µA
Shutdown Mode quiescent current
Iq4
—
µA
[1]
16
140
—
12.5
105
—
10
100
—
7.5
In the absence of BIAS_IN, VIN falling below this voltage will cause FS5600 to power off.
FS5600
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Automotive buck regulator and controller with voltage monitors and watchdog timer
11 SW1: 36 V Integrated FET DC-DC Converter
SW1 is a 3 A integrated FET DC DC converter. Load currents of up to 3.5 A may be
drawn without entering current limit. Figure 6 shows a high-level block diagram of SW1.
EN1
SW1BOOT
VCC
SW1LX
SW1IN
Q1
SW1LX
Q2
PGND
(EPAD)
CONTROL,
DRIVER
AND
LOGIC
SW1FB
aaa-037154
Figure 6. SW1 high-level block diagram
SW1IN pins provide input power to the MOSFETs, and VCC provides the voltage needed
to drive the MOSFET gates. EN1 controls the enable of the SW1 regulator.
11.1 SW1 electrical specifications
All parameters are specified at Tj = –40 °C to 150 °C, VSW1IN = 6 V to 18 V, Vout = 5 V,
typical external component values, unless otherwise noted. Typical parameters are
specified at VSW1IN = 12 V, Tj = 25 °C unless otherwise noted.
Table 8. SW1 electrical specifications
Parameter
Symbol
Min
Typical
Max
Units
Output Voltage Accuracy
(PWM mode, SW1IN = 6 V to 18 V, 0 A =
WD_ERR_LIMIT.
Example behavior: Suppose OTP_WD_PGOODx = 1; if a watchdog error occurs during
the 1024 ms initial period, PGOODx pin is toggled, the FLT_ERR_CNT incremented,
and the watchdog restarted. This allows the system MCU to reset and try refreshing the
watchdog again. If the MCU fails continuously, the FLT_ERR_CNT reaches its limit and
the FS5600 may transition to the deep fail-safe state (if enabled) to prevent a continuous
fault loop. While in the NORMAL STATE, if a watchdog failure occurs (watchdog error
count reaches limit), PGOODx is toggled, FLT_ERR_CNT incremented and the watchdog
restarted. The state machine will return to INIT_RUN state or Deep Fail-Safe based on
the watchdog fault impact settings (independent of PGOODx behavior).
17.7 FS0B pin
The FS0B pin indicates to the system status of the various safety mechanisms being
handled by the FS5600. This includes indication of health of internal circuitry (via ABIST),
a valid watchdog, valid SW1, SW2, VMON1, VMON2, VMON3, and VMON4, valid
ERRMON, valid FCCU, and monitoring of PGOOD1/2.
The FS0B pin is released high in the NORMAL state. It is asserted low in all other states.
The FS0B pin is internally held low when a valid VIN is present with EN1 and EN2 =
Low. It is also asserted low if the VIN pin has a disconnection, provided SW1IN pin is
connected.
FS0B is a global pin, and can be pulled up to VIN if required in the system.
17.7.1 FS0B pin electrical specifications
All parameters are specified at TA = –40 °C to 125 °C, VIN = 12 V, and typical external
component values, unless otherwise noted. Typical values are specified at 25 °C, unless
otherwise noted.
Table 46. FS0B pin electrical specifications
Parameter
Symbol
FS0B_VOH (10 kohm pullup to VDDIO)
FS0B_VOH —
FS0B_VOL(10 kohm pullup to VDDIO)
FS0B_VOL
Min
0.4
Typ
Max
Unit
—
VDDIO – 0.5
V
—
—
V
17.8 PGOOD1, PGOOD2, FS0B stuck at fault check
PGOOD1, PGOOD2, and FS0B pins are continually monitored by digital to catch 'stuckat' faults. The output at these pins is compared to the internal digital command in real
time.
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Automotive buck regulator and controller with voltage monitors and watchdog timer
PGOOD1_STUCK_AT_1 = 1 indicates that PGOOD1 pin is stuck at 1.
PGOOD1_STUCK_AT_0 = 1 indicates that PGOOD1 pin is stuck at 0.
PGOOD2_STUCK_AT_1 = 1 indicates that PGOOD2 pin is stuck at 1.
PGOOD2_STUCK_AT_0 = 1 indicates that PGOOD2 pin is stuck at 0.
FS0B_STUCK_AT_1 = 1 indicates that FS0B pin is stuck at 1.
FS0B_STUCK_AT_0 = 1 indicates that FS0B pin is stuck at 0.
During ABIST, the PGOOD1, PGOOD2, and FS0B are to be checked to ensure they
are at logic low. If any of them is not at logic low during ABIST, the corresponding
'STUCK_AT_1' bit is set.
When the FS56 releases PGOOD1, PGOOD2 or FS0B high, it monitors the pin to ensure
it is at logic high. If not, the corresponding 'STUCK_AT_0' bit is set set.
Note: There is no state transition due to stuck-at-faults. The FS5600 only reports stuck
2
at faults via the corresponding I C bits. System software should evaluate the status of
these bits to control state transitions.
2
17.9 I C robustness
2
17.9.1 I C CRC verification
2
When this feature is enabled, a selectable CRC verification is performed on each I C
transaction.
When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled.
When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled.
2
After each I C transaction, the device calculates the corresponding CRC byte to ensure
the configuration command has not been corrupted.
When a CRC fault is detected, the FS5600 ignores the erroneous configuration
command and sets the CRC_I bit.
The CRC_I is cleared by writing a 1 to it.
The FS5600 implements a CRC-8-SAE, per the SAE J1850 specification.
Polynomial = 0x11D
Initial value = 0xFF
Figure 18 shows the 8-bit CRC polynomial per SAE J1850.
I2C CRS Polynominal
Seed: 1 1 1 1 1 1 1 1
MSB Data
7
6
5
4
3
2
1
0
aaa-028696
Figure 18. 8-bit CRC Polynomial
FS5600
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Automotive buck regulator and controller with voltage monitors and watchdog timer
17.9.2 NOT logic registers
To prevent unintended writes to critical registers, a required two-step writing process
must be followed.
1. Write the desired data in the REGISTER
2. Write the NOT value of Step 1 to the corresponding NOT_REGISTER
For example,
• SWx regulator will be enabled if ((SWx_EN = 1 AND NOT_SWx_EN = 0) AND (ENx pin
= HIGH)).
• SWx regulator will be disabled if ((SWx_EN = 0 AND NOT_SWx_EN = 1) OR (ENx pin
= LOW)).
A real-time XOR is performed to ensure that only complimentary register values are
accepted. Refer to Section 18 for list of registers where this feature is applicable.
2
17.10 I C Write protection
To prevent unintended writes to critical registers during system NORMAL state, certain
registers may be modified only in the INIT_RUN state. These are:
Table 47. List of registers modifiable only during INIT_RUN state
Register name
Register names (Continued)
FCCU12_BISTABLE
FCCU2_FLT_POL
FCCU1_FLT_POL
NOT_FCCU12_FLT_POL
NOT_FCCU12_BISTABLE
NOT_FCCU2_FLT_POL
NOT_FCCU1_FLT_POL
NOT_SW1_EN
SW1_EN
NOT_SW2_EN
SW2_EN
NOT_FLT_ERR_CNT_LIMIT[1:0]
FLT_ERR_CNT_LIMIT[1:0]
NOT_WD_ERR_LIMIT[1:0]
WD_ERR_LIMIT[1:0]
NOT_WD_RFR_LIMIT[1:0]
WD_RFR_LIMIT[1:0]
NOT_WD_FAIL_IMPACT[1:0]
WD_FAIL_IMPACT[1:0]
CLR_FLT_ERR_CNT
FCCU12_FLT_POL
NOT_CLR_FLT_ERR_CNT
The following registers are protected after the first WD_OK in the INIT_RUN if the
watchdog is enabled. These are:
Table 48. INIT_RUN protected registers after first WD_OK if watchdog enabled.
FS5600
Product data sheet
Register name
Register names (Continued)
FLT_ERR_CNT_LIMIT[1:0]
NOT_FLT_ERR_CNT_LIMIT[1:0]
WD_ERR_LIMIT[1:0]
NOT_WD_ERR_LIMIT[1:0]
WD_RFR_LIMIT[1:0]
NOT_WD_RFR_LIMIT[1:0]
WD_FAIL_IMPACT[1:0]
NOT_WD_FAIL_IMPACT[1:0]
CLR_FLT_ERR_CNT
NOT_CLR_FLT_ERR_CNT
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17.11 Fault error counter
A fault error counter is implemented to count the number of faults occurring in the
application and based on system reaction. The limit value of the fault error counter is
programmable using the FLT_ERR_CNT_LIMIT[1:0] bits.
Note: “FLT_ERR_CNT_LIMIT[1:0]” should be initialized in the application once during
system power-up. Changing it during normal operation may reset the FLT_ERR_CNT
value.
Table 49. FLT_ERR_CNT_LIMIT[1:0] description
FLT_ERR_CNT_LIMIT[1:0]
Configure the maximum value of the Fault
error counter
00
Max value = 1
01 (Reset State)
Max value = 2
10
Max value = 6
11
Max value = 12
The fault error counter value is stored in the FLT_ERR_CNT[3:0] bits and starts at “0”
2
after a POR. The FLT_ERR_CNT[3:0] may be cleared in the application via I C by writing
0b1 to the CLR_FLT_ERR_CNT bit and 0b0 to the NOT_CLR_FLT_ERR_CNT bit.
The FLT_ERR_CNT[3:0] decrements by '1' when the watchdog timer is refreshed after
the watchdog refresh counter reaches its maximum value.
Note: Use the CLR_FLT_ERR_CNT bit only if the watchdog is disabled. If watchdog is
enabled, use that to decrement the FLT_ERR_CNT[3:0]. Using the CLR_FLT_ERR_CNT
when watchdog is enabled is not recommended.
The fault error counter is incremented each time an assigned fault occurs.
Table 50. Fault counter source assignment
FS5600
Product data sheet
OTP bit
Fault counter configuration
OTP_SW1_FLT_CNT_EN = 1
enables SW1 OV and/or UV faults to increment
FLT_ERR_CNT if the SW1 OV and/or UV faults are
assigned to either of the PGOODx pins.
OTP_SW2_FLT_CNT_EN = 1
enables SW2 OV and/or UV faults to increment
FLT_ERR_CNT if the SW2 OV and/or UV faults are
assigned to either of the PGOODx pins.
OTP_VMON1_FLT_CNT_EN = 1
enables VMON1 OV and/or UV faults to increment
FLT_ERR_CNT if the VMON1 OV and/or UV faults are
assigned to either of the PGOODx pins.
OTP_VMON2_FLT_CNT_EN = 1
enables VMON2 OV and/or UV faults to increment
FLT_ERR_CNT if the VMON2 OV and/or UV faults are
assigned to either of the PGOODx pins.
OTP_VMON3_FLT_CNT_EN = 1
enables VMON3 OV and/or UV faults to increment
FLT_ERR_CNT if the VMON3 OV and/or UV faults are
assigned to either of the PGOODx pins.
OTP_VMON4_FLT_CNT_EN = 1
enables VMON4 OV and/or UV faults to increment
FLT_ERR_CNT if the VMON4 OV and/or UV faults are
assigned to either of the PGOODx pins.
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Table 50. Fault counter source assignment...continued
OTP bit
Fault counter configuration
[1]
increments FLT_ERR_CNT if a valid fault on the
ERRMON1 pin is detected.
OTP_ERRMON2_FLT_CNT_EN = 1
[1]
increments FLT_ERR_CNT if a valid fault on the
ERRMON2 pin is detected.
OTP_FCCU_FLT_CNT_EN = 1
increments FLT_ERR_CNT if a valid fault on the
FCCU1/FCCU2 pin is detected
OTP_ERRMON1_FLT_CNT_EN = 1
[1]
FLT_ERR_CNT increment due to an ERRMON1/2 fault occurs only in the NORMAL STATE. If a fault occurs in the
ERRMON1/2 in the INIT_RUN state, the FLT_ERR_CNT is not incremented.
17.12 Latent failure detection
17.12.1 Analog built-in self-test (ABIST)
Analog Built In Self-test (ABIST) may be enabled via OTP by setting the OTP_ABIST_EN
bit. ABIST is bypassed if OTP_ABIST_EN = 0. If enabled, the following actions are
performed.
•
•
•
•
•
CRC check on mirror registers
Checking that internal oscillators are within 15% tolerance
Checking main band gap and monitoring band gap are within 12% of each other
ABIST on SW1, SW2, VMON1, VMON2, VMON3, VMON4 voltage monitors.
Check on PGOOD1, PGOOD2, and FS0B pins (check if PGOOD1, PGOOD2, and
FS0B pins are low during ABIST)
GPIO pins when used as inputs (FCCU/ERRMON) can be checked at the system level
using real-time status registers (GPIO1/2/3_RT).
Results from ABIST are stored in registers for evaluation by the processor.
The system microcontroller shall be responsible to evaluate the ABIST results and
determine if the FS5600 can proceed to the NORMAL STATE.
Table 51. ABIST flag bits
FS5600
Product data sheet
Flag name
Description
ABIST_CRC_ERR = 1
indicates that there was an error with the CRC
values in the mirror register.
ABIST_OSC_ERR = 1
indicates that the 20 MHz oscillator is not within
15 % of its nominal value.
BG_ERR = 1
indicates that the main and monitoring band
gaps are not within 12 % of each other.
ABIST_VMON1_OV_ERR = 1
indicates that the VMON1's over voltage
monitor is not operating in the expected range.
ABIST_VMON1_UV_ERR = 1
indicates that the VMON1's under voltage
monitor is not operating in the expected range.
ABIST_VMON2_OV_ERR = 1
indicates that the VMON2's over voltage
monitor is not operating in the expected range.
ABIST_VMON2_UV_ERR = 1
indicates that the VMON2's under voltage
monitor is not operating in the expected range.
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Table 51. ABIST flag bits...continued
Flag name
Description
ABIST_VMON3_OV_ERR = 1
indicates that the VMON3's over voltage
monitor is not operating in the expected range.
ABIST_VMON3_UV_ERR = 1
indicates that the VMON3's under voltage
monitor is not operating in the expected range.
ABIST_VMON4_OV_ERR = 1
indicates that the VMON4's over voltage
monitor is not operating in the expected range.
ABIST_VMON4_UV_ERR = 1
indicates that the VMON4's under voltage
monitor is not operating in the expected range.
ABIST_SW1_OV_ERR = 1
indicates that the SW1's over voltage monitor is
not operating in the expected range.
ABIST_SW1_UV_ERR = 1
indicates that the SW1's under voltage monitor
is not operating in the expected range.
ABIST_SW2_OV_ERR = 1
indicates that the SW2's over voltage monitor is
not operating in the expected range.
ABIST_SW2_UV_ERR = 1
indicates that the SW2's under voltage monitor
is not operating in the expected range.
The above bits are all 0 if ABIST test is successful.
17.12.2 On-demand ABIST
When in the NORMAL STATE or INIT_RUN state, an application can request an ondemand ABIST to be performed by setting the OD_ABIST bit. This OD_ABIST bit is selfclearing after completing the on-demand ABIST.
FS0B is asserted low during on-demand ABIST if initiated in the INIT_RUN state.
FS0B remains high during on-demand ABIST if initiated in the NORMAL state.
17.12.3 Logical Built-In Self-Test (LBIST)
The FS5600 includes a Logical Built-In Self-Test (LBIST) feature to verify functionality of
the logic block in the FS5600.
LBIST can be disabled by setting the OTP_LBIST_DIS[7:0] to 0b0011_0110.
LBIST is enabled for all other values of OTP_LBIST_DIS[7:0]. If LBIST is disabled via
OTP, the following conditions should be valid for LBIST to be truly disabled:
• No boot error (from OTP controller)
• No CRC error (from OTP controller)
• No ECC error (from OTP controller)
2
If one of these conditions are not satisfied LBIST is enabled. LBIST_PASS bit in the I C
map is set when LBIST is completed successfully and passes.
17.12.4 VCC and VDIG monitoring
VCC and VDIG voltages are monitored for over and under voltage faults. The part is
powered down if any of these faults is detected. See the state transition table for specific
transitions.
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All parameters are specified at TA = –40 to 125 °C, VIN = 12 V, ENx = 12 V, VCC = 5.0 V,
No Load on regulators, Fsw = 2.2 MHz, and typical external component values, unless
otherwise noted. Typical values are specified at 25 °C, unless otherwise noted.
Table 52. POR Thresholds
Parameter
Symbol
Min
Typ
Max
Unit
VDIG Rising
POR
VDIG_POR
1.44
V
VDIG Falling
POR
VDIG_POR
1.40
V
VDIG
Overvoltage
Threshold
VDIG_OV
1.95
V
VCC Rising
POR
VCC_POR
3.2
V
VCC Falling
POR
VCC_POR
2.6
V
VCC
Overvoltage
Threshold
VCC_OV
5.8
V
17.13 FS5600 operation states and state machine
Figure 19 shows the high-level operation states of the FS5600 ASIL B, and Enhanced
ASIL B versions.
EN1 = EN2 = LOW
Shutdown Mode
I2
Power Down
I1
Any State after
BIST
EN1 or EN2 = HIGH
BOS and
Internal Core
Power Up
Any state after
Internal Core
Power Up
J
Wait for valid
VDIG, VCC
Thermal
Shutdown
G
NORMAL
STATE
(FS0B = 1)
K
BIST
(optional)
D1
H
ABIST/LBIST
Complete/Bypassed
Power Up
Deep Fail Safe
(FS0B = 0)
A
B
F
E1
D2
INIT_RUN
(FS0B = 0)
M
System ON
C
E2
On Demand ABIST
(FS0B = 1 for D1-E1)
(FS0B = 0 for D2-E2)
L
Transition
ULPM Mode
System OFF
aaa-037161
Figure 19. FS5600 state diagram
FS5600
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17.13.1 Shut-down mode
This is the state of the FS5600 when a valid VIN is applied, but EN1 and EN2 pins are
held low.
From one of the operation modes, (INIT_RUN/NORMAL STATE/On Demand ABIST,
Deep Fail-Safe), when EN1 and EN2 = 0, the IC enters the shut-down mode through the
'Power Down' state.
When entering the shut-down mode from INIT_RUN, NORMAL STATE or on-demand
ABIST states, the FS5600 sequences the GPOs in the reverse order of the power-up at
the appropriate time. See Section 17.13.8 for details.
For example, if OTP_GPO1_DELAY is set to 1 ms, and OTP_GPO2_DELAY is set to 5
ms:
• When EN1 = EN2 = 0, GPO2 is asserted low immediately, 4 ms after which GPO1 is
asserted low, 1 ms after which SW1 and SW2 regulators are disabled.
• FS0B is asserted low immediately after NORMAL STATE is exited.
17.13.2 Built-in self-test (BIST)
Analog Built-in self-test (ABIST) and logical built-in self-test (LBIST) are executed in this
state if enabled. This state is bypassed if both are disabled.
17.13.3 Power-up
SW1, SW2, and the various GPOs in FS5600 are powered up in this state. SW1 and
SW2 are enabled after exiting BIST or thermal shutdown and if their respective ENx
pin is held high. The power-up state exits upon completion of the highest delay among
OTP_GPO1_DELAY[2:0], OTP_GPO2_DELAY[2:0] and OTP_GPO3_DELAY[2:0].
The OTP_PGOOD1_DELAY[2:0] and OTP_PGOOD2_DELAY[2:0] timers run in parallel
to the GPO timers and do not need to expire to exit the power-up state. PGOOD1 and
PGOOD2 may be released high even in the INIT_RUN state.
17.13.4 Power-up in Debug Mode
The FS5600 offers a Debug Mode of operation that is useful during system bring up and/
or development. When in Debug Mode, the following restrictions are in place:
• Deep Fail-Safe transition is disabled
• Watchdog window duration is set to infinite
To power up in Debug Mode, apply VDDOTP_GPIO1 = 8 V before EN1 or EN2 go high
or before VIN is applied. In this condition, the FS5600 pauses power-up and waits for
VDDOTP_GPIO1 < 1 V before continuing to power up in Debug Mode. Ensure that there
is board-level isolation on the VDDOTP_GPIO1 bus if the GPIO1 function is used at a
lower voltage level.
2
While VDDOTP_GPIO1 is maintained at 8 V, the following I C commands can be sent to
open access to the OTP mirror registers:
SET_REG:FS5600:Functional:TM_ENTRY:0xD5A7
SET_REG:FS5600:Functional:TM_ENTRY:0xB8EE
SET_REG:FS5600:Functional:TM_ENTRY:0x0F37
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The mirror registers modified in this fashion take effect during power-up when
VDDOTP_GPIO < 1 V. Contact your NXP representative for commands needed to
access the mirror registers.
17.13.5 INIT_RUN
The INIT_RUN state is entered after the power-up state. Either or both SW1 and SW2
may be enabled to enter the INIT_RUN state. The state machine can remain in the
INIT_RUN state indefinitely. In this state, the state machine waits for conditions to
transition to the normal state if enabled to do so. Alternatively, the state machine may
proceed to power down to the Deep Fail-Safe state if conditions enabling this are met.
INIT_RUN state may also be entered from the normal state by setting the
GOTO_INIT_RUN and clearing the NOT_GOTO_INIT_RUN bits.
17.13.6 Normal state
In the normal state, the FS0B pin is de-asserted to indicate to the system that essential
parameters monitored by the FS5600 are in expected range. The normal state is
entered from the INIT_RUN state, provided conditions for this transition are met.
OTP_NORMAL_STATE_EN bit should be set to 1 to enable transition to the normal state.
OTP_ERRMON1_SAFE = 1 is an enabling condition for a valid ERRMON1 signal
to control transition to the normal state. OTP_ERRMON2_SAFE = 1 is an enabling
condition for a valid ERRMON2 signal to control transition to the normal state.
OTP_PGOOD1_SAFE = 1 is an enabling condition for a valid PGOOD1 output to control
transition to the normal state. OTP_PGOOD2_SAFE = 1 is an enabling condition for a
valid PGOOD2 output to control transition to the normal state.
See Section 17.13.10 for conditions to transition to the normal state.
17.13.7 Deep fail-safe state
In the deep fail-safe state, the FS5600 is shut down. All the regulators are turned off and
signal outputs are asserted low. The only way to exit deep fail-safe state is through a
power cycle on the VIN input, or if both EN1 and EN2 are pulled low in the application.
Deep fail-safe can be entered when the fault error counter reaches is maximum value, or
when a watchdog failure is programmed to go to deep fail-safe. OTP_DFS_EN must be
set to 1 to enable transition to the Deep Fail-Safe state. See Section 17.13.10 for detailed
conditions.
17.13.8 Power-down
The FS56 enters a graceful power-down when both EN1 and EN2 are asserted low in the
application.
The power-down follows a reverse of the power-up sequence for the GPOs (each
following the OTP_GPOx_DELAY[2:0] setting) followed by SW1 and/or SW2.
If entering power-down from deep fail-safe, thermal shut-down, or power-up, the state
machine immediately enters shut-down mode after SW1, SW2, and GPIOs are asserted
low (no power-down sequence).
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17.13.9 Low-power operation
There are several ways to reduce the quiescent current consumption of the FS5600.
These are:
2
• Turning off SW1 and SW2 (via I C, or using EN1/2 pins)
• Changing SW1 and SW2 operation mode from PWM to Auto Skip or PFM mode.
2
The operation mode of SW1 and SW2 may be changed using I C or by using the MODE
pin.
17.13.9.1 Ultra low-power operation
When (MODE pin =1) AND (OTP_MODE_SYNCINB_SEL[1:0] = 00) AND
(OTP_ULPM_EN = 1), the FS5600 achieves further reduction in quiescent current by
2
turning off the internal 20 MHz clock. In this condition, I C access is not available, the
watchdog timer function is not available and external voltage monitors (VMON1-4)
are disabled. PGOOD pins assigned to the external voltage monitors (VMON1-4) are
asserted low. If the respective regulator is enabled, voltage monitors for SW1 and SW2
regulators remain enabled. The OTP_ULPM_EN bit is set to 1 in the QM version of
FS5600. The user may choose its value in ASIL B and Enhanced ASIL B versions.
17.13.10 State transition table
Table 53. State transition table
Transition
Description
Transition conditions
A
Power up to INIT_RUN
Completion of SW1 soft-start (if EN1 = high)
&&
Completion of SW2 soft-start (if EN2 = high)
&&
Expiration of largest delay among OTP_GPOx_DELAY[2:0] (if GPIOx pin
used as GPO AND OTP_GPOx_DELAY[2:0] NOT EQUAL to 0b000)
Note: If one regulator is disabled, its soft-start completion signal is ignored
as a condition for this state transition.
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Automotive buck regulator and controller with voltage monitors and watchdog timer
Table 53. State transition table...continued
Transition
Description
Transition conditions
B
INIT_RUN to NORMAL
STATE
OTP_NORMAL STATE_EN = 1 &&
[
(PGOOD1 released high internally && OTP_PGOOD1_SAFE = 1) OR (OTP_
PGOOD1_SAFE = 0)
&&
(PGOOD2 released high internally && OTP_PGOOD2_SAFE = 1) OR (OTP_
PGOOD2_SAFE = 0)
&&
(OTP_GPIO1_CFG[1:0] = 0b10 && (OTP_ERRMON1_FLT_POL XOR
ERRMON1_pin) && OTP_ERRMON1_SAFE = 1) OR (OTP_GPIO1_
CFG[1:0] = 0b10 && OTP_ERRMON1_SAFE = 0)
OR (OTP_GPIO1_CFG[1:0] != 0b10)
&&
(OTP_GPIO3_CFG[1:0] = 0b10 && (OTP_ERRMON2_FLT_POL XOR
ERRMON2_pin) && OTP_ERRMON2_SAFE = 1) OR(OTP_GPIO3_
CFG[1:0] = 0b10 && OTP_ERRMON2_SAFE = 0)
OR (OTP_GPIO3_CFG[1:0] != 0b10)
]
&&
[
(OTP_MODE_SYNCINB = 1 && OTP_ULPM_EN = 1 && MODE_SYNCIN
pin = Low)
OR
(OTP_MODE_SYNCINB = 1 && OTP_ULPM_EN = 0)
OR
(OTP_MODE_SYNCINB = 0)
]
&&
[
OTP_WD_DIS = 1 OR
(Valid WD (WD_ERR_CNT = 0) && WD refreshed at least once)
]
&&
GOTO_NORMAL = 1 (set by system software)
C
NORMAL STATE to INIT_
RUN
Condition 1:
(PGOOD1 asserted low internally && OTP_PGOOD1_SAFE = 1)
C
NORMAL STATE to INIT_
RUN
Condition 2:
(PGOOD2 asserted low internally && OTP_PGOOD2_SAFE = 1)
C
NORMAL STATE to INIT_
RUN
Condition 3:
(WD Error Limit Reached (WD_ERR_CNT[1:0] >= WD_ERR_LIMIT[1:0] )
&&
WD_FAIL_IMPACT[1:0] = 01)
C
NORMAL STATE to INIT_
RUN
Condition 4:
(OTP_GPIO1_CFG[1:0] = 0b10 && OTP_ERRMON1_SAFE = 1 && Fault
Detected and no ACK)
C
NORMAL STATE to INIT_
RUN
Condition 5:
(OTP_GPIO3_CFG[1:0] = 0b10 && OTP_ERRMON2_SAFE = 1 && Fault
Detected and no ACK)
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Automotive buck regulator and controller with voltage monitors and watchdog timer
Table 53. State transition table...continued
Transition
Description
Transition conditions
C
NORMAL STATE to INIT_
RUN
Condition 6:
(OTP_MODE_SYNCINB = 1 && OTP_ULPM_EN = 1 && MODE_SYNCIN
pin = High)
C
NORMAL STATE to INIT_
RUN
Condition 7:
(FCCUxx_ERR = 1)
C
NORMAL STATE to INIT_
RUN
Condition 8:
(GOTO_INIT_RUN = 1 set by system software)
D1
NORMAL STATE to OnDemand ABIST
OD_ABIST = 1
E1
On-Demand ABIST to
NORMAL STATE
OD_ABIST = 0 (upon self-clearing after completion of On Demand ABIST)
D2
INIT_RUN to On-Demand
ABIST
OD_ABIST = 1
E2
On-Demand ABIST to INIT_ OD_ABIST = 0 (upon self-clearing after completion of On Demand ABIST)
RUN
F
INIT_RUN to Deep FailSafe
OTP_DFS_EN = 1
&&
FLT_ERR_CNT[3:0] reaches limit
G
NORMAL STATE/INIT_
RUN/On-Demand ABIST/
Deep Fail-Safe to Thermal
Shutdown
Tj > Tjmax_rise
H
Thermal Shut-down to
Power Up
Tj < Tjmax_fall
I1
Any State after BIST to
Power Down
EN1 and EN2 = 0
I2
Power Down to Shutdown
Mode
Completion of Power Down
J
Any state after Internal Core Condition 1:
Power Up up to Wait for
VCC_UV_F (VCC under-voltage)
valid VDIG, VCC
J
Any state after Internal Core Condition 2:
Power Up up to Wait for
VCC_OV_R (VCC over-voltage)
valid VDIG, VCC
J
Any state after Internal Core Condition 3:
Power Up up to Wait for
VCC_POR
valid VDIG, VCC
J
Any state after Internal Core Condition 4:
Power Up up to Wait for
VDIG_POR (includes UV on VDIG)
valid VDIG, VCC
J
Any state after Internal Core Condition 5:
Power Up up to Wait for
VDIG_OV
valid VDIG, VCC
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Table 53. State transition table...continued
Transition
Description
Transition conditions
K
NORMAL STATE to Deep
Fail Safe
OTP_DFS_EN = 1
&&
WD_ERR_CNT[1:0] >= WD_ERR_LIMIT[1:0] && WD_FAIL_IMPACT[1:0] =
0b10
L
INIT_RUN to ULPM Mode
(OTP_MODE_SYNCINB = 1 && OTP_ULPM_EN = 1 && MODE_SYNCIN
pin = High)
M
ULPM Mode to INIT_RUN
(OTP_MODE_SYNCINB = 1 && OTP_ULPM_EN = 1 && MODE_SYNCIN
pin = Low)
2
18 I C Register Map
FS5600
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 August 2022
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FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
2
Table 54. I C register map
ADDRESS Register Name
0x00
0x01
SW1CTRL
NOT_SW1CTRL
0x02
0x03
0x04
BLANK
SW2CTRL
NOT_SW2CTRL
FS5600
Product data sheet
Default
BIT15
BIT7
BIT14
BIT6
BIT13
BIT5
BIT12
BIT4
BIT11
BIT3
BIT10
BIT2
BIT9
BIT1
BIT8
BIT0
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
SW1_EN
0000_0000
—
—
—
—
—
RWOTP
RWOTP
RWOTP
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
NOT_
SW1_EN
NOT_SW1_MODE[1:0]
0000_0111
—
—
—
—
—
RWOTP
RWOTP
RWOTP
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
SW2_EN
0000_0000
—
—
—
—
—
RWOTP
RWOTP
RWOTP
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
NOT_
SW2_EN
NOT_SW2_MODE[1:0]
0000_0111
—
—
—
—
—
RWOTP
RWOTP
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 August 2022
SW1_MODE[1:0]
SW2_MODE[1:0]
RWOTP
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61 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
2
Table 54. I C register map...continued
ADDRESS Register Name
0x06
0x07
0x09
0x0A
GPIO_CTRL
NOT_
GPIO_CTRL
CLOCK_CTRL
NOT_
CLOCK_CTRL
Default
BIT15
BIT7
BIT14
BIT6
BIT13
BIT5
BIT12
BIT4
BIT11
BIT3
BIT10
BIT2
BIT9
BIT1
BIT8
BIT0
MSB
—
—
—
—
—
—
—
MODE_RT
0000_0000
—
—
—
—
—
—
—
RO
LSB
—
—
GPIO3_RT
GPIO2_RT
GPIO1_RT
GPIO3_
OUTPUT
GPIO2_
OUTPUT
GPIO1_
OUTPUT
0000_0000
—
—
RO
RO
RO
RWOTP
RWOTP
RWOTP
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
NOT_
GPIO3_
OUTPUT
NOT_
GPIO2_
OUTPUT
NOT_
GPIO1_
OUTPUT
0000_0111
—
—
—
—
—
RWOTP
RWOTP
RWOTP
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
FSS_FMOD
FSS_EN
0000_0000
—
—
RWOTP
RWOTP
RWOTP
RWOTP
RWOTP
RWOTP
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
0000_0000
—
—
—
—
MSB
0x0C
WATCHDOG
_CTRL1
FS5600
Product data sheet
WD_ERR_LIMIT[1:0]
0100_0010
RW
LSB
—
0000_0000
—
RW
—
—
CLK_FREQ[3:0]
NOT_CLK_FREQ[3:0]
RWOTP
WD_RFR_LIMIT[1:0]
RW
RW
WD_RFR_CNT[2:0]
RO
RO
RWOTP
RWOTP
—
WD_FAIL_IMPACT[1:0]
—
RWOTP
RWOTP
WD_ERR_CNT[3:0]
RO
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Rev. 3 — 2 August 2022
RWOTP
RO
RO
RO
RO
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62 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
2
Table 54. I C register map...continued
ADDRESS Register Name
Default
MSB
0x0D
NOT_
WATCHDOG
_CTRL1
BIT15
BIT7
WATCHDOG
_CTRL2
NOT_
WATCHDOG
_CTRL2
—
BIT12
BIT4
NOT_WD_RFR_LIMIT[1:0]
WATCHDOG
_SEED
Product data sheet
NOT_WD_FAIL_
IMPACT[1:0]
RW
RW
—
RWOTP
RWOTP
LSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
—
WD_WINDOW[3:0]
WDW_DC[2:0]
0011_0010
RW
RW
RW
RW
—
RW
RW
RW
LSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
—
NOT_WD_WINDOW[3:0]
NOT_WDW_DC[2:0]
1100_0101
RWP
RWP
RWP
RWP
—
RWP
RWP
RWP
LSB
—
—
—
—
—
—
—
—
0000_0100
—
—
—
—
—
—
—
—
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
0101_1010
WD_SEED[15:8]
EXTRW
EXTRW
EXTRW
LSB
0000_0000
EXTRW
EXTRW
WD_SEED[7:0]
EXTRW
EXTRW
EXTRW
EXTRW
EXTRW
WD_ANSWER[15:8]
EXTRW
EXTRW
EXTRW
LSB
0000_0000
FS5600
BIT8
BIT0
—
MSB
WATCHDOG
_ANSWER
—
BIT9
BIT1
RW
1011_0010
0x12
BIT10
BIT2
RW
MSB
0x11
BIT11
BIT3
1001_1001
MSB
0x10
BIT13
BIT5
NOT_WD_ERR_LIMIT[1:0]
MSB
0x0F
BIT14
BIT6
EXTRW
EXTRW
WD_ANSWER[7:0]
EXTRW
EXTRW
EXTRW
EXTRW
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Rev. 3 — 2 August 2022
EXTRW
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63 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
2
Table 54. I C register map...continued
ADDRESS Register Name
0x14
0x15
0x16
0x17
OD_ABIST_
CTRL
NOT_OD_ABIST
BIST_STATUS1
BIST_STATUS2
FS5600
Product data sheet
Default
BIT15
BIT7
BIT14
BIT6
BIT13
BIT5
BIT12
BIT4
BIT11
BIT3
BIT10
BIT2
BIT9
BIT1
BIT8
BIT0
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
—
—
OD_ABIST
0000_0000
—
—
—
—
—
—
—
EXTRW
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
—
—
NOT_OD_
ABIST
0000_0001
—
—
—
—
—
—
—
EXTRW
MSB
—
BG_ERR
ABIST_
SW2_
UV_ERR
ABIST_
SW2_
OV_ERR
ABIST_
SW1_
UV_ERR
ABIST_
SW1_
OV_ERR
ABIST_
VMON4_
UV_ERR
ABIST_
VMON4_
OV_ERR
0000_0000
—
RO
RO
RO
RO
RO
RO
RO
LSB
ABIST_
VMON3_
UV_ERR
ABIST_
VMON3_
OV_ERR
ABIST_
VMON2_
UV_ERR
ABIST_
VMON2_
OV_ERR
ABIST_
VMON1_
UV_ERR
ABIST_
VMON1_
OV_ERR
ABIST_
OSC_ERR
ABIST_
CRC_ERR
0000_0000
RO
RO
RO
RO
RO
RO
RO
RO
MSB
—
—
FS0B_
STUCK_
AT_0
FS0B_
STUCK_
AT_1
PGOOD2_
STUCK_
AT_0
PGOOD2_
STUCK_
AT_1
PGOOD1_
STUCK_
AT_0
PGOOD1_
STUCK_
AT_1
0000_0000
—
—
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
LSB
—
—
—
—
—
—
LBIST_
DONE
LBIST_PASS
0000_0000
—
—
—
—
—
—
RO
RO
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FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
2
Table 54. I C register map...continued
ADDRESS Register Name
0x19
0x1A
0x1C
0x1D
FAULT_CTRL
NOT_
FAULT_CTRL
VMON_STS
VMON_RT
FS5600
Product data sheet
Default
BIT15
BIT7
BIT14
BIT6
BIT13
BIT5
BIT12
BIT4
BIT11
BIT3
BIT10
BIT2
BIT9
BIT1
BIT8
BIT0
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
CLR_FLT_
ERR_CNT
0000_0001
—
EXTRW
RO
RO
RO
RO
RW
RW
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
NOT_
CLR_FLT_
ERR_CNT
—
—
—
—
NOT_FLT_ERR_
CNT_LIMIT[1:0]
0100_0010
—
EXTRW
—
—
—
—
RW
RW
MSB
—
SW2_ILIM_I
SW1_ILIM_I
TSD_I
SW2_UV_I
SW1_UV_I
VMON4_
UV_I
VMON3_
UV_I
0000_0000
—
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
LSB
VMON2_
UV_I
VMON1_
UV_I
SW2_OV_I
SW1_OV_I
VMON4_
OV_I
VMON3_
OV_I
VMON2_
OV_I
VMON1_
OV_I
0000_0000
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
FLGWC
MSB
—
SW2_
ILIM_RT
SW1_
ILIM_RT
TSD_RT
VMON4_
UV_RT
VMON3_
UV_RT
0000_0000
—
RO
RO
RO
RO
RO
RO
RO
LSB
VMON2_
UV_RT
VMON1_
UV_RT
SW2_
OV_RT
SW1_
OV_RT
VMON4_
OV_RT
VMON3_
OV_RT
VMON2_
OV_RT
VMON1_
OV_RT
0000_0000
RO
RO
RO
RO
RO
RO
RO
RO
FLT_ERR_CNT[3:0]
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Rev. 3 — 2 August 2022
FLT_ERR_CNT_LIMIT[1:0]
SW2_UV_RT SW1_UV_RT
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65 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
2
Table 54. I C register map...continued
ADDRESS Register Name
0x1E
0x21
0x22
0x24
GPIO_STS
FCCU_CFG
NOT_
FCCU_CFG
STATE_CTRL
FS5600
Product data sheet
Default
BIT15
BIT7
BIT14
BIT6
MSB
—
0000_0000
—
FLGWC
LSB
—
0000_0000
BIT13
BIT5
BIT12
BIT4
BIT11
BIT3
BIT10
BIT2
FCCU12_
ERR
—
—
FLGWC
FLGWC
—
—
FLGWC
FLGWC
—
BAD_WD_
TIMING
BAD_
WD_DATA
—
—
I2C_
CRC_ERR
I2C_
REQ_ERR
—
—
FLGWC
FLGWC
—
—
FLGWC
FLGWC
MSB
—
FCCU12_
FLT_POL
FCCU1_
FLT_POL
FCCU2_
FLT_POL
—
—
—
FCCU12_
BISTABLE
0000_0001
—
RW
RW
RW
—
—
—
RW
LSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
MSB
—
NOT_
FCCU12_
FLT_POL
NOT_
FCCU1_
FLT_POL
NOT_
FCCU2_
FLT_POL
—
—
—
NOT_
FCCU12_
BISTABLE
0111_0000
—
RW
RW
RW
—
—
—
RW
LSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
MSB
DBG_EXIT
—
—
—
—
—
—
—
0000_0000
WP
—
—
—
—
—
—
—
LSB
—
—
—
—
—
—
GOTO_
INIT_RUN
GOTO_
NORMAL
0000_0000
—
—
—
—
—
—
EXTRW
EXTRW
FCCU2_ERR FCCU1_ERR
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Rev. 3 — 2 August 2022
BIT9
BIT1
BIT8
BIT0
ERRMON2_I ERRMON1_I
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66 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
2
Table 54. I C register map...continued
ADDRESS Register Name
0x25
NOT_
STATE_CTRL
0x26
0x27
STATE
ID1
Default
BIT15
BIT7
BIT14
BIT6
BIT13
BIT5
BIT12
BIT4
BIT11
BIT3
BIT10
BIT2
BIT9
BIT1
BIT8
BIT0
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
—
—
—
NOT_
GOTO_
INIT_RUN
NOT_
GOTO_
NORMAL
0000_0011
—
—
—
—
—
—
EXTRW
EXTRW
MSB
—
—
—
—
—
—
—
—
0000_0000
—
—
—
—
—
—
—
—
LSB
—
—
—
0000_0000
—
—
—
RO
RO
MSB
—
—
0000_0000
—
—
LSB
1011_0000
0x28
FS5600
Product data sheet
ID2
PMIC_FSM[4:0]
RO
RO
FULL_LAYER_REV[2:0]
RO
RO
METAL_LAYER_REV[2:0]
RO
FAM_ID[3:0]
RO
RO
RO
RO
RO
RO
DEVICEID[3:0]
RO
RO
MSB
Reserved for NXP use.
0000_0000
Reserved for NXP use.
LSB
Reserved for NXP use.
1011_0000
Reserved for NXP use.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 August 2022
RO
RO
RO
RO
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67 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
18.1 Register descriptions
The following bit-types are used in the FS5600 register map.
Table 55. FS5600 register map bit-types
Bit type
Description
RWOTP
Read-write bit with default value loaded from
OTP
RO
Read-only
RW
Read-write capable
FLGWC
Write 1 to clear flag bit
EXTRW
Read-write bit with self-set/reset capability
18.1.1 SW1CTRL register
Table 56. SW1CTRL register description
Bit
Symbol
Description
2
SW1_EN
Switcher enable. Applied to the switcher only when SW1_EN =
NOT(NOT_SW1_EN).
1b'0 — Disable SW1.
1b'1 — SW1 Enabled provided EN1 is high.
Reset Condition — POR
1 to 0
SW1_MODE[1:0]
SW1 Operating mode. Applied to the switcher only when SW1_
MODE[1:0] = NOT(NOT_SW1_MODE[1:0]).
2b'00 — SW1 in PFM Mode.
2b'01 — Reserved.
2b'10 — Reserved.
2b'11 — SW1 in PWM mode.
Reset Condition — POR
18.1.2 NOT_SW1CTRL register
Table 57. NOT_SW1CTRL register description
Bit
Symbol
Description
2
NOT_SW1_EN
Switcher enable. Applied to the switcher only when SW1_EN =
NOT(NOT_SW1_EN).
1b'0 — See SW1_EN in SW1CTRL register.
1b'1 — See SW1_EN in SW1CTRL register.
Reset Condition — POR
1 to 0
NOT_SW1_MODE[1:0]
—
SW1 Operating Mode. Applied to the switcher only when SW1_
MODE[1:0] = NOT(NOT_SW1_MODE[1:0])
2b'00 — See SW1_MODE[1:0] in SW1CTRL register.
2b'01 — See SW1_MODE[1:0] in SW1CTRL register.
2b'10 — See SW1_MODE[1:0] in SW1CTRL register.
2b'11 — See SW1_MODE[1:0] in SW1CTRL register.
Reset — Condition POR
FS5600
Product data sheet
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Rev. 3 — 2 August 2022
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68 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
18.1.3 SW2CTRL register
Table 58. SW2CTRL register description
Bit
Symbol
Description
2
SW2_EN
Switcher enable. Applied to the switcher only when SW2_EN =
NOT(NOT_SW2_EN).
1b'0 — Disable SW2.
1b'1 — SW2 Enabled provided EN2 is high.
Reset Condition — POR
1 to 0
SW2_MODE[1:0]
SW2 Operating mode. Applied to the switcher only when SW2_
MODE[1:0] = NOT(NOT_SW2_MODE[1:0]).
2b'00 — SW2 in PFM Mode.
2b'01 — Reserved.
2b'10 — Reserved.
2b'11 — SW2 in PWM Mode.
Reset Condition — POR
18.1.4 NOT_SW2CTRL register
Table 59. NOT_SW2CTRL register description
Bit
Symbol
Description
2
NOT_SW2_EN
Switcher enable. Applied to the switcher only when SW2_EN =
NOT(NOT_SW2_EN).
1b'0 — See SW2_EN in SW2CTRL register.
1b'1 — See SW2_EN in SW2CTRL register.
Reset Condition — POR
1 to 0
NOT_SW2_MODE[1:0]
SW2 Operating mode. Applied to the switcher only when SW2_
MODE[1:0] = NOT(NOT_SW2_MODE[1:0]).
2b'00 — See SW2_MODE[1:0] in SW2CTRL register.
2b'01 — See SW2_MODE[1:0] in SW2CTRL register.
2b'10 — See SW2_MODE[1:0] in SW2CTRL register.
2b'11 — See SW2_MODE[1:0] in SW2CTRL register.
Reset Condition — POR
18.1.5 GPIO_CTRL register
Table 60. GPIO_CTRL register description
Bit
Symbol
Description
8
MODE_RT
SYNCIN_MODE input state (after deglitcher).
1b'0 — SYNCIN_MODE pin is low.
1b'1 — SYNCIN_MODE pin is high.
Reset Condition — POR
5
GPIO3_RT
GPIO3 input state (after deglitcher).
1b'0 — GPIO3 pin is low.
1b'1 — GPIO3 pin is high.
Reset Condition — POR
FS5600
Product data sheet
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Rev. 3 — 2 August 2022
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69 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
Table 60. GPIO_CTRL register description...continued
Bit
Symbol
Description
4
GPIO2_RT
GPIO2 input state (after deglitcher).
1b'0 — GPIO2 pin is low.
1b'1 — GPIO2 pin is high.
Reset Condition — POR
3
GPIO1_RT
GPIO1 input state (after deglitcher).
1b'0 — GPIO1_VDDOTP pin is low.
1b'1 — GPIO1_VDDOTP pin is high.
Reset Condition — POR
2
GPIO3_OUTPUT
GPIO3 output control if programmed as output by OTP_GPIO3_
CFG[1:0].
Applied to the output only when GPIO3_OUTPUT = NOT(NOT_
GPIO3_OUTPUT).
1b'0 — GPIO3 pin output driven low.
1b'1 — GPIO3 pin output HZ (pull-up).
Reset Condition — POR
1
GPIO2_OUTPUT
GPIO2 output control if programmed as output by OTP_GPIO2_
CFG[1:0].
Applied to the output only when GPIO2_OUTPUT = NOT(NOT_
GPIO2_OUTPUT).
1b'0 — GPIO2 pin output driven low.
1b'1 — GPIO2 pin output HZ (pull-up).
Reset Condition — POR
0
GPIO1_OUTPUT
GPIO1 output control if programmed as output by OTP_GPIO1_
CFG[1:0].
Applied to the output only when GPIO1_OUTPUT = NOT(NOT_
GPIO1_OUTPUT).
1b'0 — GPIO1_VDDOTP pin output driven low.
1b'1 — GPIO1_VDDOTP pin output HZ (pull-up) Reset Condition —
POR.
18.1.6 NOT_GPIO_CTRL register
Table 61. NOT_GPIO_CTRL register description
Bit
Symbol
Description
2
NOT_GPIO3_OUTPUT
GPIO3 output control.
1b'0 — See GPIO3_OUTPUT in GPIO_CTRL register.
1b'1 — See GPIO3_OUTPUT in GPIO_CTRL register.
Reset Condition — POR
1
NOT_GPIO2_OUTPUT
GPIO2 output control
1b'0 — See GPIO2_OUTPUT in GPIO_CTRL register.
1b'1 — See GPIO2_OUTPUT in GPIO_CTRL register.
Reset Condition — POR
0
NOT_GPIO1_OUTPUT
GPIO1 output control
1b'0 — See GPIO1_OUTPUT in GPIO_CTRL register.
1b'1 — See GPIO1_OUTPUT in GPIO_CTRL register.
Reset Condition — POR
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18.1.7 CLOCK_CTRL register
Table 62. CLOCK_CTRL register description
Bit
Symbol
Description
5
FSS_FMOD
Frequency (triangular period) of internal 20 MHz oscillator frequency
spread spectrum.
1b'0 — 23.5 kHz
1b'1 — 94 kHz
Reset Condition — POR
4
FSS_EN
Internal 20 MHz oscillator frequency spread spectrum control.
1b'0 — Frequency spread spectrum disabled.
1b'1 — Frequency spread spectrum enabled.
Reset Condition — POR
3 to 0
CLK_FREQ[3:0]
Internal 20 MHz oscillator frequency selection (Unit MHz).
Applied to the oscillator only when CLK_FREQ[3:0] = NOT(NOT_
CLK_FREQ[3:0])
4b'0000 — 20
4b'0001 — 21
4b'0010 — 22
4b'0011 — 23
4b'0100 — 24
4b'0101 — NA
4b'0110 — NA
4b'0111 — NA
4b'1000 — NA
4b'1001 — 16
4b'1010 — 17
4b'1011 — 18
4b'1100 — 19
4b'1101 — NA
4b'1110 — NA
4b'1111 — NA
Reset Condition — POR
18.1.8 NOT_CLOCK_CTRL register
Table 63. NOT_CLOCK_CTRL register description
Bit
Symbol
Description
3 to 0
NOT_CLK_FREQ[3:0]
Internal 20 MHz oscillator frequency programming (Unit MHz).
4b'0000 - 4b’1111 — See CLK_FREQ[3:0] in CLK_CTRL register.
Reset Condition — POR
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18.1.9 WATCHDOG_CTRL1 register
Table 64. WATCHDOG_CTRL1 register description
Bit
Symbol
Description
15 to 14
WD_ERR_LIMIT[1:0]
Watchdog error counter limit.
Applied only when WD_ERR_LIMIT[1:0] = NOT(NOT_WD_ERR_
LIMIT[1:0])
00 — Max value is 8.
01 — Max value is 6.
10 — Max value is 4.
11 — Max value is 2.
Reset Condition — POR
12 to 11
WD_RFR_LIMIT[1:0]
Watchdog refresh counter limit.
Applied only when WD_RFR_LIMIT[1:0] = NOT(NOT_WD_RFR_
LIMIT[1:0])
00 — Max value is 6.
01 — Max value is 4.
10 — Max value is 2.
11 — Max value is 1.
Reset Condition — POR
9 to 8
WD_FAIL_IMPACT[1:0]
Watchdog fail impact.
Applied only when WD_FAIL_IMPACT[1:0] = NOT(NOT_WD_FAIL_
IMPACT[1:0])
00 — No impact on FSM : stay in NORMAL state.
01 — Transition to INIT_RUN or remain in INIT_RUN state.
10 — Transition to DEEP_FAIL_SAFE state.
11 — No impact on FSM : stay in NORMAL state.
Reset Condition — POR
6 to 4
WD_RFR_CNT[2:0]
Watchdog refresh counter value. Resets on overflow.
3b'000 — Counter Value = 0.
3b'001 — Counter Value = 1.
3b'010 — Counter Value = 2.
3b'011 — Counter Value = 3.
3b'100 — Counter Value = 4.
3b'101 — Counter Value = 5.
3b'110 — Counter Value = 6.
3b'111 — Counter Value = 7.
Reset Condition — POR
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Table 64. WATCHDOG_CTRL1 register description...continued
Bit
Symbol
Description
3 to 0
WD_ERR_CNT[3:0]
Watchdog error counter value
4b'0000 — Counter Value = 0.
4b'0001 — Counter Value = 1.
4b'0010 — Counter Value = 2.
4b'0011 — Counter Value = 3.
4b'0100 — Counter Value = 4.
4b'0101 — Counter Value = 5.
4b'0110 — Counter Value = 6.
4b'0111 — Counter Value = 7.
4b'1000 — Counter Value = 8.
4b'1001 — Counter Value = 9.
4b'1010 — Counter Value = 10.
4b'1011 — Counter Value = 11.
4b'1100 — Counter Value = 12.
4b'1101 — Counter Value = 13.
4b'1110 — Counter Value = 14.
4b'1111 — Counter Value = 15.
Reset Condition — POR
18.1.10 NOT_WATCHDOG_CTRL1 register
Table 65. NOT_WATCHDOG_CTRL1 register description
Bit
Symbol
Description
15 to 14
NOT_WD_ERR_LIMIT[1:0]
Watchdog error counter limit.
2b'00 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register.
2b'01 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register.
2b'10 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register.
2b'11 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register.
Reset Condition — POR
12 to 11
NOT_WD_RFR_LIMIT[1:0]
Watchdog refresh counter limit.
2b'00 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register.
2b'01 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register.
2b'10 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register.
2b'11 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register.
Reset Condition — POR
9 to 8
NOT_WD_FAIL_IMPACT[1:0]
Watchdog fail impact.
2b'00 — See WD_FAIL_IMPACT[1:0] in WATCHDOG_CTRL1
register.
2b'01 — See WD_FAIL_IMPACT[1:0] in WATCHDOG_CTRL1
register.
2b'10 — See WD_FAIL_IMPACT[1:0] in WATCHDOG_CTRL1
register.
2b'11 — See WD_FAIL_IMPACT[1:0] in WATCHDOG_CTRL1
register.
Reset Condition — POR
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18.1.11 WATCHDOG_CTRL2 register
Table 66. WATCHDOG_CTRL2 register description
Bit
Symbol
Description
15 to 12
WD_WINDOW[3:0]
Watchdog window duration,
Applied only when WD_WD_WINDOW[3:0] = NOT(NOT_WD_
WINDOW[3:0])
4b'0000 — Infinite.
4b'0001 — 1 ms.
4b'0010 — 2 ms.
4b'0011 — 3 ms.
4b'0100 — 4 ms.
4b'0101 — 6 ms.
4b'0110 — 8 ms.
4b'0111 — 12 ms.
4b'1000 — 16 ms.
4b'1001 — 24 ms.
4b'1010 — 32 ms.
4b'1011 — 64 ms.
4b'1100 — 128 ms.
4b'1101 — 256 ms.
4b'1110 — 512 ms.
4b'1111 — 1024 ms.
Reset Condition — POR
10 to 8
WDW_DC[2:0]
Watchdog window duty cycle.
Applied only when WDW_DC[2:0] = NOT(NOT_WDW_DC[2:0]).
3b'000 — Closed window 31.25 % Open window 68.75 %.
3b'001 — Closed window 37.5 % Open window 62.5 %.
3b'010 — Closed window 50 % Open window 50 %.
3b'011 — Closed window 62.5 % Open window 37.5 %.
3b'100 — Closed window 68.75 % Open window 31.25 %.
3b'101 — Closed window 50 % Open window 50 %.
3b'110 — Closed window 50 % Open window 50 %.
3b'111 — Closed window 50 % Open window 50 %.
Reset Condition — POR
18.1.12 NOT_WATCHDOG_CTRL2 register
Table 67. NOT_WATCHDOG_CTRL2 register description
Bit
Symbol
Description
15 to 12
NOT_WD_WINDOW[3:0]
Watchdog window duration.
4b'0000 - 4b’1111 — See WD_WINDOW[3:0] in WATCHDOG_CTRL2
register.
Reset Condition — POR
10 to 8
NOT_WDW_DC[2:0]
Watchdog window duty cycle.
3b'000 - 3b’111 — See WDW_DC[2:0] in WATCHDOG_CTRL2
register.
Reset Condition — POR
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18.1.13 WATCHDOG_SEED register
Table 68. WATCHDOG_SEED register description
Bit
Symbol
Description
15 to 0
WD_SEED[15:0]
Watchdog seed.
WD_SEED[15:0] — Default value (after reset) is 16'h5AB2 for simple
or challenger watchdog.
It is impossible to write 16'hFFFF for challenger watchdog.
It is impossible to write 16'h0000 or 16'hFFFF for simple watchdog.
Reset Condition — POR
18.1.14 WATCHDOG_ANSWER register
Table 69. WATCHDOG_ANSWER register description
Bit
Symbol
Description
15 to 0
WD_ANSWER[15:0]
Watchdog answer.
WD_ANSWER[15:0] — For good data refresh:
• For simple watchdog WD_ANSWER = WD_SEED.
• For challenger watchdog WD_ANSWER = ~WD_SEED.
Reset Condition — POR
18.1.15 OD_ABIST_CTRL register
Table 70. OD_ABIST_CTRL register description
Bit
Symbol
Description
0
OD_ABIST
On-demand ABIST.
1b'0 — No action.
1b'1 — Start on-demand ABIST if OD_ABIST = NOT(NOT_OD_
ABIST), self cleared when ABIST is finished.
Reset Condition — POR
18.1.16 NOT_OD_ABIST register
Table 71. NOT_OD_ABIST register description
Bit
Symbol
Description
0
NOT_OD_ABIST
On-demand ABIST.
1b'0 — See OD_ABIST in OD_ABIST_CTRL register.
1b'1 — See OD_ABIST in OD_ABIST_CTRL register.
Reset Condition — POR
18.1.17 BIST_STATUS1 register
Table 72. BIST_STATUS1 register description
Bit
Symbol
Description
14
BG_ERR
Bandgap monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
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Table 72. BIST_STATUS1 register description...continued
Bit
Symbol
Description
13
ABIST_SW2_UV_ERR
Switcher SW2 undervoltage monitor ABIST status,
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
12
ABIST_SW2_OV_ERR
Switcher SW2 overvoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
11
ABIST_SW1_UV_ERR
Switcher SW1 undervoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
10
ABIST_SW1_OV_ERR
Switcher SW1 overvoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
9
ABIST_VMON4_UV_ERR
VMON4 undervoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
8
ABIST_VMON4_OV_ERR
VMON4 overvoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
7
ABIST_VMON3_UV_ERR
VMON3 undervoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
6
ABIST_VMON3_OV_ERR
VMON3 overvoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
5
ABIST_VMON2_UV_ERR
VMON2 undervoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
4
ABIST_VMON2_OV_ERR
VMON2 overvoltage monitor ABIST status
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
3
ABIST_VMON1_UV_ERR
VMON1 undervoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
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Table 72. BIST_STATUS1 register description...continued
Bit
Symbol
Description
2
ABIST_VMON1_OV_ERR
VMON1 overvoltage monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
1
ABIST_OSC_ERR
Oscillators 20 MHz / 100 kHz monitor ABIST status.
1b'0 — No error.
1b'1 — Error detected
POR
0
ABIST_CRC_ERR
OTP CRC status calculated during ABIST.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
18.1.18 BIST_STATUS2 register
Table 73. BIST_STATUS2 register description
Bit
Symbol
Description
13
FS0B_STUCK_AT_0
FS0B pin stuck at 0 flag.
1b'0 — No stuck at 0 detected.
1b'1 — Stuck at 0 detected.
Reset Condition — POR
12
FS0B_STUCK_AT_1
FS0B pin stuck at 1 flag.
1b'0 — No error.
1b'1 — Stuck at 1 detected.
Reset Condition — POR
11
PGOOD2_STUCK_AT_0
PGOOD2 pin stuck at 0 flag.
1b'0 — No stuck at 0 detected.
1b'1 — Stuck at 0 detected.
Reset Condition — POR
10
PGOOD2_STUCK_AT_1
PGOOD2 pin stuck at 1 flag.
1b'0 — No error.
1b'1 — Stuck at 1 detected.
Reset Condition — POR
9
PGOOD1_STUCK_AT_0
PGOOD1 pin stuck at 0 flag.
1b'0 — No stuck at 0 detected.
1b'1 — Stuck at 0 detected.
Reset Condition — POR
8
PGOOD1_STUCK_AT_1
PGOOD1 pin stuck at 1 flag.
1b'0 — No stuck at 1 detected.
1b'1 — Stuck at 1 detected.
Reset Condition — POR
1
LBIST_DONE
LBIST completion status.
1b'0 — LBIST did not run.
1b'1 — LBIST ran.
Reset Condition — POR
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Table 73. BIST_STATUS2 register description...continued
Bit
Symbol
Description
0
LBIST_PASS
Logic BIST status.
1b'0 — Fail or not run.
1b'1 — Logic BIST done and pass.
Reset Condition — POR
18.1.19 FAULT_CTRL register
Table 74. FAULT_CTRL register description
Bit
Symbol
Description
6
CLR_FLT_ERR_CNT
Clear fault error counter.
1b'0 — Nothing happens.
1b'1 — Clear fault error counter. Clear CLR_FLT_ERR_CNT bit.
Reset Condition — POR
5 to 2
FLT_ERR_CNT[3:0]
Fault error counter value.
4b'0000 — Counter Value = 0.
4b'0001 — Counter Value = 1.
4b'0010 — Counter Value = 2.
4b'0011 — Counter Value = 3.
4b'0100 — Counter Value = 4.
4b'0101 — Counter Value = 5.
4b'0110 — Counter Value = 6.
4b'0111 — Counter Value = 7.
4b'1000 — Counter Value = 8.
4b'1001 — Counter Value = 9.
4b'1010 — Counter Value = 10.
4b'1011 — Counter Value = 11.
4b'1100 — Counter Value = 12.
4b'1101 — Counter Value = 13.
4b'1110 — Counter Value = 14.
4b'1111 — Counter Value = 15.
Reset Condition — POR
1 to 0
FLT_ERR_CNT_LIMIT[1:0]
Fault error counter limit.
Applied only when FLT_ERR_CNT_LIMIT[1:0] = NOT(NOT_FLT_
ERR_CNT_LIMIT[1:0]).
2b'00 — Max value is 1.
2b'01 — Max value is 2.
2b'10 — Max value is 6.
2b'11 — Max value is 12.
Reset Condition — POR
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18.1.20 NOT_FAULT_CTRL register
Table 75. NOT_FAULT_CTRL register description
Bit
Symbol
Description
6
NOT_CLR_FLT_ERR_CNT
Clear fault error counter (NOT bit).
1b'0 — See CLR_FLT_ERR_CNT in FAULT_CTRL register.
1b'1 — See CLR_FLT_ERR_CNT in FAULT_CTRL register.
Reset Condition — POR
1 to 0
NOT_FLT_ERR_CNT_LIMIT[1:0]
Fault error counter limit.
2b'00 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register.
2b'01 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register.
2b'10 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register.
2b'11 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register.
Reset Condition — POR
18.1.21 VMON_STS register
Table 76. VMON_STS register description
Bit
Symbol
Description
14
SW2_ILIM_I
SW2 current limit fault.
1b'0 — No overvoltage.
1b'1 — Current limit detected.
Reset Condition — POR
13
SW1_ILIM_I
SW1 current limit fault.
1b'0 — No overvoltage.
1b'1 — Current limit detected.
Reset Condition — POR
12
TSD_I
Thermal shutdown indicator.
1b'0 — No thermal shutdown or cleared.
1b'1 — Thermal shutdown detected.
Reset Condition — POR
11
SW2_UV_I
SW2 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
10
SW1_UV_I
SW1 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
9
VMON4_UV_I
VMON4 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
8
VMON3_UV_I
VMON3 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
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Table 76. VMON_STS register description...continued
Bit
Symbol
Description
7
VMON2_UV_I
VMON2 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
6
VMON1_UV_I
VMON1 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
5
SW2_OV_I
SW2 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
4
SW1_OV_I
SW1 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
3
VMON4_OV_I
VMON4 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
2
VMON3_OV_I
VMON3 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
1
VMON2_OV_I
VMON2 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
0
VMON1_OV_I
VMON1 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
18.1.22 VMON_RT register
Table 77. VMON_RT register description
Bit
Symbol
Description
14
SW2_ILIM_RT
SW2 current limit.
1b'0 — No current limit fault.
1b'1 — Current limit exists.
Reset Condition — POR
13
SW1_ILIM_RT
SW1 current limit.
1b'0 — No current limit fault.
1b'1 — Current limit exists.
Reset Condition — POR
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Table 77. VMON_RT register description...continued
Bit
Symbol
Description
12
TSD_RT
thermal shutdown indicator.
1b'0 — No thermal shutdown or cleared.
1b'1 — Thermal shutdown detected.
Reset Condition — POR
11
SW2_UV_RT
SW2 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
10
SW1_UV_RT
SW1 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
9
VMON4_UV_RT
VMON4 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
8
VMON3_UV_RT
VMON3 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
7
VMON2_UV_RT
VMON2 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
6
VMON1_UV_RT
VMON1 monitor undervoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
5
SW2_OV_RT
SW2 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
4
SW1_OV_RT
SW1 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
3
VMON4_OV_RT
VMON4 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
2
VMON3_OV_RT
VMON3 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
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Table 77. VMON_RT register description...continued
Bit
Symbol
Description
1
VMON2_OV_RT
VMON2 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
0
VMON1_OV_RT
VMON1 monitor overvoltage.
1b'0 — No overvoltage.
1b'1 — Overvoltage detected.
Reset Condition — POR
18.1.23 GPIO_STS register
Table 78. GPIO_STS register description
Bit
Symbol
Description
14
FCCU2_ERR
FCCU2 error.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
13
FCCU1_ERR
FCCU1 error.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
12
FCCU12_ERR
FCCU12 error (bistable).
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
9
ERRMON2_I
ERRMON2 error.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
8
ERRMON1_I
ERRMON1 error.
1b'0 — No error.
1b'1 — Error detected.
Reset Condition — POR
5
BAD_WD_TIMING
Watchdog error bad timing.
1b'0 — No error.
1b'1 — Error detected, during watchdog refresh. Bad timing (wrote to
answer register in closed window or timeout).
Reset Condition — POR
4
BAD_WD_DATA
Watchdog error bad answer.
1b'0 — No error.
1b'1 — Error detected, during watchdog refresh. Bad data written in
answer register.
Reset Condition — POR
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Table 78. GPIO_STS register description...continued
Bit
Symbol
Description
1
I2C_CRC_ERR
I2C CRC error.
1b'0 — No error.
1b'1 — CRC error detected in write operation.
Reset Condition — POR
0
I2C_REQ_ERR
I2C request error.
1b'0 — No error.
1b'1 — Request error.
Reset Condition — POR
18.1.24 FCCU_CFG register
Table 79. FCCU_CFG register description
Bit
Symbol
Description
14
FCCU12_FLT_POL
FCCU bistable fault polarity.
Applied only when FCCU12_FLT_POL = NOT(NOT_FCCU12_FLT_
POL).
1b'0 — FCCU1 low or FCCU2 high is a fault.
1b'1 — FCCU1 high or FCCU2 low is a fault.
Reset Condition — POR
13
FCCU1_FLT_POL
FCCU1 fault polarity.
Applied only when FCCU1_FLT_POL = NOT(NOT_FCCU1_FLT_
POL).
1b'0 — FCCU1 low is a fault.
1b'1 — FCCU1 high is a fault.
Reset Condition — POR
12
FCCU2_FLT_POL
FCCU2 fault polarity.
Applied only when FCCU2_FLT_POL = NOT(NOT_FCCU2_FLT_
POL).
1b'0 — FCCU2 low is a fault.
1b'1 — FCCU2 high is a fault.
Reset Condition — POR
8
FCCU12_BISTABLE
FCCU1/FCCU2 bistable control.
Applied only when FCC12_BISTABLE = NOT(NOT_FCCU12_
BISTABLE).
1b'0 — Independent FCCU1/FCCU2.
1b'1 — FCCU1/FCCU2 configured as bistable.
Reset Condition — POR
18.1.25 NOT_FCCU_CFG register
Table 80. NOT_FCCU_CFG register description
Bit
Symbol
Description
14
NOT_FCCU12_FLT_POL
FCCU bistable fault polarity.
See FCCU12_FLT_POL in FCCU_CFG register.
Reset Condition — POR
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Automotive buck regulator and controller with voltage monitors and watchdog timer
Table 80. NOT_FCCU_CFG register description...continued
Bit
Symbol
Description
13
NOT_FCCU1_FLT_POL
FCCU1 fault polarity.
See FCCU1_FLT_POL in FCCU_CFG register.
Reset Condition — POR
12
NOT_FCCU2_FLT_POL
FCCU2 fault polarity.
See FCCU2_FLT_POL in FCCU_CFG register.
Reset Condition — POR
8
NOT_FCCU12_BISTABLE
FCCU1/FCCU2 bistable control.
See FCCU12_BISTABLE in FCCU_CFG register.
Reset Condition — POR
18.1.26 STATE_CTRL register
Table 81. STATE_CTRL register description
Bit
Symbol
Description
15
DBG_EXIT
Used to unlatch debug mode.
1b'0 — Nothing happens.
1b'1 — Exit debug mode.
Reset Condition — POR
1
GOTO_INIT_RUN
Go to INIT_RUN state command.
Applied only when GOTO_INIT_RUN = NOT(NOT_GOTO_INIT_
RUN).
1b'0 — Nothing happens.
1b'1 — Go to INIT_RUN state (if current state is NORMAL, bit selfcleared when in state INIT_RUN).
Reset Condition — POR
0
GOTO_NORMAL
Go to NORMAL state command.
Applied only when GOTO_NORMAL = NOT(NOT_GOTO_NORMAL).
1b'0 — Nothing happens.
1b'1 — Go to NORMAL state (if current state is INIT_RUN, bit selfcleared when in state NORMAL).
Reset Condition — POR
18.1.27 NOT_STATE_CTRL register
Table 82. NOT_STATE_CTRL register description
Bit
Symbol
Description
1
NOT_GOTO_INIT_RUN
Go to INIT_RUN state command.
1b'0 — See GOTO_INIT_RUN in STATE_CTRL register.
1b'1 — See GOTO_INIT_RUN in STATE_CTRL register.
Reset Condition — POR
0
NOT_GOTO_NORMAL
Go to NORMAL state command.
1b'0 — See GOTO_NORMAL in STATE_CTRL register.
1b'1 — See GOTO_NORMAL in STATE_CTRL register.
Reset Condition — POR
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Automotive buck regulator and controller with voltage monitors and watchdog timer
18.1.28 STATE register
Table 83. STATE register description
Bit
Symbol
Description
4 to 0
PMIC_FSM[4:0]
Indicates FSM State.
5b'00100 - ABIST
5b'00101 - Power Up
5b'01000 - Deep Fail-Safe
5b'01001 - INIT RUN
5b'01100 - NORMAL
5b'01101 - Thermal Shutdown
5b'10000 - Power Down
5b'10001 - POR
Others - Reserved
Reset Condition — POR
18.1.29 ID1 register
Table 84. ID1 register description
Bit
Symbol
Description
13 to 11
FULL_LAYER_REV[2:0]
Silicon revision identification
10 to 8
METAL_LAYER_REV[2:0]
Silicon revision identification
7 to 4
FAM_ID[3:0]
Family Id (1011 for FS56).
4b'1011 — Family Id (1011 for FS56).
Reset Condition — POR
3 to 0
DEVICEID[3:0]
Device variation identification. Defaulted to 0.
19 Typical application curves
(VIN = 12 V, Switching Frequency = 450 kHz, Hardware: KITFS5600FRDMEVM, SW1 =
5 V, SW2 = 3.3 V, Temperature = 25 C, SW1 Inductor = 6.8 μH, 14.5 mΩ, SW2 HS FET:
BUK9M9R5-40H, SW2 LS FET: BUK9M3R3, SW2 Inductor: 4.7 μH, 7.5 mΩ DCR, unless
otherwise noted..)
Figure 20. SW1 Soft-start
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Automotive buck regulator and controller with voltage monitors and watchdog timer
Figure 21. SW1 Load Transient Response
Figure 22. SW2 Load Transient Response
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Automotive buck regulator and controller with voltage monitors and watchdog timer
aaa-044949
5.1
Vout
(V)
4.9
4.7
4.5
Vout = No Load
Vout = 1 A
Vout = 2 A
Vout = 3 A
12
11
10
9
8
7
6
5
4
Vin (V)
3
Figure 23. SW1 Dropout Performance
aaa-044950
3.3
Vout
(V)
3.2
3.1
3.0
Vout = No Load
Vout = 1 A
Vout = 2 A
Vout = 3 A
12
11
10
9
8
7
6
5
4
Vin (V)
3
Figure 24. SW2 Dropout Performance
aaa-044951
100
Efficiency
(%)
90
80
70
60
Vout = 5 V
Vout = 3.3 V
0
1
2
3
Load current (A)
4
Figure 25. SW1 Efficiency (12 Vin, 450 kHz)
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Automotive buck regulator and controller with voltage monitors and watchdog timer
aaa-044952
100
Efficiency
(%)
90
80
70
60
Vout = 5 V
Vout = 3.3 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Load current (A)
Figure 26. SW2 Efficiency (12 Vin, 450 kHz)
aaa-044953
100
Efficiency
(%)
90
80
70
60
Vin = 12 V
Vin = 28 V
0
1
2
3
Load current (A)
4
Figure 27. SW1 Efficiency (5 Vout, 450 kHz)
aaa-044954
100
Efficiency
(%)
90
80
70
60
Vin = 12 V
Vin = 28 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Load current (A)
Figure 28. SW2 Efficiency (5 Vout, 450 kHz)
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Automotive buck regulator and controller with voltage monitors and watchdog timer
aaa-044955
5.0
Output
voltage
(V)
4.9
4.8
4.7
0
1
2
3
Load current (A)
4
Figure 29. SW1 Load Regulation
aaa-044956
3.35
Output
voltage
(V)
3.33
3.31
3.29
3.27
3.25
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Load current (A)
Figure 30. SW2 Load Regulation
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Automotive buck regulator and controller with voltage monitors and watchdog timer
20 Typical Application Block Diagram
Other System Loads
FS5600
Battery (< 40 V)
SW1
SW2
5.0 V
3.3 V
FS0B
PF-PMIC
PF-PMIC
Other System Loads
PGOOD1
PGOOD2
GPIO1 = ERRMON1
GPIO2 = VMON3
Misc System Voltage
GPIO3 = VMON4
Misc System Voltage
VMON1
VMON2
I2C
MCU
aaa-037163
Figure 31. Typical application block diagram
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20.1 Example power up and power down waveforms
t0
t1
t2
t3 t4 t5 t6
t7
t8
t9 t10
t11 t12
VIN
(Battery)
EN1 and EN2
VCC
BIAS_IN (applied externally)
VDIG
SW1 and SW2
PGOOD1
GPO1
GPO2
All VMONs pass.
Watchdog OK
DON'T CARE
FS0B
aaa-037164
Figure 32. Example power up and power down waveforms
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Automotive buck regulator and controller with voltage monitors and watchdog timer
21 Typical Application Schematic
pi-filter
VIN
GND
SWIN
VDDIO
GND
C19
C18
C10
10 µF
2.2 µF
2.2 µF
R20
5.1 kΩ
PGOOD2
VDDIO
EXT_CLOCK
R8
5.1 kΩ
VIN
33
SDA
R11
2.2 kΩ
VDDOTP/GPIO1
SW2COMP
R10
1.5 kΩ
C9
20 pF
450 kHz
SW2OUT
SW2FB
SW2CSN
SW2CSN
SW2CSP
SW2CSP
C11
20 nF
SW1FB
PGOOD1
PGOOD2
VDIG
BIAS_IN
VCC
R9
5.1 kΩ
25
1
24
2
23
3
22
4
21
FS5600
5
20
6
19
7
18
8
17
SW2GLS
9
GND
26
SW1OUT
VIN
10
11
12
13
14
15
FS0B
FS0B
EN1
EN1
EN2
EN2
SW1LX
SW1LX
SW1IN
SW1BOOT
SWIN
SW2LX
6
LPRE1
16
Vp
Vq
3
GND
Vr
Vs
VMON3
R19
5.1 kΩ
VMON4
R18
5.1 kΩ
GND
4
SW2OUT
C14
22 µF
BUK9K18-40E
Q1
VMON2
R14
5.1 kΩ
R16
5.1 kΩ
0.010
R15
5.1 kΩ
VMON1
GND
R17
5.1 kΩ
2
GND
R13
5.1 kΩ
VMON2
1
C2
22 µF
GND
R12
5.1 kΩ
GND
2
C1
22 µF
C3
10 µF
4.7 µH
5
C13
10 µF
1
C17
0.1 µF
VMON1
RSNS1
SW1OUT
SWIN
C12
0.1 µF
SW2GLS
2
4.7 µH
VMON4
SW2LX
L1
1
SW1IN
VMON3
SW2GLS
SW1LX
VMON1
2.2 kΩ
27
VMON2
R6
28
GPIO2_VMON3
SCL
29
GPIO3_VMON4
2.2 kΩ
30
SW2BOOT
R5
31
SW2GHS
GND
32
SW2LX
VDDIO
Used as GPO
in system
U2
EP
GND
VIN
VDDIO
C6
0.1 µF
PGOOD1
SYNCIN/MODE
C4
4.7 µF
C15
22 µF
C16
22 µF
SW2CSP
2
1
4
3
SW2CSN
GND
GND
SW2GLS
SW2GHS
aaa-037162
Figure 33. Typical application schematic
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22 Package Outlines
22.1 Package outline – ES version (wettable flank)
Figure 34. Package outline HVQFN32 (SOT617-24(SC)) – ES version (wettable flank)
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Figure 35. Package outline detail HVQFN32 (SOT617-24(SC)) – ES version (wettable flank)
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Figure 36. PCB design guidelines – solder mask opening pattern for HVQFN32
(SOT617-24(SC)) – ES version (wettable flank)
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Figure 37. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) –
ES version (wettable flank)
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Figure 38. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) –
ES version (wettable flank)
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Figure 39. Package outline note HVQFN32 (SOT617-24(SC)) – ES version (wettable flank)
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22.2 Package outlines – EP version (non-wettable flank)
Figure 40. Package outline HVQFN32 (SOT617-24(SC)) – EP version (non-wettable flank)
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Figure 41. Package outline detail HVQFN32 (SOT617-24(SC)) – EP version (non-wettable
flank)
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Figure 42. PCB design guidelines – solder mask opening pattern for HVQFN32
(SOT617-24(SC)) – EP version (non-wettable flank)
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Figure 43. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) –
EP version (non-wettable flank)
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Figure 44. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) –
EP version (non-wettable flank)
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Figure 45. Package outline note HVQFN32 (SOT617-24(SC)) – EP version (non-wettable
flank)
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23 Revision History
Table 85. Revision history
Document ID
Release
date
FS5600 v.3
20220802 Product data sheet
Modifications
• In Section 2, added up to 15 A load capability for Buck Controller - External FET
• In Figure 1, under SW@ - Buck Controller, changed >10 A to up to 15 A
• In Section 10, added this note below the table: In the absence of BIAS_IN, VIN falling below this
voltage will cause FS5600 to power off
• In Section 12.1, corrected the units of Error Amplifier Transconductance from ms to mS
• In Section 12.2.1, added this to the end of the paragraph after the first table: When operating at 450
kHz or lower, by choosing low Rds(on) MOSFETs in separate packages, and with a low DCR inductor,
SW2 can be designed to support loads of up to 15 A. Refer to the schematic of KITFS5600FRDMEVM
for a design that can support 15 A.
• Reorganized Section 12, adding Section 12.2.1.2 material
• In Section 12.2.1.1, added Use closest standard values for resistor and capacitors to the end of the
section
• In Section 17.6.1, added PGOODx toggle due to a before watchdog failure
• In Section 17.13.7, changed OTP_DFN_EN to OTP_DFS_EN
• Added Section 19
• In Figure 11, in the Divider 1 box, changed /8 to /7. In the Divider 2 box, changed /48 to /44.
• In Figure 33, made these pin numbering changes at the lower left:
Swap 5-6
Swap 4-2
Swap 3-1
FS5600 v.2
20210601 Product data sheet
Modifications
Moved from Objective status to Product status
FS5600 v.1
20201029 Objective data sheet
Modifications
Initial release
FS5600
Product data sheet
Data sheet status
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 August 2022
Change notice
Supersedes
CIN# 202202008I
v.2
—
v.1
—
—
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24 Legal information
24.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
24.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
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Limited warranty and liability — Information in this document is believed
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Notwithstanding any damages that customer might incur for any reason
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Applications — Applications that are described herein for any of these
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NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
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make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
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NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
Security — Customer understands that all NXP products may be subject to
unidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the design
and operation of its applications and products throughout their lifecycles
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or
proprietary technologies supported by NXP products for use in customer’s
applications. NXP accepts no liability for any vulnerability. Customer should
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make the
ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may be
provided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.
Suitability for use in automotive applications (functional safety) —
This NXP product has been qualified for use in automotive applications.
It has been developed in accordance with ISO 26262, and has been
ASIL classified accordingly. If this product is used by customer in the
development of, or for incorporation into, products or services (a) used in
safety critical applications or (b) in which failure could lead to death, personal
injury, or severe physical or environmental damage (such products and
services hereinafter referred to as “Critical Applications”), then customer
makes the ultimate design decisions regarding its products and is solely
responsible for compliance with all legal, regulatory, safety, and security
related requirements concerning its products, regardless of any information
or support that may be provided by NXP. As such, customer assumes all
risk related to use of any products in Critical Applications and NXP and
its suppliers shall not be liable for any such use by customer. Accordingly,
customer will indemnify and hold NXP harmless from any claims, liabilities,
damages and associated costs and expenses (including attorneys’ fees)
that NXP may incur related to customer’s incorporation of any product in a
Critical Application.
24.4 Trademarks
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
SafeAssure — is a trademark of NXP B.V.
FS5600
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 August 2022
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107 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Tab. 31.
Tab. 32.
Tab. 33.
Tab. 34.
Tab. 35.
Tab. 36.
Tab. 37.
Tab. 38.
Tab. 39.
Tab. 40.
Tab. 41.
Tab. 42.
Tab. 43.
Tab. 44.
Device options ...................................................2
Ordering information ..........................................3
Pin description ...................................................6
ESD ratings ....................................................... 8
Temperature range ............................................ 8
QFN32 thermal resistance and package
dissipation ratings ............................................. 8
Device level electrical parameters .....................9
SW1 electrical specifications ...........................10
SW1 external component selection .................11
OTP_SW1_VOLT[7:0] selection ...................... 12
OTP_SW1_MIN_TON[1:0] selection ............... 15
SW1_MODE[1:0] selection. .............................15
OTP_SW1_PFM_TON[1:0] selection .............. 16
SW1 compensation selection .......................... 16
OTP_SW1_SLOPECOMP[1:0] Value ..............17
OTP_SW1_GM_COMP[1:0] Value .................. 17
OTP_SW1_PWM_R_COMP[2:0] Value .......... 17
SW2 electrical characteristics ......................... 19
SW2 recommended external components .......20
MOSFET selection .......................................... 21
SW2 Compensation selection ......................... 21
OTP_SW2_VOLT[5:0] Selection ..................... 23
OTP_SW2_TON_MIN[1:0] Selection ...............25
SW2_MODE[2:0] selection ..............................25
OTP_SW2_PFM_TON[1:0] Selection ..............26
OTP_SW2_SLOPECOMP[5:0] selection .........26
FS5600 clock electrical characteristics ............29
Internal oscillator frequency selection ............. 30
SW1 and SW2 switching frequency
selection .......................................................... 31
I/O pin electrical specifications ........................32
PGOOD1/2, GPIO1/2/3 delay selection .......... 34
I2C address selection ......................................35
Thermal protection characteristics ...................35
GPIO1 function selection ................................ 36
GPIO2 function selection ................................ 36
GPIO3 function selection ................................ 37
VMON1-4 electrical specifications ...................37
Watchdog window period configuration ........... 40
Watchdog window duty cycle configuration ..... 41
Watchdog error counter ...................................42
WD_FAIL_IMPACT[1:0] description .................42
Watchdog refresh counter configuration ..........43
FCCU1/2 status reporting error scenarios ....... 45
ERRMON acknowledge timer selection .......... 46
Tab. 45.
Tab. 46.
Tab. 47.
Tab. 48.
Tab. 49.
Tab. 50.
Tab. 51.
Tab. 52.
Tab. 53.
Tab. 54.
Tab. 55.
Tab. 56.
Tab. 57.
Tab. 58.
Tab. 59.
Tab. 60.
Tab. 61.
Tab. 62.
Tab. 63.
Tab. 64.
Tab. 65.
Tab. 66.
Tab. 67.
Tab. 68.
Tab. 69.
Tab. 70.
Tab. 71.
Tab. 72.
Tab. 73.
Tab. 74.
Tab. 75.
Tab. 76.
Tab. 77.
Tab. 78.
Tab. 79.
Tab. 80.
Tab. 81.
Tab. 82.
Tab. 83.
Tab. 84.
Tab. 85.
PGOOD1/2 programmable reactions .............. 47
FS0B pin electrical specifications ....................48
List of registers modifiable only during
INIT_RUN state ............................................... 50
INIT_RUN protected registers after first
WD_OK if watchdog enabled. ......................... 50
FLT_ERR_CNT_LIMIT[1:0] description ........... 51
Fault counter source assignment .................... 51
ABIST flag bits ................................................ 52
POR Thresholds ..............................................54
State transition table ....................................... 57
I2C register map ............................................. 61
FS5600 register map bit-types ........................ 68
SW1CTRL register description ........................68
NOT_SW1CTRL register description .............. 68
SW2CTRL register description ........................69
NOT_SW2CTRL register description .............. 69
GPIO_CTRL register description .....................69
NOT_GPIO_CTRL register description ........... 70
CLOCK_CTRL register description ................. 71
NOT_CLOCK_CTRL register description ........ 71
WATCHDOG_CTRL1 register description ....... 72
NOT_WATCHDOG_CTRL1 register
description ....................................................... 73
WATCHDOG_CTRL2 register description ....... 74
NOT_WATCHDOG_CTRL2 register
description ....................................................... 74
WATCHDOG_SEED register description .........75
WATCHDOG_ANSWER register
description ....................................................... 75
OD_ABIST_CTRL register description ............ 75
NOT_OD_ABIST register description ..............75
BIST_STATUS1 register description ................75
BIST_STATUS2 register description ................77
FAULT_CTRL register description ...................78
NOT_FAULT_CTRL register description ......... 79
VMON_STS register description ..................... 79
VMON_RT register description ....................... 80
GPIO_STS register description ....................... 82
FCCU_CFG register description ..................... 83
NOT_FCCU_CFG register description ............ 83
STATE_CTRL register description ...................84
NOT_STATE_CTRL register description ......... 84
STATE register description ..............................85
ID1 register description ................................... 85
Revision history ............................................. 105
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
FS5600 Functional block diagram .....................2
FS5600 internal block diagram ......................... 4
Regulator input options ..................................... 4
QM version pinout .............................................5
ASIL B, and enhanced ASIL B version
pinout .................................................................5
FS5600
Product data sheet
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
SW1 high-level block diagram .........................10
SW1 output voltage setting using an
external resistor divider ................................... 12
SW2 high-level block diagram .........................19
SW2 application schematic with Rshunt
current sensing ................................................22
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Rev. 3 — 2 August 2022
© 2022 NXP B.V. All rights reserved.
108 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
Fig. 31.
Fig. 32.
Fig. 33.
Fig. 34.
Fig. 35.
DCR current sense with a single capacitor ......22
Clock management system high-level block
diagram ............................................................29
Windowed watchdog concept ..........................40
Challenger watchdog formula ..........................42
Watchdog error counter configurations ............43
Watchdog refresh counter configurations ........ 44
FCCU 1/2 bi-stable protocol example ............. 44
Low-level ERRMONx detected as error .......... 46
8-bit CRC Polynomial ......................................49
FS5600 state diagram .....................................54
SW1 Soft-start .................................................85
SW1 Load Transient Response ...................... 86
SW2 Load Transient Response ...................... 86
SW1 Dropout Performance ............................. 87
SW2 Dropout Performance ............................. 87
SW1 Efficiency (12 Vin, 450 kHz) ................... 87
SW2 Efficiency (12 Vin, 450 kHz) ................... 88
SW1 Efficiency (5 Vout, 450 kHz) ................... 88
SW2 Efficiency (5 Vout, 450 kHz) ................... 88
SW1 Load Regulation ..................................... 89
SW2 Load Regulation ..................................... 89
Typical application block diagram ....................90
Example power up and power down
waveforms ....................................................... 91
Typical application schematic ..........................92
Package outline HVQFN32
(SOT617-24(SC)) – ES version (wettable
flank) ................................................................93
Package outline detail HVQFN32
(SOT617-24(SC)) – ES version (wettable
flank) ................................................................94
FS5600
Product data sheet
Fig. 36.
Fig. 37.
Fig. 38.
Fig. 39.
Fig. 40.
Fig. 41.
Fig. 42.
Fig. 43.
Fig. 44.
Fig. 45.
PCB design guidelines – solder
mask opening pattern for HVQFN32
(SOT617-24(SC)) – ES version (wettable
flank) ................................................................95
PCB guidelines – I/O pads and solderable
area for HVQFN32 (SOT617-24(SC)) – ES
version (wettable flank) ................................... 96
PCB design guidelines – solder paste
stencil for HVQFN32 (SOT617-24(SC)) –
ES version (wettable flank) ............................. 97
Package outline note HVQFN32
(SOT617-24(SC)) – ES version (wettable
flank) ................................................................98
Package outline HVQFN32
(SOT617-24(SC)) – EP version (nonwettable flank) ................................................. 99
Package outline detail HVQFN32
(SOT617-24(SC)) – EP version (nonwettable flank) ............................................... 100
PCB design guidelines – solder
mask opening pattern for HVQFN32
(SOT617-24(SC)) – EP version (nonwettable flank) ............................................... 101
PCB guidelines – I/O pads and solderable
area for HVQFN32 (SOT617-24(SC)) – EP
version (non-wettable flank) .......................... 102
PCB design guidelines – solder paste
stencil for HVQFN32 (SOT617-24(SC)) –
EP version (non-wettable flank) .................... 103
Package outline note HVQFN32
(SOT617-24(SC)) – EP version (nonwettable flank) ............................................... 104
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 August 2022
© 2022 NXP B.V. All rights reserved.
109 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
Contents
1
2
2.1
3
4
5
6
7
8
9
10
11
General Description ............................................ 1
Features and Benefits ........................................ 1
Overview ............................................................ 2
Applications .........................................................2
Ordering Information .......................................... 2
FS5600 Internal Block Diagram ......................... 4
Regulator Input Configurations ......................... 4
Pinout and Pin Description ................................ 5
ESD Ratings ........................................................ 8
Thermal Characteristics ..................................... 8
Device Level Electrical Parameters ...................9
SW1: 36 V Integrated FET DC-DC
Converter ........................................................... 10
11.1
SW1 electrical specifications ........................... 10
11.2
SW1 external component selection ................. 11
11.3
SW1 operation .................................................11
11.3.1
Output voltage selection .................................. 11
11.3.2
PFM and pulse skipping operation .................. 15
11.3.3
PFM operation ................................................. 15
11.3.4
Soft-start .......................................................... 16
11.3.5
Current limit protection .................................... 16
11.3.6
Compensation selection .................................. 16
11.3.7
SW1 fault monitoring ....................................... 17
12
SW2: 36 V DC-DC Controller with External
FETs ....................................................................19
12.1
SW2 electrical characteristics ..........................19
12.2
SW2 operation .................................................20
12.2.1
SW2 external component selection ................. 20
12.2.1.1 Compensation network .................................... 21
12.2.1.2 Inductor current sense selection ......................21
12.2.2
Output voltage selection .................................. 23
12.2.3
Pulse skipping operation ................................. 25
12.2.4
PFM operation ................................................. 25
12.2.5
Soft-start .......................................................... 26
12.2.6
Current limit protection .................................... 26
12.2.7
Slope compensation ........................................ 26
12.2.8
SW2 fault monitoring ....................................... 28
13
BIAS_IN Input .................................................... 28
14
FS5600 Clock Management ..............................28
14.1
FS5600 clock electrical characteristics ............ 29
14.2
High frequency oscillator ................................. 30
14.3
Spread spectrum ............................................. 30
14.4
SW1 and SW2 switching frequency
selection ...........................................................31
14.5
External clock synchronization ........................ 31
14.6
SYNCOUT function settings ............................ 32
15
I/O Pins in FS5600 ............................................ 32
15.1
I/O pins electrical specifications .......................32
15.2
EN1 and EN2 .................................................. 33
15.2.1
Programming turn-off delay ............................. 33
15.3
PGOOD1 and PGOOD2 ..................................33
15.4
GPIO1/2/3 ........................................................ 33
15.5
MODE pin ........................................................ 34
15.6
I2C communication .......................................... 35
16
Thermal Protection ........................................... 35
17
Functional safety features in FS5600 .............. 35
FS5600
Product data sheet
17.1
17.2
17.2.1
17.3
17.3.1
17.3.2
17.3.3
17.3.4
17.4
17.4.1
GPIO1/2/3 feature selection ............................ 36
OV/UV monitors ...............................................37
VMON1-4 electrical specifications ................... 37
Watchdog ......................................................... 39
Simple watchdog ............................................. 41
Challenger watchdog ....................................... 41
Watchdog error counter and error impact ........ 42
Watchdog refresh counter ............................... 43
FCCU monitoring ............................................. 44
BI_STABLE protocol with FCCU1 and
FCCU2 ............................................................. 44
17.4.2
Single/independent FCCU monitoring ............. 45
17.4.3
FCCU status reporting via interrupt register .....45
17.5
External signal monitoring using ERRMON ..... 45
17.6
PGOOD1/2 programmable reactions for
ASIL B and Enhanced ASIL B versions ........... 47
17.6.1
Watchdog impact on PGOOD1/2 .....................48
17.7
FS0B pin ..........................................................48
17.7.1
FS0B pin electrical specifications .................... 48
17.8
PGOOD1, PGOOD2, FS0B stuck at fault
check ................................................................48
17.9
I2C robustness ................................................ 49
17.9.1
I2C CRC verification ........................................ 49
17.9.2
NOT logic registers ..........................................50
17.10
I2C Write protection .........................................50
17.11
Fault error counter ...........................................51
17.12
Latent failure detection .................................... 52
17.12.1 Analog built-in self-test (ABIST) .......................52
17.12.2 On-demand ABIST .......................................... 53
17.12.3 Logical Built-In Self-Test (LBIST) .....................53
17.12.4 VCC and VDIG monitoring .............................. 53
17.13
FS5600 operation states and state machine ....54
17.13.1 Shut-down mode ............................................. 55
17.13.2 Built-in self-test (BIST) .....................................55
17.13.3 Power-up ..........................................................55
17.13.4 Power-up in Debug Mode ................................55
17.13.5 INIT_RUN ........................................................ 56
17.13.6 Normal state .................................................... 56
17.13.7 Deep fail-safe state ......................................... 56
17.13.8 Power-down ..................................................... 56
17.13.9 Low-power operation ....................................... 57
17.13.9.1 Ultra low-power operation ................................57
17.13.10 State transition table ........................................57
18
I2C Register Map ...............................................60
18.1
Register descriptions ....................................... 68
18.1.1
SW1CTRL register ...........................................68
18.1.2
NOT_SW1CTRL register ................................. 68
18.1.3
SW2CTRL register ...........................................69
18.1.4
NOT_SW2CTRL register ................................. 69
18.1.5
GPIO_CTRL register ....................................... 69
18.1.6
NOT_GPIO_CTRL register .............................. 70
18.1.7
CLOCK_CTRL register .................................... 71
18.1.8
NOT_CLOCK_CTRL register ...........................71
18.1.9
WATCHDOG_CTRL1 register ..........................72
18.1.10 NOT_WATCHDOG_CTRL1 register ................ 73
18.1.11 WATCHDOG_CTRL2 register ..........................74
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Rev. 3 — 2 August 2022
© 2022 NXP B.V. All rights reserved.
110 / 111
FS5600
NXP Semiconductors
Automotive buck regulator and controller with voltage monitors and watchdog timer
18.1.12 NOT_WATCHDOG_CTRL2 register ................ 74
18.1.13 WATCHDOG_SEED register ........................... 75
18.1.14 WATCHDOG_ANSWER register ..................... 75
18.1.15 OD_ABIST_CTRL register ...............................75
18.1.16 NOT_OD_ABIST register ................................ 75
18.1.17 BIST_STATUS1 register .................................. 75
18.1.18 BIST_STATUS2 register .................................. 77
18.1.19 FAULT_CTRL register ..................................... 78
18.1.20 NOT_FAULT_CTRL register ............................ 79
18.1.21 VMON_STS register ........................................ 79
18.1.22 VMON_RT register .......................................... 80
18.1.23 GPIO_STS register ..........................................82
18.1.24 FCCU_CFG register ........................................ 83
18.1.25 NOT_FCCU_CFG register ...............................83
18.1.26 STATE_CTRL register ..................................... 84
18.1.27 NOT_STATE_CTRL register ............................ 84
18.1.28 STATE register .................................................85
18.1.29 ID1 register ...................................................... 85
19
Typical application curves ............................... 85
20
Typical Application Block Diagram ................. 90
20.1
Example power up and power down
waveforms ........................................................91
21
Typical Application Schematic .........................92
22
Package Outlines .............................................. 93
22.1
Package outline – ES version (wettable
flank) ................................................................ 93
22.2
Package outlines – EP version (nonwettable flank) ................................................. 99
23
Revision History ..............................................105
24
Legal information ............................................ 106
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© 2022 NXP B.V.
All rights reserved.
For more information, please visit: http://www.nxp.com
Date of release: 2 August 2022
Document identifier: FS5600
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