NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX8MNIEC
Rev. 1, 03/2021
MIMX8MN6CVTIZAA
MIMX8MN4CVTIZAA
MIMX8MN2CVTIZAA
MIMX8MN5CVPIZAA
MIMX8MN1CVPIZAA
i.MX 8M Nano
Applications Processor
Datasheet for Industrial
Products
MIMX8MN5CVTIZAA
MIMX8MN3CVTIZAA
MIMX8MN1CVTIZAA
MIMX8MN3CVPIZAA
Package Information
Plastic Package
FCBGA 14 x 14 mm, 0.5 mm pitch
FCBGA 11 x 11 mm, 0.5 mm pitch
Ordering Information
See Table 3 on page 6
1
i.MX 8M Nano introduction
The i.MX 8M Nano application processor represents
NXP’s latest graphics and audio experience combining
state-of-the-art
media-specific
features
with
high-performance processing while optimized for lowest
power consumption.
The i.MX 8M Nano family of processors features
advanced implementation of a quad Arm® Cortex®-A53 core, which operates at speeds of up to
1.4 GHz. A general purpose Cortex®-M7 running up to
750 MHz core processor is for real-time and low-power
processing.
The i.MX 8M Nano family of processors provides additional computing resources and peripherals:
• Advanced security modules for secure boot,
cipher acceleration and DRM support
• A wide range of audio interfaces, including I2S,
AC 97, TDM, and S/PDIF
• Large set of peripherals that are commonly used
in consumer/industrial market, including USB
and Ethernet
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
© 2019-2021 NXP Semiconductors All rights reserved.
1. i.MX 8M Nano introduction . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Recommended connections for unused input/output
12
3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 14
3.2. Power supplies requirements and restrictions . . . 27
3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 33
3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 36
3.7. Output buffer impedance parameters . . . . . . . . . 37
3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 39
3.9. External peripheral interface parameters . . . . . . 40
4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 74
4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 74
4.2. Boot device interface allocation . . . . . . . . . . . . . . 74
5. Package information and contact assignments . . . . . . . 76
5.1. 14 x 14 mm package information . . . . . . . . . . . . 76
5.2. 11 x 11 mm package information . . . . . . . . . . . . 92
5.3. DDR pin function list . . . . . . . . . . . . . . . . . . . . . 107
6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
i.MX 8M Nano introduction
Table 1. Features
Subsystem
Cortex®-A53 MPCore platform
Feature
Quad symmetric Cortex® -A53 processors
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Media Processing Engine (MPE) with Arm® NEONTM technology supporting the
Advanced Single Instruction Multiple Data architecture:
• Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture
Support of 64-bit Arm®v8-A architecture
512 KB unified L2 cache
Cortex®-M7 core platform
Low power microcontroller available for customer application:
• low power standby mode
• IoT features including Weave
• Manage IR or wireless remote
• ML inference applications (enhanced for i.MX 8M Nano)
Cortex® M7 CPU:
• 256 KB tightly coupled memory (TCM)
Connectivity
One USB 2.0 OTG controllers with integrated PHY interfaces:
• Spread spectrum clock support
Three Ultra Secure Digital Host Controller (uSDHC) interfaces:
• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec
• SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100
MB/sec
• Support for SDXC (extended capacity)
One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),
Ethernet AVB, and IEEE 1588
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Four I2C modules
Three SPI modules
On-chip memory
Boot ROM (256 KB)
On-chip RAM (512 KB + 32 KB)
GPIO and pin multiplexing
General-purpose input/output (GPIO) modules with interrupt capability
Input/output multiplexing controller (IOMUXC) to provide centralized pad control
Power management
Temperature sensor with programmable trip points
Flexible power domain partitioning with internal power switches to support efficient
power management
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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NXP Semiconductors
i.MX 8M Nano introduction
Table 1. Features (continued)
Subsystem
External memory interface
Feature
16-bit DRAM interfaces:
• LPDDR4-3200
• DDR4-2400
• DDR3L-1600
8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
eMMC 5.1 Flash (3 interfaces)
SPI NOR Flash (3 interfaces)
QuadSPI Flash with support for XIP (for Cortex®-M7 in low-power mode) and parallel
read mode of two identical FLASH devices
Multimedia
Graphic Processing Unit:
• GC7000UL with OpenCL and Vulkan support
• 2 shader
• 99.8 million triangles/sec
• 0.6 giga pixel/sec
• 9.6 GFLOPs 32-bit/19.2 GFLOPs 16-bit
• Supports OpenGL ES 1.1, 2.0, 3.0, OpenCL
• Core clock frequency of 600 MHz
• Shader clock frequency of 600 MHz
LCDIF Display Controller:
• Support up to 1080p60 display through MIPI DSI
MIPI Interfaces:
• 4-lane MIPI DSI interface
• 4-lane MIPI CSI interface
Audio:
• S/PDIF input and output, including a raw capture input mode
• Five external synchronous audio interface (SAI) modules supporting I2S, AC97,
TDM, codec/DSP, and DSD interfaces, comprising one SAI with 4 Tx and 4 Rx
lanes, two SAI with 2 Tx and 2 Rx lanes, and two SAI with 1 Tx and 1Rx lane. All
ports support 49.152 MHz BCLK.
• ASRC supports processing 32 audio channels, 4 context groups, 8 kHz to 384 kHz
sample rate and 1/16 to 8x sample rate conversion ratio.
• Pulse Density Modulation (PDM) input
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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3
i.MX 8M Nano introduction
Table 1. Features (continued)
Subsystem
Security
Feature
Resource Domain Controller (RDC):
• supports 4 domains and up to 8 regions of DDR
Arm® TrustZone® (TZ) architecture:
• Arm® Cortex-A53 MPCore TrustZone support
On-chip RAM (OCRAM) secure region protection using OCRAM controller
High Assurance Boot (HAB)
Cryptographic acceleration and assurance module (CAAM):
• Support Widevine and PlayReady content protection
• Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms
• Real-time integrity checker (RTIC)
• DRM support for RSA, AES, 3DES, DES
• Side channel attack resistance
• True random number generation (RNG)
• Manufacturing protection support
Secure non-volatile storage (SNVS):
• Secure real-time clock (RTC)
Secure JTAG controller (SJC)
System debug
Arm® CoreSightTM debug and trace technology
Trace Port Interface Unit (TPIU) to support off-chip real-time trace
Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering
Unified trace capability for Quad Cortex®-A53 and Cortex®-M7 CPUs
Cross Triggering Interface (CTI)
Support for 4-pin (JTAG) debug interface
NOTE
The actual feature set depends on the part numbers as described in Table 3.
Functions such as display and camera interfaces, and connectivity
interfaces, may not be enabled for specific part numbers.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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NXP Semiconductors
i.MX 8M Nano introduction
1.1
Block diagram
Figure 1 shows the functional modules in the i.MX 8M Nano applications processor system.
Security
TrustZone
DRM Ciphers
Secure Clock
Main CPU Platform
Connectivity
Quad Cortex®-A53
1 GB Ethernet
(IEEE1588, EEE, and AVB)
32 KB I-cache
32 KB D-cache
NEON
S/PDIF Rx and Tx
FPU
5x I2S/SAI
eFuse Key Storage
512 KB L2 Cache
Random Number
32 KB Secure RAM
Low Power, Security CPU
1x USB 2.0 OTG and PHY
PDM
Cortex®-M7
4x UART
System Control
256 KB TCM
4x I2C
3x Smart DMA
XTAL
PLLs
Multimedia
3D Graphics: GC7000UL
3x SPI
External Memory
3x Watchdog
LPDDR4/DDR4/DDR3L
4x PWM
4-lane MIPI-DSI Interface
eMMC 5.1/SD 3.0
6x Timer
4-lane MIPI-CSI Interface
Secure JTAG
NAND CTL (BCH62)
Temperature Sensor
ASRC
Dual-ch QuadSPI
512 KB OCRAM
Figure 1. i.MX 8M Nano system block diagram
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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5
i.MX 8M Nano introduction
NOTE
Some modules shown in this block diagram are not offered on all
derivatives. See Table 2 for exceptions.
Table 2. Modules supported
Key Modules
6CVT
5CVT
4CVT
3CVT
2CVT
1CVT
5CVP
3CVP
1CVP
Cortex® A53
4x
4x
2x
2x
1x
1x
4x
2x
1x
Cortex® M7
1x
1x
1x
1x
1x
1x
1x
1x
1x
GPU
1x
N/A
1x
N/A
1x
N/A
N/A
N/A
N/A
MIPI DSI
1x
1x
1x
1x
1x
1x
N/A
N/A
N/A
1.2
Ordering information
Table 3 shows examples of orderable sample part numbers covered by this data sheet. This table does not
include all possible orderable part numbers. If your desired part number is not listed in the table, or you
have questions about available parts, contact your NXP representative.
Table 3. Orderable part numbers
Cortex-A53
CPU speed
grade
Qualification
tier
Temperature
Tj (C)
4x A53, M7, GPU,
MIPI DSI
1.4 GHz
Industrial
-40 to 105
14 x 14 mm,
0.5 mm pitch
i.MX 8M Nano
QuadLite
4x A53, M7, No
GPU, MIPI DSI
1.4 GHz
Industrial
-40 to 105
14 x 14 mm,
0.5 mm pitch
MIMX8MN4CVTIZAA
i.MX 8M Nano
Dual
2x A53, M7, GPU,
MIPI DSI
1.4 GHz
Industrial
-40 to 105
14 x 14 mm,
0.5 mm pitch
MIMX8MN3CVTIZAA
i.MX 8M Nano
DualLite
2x A53, M7, No
GPU, MIPI DSI
1.4 GHz
Industrial
-40 to 105
14 x 14 mm,
0.5 mm pitch
MIMX8MN2CVTIZAA
i.MX 8M Nano
Solo
1x A53, M7, GPU,
MIPI DSI
1.4 GHz
Industrial
-40 to 105
14 x 14 mm,
0.5 mm pitch
MIMX8MN1CVTIZAA
i.MX 8M Nano
SoloLite
1x A53, M7, No
GPU, MIPI DSI
1.4 GHz
Industrial
-40 to 105
14 x 14 mm,
0.5 mm pitch
MIMX8MN5CVPIZAA
i.MX 8M Nano
UltraLite Quad
4x A53, M7, No
GPU, No MIPI DSI
1.4 GHz
Industrial
-40 to 105
11 x 11 mm,
0.5 mm pitch
MIMX8MN3CVPIZAA
i.MX 8M Nano
UltraLite Dual
2x A53, M7, No
GPU, No MIPI DSI
1.4 GHz
Industrial
-40 to 105
11 x 11 mm,
0.5 mm pitch
MIMX8MN1CVPIZAA
i.MX 8M Nano
UltraLite Solo
1x A53, M7, No
GPU, No MIPI DSI
1.4 GHz
Industrial
-40 to 105
11 x 11 mm,
0.5 mm pitch
Part number
Sub-Family
Options
MIMX8MN6CVTIZAA
i.MX 8M Nano
Quad
MIMX8MN5CVTIZAA
Package
Figure 2 describes the part number nomenclature so that the users can identify the characteristics of the
specific part number.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
6
NXP Semiconductors
i.MX 8M Nano introduction
Contact an NXP representative for additional details.
MIMX8MN@+##$$%A
Silicon revision
Fusing options
Core frequency – Arm A53
Package type – all ROHS
Data Sheet Temperature
Part differentiator
Qualification level
Qualification level
Samples
P
Mass Production
M
Part number series
Description
IMX8MN
i.MX 8M Nano
Part number series
Part differentiator
@
i.MX 8M Nano Quad
GPU, 4x A53
6
i.MX 8M Nano QuadLite
*i.MX 8M Nano UltraLite Quad
No GPU, 4x A53
5
i.MX 8M Nano Dual
GPU, 2x A53
4
i.MX 8M Nano DualLite
*i.MX 8M Nano UltraLite Dual
No GPU, 2x A53
3
i.MX 8M Nano Solo
GPU, 1x A53
2
i.MX 8M Nano SoloLite
*i.MX 8M Nano UltraLite Solo
No GPU, 1x A53
1
+
A53 core frequency
$$
+95oC
D
1.5 GHz
JZ
Industrial: -40 to 105oC
C
1.4 GHz
IZ
Temperature Tj
Consumer: 0 to
Package Type
ROH
S
Fusing
%
FCBGA486
14 x14mm, 0.5mm pitch
VT
Default
A
FCBGA306
11x11mm, 0.5mm pitch
VP
Immersiv3D w/ Dolby Atmos
C
Immersiv3D w/ Dolby Atmos & DTS
D
Silicon Rev
A
Rev A0
A
*i.MX 8M Nano UltraLite Quad/Dual/Solo (11x11 package) has no MIPI DSI
Figure 2. Part number nomenclature—i.MX 8M Nano family of processors
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
7
Modules list
2
Modules list
The i.MX 8M Nano family of processors contains a variety of digital and analog modules. Table 4
describes these modules in alphabetical order.
Table 4. i.MX 8M Nano modules list
Block mnemonic
Block name
APBH-DMA
NAND Flash and BCH ECC
DMA Controller
Arm
Arm Platform
The Arm Core Platform includes a quad Cortex-A53 core and a
Cortex-M7 core. The Cortex-A53 core includes associated
sub-blocks, such as the Level 2 Cache Controller, Snoop Control
Unit (SCU), General Interrupt Controller (GIC), private timers,
watchdog, and CoreSight debug modules. The Cortex-M7 core is
used as a customer microcontroller.
BCH
Binary-BCH ECC Processor
The BCH module provides up to 62-bit ECC encryption/decryption
for NAND Flash controller (GPMI)
CAAM
Cryptographic accelerator and
assurance module
CAAM is a cryptographic accelerator and assurance module. CAAM
implements several encryption and hashing functions, a run-time
integrity checker, entropy source generator, and a Pseudo Random
Number Generator (PRNG). The PRNG is certifiable by the
Cryptographic Algorithm Validation Program (CAVP) of the National
Institute of Standards and Technology (NIST).
CAAM also implements a Secure Memory mechanism. In i.MX 8M
Nano processors, the secure memory provided is 32 KB.
CCM
GPC
SRC
Brief description
DMA controller used for GPMI2 operation.
Clock Control Module, General These modules are responsible for clock and reset distribution in the
Power Controller, System Reset system, and also for the system power management.
Controller
CSU
Central Security Unit
The Central Security Unit (CSU) is responsible for setting
comprehensive security policy within the i.MX 8M Nano platform.
CTI-0
CTI-1
CTI-2
CTI-3
CTI-4
Cross Trigger Interface
Cross Trigger Interface (CTI) allows cross-triggering based on inputs
from masters attached to CTIs. The CTI module is internal to the
Cortex-A53 core platform.
DAP
Debug Access Port
The DAP provides real-time access for the debugger without halting
the core to access:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains.
DDRC
Double Data Rate Controller
The DDR Controller has the following features:
• Supports 16-bit LPDDR4-3200, DDR4-2400, and DDR3L-1600
• Supports up to 8 Gbyte DDR memory space
eCSPI1
eCSPI2
eCSPI3
Configurable SPI
Full-duplex enhanced Synchronous Serial Interface, with data rate
up to 52 Mbit/s. Configurable to support Master/Slave modes, four
chip selects to support multiple peripherals.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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Modules list
Table 4. i.MX 8M Nano modules list (continued)
Block mnemonic
Block name
Brief description
ENET1
Ethernet Controller
The Ethernet Media Access Controller (MAC) is designed to support
10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to
complete the interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the ENET chapter
of the i.MX 8M Nano Applications Processor Reference Manual
(IMX8MNRM) for details.
FlexSPI
FlexSPI
The FlexSPI module acts as an interface to external serial flash
devices. This module contains the following features:
• Flexible sequence engine to support various flash vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash devices
• Multi master access with priority and flexible and configurable
buffer for each master
GIC
Generic Interrupt Controller
The GIC handles all interrupts from the various subsystems and is
ready for virtualization.
GPC
General Power Control Module The GPC independently control reset and gated clock to each
switched power domain when powering on/off the domain.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O Modules
Used for general purpose input/output to external ICs. Each GPIO
module supports up to 32 bits of I/O.
GPMI
General Purpose Memory
Interface
The GPMI module supports up to 8x NAND devices and 62-bit ECC
encryption/decryption for NAND Flash Controller (GPMI2). GPMI
supports separate DMA channels for each NAND device.
GPT1
GPT2
GPT3
GPT4
GPT5
GPT6
General Purpose Timer
Each GPT is a 32-bit “free-running” or “set-and-forget” mode timer
with programmable prescaler and compare and capture register. A
timer counter value can be captured using an external event and can
be configured to trigger a capture event on either the leading or
trailing edges of an input pulse. When the timer is configured to
operate in “set-and-forget” mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on
an external clock or on an internal clock.
GPU3D
Graphics Processing Unit-3D
I2C1
I2C2
I2C3
I2C4
I2C Interface
The GPU3D provides hardware acceleration for 3D graphics
algorithms with sufficient processor power to run desktop quality
interactive graphics applications on displays.
I2C provides serial interface for external devices. Data rates of up to
320 kbps are supported.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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9
Modules list
Table 4. i.MX 8M Nano modules list (continued)
Block mnemonic
Block name
Brief description
IOMUXC
IOMUX Control
This module enables flexible I/O multiplexing. Each IO pad has a
default as well as several alternate functions. The alternate functions
are software configurable.
LCDIF
LCD interface
The LCDIF is a general purpose display controller used to drive a
wide range of display devices varying in size and capability, the key
feature of the display controller includes:
• Support 8-bit/16-bit/24-bit/32-bit pixel depth
• Support DOTCLK mode for MIPI-DPI interface
• Support resolution up to 1920 x1200p60
MIPI CSI (four-lane)
MIPI Camera Serial Interface
This module provides one four-lane MIPI camera serial interfaces,
which operates up to a maximum bit rate of 1.5 Gbps.
MIPI DSI (four-lane)
MIPI Display Serial Interface
This module provides a four-lane MIPI display serial interface
operating up to a maximum bit rate of 1.5 Gbps.
OCOTP_CTRL
OTP Controller
The On-Chip OTP controller (OCOTP_CTRL) provides an interface
for reading, programming, and/or overriding identification and control
information stored in on-chip fuse elements. The module supports
electrically programmable poly fuses (eFUSEs). The OCOTP_CTRL
also provides a set of volatile software-accessible signals that can be
used for software control of hardware elements, not requiring non
volatility. The OCOTP_CTRL provides the primary user-visible
mechanism for interfacing with on-chip fuse elements. Among the
uses for the fuses are unique chip identifiers, mask revision
numbers, cryptographic keys, JTAG secure mode, boot
characteristics, and various control signals requiring permanent non
volatility.
OCRAM
On-Chip Memory controller
The On-Chip Memory controller (OCRAM) module is designed as an
interface between the system’s AXI bus and the internal (on-chip)
SRAM memory module.
In i.MX 8M Nano processors, the OCRAM is used for controlling the
512 KB multimedia RAM through a 64-bit AXI bus.
PDM
Pulse Density Modulation
PWM1
PWM2
PWM3
PWM4
Pulse Width Modulation
The pulse-width modulator (PWM) has a 16-bit counter and is
optimized to generate sound from stored sample audio images. It
can also generate tones. It uses 16-bit resolution and a 4x16 data
FIFO to generate sound.
SAI2
SAI3
SAI5
SAI6
SAI7
Synchronous Audio Interface
The SAI module provides a synchronous audio interface (SAI) that
supports full duplex serial interfaces with frame synchronization,
such as I2S, AC97, TDM, and codec/DSP interfaces.
The PDM supports up to 8-channels (4 lanes).
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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Modules list
Table 4. i.MX 8M Nano modules list (continued)
Block mnemonic
Block name
Brief description
SDMA
Smart Direct Memory Access
The SDMA is a multichannel flexible DMA engine. It helps in
maximizing system performance by offloading the various cores in
dynamic data routing. It has the following features:
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi channel DMA supporting up to 32 time-division multiplexed
DMA channels
• 48 events with total flexibility to trigger any combination of
channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between Arm and SDMA
• Very fast Context-Switching with 2-level priority based preemptive
multi tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment,
decrement, and no address changes on source and destination
address)
• DMA ports can handle unidirectional and bidirectional flows (Copy
mode)
• Up to 8-word buffer for configurable burst transfers for EMIv2.5
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SJC
Secure JTAG Controller
The SJC provides JTAG interface (designed to be compatible with
JTAG TAP standards) to internal logic. The i.MX 8M Nano family of
processors uses JTAG port for system debugging.
The JTAG port must be accessible during platform initial laboratory
bring-up, for troubleshooting, as well as for software debugging by
authorized entities. The i.MX 8M Nano SJC incorporates three
security modes for protecting against unauthorized accesses.
Modes are selected through eFUSE configuration.
SNVS
Secure Non-Volatile Storage
Secure Non-Volatile Storage, including Secure Real Time Clock,
Security State Machine, Master Key Control, and Violation/Tamper
Detection and reporting.
SPDIF1
Sony Philips Digital
Interconnect Format
A standard audio file transfer format, developed jointly by the Sony
and Phillips corporations. It supports Transmitter and Receiver
functionality.
TEMPSENSOR
Temperature Sensor
Temperature sensor
TZASC
Trust-Zone Address Space
Controller
The TZASC (TZC-380 by Arm) provides security address region
control functions required for intended application. It is used on the
path to the DRAM controller.
UART1
UART2
UART3
UART4
UART Interface
Each of the UARTv2 modules supports the following serial data
transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even,
odd, or none)
• Programmable baud rates up to 4 Mbps. This is a higher max
baud rate relative to the 1.875 MHz, which is stated by the
TIA/EIA-232-F standard.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting
auto-baud
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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11
Modules list
Table 4. i.MX 8M Nano modules list (continued)
Block mnemonic
Block name
Brief description
uSDHC1
uSDHC2
uSDHC3
SD/MMC and SDXC
Enhanced Multi-Media Card /
Secure Digital Host Controller
i.MX 8M Nano SoC characteristics:
All the MMC/SD/SDIO controller IPs are based on the uSDHC IP.
They are designed to support:
• SD/SDIO standard, up to version 3.0.
• MMC standard, up to version 5.1.
• 1.8 V and 3.3 V operation, but do not support 1.2 V operation.
• 1-bit/4-bit SD and SDIO modes, 1-bit/4-bit/8-bit MMC mode.
One uSDHC controller (SD1) can support up to an 8-bit interface, the
other controller (SD2) can only support up to a 4-bit interface.
USB 2.0
1x USB 2.0 controller and PHY One USB controller and PHY that support USB 2.0.
WDOG1
WDOG2
WDOG3
2.1
Watchdog
The watchdog (WDOG) timer supports two comparison points
during each counting period. Each of the comparison points is
configurable to evoke an interrupt to the Arm core, and a second
point evokes an external event on the WDOG line.
Recommended connections for unused input/output
If a function of the i.MX 8M Nano is not in use, the I/Os and power rails of that function can be terminated
to reduce overall board power.
Table 5 shows the recommended connections for 14 x 14 mm package unused power supply rails.
Table 5. Recommended connections for 14 x 14 mm package unused power supply rails
Function
Ball Name
Recommendations
if Unused
MIP-CSI and
MIPI-DSI
VDD_MIPI_0P8, VDD_MIPI_1P2, VDD_MIPI_1P8
Leave unconnected
USB1
VDD_USB_0P8, VDD_USB_1P8, VDD_USB_3P3
Leave unconnected
GPU
VDD_GPU
Leave unconnected
NVCC_CLK, NVCC_ECSPI, NVDD_ENET, NVCC_GPIO1, NVCC_I2C,
NVCC_JTAG, NVCC_NAND, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, NVCC_SD1,
NVCC_SD2, NVCC_UART, NVCC_SNVS_1P8, PVCC0_1P8, PVCC1_1P8,
PVCC2_1P8
All digital I/O
supplies listed in this
table must be
powered under
normal conditions
whether the
associated I/O pins
are in use or not, and
associated I/O pins
need to enable pull
in pad control
register to limit any
floating gate current.
Digital I/O
supplies
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
12
NXP Semiconductors
Modules list
Table 6 shows the recommended connections for 11 x 11 mm package unused power supply rails.
Table 6. Recommended connections for 11 x 11 mm package unused power supply rails
Function
MIP-CSI
USB1
Digital I/O
supplies
Ball Name
Recommendations
if Unused
VDD_MIPI_1P2
Leave unconnected
VDD_USB_0P8, VDD_USB_1P8, VDD_USB_3P3
Leave unconnected
NVCC_ENET_GPIO_SAI2, NVCC_CLK_JTAG_PVCC_1P8, NVCC_I2C_UART,
NVCC_SAI3_SAI5, NVCC_SD1_NAND, NVCC_ECSPI, NVCC_SD2,
NVCC_SNVS_1P8
All digital I/O
supplies listed in this
table must be
powered under
normal conditions
whether the
associated I/O pins
are in use or not, and
associated I/O pins
need to enable pull
in pad control
register to limit any
floating gate current.
Table 8 shows recommended connections for 14 x 14 mm package unused signal contacts/interfaces.
Table 7. Recommended connections for 14 x 14 mm package unused signal contacts/interfaces
Function
Ball Name
Recommendations
if Unused
MIPI-CSI
MIPI_CSI_CLK_P, MIPI_CSI_CLK_N, MIPI_CSI_Dx_P, MIPI_CSI_Dx_N
Tie all signals to
ground
MIPI-DSI
MIPI_VREG_CAP, MIPI_DSI_CLK_P, MIPI_DSI_CLK_N, MIPI_DSI_Dx_P,
MIPI_DSI_Dx_N
Leave unconnected
USB1_VBUS, USB1_DN, USB1_DP, USB1_ID, USB1_TXRTUNE
Leave unconnected
USB1
Table 8 shows recommended connections for 11 x 11 mm package unused signal contacts/interfaces.
Table 8. Recommended connections for 11 x 11 mm package unused signal contacts/interfaces
Function
USB1
MIPI-CSI
Ball Name
Recommendations
if Unused
USB1_VBUS, USB1_DN, USB1_DP, USB1_ID, USB1_TXRTUNE
Leave unconnected
MIPI_CSI_CLK_P, MIPI_CSI_CLK_N, MIPI_CSI_Dx_P, MIPI_CSI_Dx_N
Tie all signals to
ground
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
13
Electrical characteristics
3
Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX 8M Nano family
of processors.
3.1
Chip-level conditions
This section provides the device-level electrical characteristics for the IC. See Table 9 for a quick reference
to the individual tables and sections.
Table 9. i.MX 8M Nano chip-level conditions
For these characteristics, …
Topic appears …
Absolute maximum ratings
on page 14
Thermal resistance
on page 17
Operating ranges
on page 18
External clock sources
on page 21
Estimated power supply maximum currents
on page 22
Power modes
on page 23
Power supplies requirements and restrictions
on page 27
3.1.1
Absolute maximum ratings
CAUTION
Stresses beyond those listed under Table 10 may affect reliability or cause
permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those
indicated in the operating ranges or parameters tables is not implied.
Table 10. Absolute maximum ratings for 14 x 14 mm package
Parameter description
Symbol
Min
Max
Unit
Notes
Core supply voltages
VDD_ARM
VDD_SOC
-0.3
1.15
V
—
Power supply for GPU
VDD_GPU
-0.3
1.15
V
—
VDD_DRAM
-0.3
1.15
V
—
NVCC_DRAM
-0.3
1.575
V
—
VDD_DRAM_PLL_0P8
-0.3
1.15
V
—
VDD_DRAM_PLL_1P8
-0.3
2.15
V
—
NVCC_SNVS_1P8
-0.3
2.15
V
—
VDD_SNVS_0V8
-0.3
0.95
V
—
DDR PHY supply voltage
DDR I/O supply voltage
DRAM PLL supply voltage
SNVS IO supply voltage
VDD_SNVS supply voltage
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
14
NXP Semiconductors
Electrical characteristics
Table 10. Absolute maximum ratings for 14 x 14 mm package (continued)
Parameter description
Symbol
Min
Max
Unit
Notes
NVCC_JTAG,
NVCC_GPIO1,
NVCC_ENET,
NVCC_SD1,
NVCC_SD2,
NVCC_NAND,
NVCC_SAI2,
NVCC_SAI3,
NVCC_SAI5,
NVCC_ECSPI,
NVCC_I2C,
NVCC_UART,
NVCC_CLK
-0.3
3.8
V
—
PVCC0_1P8,
PVCC1_1P8,
PVCC2_1P8
-0.3
2.15
V
—
Isolated core supply voltage
VDD_ANA_0P8
-0.3
1.15
V
—
Analog core supply voltage
VDD_ANA0_1P8
-0.3
2.15
V
—
VDD_ANA1_1P8
-0.3
2.15
V
—
VDD_ARM_PLL_0P8
-0.3
1.15
V
—
VDD_ARM_PLL_1P8
-0.3
2.15
V
—
VDD_MIPI_0P8
-0.3
1.15
V
—
VDD_MIPI_1P2
-0.3
1.45
V
—
VDD_MIPI_1P8
-0.3
2.15
V
—
VDD_USB_0P8
-0.3
1.15
V
—
VDD_USB_1P8
-0.3
2.15
V
—
VDD_USB_3P3
-0.3
3.95
V
—
USB1_VBUS
-0.3
3.95
V
—
VDD_24M_XTAL_1P8
-0.3
2.15
V
—
150
oC
—
GPIO supply voltage
GPIO pre-driver supply voltage
Arm PLL supply voltage
MIPI PHY supply voltage
USB PHY supply voltage
USB_VBUS input detected
XTAL supply voltage
Storage temperature range
TSTORAGE
-40
Table 11. Absolute maximum ratings for 11 x 11 mm package
Parameter description
Core and DDR PHY supply
voltage
DDR I/O supply voltage
DRAM PLL supply voltage
SNVS IO supply voltage
Symbol
Min
Max
Unit
Notes
VDD_SOC
-0.3
1.15
V
—
NVCC_DRAM
-0.3
1.575
V
—
VDD_DRAM_PLL_1P8
-0.3
2.15
V
—
NVCC_SNVS_1P8
-0.3
2.15
V
—
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
15
Electrical characteristics
Table 11. Absolute maximum ratings for 11 x 11 mm package (continued)
Parameter description
Symbol
Min
Max
Unit
Notes
VDD_SNVS_0V8
-0.3
0.95
V
—
GPIO supply voltage
NVCC_ENET_GPIO_S
AI2,
NVCC_I2C_UART,
NVCC_SAI3_SAI5,
NVCC_SD1_NAND,
NVCC_ECSPI,
NVCC_SD2
-0.3
3.8
V
—
GPIO supply voltage
NVCC_CLK_JTAG_PV
CC_1P8
-0.3
2.15
V
—
XTAL, Analog core, MIPI PHY
and USB PHY 1.8 V supply
voltage
VDD_ANA1_XTAL_MIP
I_USB_1P8
-0.3
2.15
V
—
Analog core and ARM PLL 1.8 V
supply voltage
VDD_ANA0_ARM_PLL
_1P8
-0.3
2.15
V
—
MIPI PHY 1.2 V supply voltage
VDD_MIPI_1P2
-0.3
1.45
V
—
USB PHY 3.3 V supply voltage
VDD_USB_3P3
-0.3
3.95
V
—
USB1_VBUS
-0.3
3.95
V
—
VDD_24M_XTAL_1P8
-0.3
2.15
V
—
TSTORAGE
-40
150
oC
—
VDD_SNVS supply voltage
USB_VBUS input detected
XTAL supply voltage
Storage temperature range
Table 12. Electrostatic discharge and latch up ratings
Parameter description
Rating
Reference
Comment
Electrostatic Discharge
(ESD)
Human Body Model (HBM)
±1000 V
JS-001-2017
—
Charged Device Model (CDM)
±250 V
JS-002-2018
—
Latch UP (LU)
Immunity level:
• Class I@ 25 oC ambient
temperature
• Class II @ 105 oC ambient
temperature
A
A
JESD78E
Mandatory requirement:
JTAG_TMS pin must be
connected with a 50 ohm
series resistor near the
component.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
16
NXP Semiconductors
Electrical characteristics
3.1.2
3.1.2.1
Thermal resistance
14 x 14 mm FCBGA package thermal resistance
Table 13 displays the 14 x 14 mm FCBGA package thermal resistance data.
Table 13. 14 x 14 mm package thermal resistance data
Rating
Test conditions
Symbol
Value
Unit
Notes
Junction to Ambient
Natural Convection
Single layer board (1s)
Four layer board (2s2p)
RJA
30
o
C/W
1, 2
Junction to Ambient
Natural Convection
Four layer board (2s2p)
Four layer board (2s2p)
RJA
22.9
o
C/W
1, 2, 3
Junction to Ambient (@200 ft/min)
Single layer board (1s)
RJMA
24
o
C/W
1, 3
Junction to Ambient (@200 ft/min)
Four layer board (2s2p)
RJMA
18.5
oC/W
1, 3
Junction to Board
—
RJB
7.8
oC/W
4
Junction to Case
—
RJC
4
oC/W
5
Junction to Package Top
Natural Convection
JT
0.2
oC/W
6
1
2
3
4
5
6
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Per SEMI G38-87 and JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and printed circuit board per JEDEC JESD51-8. Board temperature is measured on the
top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
3.1.2.2
11 x 11 mm FCBGA package thermal resistance
Table 13 displays the 11 x 11 mm FCBGA package thermal resistance data.
Table 14. 11 x 11 mm thermal resistance data1
Rating
Board type2
Value
Symbol
Unit
Coreless
Junction to Ambient Thermal Resistance3
JESD51-9, 2s2p
RJA
27.7
oC/W
Junction-to-Top of Package Thermal
Characterization Parameter3
JESD51-9, 2s2p
JT
5.2
oC/W
Junction to Case Resistance4
JESD51-9, 1s
RJC
11
oC/W
1
Non-uniform power is applied on the die.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
17
Electrical characteristics
2
Thermal test board meets JEDEC specification for this package (JESD51-9). Test board has 40 vias under die shadow
mapped according to BGA layout under die. Each via is 0.2 mm in diameter and connects top layer with the first buried plane
layer.
3
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
4
Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the surface
temperature at the package top side.
3.1.3
Operating ranges
Table 15 provides the operating ranges of the i.MX 8M Nano applications processor. For details on the
chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 8M Nano
Applications Processor Reference Manual (IMX8MNRM).
Table 15. Operating ranges for 14 x 14 mm package
Symbol
Min
Typ
Max1
Unit
VDD_ARM
0.805
0.850
0.950
V
Power supply for Cortex® A53, 1.2 GHz
0.900
0.950
1.000
V
Power supply for Cortex® A53, 1.4 GHz2
0.805
0.850
0.900
V
Power supply for SoC logic4, Cortex® M7
600 MHz
0.900
0.950
1.000
V
Power supply for SoC logic, overdrive
mode, Cortex® M7 750 MHz
0.805
0.850
0.900
V
Power supply for 3D GPU, nominal mode,
400 MHz
0.900
0.950
1.000
V
Power supply for 3D GPU, overdrive
mode, 600 MHz
0.805
0.850
0.900
V
Power supply for DDRC, 0.85 V supports
up to 1.2 GHz (DDR clock)
0.900
0.950
1.000
V
Power supply for DDRC, 0.95 V supports
up to 1.6 GHz (DDR clock)
VDD_SNVS_0P8
0.760
0.800
0.900
V
Power supply for SNVS core logic
NVCC_SNVS_1P8
1.620
1.800
1.980
V
Power supply for GPIO pre-driver in SNVS
bank
NVCC_JTAG,
NVCC_GPIO1,
NVCC_ENET,
NVCC_SD1, NVCC_SD2,
NVCC_NAND,
NVCC_SAI2, NVCC_SAI3,
NVCC_SAI5,
NVCC_ECSPI,
NVCC_I2C, NVCC_UART,
NVCC_CLK
1.650
1.800
1.950
V
Power supply for GPIO when it is in 1.8 V
mode
3.000
3.300
3.600
V
Power supply for GPIO when it is in 3.3 V
mode
NVCC_ENET
2.250
2.500
2.750
V
Power supply for GPIO when it is in 2.5 V
mode
VDD_SOC3
VDD_GPU3
VDD_DRAM3
Comment
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
18
NXP Semiconductors
Electrical characteristics
Table 15. Operating ranges for 14 x 14 mm package (continued)
Symbol
Min
Typ
Max1
Unit
PVCC0_1P8,
PVCC1_1P8,
PVCC2_1P8
1.650
1.800
1.950
V
Power supply for GPIO pre-driver
VSS
—
—
—
V
Ground for all core logic and I/O
NVCC_DRAM
1.283
1.35
1.425
V
DDR3L
1.14
1.2
1.26
V
DDR4
1.06
1.1
1.14
V
LPDDR4
0.51 x
NVCC_DRAM
V
Internal output, no connection is needed.
DRAM_VREF
VDD_DRAM_PLL_0P8
0.49 x
0.5 x
NVCC_DRAM NVCC_DRAM
Comment
0.805
0.850
0.900
V
Power supply for DRAM PLL, nominal
mode
0.900
0.950
1.000
V
Power supply for DRAM PLL, overdrive
mode
VDD_ANA0_1P8
VDD_ANA1_1P8
1.71
1.8
1.89
V
Analog 1.8 V core power
VDD_ANA_0P8
0.805
0.850
0.900
V
Supplies for Analog PLL, nominal mode
0.900
0.950
1.000
V
Supplies for Analog PLL, overdrive mode
0.805
0.850
0.900
V
Power supply for Arm PLL, nominal mode
0.900
0.950
1.000
V
Power supply for Arm PLL, overdrive
mode
VDD_ARM_PLL_1P8
1.71
1.8
1.89
V
Arm PLL 1.8 V power
VDD_24M_XTAL_1P8
1.71
1.8
1.89
V
XTAL 1.8 V power
VDD_DRAM_PLL_1P8
1.71
1.8
1.89
V
Analog 1.8 V core power
VDD_MIPI_0P8
0.805
0.850
0.900
V
Digital supply for MIPI PHY, nominal mode
0.900
0.950
1.000
V
Digital supply for MIPI PHY, overdrive
mode
VDD_MIPI_1P2
1.14
1.2
1.26
V
1.2 V power for analog
VDD_MIPI_1P8
1.71
1.8
1.89
V
1.8 V power for PLL and analog
VDD_USB_0P8
0.805
0.850
0.900
V
Digital power supply from PHY’s I/O
power pads, nominal mode
0.900
0.950
1.000
V
Digital power supply from PHY’s I/O
power pads, overdrive mode
VDD_USB_1P8
1.71
1.80
1.89
V
1.8 V analog power supply
VDD_USB_3P3
3.069
3.30
3.6
V
3.3 V analog power supply
VDD_ARM_PLL_0P8
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
19
Electrical characteristics
Table 15. Operating ranges for 14 x 14 mm package (continued)
1
2
3
4
5
Symbol
Min
Typ
Max1
Unit
USB1_VBUS
1.34
—
3.60
V
USB_VBUS input detect signal
Temperature Sensor
Accuracy5
—
±3
±5
°C
Sensing temperature range 10°C to
105°C
T
J
-40
—
+105
o
See Table 3 for complete list of junction
temperature capabilities.
C
Comment
Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the
supply tolerance) is recommended. This results in an optimized power/speed ratio.
For VDD_ARM at 1.0V typical, Power-on Hours will decreased if junction temperature is increased. Please refer to i.MX 8M
Nano Product Lifetime Usage (AN12983) for details.
VDD_DRAM, VDD_SOC, and VDD_GPU are required to be tied together and keep same or ground.
Booting VDD_SOC at 0.800 V ±5% is acceptable (Vmin = 0.760 V). Software is expected to program the VDD_SOC voltage
to the typical value in this table prior to first DRAM memory access.
“EN” of TMU Enable Register (TMU_TER) is required to be always enabled for the part to operate correctly.
Table 16. Operating ranges for 11 x11 mm package
Symbol
Min
Typ
Max1
Unit
Comment
VDD_SOC
0.805
0.850
0.900
V
Power supply for SoC logic2, Cortex® M7
600 MHz; Cortex® A53, 1.2 GHz,
nominal mode, 1.2 GHz DDR clock
0.900
0.950
1.000
V
Power supply for SoC logic2, Cortex® M7
750 MHz; Cortex® A53, 1.4 GHz,
overdrive mode, 1.6 GHz DDR clock
VDD_SNVS_0P8
0.760
0.800
0.900
V
Power supply for SNVS core logic
NVCC_SNVS_1P8
1.620
1.800
1.980
V
Power supply for GPIO pre-driver in
SNVS bank
NVCC_I2C_UART,
NVCC_SAI3_SAI5,
NVCC_SD1_NAND,
NVCC_ECSPI,
NVCC_SD2,
NVCC_ENET_GPIO_SAI2
1.650
1.800
1.950
V
Power supply for GPIO when it is in 1.8 V
mode
3.000
3.300
3.600
V
Power supply for GPIO when it is in 3.3 V
mode
NVCC_CLK_JTAG_PVCC_
1P8
1.650
1.800
1.950
V
Power supply for GPIO and GPIO
pre-driver in 1.8 V mode
VSS
—
—
—
V
Ground for all core logic and I/O
NVCC_DRAM
1.283
1.35
1.425
V
DDR3L
1.14
1.2
1.26
V
DDR4
1.06
1.1
1.14
V
LPDDR4
V
Internal output, no connection is needed.
DRAM_VREF
0.49 x
0.5 x
0.51 x
NVCC_DRAM NVCC_DRAM NVCC_DRAM
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
20
NXP Semiconductors
Electrical characteristics
Table 16. Operating ranges for 11 x11 mm package (continued)
Symbol
Min
Typ
Max1
Unit
Comment
VDD_ANA1_XTAL_MIPI_U
SB_1P8,
VDD_ANA0_ARM_PLL_1P
8
1.71
1.8
1.89
V
1.8 V power for Analog core, XTAL, MIPI
PLL and analog, USB analog and ARM
PLL
VDD_DRAM_PLL_1P8
1.71
1.8
1.89
V
Analog 1.8 V core power
VDD_MIPI_1P2
1.14
1.2
1.26
V
1.2 V power for analog
VDD_USB_3P3
3.069
3.30
3.6
V
3.3 V analog power supply
USB1_VBUS
1.34
—
3.60
V
USB_VBUS input detect signal
Temperature Sensor
Accuracy2
—
±3
±5
°C
Sensing temperature range 10°C to
105°C
T
J
-40
—
+105
oC
See Table 3 for complete list of junction
temperature capabilities.
1
Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the
supply tolerance) is recommended. This results in an optimized power/speed ratio.
2 “EN” of TMU Enable Register (TMU_TER) is required to be always enabled for the part to operate correctly.
3.1.4
External clock sources
Each i.MX 8M Nano processor has two external input system clocks: a low frequency (RTC_XTALI) and
a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watch-dog counters. The clock input can only
be connected to an external oscillator. RTC_XTALO should be directly connected to VDD_SNVS_0P8.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either an external oscillator or a crystal using
internal oscillator amplifier.
Table 17 shows the interface frequency requirements.
Table 17. External input clock frequency
Parameter Description
RTC_XTALI Oscillator1
1,3
XTALI Oscillator
Symbol
Min
Typ
Max
Unit
fckil
—
32.7682
—
kHz
fxtal
24
MHz
1
The required frequency stability of this clock source is application dependent.
Recommended nominal frequency 32.768 kHz.
3 External oscillator or a fundamental frequency crystal appropriately coupled to the internal oscillator amplifier.
2
The typical values shown in Table 17 are required for use with NXP software to ensure precise time
keeping and USB operation. For RTC_XTALI operation, an external oscillator is necessary. RTC_XTALO
should be directly connected to VDD_SNVS_0P8 when using an external 32.768 kHz oscillator.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
21
Electrical characteristics
NOTE
There is no internal RC oscillator.
Table 18 shows the external input clock for OSC32K.
Table 18. External input clock for OSC32K
Symbol
Min
Typ
Max
Unit
Frequency
f
—
32.768
—
kHz
RTC_XTALI
VIH
0.7 x NVCC_SNVS_1P8
—
NVCC_SNVS_1P8
V
VIL
0
—
0.3 x NVCC_SNVS_1P8
V
3.1.5
Estimated power supply maximum currents
Power consumption is highly dependent on the application. Estimating the maximum supply currents
required for power supply design is difficult because the use cases that requires maximum supply current
is not a realistic use cases.
The table below represents the estimated maximum current on the power supply rails and should be used
as a guideline for power supply selection. The data below is based on a combination of design simulation
and characterization data based on typical datasheet voltages. Actual power consumption for typical use
cases are lower than values presented on the table below.
Table 19. Estimated power supply maximum currents for 14 x 14 mm package
Power rail
Max current
Unit
VDD_ARM
2200
mA
VDD_SOC
1000
mA
VDD_GPU
800
mA
VDD_DRAM
800
mA
VDD_ANA_0P8
50
mA
VDD_ANA0_1P8
VDD_ANA1_1P8
250
mA
3
mA
NVCC_SNVS_1P8
NVCC_
NVCC_DRAM
DRAM_VFEF
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 x F)—Data change rate. Up to 0.5 of the clock
rate (F).
In this equation, Imax is in Amps, C in Farads, V in
Volts, and F in Hertz.
10
mA
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
22
NXP Semiconductors
Electrical characteristics
Table 20. Estimated power supply maximum currents for 11 x 11 mm package
Power rail
Max current
Unit
3000
mA
3
mA
VDD_ANA1_XTAL_MIPI_USB_1P8,
VDD_ANA0_ARM_PLL_1P8,
VDD_DRAM_PLL_1P8
250
mA
VDD_MIPI_1P2
100
mA
VDD_SOC
NVCC_SNVS_1P8
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 x F)—Data change rate. Up to 0.5 of the clock
rate (F).
In this equation, Imax is in Amps, C in Farads, V in
Volts, and F in Hertz.
NVCC_
NVCC_DRAM
DRAM_VFEF
3.1.6
10
mA
Power modes
The i.MX 8M Nano supports the following power modes:
• RUN Mode: All external power rails are on, CPU is active and running; other internal modules can
be on/off based on application.
• IDLE Mode: When there is no thread running and all high-speed devices are not active, the CPU
can automatically enter this mode. The CPU can be in the power-gated state but with L2 data
retained, DRAM and the bus clock are reduced. Most of the internal logic is clock gated but still
remains powered. The M7 core can remain running. Compared with RUN mode, all the external
power rails from the PMIC remain the same, and most of the modules still remain in their state.
• SUSPEND Mode: The most efficient power saving mode where all the clocks are off and all the
unnecessary power supplies are off.
• SNVS Mode: This mode is also called RTC mode. Only the power for the SNVS domain remains
on to keep RTC and SNVS logic alive.
• OFF Mode: All power rails are off.
Table 21. Chip power in different LP mode for 14 x 14 mm package
Mode
SNVS
Typ.1
Supply
VDD_SNVS_0P8
0.10
NVCC_SNVS_1P8
1.20
2
Total
Unit
mW
1.30
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
23
Electrical characteristics
Table 21. Chip power in different LP mode for 14 x 14 mm package (continued)
Mode
SUSPEND
Low-V SUSPEND3
Typ.1
Supply
NVCC
0.80
NVCC_DRAM
2.40
NVCC_ENET
0.10
NVCC_SNVS_1P8
0.20
PVCC
0.60
VDD_DRAM
9.40
VDD_MIPI_0P8
0.10
VDD_SNVS_0P8
0.10
VDD_SOC
4.50
VDD_ARM_PLL_0P8
0.10
VDD_USB_0P8
2.50
Total2
20.80
NVCC
0.70
NVCC_DRAM
1.50
NVCC_ENET
0.10
NVCC_SNVS_1P8
0.20
PVCC
0.60
VDD_DRAM
6.80
VDD_MIPI_0P8
0.20
VDD_SNVS_0P8
0.10
VDD_SOC
3.50
VDD_ARM_PLL_0P8
0.10
VDD_USB_0P8
2.60
Total2
16.40
Unit
mW
mW
All the power numbers defined in the table are for information only. These numbers are based on typical silicon at 25oC, under
non-OS environment and use case dependent. For power numbers with OS and real use cases, see Power consumption
measurement application note for more details.
2 Sum of the listed supply rails.
3 Low-V suspend mode is low voltage suspend mode. Comparing with suspend mode (VDD_SOC/GPU/DRAM at 0.8 V), Low-V
suspend mode sets VDD_SOC/GPU/DRAM at 0.75 V.
1
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NXP Semiconductors
Electrical characteristics
Table 22. Chip power in different LP mode for 11 x 11 mm package
Mode
SUSPEND
Low-V SUSPEND
2
SNVS
Typ.1
Supply
VDD_SOC
12.1
NVCC_DRAM
2
VDD_SNVS_0P8
0.1
NVCC_SNVS_1P8
0.2
NVCC_CLK_JTAG_PVCC_1P8
1
NVCC_I2C_UART
NVCC_SAI3_SAI5
NVCC_SD1_NAND
NVCC_ECSPI
NVCC_SD2
0.2
NVCC_ENET_GPIO_SAI2
0.3
Total
15.9
VDD_SOC
9.9
NVCC_DRAM
1.5
VDD_SNVS_0P8
0.1
NVCC_SNVS_1P8
0.2
NVCC_CLK_JTAG_PVCC_1P8
0.9
NVCC_I2C_UART
NVCC_SAI3_SAI5
NVCC_SD1_NAND
NVCC_ECSPI
NVCC_SD2
0.2
NVCC_ENET_GPIO_SAI2
0.3
Total
13.1
VDD_SNVS_0P8
0.1
NVCC_SNVS_1P8
0.3
Total
0.4
Unit
mW
mW
mW
All the power numbers defined in the table are for information only. These numbers are based on typical silicon at 25oC, under
non-OS environment and use case dependent. For power numbers with OS and real use cases, see Power consumption
measurement application note for more details.
2 Low-V suspend mode is low voltage suspend mode. Comparing with suspend mode (VDD_SOC at 0.8 V), Low-V suspend
mode sets VDD_SOC at 0.75 V.
1
Table 23 and Table 25 summary the power supply states in all the power modes.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
25
Electrical characteristics
Table 23. The power supply states for 14 x 14 mm package
Power rail
OFF
SNVS
SUSPEND1
IDLE
RUN
VDD_ARM
OFF
OFF
OFF
ON
ON
VDD_SOC
OFF
OFF
ON
ON
ON
VDD_GPU
OFF
OFF
OFF
OFF
ON/OFF
VDD_DRAM
OFF
OFF
ON
ON
ON
Misc_1P82
OFF
OFF
ON
ON
ON
Misc_0P82
OFF
OFF
ON
ON
ON
VDD_MIPI_1P2
OFF
OFF
ON
ON
ON
VDD_MIPI_0P8
OFF
OFF
ON
ON
ON
VDD_DRAM_PLL_0P8
OFF
OFF
ON
ON
ON
VDD_SNVS_0P8
OFF
ON
ON
ON
ON
NVCC_SNVS_1P8
OFF
ON
ON
ON
ON
NVCC_
OFF
OFF
ON
ON
ON
PVCCx_1P8
OFF
OFF
ON
ON
ON
NVCC_DRAM
OFF
OFF
ON
ON
ON
1
SUSPEND is covering normal suspend mode (VDD_SOC/GPU/DRAM at 0.8 V) and Low-V suspend
(VDD_SOC/GPU/DRAM at 0.75 V).
2
See Table 24
Table 24. Group name
Misc_1P8
VDD_24M_XTAL_1P8
VDD_ANA0_1P8
VDD_ANA1_1P8
VDD_ARM_PLL_1P8
VDD_DRAM_PLL_1P8
VDD_MIPI_1P8
VDD_USB_1P8
Misc_0P8
VDD_ANA_0P8
VDD_ARM_PLL_0P8
VDD_USB_0P8
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NXP Semiconductors
Electrical characteristics
Table 25. The power supply states for 11 x 11 mm package
Power rail
VDD_SOC
OFF
SNVS
SUSPEND
IDLE
RUN
OFF
OFF
ON
ON
ON
VDD_ANA1_XTAL_MIPI_ OFF
USB_1P8,
VDD_ANA0_ARM_PLL_
1P8,
VDD_DRAM_PLL_1P8
OFF
ON
ON
ON
VDD_MIPI_1P2
OFF
OFF
ON
ON
ON
VDD_SNVS_0P8
OFF
ON
ON
ON
ON
NVCC_SNVS_1P8
OFF
ON
ON
ON
ON
NVCC_
OFF
OFF
ON
ON
ON
NVCC_DRAM
OFF
OFF
ON
ON
ON
3.2
Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case scenario)
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
27
Electrical characteristics
3.2.1
Power-up sequence
Figure 3 illustrates the power-up sequence for 14 x 14 mm package of i.MX 8M Nano applications
processor.
NVCC_SNVS_1P8
T1
VDD_SNVS_0P8
T2
RTC_RESET_B
T3
32K RTC_XTALI
t1
PMIC_ON_REQ
VDD_SOC,VDD_ANA_0P8,VDD_ARM_PLL_0P8
VDD_USB_0P8
VDD_GPU,VDD_DRAM,
VDD_DRAM_PLL_0P8
T4
T5
T6
VDD_MIPI_0P8
VDD_ARM
VDD_ANAx_1P8,VDD_DRAM_PLL_1P8,VDD_MIPI_1P8,
VDD_24M_XTAL_1P8,VDD_USB_1P8
VDD_ARM_PLL_1P8
PVCCx_1P8, NVCC_xxx (1.8 V)
NVCC_DRAM
T7
T8
T9
T10
T11
NVCC_xxx (2.5 and 3.3 V),VDD_USB_3P3
VDD_MIPI_1P2
T12
T13
POR_B
Figure 3. The power-up sequence for 14 x 14 mm package
NOTE
VDD_MIPI_1P2 should power up after VDD_MIPI_0P8 and
VDD_MIPI_1P8, and it can power up before the POR_B release or after the
POR_B release.
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28
NXP Semiconductors
Electrical characteristics
Table 26 represents the timing parameters of the power-up sequence for 14 x 14 mm package.
Table 26. Power-up sequence for 14 x 14 mm package
Description
Min
Typ
Max
Unit
T1
Delay from NVCC_SNVS_1P8 to VDD_SNVS_0P8
0
2
—
ms
T2
Delay from VDD_SNVS_0P8 high or RTC_SET_B de-assert
0
10
—
ms
T3
Delay from RTC_RESET_B de-assert to stable 32 k existed
—
40
100
s
T4
Delay from PMIC_ON_REQ assert to analog 0.8 V on
0
0.2
—
ms
T5
Delay from analog 0.8 V on to analog 0.8/0/9 V on
0
2
—
ms
T6
Delay from analog 0.8/0.9 V on to PHY 0.9 V on
0
15
—
s
T7
Delay from PHY 0.9 V on to VDD_ARM on
0
2
—
ms
T8
Delay from VDD_ARM on to analog 1.8 V on
0
15
—
s
T9
Delay from analog 1.8 V on to digital 1.8 V on
0
2
—
ms
T10
Delay from digital 1.8 V on to NVCC_DRAM on
0
2
—
ms
T11
Delay from NVCC_DRAM on to digital 2.5 V and 3.3 V on
0
2
—
ms
T12
Delay from digital 2.5 V and 3.3 V on to PHY 1.2 V on
0
2
—
ms
T131
Delay from digital 2.5 V and 3.3 V on to POR_B de-assert
0
20
—
ms
t1
Uncertain period before PMIC_ON_REQ assert during VDD_SNVS_0P8 ramp up.
For ramp up requirement, only VDD_ANA0_1P8 has 5 s minimum requirement, others do not have such
requirement.
During power-up, make sure NVCC_xxx - PVCCx_1P8 < 2 V.
1
The values of T13 depend on T2. RTC_RESET_B must be de-assert before POR_B de-asserts.
Figure 4 illustrates the power-up sequence for 11 x 11 mm package of i.MX 8M Nano applications
processor.
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NXP Semiconductors
29
Electrical characteristics
NVCC_SNVS_1P8
T1
VDD_SNVS_0P8
T2
RTC_RESET_B
T3
32K RTC_XTALI
t1
PMIC_ON_REQ
T4
VDD_SOC
T5
VDD_ANA1_XTAL_MIPI_USB_1P8,
VDD_ANA0_ARM_PLL_1P8,VDD_DRAM_PLL_1P8
T6
NVCC_xxx (1.8V)
T7
NVXX_DRAM
T8
NVCC_xxx (3.3 V), VDD_USB_3P3
T9
VDD_MIPI_1P2
T10
POR_B
Figure 4. The power-up sequence for 11 x 11 mm package
NOTE
VDD_MIPI_1P2 should power up after Analog 1.8 V on, and it can power
up before POR_B release or after POR_B release.
Table 27 represents the timing parameters of the power-up sequence for 11 x 11 mm package.
Table 27. Power-up sequence for 11 x 11 mm package
Description
Min
Typ
Max
Unit
T1
Delay from NVCC_SNVS_1P8 to VDD_SNVS_0P8
0
2
—
ms
T2
Delay from VDD_SNVS_0P8 high or RTC_SET_B de-assert
0
10
—
ms
T3
Delay from RTC_RESET_B de-assert to stable 32 k existed
—
40
100
s
T4
Delay from PMIC_ON_REQ assert to ARM, analog and PHY
0.8/0.9 V on
0
5
—
ms
T5
Delay from SOC, analog and PHY 0.8/0.9 V to analog 1.8 V on
0
15
—
s
T6
Delay from analog 1.8 V on to digital 1.8 V on
0
2
—
ms
T7
Delay from digital 1.8 V on to NVCC_DRAM on
0
2
—
ms
T8
Delay from NVCC_DRAM on to digital 3.3 V on
0
2
—
ms
T9
Delay from analog 1.8 V on to PHY 1.2 V on
0
2
—
ms
0
20
—
ms
T10
Delay from digital 3.3 V on to POR_B de-assert
1
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Electrical characteristics
Table 27. Power-up sequence for 11 x 11 mm package (continued)
Description
t1
Min
Typ
Max
Unit
Uncertain period before PMIC_ON_REQ assert during VDD_SNVS_0P8 ramp up.
For ramp up requirement, only VDD_ANA0_ARM_PLL_1P8 has 5 s minimum requirement, others do not have
such requirement.
1
The values of T10 depend on T2. RTC_RESET_B must be de-assert before POR_B de-asserts.
3.2.2
Power-down sequence
Figure 5 illustrates the power-down sequence for 14 x 14 mm package of i.MX 8M Nano applications
processor.
VDD_MIPI_1P2
T1
NVCC_xxx (2.5 and 3.3 V)
T2
NVCC_DRAM
T3
PVCCx_1P8, NVCC_xxx (1.8V)
VDD_ANAx_1P8, VDD_DRAM_PLL_1P8,VDD_MIPI_1P8
VDD_24M_XTAL_1P8,VDD_USB_1P8
T4
T5
VDD_ARM
T6
VDD_MIPI_0P8
VDD_GPU, VDD_DRAM,
VDD_DRAM_PLL_0P8
T7
T8
VDD_SOC, VDD_ANA_0P8
VDD_USB_0P8
T9
32K RTC_XTALI
T10
RTC_RESET_B
VDD_SNVS_0P8
T11
NVCC_SNVS_1P8
T12
Figure 5. The power-down sequence for 14 x 14 mm package
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
31
Electrical characteristics
Table 28 represents the timing parameters of the power-down sequence for 14 x 14 mm package.
Table 28. Power-down sequence for 14 x 14 mm package
Description
Min
Typ
Max
Unit
T1
Delay from PHY 1.2 V off to digital 2.5 V and 3.3 V off
0
10
—
ms
T2
Delay from digital 2.5 V and 3.3 V off to NVCC_DRAM off
0
10
—
ms
T3
Delay from NVCC_DRAM off to digital 1.8 V off
0
10
—
ms
T4
Delay from digital 1.8 V off to analog 1.8 V off
0
10
—
ms
T5
Delay from analog 1.8 V off to VDD_ARM off
0
10
—
ms
T6
Delay from VDD_ARM off to PHY 0.9 V off
0
10
—
ms
T7
Delay from PHY 0.9 V off to analog 0.8/0.9 V off
0
10
—
ms
T8
Delay from analog 0.8/0.9 V off to analog 0.8 V off
0
10
—
ms
T9
Delay from analog 0.8 V off to 32k off
0
10
—
ms
T10
Delay from 32k off to RTC_RESET_B assert
0
10
—
ms
T11
Delay from RTC_RESET_B assert to VDD_SNVS_0P8 off
0
10
—
ms
T12
Delay from VDD_SNVS_0P8 off to NVCC_SNVS_1P8 off
0
10
—
ms
During power-down, make sure NVCC_xxx - PVCCx_1P8 < 2 V.
Figure 6 illustrates the power-down sequence for 11 x 11 mm package of i.MX 8M Nano applications
processor.
VDD_MIPI_1P2
T1
NVCC_xxx (3.3 V)
T2
NVCC_DRAM
T3
NVCC_xxx (1.8 V)
VDD_ANA1_XTAL_MIPI_USB_1P8
VDD_ANA0_ARM_PLL_1P8,VDD_DRAM_PLL_1P8
T4
T5
VDD_SOC
32K RTC_XTALI
RTC_RESET_B
VDD_SNVS_0P8
T6
T7
T8
T9
NVCC_SNVS_1P8
Figure 6. The power-down sequence for 11 x 11 mm package
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NXP Semiconductors
Electrical characteristics
Table 29 represents the timing parameters of the power-down sequence for 11 x 11 mm package.
Table 29. Power-down sequence for 11 x 11 mm package
Description
3.3
Min
Typ
Max
Unit
T1
Delay from PHY 1.2 V off to digital 2.5 V and 3.3 V off
0
10
—
ms
T2
Delay from digital 2.5 V and 3.3 V off to NVCC_DRAM off
0
10
—
ms
T3
Delay from NVCC_DRAM off to digital 1.8 V off
0
10
—
ms
T4
Delay from digital 1.8 V off to analog 1.8 V off
0
10
—
ms
T5
Delay from analog 1.8 V off to VDD_SOC off
0
40
—
ms
T6
Delay from VDD_SOC off to 32k off
0
10
—
ms
T7
Delay from 32k off to RTC_RESET_B assert
0
10
—
ms
T8
Delay from RTC_RESET_B assert to VDD_SNVS_0P8 off
0
10
—
ms
T9
Delay from VDD_SNVS_0P8 off to NVCC_SNVS_1P8 off
0
10
—
ms
PLL electrical characteristics
Table 30 shows PLL electrical characteristics.
Table 30. PLL electrical parameters
PLL type
Parameter
Value
AUDIO_PLL1
Clock output range
Maximum 650 MHz
Reference clock
24 MHz
Lock time1
500 s
Clock output range
Maximum 650 MHz
Reference clock
24 MHz
Lock time
500 s
Clock output range
Maximum 650 MHz
Reference clock
24 MHz
Lock time
500 s
Clock output range
800 MHz
Reference clock
24 MHz
Lock time
50 s
Clock output range
1 GHz
Reference clock
24 MHz
Lock time
50 s
AUDIO_PLL2
VIDEO_PLL1
SYS_PLL1
SYS_PLL2
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
33
Electrical characteristics
Table 30. PLL electrical parameters (continued)
PLL type
Parameter
Value
SYS_PLL3
Clock output range
600 MHz — 1 GHz
Reference clock
24 MHz
Lock time
50 s
Clock output range
800 MHz — 2 GHz
Reference clock
24 MHz
Lock time
50 s
Clock output range
400 MHz — 800 MHz
Reference clock
24 MHz
Lock time
50 s
Clock output range
400 MHz — 800 MHz
Reference clock
24 MHz
Lock time
500 s
Clock output range
800 MHz — 1600 MHz
Reference clock
24 MHz
Lock time
50 s
ARM_PLL
M7_ALT_PLL
DRAM_PLL
GPU_PLL
1
Lock time is referring from PLL enable to valid lock flag time.
3.4
3.4.1
On-chip oscillators
OSC24M
A 24 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for the CPU,
BUS, and high-speed interfaces. For fractional PLLs, the 24 MHz clock from the oscillator can be used as
the PLL reference clock directly.
Table 31. Crystal specifications1
1
Parameter Description
Min
Typ
Max
Unit
Frequency
—
24
—
MHz
Cload
—
12
—
pF
Drive level
100
—
—
W
ESR
—
—
80
Actual working drive level is depend on real design. Please contact crystal vendor for selecting drive level of crystal.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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NXP Semiconductors
Electrical characteristics
3.4.2
OSC32K
An external 32.768 kHz oscillator is necessary.
3.5
General purpose I/O (GPIO) DC parameters
Table 32 shows DC parameters for GPIO pads. The parameters in Table 32 are guaranteed per the
operating ranges in Table 15, unless otherwise noted.
Table 32. GPIO DC parameters
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
VOH (1.8 V)
IOH = 1.6/3.2/6.4/9.6 mA (1.8 V)
IOH = 2/4/8/12 mA (3.3 V)
0.8 x VDD
—
VDD
V
0.8 x VDD
—
VDD
V
0
—
0.2 x VDD
V
0
—
0.2 x VDD
V
VOH (3.3 V)
Low-level output voltage
VOL (1.8 V)
VOL (3.3 V)
IOL = 1.6/3.2/6.4/9.6 mA (1.8 V)
IOL = 2/4/8/12 mA (3.3 V)
High-level input voltage
VIH
—
0.7 x VDD
—
VDD + 0.3
V
Low-level input voltage
VIL
—
-0.3
—
0.3 x VDD
V
Pull-up resistor
—
12
22
49
K
Pull-down resistor
—
VDD = 1.65 - 1.95V
Temp = 0 - 95 oC
13
23
48
K
Pull-up resistor
—
13
24
69
K
Pull-down resistor
—
VDD = 2.25 - 2.75V
Temp = 0 - 95 oC
9.1
33
69
K
Pull-up resistor
—
18
37
72
K
Pull-down resistor
—
VDD = 3.0 - 3.6V
Temp = 0 - 95 oC
24
43
87
K
High level input current
IIH
—
-4
—
4
A
Low level input current
IIL
—
-0.7
—
0.7
A
Table 33. Additional leakage parameters
Parameter
High level input current
Low level input current
Symbol
IIH
IIL
Pins
Min
Max
USB1_Dx
-30
30
MIPI_CSI
-4
4
USB1_ID, ONOFF, POR_B
-1
1
USB1_ID
-200
200
USB1_Dx
-6
6
MIPI_CSI, ONOFF, POR_B
-0.7
0.7
Unit
A
A
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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35
Electrical characteristics
3.5.1
DDR I/O DC electrical characteristics
The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory
Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs.
DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout
requirements stated in the hardware development guide for the i.MX 8M Nano applications processor.
3.6
I/O AC parameters
This section includes the AC parameters of the following I/O types:
• General Purpose I/O (GPIO)
The GPIO load circuit and output transition time waveforms are shown in Figure 7 and Figure 8.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 7. Load circuit for output
80%
80%
20%
Output (at pad)
tf
tr
OVDD
20%
0V
Figure 8. Output transition time waveform
3.6.1
General purpose I/O AC parameters
This section presents the I/O AC parameters for GPIO in different modes. Note that the fast or slow I/O
behavior is determined by the appropriate control bits in the IOMUXC control registers.
Table 34. Maximum frequency of operation for input
Maximum frequency (MHz)
VDD = 1.8 V, CL = 50 pF
VDD = 3.3 V, CL = 50 pF
450
440
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Electrical characteristics
Table 35. Maximum frequency of operation for output
Maximum Frequency (MHz)
Parameter
VDD = 1.8 V
VDD = 3.3 V
dse[2:0]
sre[1:0]
Driver type
CL = 10 pF
CL = 20 pF
CL = 10 pF
CL = 20 pF
00X
0X
1x Slow Slew
150
80
120
65
00X
1X
1x Fast Slew
150
80
120
65
10X
0X
2x Slow Slew
160
90
150
80
10X
1X
2x Fast Slew
160
90
150
80
01X
0X
4x Slow Slew
200
100
180
90
01X
1X
4x Fast Slew
200
100
180
90
11X
0X
6x Slow Slew
250
130
200
100
11X
1X
6x Fast Slew
250
130
200
100
3.7
Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX 8M Nano family of processors for the
following I/O types:
NOTE
DDR I/O output driver impedance is measured with “long” transmission
line of impedance Ztl attached to I/O pad and incident wave launched into
transmission line. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 9).
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Electrical characteristics
OVDD
PMOS (Rpu)
Ztl W, L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
Vin (do)
VDD
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Rpu =
Vovdd - Vref1
x Ztl
Vref1
Rpd =
Vref2
x Ztl
Vovdd - Vref2
Figure 9. Impedance matching load for measurement
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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Electrical characteristics
3.7.1
DDR I/O output buffer impedance
Table 36 shows DDR I/O output buffer impedance of i.MX 8M Nano family of processors.
Table 36. DDR I/O output buffer impedance
Parameter
Symbol
Output Driver
Impedance
Rdrv
Test Conditions
DSE
(Drive Strength)
Typical
NVCC_DRAM = 1.35 V
(DDR3L)
NVCC_DRAM = 1.2 V
(DDR4)
NVCC_DRAM = 1.1 V
(LPDDR4)
000000
Hi-Z
Hi-Z
Hi-Z
000010
240
240
240
001000
120
120
120
001010
80
80
80
011000
60
60
60
011010
48
48
48
111000
40
40
40
111010
34
34
34
Unit
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
3.8
System modules timing
This section contains the timing and electrical parameters for the modules in each i.MX 8M Nano
processor.
3.8.1
Reset timings parameters
Figure 10 shows the reset timing and Table 37 lists the timing parameters.
POR_B
(Input)
CC1
Figure 10. Reset timing diagram
Table 37. Reset timing parameters
ID
CC1
Parameter
Duration of POR_B to be qualified as valid.
Min
Max
Unit
1
—
RTC_XTALI cycle
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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39
Electrical characteristics
3.8.2
WDOG Reset timing parameters
Figure 11 shows the WDOG reset timing and Table 38 lists the timing parameters.
WDOGx_B
(Output)
CC3
Figure 11. WDOGx_B timing diagram
Table 38. WDOGx_B timing parameters
ID
CC3
Parameter
Duration of WDOG1_B Assertion
Min
Max
Unit
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOGx_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the
IOMUXC chapter of the i.MX 8M Nano Applications Processor Reference
Manual (IMX8MNRM) for detailed information.
3.9
External peripheral interface parameters
The following subsections provide information on external peripheral interfaces.
3.9.1
ECSPI timing parameters
This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.
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Electrical characteristics
3.9.1.1
ECSPI Master mode timing
Figure 12 depicts the timing of ECSPI in master mode. Table 39 lists the ECSPI master mode timing
characteristics.
ECSPIx_RDY_B
ECSPIx_SS_B
CS10
CS2
CS3
CS1
CS5
CS6
CS4
ECSPIx_SCLK
CS7 CS3
CS2
ECSPIx_MOSI
CS8
CS9
ECSPIx_MISO
Figure 12. ECSPI Master mode timing diagram
Table 39. ECSPI Master mode timing parameters
ID
Parameter
2
Min
Max
Unit
CS1
ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
tclk
43
15
—
ns
CS2
ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
21.5
7
—
ns
CS3
ECSPIx_SCLK Rise or Fall1
tRISE/FALL
—
—
ns
CS4
ECSPIx_SS_B pulse width
tCSLH
Half ECSPIx_SCLK period
—
ns
CS5
ECSPIx_SS_B Lead Time (CS setup time)
tSCS
Half ECSPIx_SCLK period - 4
—
ns
CS6
ECSPIx_SS_B Lag Time (CS hold time)
tHCS
Half ECSPIx_SCLK period - 2
—
ns
CS7
ECSPIx_MOSI Propagation Delay (CLOAD = 20 pF)
tPDmosi
-1
1
ns
CS8
ECSPIx_MISO Setup Time
tSmiso
18
—
ns
CS9
ECSPIx_MISO Hold Time
tHmiso
0
—
ns
tSDRY
5
—
ns
CS10 RDY to ECSPIx_SS_B Time2
1
Symbol
See specific I/O AC parameters Section 3.6, I/O AC parameters”.
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
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41
Electrical characteristics
3.9.1.2
ECSPI Slave mode timing
Figure 13 depicts the timing of ECSPI in Slave mode. Table 40 lists the ECSPI Slave mode timing
characteristics.
ECSPIx_SS_B
CS2
CS1
CS5
CS6
CS4
ECSPIx_SCLK
CS2
CS9
ECSPIx_MISO
CS7
CS8
ECSPIx_MOSI
Figure 13. ECSPI Slave mode timing diagram
Table 40. ECSPI Slave mode timing parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPI_SCLK Cycle Time–Write
tclk
15
43
—
ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
7
21.5
—
ns
CS4 ECSPIx_SS_B pulse width
tCSLH
Half ECSPIx_SCLK period
—
ns
CS5 ECSPIx_SS_B Lead Time (CS setup time)
tSCS
5
—
ns
CS6 ECSPIx_SS_B Lag Time (CS hold time)
tHCS
5
—
ns
CS7 ECSPIx_MOSI Setup Time
tSmosi
4
—
ns
CS8 ECSPIx_MOSI Hold Time
tHmosi
4
—
ns
CS9 ECSPIx_MISO Propagation Delay (CLOAD = 20 pF)
tPDmiso
4
19
ns
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Electrical characteristics
3.9.2
Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC 5.1 (single data
rate) timing, eMMC 5.1/SD3.0 (dual data rate) AC timing, and SDR50/SDR104 AC timing.
3.9.2.1
SD/eMMC5.1 (single data rate) AC timing
Figure 14 depicts the timing of SD3.0/eMMC5.1 (SDR), and Table 41 lists the SD3.0/eMMC5.1 (SDR)
timing characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 14. SD3.0/eMMC5.1 (SDR) timing
Table 41. SD3.0/eMMC5.1 (SDR) interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Clock Frequency (Low Speed)
fPP1
0
400
kHz
Clock Frequency (SD/SDIO Full Speed/High Speed)
fPP2
0
25/50
MHz
Clock Frequency (MMC Full Speed/High Speed)
fPP3
0
20/52
MHz
Clock Frequency (Identification Mode)
fOD
100
400
kHz
SD2
Clock Low Time
tWL
7
—
ns
SD3
Clock High Time
tWH
7
—
ns
SD4
Clock Rise Time
tTLH
—
3
ns
SD5
Clock Fall Time
tTHL
—
3
ns
3.6
ns
Card Input Clock
SD1
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6
uSDHC Output Delay
tOD
6.6
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Electrical characteristics
Table 41. SD3.0/eMMC5.1 (SDR) interface timing specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD7
uSDHC Input Setup Time
SD8
4
uSDHC Input Hold Time
tISU
2.5
—
ns
tIH
1.5
—
ns
1
In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0 – 25 MHz. In High-speed mode,
clock frequency can be any value between 0 – 50 MHz.
3
In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0 – 20 MHz. In High-speed mode,
clock frequency can be any value between 0 – 52 MHz.
4
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
2
3.9.2.2
eMMC5.1/SD3.0 (dual data rate) AC timing
Figure 15 depicts the timing of eMMC5.1/SD3.0 (DDR). Table 42 lists the eMMC5.1/SD3.0 (DDR)
timing characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to
CMD).
SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
......
Figure 15. eMMC5.1/SD3.0 (DDR) timing
Table 42. eMMC5.1/SD3.0 (DDR) interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency (eMMC5.1 DDR)
fPP
0
52
MHz
SD1
Clock Frequency (SD3.0 DDR)
fPP
0
50
MHz
6.9
ns
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2
uSDHC Output Delay
tOD
2.7
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
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Electrical characteristics
Table 42. eMMC5.1/SD3.0 (DDR) interface timing specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SD3
uSDHC Input Setup Time
tISU
2.4
—
ns
SD4
uSDHC Input Hold Time
tIH
1.3
—
ns
3.9.2.3
HS400 DDR AC timing
Figure 16 depicts the timing of HS400 mode, and Table 43 lists the HS400 timing characteristics. Be
aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD
input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check
SD5, SD6, and SD7 parameters in Table 45 SDR50/SDR104 Interface Timing Specification for CMD
input/output timing for HS400 mode.
SD1
SD3
SD2
SCK
SD4
SD5
DAT0
DAT1
...
SD4
SD5
Output from
uSDHC to eMMC DAT7
Strobe
Input from
eMMC to uSDHC
SD6
DAT0
DAT1
...
SD7
DAT7
Figure 16. HS400 Mode timing
Table 43. HS400 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock frequency
fPP
0
200
MHz
SD2
Clock low time
tCL
0.46 x tCLK
0.54 x tCLK
ns
SD3
Clock high time
tCH
0.46 x tCLK
0.54 x tCLK
ns
uSDHC Output/Card Inputs DAT (Reference to SCK)
SD4
Output skew from data of edge of SCK
tOSkew1
0.45
—
ns
SD5
Output skew from edge of SCk to data
tOSkew2
0.45
—
ns
uSDHC Input/Card Outputs DAT (Reference to Strobe)
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Electrical characteristics
Table 43. HS400 interface timing specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SD6
uSDHC input skew
tRQ
—
0.45
ns
SD7
uSDHC hold skew
tRQH
—
0.45
ns
3.9.2.4
HS200 Mode AC timing
Figure 17 depicts the timing of HS200 mode, and Table 44 lists the HS200 timing characteristics.
SD1
SD2
SD3
SCK
SD4/SD5
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD8
Figure 17. HS200 timing
iti
Table 44. HS200 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency Period
tCLK
5.0
—
ns
SD2
Clock Low Time
tCL
0.3 x tCLK
0.7 x tCLK
ns
SD3
Clock High Time
tCH
0.3 x tCLK
0.7 x tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
SD5
uSDHC Output Delay
tOD
-1.6
1
ns
—
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
SD8
1
uSDHC Output Data Window
tODW
0.5 x tCLK
HS200 is for 8 bits while SDR104 is for 4 bits.
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Electrical characteristics
3.9.2.5
SDR50/SDR104 AC timing
Figure 18 depicts the timing of SDR50/SDR104, and Table 45 lists the SDR50/SDR104 timing
characteristics.
SD1
SD2
SD3
SCK
SD4/SD5
8-bit output from uSDHC to eMMC
SD6
SD7
8-bit input from eMMC to uSDHC
SD8
Figure 18. SDR50/SDR104 timing
Table 45. SDR50/SDR104 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
5
—
ns
Card Input Clock
SD1
Clock Frequency Period
tCLK
SD2
Clock Low Time
tCL
0.46 x tCLK 0.54 x tCLK
ns
SD3
Clock High Time
tCH
0.46 x tCLK 0.54 x tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4
uSDHC Output Delay
tOD
-3
1
ns
1
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
SD5
uSDHC Output Delay
tOD
-1.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD6
uSDHC Input Setup Time
tISU
2.4
—
ns
SD7
uSDHC Input Hold Time
tIH
1.4
—
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
SD8
1
uSDHC Output Data Window
tODW
0.5 x tCLK
—
ns
Data window in SDR100 mode is variable.
3.9.2.6
Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.5/5.0/5.1 can be 1.8 V or 3.3 V depending on the working mode. The DC
parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are identical to those shown in
Table 32, "GPIO DC parameters," on page 35.
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Electrical characteristics
3.9.3
Ethernet controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
Table 46. ENET signal mapping
Pad name
RGMII/RMII
signal
Mode
Alt mode
Direction
ENET_MDC
MDC
RMII/RGMII
ALT0
O
—
ENET_MDIO
MDIO
RMII/RGMII
ALT0
I/O
—
ENET_TD3
TX_D3
RGMII
ALT0
O
Only used for RGMII
ENET_TD2
REF_CLK
RMII
ALT1
I/O
TX_D2
RGMII
ALT0
Used as RMII clock and RGMII data, there
are two RMII clock schemes.
• MAC generate output 50M reference clock
for PHY, and MAC also use this 50M clock.
• MAC use external 50M clock.
For RMII—ENET_TD2 functions as RMII
REF_CLK when configured in the ALT1
mode.
ENET_TD1
TX_D1
RMII/RGMII
ALT0
O
—
ENET_TD0
TX_D0
RMII/RGMII
ALT0
O
—
ENET_TX_CTL
TX_EN
RMII
ALT0
O
—
TX_CTL
RGMII
ALT0
TX_ER
RMII
ALT1
O
TXC
RGMII
ALT0
For RMII—ENET_TXC functions as RMII
TX_ER when configured in the ALT1 mode.
For RGMII—ENET_TXC functions as RGMII
TXC when configured in the ALT0 mode.
RX_EN
(CRS_DV)
RMII
ALT0
I
—
RX_CTL
RGMII
ALT0
RX_ER
RMII
ALT1
I
RXC
RGMII
ALT0
For RMII—ENET_RXC functions as RMII
RX_ER when configured in the ALT1 mode.
For RGMII—ENET_RXC functions as RGMII
RXC when configured in the ALT0 mode.
ENET_RD0
RX_D0
RMII/RGMII
ALT0
I
—
ENET_RD1
RX_D1
RMII/RGMII
ALT0
I
—
ENET_RD2
RX_D2
RGMII
ALT0
I
—
ENET_RD3
RX_D3
RGMII
ALT0
I
—
GPIO1_IO06
MDC
RMII/RGMII
ALT1
O
—
GPIO1_IO07
MDIO
RMII/RGMII
ALT1
I/O
—
I2C1_SCL
MDC
RMII/RGMII
ALT1
O
—
I2C1_SDA
MDIO
RMII/RGMII
ALT1
I/O
—
ENET_TXC
ENET_RX_CTL
ENET_RXC
Comments
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Electrical characteristics
Table 46. ENET signal mapping (continued)
RGMII/RMII
signal
Pad name
Mode
Alt mode
Direction
Comments
GPIO1_IO08
1588_EVENT0_
IN
RMII/RGMII
ALT1
I
Capture/compare block input/output event
bus signal. When configured for capture and
a rising edge is detected, the current timer
value is latched and transferred into the
corresponding ENET_TCCRn register for
inspection by software. When configured for
compare, the corresponding signal
1588_EVENT is asserted for one cycle when
the timer reaches the compare value
programmed in register ENET_TCCRn. An
interrupt or DMA request can be triggered if
the corresponding bit in ENET_TCSRn[TIE]
or ENET_TSCRn[TDRE] is set.
GPIO1_IO09
1588_EVENT0_
OUT
RMII/RGMII
ALT1
O
—
I2C2_SCL
1588_EVENT1_
IN
RMII/RGMII
ALT1
I
—
I2C2_SDA
1588_EVENT1_
OUT
RMII/RGMII
ALT1
O
—
GPIO1_IO00
ENET_PHY_RE
F_CLK_ROOT
RGMII
ALT1
O
Reference clock for PHY.
SD1_CLK
MDC
RMII
ALT1
O
—
SD1_CMD
MDIO
RMII
ALT1
I/O
—
SD1_DATA0
TX_D1
RMII
ALT1
O
—
SD1_DATA1
TX_D0
RMII
ALT1
O
—
SD1_DATA2
RX_D0
RMII
ALT1
I
—
SD1_DATA3
RX_D1
RMII
ALT1
I
—
SD1_DATA4
TX_EN
RMII
ALT1
O
—
SD1_DATA5
TX_ER
RMII
ALT1
O
For RMII—SD1_DATA5 functions as RMII
TX_ER when configured in the ALT1 mode.
SD1_DATA6
RX_EN
(CRS_DV)
RMII
ALT1
I
—
SD1_DATA7
RX_ER
RMII
ALT1
I
For RMII—SD1_DATA7 functions as RMII
RX_ER when configured in the ALT1 mode.
SD1_RESET_B
REF_CLK
RMII
ALT1
O
For RMII—SD1_RESET_B functions as RMII
REF_CLK when configured in the ALT1
mode.
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Electrical characteristics
3.9.3.1
RMII mode timing
Figure 19 shows RMII mode timings. Table 47 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TXD[1:0] (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RXD[1:0]
ENET_RX_ER
M20
M21
Figure 19. RMII mode signal timing diagram
Table 47. RMII signal timing
ID
Characteristic
Min.
Max.
Unit
M16
ENET_CLK pulse width high
35%
65%
ENET_CLK period
M17
ENET_CLK pulse width low
35%
65%
ENET_CLK period
M18
ENET_CLK to ENET_TXD[1:0], ENET_TXD invalid
4
—
ns
M19
ENET_CLK to ENET_TXD[1:0], ENET_TXD valid
—
15
ns
M20
ENET_RXD[1:0], ENET_RX_EN, ENET_RX_ER to ENET_CLK setup
4
—
ns
M21
ENET_CLK to ENET_RXD[1:0], ENET_RX_EN, ENET_RX_ER hold
2
—
ns
3.9.3.2
RGMII signal switching specifications
The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver
devices.
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Electrical characteristics
Table 48. RGMII signal switching specifications1
Symbol
Tcyc2
Description
Clock cycle duration
TskewT3
Data to clock output skew at transmitter
Min.
Max.
Unit
7.2
8.8
ns
-500
500
ps
3
Data to clock input skew at receiver
1
2.6
ns
4
Duty_G
Duty cycle for Gigabit
45
55
%
Duty_T4
Duty cycle for 10/100T
40
60
%
Tr/Tf
Rise/fall time (20–80%)
—
0.75
ns
TskewR
1
The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
2
For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
3
For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional
trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value
is unspecified.
4
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long
as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned
between.
2'-))?48#ATTRANSMITTER
4SKEW4
2'-))?48$NNTO
2'-))?48?#4,
48%.
48%22
4SKEW2
2'-))?48#ATRECEIVER
Figure 20. RGMII transmit signal timing diagram original
2'-))?28#ATTRANSMITTER
4SKEW4
2'-))?28$NNTO
2'-))?28?#4,
28$6
28%22
4SKEW2
2'-))?28#ATRECEIVER
Figure 21. RGMII receive signal timing diagram original
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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51
Electrical characteristics
2'-))?28#SOURCEOFDATA
)NTERNALDELAY
4SETUP4
4HOLD4
4SETUP2
4HOLD2
2'-))?28$NNTO
28$6
2'-))?28?#4,
28%22
2'-))?28#ATRECEIVER
Figure 22. RGMII receive signal timing diagram with internal delay
3.9.4
General-purpose media interface (GPMI) timing
The i.MX 8M Nano GPMI controller is a flexible interface NAND Flash controller with 8-bit data width,
up to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous Timing mode, Source Synchronous Timing mode and Toggle Timing mode
separately, as described in the following subsections.
3.9.4.1
Asynchronous mode AC timing (ONFI 1.0 compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 23 through Figure 26
depicts the relative timing between GPMI signals at the module level for different operations under
Asynchronous mode. Table 49 describes the timing parameters (NF1–NF17) that are shown in the figures.
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NF2
NF1
.!.$?#,%
NF3
NF4
NF5
NF6
NF8
.!.$?$!4!XX
NF7
NF9
Command
Figure 23. Command Latch cycle timing diagram
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Electrical characteristics
NF1
.!.$?#,%
NF3
.!.$?#%?"
NF10
.!.$?7%?"
NF5
.!.$?!,%
NF11
NF7
NF6
NF8
NAND_DATAxx
NF9
Address
Figure 24. Address Latch cycle timing diagram
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.!.$?#%?"
NF1
NF3
NF10
NF5
.!.$?7%?"
.!.$?!,%
NF11
NF7
NF6
NF9
NF8
.!.$?$!4!XX
Data to NF
Figure 25. Write Data Latch cycle timing diagram
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.!.$?#%?"
NF14
.!.$?2%?"
.!.$?2%!$9?"
NF15
NF13
NF12
NF16
.!.$?$!4!XX
NF17
Data from NF
Figure 26. Read Data Latch cycle timing diagram (Non-EDO Mode)
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.!.$?#%?"
NF14
NF13
.!.$?2%?"
.!.$?2%!$9?"
NF12
NF15
NF17
NF16
NAND_DATAxx
Data from NF
Figure 27. Read Data Latch cycle timing diagram (EDO mode)
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53
Electrical characteristics
Table 49. Asynchronous mode timing parameters1
ID
Parameter
Timing
T = GPMI Clock Cycle
Symbol
Unit
Min.
NF1
NF2
NF3
NF4
NF5
NF6
NF7
NF8
NF9
NF10
NF11
NF12
NF13
NF14
NAND_CLE setup time
NAND_CLE hold time
NAND_CE0_B setup time
NAND_CE0_B hold time
NAND_WE_B pulse width
NAND_ALE setup time
tCLS
(AS + DS) T - 0.12 [see
ns
DH T - 0.72 [see note ]
(AS + DS + 1) T [see notes
(DH+1) T - 1 [see
tCH
ns
3,2
ns
]
ns
]
note2
DS T [see note ]
2
tWP
tALS
]
2
tCLH
tCS
Max.
notes2,3
ns
(AS + DS) T - 0.49 [see notes
3,2
]
ns
tALH
DH T - 0.42 [see
note2
]
ns
tDS
DH T - 0.26 [see
note2]
ns
tDH
DH T - 1.37 [see
note2]
ns
tWC
(DS + DH) T [see
note2]
ns
NAND_WE_B hold time
tWH
DH T [see
Ready to NAND_RE_B low
tRR4
NAND_ALE hold time
Data setup time
Data hold time
Write cycle time
NAND_RE_B pulse width
READ cycle time
(AS + 2) T [see
note2]
3,2]
ns
—
tRP
DS T [see
tRC
(DS + DH) T [see
DS T [see
ns
note2]
ns
note2]
ns
note2]
NF15
NAND_RE_B high hold time
tREH
NF16
Data setup on read
tDSR
—
(DS T -0.67)/18.38 [see
notes5,6]
ns
NF17
Data hold on read
tDHR
0.82/11.83 [see notes5,6]
—
ns
1
2
3
4
5
6
ns
GPMI’s Asynchronous mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
AS minimum value can be 0, while DS/DH minimum value is 1.
T = GPMI clock period -0.075 ns (half of maximum p-p jitter).
NF12 is guaranteed by the design.
Non-EDO mode.
EDO mode, GPMI clock 100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).
In EDO mode (Figure 26), NF16/NF17 are different from the definition in non-EDO mode (Figure 25).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples
NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay
value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Nano
Applications Processor Reference Manual [IMX8MNRM]). The typical value of this control register is
0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value
should be made larger to compensate the board delay.
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3.9.4.2
Source synchronous mode AC timing (ONFI 2.x compatible)
Figure 28 to Figure 30 show the write and read timing of Source Synchronous mode.
NF19
NF18
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NF23
NAND_CLE
NF25
NF26
NF24
NAND_ALE
NF25 NF26
NAND_WE/RE_B
NF22
NAND_CLK
NAND_DQS
NAND_DQS
Output enable
NF20
NF20
NF21
NF21
NAND_DATA[7:0]
CMD
ADD
NAND_DATA[7:0]
Output enable
Figure 28. Source Synchronous mode command and address timing diagram
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55
Electrical characteristics
.!.$?#%?"
NF19
NF18
NF23
.!.$?#,%
NF23
.!.$?!,%
NF25
NF26
NF25
NF26
NF24
NF24
NAND_WE/RE_B
NF22
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NF27
NF27
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.!.$?$13
Output enable
NF29
NF29
.!.$?$1;=
NF28
NF28
.!.$?$1;=
Output enable
Figure 29. Source Synchronous mode data write timing diagram
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NF18
NF19
NF23
.!.$?#,%
NAND_ALE
.!.$?7%2%
NF23
NF25
NF26
NF25
NF26
NF24
NF24
NF25
NF25
NF22
NF26
.!.$?#,+
.!.$?$13
.!.$?$13
/UTPUTENABLE
.!.$?$!4!;=
.!.$?$!4!;=
/UTPUTENABLE
Figure 30. Source Synchronous mode data read timing diagram
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Electrical characteristics
.!.$?$13
NF30
.!.$?$!4!;=
D0
NF30
D1
D2
D3
NF31
NF31
Figure 31. NAND_DQS/NAND_DQ read valid window
Table 50. Source Synchronous mode timing parameters1
ID
Parameter
Symbol
Timing
T = GPMI Clock Cycle
Min.
NF18 NAND_CE0_B access time
NF19 NAND_CE0_B hold time
tCE
tCH
Unit
Max.
CE_DELAY T - 0.79 [see note 2]
0.5 tCK - 0.63 [see
note2]
ns
ns
NF20 Command/address NAND_DATAxx setup time
tCAS
0.5 tCK - 0.05
ns
NF21 Command/address NAND_DATAxx hold time
tCAH
0.5 tCK - 1.23
ns
tCK
—
NF22 clock period
ns
tPRE
PRE_DELAY T - 0.29 [see
NF24 postamble delay
tPOST
POST_DELAY T - 0.78 [see
NF25 NAND_CLE and NAND_ALE setup time
tCALS
0.5 tCK - 0.86
ns
NF26 NAND_CLE and NAND_ALE hold time
tCALH
0.5 tCK - 0.37
ns
NF23 preamble delay
NF27 NAND_CLK to first NAND_DQS latching transition
tDQSS
T - 0.41 [see
note2]
note2]
note2]
NF28 Data write setup
—
0.25 tCK - 0.35
NF29 Data write hold
—
0.25 tCK - 0.85
NF30 NAND_DQS/NAND_DQ read setup skew
—
—
2.06
NF31 NAND_DQS/NAND_DQ read hold skew
—
—
1.95
ns
ns
ns
1
GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
2 T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter).
For DDR Source Synchronous mode, Figure 31 shows the timing diagram of
NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 0.85 ns (max) and 1 ns
(max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an
delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be
controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI
chapter of the i.MX 8M Nano Applications Processor Reference Manual [IMX8MNRM]). Generally, the
typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. But if the
board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the
board delay.
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Electrical characteristics
3.9.4.3
3.9.4.3.1
ONFI NV-DDR2 mode (ONFI 3.2 compatible)
Command and address timing
ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.
See Section 3.9.4.1, Asynchronous mode AC timing (ONFI 1.0 compatible), for details.
3.9.4.3.2
Read and write timing
ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 3.9.4.4, Toggle
mode AC Timing, for details.
3.9.4.4
3.9.4.4.1
Toggle mode AC Timing
Command and address timing
NOTE
Toggle mode command and address timing is the same as ONFI 1.0
compatible Asynchronous mode AC timing. See Section 3.9.4.1,
Asynchronous mode AC timing (ONFI 1.0 compatible), for details.
3.9.4.4.2
Read and write timing
Figure 32. Toggle mode data write timing
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Electrical characteristics
DEV?CLK
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.&
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T#+
.&
T#+
.&
.!.$?2%?"
T#+
T#+
T#+
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Figure 33. Toggle mode data read timing
Table 51. Toggle mode timing parameters
ID
Parameter
Symbol
Timing
T = GPMI Clock Cycle
Min.
Unit
Max.
NF1
NAND_CLE setup time
tCLS
(AS + DS) T - 0.12 [see note1s,2]
NF2
NAND_CLE hold time
tCLH
DH T - 0.72 [see note2]
NF3
NAND_CE0_B setup time
tCS
(AS + DS) T - 0.58 [see notes,2]
NF4
NAND_CE0_B hold time
tCH
DH T - 1 [see note2]
NF5
NAND_WE_B pulse width
tWP
DS T [see note2]
NF6
NAND_ALE setup time
tALS
(AS + DS) T - 0.49 [see notes,2]
NF7
NAND_ALE hold time
tALH
DH T - 0.42 [see note2]
NF8
Command/address NAND_DATAxx setup time
tCAS
DS T - 0.26 [see note2]
NF9
Command/address NAND_DATAxx hold time
tCAH
DH T - 1.37 [see note2]
NF18 NAND_CEx_B access time
tCE
CE_DELAY T [see notes3,2]
—
ns
NF22 clock period
tCK
—
—
ns
tPRE
PRE_DELAY T [see notes4,2]
—
ns
NF23 preamble delay
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Electrical characteristics
Table 51. Toggle mode timing parameters (continued)
ID
Parameter
Symbol
Timing
T = GPMI Clock Cycle
Unit
Min.
Max.
NF24 postamble delay
tPOST
POST_DELAY T + 0.43 [see
note2]
—
ns
NF28 Data write setup
tDS5
0.25 tCK - 0.32
—
ns
0.25 tCK - 0.79
—
ns
—
3.18
ns
—
3.27
ns
NF29 Data write hold
5
tDH
6
NF30 NAND_DQS/NAND_DQ read setup skew
tDQSQ
NF31 NAND_DQS/NAND_DQ read hold skew
tQHS6
1
2
3
4
5
6
AS minimum value can be 0, while DS/DH minimum value is 1.
T = tCK (GPMI clock period) - 0.075 ns (half of maximum p-p jitter).
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started
with enough time of ALE/CLE assertion to low level.
PRE_DELAY + 1 (AS + DS)
Shown in Figure 32.
Shown in Figure 33.
For DDR Toggle mode, Figure 31 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid
window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI
samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which
is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Nano
Applications Processor Reference Manual [IMX8MNRM]). Generally, the typical delay value is equal to
0x7, which means a 1/4 clock cycle delay is expected. But if the board delay is big enough and cannot be
ignored, the delay value should be made larger to compensate the board delay.
3.9.5
I2C bus characteristics
The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is
designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now
NXP Semiconductors).
3.9.6
MIPI D-PHY timing parameters
MIPI D-PHY electrical specifications are compliance.
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Table 52. MIPI PHY worst power dissipation1
MODE
2.1 Gbps
Total power
consume (mW)
M4 on
S4 on
226.1
4.1
35.6
265.8
M4 on
S4 off
164.7
4.03
28.6
197.33
M4 off
S4 on
63.02
0
15.8
78.82
4.26
0.0367
0.0584
4.36
ULPS
1
Power consume on
Power consume on Power consume on
VDD_MIPI_0P8 (mW) VDD_MIPI_1P2 (mW) VDD_MIPI_1P8 (mW)
M4 indicates MIPI DSI have 4 data lane enable (at least 1 clock lane enable). S4 indicates MIPI CSI have 4 data lane enable
(at least 1 clock lane enable).
3.9.7
PDM timing parameters
Figure 34 illustrates the input timing of the PDM.
PDM Clock
PDM Bitstream
ipg_clk_app
Pulse right
pre_channel_1
ipg_dee_clk
Channel 1
Channel 0
Figure 34. PDM input timing
PDM clock operative range is from 500 kHz to 6 MHz. Within range, only need to configure ipg_clk_app
rate and CLKDIV without I/O timing concerns.
3.9.8
Pulse width modulator (PWM) timing parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
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61
Electrical characteristics
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 35 depicts the timing of the PWM, and Table 53 lists the PWM timing parameters.
0
0
07-N?/54
Figure 35. PWM timing
Table 53. PWM output timing parameters
ID
3.9.9
Parameter
Min
Max
Unit
PWM Module Clock Frequency
0
66 (ipg_clk)
MHz
P1
PWM output pulse width high
12
—
ns
P2
PWM output pulse width low
12
—
ns
FlexSPI timing parameters
Measurements are with a load of 15 pF and an input slew rate of 1 V/ns.
3.9.9.1
FlexSPI input/read timing
There are three sources for the internal sample clock for FlexSPI read data:
• Dummy read strobe generated by FlexSPI controller and looped back internally
(FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x1)
• Read strobe provided by memory device and input from DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x3)
The following sections describe input signal timing for each of these four internal sample clock sources.
3.9.9.1.1
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2
Table 54. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol
Parameter
Min.
Max.
Unit
Notes
—
66
MHz
—
—
[D:] Frequency of operation
F1
[D:] Setup time for incoming data
8.67
—
ns
1
F2
[D:] Hold time for incoming data
0
—
ns
—
1
The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.
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Table 55. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1, 0x2
Symbol
Parameter
Min.
Max.
Unit
Notes
—
[D:] Frequency of operation
—
133
MHz
—
F1
[D:] Setup time for incoming data
1.5
—
ns
1
F2
[D:] Hold time for incoming data
1
—
ns
—
1
The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.
FLEXSPI_SCLK
F1
F2
F1
F2
FLEXSPI_DATA[7:0]
Internal Sample Clock
Figure 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge, and FlexSPI controller sampling read data on the falling edge.
3.9.9.1.2
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in SDR mode:
• A1—Memory generates both read data and read strobe on SCK rising edge (or falling edge)
• A2—Memory generates read data on SCK falling edge and generates read strobe on SCK rising
edge
Table 56. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)
Symbol
Parameter
Min.
Max.
Unit
—
[D:] Frequency of operation
—
166
MHz
F3
[D:] Time from SCK to data valid
—
—
ns
F4
[D:] Time from SCK to DQS
—
—
ns
—
[D:] Time delta between TSCKD and
TSCKDQS
-2
2
ns
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Electrical characteristics
FLEXSPI_SCLK
F3
F3
FLEXSPI_DATA[7:0]
F4
F4
FLEXSPI_DQS
Figure 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)
NOTE
Timing shown is based on the memory generating read data and read strobe
on the SCK rising edge. The FlexSPI controller samples read data on the
DQS falling edge.
Table 57. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)
Symbol
Parameter
Min.
Max.
Unit
—
[D:] Frequency of operation
—
166
MHz
F5
[D:] Time from SCK to data valid
—
—
ns
F6
[D:] Time from SCK to DQS
—
—
ns
—
[D:] Time delta between TSCKD and
TSCKDQS
-2
2
ns
FLEXSPI_SCLK
F5
F5
F5
FLEXSPI_DATA[7:0]
F6
F6
F6
FLEXSPI_DQS
Internal Sample Clock
Figure 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half-cycle delayed DQS falling edge.
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3.9.9.1.3
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2
Table 58. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol
Parameter
Min.
Max.
Unit
Notes
—
33
MHz
—
—
[D:] Frequency of operation
F1
[D:] Setup time for incoming data
8.67
—
ns
1
F2
[D:] Hold time for incoming data
0
—
ns
—
1
The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.
Table 59. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1, 0x2
Symbol
Parameter
Min.
Max.
Unit
Notes
—
[D:] Frequency of operation
—
66
MHz
—
F1
[D:] Setup time for incoming data
1.5
—
ns
1
F2
[D:] Hold time for incoming data
1
—
ns
—
1
The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.
SCLK
F1
F2
F1
F2
SIO[0:7]
Internal Sample Clocks
Figure 39. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2
3.9.9.1.4
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
Table 60. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case 1)
Symbol
Parameter
Min.
Max.
Unit
—
[D:] Frequency of operation
—
166
MHz
TSCKD
[D:] Time from SCK to data valid
—
—
ns
TSCKDQS
[D:] Time from SCK to DQS
—
—
ns
TSCKD - TSCKDQS
[D:] Time delta between TSCKD and
TSCKDQS
-0.6
0.6
ns
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SCK
TSCKD
SIO[0:7]
TSCKDQS
DQS
Figure 40. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3
3.9.9.2
FlexSPI output/write timing
The following sections describe output signal timing for the FlexSPI controller including control signals
and data outputs.
3.9.9.2.1
SDR mode
Table 61. FlexSPI output timing in SDR mode
Symbol
Parameter
Min.
Max.
Unit
—
166
MHz
6.02
—
ns
—
[D:] Frequency of operation1
TCK
[D:] SCK clock period
TDSO
[D:] Output data setup time
2
—
ns
TDHO
[D:] Output data hold time
2
—
ns
TCSS
[D:] Chip select output setup time
3 x TCK - 1
—
ns
TCSH
[D:] Chip select output hold time
3 x TCK - 1
—
ns
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the
FlexSPI SDR input timing specifications.
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the
default values are shown above. See the i.MX 8M Nano Applications
Processor Reference Manual (IMX8MNRM) for more details.
SCK
TCSS
TCK
TCSH
CS
TDVO
TDVO
SIO[0:7]
TDHO
TDHO
Figure 41. FlexSPI output timing in SDR mode
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3.9.9.2.2
DDR mode
Table 62. FlexSPI output timing in DDR mode
Symbol
Parameter
Min.
Max.
Unit
—
166
MHz
6.02
—
ns
—
[D:] Frequency of operation1
TCK
[D:] SCK clock period
TDSO
[D:] Output data setup time
—
0.6
ns
TDHO
[D:] Output data hold time
0.6
—
ns
TCSS
[D:] Chip select output setup time
3 x TCK - 1.075
—
ns
TCSH
[D:] Chip select output hold time
3 x TCK - 1.075
—
ns
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the
FlexSPI SDR input timing specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the
default values are shown above. See the i.MX 8M Nano Applications
Processor Reference Manual (IMX8MNRM) for more details.
SCK
TCSS
TCK
TCSH
CS
TDVO
SIO[0:7]
TDHO
TDVO
TDHO
Figure 42. FlexSPI output timing in DDR mode
3.9.10
SAI/I2S switching specifications
This section provides the AC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes.
All timings are given for non inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 63. Master mode SAI timing (50 MHz)1
Num
Characteristic
Min
Max
Unit
S1
SAI_MCLK cycle time
20
—
ns
S2
SAI_MCLK pulse width high/low
40%
60%
MCLK period
S3
SAI_BCLK cycle time
20
—
ns
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Table 63. Master mode SAI timing (50 MHz)1 (continued)
Num
Characteristic
Min
Max
Unit
S4
SAI_BCLK pulse width high/low
40%
60%
BCLK period
S5
SAI_BCLK to SAI_FS output valid
—
2
ns
S6
SAI_BCLK to SAI_FS output invalid
0
—
ns
S7
SAI_BCLK to SAI_TXD valid
—
2
ns
S8
SAI_BCLK to SAI_TXD invalid
0
—
ns
S9
SAI_RXD/SAI_FS input setup before SAI_BCLK
2
—
ns
S10
SAI_RXD/SAI_FS input hold after SAI_BCLK
0
—
ns
1
To achieve 50 MHz for BCLK operation, clock must be set in feedback mode.
Table 64. Master mode SAI timing (25 MHz)
Num
Characteristic
Min
Max
Unit
S1
SAI_MCLK cycle time
40
—
ns
S2
SAI_MCLK pulse width high/low
40%
60%
MCLK period
S3
SAI_BCLK cycle time
40
—
ns
S4
SAI_BCLK pulse width high/low
40%
60%
BCLK period
S5
SAI_BCLK to SAI_FS output valid
—
2
ns
S6
SAI_BCLK to SAI_FS output invalid
0
—
ns
S7
SAI_BCLK to SAI_TXD valid
—
2
ns
S8
SAI_BCLK to SAI_TXD invalid
0
—
ns
S9
SAI_RXD/SAI_FS input setup before SAI_BCLK
12
—
ns
S10
SAI_RXD/SAI_FS input hold after SAI_BCLK
0
—
ns
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Figure 43. SAI timing—Master modes
Table 65. Slave mode SAI timing (50 MHz)1
Num
Characteristic
Min
Max
Unit
S11
SAI_BCLK cycle time (input)
20
—
ns
S12
SAI_BCLK pulse width high/low (input)
40%
60%
BCLK period
S13
SAI_FS input setup before SAI_BCLK
2
—
ns
S14
SAI_FA input hold after SAI_BCLK
2
—
ns
S17
SAI_RXD setup before SAI_BCLK
2
—
ns
S18
SAI_RXD hold after SAI_BCLK
2
—
ns
1
TX does not support 50 MHz operation in Slave mode.
Table 66. Slave mode SAI timing (25 MHz)
Num
Characteristic
Min
Max
Unit
S11
SAI_BCLK cycle time (input)
40
—
ns
S12
SAI_BCLK pulse width high/low (input)
40%
60%
BCLK period
S13
SAI_FS input setup before SAI_BCLK
12
—
ns
S14
SAI_FA input hold after SAI_BCLK
2
—
ns
S15
SAI_BCLK to SAI_TXD/SAI_FS output valid
—
7
ns
S16
SAI_BCLK to SAI_TXD/SAI_FS output invalid
0
—
ns
S17
SAI_RXD setup before SAI_BCLK
12
—
ns
S18
SAI_RXD hold after SAI_BCLK
2
—
ns
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Electrical characteristics
Figure 44. SAI Timing — Slave Modes
3.9.11
SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 67 and Figure 45 and Figure 46 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 67. SPDIF timing parameters
Timing Parameter Range
Parameter
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
SPDIF_OUT output (Load = 50 pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIF_OUT output (Load = 30 pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
Modulating Rx clock (SPDIF_SR_CLK) period
srckp
SPDIF_SR_CLK high period
1.5
13.6
18.0
ns
40.0
—
ns
srckph
16.0
—
ns
SPDIF_SR_CLK low period
srckpl
16.0
—
ns
Modulating Tx clock (SPDIF_ST_CLK) period
stclkp
40.0
—
ns
SPDIF_ST_CLK high period
stclkph
16.0
—
ns
SPDIF_ST_CLK low period
stclkpl
16.0
—
ns
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srckp
srckpl
SPDIF_SR_CLK
srckph
VM
VM
(Output)
Figure 45. SPDIF_SR_CLK timing diagram
stclkp
stclkpl
SPDIF_ST_CLK
stclkph
VM
VM
(Input)
Figure 46. SPDIF_ST_CLK timing diagram
3.9.12
3.9.12.1
UART I/O configuration and timing parameters
UART RS-232 I/O configuration in different modes
The i.MX 8M Nano UART interfaces can serve both as DTE or DCE device. This can be configured by
the DCEDTE control bit (default 0—DCE mode). Table 68 shows the UART I/O configuration based on
the enabled mode.
Table 68. UART I/O configuration vs. mode
DTE Mode
DCE Mode
Port
Direction
Description
Direction
Description
UARTx_RTS_B
Output
UARTx_RTS_B from DTE to DCE
Input
UARTx_RTS_B from DTE to DCE
UARTx_CTS_B
Input
UARTx_CTS_B from DCE to DTE
Output
UARTx_CTS_B from DCE to DTE
UARTx_TX_ DATA
Input
Serial data from DCE to DTE
Output
Serial data from DCE to DTE
UARTx_RX_DATA
Output
Serial data from DTE to DCE
Input
Serial data from DTE to DCE
3.9.12.2
UART RS-232 Serial mode timing
This section describes the electrical information of the UART module in the RS-232 mode.
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3.9.12.2.1
UART transmitter
Figure 47 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit
format. Table 69 lists the UART RS-232 Serial mode transmit timing characteristics.
UA1
Start
Bit
UARTx_TX_DATA
(output)
Possible
Parity
Bit
UA1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
Next
Start
Bit
UA1
UA1
Figure 47. UART RS-232 Serial mode transmit timing diagram
Table 69. RS-232 Serial mode transmit timing parameters
ID
Parameter
UA1
1
2
Transmit Bit Time
Symbol
Min
Max
Unit
tTbit
1/Fbaud_rate1 - Tref_clk2
1/Fbaud_rate + Tref_clk
—
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
3.9.12.2.2
UART receiver
Figure 48 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 70 lists
Serial mode receive timing characteristics.
UA2
UARTx_RX_DATA
(output)
Start
Bit
Possible
Parity
Bit
UA2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
UA2
Next
Start
Bit
UA2
Figure 48. UART RS-232 Serial mode receive timing diagram
Table 70. RS-232 Serial mode receive timing parameters
ID
Parameter
Symbol
Min
Max
Unit
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 - 1/(16 x
Fbaud_rate)
1/Fbaud_rate + 1/(16 x
Fbaud_rate)
—
1
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
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3.9.13
USB PHY parameters
This section describes the USB-OTG PHY parameters.
3.9.13.1
Pad/Package/Board connections
The USB1_VBUS pin cannot directly connect to the 5 V VBUS voltage on the USB2.0 link.
Each USB1_VBUS pin must be isolated by an external 30 K1% precision resistor.
The USB 2.0 PHY uses USB1_TXRTUNE and an external resistor to calibrate the USB1_DP/DN 45
source impedance. The external resistor value is 200 1% precision on USB1_TXRTUNE pad to ground.
3.9.13.2
USB PHY worst power consumption
Table 71 shows the USB 2.0 PHY worst power dissipation.
Table 71. USB 2.0 PHY worst power dissipation
VDD_USB_3P3
VDD_USB_1P8
Total Power
Mode
VDD_USB_0P8
HS TX
8.286
4.63
23.409
70.448
FS TX
6.767
12.52
5.968
63.22
LS TX
7.001
Suspend
0.752
0.164
0.106
1.465
Sleep
0.761
0.163
0.106
1.472
mA
13.58
mA
6.224
mA
67.779
mW
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Boot mode configuration
4
Boot mode configuration
This section provides information on Boot mode configuration pins allocation and boot devices interfaces
allocation.
4.1
Boot mode configuration pins
Table 72 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed Boot mode options configured by the Boot mode pins, see the “System Boot,
Fusemap, and eFuse” chapter in the i.MX 8M Nano Applications Processor Reference Manual
(IMX8MNRM).
Table 72. Fuses and associated pins used for boot
Interface
IP instance
Allocated pads during boot
BOOT_MODE0
Input
ccmsrcgpcmix.BOOT_MODE[0]
BOOT_MODE1
Input
ccmsrcgpcmix.BOOT_MODE[1]
BOOT_MODE2
Input
ccmsrcgpcmix.BOOT_MODE[2]
BOOT_MODE3
Input
ccmsrcgpcmix.BOOT_MODE[3]
4.2
Comment
Boot mode selection
Boot device interface allocation
Table 73 lists the interfaces that can be used by the boot process in accordance with the specific Boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 73. Interface allocation during boot
Interface
IP Instance
Allocated Pads During Boot
Comment
SPI
ECSPI-1
ECSPI1_SCLK, ECSPI1_MOSI, ECSPI1_MISO,
ECSPI1_SS0
The chip-select pin used depends
on the fuse “CS select (SPI only)“.
SPI
ECSPI-2
ECSPI2_SCLK, ECSPI2_MOSI, ECSPI2_MISO,
ECSPI2_SS0
The chip-select pin used depends
on the fuse “CS select (SPI only)“.
SPI
ECSPI-3
UART1_RXD, UART1_TXD, UART2_RXD,
UART2_TXD
The chip-select pin used depends
on the fuse “CS select (SPI only)“.
NAND Flash
GPMI
NAND_ALE, NAND_CE0_B, NAND_CLE,
8-bit, only CS0 is supported.
NAND_DATA00,NAND_DATA01,NAND_DATA02,
NAND_DATA03,NAND_DATA04,NAND_DATA05,
NAND_DATA06, NAND_DATA07, NAND_DQS,
NAND_RE_B, NAND_READY_B, NAND_WE_B,
NAND_WP_B
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Table 73. Interface allocation during boot (continued)
Interface
IP Instance
Allocated Pads During Boot
Comment
SD/MMC
USDHC-1
GPIO1_IO03, GPIO1_IO06, GPIO1_IO07,
SD1_RESET_B, SD1_CLK, SD1_CMD,
SD1_STROBE, SD1_DATA0, SD1_DATA1,
SD1_DATA2, SD1_DATA3, SD1_DATA4,
SD1_DATA5, SD1_DATA6, SD1_DATA7
SD/MMC
USDHC-2
GPIO1_IO04, GPIO1_IO08, GPIO1_IO07,
1 or 4-bit
SD2_RESET_B, SD2_WP, SD2_CLK, SD2_CMD,
SD2_DATA0, SD2_DATA1, SD2_DATA2,
SD2_DATA3
SD/MMC
USDHC-3
NAND_CE1_B, NAND_CE2_B, NAND_CE3_B,
1, 4, or 8-bit
NAND_CLE, NAND_DATA02, NAND_DATA03,
NAND_DATA04,NAND_DATA05,NAND_DATA06,
NAND_DATA07, NAND_RE_B, NAND_READY_B,
NAND_WE_B, NAND_WP_B
FlexSPI
FlexSPI
USB
USB_OTG PHY
1, 4, or 8-bit
NAND_ALE, NAND_CE0_B, NAND_CE1_B,
For FlexSPI flash
NAND_CE2_B, NAND_CE3_B, NAND_CLE,
NAND_DATA00,NAND_DATA01,NAND_DATA02,
NAND_DATA03,NAND_DATA04,NAND_DATA05,
NAND_DATA06, NAND_DATA07, NAND_DQS,
NAND_RE_B
Dedicated USB pins
—
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Package information and contact assignments
5
Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
5.1
5.1.1
14 x 14 mm package information
14 x 14 mm, 0.5 mm pitch, ball matrix
Figure 49 shows the top, bottom, and side views of the 14 × 14 mm FCBGA package.
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Figure 49. 14 X 14 MM BGA, case x package top, bottom, and side views
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Package information and contact assignments
5.1.2
14 x 14 mm supplies contact assignments and functional contact
assignments
Table 74 shows supplies contact assignments for the 14 x 14 mm package.
Table 74. i.MX 8M Nano 14 x 14 mm supplies contact assignments
Supply Rail Name
Ball(s) Position(s)
Remark
NVCC_CLK
M19
Supply for CLK interface
NVCC_DRAM
P7, K8, N8, R8, V8, K9, L9, M9, N9, R9, T9, U9, V9
Supply for DRAM interface
NVCC_ECSPI
H10
Supply for ECSPI interface
NVCC_ENET
W22
Supply for ENET interface
NVCC_GPIO1
W12
Supply for GPIO1 interface
NVCC_I2C
J11
Supply for I2C interface
NVCC_JTAG
L19
Supply for JTAG interface
NVCC_NAND
U19
Supply for NAND interface
NVCC_SAI2
V19
Supply for SAI interface
NVCC_SAI3
Y10
Supply for SAI interface
NVCC_SAI5
W17
Supply for SAI interface
NVCC_SD1
V20
Supply for SD interface
NVCC_SD2
V22
Supply for SD interface
NVCC_SNVS_1P8
J22
Supply for SNVS interface
NVCC_UART
J12
Supply for UART interface
PVCC0_1P8
AB13
Digital IO pre-drive
PVCC1_1P8
T19
Digital IO pre-drive
PVCC2_1P8
J13
Digital IO pre-drive
VDD_24M_XTAL_1P8
N19
Supply for XTAL
VDD_ANA_0P8
L17, N17
Supply for Analog logic
VDD_ANA0_1P8
AA14, Y15
Supply for Analog logic
VDD_ANA1_1P8
P19, N20
Supply for Analog logic
VDD_ARM
R13, T13, U13, V13, W13, T14, W14, R15, T15, U15, V15,
W15, V16, W16
Supply for ARM
VDD_ARM_PLL_0P8
P16
Supply for ARM PLL
VDD_ARM_PLL_1P8
R19
Supply for ARM PLL
VDD_DRAM
J10, L10, N10, R10, U10, W10
Supply for DRAM module
VDD_DRAM_PLL_0P8
P9
Supply for DRAM PLL
VDD_DRAM_PLL_1P8
P5
Supply for DRAM PLL
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Table 74. i.MX 8M Nano 14 x 14 mm supplies contact assignments (continued)
VDD_GPU
R11, U11, W11, P12, V12
Supply for GPU
VDD_MIPI_0P8
J14
Supply for MIPI PHY
VDD_MIPI_1P2
J15
Supply for MIPI PHY
VDD_MIPI_1P8
H13
Supply for MIPI PHY
VDD_SNVS_0P8
K22
Supply for SNVS logic
VDD_SOC
N13, K15, L15, M15, N15, K16, R17, U17, L18, N18, R18,
U18
Supply for SOC logic
VDD_USB_0P8
J17
Supply for USB PHY
VDD_USB_1P8
H15
Supply for USB PHY
VDD_USB_3P3
K19
Supply for USB PHY
VSS
A1, AG1, C2, H2, Y2, AE2, B3, E3, F3, J3, K3, N3, P3, R3, —
V3, W3, AB3, AC3, AF3, C5, AE5, C6, AE6, G7, J7, K7, N7,
R7, V7, W7, AA7, C9, G9, AA9, AE9, C10, G10, AA10, AE10,
L12, M12, N12, R12, T12, U12, C13, G13, P13, Y13, AA13,
AE13, C14, AE14, C15, G15, P15, AA15, AE15, L16, M16,
N16, R16, T16, U16, C18, G18, H18, Y18, AA18, AE18, C19,
G19, AA19, AE19, K20, R20, G21, J21, K21, N21, P21, R21,
V21, W21, AA21, C22, AE22, C23, AE23, E25, F25, J25,
K25, N25, P25, R25, V25, W25, AB25, AC25, B26, A27,
AG27
Table 75 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package.
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
24M_XTALI
B27
NVCC_CLK
ANALOG
—
—
Input
24M_XTALO
C26
NVCC_CLK
ANALOG
—
—
Output
BOOT_MODE0
G26
NVCC_JTAG
GPIO
ALT0
ccmsrcgpcmix.BOOT_MODE[0] Input with PD
BOOT_MODE1
G27
NVCC_JTAG
GPIO
ALT0
ccmsrcgpcmix.BOOT_MODE[1] Input with PD
BOOT_MODE2
C27
NVCC_JTAG
GPIO
ALT0
ccmsrcgpcmix.BOOT_MODE[2] Input with PD
BOOT_MODE3
D26
NVCC_JTAG
GPIO
ALT0
ccmsrcgpcmix.BOOT_MODE[3] Input with PD
CLKIN1
H27
NVCC_CLK
GPIO
—
—
Input without
PU/PD
CLKIN2
J27
NVCC_CLK
GPIO
—
—
Input without
PU/PD
CLKOUT1
H26
NVCC_CLK
GPIO
—
—
Output low
without
PU/PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
79
Package information and contact assignments
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
CLKOUT2
J26
NVCC_CLK
GPIO
—
—
Output low
without
PU/PD
DRAM_AC00
F4
NVCC_DRAM
DDR
—
—
Output low
DRAM_AC01
F5
NVCC_DRAM
DDR
—
—
Output low
DRAM_AC02
K4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC03
J4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC04
L2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC05
L1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC06
F6
NVCC_DRAM
DDR
—
—
Input
DRAM_AC07
J5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC08
J6
NVCC_DRAM
DDR
—
—
Input
DRAM_AC09
K6
NVCC_DRAM
DDR
—
—
Input
DRAM_AC10
E4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC11
D5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC12
N4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC13
N5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC14
K5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC15
N6
NVCC_DRAM
DDR
—
—
Input
DRAM_AC16
M1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC17
M2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC19
N2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC20
AB4
NVCC_DRAM
DDR
—
—
Output low
DRAM_AC21
AB5
NVCC_DRAM
DDR
—
—
Output low
DRAM_AC22
W4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC23
V4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC24
U2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC25
U1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC26
N1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC27
R6
NVCC_DRAM
DDR
—
—
Input
DRAM_AC28
W6
NVCC_DRAM
DDR
—
—
Input
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
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NXP Semiconductors
Package information and contact assignments
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
DRAM_AC29
V6
NVCC_DRAM
DDR
—
—
Input
DRAM_AC30
AC4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC31
AD5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC32
R4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC33
R5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC34
T1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC35
T2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC36
V5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC37
W5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC38
AB6
NVCC_DRAM
DDR
—
—
Input
DRAM_ALERT_N
R2
NVCC_DRAM
DDR
—
—
Input
DRAM_DM0
A4
NVCC_DRAM
DDR
—
—
Input
DRAM_DM1
F1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ00
A5
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ01
B5
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ02
D2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ03
D1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ04
C1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ05
B1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ06
A3
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ07
B4
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ08
F2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ09
G2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ10
J1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ11
J2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ12
K2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ13
K1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ14
E1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ15
E2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQS0_N
B2
NVCC_DRAM
—
—
—
Input
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
81
Package information and contact assignments
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
DRAM_DQS0_P
A2
NVCC_DRAM
DDRCLK
—
—
Input
DRAM_DQS1_N
H1
NVCC_DRAM
—
—
—
Input
DRAM_DQS1_P
G1
NVCC_DRAM
DDRCLK
—
—
Input
DRAM_RESET_N
R1
NVCC_DRAM
DDR
—
—
Output low
DRAM_VREF
P1
NVCC_DRAM
DDR
—
—
—
DRAM_ZN
P2
NVCC_DRAM
DDR
—
—
—
ECSPI1_MISO
A7
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[8]
Input with PD
ECSPI1_MOSI
B7
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[7]
Input with PD
ECSPI1_SCLK
D6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[6]
Input with PD
ECSPI1_SS0
B6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[9]
Input with PD
ECSPI2_MISO
A8
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[12]
Input with PD
ECSPI2_MOSI
B8
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[11]
Input with PD
ECSPI2_SCLK
E6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[10]
Input with PD
ECSPI2_SS0
A6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[13]
Input with PD
ENET_MDC
AC27
NVCC_ENET
GPIO
ALT5
GPIO1.IO[16]
Input with PD
ENET_MDIO
AB27
NVCC_ENET
GPIO
ALT5
GPIO1.IO[17]
Input with PD
ENET_RD0
AE27
NVCC_ENET
GPIO
ALT5
GPIO1.IO[26]
Input with PD
ENET_RD1
AD27
NVCC_ENET
GPIO
ALT5
GPIO1.IO[27]
Input with PD
ENET_RD2
AD26
NVCC_ENET
GPIO
ALT5
GPIO1.IO[28]
Input with PD
ENET_RD3
AC26
NVCC_ENET
GPIO
ALT5
GPIO1.IO[29]
Input with PD
ENET_RXC
AE26
NVCC_ENET
GPIO
ALT5
GPIO1.IO[25]
Input with PD
ENET_RX_CTL
AF27
NVCC_ENET
GPIO
ALT5
GPIO1.IO[24]
Input with PD
ENET_TD0
AG26
NVCC_ENET
GPIO
ALT5
GPIO1.IO[21]
Input with PD
ENET_TD1
AF26
NVCC_ENET
GPIO
ALT5
GPIO1.IO[20]
Input with PD
ENET_TD2
AG25
NVCC_ENET
GPIO
ALT5
GPIO1.IO[19]
Input with PD
ENET_TD3
AF25
NVCC_ENET
GPIO
ALT5
GPIO1.IO[18]
Input with PD
ENET_TXC
AG24
NVCC_ENET
GPIO
ALT5
GPIO1.IO[23]
Input with PD
ENET_TX_CTL
AF24
NVCC_ENET
GPIO
ALT5
GPIO1.IO[22]
Input with PD
GPIO1_IO00
AG14
NVCC_GPIO1
GPIO
ALT6
GPIO1.IO[0]
Input with PD
GPIO1_IO01
AF14
NVCC_GPIO1
GPIO
ALT6
GPIO1.IO[1]
1
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
82
NXP Semiconductors
Package information and contact assignments
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
GPIO1_IO02
AG13
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[2]
Input with PU
GPIO1_IO03
AF13
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[3]
Input with PD
GPIO1_IO04
AG12
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[4]
Input with PD
GPIO1_IO05
AF12
NVCC_GPIO1
GPIO
ALT6
GPIO1.IO[5]
1
GPIO1_IO06
AG11
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[6]
Input with PD
GPIO1_IO07
AF11
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[7]
Input with PD
GPIO1_IO08
AG10
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[8]
Input with PD
GPIO1_IO09
AF10
NVCC_GPIO1
GPIO
ALT1
GPIO1.IO[9]
Input with PD
GPIO1_IO10
AD10
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[10]
Input with PD
GPIO1_IO11
AC10
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[11]
Input with PD
GPIO1_IO12
AB10
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[12]
Input with PD
GPIO1_IO13
AD9
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[13]
Input with PD
GPIO1_IO14
AC9
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[14]
Input with PD
GPIO1_IO15
AB9
NVCC_GPIO1
GPIO
ALT0
GPIO1.IO[15]
Input with PD
I2C1_SCL
E9
NVCC_I2C
GPIO
ALT5
GPIO5.IO[14]
Input with PD
I2C1_SDA
F9
NVCC_I2C
GPIO
ALT5
GPIO5.IO[15]
Input with PD
I2C2_SCL
D10
NVCC_I2C
GPIO
ALT5
GPIO5.IO[16]
Input with PD
I2C2_SDA
D9
NVCC_I2C
GPIO
ALT5
GPIO5.IO[17]
Input with PD
I2C3_SCL
E10
NVCC_I2C
GPIO
ALT5
GPIO5.IO[18]
Input with PD
I2C3_SDA
F10
NVCC_I2C
GPIO
ALT5
GPIO5.IO[19]
Input with PD
I2C4_SCL
D13
NVCC_I2C
GPIO
ALT5
GPIO5.IO[20]
Input with PD
I2C4_SDA
E13
NVCC_I2C
GPIO
ALT5
GPIO5.IO[21]
Input with PD
JTAG_MOD
D27
NVCC_JTAG
GPIO
ALT0
cjtag_wrapper.MOD
Input with PD
JTAG_TCK
F26
NVCC_JTAG
GPIO
ALT0
cjtag_wrapper.TCK
Input with PU
JTAG_TDI
E27
NVCC_JTAG
GPIO
ALT0
cjtag_wrapper.TDI
Input with PU
JTAG_TDO
E26
NVCC_JTAG
GPIO
ALT0
cjtag_wrapper.TDO
Input with PU
JTAG_TMS2
F27
NVCC_JTAG
GPIO
ALT0
cjtag_wrapper.TMS
Input with PU
MIPI_CSI_CLK_N
A16
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_CSI_CLK_P
B16
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_CSI_D0_N
A14
VDD_MIPI_1P8
PHY
—
—
Input
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
83
Package information and contact assignments
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
MIPI_CSI_D0_P
B14
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_CSI_D1_N
A15
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_CSI_D1_P
B15
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_CSI_D2_N
A17
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_CSI_D2_P
B17
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_CSI_D3_N
A18
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_CSI_D3_P
B18
VDD_MIPI_1P8
PHY
—
—
Input
MIPI_DSI_CLK_N
A11
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_CLK_P
B11
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_D0_N
A9
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_D0_P
B9
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_D1_N
A10
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_D1_P
B10
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_D2_N
A12
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_D2_P
B12
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_D3_N
A13
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_DSI_D3_P
B13
VDD_MIPI_1P8
PHY
—
—
Output low
MIPI_VREG_CAP
D15
0.35 - 0.45 V
PHY
—
—
Output
NAND_ALE
N22
NVCC_NAND
GPIO
ALT5
GPIO3.IO[0]
Input with PD
NAND_CE0_B
N24
NVCC_NAND
GPIO
ALT5
GPIO3.IO[1]
Input with PD
NAND_CE1_B
P27
NVCC_NAND
GPIO
ALT5
GPIO3.IO[2]
Input with PD
NAND_CE2_B
M27
NVCC_NAND
GPIO
ALT5
GPIO3.IO[3]
Input with PD
NAND_CE3_B
L27
NVCC_NAND
GPIO
ALT5
GPIO3.IO[4]
Input with PD
NAND_CLE
K27
NVCC_NAND
GPIO
ALT5
GPIO3.IO[5]
Input with PD
NAND_DATA00
P23
NVCC_NAND
GPIO
ALT5
GPIO3.IO[6]
Input with PD
NAND_DATA01
K24
NVCC_NAND
GPIO
ALT5
GPIO3.IO[7]
Input with PD
NAND_DATA02
K23
NVCC_NAND
GPIO
ALT5
GPIO3.IO[8]
Input with PD
NAND_DATA03
N23
NVCC_NAND
GPIO
ALT5
GPIO3.IO[9]
Input with PD
NAND_DATA04
M26
NVCC_NAND
GPIO
ALT5
GPIO3.IO[10]
Input with PD
NAND_DATA05
L26
NVCC_NAND
GPIO
ALT5
GPIO3.IO[11]
Input with PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
84
NXP Semiconductors
Package information and contact assignments
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
NAND_DATA06
K26
NVCC_NAND
GPIO
ALT5
GPIO3.IO[12]
Input with PD
NAND_DATA07
N26
NVCC_NAND
GPIO
ALT5
GPIO3.IO[13]
Input with PD
NAND_DQS
R22
NVCC_NAND
GPIO
ALT5
GPIO3.IO[14]
Input with PD
NAND_RE_B
N27
NVCC_NAND
GPIO
ALT5
GPIO3.IO[15]
Input with PD
NAND_READY_B
P26
NVCC_NAND
GPIO
ALT5
GPIO3.IO[16]
Input with PD
NAND_WE_B
R26
NVCC_NAND
GPIO
ALT5
GPIO3.IO[17]
Input with PD
NAND_WP_B
R27
NVCC_NAND
GPIO
ALT5
GPIO3.IO[18]
Input with PD
ONOFF
A25
NVCC_SNVS_1P8
GPIO
ALT0
snvsmix.ONOFF
Input without
PU/PD
PMIC_ON_REQ
A24
NVCC_SNVS_1P8
GPIO
ALT0
snvsmix.PMIC_ON_REQ
Open-drain
output high
with PU
PMIC_STBY_REQ
E24
NVCC_SNVS_1P8
GPIO
ALT0
ccmsrcgpcmix.PMIC_STBY_RE
Q
Output low
with PD
POR_B
B24
NVCC_SNVS_1P8
GPIO
ALT0
snvsmix.POR_B
Input without
PU/PD
RTC_XTALI
A26
NVCC_SNVS_1P8
ANALOG
ALT0
snvsmix.RTC
Input
RTC_XTALO
B25
NVCC_SNVS_1P8
ANALOG
—
—
Output,
inverted of
RTC_XTALI
RTC_RESET_B
F24
NVCC_SNVS_1P8
GPIO
ALT0
snvsmix.RTC_POR_B
Input without
PU/PD
SAI2_MCLK
AD19
NVCC_SAI2
GPIO
ALT5
GPIO4.IO[27]
Input with PD
SAI2_RXC
AB22
NVCC_SAI2
GPIO
ALT5
GPIO4.IO[22]
Input with PD
SAI2_RXD0
AC24
NVCC_SAI2
GPIO
ALT5
GPIO4.IO[23]
Input with PD
SAI2_RXFS
AC19
NVCC_SAI2
GPIO
ALT5
GPIO4.IO[21]
Input with PD
SAI2_TXC
AD22
NVCC_SAI2
GPIO
ALT5
GPIO4.IO[25]
Input with PD
SAI2_TXD0
AC22
NVCC_SAI2
GPIO
ALT5
GPIO4.IO[26]
Input with PD
SAI2_TXFS
AD23
NVCC_SAI2
GPIO
ALT5
GPIO4.IO[24]
Input with PD
SAI3_MCLK
AD6
NVCC_SAI3
GPIO
ALT5
GPIO5.IO[2]
Input with PD
SAI3_RXC
AG7
NVCC_SAI3
GPIO
ALT5
GPIO4.IO[29]
Input with PD
SAI3_RXD
AF7
NVCC_SAI3
GPIO
ALT5
GPIO4.IO[30]
Input with PD
SAI3_RXFS
AG8
NVCC_SAI3
GPIO
ALT5
GPIO4.IO[28]
Input with PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
85
Package information and contact assignments
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
SAI3_TXC
AG6
NVCC_SAI3
GPIO
ALT5
GPIO5.IO[0]
Input with PD
SAI3_TXD
AF6
NVCC_SAI3
GPIO
ALT5
GPIO5.IO[1]
Input with PD
SAI3_TXFS
AC6
NVCC_SAI3
GPIO
ALT5
GPIO4.IO[31]
Input with PD
SAI5_MCLK
AD15
NVCC_SAI5
GPIO
ALT5
GPIO3.IO[25]
3
SAI5_RXC
AC15
NVCC_SAI5
GPIO
ALT5
GPIO3.IO[20]
Input with PD
SAI5_RXD0
AD18
NVCC_SAI5
GPIO
ALT5
GPIO3.IO[21]
Input with PD
SAI5_RXD1
AC14
NVCC_SAI5
GPIO
ALT5
GPIO3.IO[22]
Input with PD
SAI5_RXD2
AD13
NVCC_SAI5
GPIO
ALT5
GPIO3.IO[23]
Input with PD
SAI5_RXD3
AC13
NVCC_SAI5
GPIO
ALT5
GPIO3.IO[24]
Input with PD
SAI5_RXFS
AB15
NVCC_SAI5
GPIO
ALT5
GPIO3.IO[19]
Input with PD
SD1_CLK
V26
NVCC_SD1
GPIO
ALT5
GPIO2.IO[0]
Input with PD
SD1_CMD
V27
NVCC_SD1
GPIO
ALT5
GPIO2.IO[1]
Input with PD
SD1_DATA0
Y27
NVCC_SD1
GPIO
ALT5
GPIO2.IO[2]
Input with PD
SD1_DATA1
Y26
NVCC_SD1
GPIO
ALT5
GPIO2.IO[3]
Input with PD
SD1_DATA2
T27
NVCC_SD1
GPIO
ALT5
GPIO2.IO[4]
Input with PD
SD1_DATA3
T26
NVCC_SD1
GPIO
ALT5
GPIO2.IO[5]
Input with PD
SD1_DATA4
U27
NVCC_SD1
GPIO
ALT5
GPIO2.IO[6]
Input with PD
SD1_DATA5
U26
NVCC_SD1
GPIO
ALT5
GPIO2.IO[7]
Input with PD
SD1_DATA6
W27
NVCC_SD1
GPIO
ALT5
GPIO2.IO[8]
Input with PD
SD1_DATA7
W26
NVCC_SD1
GPIO
ALT5
GPIO2.IO[9]
Input with PD
SD1_RESET_B
R23
NVCC_SD1
GPIO
ALT5
GPIO2.IO[10]
Input with PD
SD1_STROBE
R24
NVCC_SD1
GPIO
ALT5
GPIO2.IO[11]
Input with PD
SD2_CD_B
AA26
NVCC_SD2
GPIO
ALT5
GPIO2.IO[12]
Input with PD
SD2_CLK
W23
NVCC_SD2
GPIO
ALT5
GPIO2.IO[13]
Input with PD
SD2_CMD
W24
NVCC_SD2
GPIO
ALT5
GPIO2.IO[14]
Input with PD
SD2_DATA0
AB23
NVCC_SD2
GPIO
ALT5
GPIO2.IO[15]
Input with PD
SD2_DATA1
AB24
NVCC_SD2
GPIO
ALT5
GPIO2.IO[16]
Input with PD
SD2_DATA2
V24
NVCC_SD2
GPIO
ALT5
GPIO2.IO[17]
Input with PD
SD2_DATA3
V23
NVCC_SD2
GPIO
ALT5
GPIO2.IO[18]
Input with PD
SD2_RESET_B
AB26
NVCC_SD2
GPIO
ALT5
GPIO2.IO[19]
Input with PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
86
NXP Semiconductors
Package information and contact assignments
Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
SD2_WP
AA27
NVCC_SD2
GPIO
ALT5
GPIO2.IO[20]
Input with PD
SPDIF_EXT_CLK
AF8
NVCC_SAI3
GPIO
ALT5
GPIO5.IO[5]
Input with PD
SPDIF_RX
AG9
NVCC_SAI3
GPIO
ALT5
GPIO5.IO[4]
Input with PD
SPDIF_TX
AF9
NVCC_SAI3
GPIO
ALT5
GPIO5.IO[3]
Input with PD
TSENSOR_TEST_
OUT
J23
VDD_ANA1_1P8
ANALOG
—
—
Output low
TSENSOR_RES_E
XT
J24
VDD_ANA1_1P8
ANALOG
—
—
—
UART1_RXD
E14
NVCC_UART
GPIO
ALT5
GPIO5.IO[22]
Input with PD
UART1_TXD
F13
NVCC_UART
GPIO
ALT5
GPIO5.IO[23]
Input with PD
UART2_RXD
F15
NVCC_UART
GPIO
ALT5
GPIO5.IO[24]
Input with PD
UART2_TXD
E15
NVCC_UART
GPIO
ALT5
GPIO5.IO[25]
Input with PD
UART3_RXD
E18
NVCC_UART
GPIO
ALT5
GPIO5.IO[26]
Input with PD
UART3_TXD
D18
NVCC_UART
GPIO
ALT5
GPIO5.IO[27]
Input with PD
UART4_RXD
F19
NVCC_UART
GPIO
ALT5
GPIO5.IO[28]
Input with PD
UART4_TXD
F18
NVCC_UART
GPIO
ALT5
GPIO5.IO[29]
Input with PD
USB1_DN
A22
VDD_USB_3P3
PHY
—
—
Input
USB1_DP
B22
VDD_USB_3P3
PHY
—
—
Input
USB1_ID
D22
VDD_USB_1P8
PHY
—
—
Input
USB1_TXRTUNE
E19
VDD_USB_1P8
PHY
—
—
—
USB1_VBUS
F22
VDD_USB_3P3
PHY
—
—
—
1
During reset: output high without PU/PD; After reset: input with PU
Mandatory requirement: JTAG_TMS pin must be connected with a 50 ohm serial resistor near the component.
3 During reset: input without PU/PD; After reset: input with PD
2
5.1.3
i.MX 8M Nano 14 x 14 mm 0.5 mm pitch ball map
Table 76 shows the i.MX 8M Nano 14 x 14 mm 0.5 mm pitch ball map.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
87
88
VSS
DRAM_AC10
VSS
DRAM_AC00
UART4_TXD
UART4_RXD
VSS
VSS
USB1_TXRTUNE
UART3_RXD
UART2_TXD
UART1_RXD
I2C4_SDA
JTAG_TCK
JTAG_TMS
BOOT_MODE0
BOOT_MODE1
VSS
JTAG_TDI
JTAG_TDO
VSS
RTC_RESET_B PMIC_STBY_REQ
USB1_VBUS
UART2_RXD
VSS
VSS
UART1_TXD
VSS
JTAG_MOD
BOOT_MODE3
USB1_ID
UART3_TXD
MIPI_VREG_CAP
I2C4_SCL
I2C2_SCL
BOOT_MODE2
24M_XTALO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MIPI_DSI_D1_N
MIPI_DSI_D0_N
MIPI_CSI_D1_N
MIPI_CSI_D0_N
MIPI_DSI_D3_N
MIPI_DSI_D2_N
24M_XTALI
VSS
RTC_XTALO
POR_B
USB1_DP
MIPI_CSI_D3_P
MIPI_CSI_D2_P
VSS
RTC_XTALI
ONOFF
PMIC_ON_REQ
USB1_DN
MIPI_CSI_D3_N
MIPI_CSI_D2_N
MIPI_CSI_CLK_P MIPI_CSI_CLK_N
MIPI_CSI_D1_P
MIPI_CSI_D0_P
MIPI_DSI_D3_P
MIPI_DSI_D2_P
MIPI_DSI_CLK_P MIPI_DSI_CLK_N
MIPI_DSI_D1_P
MIPI_DSI_D0_P
9
I2C3_SCL
VSS
8
I2C3_SDA
I2C2_SDA
ECSPI2_MISO
ECSPI2_MOSI
7
VSS
I2C1_SCL
ECSPI1_MISO
ECSPI2_SS0
ECSPI1_MOSI
ECSPI1_SS0
6
I2C1_SDA
VSS
DRAM_DQ00
5
VSS
ECSPI1_SCLK
ECSPI2_SCLK
DRAM_DQ01
DRAM_DM0
DRAM_DQ06
DRAM_DQS0_P
VSS
A
4
DRAM_AC06
VSS
DRAM_DQ07
VSS
DRAM_DQS0_N
DRAM_DQ05
B
3
DRAM_AC11
VSS
DRAM_DQ04
C
2
DRAM_AC01
DRAM_DQ02
DRAM_DQ03
D
1
VSS
DRAM_DQ15
DRAM_DQ08
DRAM_DQ09
DRAM_DQ14
DRAM_DM1
DRAM_DQS1_P
E
F
G
Package information and contact assignments
Table 76. 14 x 14 mm, 0.5 mm pitch ball map
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
DRAM_AC02
DRAM_AC12
NXP Semiconductors
NAND_DATA07
NAND_RE_B
NAND_READY_B
NAND_CE1_B
NAND_CE2_B
NAND_CE3_B
NAND_CLE
NAND_DATA06
VSS
NAND_DATA01
NAND_CE0_B
VSS
NAND_DATA02
NAND_DATA03
VDD_SNVS_0P8
VSS
VDD_USB_3P3
NAND_ALE
NAND_DATA04 NAND_DATA05
NVCC_JTAG
VDD_SOC
VSS
VSS
NAND_DATA00
VSS
VDD_SOC
NVCC_DRAM
VSS
VDD_ANA1_1P8
VDD_24M_XTAL_1P8
NVCC_CLK
VSS
VDD_SOC
VDD_SOC
VSS
VDD_ARM_PLL_0P8
VDD_SOC
VDD_SOC
VDD_SOC
VSS
VSS
VDD_ANA_0P8
VDD_SOC
VSS
VSS
VDD_DRAM
VDD_ANA_0P8
VSS
VDD_DRAM
VDD_GPU
VSS
NVCC_DRAM
CLKIN2
CLKOUT2
VSS
TSENSOR_RES_EXT
TSENSOR_TEST_OUT
NVCC_SNVS_1P8
VSS
VDD_USB_0P8
VDD_MIPI_1P2
VDD_MIPI_0P8
PVCC2_1P8
NVCC_UART
NVCC_I2C
VDD_DRAM
CLKIN1
CLKOUT1
VSS
VDD_USB_1P8
VDD_MIPI_1P8
NVCC_ECSPI
9
VDD_ANA1_1P8
NVCC_DRAM
8
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
VSS
7
VDD_DRAM_PLL_0P8
VSS
6
VSS
DRAM_AC08
5
NVCC_DRAM
DRAM_AC09
DRAM_AC15
DRAM_AC07
VSS
4
DRAM_AC14
DRAM_AC03
VSS
DRAM_DQ11
DRAM_DQS1_N
3
DRAM_AC13
DRAM_DQ12
DRAM_DQ10
H
2
VDD_DRAM_PLL_1P8
VSS
VSS
VSS
DRAM_AC04
DRAM_DQ13
J
1
DRAM_AC17
DRAM_AC05
DRAM_AC19
DRAM_AC16
DRAM_ZN
K
DRAM_AC26
L
DRAM_VREF
M
N
P
Package information and contact assignments
Table 76. 14 x 14 mm, 0.5 mm pitch ball map (continued)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
89
90
SD1_DATA7
SD2_CD_B
SD2_WP
SD2_RESET_B
ENET_MDIO
SD1_DATA6
VSS
VSS
SD1_DATA0
SD2_CMD
SD2_DATA1
NVCC_ENET
VSS
SD1_CMD
SD1_CLK
VSS
SD2_DATA2
SD2_DATA3
NVCC_SD2
VSS
NVCC_SD1
NVCC_SAI2
VDD_ARM
VDD_ARM
NVCC_SAI5
VDD_ARM
VDD_ARM
VDD_ARM
VDD_ARM
VDD_ARM
SD1_DATA4
SD1_DATA5
NVCC_NAND
VDD_SOC
VDD_SOC
VSS
VDD_ARM
VDD_ARM
VSS
NVCC_GPIO1
SD2_CLK
VSS
SD1_DATA1
VSS
VSS
VSS
VDD_ANA0_1P8
VSS
VSS
VDD_GPU
VDD_GPU
VDD_GPU
VDD_DRAM
VDD_DRAM
SD2_DATA0
SAI2_RXC
SAI5_RXFS
VSS
PVCC0_1P8
NVCC_SAI3
SD1_DATA2
SD1_DATA3
PVCC1_1P8
VSS
VDD-ARM
VDD_ARM
VDD_ARM
VSS
NAND_WP_B
NAND_WE_B
VSS
SD1_STROBE
SD1_RESET_B
NAND_DQS
VSS
VSS
VDD_ARM_PLL_1P8
VDD_SOC
VDD_SOC
VSS
VDD_ARM
VDD_ARM
VSS
VDD_GPU
VDD_DRAM
9
VDD_ANA0_1P8
VSS
GPIO1_IO12
NVCC_DRAM
8
NVCC_DRAM NVCC_DRAM NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
7
VSS
VSS
DRAM_AC27
6
VSS
DRAM_AC29
DRAM_AC33
DRAM_AC32
VSS
DRAM_ALERT_N
DRAM_RESET_N
R
5
GPIO1_IO15
DRAM_AC28
DRAM_AC38
DRAM_AC35
DRAM_AC34
DRAM_AC25
DRAM_AC24
T
U
4
DRAM_AC36
DRAM_AC23
VSS
V
3
VSS
DRAM_AC37
DRAM_AC21
VSS
DRAM_AC22
W
DRAM_AC20
VSS
Y
2
VSS
AA
1
VSS
AB
Package information and contact assignments
Table 76. 14 x 14 mm, 0.5 mm pitch ball map (continued)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
NXP Semiconductors
GPIO1_IO07
GPIO1_IO05
GPIO1_IO03
GPIO1_IO01
ENET_TX_CTL
ENET_TD3
ENET_TD1
ENET_RX_CTL
GPIO1_IO06
GPIO1_IO04
GPIO1_IO02
GPIO1_IO00
ENET_TXC
ENET_TD2
ENET_TD0
VSS
SAI2_TXC
SAI2_TXFS
VSS
VSS
ENET_RD0
ENET_RD1
ENET_RD2
SAI2_MCLK
VSS
ENET_RXC
SAI5_RXD0
VSS
ENET_MDC
ENET_RD3
VSS
SAI2_RXD0
SAI2_TXD0
SAI2_RXFS
SAI5_RXC
SAI5_MCLK
VSS
SAI5_RXD3
SAI5_RXD1
SAI5_RXD2
VSS
VSS
GPIO1_IO10 GPIO1_IO11
GPIO1_IO09
VSS
9
GPIO1_IO08
GPIO1_IO13 GPIO1_IO14
8
SPDIF_TX
7
SPDIF_RX
VSS
6
SAI3_RXFS SPDIF_EXT_CLK
SAI3_RXD
5
SAI3_RXC
DRAM_AC30
SAI3_TXFS
VSS
AC
4
SAI3_MCLK
DRAM_AC31
AD
3
VSS
VSS
VSS
AE
2
SAI3_TXD
VSS
AF
1
SAI3_TXC
VSS
AG
Package information and contact assignments
Table 76. 14 x 14 mm, 0.5 mm pitch ball map (continued)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
91
Package information and contact assignments
5.2
5.2.1
11 x 11 mm package information
11 x 11 mm, 0.5 mm pitch, ball matrix
Figure 50 shows the top, bottom, and side views of the 11 × 11 mm FCBGA package.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
92
NXP Semiconductors
Package information and contact assignments
Figure 50. 11 X 11 MM BGA, case x package top, bottom, and side views
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
93
Package information and contact assignments
5.2.2
11 x 11 mm supplies contact assignments and functional contact
assignments
Table 77 shows supplies contact assignments for the 11 x 11 mm package.
Table 77. i.MX 8M Nano 11 x 11 mm supplies contact assignments
Supply Rail Name
Ball(s) Position(s)
Remark
NVCC_CLK_JTAG_PVCC_1
P8
L15
Supply for CLK, JTAG interface and Digital I/O
pre-drive
NVCC_DRAM
G6, J6, J7, L6, N6, N7, R6
Supply for DRAM interface
NVCC_ECSPI
G8
Supply for ECSPI interface
NVCC_ENET_GPIO_SAI2
R12
Supply for ENET, GPIO1, and SAI2 interface
NVCC_I2C_UART
G10
Supply for I2C and UART interface
NVCC_SAI3_SAI5
R10
Supply for SAI3 and SAI5 interface
NVCC_SD1_NAND
N15
Supply for SD1 and NAND interface
NVCC_SD2
R16
Supply for SD interface
NVCC_SNVS_1P8
G14
Supply for SNVS interface
VDD_ANA1_XTAL_MIPI_US
B_1P8
G12
Supply for XTAL, Analog logic, MIPI, and USB
1.8 V
VDD_ANA0_ARM_PLL_1P8
R14
Supply for Analog logic and ARM PLL 1.8 V
VDD_DRAM_PLL_1P8
L7
Supply for DRAM PLL
VDD_MIPI_1P2
F12
Supply for MIPI PHY
VDD_SNVS_0P8
J15
Supply for SNVS logic
VDD_SOC
J9, J10, J11, J12, J13, K10, K12, L9, L10, L12, Supply for SOC logic
L13, M10, M12, N9, N10, N11, N12, N13
VDD_USB_3P3
F14
VSS
A1, AA1, E3, G3, J3, L3, N3, R3, U3, C4, W4, —
C6, W6, C8, H8, J8, L8, N8, P8, W8, C10,
H10, P10, W10, K11, M11, C12, H12, P12,
W12, C14, H14, J14, L14, N14, P14, W14,
C16, W16, C18, W18, E19, G19, J19, L19,
N19, R19, U19, B20, A21, AA21
Supply for USB PHY
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
94
NXP Semiconductors
Package information and contact assignments
Table 78 shows an alpha-sorted list of functional contact assignments for the 11 x 11 mm package.
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
24M_XTALI
B21
NVCC_CLK_JTAG
_PVCC_1P8
ANALOG
—
—
Input
24M_XTALO
C20
NVCC_CLK_JTAG
_PVCC_1P8
ANALOG
—
—
Output
BOOT_MODE0
G16
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
ccmsrcgpcmix.BOOT_MODE[0] Input with PD
BOOT_MODE1
G18
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
ccmsrcgpcmix.BOOT_MODE[1] Input with PD
BOOT_MODE2
F16
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
ccmsrcgpcmix.BOOT_MODE[2] Input with PD
BOOT_MODE3
G17
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
ccmsrcgpcmix.BOOT_MODE[3] Input with PD
CLKIN1
E20
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
—
—
Input without
PU/PD
CLKIN2
F20
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
—
—
Input without
PU/PD
CLKOUT1
E21
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
—
—
Output low
without
PU/PD
CLKOUT2
F21
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
—
—
Output low
without
PU/PD
DRAM_AC00
P1
NVCC_DRAM
DDR
—
—
Output low
DRAM_AC01
N1
NVCC_DRAM
DDR
—
—
Output low
DRAM_AC02
N2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC03
P2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC04
G5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC05
G4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC06
D4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC07
E4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC08
R1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC09
R2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC10
M2
NVCC_DRAM
DDR
—
—
Input
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
95
Package information and contact assignments
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
DRAM_AC11
L2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC12
L1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC13
M1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC14
Y1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC15
L5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC16
J4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC17
J5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC20
T1
NVCC_DRAM
DDR
—
—
Output low
DRAM_AC21
T2
NVCC_DRAM
DDR
—
—
Output low
DRAM_AC23
R4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC24
Y2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC25
AA2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC26
W2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC28
AA3
NVCC_DRAM
DDR
—
—
Input
DRAM_AC29
V4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC30
W1
NVCC_DRAM
DDR
—
—
Input
DRAM_AC31
Y3
NVCC_DRAM
DDR
—
—
Input
DRAM_AC32
R5
NVCC_DRAM
DDR
—
—
Input
DRAM_AC33
U2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC34
V2
NVCC_DRAM
DDR
—
—
Input
DRAM_AC35
U4
NVCC_DRAM
DDR
—
—
Input
DRAM_AC36
V1
NVCC_DRAM
DDR
—
—
Input
DRAM_ALERT_N
N5
NVCC_DRAM
DDR
—
—
Input
DRAM_DM0
B2
NVCC_DRAM
DDR
—
—
Input
DRAM_DM1
H2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ00
B3
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ01
A2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ02
A3
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ03
B4
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ04
E2
NVCC_DRAM
DDR
—
—
Input
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
96
NXP Semiconductors
Package information and contact assignments
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
DRAM_DQ05
D1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ06
C1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ07
D2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ08
G1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ09
H1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ10
J1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ11
J2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ12
K1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ13
K2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ14
F2
NVCC_DRAM
DDR
—
—
Input
DRAM_DQ15
E1
NVCC_DRAM
DDR
—
—
Input
DRAM_DQS0_N
C2
NVCC_DRAM
—
—
—
Input
DRAM_DQS0_P
B1
NVCC_DRAM
DDRCLK
—
—
Input
DRAM_DQS1_N
F1
NVCC_DRAM
—
—
—
Input
DRAM_DQS1_P
G2
NVCC_DRAM
DDRCLK
—
—
Input
DRAM_RESET_N
N4
NVCC_DRAM
DDR
—
—
Output low
DRAM_VREF
L4
NVCC_DRAM
DDR
—
—
—
DRAM_ZN
U1
NVCC_DRAM
DDR
—
—
—
ECSPI1_MISO
D6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[8]
Input with PD
ECSPI1_MOSI
F6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[7]
Input with PD
ECSPI1_SCLK
E6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[6]
Input with PD
ECSPI1_SS0
B6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[9]
Input with PD
ECSPI2_MISO
B5
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[12]
Input with PD
ECSPI2_MOSI
A6
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[11]
Input with PD
ECSPI2_SCLK
A4
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[10]
Input with PD
ECSPI2_SS0
A5
NVCC_ECSPI
GPIO
ALT5
GPIO5.IO[13]
Input with PD
ENET_MDC
Y18
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[16]
Input with PD
ENET_MDIO
T16
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[17]
Input with PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
97
Package information and contact assignments
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
ENET_RD0
AA19
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[26]
Input with PD
ENET_RD1
Y15
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[27]
Input with PD
ENET_RD2
Y16
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[28]
Input with PD
ENET_RD3
AA16
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[29]
Input with PD
ENET_RXC
U16
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[25]
Input with PD
ENET_RX_CTL
V16
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[24]
Input with PD
ENET_TD0
U18
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[21]
Input with PD
ENET_TD1
AA18
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[20]
Input with PD
ENET_TD2
V18
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[19]
Input with PD
ENET_TD3
AA17
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[18]
Input with PD
ENET_TXC
Y19
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[23]
Input with PD
ENET_TX_CTL
Y17
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO1.IO[22]
Input with PD
GPIO1_IO00
V8
NVCC_ENET_GPI
O_SAI2
GPIO
ALT6
GPIO1.IO[0]
Input with PD
GPIO1_IO01
R8
NVCC_ENET_GPI
O_SAI2
GPIO
ALT6
GPIO1.IO[1]
1
GPIO1_IO02
AA8
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[2]
Input with PU
GPIO1_IO03
Y9
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[3]
Input with PD
GPIO1_IO04
AA7
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[4]
Input with PD
GPIO1_IO05
T8
NVCC_ENET_GPI
O_SAI2
GPIO
ALT6
GPIO1.IO[5]
1
GPIO1_IO06
Y8
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[6]
Input with PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
98
NXP Semiconductors
Package information and contact assignments
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
GPIO1_IO07
U8
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[7]
Input with PD
GPIO1_IO08
V10
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[8]
Input with PD
GPIO1_IO09
AA9
NVCC_ENET_GPI
O_SAI2
GPIO
ALT1
GPIO1.IO[9]
Input with PD
GPIO1_IO10
AA10
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[10]
Input with PD
GPIO1_IO11
Y11
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[11]
Input with PD
GPIO1_IO12
U10
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[12]
Input with PD
GPIO1_IO13
T10
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[13]
Input with PD
GPIO1_IO14
Y10
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[14]
Input with PD
GPIO1_IO15
AA11
NVCC_ENET_GPI
O_SAI2
GPIO
ALT0
GPIO1.IO[15]
Input with PD
I2C1_SCL
B7
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[14]
Input with PD
I2C1_SDA
A7
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[15]
Input with PD
I2C2_SCL
F10
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[16]
Input with PD
I2C2_SDA
D8
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[17]
Input with PD
I2C3_SCL
F8
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[18]
Input with PD
I2C3_SDA
E8
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[19]
Input with PD
I2C4_SCL
B8
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[20]
Input with PD
I2C4_SDA
A8
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[21]
Input with PD
JTAG_MOD
D18
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
cjtag_wrapper.MOD
Input with PD
JTAG_TCK
D21
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
cjtag_wrapper.TCK
Input with PU
JTAG_TDI
C21
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
cjtag_wrapper.TDI
Input with PU
JTAG_TDO
D20
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
cjtag_wrapper.TDO
Input with PU
JTAG_TMS2
E18
NVCC_CLK_JTAG
_PVCC_1P8
GPIO
ALT0
cjtag_wrapper.TMS
Input with PU
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
99
Package information and contact assignments
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
MIPI_CSI_CLK_N
A13
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_CLK_P
B13
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_D0_N
A11
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_D0_P
B11
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_D1_N
A12
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_D1_P
B12
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_D2_N
A14
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_D2_P
B14
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_D3_N
A15
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_CSI_D3_P
B15
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
MIPI_VREG_CAP
D12
0.35 - 0.45 V
PHY
—
—
Output
NAND_ALE
J17
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[0]
Input with PD
NAND_CE0_B
L21
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[1]
Input with PD
NAND_CE1_B
H20
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[2]
Input with PD
NAND_CE2_B
L16
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[3]
Input with PD
NAND_CE3_B
L20
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[4]
Input with PD
NAND_CLE
K20
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[5]
Input with PD
NAND_DATA00
M21
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[6]
Input with PD
NAND_DATA01
J20
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[7]
Input with PD
NAND_DATA02
M20
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[8]
Input with PD
NAND_DATA03
K21
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[9]
Input with PD
NAND_DATA04
L18
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[10]
Input with PD
NAND_DATA05
J18
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[11]
Input with PD
NAND_DATA06
N20
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[12]
Input with PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
100
NXP Semiconductors
Package information and contact assignments
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
NAND_DATA07
G20
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[13]
Input with PD
NAND_DQS
H21
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[14]
Input with PD
NAND_RE_B
G21
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[15]
Input with PD
NAND_READY_B
L17
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[16]
Input with PD
NAND_WE_B
J16
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[17]
Input with PD
NAND_WP_B
J21
NVCC_SD1_NAND
GPIO
ALT5
GPIO3.IO[18]
Input with PD
ONOFF
E14
NVCC_SNVS_1P8
GPIO
ALT0
snvsmix.ONOFF
Input without
PU/PD
PMIC_ON_REQ
E16
NVCC_SNVS_1P8
GPIO
ALT0
snvsmix.PMIC_ON_REQ
Open-drain
output high
with PU
PMIC_STBY_REQ
A19
NVCC_SNVS_1P8
GPIO
ALT0
ccmsrcgpcmix.PMIC_STBY_RE
Q
Output low
with PD
POR_B
A18
NVCC_SNVS_1P8
GPIO
ALT0
snvsmix.POR_B
Input without
PU/PD
RTC_XTALI
A20
NVCC_SNVS_1P8
ANALOG
ALT0
snvsmix.RTC
Input
RTC_XTALO
B19
NVCC_SNVS_1P8
ANALOG
—
—
Output,
inverted of
RTC_XTALI
RTC_RESET_B
B18
NVCC_SNVS_1P8
GPIO
ALT0
snvsmix.RTC_POR_B
Input without
PU/PD
SAI2_MCLK
Y12
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO4.IO[27]
Input with PD
SAI2_RXC
AA15
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO4.IO[22]
Input with PD
SAI2_RXD0
AA14
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO4.IO[23]
Input with PD
SAI2_RXFS
Y13
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO4.IO[21]
Input with PD
SAI2_TXC
AA13
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO4.IO[25]
Input with PD
SAI2_TXD0
Y14
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO4.IO[26]
Input with PD
SAI2_TXFS
AA12
NVCC_ENET_GPI
O_SAI2
GPIO
ALT5
GPIO4.IO[24]
Input with PD
SAI3_MCLK
AA5
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO5.IO[2]
Input with PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
101
Package information and contact assignments
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
SAI3_RXC
Y6
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO4.IO[29]
Input with PD
SAI3_RXD
AA6
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO4.IO[30]
Input with PD
SAI3_RXFS
Y4
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO4.IO[28]
Input with PD
SAI3_TXC
Y5
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO5.IO[0]
Input with PD
SAI3_TXD
AA4
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO5.IO[1]
Input with PD
SAI3_TXFS
Y7
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO4.IO[31]
Input with PD
SAI5_MCLK
W11
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO3.IO[25]
3
SAI5_RXC
V14
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO3.IO[20]
Input with PD
SAI5_RXD0
U12
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO3.IO[21]
Input with PD
SAI5_RXD1
T14
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO3.IO[22]
Input with PD
SAI5_RXD2
V12
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO3.IO[23]
Input with PD
SAI5_RXD3
U14
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO3.IO[24]
Input with PD
SAI5_RXFS
T12
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO3.IO[19]
Input with PD
SD1_CLK
R21
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[0]
Input with PD
SD1_CMD
T21
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[1]
Input with PD
SD1_DATA0
N18
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[2]
Input with PD
SD1_DATA1
N17
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[3]
Input with PD
SD1_DATA2
N21
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[4]
Input with PD
SD1_DATA3
P20
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[5]
Input with PD
SD1_DATA4
P21
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[6]
Input with PD
SD1_DATA5
T20
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[7]
Input with PD
SD1_DATA6
R20
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[8]
Input with PD
SD1_DATA7
N16
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[9]
Input with PD
SD1_RESET_B
R18
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[10]
Input with PD
SD1_STROBE
R17
NVCC_SD1_NAND
GPIO
ALT5
GPIO2.IO[11]
Input with PD
SD2_CD_B
U20
NVCC_SD2
GPIO
ALT5
GPIO2.IO[12]
Input with PD
SD2_CLK
Y21
NVCC_SD2
GPIO
ALT5
GPIO2.IO[13]
Input with PD
SD2_CMD
V21
NVCC_SD2
GPIO
ALT5
GPIO2.IO[14]
Input with PD
SD2_DATA0
AA20
NVCC_SD2
GPIO
ALT5
GPIO2.IO[15]
Input with PD
SD2_DATA1
U21
NVCC_SD2
GPIO
ALT5
GPIO2.IO[16]
Input with PD
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
102
NXP Semiconductors
Package information and contact assignments
Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)
Reset condition
Ball name
Ball
Power group
Ball type
Default
mode
Default function
Input/
Output
status
SD2_DATA2
W20
NVCC_SD2
GPIO
ALT5
GPIO2.IO[17]
Input with PD
SD2_DATA3
V20
NVCC_SD2
GPIO
ALT5
GPIO2.IO[18]
Input with PD
SD2_RESET_B
Y20
NVCC_SD2
GPIO
ALT5
GPIO2.IO[19]
Input with PD
SD2_WP
W21
NVCC_SD2
GPIO
ALT5
GPIO2.IO[20]
Input with PD
SPDIF_EXT_CLK
T6
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO5.IO[5]
Input with PD
SPDIF_RX
U6
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO5.IO[4]
Input with PD
SPDIF_TX
V6
NVCC_SAI3_SAI5
GPIO
ALT5
GPIO5.IO[3]
Input with PD
TSENSOR_RES_E
XT
D16
VDD_ANA1_XTAL_
MIPI_USB_1P8
ANALOG
—
—
—
UART1_RXD
A9
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[22]
Input with PD
UART1_TXD
E10
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[23]
Input with PD
UART2_RXD
B9
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[24]
Input with PD
UART2_TXD
C11
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[25]
Input with PD
UART3_RXD
B10
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[26]
Input with PD
UART3_TXD
E12
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[27]
Input with PD
UART4_RXD
A10
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[28]
Input with PD
UART4_TXD
D10
NVCC_I2C_UART
GPIO
ALT5
GPIO5.IO[29]
Input with PD
USB1_DN
A17
VDD_USB_3P3
PHY
—
—
Input
USB1_DP
B17
VDD_USB_3P3
PHY
—
—
Input
USB1_ID
D14
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
Input
USB1_TXRTUNE
B16
VDD_ANA1_XTAL_
MIPI_USB_1P8
PHY
—
—
—
USB1_VBUS
A16
VDD_USB_3P3
PHY
—
—
—
1
During reset: output high without PU/PD; After reset: input with PU
Mandatory requirement: JTAG_TMS pin must be connected with a 50 ohm serial resistor near the component.
3 During reset: input without PU/PD; After reset: input with PD
2
5.2.3
i.MX 8M Nano 11 x 11 mm 0.5 mm pitch ball map
Table 79 shows the i.MX 8M Nano 11 x 11 mm 0.5 mm pitch ball map.
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
103
104
UART3_TXD
ONOFF
VDD_MIPI_1P2
VDD_USB_3P3
CLKIN1
CLKOUT1
CLKOUT2
JTAG_TDI
24M_XTALO
24M_XTALI
VSS
VSS
RTC_XTALI
20
JTAG_TCK
JTAG_TDO
PMIC_STBY_REQ
POR_B
19
CLKIN2
RTC_XTALO
RTC_RESET_B
18
VSS
VSS
17
JTAG_MOD
USB1_DN
USB1_DP
16
JTAG_TMS
USB1_VBUS
MIPI_CSI_D3_N
MIPI_CSI_D3_P
15
USB1_TXRTUNE
MIPI_CSI_D2_N
MIPI_CSI_D2_P
MIPI_CSI_CLK_P MIPI_CSI_CLK_N
14
VSS
VSS
13
USB1_ID
12
MIPI_CSI_D1_N
MIPI_CSI_D1_P
MIPI_CSI_D0_N
11
VSS
MIPI_CSI_D0_P
UART2_TXD
UART4_RXD
10
MIPI_VREG_CAP
UART3_RXD
VSS
UART1_RXD
UART2_RXD
9
UART4_TXD
I2C4_SDA
I2C4_SCL
8
PMIC_ON_REQ TSENSOR_RES_EXT
UART1_TXD
I2C2_SCL
VSS
I2C1_SDA
I2C1_SCL
7
I2C2_SDA
ECSPI2_MOSI
ECSPI1_SS0
6
BOOT_MODE2
I2C3_SDA
I2C3_SCL
VSS
5
ECSPI1_MISO
4
ECSPI1_SCLK
3
ECSPI1_MOSI
ECSPI2_SS0
DRAM_DQ02
DRAM_DQ01
ECSPI2_MISO
DRAM_DM0
VSS
ECSPI2_SCLK
VSS
DRAM_DQS0_N
DRAM_DQS0_P
A
DRAM_DQ03
DRAM_AC06
DRAM_DQ07
DRAM_DQ06
B
DRAM_AC07
DRAM_DQ04
DRAM_DQ14
DRAM_DQ05
C
2
DRAM_DQ00
DRAM_DQ15
DRAM_DQS1_N
D
1
VSS
E
F
Package information and contact assignments
Table 79. 11 x 11 mm, 0.5 mm pitch ball map
21
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
NXP Semiconductors
NVCC_DRAM
VSS
VDD_SOC
VDD_DRAM_PLL_1P8
VSS
VDD_SOC
NAND_WP_B
NAND_DQS
NAND_RE_B
20
NAND_DATA03
19
NAND_DATA07
VSS
18
NAND_CE0_B
VSS
VSS
BOOT_MODE1
17
NAND_DATA00
NAND_DATA05
NAND_DATA04
16
BOOT_MODE3
BOOT_MODE0
15
NAND_DATA01 NAND_CE1_B
NAND_ALE
NAND_READY_B
NAND_CLE
NAND_WE_B
NAND_CE2_B
NVCC_SNVS_1P8
14
NAND_CE3_B
VDD_SNVS_0P8
NVCC_CLK_JTAG_PVCC_1P8
VSS
VDD_ANA1_XTAL_MIPI_USB_1P8
13
NAND_DATA02
VSS
VSS
VSS
12
VDD_SOC
VDD_SOC
11
VDD_SOC
VDD_SOC
VDD_SOC
10
VDD_SOC
9
VDD_SOC
8
VSS
7
NVCC_I2C_UART
NVCC_ECSPI
6
VSS
VSS
NVCC_DRAM
DRAM_AC04
DRAM_AC05
VSS
DRAM_DQS1_P
5
VDD_SOC
NVCC_DRAM
NVCC_DRAM
VDD_SOC
DRAM_AC17
DRAM_AC15
DRAM_DM1
DRAM_DQ08
G
4
VDD_SOC
DRAM_AC16
DRAM_DQ11
DRAM_DQ09
H
3
VSS
VDD_SOC
DRAM_DQ13
DRAM_DQ10
DRAM_VREF
DRAM_AC11
DRAM_AC10
DRAM_DQ12
J
2
VSS
DRAM_AC12
DRAM_AC13
K
1
VSS
L
M
Package information and contact assignments
Table 79. 11 x 11 mm, 0.5 mm pitch ball map (continued)
21
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
105
106
ENET_TD2
SD2_DATA3
SD2_CMD
VSS
SD2_DATA2
SD2_WP
SD1_CLK
SD1_DATA4
SD1_DATA3
SD1_DATA2
NAND_DATA06
20
SD1_CMD
SD1_DATA6
19
SD2_DATA1
SD1_DATA5
VSS
18
SD2_CD_B
VSS
VSS
SD1_DATA0
17
SD1_RESET_B
16
ENET_TD0
SD1_DATA1
SD1_STROBE
NVCC_SD1_NAND
SD1_DATA7
VSS
NVCC_SD2
15
ENET_MDIO
14
ENET_RXC
VSS
ENET_RX_CTL
VDD_ANA0_ARM_PLL_1P8
VSS
SAI5_RXD1
11
SAI5_RXD3
SAI5_RXC
VSS
VDD_SOC
VSS
NVCC_ENET_GPIO_SAI2
VSS
VDD_SOC
13
VDD_SOC
SAI5_RXFS
NVCC_SAI3_SAI5
VSS
12
VDD_SOC
SAI5_RXD0
VSS
10
SAI5_RXD2
GPIO1_IO13
GPIO1_IO01
9
GPIO1_IO12
GPIO1_IO05
NVCC_DRAM
8
VSS
GPIO1_IO08
VSS
GPIO1_IO07
7
NVCC_DRAM
DRAM_ALERT_N
DRAM_AC32
NVCC_DRAM
DRAM_RESET_N
VSS
DRAM_AC02
6
VDD_SOC
GPIO1_IO00
VSS
SPDIF_EXT_CLK
DRAM_AC03
DRAM_AC01
DRAM_AC23
VSS
DRAM_AC09
DRAM_AC00
N
5
SPDIF_RX
DRAM_AC21
DRAM_AC08
P
4
SAI5_MCLK
SPDIF_TX
DRAM_AC35
VSS
DRAM_AC33
DRAM_AC20
R
3
VSS
DRAM_AC34
DRAM_AC26
DRAM_ZN
T
2
DRAM_AC29
DRAM_AC36
DRAM_AC30
U
1
VSS
V
W
Package information and contact assignments
Table 79. 11 x 11 mm, 0.5 mm pitch ball map (continued)
21
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
Package information and contact assignments
Table 79. 11 x 11 mm, 0.5 mm pitch ball map (continued)
SD2_CLK
21
VSS
20
SD2_DATA0 SD2_RESET_B
ENET_MDC
ENET_TD1
ENET_TXC
ENET_TX_CTL
ENET_TD3
19
ENET_RD0
ENET_RD2
ENET_RD3
18
ENET_RD1
17
SAI2_RXC
16
SAI2_TXD0
15
SAI2_RXD0
SAI2_MCLK
SAI2_TXFS
14
SAI2_RXFS
GPIO1_IO11
GPIO1_IO15
13
SAI2_TXC
GPIO1_IO14
12
GPIO1_IO10
11
GPIO1_IO03
10
GPIO1_IO09
SAI3_TXFS
GPIO1_IO04
9
GPIO1_IO06
SAI3_RXC
SAI3_RXD
8
GPIO1_IO02
SAI3_TXC
SAI3_MCLK
7
SAI3_RXFS
6
SAI3_TXD
5
DRAM_AC31
4
DRAM_AC28
3
DRAM_AC24
DRAM_AC14
VSS
5.3
2
DRAM_AC25
Y
AA
1
DDR pin function list
Table 80 shows the DDR pin function list.
Table 80. DDR pin function list
Ball name
LPDDR4
DDR4
DDR3/3L
DRAM_DQS0_P
DQS0_t_A
DQSL_t_A
DQSL_A
DRAM_DQS0_N
DQS0_c_A
DQSL_c_A
DQSL#_A
DRAM_DM0
DMI0_A
DML_n_A / DBIL_n_A
DML_A
DRAM_DQ00
DQ0_A
DQL0_A
DQL0_A
DRAM_DQ01
DQ1_A
DQL1_A
DQL1_A
DRAM_DQ02
DQ2_A
DQL2_A
DQL2_A
DRAM_DQ03
DQ3_A
DQL3_A
DQL3_A
DRAM_DQ04
DQ4_A
DQL4_A
DQL4_A
DRAM_DQ05
DQ5_A
DQL5_A
DQL5_A
DRAM_DQ06
DQ6_A
DQL6_A
DQL6_A
DRAM_DQ07
DQ7_A
DQL7_A
DQL7_A
DRAM_DQS1_P
DQS1_t_A
DQSU_t_A
DQSU_A
DRAM_DQS1_N
DQS1_c_A
DQSU_c_A
DQSU#_A
DRAM_DM1
DMI1_A
DMU_n_A / DBIU_n_A
DMU_A
DRAM_DQ08
DQ08_A
DQU0_A
DQU0_A
DRAM_DQ09
DQ09_A
DQU1_A
DQU1_A
DRAM_DQ10
DQ10_A
DQU2_A
DQU2_A
DRAM_DQ11
DQ11_A
DQU3_A
DQU3_A
DRAM_DQ12
DQ12_A
DQU4_A
DQU4_A
DRAM_DQ13
DQ13_A
DQU5_A
DQU5_A
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
107
Package information and contact assignments
Table 80. DDR pin function list (continued)
DRAM_DQ14
DQ14_A
DQU6_A
DQU6_A
DRAM_DQ15
DQ15_A
DQU7_A
DQU7_A
DRAM_RESET_N
RESET_N
RESET_n
RESET#
DRAM_ALERT_N
MTEST1
ALERT_n / MTEST1
MTEST1
DRAM_AC00
CKE0_A
CKE0
CKE0
DRAM_AC01
CKE1_A
CKE1
CKE1
DRAM_AC02
CS0_A
CS0_n
CS0#
DRAM_AC03
CS1_A
C0
—
DRAM_AC04
CK_t_A
BG0
BA2
DRAM_AC05
CK_c_A
BG1
A14
DRAM_AC06
—
ACT_n
A15
DRAM_AC07
—
A9
A9
DRAM_AC08
CA0_A
A12
A12 / BC#
DRAM_AC09
CA1_A
A11
A11
DRAM_AC10
CA2_A
A7
A7
DRAM_AC11
CA3_A
A8
A8
DRAM_AC12
CA4_A
A6
A6
DRAM_AC13
CA5_A
A5
A5
DRAM_AC14
—
A4
A4
DRAM_AC15
—
A3
A3
DRAM_AC16
—
CK_t_A
CK_A
DRAM_AC17
—
CK_c_A
CK#_A
DRAM_AC19
MTEST
MTEST
MTEST
DRAM_AC20
CKE0_B
CK_t_B
CK_B
DRAM_AC21
CKE1_B
CK_c_B
CK#_B
DRAM_AC22
CS1_B
—
—
DRAM_AC23
CS0_B
—
—
DRAM_AC24
CK_t_B
A2
A2
DRAM_AC25
CK_c_B
A1
A1
DRAM_AC26
—
BA1
BA1
DRAM_AC27
—
PARITY
—
DRAM_AC28
CA0_B
A13
A13
DRAM_AC29
CA1_B
BA0
BA0
DRAM_AC30
CA2_B
A10 / AP
A10 / AP
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
108
NXP Semiconductors
Package information and contact assignments
Table 80. DDR pin function list (continued)
DRAM_AC31
CA3_B
A0
A0
DRAM_AC32
CA4_B
C2
—
DRAM_AC33
CA5_B
CAS_n / A15
CAS#
DRAM_AC34
—
WE_n / A14
WE#
DRAM_AC35
—
RAS_n / A16
RAS#
DRAM_AC36
—
ODT0
ODT0
DRAM_AC37
—
ODT1
ODT1
DRAM_AC38
—
CS1_n
CS1#
DRAM_ZN
ZQ
ZQ
ZQ
DRAM_VREF
VREF
VREF
VREF
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
109
Revision history
6
Revision history
Table 81 provides a revision history for this data sheet.
Table 81. Revision history
Rev.number
Date
Substantive change(s)
Rev. 1
03/2021
• Updated the M7 frequency in the Chapter 1, i.MX 8M Nano introduction
• Added a note for the Figure 1, "i.MX 8M Nano system block diagram" and Table 2,
"Modules supported"
• Added part numbers for 11 x 11 mm package and descriptions in the Table 3, "Orderable
part numbers"
• Updated the package type and part differentiator in the Figure 2, "Part number
nomenclature—i.MX 8M Nano family of processors"
• Updated the LCDIF descriptions in the Table 4, "i.MX 8M Nano modules list"
• Updated the Section 2.1, Recommended connections for unused input/output
• Updated the title and the maximum values of VDD_ARM_PLL_0P8 and VDD_USB_0P8
in the Table 10, "Absolute maximum ratings for 14 x 14 mm package"
• Added the Table 11, "Absolute maximum ratings for 11 x 11 mm package"
• Updated the title of Table 13, "14 x 14 mm package thermal resistance data"
• Added the new Section 3.1.2.2, 11 x 11 mm FCBGA package thermal resistance
• Updated the VDD_ANA_0P8, VDD_ARM_PLL_0P8, VDD_MIPI_0P8, VDD_USB_0P8,
VDD_DRAM_PLL_0P8, and USB1_VBUS in the Table 15, "Operating ranges for 14 x 14
mm package"
• Added the Table 16, "Operating ranges for 11 x11 mm package"
• Updated the title of Table 19, "Estimated power supply maximum currents for 14 x 14 mm
package"
• Added the Table 20, "Estimated power supply maximum currents for 11 x 11 mm package"
• Updated and added Low-V suspend mode data in the Table 21, "Chip power in different LP
mode for 14 x 14 mm package"
• Added the Table 22, "Chip power in different LP mode for 11 x 11 mm package"
• Updated and added a foot note in the Table 23, "The power supply states for 14 x 14 mm
package"
• Added the Table 25, "The power supply states for 11 x 11 mm package"
• Updated POR_B and added a note for Figure 3, "The power-up sequence for 14 x 14 mm
package"
• Updated the T13 descriptions in the Table 26, "Power-up sequence for 14 x 14 mm
package"
• Added the Figure 4, "The power-up sequence for 11 x 11 mm package" and Table 27,
"Power-up sequence for 11 x 11 mm package"
• Updated the titles of Figure 5, "The power-down sequence for 14 x 14 mm package" and
Table 28, "Power-down sequence for 14 x 14 mm package"
• Added the Figure 6, "The power-down sequence for 11 x 11 mm package" and Table 29,
"Power-down sequence for 11 x 11 mm package"
• Removed the Section, Power supplies constraints
• Updated the lock time and GPU values in the Table 30, "PLL electrical parameters"; added
the M7_ALT_PLL in the Table 30, "PLL electrical parameters"
• Fixed a typo in the Table 74, "i.MX 8M Nano 14 x 14 mm supplies contact assignments"
• Changed the name of TSENSOR_RES_EXT in the Table 75, "i.MX 8M Nano 14 x 14 mm
functional contact assignments"; updated the input/out status of GPIO1_IO07,
NAND_CE0_B, and NAND_RE_B in the Table 75, "i.MX 8M Nano 14 x 14 mm functional
contact assignments"
• Updated the names of H10, M1, and W22 in the Table 76, "14 x 14 mm, 0.5 mm pitch ball
map"
• Added the Section 5.2, 11 x 11 mm package information
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
110
NXP Semiconductors
Revision history
Table 81. Revision history (continued)
Rev.number
Date
Substantive change(s)
Rev. 1
02/2021
• Updated LPDDR4 information of DRAM_AC14 and DRAMAC34 in the Table 80, "DDR pin
function list"
Rev. 0.1
03/2020
• Updated the Table, “Power supplies constraints”
Rev. 0
10/2019
• Initial version
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021
NXP Semiconductors
111
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Date of release: April, 2021
Document identifier: IMX8MNIEC