NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMXRT1050IEC
Rev. 1, 03/2018
MIMXRT1051CVL5A
MIMXRT1051CVL5B
MIMXRT1052CVL5A
MIMXRT1052CVL5B
i.MX RT1050 Crossover
Processors for Industrial
Products
Package Information
Plastic Package
196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch
Ordering Information
See Table 1 on page 5
1
i.MX RT1050 introduction
The i.MX RT1050 is a new processor family featuring
NXP’s advanced implementation of the Arm
Cortex®-M7 core, which operates at speeds up to 528
MHz to provide high CPU performance and best
real-time response.
The i.MX RT1050 processor has 512 KB on-chip RAM,
which can be flexibly configured as TCM or
general-purpose on-chip RAM. The i.MX RT1050
integrates advanced power management module with
DCDC and LDO that reduces complexity of external
power supply and simplifies power sequencing. The
i.MX RT1050 also provides various memory interfaces,
including SDRAM, RAW NAND FLASH, NOR
FLASH, SD/eMMC, Quad SPI, and a wide range of
other interfaces for connecting peripherals, such as
WLAN, Bluetooth™, GPS, displays, and camera
sensors. The i.MX RT1050 also has rich audio and video
features, including LCD display, basic 2D graphics,
camera interface, SPDIF, and I2S audio interface.
© 2017-2018 NXP Semiconductors. All rights reserved.
1. i.MX RT1050 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 5
2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1. Special signal considerations . . . . . . . . . . . . . . . 14
3.2. Recommended connections for unused analog
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 17
4.2. System power and clocks . . . . . . . . . . . . . . . . . . 23
4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5. External memory interface . . . . . . . . . . . . . . . . . 38
4.6. Display and graphics . . . . . . . . . . . . . . . . . . . . . . 48
4.7. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.8. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.9. Communication interfaces . . . . . . . . . . . . . . . . . . 60
4.10. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 75
5.2. Boot device interface allocation . . . . . . . . . . . . . . 75
6. Package information and contact assignments . . . . . . . 80
6.1. 10 x 10 mm package information . . . . . . . . . . . . 80
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
i.MX RT1050 introduction
The i.MX RT1050 is specifically useful for applications such as:
• Industrial Human Machine Interfaces (HMI)
• Motor Control
• Home Appliance
1.1
Features
The i.MX RT1050 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the
following features:
• Supports single Arm Cortex-M7 MPCore with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
— Support the Armv7-M Thumb instruction set
• Integrated MPU, up to 16 individual protection regions
• Up to 512 KB I-TCM and D-TCM in total
• Frequency of 528 MHz
• Cortex M7 CoreSight™ components integration for debug
• Frequency of the core, as per Table 9, "Operating ranges," on page 19.
The SoC-level memory system consists of the following additional components:
— Boot ROM (96 KB)
— On-chip RAM (512 KB)
– Configurable RAM size up to 512 KB shared with M7 TCM
• External memory interfaces:
— 8/16-bit SDRAM, up to SDRAM-166
— 8/16-bit SLC NAND FLASH, with ECC handled in software
— SD/eMMC
— SPI NOR FLASH
— Parallel NOR FLASH with XIP support
— Single/Dual channel Quad SPI FLASH with XIP support
• Timers and PWMs:
— Two General Programmable Timers (GPT)
– 4-channel generic 32-bit resolution timer
– Each support standard capture and compare operation
— Four Periodical Interrupt Timer (PIT)
– Generic 16-bit resolution timer
– Periodical interrupt generation
— Four Quad Timers (QTimer)
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i.MX RT1050 introduction
– 4-channel generic 16-bit resolution timer for each
– Each support standard capture and compare operation
– Quadrature decoder integrated
— Four FlexPWMs
– Up to 8 individual PWM channels for each
– 16-bit resolution PWM suitable for Motor Control applications
— Four Quadrature Encoder/Decoders
Each i.MX RT1050 processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Display Interface:
— Parallel RGB LCD interface
– Support 8/16/24 bit interface
– Support up to 1366 x 768 WXGA resolution
– Support Index color with 256 entry x 24 bit color LUT
– Smart LCD display with 8/16-bit MPU/8080 interface
• Audio:
— S/PDIF input and output
— Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces
— MQS interface for medium quality audio via GPIO pads
• Generic 2D graphics engine:
— BitBlit
— Flexible image composition options—alpha, chroma key
— Image rotation (90, 180, 270)
— Porter-Daff operation
— Image size
— Color space conversion
— Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)
— Standard 2D-DMA operation
• Camera sensors:
— Support 24-bit, 16-bit, and 8-bit CSI input
• Connectivity:
— Two USB 2.0 OTG controllers with integrated PHY interfaces
— Two Ultra Secure Digital Host Controller (uSDHC) interfaces
– MMC 4.5 compliance with HS200 support up to 200 MB/sec
– SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec
– Support for SDXC (extended capacity)
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i.MX RT1050 introduction
•
— One 10/100 M Ethernet controller with support for IEEE1588
— Eight universal asynchronous receiver/transmitter (UARTs) modules
— Four I2C modules
— Four SPI modules
— Two FlexCAN modules
GPIO and Pin Multiplexing:
— General-purpose input/output (GPIO) modules with interrupt capability
— Input/output multiplexing controller (IOMUXC) to provide centralized pad control
— Two FlexIOs
The i.MX RT1050 processors integrate advanced power management unit and controllers:
• Full PMIC integration. On-chip DCDC and LDO
• Temperature sensor with programmable trip points
• GPC hardware power management controller
The i.MX RT1050 processors support the following system debug:
• Arm CoreSight debug and trace architecture
• Trace Port Interface Unit (TPIU) to support off-chip real-time trace
• Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse
Security functions are enabled and accelerated by the following hardware:
• High Assurance Boot (HAB)
• Data Co-Processor (DCP):
— AES-128, ECB, and CBC mode
— SHA-1 and SHA-256
— CRC-32
• Bus Encryption Engine (BEE)
— AES-128, ECB, and CTR mode
— On-the-fly QSPI Flash decryption
• True random number generation (TRNG)
• Secure Non-Volatile Storage (SNVS)
— Secure real-time clock (RTC)
— Zero Master Key (ZMK)
• Secure JTAG Controller (SJC)
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions such as display and camera interfaces, connectivity interfaces,
and security features are not offered on all derivatives.
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i.MX RT1050 introduction
1.2
Ordering information
Table 1 provides examples of orderable part numbers covered by this Data Sheet.
Table 1. Ordering information
Part Number
Feature
Package
Junction
Temperature Tj
(C)
MIMXRT1051CVL5A
MIMXRT1051CVL5B
Features supports:
• 528 MHz, industrial grade for general
purpose
• No LCD/PXP/CSI
• CAN x2
• Ethernet
• eMMC 4.5/SD 3.0 x2
• USB OTG x2
• UART x8
• SAI x3
• Timer x4
• PWM x4
• I2C x4
• SPI x4
10 x 10 mm, 0.65 pitch, 196
MAPBGA
-40 to +105 C
MIMXRT1052CVL5A
MIMXRT1052CVL5B
Features supports:
• 528 MHz, industrial grade for general
purpose
• With LCD/CSI/PXP
• CAN x2
• Ethernet
• eMMC 4.5/SD 3.0 x2
• USB OTG x2
• UART x8
• SAI x3
• Timer x4
• PWM x4
• I2C x4
• SPI x4
10 x 10 mm, 0.65 pitch, 196
MAPBGA
-40 to +105 C
Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be
identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The
primary characteristic which describes which data sheet applies to a specific part is the temperature grade
(junction) field.
• The i.MX RT1050 Crossover Processors for Industrial Products Data Sheet (IMXRT1050IEC)
covers parts listed with a “C (Industrial temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/imxrtseries
or contact an NXP representative for details.
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i.MX RT1050 introduction
M
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Special
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Part # series
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First Generation RT family
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Reserved
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Frequency
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Temperature
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Consumer: 0 to + 95 °C
D
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C
Figure 1. Part number nomenclature—i.MX RT1050
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Architectural overview
2
Architectural overview
The following subsections provide an architectural overview of the i.MX RT1050 processor system.
2.1
Block diagram
Figure 2 shows the functional modules in the i.MX RT1050 processor system1.
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Figure 2. i.MX RT1050 system block diagram
1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.
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Modules list
3
Modules list
The i.MX RT1050 processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX RT1050 modules list
Block Mnemonic
Block Name
Subsystem
Brief Description
ACMP1
ACMP2
ACMP3
ACMP4
Analog Comparator
Analog
The comparator (CMP) provides a circuit for comparing
two analog input voltages. The comparator circuit is
designed to operate across the full range of the supply
voltage (rail-to-rail operation).
ADC1
ADC2
Analog to Digital
Converter
Analog
The ADC is a 12-bit general purpose analog to digital
converter.
AOI
And-Or-Inverter
Cross Trigger
The AOI provides a universal boolean function
generator using a four team sum of products expression
with each product term containing true or complement
values of the four selected inputs (A, B, C, D).
Arm
Arm Platform
Arm
The Arm Core Platform includes one Cortex-M7 core. It
includes associated sub-blocks, such as Nested
Vectored Interrupt Controller (NVIC), Floating-Point
Unit (FPU), Memory Protection Unit (MPU), and
CoreSight debug modules.
BEE
Bus Encryption Engine
Security
CCM
GPC
SRC
On-The-Fly FlexSPI Flash Decryption
Clock Control Module, Clocks, Resets, and These modules are responsible for clock and reset
General Power
Power Control
distribution in the system, and also for the system
Controller, System Reset
power management.
Controller
CSI
Parallel CSI
Multimedia
Peripherals
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
CSU
Central Security Unit
Security
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
RT1050 platform.
DAP
Debug Access Port
System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-M7
Core Platform.
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Modules list
Table 2. i.MX RT1050 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
DCDC
DCDC Converter
Analog
The DCDC module is used for generating power supply
for core logic. Main features are:
• Adjustable high efficiency regulator
• Supports 3.0 V input voltage for A0 and 3.3 V input
voltage for A1
• Supports nominal run and low power standby modes
• Supports at 0.9 ~ 1.3 V output in run mode
• Supports at 0.9 ~ 1.0 V output in standby mode
• Over current and over voltage detection
eDMA
enhanced Direct Memory
Access
System Control
Peripherals
There is an enhanced DMA (eDMA) engine and two
DMA_MUX.
• The eDMA is a 32 channel DMA engine, which is
capable of performing complex data transfers with
minimal intervention from a host processor.
• The DMA_MUX is capable of multiplexing up to 128
DMA request sources to the 32 DMA channels of
eDMA.
ENC
Quadrature
Encoder/Decoder
Timer Peripherals
The enhanced quadrature encoder/decoder module
provides interfacing capability to position/speed
sensors. There are five input signals: PHASEA,
PHASEB, INDEX, TRIGGER, and HOME. This module
is used to decode shaft position, revolution count, and
speed.
ENET
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
EWM
External Watchdog
Monitor
Timer Peripherals
The EWM modules is designed to monitor external
circuits, as well as the software flow. This provides a
back-up mechanism to the internal WDOG that can
reset the system. The EWM differs from the internal
WDOG in that it does not reset the system. The EWM,
if allowed to time-out, provides an independent trigger
pin that when asserted resets or places an external
circuit into a safe mode.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
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Modules list
Table 2. i.MX RT1050 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
FlexIO1
FlexIO2
Flexible Input/output
Connectivity and
Communications
The FlexIO is capable of supporting a wide range of
protocols including, but not limited to: UART, I2C, SPI,
I2S, camera interface, display interface, PWM
waveform generation, etc. The module can remain
functional when the chip is in a low power mode
provided the clock it is using remain active.
FlexPWM1
FlexPWM2
FlexPWM3
FlexPWM4
Pulse Width Modulation
Timer Peripherals
The pulse-width modulator (PWM) contains four PWM
sub-modules, each of which is set up to control a single
half-bridge power stage. Fault channel support is
provided. The PWM module can generate various
switching patterns, including highly sophisticated
waveforms.
FlexRAM
RAM
Memories
The i.MX RT1050 has 512 KB of on-chip RAM which
could be flexible allocated to I-TCM, D-TCM, and
on-chip RAM (OCRAM) in a 32 KB granularity. The
FlexRAM is the manager of the 512 KB on-chip RAM
array. Major functions of this blocks are: interfacing to
I-TCM and D-TCM of Arm core and OCRAM controller;
dynamic RAM arrays allocation for I-TCM, D-TCM, and
OCRAM.
FlexSPI
Quad Serial Peripheral
Interface
Connectivity and
Communications
FlexSPI acts as an interface to one or two external
serial flash devices, each with up to four bidirectional
data lines.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
GPT1
GPT2
General Purpose Timer
Timer Peripherals
Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
KPP
Keypad Port
Human Machine
Interfaces
The KPP is a 16-bit peripheral that can be used as a
keypad matrix interface or as general purpose
input/output (I/O). It supports 8 x 8 external key pad
matrix. Main features are:
• Multiple-key detection
• Long key-press detection
• Standby key-press detection
• Supports a 2-point and 3-point contact key matrix
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Modules list
Table 2. i.MX RT1050 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
LCDIF
LCD interface
Multimedia
Peripherals
The LCDIF is a general purpose display controller used
to drive a wide range of display devices varying in size
and capabilities. The LCDIF is designed to support
dumb (synchronous 24-bit Parallel RGB interface) and
smart (asynchronous parallel MPU interface) LCD
devices.
LPI2C1
LPI2C2
LPI2C3
LPI2C4
Low Power
Inter-integrated Circuit
Connectivity and
Communications
The LPI2C is a low power Inter-Integrated Circuit (I2C)
module that supports an efficient interface to an I2C bus
as a master.
The I2C provides a method of communication between
a number of external devices. More detailed
information, see Section 4.9.2, “LPI2C module timing
parameters.
LPSPI1
LPSPI2
LPSPI3
LPSPI4
Low Power Serial
Peripheral Interface
Connectivity and
Communications
The LPSPI is a low power Serial Peripheral Interface
(SPI) module that support an efficient interface to an
SPI bus as a master and/or a slave.
• It can continue operating while the chip is in stop
modes, if an appropriate clock is available
• Designed for low CPU overhead, with DMA off
loading of FIFO register access
LPUART1
LPUART2
LPUART3
LPUART4
LPUART5
LPUART6
LPUART7
LPUART8
UART Interface
Connectivity
Peripherals
Each of the UART modules support the following serial
data transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 5 Mbps.
MQS
Medium Quality Sound
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
PXP
Pixel Processing Pipeline
Multimedia
Peripherals
A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending, and
rotation. The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications.
QuadTimer1
QuadTimer2
QuadTimer3
QuadTimer4
QuadTimer
Timer Peripherals
The quad-timer provides four time channels with a
variety of controls affecting both individual and
multi-channel features.Specific features include
up/down count, cascading of counters, programmable
module, count once/repeated, counter preload,
compare registers with preload, shared use of input
signals, prescaler controls, independent
capture/compare, fault input control, programmable
input filters, and multi-channel synchronization.
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Modules list
Table 2. i.MX RT1050 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
ROMCP
ROM Controller with
Patch
Memories and
The ROMCP acts as an interface between the Arm
Memory Controllers advanced high-performance bus and the ROM. The
on-chip ROM is only used by the Cortex-M7 core during
boot up. Size of the ROM is 96 KB.
RTC OSC
Real Time Clock
Oscillator
Clock Sources and The RTC OSC provides the clock source for the
Control
Real-Time Clock module. The RTC OSC module, in
conjunction with an external crystal, generates a 32.678
kHz reference clock for the RTC.
RTWDOG
Watch Dog
Timer Peripherals
The RTWDG module is a high reliability independent
timer that is available for system to use. It provides a
safety feature to ensure software is executing as
planned and the CPU is not stuck in an infinite loop or
executing unintended code. If the WDOG module is not
serviced (refreshed) within a certain period, it resets the
MCU. Windowed refresh mode is supported as well.
SAI1
SAI2
SAI3
Synchronous Audio
Interface
Multimedia
Peripherals
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
SA-TRNG
Standalone True Random
Number Generator
Security
The SA-TRNG is hardware accelerator that generates
a 512-bit entropy as needed by an entropy consuming
module or by other post processing functions.
SEMC
Smart External Memory
Controller
Memory and
Memory Controller
The SEMC is a multi-standard memory controller
optimized for both high-performance and low pin-count.
It can support multiple external memories in the same
application with shared address and data pins. The
interface supported includes SDRAM, NOR Flash,
SRAM, and NAND Flash, as well as 8080 display
interface.
SJC
System JTAG Controller
System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX
RT1050 processors use JTAG port for production,
testing, and system debugging. In addition, the SJC
provides BSR (Boundary Scan Register) standard
support, which complies with IEEE 1149.1 and IEEE
1149.6 standards.
The JTAG port is accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX RT1050 SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
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Modules list
Table 2. i.MX RT1050 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SPDIF
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
Temp Monitor
Temperature Monitor
Analog
TSC
Touch Screen
Human Machine
Interfaces
USBO2
Universal Serial Bus 2.0
Connectivity
Peripherals
USBO2 (USB OTG1 and USB OTG2) contains:
• Two high-speed OTG 2.0 modules with integrated
HS USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
Peripherals
i.MX RT1050 specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia
Card System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC
MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
WDOG1
WDOG2
Watch Dog
Timer Peripherals
The watchdog (WDOG) Timer supports two comparison
points during each counting period. Each of the
comparison points is configurable to evoke an interrupt
to the Arm core, and a second point evokes an external
event on the WDOG line.
XBAR
Cross BAR
Cross Trigger
Each crossbar switch is an array of muxes with shared
inputs. Each mux output provides one output of the
crossbar. The number of inputs and the number of
muxes/outputs are user configurable and registers are
provided to select which of the shared inputs are routed
to each output.
The temperature sensor implements a temperature
sensor/conversion function based on a
temperature-dependent voltage to time conversion.
With touch controller to support 4-wire and 5-wire
resistive touch panel.
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13
Modules list
3.1
Special signal considerations
Table 3 lists special signal considerations for the i.MX RT1050 processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, “Package information and contact
assignments.” Signal descriptions are provided in the i.MX RT1050 Reference Manual
(IMXRT1050_RM).
Table 3. Special signal considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
One general purpose differential high speed clock Input/output (LVDS I/O) is provided.
It can be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals.
See the i.MX RT1050 Reference Manual (IMX6ULRM) for details on the respective clock trees.
Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding
CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of
the CLK1_N/P pairs may remain unconnected.
DCDC_PSWITCH
PAD is in DCDC_IN domain and connected the ground to bypass DCDC.
To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must
remain unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be @
,QWHUQDO6DPSOH&ORFN
Figure 17. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge, and FlexSPI controller sampling read data on the falling edge.
4.5.2.1.2
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in SDR mode:
• A1 - Memory generates both read data and read strobe on SCK rising edge (or falling
edge)
• A2 - Memory generates read data on SCK falling edge and generates read strobe on
SCK rising edgeSCK rising edge
Table 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1)
Value
Symbol
Parameter
Unit
Min
Max
Frequency of operation
—
166
MHz
TSCKD
Time from SCK to data valid
—
—
ns
TSCKDQS
Time from SCK to DQS
—
—
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
-2
2
ns
6&.
76&.'
76&.'
6,2> @
76&.'46
76&.'46
'46
Figure 18. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1)
i.MX RT1050 Crossover Processors for Industrial Products, Rev. 1, 03/2018
NXP Semiconductors
43
Electrical characteristics
NOTE
Timing shown is based on the memory generating read data and read strobe
on the SCK rising edge. The FlexSPI controller samples read data on the
DQS falling edge.
Table 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2)
Value
Symbol
Parameter
Unit
Min
Max
Frequency of operation
—
166
MHz
TSCKD
Time from SCK to data valid
—
—
ns
TSCKDQS
Time from SCK to DQS
—
—
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
-2
2
ns
6&.
76&.'
76&.'
76&.'
6,2> @
76&.'46
76&.'46
76&.'46
'46
,QWHUQDO6DPSOH&ORFN
Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half cycle delayed DQS falling edge.
4.5.2.1.3
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 39. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
30
MHz
TIS
Setup time for incoming data
8.67
—
ns
TIH
Hold time for incoming data
0
—
ns
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Electrical characteristics
Table 40. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1
Symbol
Parameter
Min
Max
Unit
Frequency of operation
—
66
MHz
TIS
Setup time for incoming data
2
—
ns
TIH
Hold time for incoming data
1
—
ns
6&/.
7,6
7,+
7,6
7,+
6,2> @
,QWHUQDO6DPSOH&ORFN
Figure 20. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
4.5.2.1.4
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in DDR mode:
• B1 - Memory generates both read data and read strobe on SCK edge
• B2 - Memory generates read data on SCK edge and generates read strobe on SCK2
edge
Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
Symbol
Parameter
Min
Max
Unit
Frequency of operation
—
166
MHz
TSCKD
Time from SCK to data valid
—
—
ns
TSCKDQS
Time from SCK to DQS
—
—
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
-1
1
ns
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45
Electrical characteristics
6&.
76&.'
6,2> @
76&.'46
'46
Figure 21. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)
Symbol
Parameter
Min
Max
Unit
Frequency of operation
—
166
MHz
TSCKD
Time from SCK to data valid
—
—
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
-1
1
ns
6&.
76&.'
6,2> @
6&.
76&.'46
'46
Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)
4.5.2.2
FlexSPI output/write timing
The following sections describe output signal timing for the FlexSPI controller including control signals
and data outputs.
4.5.2.2.1
SDR mode
Table 43. FlexSPI output timing in SDR mode
Symbol
Parameter
Min
Max
Unit
Frequency of operation
—
1661
MHz
Tck
SCK clock period
6.0
—
ns
TDVO
Output data valid time
—
1
ns
TDHO
Output data hold time
-1
—
ns
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Table 43. FlexSPI output timing in SDR mode (continued)
Symbol
Parameter
Min
Max
Unit
TCSS
Chip select output setup time
3 x TCK - 1
—
ns
TCSH
Chip select output hold time
3 x TCK + 2
—
ns
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1050 Reference Manual (IMXRT1050_RM) for more details.
6&.
7&66
7&6+
7&.
&6
7'92
7'92
6,2> @
7'+2
7'+2
Figure 23. FlexSPI output timing in SDR mode
4.5.2.2.2
DDR mode
Table 44. FlexSPI output timing in DDR mode
Symbol
Parameter
Min
Max
Unit
Frequency of operation1
—
166
MHz
Tck
SCK clock period
6.0
—
ns
TDVO
Output data valid time
—
2.2
ns
TDHO
Output data hold time
0.8
—
ns
TCSS
Chip select output setup time
3 x TCK / 2 - 0.7
—
ns
TCSH
Chip select output hold time
3 x TCK / 2 + 0.8 —
ns
1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1050 Reference Manual (IMXRT1050_RM) for more details.
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47
Electrical characteristics
6&.
7&66
7&.
7&6+
&6
7'92
7'92
6,2> @
7'+2
7'+2
Figure 24. FlexSPI output timing in DDR mode
4.6
Display and graphics
The following sections provide information on display and graphic interfaces.
4.6.1
CMOS Sensor Interface (CSI) timing parameters
The following sections describe the CSI timing in gated and ungated clock modes.
4.6.1.0.1
Gated clock mode timing
Figure 25 and Figure 26 shows the gated clock mode timings for CSI, and Table 45 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC
(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P5
P6
CSI_PIXCLK
P3
P4
CSI_DATA[23:00]
Figure 25. CSI Gated clock mode—sensor data at falling edge, latch data at rising edge
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CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P6
P5
CSI_PIXCLK
P3
P4
CSI_DATA[23:00]
Figure 26. CSI Gated clock mode—sensor data at rising edge, latch data at falling edge
Table 45. CSI gated clock mode timing parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
CSI_VSYNC to CSI_HSYNC time
tV2H
33.5
—
ns
P2
CSI_HSYNC setup time
tHsu
1
—
ns
P3
CSI DATA setup time
tDsu
1
—
ns
P4
CSI DATA hold time
tDh
1
—
ns
P5
CSI pixel clock high time
tCLKh
3.75
—
ns
P6
CSI pixel clock low time
tCLKl
3.75
—
ns
P7
CSI pixel clock frequency
fCLK
—
80
MHz
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Electrical characteristics
4.6.1.0.2
Ungated clock mode timing
Figure 27 shows the ungated clock mode timings of CSI, and Table 46 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are
used, and the CSI_HSYNC signal is ignored.
CSI_VSYNC
P1
P6
P4
P5
CSI_PIXCLK
P2
P3
CSI_DATA[23:00]
Figure 27. CSI ungated clock mode—sensor data at falling edge, latch data at rising edge
Table 46. CSI ungated clock mode timing parameters
ID
Parameter
Symbol
Min.
Max.
Units
tVSYNC
33.5
—
ns
P1
CSI_VSYNC to pixel clock time
P2
CSI DATA setup time
tDsu
1
—
ns
P3
CSI DATA hold time
tDh
1
—
ns
P4
CSI pixel clock high time
tCLKh
3.75
—
ns
P5
CSI pixel clock low time
tCLKl
3.75
—
ns
P6
CSI pixel clock frequency
fCLK
—
80
MHz
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
• Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
• Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
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Electrical characteristics
4.6.2
LCD Controller (LCDIF) timing parameters
Figure 28 shows the LCDIF timing and Table 47 lists the timing parameters.
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Figure 28. LCD timing
Table 47. LCD timing parameters
ID
Parameter
Symbol
Min
Max
Unit
tCLK(LCD)
—
75
MHz
L1
LCD pixel clock frequency
L2
LCD pixel clock high (falling edge capture)
tCLKH(LCD)
3
—
ns
L3
LCD pixel clock low (rising edge capture)
tCLKL(LCD)
3
—
ns
L4
LCD pixel clock high to data valid (falling edge capture)
td(CLKH-DV)
-1
1
ns
L5
LCD pixel clock low to data valid (rising edge capture)
td(CLKL-DV)
-1
1
ns
L6
LCD pixel clock high to control signal valid (falling edge capture)
td(CLKH-CTRLV)
-1
1
ns
L7
LCD pixel clock low to control signal valid (rising edge capture)
td(CLKL-CTRLV)
-1
1
ns
4.7
Audio
This section provide information about SAI/I2S and SPDIF.
4.7.1
SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
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Electrical characteristics
Table 48. Master mode SAI timing
Num
Characteristic
Min
Max
Unit
S1
SAI_MCLK cycle time
2 x tsys
—
ns
S2
SAI_MCLK pulse width high/low
40%
60%
MCLK period
S3
SAI_BCLK cycle time
4 x tsys
—
ns
S4
SAI_BCLK pulse width high/low
40%
60%
BCLK period
S5
SAI_BCLK to SAI_FS output valid
—
15
ns
S6
SAI_BCLK to SAI_FS output invalid
0
—
ns
S7
SAI_BCLK to SAI_TXD valid
—
15
ns
S8
SAI_BCLK to SAI_TXD invalid
0
—
ns
S9
SAI_RXD/SAI_FS input setup before SAI_BCLK
15
—
ns
S10
SAI_RXD/SAI_FS input hold after SAI_BCLK
0
—
ns
Figure 29. SAI timing—Master modes
Table 49. Slave mode SAI timing
Num
Characteristic
Min
Max
Unit
S11
SAI_BCLK cycle time (input)
4 x tsys
—
ns
S12
SAI_BCLK pulse width high/low (input)
40%
60%
BCLK period
S13
SAI_FS input setup before SAI_BCLK
10
—
ns
S14
SAI_FA input hold after SAI_BCLK
2
—
ns
S15
SAI_BCLK to SAI_TXD/SAI_FS output valid
—
20
ns
S16
SAI_BCLK to SAI_TXD/SAI_FS output invalid
0
—
ns
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Table 49. Slave mode SAI timing
Num
Characteristic
Min
Max
Unit
S17
SAI_RXD setup before SAI_BCLK
10
—
ns
S18
SAI_RXD hold after SAI_BCLK
2
—
ns
Figure 30. SAI timing—Slave mode
4.7.2
SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 50 and Figure 31 and Figure 32 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 50. SPDIF timing parameters
Timing Parameter Range
Characteristics
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
SPDIF_OUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIF_OUT1 output (Load = 30pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
40.0
—
Modulating Rx clock (SPDIF_SR_CLK) period
srckp
ns
ns
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Electrical characteristics
Table 50. SPDIF timing parameters (continued)
Timing Parameter Range
Characteristics
Symbol
Unit
Min
Max
SPDIF_SR_CLK high period
srckph
16.0
—
ns
SPDIF_SR_CLK low period
srckpl
16.0
—
ns
Modulating Tx clock (SPDIF_ST_CLK) period
stclkp
40.0
—
ns
SPDIF_ST_CLK high period
stclkph
16.0
—
ns
SPDIF_ST_CLK low period
stclkpl
16.0
—
ns
srckp
srckpl
SPDIF_SR_CLK
srckph
VM
VM
(Output)
Figure 31. SPDIF_SR_CLK timing diagram
stclkp
stclkpl
SPDIF_ST_CLK
VM
stclkph
VM
(Input)
Figure 32. SPDIF_ST_CLK timing diagram
4.8
Analog
The following sections provide information about analog interfaces.
4.8.1
DCDC
Table 51 introduces the DCDC electrical specifications.
Table 51. DCDC electrical specifications
Mode
Buck mode, one output
Notes
Input voltage
2.9 V (A0);
3.3 V (A1)
Min = 2.8 V
Max = 3.0 V (A0) and 3.6 V A1)
Output voltage
1.1 V
Configurable 0.8 ~ 1.575 V with 25 mV one
step in the Run mode
Max loading
500 mA
—
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Table 51. DCDC electrical specifications (continued)
Mode
Buck mode, one output
Notes
Loading in low power modes
200 A ~ 30 mA
—
Efficiency
90% max
@150 mA
Low power mode
Open loop mode
Ripple is about 15 mV in Run mode
Run mode
• Always continuous mode
• Support discontinuous mode
Configurable by register
Inductor
4.7 H
—
Capacitor
33 F
—
Over voltage protection
1.55 V
Detect VDDSOC, when the voltage is higher
than 1.6 V, shutdown DCDC.
Over Current protection
1A
Detect the peak current
• Run mode: when the current is larger than
1 A, shutdown DCDC.
Low DCDC_IN detection
2.6 V
Detect the DCDC_IN, when battery is lower
than 2.6 V, shutdown DCDC.
4.8.2
A/D converter
This section introduces information about A/D converter.
4.8.2.1
12-bit ADC electrical characteristics
The section provide information about 12-bit ADC electrical characteristics.
4.8.2.1.1
12-bit ADC operating conditions
Table 52. 12-bit ADC operating conditions
Characteristic
Supply voltage
Conditions
Symb
Typ1
Min
Max
Unit
Comment
Absolute
VDDA
3.0
-
3.6
V
—
Delta to VDD
(VDD-VDDA)2
VDDA
-100
0
100
mV
—
Ground voltage
Delta to VSS
(VSS-VSSAD)
VSSAD
-100
0
100
mV
—
Ref Voltage High
—
VDDA
1.13
VDDA
VDDA
V
—
Ref Voltage Low
—
VSS
VSSAD
VSSAD
VSSAD
V
—
Input Voltage
—
VADIN
VREFL
—
VREFH
V
—
Input Capacitance
8/10/12 bit modes
CADIN
—
1.5
2
pF
—
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Electrical characteristics
Table 52. 12-bit ADC operating conditions (continued)
Characteristic
Input Resistance
Analog Source
Resistance
Conditions
ADLPC=0, ADHSC=1
Symb
RADIN
Typ1
Min
Max
Unit
Comment
—
5
7
kohms
—
ADLPC=0, ADHSC=0
—
12.5
15
kohms
—
ADLPC=1, ADHSC=0
—
25
30
kohms
—
RAS
12 bit mode fADCK =
40MHz ADLSMP=0,
ADSTS=10, ADHSC=1
—
—
1
kohms
Tsamp=150
ns
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
ADC Conversion Clock ADLPC=0, ADHSC=1
Frequency
12 bit mode
fADCK
4
—
40
MHz
—
ADLPC=0, ADHSC=0
12 bit mode
4
—
30
MHz
—
ADLPC=1, ADHSC=0
12 bit mode
4
—
20
MHz
—
1
Typical values assume VDDAD = 3.0 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential differences
Figure 33. 12-bit ADC input impedance equivalency diagram
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12-bit ADC characteristics
Table 53. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD)
Characteristic
Supply Current
Conditions1
ADLPC=1,
ADHSC=0
Symb
IDDA
Typ2
Min
—
350
ADLPC=0,
ADHSC=0
460
ADLPC=0,
ADHSC=1
750
Max
Unit
Comment
—
µA
ADLSMP=0
ADSTS=10 ADCO=1
Supply Current
Stop, Reset, Module
Off
IDDA
—
1.4
2
µA
—
ADC Asynchronous
Clock Source
ADHSC=0
fADACK
—
10
—
MHz
tADACK = 1/fADACK
—
20
—
—
2
—
cycles
—
Sample Cycles
ADHSC=1
ADLSMP=0,
ADSTS=00
Csamp
ADLSMP=0,
ADSTS=01
4
ADLSMP=0,
ADSTS=10
6
ADLSMP=0,
ADSTS=11
8
ADLSMP=1,
ADSTS=00
12
ADLSMP=1,
ADSTS=01
16
ADLSMP=1,
ADSTS=10
20
ADLSMP=1,
ADSTS=11
24
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Table 53. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)
Characteristic
Conversion Cycles
Conversion Time
Total Unadjusted
Error
Differential
Non-Linearity
Conditions1
ADLSMP=0
ADSTS=00
Symb
Cconv
Typ2
Min
—
28
ADLSMP=0
ADSTS=01
30
ADLSMP=0
ADSTS=10
32
ADLSMP=0
ADSTS=11
34
ADLSMP=1
ADSTS=00
38
ADLSMP=1
ADSTS=01
42
ADLSMP=1
ADSTS=10
46
ADLSMP=1,
ADSTS=11
50
ADLSMP=0
ADSTS=00
Tconv
—
0.7
ADLSMP=0
ADSTS=01
0.75
ADLSMP=0
ADSTS=10
0.8
ADLSMP=0
ADSTS=11
0.85
ADLSMP=1
ADSTS=00
0.95
ADLSMP=1
ADSTS=01
1.05
ADLSMP=1
ADSTS=10
1.15
ADLSMP=1,
ADSTS=11
1.25
12 bit mode
Comment
cycles
—
—
µs
Fadc=40 MHz
LSB
1 LSB =
(VREFH VREFL)/2
N
AVGE = 1, AVGS = 11
LSB
AVGE = 1, AVGS = 11
3.4
—
10 bit mode
—
1.5
—
8 bit mode
—
1.2
—
—
0.76
—
10bit mode
—
0.36
—
8 bit mode
—
0.14
—
DNL
Unit
—
—
12 bit mode
TUE
Max
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Table 53. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)
Conditions1
Characteristic
Integral Non-Linearity 12 bit mode
Zero-Scale Error
Typ2
Max
2.78
—
10bit mode
—
0.61
—
8 bit mode
—
0.14
—
—
-1.14
—
10bit mode
—
-0.25
—
8 bit mode
—
-0.19
—
—
-1.06
—
10bit mode
—
-0.03
—
8 bit mode
—
-0.02
—
10.7
—
12 bit mode
INL
Min
—
12 bit mode
Full-Scale Error
Symb
EZS
EFS
Effective Number of
Bits
12 bit mode
ENOB
10.1
Signal to Noise plus
Distortion
See ENOB
SINAD
SINAD = 6.02 x ENOB + 1.76
1
2
Unit
Comment
LSB
AVGE = 1, AVGS = 11
LSB
AVGE = 1, AVGS = 11
LSB
AVGE = 1, AVGS = 11
Bits
AVGE = 1, AVGS = 11
dB
AVGE = 1, AVGS = 11
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE
The ADC electrical spec would be met with the calibration enabled
configuration.
4.8.3
ACMP
Table 54 lists the ACMP electrical specifications.
Table 54. Comparator and 6-bit DAC electrical specifications
Symbol
Description
VDD
Supply voltage
IDDHS
Min.
3.0
Typ.
Max.
Unit
—
3.6
V
Supply current, High-speed mode —
(EN = 1, PMODE = 1)
347
—
A
IDDLS
Supply current, Low-speed mode
(EN = 1, PMODE = 0)
—
42
—
A
VAIN
Analog input voltage
VSS
—
VDD
V
VAIO
Analog input offset voltage
—
—
21
mV
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Electrical characteristics
Table 54. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
VH
Description
Min.
Typ.
Max.
Analog comparator hysteresis1
Unit
mV
• CR0[HYSTCTR] = 00
—
1
2
• CR0[HYSTCTR] = 01
—
21
54
• CR0[HYSTCTR] = 10
—
42
108
• CR0[HYSTCTR] = 11
—
64
184
VCMPOH
Output high
VDD - 0.5
—
—
V
VCMPOI
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed
mode (EN = 1, PMODE = 1)2
—
25
40
ns
tDLS
Propagation delay, low-speed
mode (EN = 1, PMODE = 0)2
—
50
90
ns
tDInit
Analog comparator initialization
delay3
—
1.5
—
s
IDAC6b
6-bit DAC current adder (enabled) —
5
—
A
RDAC6b
6-bit DAC reference inputs
—
VDD
—
V
INLDAC6b
6-bit DAC integral non-linearity
-0.3
—
0.3
LSB4
DNLDAC6b
6-bit DAC differential non-linearity -0.15
—
0.15
LSB4
1
Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V in high speed mode.
Signal swing is 100 mV.
3 Comparator initialization delay is defined as the time between software writes to the enable comparator module and the
comparator output setting to a stable level.
4 1 LSB = V
reference / 64
2
4.9
Communication interfaces
The following sections provide the information about communication interfaces.
4.9.1
LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables provide timing
characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input
signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
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Table 55. LPSPI Master mode timing
Number
Symbol
1
fOP
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Description
Min.
Max.
Units
Note
fperiph / 2048
fperiph / 2
Hz
1
2 x tperiph
2048 x tperiph
ns
2
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tperiph - 30
1024 x tperiph
ns
—
Data setup time (inputs)
18
—
ns
—
tHI
Data hold time (inputs)
0
—
ns
—
8
tV
Data valid (after SPSCK edge(
—
15
ns
—
9
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
tFI
Rise time input
Fall time input
—
tperiph - 25
ns
—
11
tRO
tFO
Rise time output
Fall time output
—
25
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
1
Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be
guaranteed this limit is not exceeded.
2 t
periph = 1 / fperiph
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Figure 34. LPSPI Master mode timing (CPHA = 0)
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Electrical characteristics
66
287387
636&.
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287387
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Figure 35. LPSPI Master mode timing (CPHA = 1)
Table 56. LPSPI Slave mode timing
Number
Symbol
1
fOP
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Description
Min.
Max.
Units
Note
0
fperiph / 2
Hz
1
4 x tperiph
—
ns
2
Enable lead time
1
—
tperiph
—
Enable lag time
1
—
tperiph
—
tperiph - 30
—
ns
—
Data setup time (inputs)
2.5
—
ns
—
tHI
Data hold time (inputs)
3.5
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tV
Data valid (after SPSCK edge)
—
31
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
tFI
Rise time input
Fall time input
—
tperiph - 25
ns
—
13
tRO
tFO
Rise time input
Fall time input
—
25
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
1
Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be
guaranteed this limit is not exceeded.
2 t
periph = 1 / fperiph
3
Time to data active from high-impedance state
4
Hold time to high-impedance state
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66
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636&.
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,1387
636&.
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66
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Figure 37. LPSPI Slave mode timing (CPHA = 1)
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Electrical characteristics
4.9.2
LPI2C module timing parameters
This section describes the timing parameters of the LPI2C module.
Table 57. LPI2C module timing parameters
Symbol
fSCL
1
2
Description
SCL clock frequency
Min
Max
Standard mode (Sm)
0
100
Fast mode (Fm)
0
400
Fast mode Plus (Fm+)
0
1000
Ultra Fast mode (UFm)
0
5000
High speed mode (Hs-mode)
0
3400
Unit
kHz
Notes
1, 2
Hs-mode is only supported in slave mode.
See General switching specifications.
4.9.3
Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single
Data Rate) timing, eMMC4.4/4.41/4.5 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.9.3.1
SD/eMMC4.3 (single data rate) AC timing
Figure 38 depicts the timing of SD/eMMC4.3, and Table 58 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 38. SD/eMMC4.3 timing
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Table 58. SD/eMMC4.3 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Clock Frequency (Low Speed)
fPP1
0
400
kHz
Clock Frequency (SD/SDIO Full Speed/High Speed)
fPP2
0
25/50
MHz
Clock Frequency (MMC Full Speed/High Speed)
fPP3
0
20/52
MHz
Clock Frequency (Identification Mode)
fOD
100
400
kHz
SD2
Clock Low Time
tWL
7
—
ns
SD3
Clock High Time
tWH
7
—
ns
SD4
Clock Rise Time
tTLH
—
3
ns
SD5
Clock Fall Time
tTHL
—
3
ns
3.6
ns
Card Input Clock
SD1
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6
uSDHC Output Delay
tOD
-6.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD7
uSDHC Input Setup Time
tISU
2.5
—
ns
SD8
uSDHC Input Hold Time4
tIH
1.5
—
ns
1
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
2
4.9.3.2
eMMC4.4/4.41 (dual data rate) AC timing
Figure 39 depicts the timing of eMMC4.4/4.41. Table 59 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
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SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
......
Figure 39. eMMC4.4/4.41 timing
Table 59. eMMC4.4/4.41 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency (eMMC4.4/4.41 DDR)
fPP
0
52
MHz
SD1
Clock Frequency (SD3.0 DDR)
fPP
0
50
MHz
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2
uSDHC Output Delay
tOD
2.5
7.1
ns
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD3
uSDHC Input Setup Time
tISU
1.7
—
ns
SD4
uSDHC Input Hold Time
tIH
1.5
—
ns
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4.9.3.3
SDR50/SDR104 AC timing
Figure 40 depicts the timing of SDR50/SDR104, and Table 60 lists the SDR50/SDR104 timing
characteristics.
6'
6'
6'
6&.
6'6'
ELWRXWSXWIURPX6'+&WRFDUG
6'
6'
ELWLQSXWIURPFDUGWRX6'+&
6'
Figure 40. SDR50/SDR104 timing
Table 60. SDR50/SDR104 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency Period
tCLK
5.0
—
ns
SD2
Clock Low Time
tCL
0.46 x tCLK
0.54 x tCLK
ns
SD3
Clock High Time
tCH
0.46 x tCLK
0.54 x tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4
uSDHC Output Delay
tOD
–3
1
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
SD5
uSDHC Output Delay
tOD
–1.6
1
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD6
uSDHC Input Setup Time
tISU
2.5
—
ns
SD7
uSDHC Input Hold Time
tIH
1.5
—
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
SD8
1Data
Card Output Data Window
tODW
0.5 x tCLK
—
ns
window in SDR104 mode is variable.
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4.9.3.4
HS200 mode timing
Figure 41 depicts the timing of HS200 mode, and Table 61 lists the HS200 timing characteristics.
6'
6'
6'
6&.
6'6'
ELWRXWSXWIURPX6'+&WRH00&
ELWLQSXWIURPH00&WRX6'+&
6'
Figure 41. HS200 mode timing
Table 61. HS200 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency Period
tCLK
5.0
—
ns
SD2
Clock Low Time
tCL
0.46 x tCLK
0.54 x tCLK
ns
SD3
Clock High Time
tCH
0.46 x tCLK
0.54 x tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
uSDHC Output Delay
SD5
tOD
–1.6
0.74
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
Card Output Data Window
SD8
1HS200
4.9.3.5
tODW
0.5 x tCLK
—
ns
is for 8 bits while SDR104 is for 4 bits.
Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 21,
"Single voltage GPIO DC parameters," on page 30.
4.9.4
Ethernet controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
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4.9.4.1
ENET MII mode timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.9.4.1.1
MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
Figure 42 shows MII receive signal timings. Table 62 describes the timing parameters (M1–M4) shown in
the figure.
M3
ENET_RX_CLK (input)
M4
ENET_RX_DATA3,2,1,0
(inputs)
ENET_RX_EN
ENET_RX_ER
M1
M2
Figure 42. MII receive signal timing diagram
Table 62. MII receive signal timing
Characteristic1
ID
Min.
Max.
Unit
M1
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5
—
ns
M2
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5
—
ns
M3
ENET_RX_CLK pulse width high
35%
65%
ENET_RX_CLK period
M4
ENET_RX_CLK pulse width low
35%
65%
ENET_RX_CLK period
1
ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
4.9.4.1.2
MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
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Figure 43 shows MII transmit signal timings. Table 63 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET_TX_CLK (input)
M5
M8
ENET_TX_DATA3,2,1,0
(outputs)
ENET_TX_EN
ENET_TX_ER
M6
Figure 43. MII transmit signal timing diagram
Table 63. MII transmit signal timing
Characteristic1
ID
Min.
Max.
Unit
M5
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
5
—
ns
M6
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
—
20
ns
M7
ENET_TX_CLK pulse width high
35%
65%
ENET_TX_CLK period
M8
ENET_TX_CLK pulse width low
35%
65%
ENET_TX_CLK period
1 ENET_TX_EN,
4.9.4.1.3
ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)
Figure 44 shows MII asynchronous input timings. Table 64 describes the timing parameter (M9) shown in
the figure.
ENET_CRS, ENET_COL
M9
Figure 44. MII asynchronous inputs timing diagram
Table 64. MII asynchronous inputs signal timing
ID
1
M9
1
Characteristic
ENET_CRS to ENET_COL minimum pulse width
Min.
Max.
Unit
1.5
—
ENET_TX_CLK period
ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
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Electrical characteristics
4.9.4.1.4
MII serial management channel timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 45 shows MII asynchronous input timings. Table 65 describes the timing parameters (M10–M15)
shown in the figure.
M14
M15
ENET_MDC (output)
M10
ENET_MDIO (output)
M11
ENET_MDIO (input)
M12
M13
Figure 45. MII serial management channel timing diagram
Table 65. MII serial management channel timing
ID
Characteristic
Min.
Max.
Unit
M10
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
0
—
ns
M11
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
—
5
ns
M12
ENET_MDIO (input) to ENET_MDC rising edge setup
18
—
ns
M13
ENET_MDIO (input) to ENET_MDC rising edge hold
0
—
ns
M14
ENET_MDC pulse width high
40%
60%
ENET_MDC period
M15
ENET_MDC pulse width low
40%
60%
ENET_MDC period
4.9.4.2
RMII mode timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.
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Figure 46 shows RMII mode timings. Table 66 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20
M21
Figure 46. RMII mode signal timing diagram
Table 66. RMII signal timing
ID
Characteristic
Min.
Max.
Unit
M16
ENET_CLK pulse width high
35%
65%
ENET_CLK period
M17
ENET_CLK pulse width low
35%
65%
ENET_CLK period
M18
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
4
—
ns
M19
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
—
13
ns
M20
ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER
to ENET_CLK setup
2
—
ns
M21
ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER
hold
2
—
ns
4.9.5
Flexible Controller Area Network (FLEXCAN) AC electrical
specifications
Please refer to Section 4.3.2.1, “General purpose I/O AC parameters.
4.9.6
LPUART electrical specifications
Please refer to Section 4.3.2.1, “General purpose I/O AC parameters.
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Electrical characteristics
4.9.7
USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG with the following amendments.
• USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
• Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
— Portable device only
4.10
Timers
This section provide information on timers.
4.10.1
Pulse Width Modulator (PWM) characteristics
This section describes the electrical information of the PWM.
Table 67. PWM timing parameters
Parameter
Symbo
Min
Typ
Max
Unit
PWM Clock Frequency
—
80
—
120
MHz
Power-up Time
tpu
—
25
—
s
4.10.2
Quad timer timing
Table 68 listed the timing parameters.
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Electrical characteristics
Table 68. Quad timer timing
Symbo
Min1
Max
Unit
TIN
2T + 6
—
ns
Timer input high/low period
TINHL
1T + 3
—
ns
Timer output period
TOUT
33
—
ns
TOUTHL
16.7
—
ns
Characteristic
Timer input period
Timer output high/low period
1
See Figure
T = clock cycle. For 60 MHz operation, T = 16.7 ns.
4IMER)NPUTS
4 ).
4 ).(,
4 ).(,
4 /54
4 /54(,
4 /54(,
4IMER/UTPUTS
Figure 47. Quad timer timing
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Boot mode configuration
5
Boot mode configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot mode configuration pins
Table 69 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1050
Fuse Map document and the System Boot chapter in i.MX RT1050 Reference Manual (IMXRT1050_RM).
Table 69. Fuses and associated pins used for boot
Pad
5.2
Default setting on reset
eFuse name
GPIO_AD_B0_04
100 K pull-down
BOOT_MODE0
GPIO_AD_B0_05
100 K pull-down
BOOT_MODE1
GPIO_B0_04
100 K pull-down
BT_CFG[0]
GPIO_B0_05
100 K pull-down
BT_CFG[1]
GPIO_B0_06
100 K pull-down
BT_CFG[2]
GPIO_B0_07
100 K pull-down
BT_CFG[3]
GPIO_B0_08
100 K pull-down
BT_CFG[4]
GPIO_B0_09
100 K pull-down
BT_CFG[5]
GPIO_B0_10
100 K pull-down
BT_CFG[6]
GPIO_B0_11
100 K pull-down
BT_CFG[7]
GPIO_B0_12
100 K pull-down
BT_CFG[8]
GPIO_B0_13
100 K pull-down
BT_CFG[9]
GPIO_B0_14
100 K pull-down
BT_CFG[10]
GPIO_B0_15
100 K pull-down
BT_CFG[11]
Details
Boot Options, Pin value overrides
fuse settings for BT_FUSE_SEL =
‘0’. Signal Configuration as Fuse
Override Input at Power Up.
These are special I/O lines that
control the boot up configuration
during product development. In
production, the boot configuration
can be controlled by fuses.
Boot device interface allocation
The following tables list the interfaces that can be used by the boot process in accordance with the specific
boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 70. Boot trough NAND
PAD Name
IO Function
ALT
Comments
GPIO_EMC_00
semc.DATA[0]
ALT 0
—
GPIO_EMC_01
semc.DATA[1]
ALT 0
—
GPIO_EMC_02
semc.DATA[2]
ALT 0
—
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Boot mode configuration
Table 70. Boot trough NAND
GPIO_EMC_03
semc.DATA[3]
ALT 0
—
GPIO_EMC_04
semc.DATA[4]
ALT 0
—
GPIO_EMC_05
semc.DATA[5]
ALT 0
—
GPIO_EMC_06
semc.DATA[6]
ALT 0
—
GPIO_EMC_07
semc.DATA[7]
ALT 0
—
GPIO_EMC_30
semc.DATA[8]
ALT 0
—
GPIO_EMC_31
semc.DATA[9]
ALT 0
—
GPIO_EMC_32
semc.DATA[10]
ALT 0
—
GPIO_EMC_33
semc.DATA[11]
ALT 0
—
GPIO_EMC_34
semc.DATA[12]
ALT 0
—
GPIO_EMC_35
semc.DATA[13]
ALT 0
—
GPIO_EMC_36
semc.DATA[14]
ALT 0
—
GPIO_EMC_37
semc.DATA[15]
ALT 0
—
GPIO_EMC_18
semc.ADDR[9]
ALT 0
—
GPIO_EMC_19
semc.ADDR[11]
ALT 0
—
GPIO_EMC_20
semc.ADDR[12]
ALT 0
—
GPIO_EMC_22
semc.BA1
ALT 0
—
GPIO_EMC_41
semc.CSX[0]
ALT 0
—
Table 71. Boot trough NOR
PAD Name
IO Function
ALT
Comments
GPIO_EMC_00
semc.DATA[0]
ALT 0
—
GPIO_EMC_01
semc.DATA[1]
ALT 0
—
GPIO_EMC_02
semc.DATA[2]
ALT 0
—
GPIO_EMC_03
semc.DATA[3]
ALT 0
—
GPIO_EMC_04
semc.DATA[4]
ALT 0
—
GPIO_EMC_05
semc.DATA[5]
ALT 0
—
GPIO_EMC_06
semc.DATA[6]
ALT 0
—
GPIO_EMC_07
semc.DATA[7]
ALT 0
—
GPIO_EMC_30
semc.DATA[8]
ALT 0
—
GPIO_EMC_31
semc.DATA[9]
ALT 0
—
GPIO_EMC_32
semc.DATA[10]
ALT 0
—
GPIO_EMC_33
semc.DATA[11]
ALT 0
—
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Boot mode configuration
Table 71. Boot trough NOR
GPIO_EMC_34
semc.DATA[12]
ALT 0
—
GPIO_EMC_35
semc.DATA[13]
ALT 0
—
GPIO_EMC_36
semc.DATA[14]
ALT 0
—
GPIO_EMC_37
semc.DATA[15]
ALT 0
—
GPIO_EMC_09
semc.ADDR[0]
ALT 0
—
GPIO_EMC_10
semc.ADDR[1]
ALT 0
—
GPIO_EMC_11
semc.ADDR[2]
ALT 0
—
GPIO_EMC_12
semc.ADDR[3]
ALT 0
—
GPIO_EMC_13
semc.ADDR[4]
ALT 0
—
GPIO_EMC_14
semc.ADDR[5]
ALT 0
—
GPIO_EMC_15
semc.ADDR[6]
ALT 0
—
GPIO_EMC_16
semc.ADDR[7]
ALT 0
—
GPIO_EMC_19
semc.ADDR[11]
ALT 0
—
GPIO_EMC_20
semc.ADDR[12]
ALT 0
—
GPIO_EMC_21
semc.BA0
ALT 0
—
GPIO_EMC_22
semc.BA1
ALT 0
—
GPIO_EMC_41
semc.CSX[0]
ALT 0
—
Table 72. Boot through FlexSPI
PAD Name
IO Function
Mux Mode
Comments
GPIO_SD_B1_00
flexspi.B_DATA[3]
ALT 1
—
GPIO_SD_B1_01
flexspi.B_DATA[2]
ALT 1
—
GPIO_SD_B1_02
flexspi.B_DATA[1]
ALT 1
—
GPIO_SD_B1_03
flexspi.B_DATA[0]
ALT 1
—
GPIO_SD_B1_04
flexspi.B_SCLK
ALT 1
—
GPIO_SD_B0_05
flexspi.B_DQS
ALT 4
—
GPIO_SD_B0_04
flexspi.B_SS0_B
ALT 4
—
GPIO_SD_B0_01
flexspi.B_SS1_B
ALT 6
—
GPIO_SD_B1_05
flexspi.A_DQS
ALT 1
—
GPIO_SD_B1_06
flexspi.A_SS0_B
ALT 1
—
GPIO_SD_B0_00
flexspi.A_SS1_B
ALT 6
—
GPIO_SD_B1_07
flexspi.A_SCLK
ALT 1
—
GPIO_SD_B1_08
flexspi.A_DATA[0]
ALT 1
—
GPIO_SD_B1_09
flexspi.A_DATA[1]
ALT 1
—
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Boot mode configuration
Table 72. Boot through FlexSPI (continued)
PAD Name
IO Function
Mux Mode
Comments
GPIO_SD_B1_10
flexspi.A_DATA[2]
ALT 1
—
GPIO_SD_B1_11
flexspi.A_DATA[3]
ALT 1
—
Table 73. Boot through SD1
PAD Name
IO Function
Mux Mode
Comments
GPIO_SD_B0_00
usdhc1.CMD
ALT 0
—
GPIO_SD_B0_01
usdhc1.CLK
ALT 0
—
GPIO_SD_B0_02
usdhc1.DATA0
ALT 0
—
GPIO_SD_B0_03
usdhc1.DATA1
ALT 0
—
GPIO_SD_B0_04
usdhc1.DATA2
ALT 0
—
GPIO_SD_B0_05
usdhc1.DATA3
ALT 0
—
Table 74. Boot through SD2
PAD Name
IO Function
Mux Mode
Comments
GPIO_SD_B1_00
usdhc2.DATA3
ALT 0
—
GPIO_SD_B1_01
usdhc2.DATA2
ALT 0
—
GPIO_SD_B1_02
usdhc2.DATA1
ALT 0
—
GPIO_SD_B1_03
usdhc2.DATA0
ALT 0
—
GPIO_SD_B1_04
usdhc2.CLK
ALT 0
—
GPIO_SD_B1_05
usdhc2.CMD
ALT 0
—
GPIO_SD_B1_06
usdhc2.RESET_B
ALT 0
—
GPIO_SD_B1_08
usdhc2.DATA4
ALT 0
—
GPIO_SD_B1_09
usdhc2.DATA5
ALT 0
—
GPIO_SD_B1_10
usdhc2.DATA6
ALT 0
—
GPIO_SD_B1_11
usdhc2.DATA7
ALT 0
—
Table 75. Boot through SPI-1
PAD Name
IO Function
Mux Mode
Comments
GPIO_SD_B0_00
lpspi1.SCK
ALT 4
—
GPIO_SD_B0_02
lpspi1.SDO
ALT 4
—
GPIO_SD_B0_03
lpspi1.SDI
ALT 4
—
GPIO_SD_B0_01
lpspi1.PCS0
ALT 4
—
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Boot mode configuration
Table 76. Boot through SPI-2
PAD Name
IO Function
Mux Mode
Comments
GPIO_SD_B1_07
lpspi2.SCK
ALT 4
—
GPIO_SD_B1_08
lpspi2.SDO
ALT 4
—
GPIO_SD_B1_09
lpspi2.SDI
ALT 4
—
GPIO_SD_B1_06
lpspi2.PCS0
ALT 4
—
Table 77. Boot through SPI-3
PAD Name
IO Function
Mux Mode
Comments
GPIO_AD_B0_00
lpspi3.SCK
ALT 7
—
GPIO_AD_B0_01
lpspi3.SDO
ALT 7
—
GPIO_AD_B0_02
lpspi3.SDI
ALT 7
—
GPIO_SD_B0_03
lpspi3.PCS0
ALT 7
—
Table 78. Boot through SPI-4
PAD Name
IO Function
Mux Mode
Comments
GPIO_B0_03
lpspi4.SCK
ALT 3
—
GPIO_B0_02
lpspi4.SDO
ALT 3
—
GPIO_B0_01
lpspi4.SDI
ALT 3
—
GPIO_B0_00
lpspi4.PCS0
ALT 3
—
Table 79. Boot through UART1
PAD Name
IO Function
Mux Mode
Comments
GPIO_AD_B0_12
lpuart1.TX
ALT 2
—
GPIO_AD_B0_13
lpuart1.RX
ALT 2
—
GPIO_AD_B0_14
lpuart1.CTS_B
ALT 2
—
GPIO_AD_B0_15
lpuart1.RTS_B
ALT 2
—
Table 80. Boot through UART2
PAD Name
IO Function
Mux Mode
Comments
GPIO_AD_B1_00
lpuart2.CTS_B
ALT 2
—
GPIO_AD_B1_01
lpuart2.RTS_B
ALT 2
—
GPIO_AD_B1_02
lpuart2.TX
ALT 2
—
GPIO_AD_B1_03
lpuart2.RX
ALT 2
—
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Package information and contact assignments
6
Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
6.1.1
10 x 10 mm package information
10 x 10 mm, 0.65 mm pitch, ball matrix
Figure 48 shows the top, bottom, and side views of the 10 x 10 mm MAPBGA package.
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Package information and contact assignments
Figure 48. 10 x 10 mm BGA, case x package top, bottom, and side Views
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Package information and contact assignments
6.1.2
10 x 10 mm supplies contact assignments and functional contact
assignments
Table 81 shows the device connection list for ground, sense, and reference contact signals.
Table 81. 10 x 10 mm supplies contact assignment
Supply Rail Name
Ball(s) Position(s)
Remark
DCDC_IN
L1, L2
—
DCDC_IN_Q
K4
—
DCDC_GND
N1, N2
—
DCDC_LP
M1, M2
—
DCDC_PSWITCH
K3
—
DCDC_SENSE
J5
—
GPANAIO
N10
—
NGND_KEL0
K9
—
NVCC_EMC
E6, F5
—
NVCC_GPIO
E9, F10, J10
—
NVCC_PLL
P10
—
NVCC_SD0
J6
—
NVCC_SD1
K5
—
VDDA_ADC_3P3
N14
—
VDD_HIGH_CAP
P8
—
VDD_HIGH_IN
P12
—
VDD_SNVS_CAP
M10
—
VDD_SNVS_IN
M9
—
VDD_SOC_IN
F6, F7, F8, F9, G6, G9, H6, H9, J9
—
VDD_USB_CAP
K8
—
VSS
A1, A14, B5, B10, E2, E13, G7, G8, H7, H8, J7, J8, K2, K13, L9, N5, N8, P1, P14
—
Table 82 shows an alpha-sorted list of functional contact assignments for the 10 x 10 mm package.
Table 82. 10 x 10 mm functional contact assignments
Default Setting
10 x 10
Ball
Power
Group
Ball
Type
CCM_CLK1_N
P13
—
CCM_CLK1_P
N13
—
Ball Name
Default
Mode
Default
Function
Input/
Output
Value
—
—
CCM_CLK1_N
—
—
—
—
CCM_CLK1_P
—
—
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Package information and contact assignments
Table 82. 10 x 10 mm functional contact assignments (continued)
GPIO_AD_B0_00
M14
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[0]
Input
Keeper
GPIO_AD_B0_01
H10
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[1]
Input
Keeper
GPIO_AD_B0_02
M11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[2]
Input
Keeper
GPIO_AD_B0_03
G11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[3]
Input
Keeper
GPIO_AD_B0_04
F11
NVCC_GPIO
Digital
GPIO
ALT0
SRC.BOOT.MODE[0]
Input
100 K PD
GPIO_AD_B0_05
G14
NVCC_GPIO
Digital
GPIO
ALT0
SRC.BOOT.MODE[1]
Input
100 K PD
GPIO_AD_B0_06
E14
NVCC_GPIO
Digital
GPIO
ALT0
JTAG.MUX.TMS
Input
47 K PU
GPIO_AD_B0_07
F12
NVCC_GPIO
Digital
GPIO
ALT0
JTAG.MUX.TCK
Input
47 K PU
GPIO_AD_B0_08
F13
NVCC_GPIO
Digital
GPIO
ALT0
JTAG.MUX.MOD
Input
100 K PU
GPIO_AD_B0_09
F14
NVCC_GPIO
Digital
GPIO
ALT0
JTAG.MUX.TDI
Input
47 K PU
GPIO_AD_B0_10
G13
NVCC_GPIO
Digital
GPIO
ALT0
JTAG.MUX.TDO
Input
Keeper
GPIO_AD_B0_11
G10
NVCC_GPIO
Digital
GPIO
ALT0
JTAG.MUX.TRSTB
Input
47 K PU
GPIO_AD_B0_12
K14
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[12]
Input
Keeper
GPIO_AD_B0_13
L14
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[13]
Input
Keeper
GPIO_AD_B0_14
H14
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[14]
Input
Keeper
GPIO_AD_B0_15
L10
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[15]
Input
Keeper
GPIO_AD_B1_00
J11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[16]
Input
Keeper
GPIO_AD_B1_01
K11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[17]
Input
Keeper
GPIO_AD_B1_02
L11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[18]
Input
Keeper
GPIO_AD_B1_03
M12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[19]
Input
Keeper
GPIO_AD_B1_04
L12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[20]
Input
Keeper
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Package information and contact assignments
Table 82. 10 x 10 mm functional contact assignments (continued)
GPIO_AD_B1_05
K12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[21]
Input
Keeper
GPIO_AD_B1_06
J12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[22]
Input
Keeper
GPIO_AD_B1_07
K10
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[23]
Input
Keeper
GPIO_AD_B1_08
H13
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[24]
Input
Keeper
GPIO_AD_B1_09
M13
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[25]
Input
Keeper
GPIO_AD_B1_10
L13
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[26]
Input
Keeper
GPIO_AD_B1_11
J13
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[27]
Input
Keeper
GPIO_AD_B1_12
H12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[28]
Input
Keeper
GPIO_AD_B1_13
H11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[29]
Input
Keeper
GPIO_AD_B1_14
G12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[30]
Input
Keeper
GPIO_AD_B1_15
J14
NVCC_GPIO
Digital
GPIO
ALT5
GPIO1.IO[31]
Input
Keeper
GPIO_B0_00
D7
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[0]
Input
Keeper
GPIO_B0_01
E7
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[1]
Input
Keeper
GPIO_B0_02
E8
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[2]
Input
Keeper
GPIO_B0_03
D8
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[3]
Input
Keeper
GPIO_B0_04
C8
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[4]
Input
Keeper
GPIO_B0_05
B8
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[5]
Input
Keeper
GPIO_B0_06
A8
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[6]
Input
Keeper
GPIO_B0_07
A9
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[7]
Input
Keeper
GPIO_B0_08
B9
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[8]
Input
Keeper
GPIO_B0_09
C9
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[9]
Input
Keeper
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Package information and contact assignments
Table 82. 10 x 10 mm functional contact assignments (continued)
GPIO_B0_10
D9
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[10]
Input
Keeper
GPIO_B0_11
A10
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[11]
Input
Keeper
GPIO_B0_12
C10
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[12]
Input
Keeper
GPIO_B0_13
D10
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[13]
Input
Keeper
GPIO_B0_14
E10
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[14]
Input
Keeper
GPIO_B0_15
E11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[15]
Input
Keeper
GPIO_B1_00
A11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[16]
Input
Keeper
GPIO_B1_01
B11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[17]
Input
Keeper
GPIO_B1_02
C11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[18]
Input
Keeper
GPIO_B1_03
D11
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[19]
Input
Keeper
GPIO_B1_04
E12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[20]
Input
Keeper
GPIO_B1_05
D12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[21]
Input
Keeper
GPIO_B1_06
C12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[22]
Input
Keeper
GPIO_B1_07
B12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[23]
Input
Keeper
GPIO_B1_08
A12
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[24]
Input
Keeper
GPIO_B1_09
A13
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[25]
Input
Keeper
GPIO_B1_10
B13
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[26]
Input
Keeper
GPIO_B1_11
C13
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[27]
Input
Keeper
GPIO_B1_12
D13
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[28]
Input
Keeper
GPIO_B1_13
D14
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[29]
Input
Keeper
GPIO_B1_14
C14
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[30]
Input
Keeper
i.MX RT1050 Crossover Processors for Industrial Products, Rev. 1, 03/2018
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85
Package information and contact assignments
Table 82. 10 x 10 mm functional contact assignments (continued)
GPIO_B1_15
B14
NVCC_GPIO
Digital
GPIO
ALT5
GPIO2.IO[31]
Input
Keeper
GPIO_EMC_00
E3
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[0]
Input
Keeper
GPIO_EMC_01
F3
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[1]
Input
Keeper
GPIO_EMC_02
F4
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[2]
Input
Keeper
GPIO_EMC_03
G4
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[3]
Input
Keeper
GPIO_EMC_04
F2
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[4]
Input
Keeper
GPIO_EMC_05
G5
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[5]
Input
Keeper
GPIO_EMC_06
H5
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[6]
Input
Keeper
GPIO_EMC_07
H4
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[7]
Input
Keeper
GPIO_EMC_08
H3
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[8]
Input
Keeper
GPIO_EMC_09
C2
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[9]
Input
Keeper
GPIO_EMC_10
G1
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[10]
Input
Keeper
GPIO_EMC_11
G3
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[11]
Input
Keeper
GPIO_EMC_12
H1
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[12]
Input
Keeper
GPIO_EMC_13
A6
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[13]
Input
Keeper
GPIO_EMC_14
B6
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[14]
Input
Keeper
GPIO_EMC_15
B1
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[15]
Input
Keeper
GPIO_EMC_16
A5
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[16]
Input
Keeper
GPIO_EMC_17
A4
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[17]
Input
Keeper
GPIO_EMC_18
B2
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[18]
Input
Keeper
GPIO_EMC_19
B4
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[19]
Input
Keeper
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Package information and contact assignments
Table 82. 10 x 10 mm functional contact assignments (continued)
GPIO_EMC_20
A3
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[20]
Input
Keeper
GPIO_EMC_21
C1
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[21]
Input
Keeper
GPIO_EMC_22
F1
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[22]
Input
Keeper
GPIO_EMC_23
G2
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[23]
Input
Keeper
GPIO_EMC_24
D3
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[24]
Input
Keeper
GPIO_EMC_25
D2
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[25]
Input
Keeper
GPIO_EMC_26
B3
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[26]
Input
Keeper
GPIO_EMC_27
A2
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[27]
Input
100 K PD
GPIO_EMC_28
D1
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[28]
Input
Keeper
GPIO_EMC_29
E1
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[29]
Input
Keeper
GPIO_EMC_30
C6
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[30]
Input
Keeper
GPIO_EMC_31
C5
NVCC_EMC
Digital
GPIO
ALT5
GPIO4.IO[31]
Input
Keeper
GPIO_EMC_32
D5
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[18]
Input
Keeper
GPIO_EMC_33
C4
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[19]
Input
Keeper
GPIO_EMC_34
D4
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[20]
Input
Keeper
GPIO_EMC_35
E5
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[21]
Input
Keeper
GPIO_EMC_36
C3
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[22]
Input
Keeper
GPIO_EMC_37
E4
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[23]
Input
Keeper
GPIO_EMC_38
D6
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[24]
Input
Keeper
GPIO_EMC_39
B7
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[25]
Input
Keeper
GPIO_EMC_40
A7
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[26]
Input
Keeper
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Package information and contact assignments
Table 82. 10 x 10 mm functional contact assignments (continued)
GPIO_EMC_41
C7
NVCC_EMC
Digital
GPIO
ALT5
GPIO3.IO[27]
Input
Keeper
GPIO_SD_B0_00
J4
NVCC_SD0
Digital
GPIO
ALT5
GPIO3.IO[12]
Input
Keeper
GPIO_SD_B0_01
J3
NVCC_SD0
Digital
GPIO
ALT5
GPIO3.IO[13]
Input
Keeper
GPIO_SD_B0_02
J1
NVCC_SD0
Digital
GPIO
ALT5
GPIO3.IO[14]
Input
Keeper
GPIO_SD_B0_03
K1
NVCC_SD0
Digital
GPIO
ALT5
GPIO3.IO[15]
Input
Keeper
GPIO_SD_B0_04
H2
NVCC_SD0
Digital
GPIO
ALT5
GPIO3.IO[16]
Input
Keeper
GPIO_SD_B0_05
J2
NVCC_SD0
Digital
GPIO
ALT5
GPIO3.IO[17]
Input
Keeper
GPIO_SD_B1_00
L5
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[0]
Input
Keeper
GPIO_SD_B1_01
M5
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[1]
Input
Keeper
GPIO_SD_B1_02
M3
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[2]
Input
Keeper
GPIO_SD_B1_03
M4
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[3]
Input
Keeper
GPIO_SD_B1_04
P2
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[4]
Input
Keeper
GPIO_SD_B1_05
N3
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[5]
Input
Keeper
GPIO_SD_B1_06
L3
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[6]
Input
Keeper
GPIO_SD_B1_07
L4
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[7]
Input
Keeper
GPIO_SD_B1_08
P3
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[8]
Input
Keeper
GPIO_SD_B1_09
N4
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[9]
Input
Keeper
GPIO_SD_B1_10
P4
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[01]
Input
Keeper
GPIO_SD_B1_11
P5
NVCC_SD1
Digital
GPIO
ALT5
GPIO3.IO[11]
Input
Keeper
ONOFF
M6
VDD_SNVS_IN
Digital
GPIO
ALT0
ONOFF
Input
100 K PU
PMIC_ON_REQ
K7
VDD_SNVS_IN
Digital
GPIO
ALT0
SNVS_LP.PMIC_ON_RE
Q
Output
100 K PU
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NXP Semiconductors
Package information and contact assignments
Table 82. 10 x 10 mm functional contact assignments (continued)
PMIC_STBY_REQ
L7
VDD_SNVS_IN
Digital
GPIO
ALT0
CCM.PMIC_VSTBY_RE
Q
Output
100 K PU
(PKE
disabled)
POR_B
M7
VDD_SNVS_IN
Digital
GPIO
ALT0
SRC.POR_B
Input
100 K PU
RTC_XTALI
N9
—
—
—
—
—
—
RTC_XTALO
P9
—
—
—
—
—
—
TEST_MODE
K6
VDD_SNVS_IN
Digital
GPIO
ALT0
TCU.TEST_MODE
Input
100 K PU
USB_OTG1_CHD_B
N12
—
—
—
—
—
—
USB_OTG1_DN
M8
—
—
—
—
—
—
USB_OTG1_DP
L8
—
—
—
—
—
—
USB_OTG1_VBUS
N6
—
—
—
—
—
—
USB_OTG2_DN
N7
—
—
—
—
—
—
USB_OTG2_DP
P7
—
—
—
—
—
—
USB_OTG2_VBUS
P6
—
—
—
—
—
—
XTALI
P11
—
—
—
—
—
—
XTALO
N11
—
—
—
—
—
—
L6
VDD_SNVS_IN
Digital
GPIO
ALT5
GPIO5.IO[0]
Input
100 K PU
WAKEUP
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NXP Semiconductors
89
90
GPIO_B0_14
NVCC_GPIO
GPIO_AD_B0_11
VSS
A
VSS
GPIO_EMC_16
D
GPIO_B1_12
GPIO_B1_05
GPIO_B1_03
GPIO_B0_13
GPIO_B0_10
GPIO_B0_03
GPIO_B0_00
C
GPIO_B1_14
GPIO_B1_11
GPIO_B1_06
GPIO_B1_02
GPIO_B0_12
GPIO_B0_09
GPIO_B0_04
B
GPIO_B1_15
GPIO_B1_10
GPIO_B1_07
GPIO_B1_01
VSS
GPIO_B0_08
GPIO_B0_05
A
VSS
GPIO_B1_09
GPIO_B1_08
GPIO_B1_00
GPIO_B0_11
GPIO_B0_07
GPIO_B0_06
GPIO_EMC_41 GPIO_EMC_39 GPIO_EMC_40
GPIO_EMC_38 GPIO_EMC_30 GPIO_EMC_14 GPIO_EMC_13
GPIO_EMC_32 GPIO_EMC_31
GPIO_EMC_34 GPIO_EMC_33 GPIO_EMC_19 GPIO_EMC_17
GPIO_EMC_24 GPIO_EMC_36 GPIO_EMC_26 GPIO_EMC_20
F
E
B
GPIO_EMC_25 GPIO_EMC_09 GPIO_EMC_18 GPIO_EMC_27
GPIO_B1_13
G
C
GPIO_EMC_28 GPIO_EMC_21 GPIO_EMC_15
D
GPIO_AD_B0_05 GPIO_AD_B0_09 GPIO_AD_B0_06
VSS
NVCC_GPIO
VDD_SOC_IN
VDD_SOC_IN
GPIO_AD_B0_10 GPIO_AD_B0_08
GPIO_B0_02
VDD_SOC_IN
VSS
GPIO_B1_04
GPIO_B0_01
VDD_SOC_IN
VSS
GPIO_AD_B1_14 GPIO_AD_B0_07
NVCC_EMC
VDD_SOC_IN
VDD_SOC_IN
GPIO_B0_15
GPIO_EMC_35
NVCC_EMC
GPIO_EMC_05
GPIO_AD_B0_03 GPIO_AD_B0_04
GPIO_EMC_37
GPIO_EMC_02
GPIO_EMC_03
VSS
GPIO_EMC_00
GPIO_EMC_04
GPIO_EMC_23
GPIO_EMC_29
GPIO_EMC_01
GPIO_EMC_22
GPIO_EMC_10
E
14
13
12
11
10
9
8
7
6
5
4
3
2
1
6.1.3
GPIO_EMC_11
F
G
Package information and contact assignments
10 x 10 mm, 0.65 mm pitch, ball map
Table 83 shows the 10 x 10 mm, 0.65 mm pitch ball map for the i.MX RT1050.
Table 83. 10 x 10 mm, 0.65 mm pitch, ball map
i.MX RT1050 Crossover Processors for Industrial Products, Rev. 1, 03/2018
NXP Semiconductors
NXP Semiconductors
14
13
12
11
10
9
8
7
6
5
4
3
2
1
USB_OTG1_DN
VDD_SNVS_IN
USB_OTG1_VBUS
USB_OTG2_DN
VSS
RTC_XTALI
GPANAIO
XTALO
USB_OTG2_VBUS
USB_OTG2_DP
VDD_HIGH_CAP
RTC_XTALO
NVCC_PLL
XTALI
VSS
USB_OTG1_DP
PMIC_STBY_REQ
WAKEUP
GPIO_SD_B1_00
GPIO_SD_B1_07
GPIO_AD_B0_00
M
VDDA_ADC_3P3
N
VSS
P
L
GPIO_AD_B0_13
GPIO_AD_B1_10
GPIO_AD_B1_04
USB_OTG1_CHD_B GPIO_AD_B1_03
GPIO_AD_B1_09
GPIO_AD_B1_02
GPIO_AD_B0_02
CCM_CLK1_P
J
VSS
NVCC_GPIO
VDD_SOC_IN
VSS
VSS
NVCC_SD0
DCDC_SENSE
GPIO_SD_B0_00
GPIO_AD_B0_01
VDD_SOC_IN
VSS
VSS
VDD_SOC_IN
GPIO_EMC_06
GPIO_EMC_07
GPIO_EMC_08
GPIO_AD_B1_11 GPIO_AD_B1_08
K
J
H
GPIO_AD_B0_12 GPIO_AD_B1_15 GPIO_AD_B0_14
VSS
GPIO_AD_B1_05 GPIO_AD_B1_06 GPIO_AD_B1_12
GPIO_AD_B1_01 GPIO_AD_B1_00 GPIO_AD_B1_13
GPIO_AD_B1_07
NGND_KEL0
VDD_USB_CAP
PMIC_ON_REQ
TEST_MODE
NVCC_SD1
DCDC__IN_Q
GPIO_EMC_12
H
GPIO_SD_B0_05 GPIO_SD_B0_04
GPIO_SD_B0_03 GPIO_SD_B0_02
K
GPIO_SD_B1_06 DCDC_PSWITCH GPIO_SD_B0_01
DCDC_IN
DCDC_IN
L
VDD_SNVS_CAP GPIO_AD_B0_15
ONOFF
GPIO_SD_B1_01
CCM_CLK1_N
VDD_HIGH_IN
POR_B
VSS
GPIO_SD_B1_11
GPIO_SD_B1_03
GPIO_SD_B1_09
GPIO_SD_B1_02
DCDC_LP
GPIO_SD_B1_10
DCDC_GND
GPIO_SD_B1_04
DCDC_LP
GPIO_SD_B1_05
DCDC_GND
VSS
M
GPIO_SD_B1_08
N
P
Package information and contact assignments
Table 83. 10 x 10 mm, 0.65 mm pitch, ball map (continued)
i.MX RT1050 Crossover Processors for Industrial Products, Rev. 1, 03/2018
91
Revision history
7
Revision history
Table 84 provides a revision history for this data sheet.
Table 84. i.MX RT1050 Data Sheet document revision history
Rev.
Number
Rev. 1
Date
03/2018
Substantive Change(s)
•
•
•
•
•
•
•
•
•
•
•
•
•
Rev. 0
10/2017
Updated the frequency and LCD display resolution in the Section 1.1, “Features
Updated the Table 1 Ordering information
Updated the Figure 1, "Part number nomenclature—i.MX RT1050"
Added 24-bit Parallel CSI in the Figure 2, "i.MX RT1050 system block diagram"
Updated the SJC description and DCDC input voltage in the Table 2 i.MX RT1050 modules list
Removed ADC_VREF from the Table 5 Recommended connections for unused analog interfaces
Updated the DCDC power supply in the Table 7 Absolute maximum ratings and Table 9 Operating
ranges
Updated the test conditions DCDC supply voltage in the Table 12 Low power mode current and power
consumption
Updated the Table 34 SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x1)
Updated the parameters in the Section 4.5.2, “FlexSPI parameters
Updated the Table 51 DCDC electrical specifications
Updated the Table 52 12-bit ADC operating conditions
Updated the notes of the Table 55 LPSPI Master mode timing and the Table 56 LPSPI Slave mode
timing
• Initial version
i.MX RT1050 Crossover Processors for Industrial Products, Rev. 1, 03/2018
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NXP Semiconductors
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information in this document. NXP reserves the right to make changes without further
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products for any particular purpose, nor does NXP assume any liability arising out of
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liability, including without limitation consequential or incidental damages. “Typical”
parameters that may be provided in NXP data sheets and/or specifications can and do
vary in different applications, and actual performance may vary over time. All operating
parameters, including “typicals” must be validated for each customer application by
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© 2017-2018 NXP B.V.
Document Number: IMXRT1050IEC
Rev. 1
03/2018
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