NXP Semiconductors
Data Sheet: Technical Data
K02P64M100SFA
Rev. 4, 08/2016
Kinetis K02 64 KB/128 KB Flash
100 MHz ARM® Cortex®-M4 Based Microcontroller with FPU
Ideal for low-power applications that require processing
efficiency and high peripheral integration. These devices share
the comprehensive enablement and scalability of the Kinetis
family.
This product offers:
• Run power consumption down to 117.5 µA/MHz and static
power consumption down to 2.8 µA with full state retention
and 5.7 µs wakeup. Lowest static mode down to 70 nA.
• Excellent processing efficiency, 100 MHz ARM® Cortex®M4-based device with floating-point unit in a tiny form factor
MK02FN128VLH10
MK02FN128VLF10
MK02FN128VFM10
MK02FN64VLH10
MK02FN64VLF10
MK02FN64VFM10
64 LQFP (LH)
10 x 10 x 1.4 Pitch 0.5
mm
48 LQFP (LF)
7 x 7 x 1.4 Pitch 0.5
mm
32 QFN (FM)
5 x 5 x 1 Pitch 0.5 mm
Performance
• 100 MHz ARM Cortex-M4 core with DSP instructions
delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• Up to 128 KB of embedded flash and 16 KB of RAM
• Preprogrammed Kinetis flashloader for one-time, insystem factory programming
Analog modules
• One 16-bit SAR ADC (1.2 MS/s in 12bit mode)
• One 12-bit DAC
• Two analog comparators (CMP) with 6- bit DAC
• Accurate internal voltage reference (not available in
32-pin QFN package)
Communication interfaces
• One SPI module
• Two UART modules
• One I2C: Support for up to 1 Mbps operation
System peripherals
• Flexible low-power modes, multiple wake up sources
• 4-channel DMA controller
• Independent External and Software Watchdog monitor Timers
• One 6-channel general-purpose/PWM timer
Clocks
• Two 2-channel general-purpose timers with
• Crystal oscillator: 32-40 kHz or 3-32 MHz
quadrature decoder functionality (FTM2 does not
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
have external pins on the 32-pin QFN or the 48-pin
• Multi-purpose clock generator with FLL
LQFP package)
• Periodic interrupt timers
Security and integrity modules
• 16-bit low-power timer
• Hardware CRC module
• Programmable delay block
• 128-bit unique identification (ID) number per chip
• Flash access control to protect proprietary software
Operating Characteristics
• Voltage range (including flash writes): 1.71 to 3.6 V
Human-machine interface
• Temperature range (ambient): -40 to 105°C
• Up to 46 general-purpose I/O (GPIO)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Part Number
Memory
Number of GPIOs
Flash (KB)
SRAM (KB)
MK02FN128VLH10
128
16
46
MK02FN128VLF10
128
16
35
MK02FN128VFM10
128
16
26
MK02FN64VLH10
64
16
46
MK02FN64VLF10
64
16
35
MK02FN64VFM10
64
16
26
Device Revision Number
Device Mask Set Number
SIM_SDID[REVID]
JTAG ID Register[PRN]
0N36M
0000
0000
Related Resources
Type
Description
Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
KINETISKMCUSELGD
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K02P64M100SFARM
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for Kinetis_K_0N36M
a particular device mask set.
Package
drawing
Package dimensions are provided by the part number:
• MK02FN64VFM10
• MK02FN128VFM10
• MK02FN64VLF10
• MK02FN128VLF10
• MK02FN64VLH10
• MK02FN128VLH10
•
•
•
•
•
•
98ARE10566D
98ARE10566D
98ASH00962A
98ASH00962A
98ASS23234W
98ASS23234W
Figure 1 shows the functional modules in the chip.
2
NXP Semiconductors
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
ARM ® Cortex™-M4
Core
Debug
interfaces
Interrupt
controller
System
DMA (4 ch)
DSP
FPU
Program
flash
(Up to 128 KB)
RAM
(16 KB)
Clocks
Frequencylocked loop
Low-leakage
wakeup
Low/high
frequency
oscillators
Internal
and external
watchdogs
Internal
reference
clocks
Security
Analog
Timers
CRC
16-bit
SAR ADC x1
Timers
x1 (6ch)
x2 (2ch)
Flash access
control
Comparator
with 6-bit DAC
x2
Programmable
12-bit DAC
x1
Periodic
interrupt
timers
High
performance
voltage ref
16-bit
low-power
timer
and Integrity
Memories and Memory Interfaces
delay block
Communication Interfaces
2
I C
x1
UART
x2
Human-Machine
Interface (HMI)
Up to
46 GPIOs
SPI
x1
Figure 1. Functional block diagram
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
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NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 16
2.2.7 Designing with radiated emissions in mind..........17
2.2.8 Capacitance attributes.........................................17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications..................................17
2.3.2 General switching specifications......................... 18
2.4 Thermal specifications..................................................... 18
2.4.1 Thermal operating requirements......................... 18
2.4.2 Thermal attributes................................................19
3 Peripheral operating requirements and behaviors.................. 20
3.1 Core modules.................................................................. 20
3.1.1 SWD electricals .................................................. 20
3.1.2 JTAG electricals.................................................. 21
3.2 System modules.............................................................. 24
3.3 Clock modules................................................................. 24
3.3.1 MCG specifications..............................................24
3.3.2 IRC48M specifications.........................................26
3.3.3 Oscillator electrical specifications........................26
3.4 Memories and memory interfaces................................... 29
3.4.1 Flash electrical specifications.............................. 29
3.5 Security and integrity modules........................................ 30
3.6 Analog............................................................................. 30
4
NXP Semiconductors
4
5
6
7
3.6.1 ADC electrical specifications............................... 30
3.6.2 CMP and 6-bit DAC electrical specifications....... 34
3.6.3 12-bit DAC electrical characteristics....................37
3.6.4 Voltage reference electrical specifications.......... 40
3.7 Timers..............................................................................41
3.8 Communication interfaces............................................... 41
3.8.1 DSPI switching specifications (limited voltage
range).................................................................. 42
3.8.2 DSPI switching specifications (full voltage
range).................................................................. 43
3.8.3 Inter-Integrated Circuit Interface (I2C) timing...... 45
3.8.4 UART switching specifications............................ 47
Dimensions............................................................................. 47
4.1 Obtaining package dimensions....................................... 47
Pinout...................................................................................... 47
5.1 K02F Signal Multiplexing and Pin Assignments.............. 47
5.2 Recommended connection for unused analog and
digital pins........................................................................50
5.3 K02F Pinouts................................................................... 51
Part identification.....................................................................54
6.1 Description.......................................................................54
6.2 Format............................................................................. 54
6.3 Fields............................................................................... 55
6.4 Example...........................................................................55
6.5 48-pin LQFP part marking............................................... 56
6.6 32-pin QFN part marking................................................. 56
Terminology and guidelines.................................................... 56
7.1 Definitions........................................................................ 56
7.2 Examples......................................................................... 57
7.3 Typical-value conditions.................................................. 57
7.4 Relationship between ratings and operating
requirements....................................................................58
7.5 Guidelines for ratings and operating requirements..........58
8 Revision History...................................................................... 58
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
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NXP Semiconductors
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
145
mA
VDIO
Digital input voltage
–0.3
VDD + 0.3
V
VAIO
Analog1
–0.3
VDD + 0.3
V
–25
25
mA
VDD – 0.3
VDD + 0.3
V
ID
VDDA
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
Notes
Table continues on the next page...
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Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
0.7 × VDD
—
V
0.75 × VDD
—
V
—
0.35 × VDD
V
—
0.3 × VDD
V
0.06 × VDD
—
V
VDDA
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
Notes
• 1.7 V ≤ VDD ≤ 2.7 V
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VHYS
Input hysteresis
IICIO
Analog and I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
1
-3
—
mA
-25
—
mA
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
2
1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or
greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VIO_MIN-VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
Notes
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
Table continues on the next page...
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7
NXP Semiconductors
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol
Description
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Min.
Typ.
Max.
Unit
—
80
—
mV
1.54
1.60
1.66
V
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
Min.
Typ.
Max.
Unit
Notes
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
VDD – 0.5
—
—
V
1
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VDD – 0.5
—
—
V
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
VDD – 0.5
—
—
V
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
VDD – 0.5
—
—
V
IOHT
Output high current total for all ports
—
—
100
mA
VOL
Output low voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
0.5
V
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
V
VOH
VOH
VOL
VOL
Description
Output high voltage — Normal drive pad except
RESET_B
Output high voltage — High drive pad except
RESET_B
1
1
Output low voltage — High drive pad except
RESET_B
1
Output low voltage — RESET_B
Table continues on the next page...
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Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
General
Table 3. Voltage and current operating behaviors (continued)
Symbol
Min.
Typ.
Max.
Unit
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
—
0.5
V
Output low current total for all ports
—
—
100
mA
All pins other than high drive port pins
—
0.002
0.5
μA
High drive port pins
—
0.004
0.5
μA
Input leakage current (total all pins) for full
temperature range
—
—
1.0
μA
2
RPU
Internal pullup resistors
20
—
50
kΩ
3
RPD
Internal pulldown resistors
20
—
50
kΩ
4
IOLT
IIN
IIN
Description
Notes
Input leakage current (per pin) for full
temperature range
1, 2
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
CPU and system clocks = 72 MHz
Bus clock = 36 MHz
Flash clock = 24 MHz
MCG mode: FEI
Table 4. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating
temperature range of the chip.
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
—
—
135
μs
—
—
135
μs
—
—
75
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
Table continues on the next page...
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
9
NXP Semiconductors
General
Table 4. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
—
75
μs
—
—
5.7
μs
—
—
5.7
μs
Notes
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
The current parameters in the table below are derived from code executing a while(1)
loop from flash, unless otherwise noted.
The IDD typical values represent the statistical mean at 25°C, and the IDD maximum
values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction
temperature unless otherwise noted. The maximum values represent characterized
results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 5. Power consumption operating behaviors
Symbol
IDDA
Description
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
@ 1.8V
—
18.70
19.37
mA
2, 3, 4
@ 3.0V
—
18.71
19.38
mA
@ 1.8V
—
18.13
18.80
mA
@ 3.0V
—
18.19
18.86
mA
@ 1.8V
—
22.2
22.87
mA
@ 3.0V
—
22.4
23.07
mA
@ 1.8V
—
12.74
13.41
mA
@ 3.0V
—
12.82
13.49
mA
Analog supply current
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
4
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
IDD_RUN
5
Run mode current in Compute operation —
CoreMark benchmark code executing from flash
2, 3, 6
Table continues on the next page...
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Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
IDD_RUN
Run mode current in Compute operation —
code executing from flash
IDD_RUN
IDD_RUN
Min.
Typ.
Max.
Unit
Notes
@ 1.8V
—
12.10
13.10
mA
6
@ 3.0V
—
12.20
13.37
mA
@ 1.8V
—
12.8
13.47
mA
@ 3.0V
—
12.9
13.57
mA
—
14.8
15.47
mA
• @ 25°C
—
14.9
15.57
mA
• @ 70°C
—
14.9
15.57
mA
• @ 85°C
—
14.9
15.57
mA
• @ 105°C
—
15.5
16.20
mA
—
12.1
12.77
mA
• @ 25°C
—
12.2
12.87
mA
• @ 70°C
—
12.2
12.87
mA
• @ 85°C
—
12.2
12.87
mA
• @ 105°C
—
12.7
13.37
mA
Run mode current — all peripheral clocks
disabled, code executing from flash
7
Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
8
@ 3.0V
IDD_RUN
Run mode current — Compute operation, code
executing from flash
@ 1.8V
9
@ 3.0V
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
5.5
6.17
mA
7
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
3.5
4.17
mA
10
IDD_VLPR
Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
@ 1.8V
—
0.58
0.86
mA
2, 11, 3
@ 3.0V
—
0.59
0.87
mA
@ 1.8V
—
0.47
0.75
mA
@ 3.0V
—
0.47
0.75
mA
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
0.62
0.90
mA
IDD_VLPR
IDD_VLPR
Very-low-power run mode current in Compute
operation, code executing from flash
11
12
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11
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General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
0.76
1.04
mA
13
IDD_VLPW
Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
0.28
0.56
mA
14
IDD_STOP
Stop mode current at 3.0 V
@ -40°C to 25°C
—
0.26
0.33
mA
@ 70°C
—
0.30
0.47
mA
@ 85°C
—
0.35
0.52
mA
@ 105°C
—
0.43
0.60
mA
IDD_VLPS
Very-low-power stop mode current at 3.0 V
@ -40°C to 25°C
—
2.80
8.30
µA
@ 70°C
—
13.30
29.90
µA
@ 85°C
—
26.90
46.45
µA
@ 105°C
—
56.80
67.05
µA
@ -40°C to 25°C
—
1.3
1.71
µA
@ 70°C
—
3.8
5.35
µA
@ 85°C
—
7.6
8.50
µA
@ 105°C
—
15.1
19.05
µA
@ -40°C to 25°C
—
1.3
1.55
µA
@ 70°C
—
3.1
4.05
µA
@ 85°C
—
7.2
8.60
µA
@ 105°C
—
12.0
14.10
µA
@ -40°C to 25°C
—
0.63
0.87
µA
@ 70°C
—
1.70
2.35
µA
@ 85°C
—
2.8
3.40
µA
@ 105°C
—
7.6
8.80
µA
@ -40°C to 25°C
—
0.35
0.46
µA
@ 70°C
—
1.38
1.94
µA
@ 85°C
—
2.4
2.95
µA
@ 105°C
—
7.3
8.45
µA
@ -40°C to 25°C
—
0.07
0.16
µA
@ 70°C
—
1.05
1.78
µA
@ 85°C
—
2.1
2.80
µA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
Table continues on the next page...
12
NXP Semiconductors
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General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
@ 105°C
Min.
Typ.
Max.
Unit
—
6.9
8.25
µA
Notes
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. Cache on and prefetch on, low compiler optimization
3. CoreMark benchmark compiled using IAR 7.2 with optimization level low
4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled.
5. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
6. 72 MHz core and system clock, 36 MHz bus clock and 24 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled. Compute operation.
7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks disabled.
8. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute
operation.
10. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode.
11. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. Compute operation.
Code executing from flash.
12. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
13. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled, but peripherals are not in active operation. Code executing from flash.
14. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
Table 6. Low power mode peripheral adders—typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
440
490
540
560
570
580
nA
VLLS3
440
490
540
560
570
580
LLS
490
490
540
560
570
680
Table continues on the next page...
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13
NXP Semiconductors
General
Table 6. Low power mode peripheral adders—typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
VLPS
510
560
560
560
610
680
STOP
510
560
560
560
610
680
48 Mhz internal reference clock
350
350
350
350
350
350
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
22
22
22
22
22
22
µA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
66
66
66
66
66
66
µA
214
237
246
254
260
268
I48MIRC
MCGIRCLK (4 MHz internal reference
clock)
>OSCERCLK (4 MHz external crystal)
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42
42
42
42
42
42
µA
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
14
NXP Semiconductors
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
General
Figure 3. Run mode supply current vs. core frequency
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
15
NXP Semiconductors
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 64 LQFP package
Parame Conditions
ter
VEME
Clocks
Frequency range
Level
(Typ.)
Unit
Notes
Device configuration, test FSYS = 100 MHz
150 kHz–50 MHz
conditions and EM
50 MHz–150 MHz
FBUS = 50 MHz
testing per standard IEC
External crystal = 10 MHz 150 MHz–500 MHz
61967-2.
500 MHz–1000 MHz
Supply voltage: VDD =
11
dBuV
1, 2, 3
3.3 V
N
IEC level
12
11
8
4
Temp = 25°C
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. Measurements were performed on a similar 64LQFP device.
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
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NXP Semiconductors
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
General
4. IEC Level Maximums: N ≤ 12dBmV, M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV .
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to nxp.com
• Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed run mode
fSYS
System and core clock
—
100
MHz
fBUS
Bus clock
—
50
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
72
MHz
fBUS
Bus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
VLPR mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
fLPTMR_pin
Table continues on the next page...
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17
NXP Semiconductors
General
Table 9. Device clock specifications (continued)
Symbol
Description
fLPTMR_ERCLK LPTMR external reference clock
Min.
Max.
Unit
—
16
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
50
—
ns
4
Port rise and fall time
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
5
—
—
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
10
ns
5
ns
30
ns
16
ns
—
—
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can
be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
2.4 Thermal specifications
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General
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Notes
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Board type
Symbol
Descriptio
n
64 LQFP
48 LQFP
32 QFN
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
66
79
97
°C/W
1
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
48
55
33
°C/W
1
Single-layer
(1s)
RθJMA
Thermal
54
resistance,
junction to
ambient (200
ft./min. air
speed)
67
81
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal
41
resistance,
junction to
ambient (200
ft./min. air
speed)
49
28
°C/W
1
—
RθJB
Thermal
resistance,
junction to
board
30
33
13
°C/W
2
—
RθJC
Thermal
resistance,
junction to
case
17
23
2.0
°C/W
3
—
ΨJT
Thermal
3
characterizati
5
6
°C/W
4
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NXP Semiconductors
Peripheral operating requirements and behaviors
Board type
Symbol
Descriptio
n
64 LQFP
48 LQFP
32 QFN
Unit
Notes
on
parameter,
junction to
package top
outside
center
(natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 12. SWD full voltage range electricals
Symbol
S1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
33
MHz
1/S1
—
ns
15
—
ns
SWD_CLK frequency of operation
• Serial wire debug
S2
SWD_CLK cycle period
S3
SWD_CLK clock pulse width
• Serial wire debug
S4
SWD_CLK rise and fall times
—
3
ns
S9
SWD_DIO input data setup time to SWD_CLK rise
8
—
ns
S10
SWD_DIO input data hold time after SWD_CLK rise
1.4
—
ns
S11
SWD_CLK high to SWD_DIO data valid
—
25
ns
S12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
20
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Peripheral operating requirements and behaviors
S2
S3
S3
SWD_CLK (input)
S4
S4
Figure 5. Serial wire clock input timing
SWD_CLK
S9
SWD_DIO
S10
Input data valid
S11
SWD_DIO
Output data valid
S12
SWD_DIO
S11
SWD_DIO
Output data valid
Figure 6. Serial wire data timing
3.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
1/J1
—
ns
50
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 13. JTAG limited voltage range electricals (continued)
Symbol
Description
• Boundary Scan
Min.
Max.
Unit
25
—
ns
• JTAG and CJTAG
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
1
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
19
ns
J12
TCLK low to TDO high-Z
—
19
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Table 14. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
15
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
33
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
1.4
—
ns
J7
TCLK low to boundary scan output data valid
—
27
ns
J8
TCLK low to boundary scan output high-Z
—
27
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
26.2
ns
J12
TCLK low to TDO high-Z
—
26.2
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
22
NXP Semiconductors
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
Peripheral operating requirements and behaviors
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
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NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
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NXP Semiconductors
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 15. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Δfints_t
Total deviation of internal reference frequency
(slow clock) over voltage and temperature
—
+0.5/-0.7
±2
%
31.25
—
39.0625
kHz
—
± 0.3
± 0.6
%fdco
1
fints_t
Internal reference frequency (slow clock) —
user trimmed
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
± 1.5
%fdco
1
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
—
+1/-2
±5
%fintf_ft
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
fintf_ft
Δfintf_ft
fintf_t
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
Table continues on the next page...
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25
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
95.98
—
MHz
Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire
—
—
180
—
ps
—
—
150
FLL target frequency acquisition time
—
—
1
ms
7
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2.0 V
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