Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document number: K11P121M50SF4V2
Rev 6, 04/2014
Kinetis K11D Sub-Family Data
Sheet
50 MHz ARM® Cortex®-M4-based Microcontroller
MK11DX128AVMC5
MK11DX256AVMC5
MK11DN512AVMC5
The K11 product family members are optimized for cost-sensitive
applications requiring low-power, processing efficiency and the
need for extensive tamper protection, such as Electronic Point of
Sales. This device shares the comprehensive enablement and
scalability of the Kinetis family.
This product offers:
• Up to 512 KB of flash memory with up to 64 KB of SRAM
• DryIce Tamper Detection with active/passive pin,
temperature, clock, supply voltage monitoring
• Run power consumption down to 189 μA/MHz and Static
power consumption down to 3.1 μA with full state retention
and 6 μs wakeup. Lowest Static mode down to 359 nA
Performance
• Up to 50 MHz ARM® Cortex®-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• Up to 512 KB of program flash
• Up to 64 KB RAM
• 64 KB FlexNVM and 4 KB FlexRAM on FlexMemory
devices
System peripherals
• Multiple low-power modes
• 16-channel DMA controller
• External watchdog monitor
• Software watchdog
Clocks
• 32 kHz and 3-32 MHz crystal oscillator
• Multipurpose clock generator
Security and integrity modules
• Hardware CRC module
• Tamper detect and secure storage
• Hardware random-number generator
• Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
• 128-bit unique identification (ID) number per chip
121 BGA
8 x 8 x 1.4 mm Pitch 0.65 mm
Communication interfaces
• Two SPI modules
• Two I2C modules
• Four UART modules
• I2S module
Timers
• 8-channel motor control/general purpose/PWM
timers
• Two 2-channel general purpose timers
• 32-bit PITs and 16-bit low-power timer
• Carrier modulator transmitter
• Real-time clock
• Programmable delay block
Analog modules
• 16-bit SAR ADC
• Two analog comparators (CMP)
• 12-bit DAC
• Voltage reference
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2013–2014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MK11DX128AVMC5
128 KB
32
64
MK11DX256AVMC5
256 KB
32
64
MK11DN512AVMC5
512 KB
64
64
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K10PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K11P121M50SF4V2RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
K11P121M50SF4V21
Package
drawing
Package dimensions are provided in package drawings.
• MAPBGA 121-pin:
98ASA00344D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Kinetis K11D Family
ARM ® Cortex™-M4
Core
Debug
interfaces
DSP
Interrupt
controller
System
Memories and Memory Interfaces
Internal
and external
watchdogs
Program
flash
DMA
FlexMemory
Frequencylocked loop
Low-leakage
wakeup
Serial
programming
interface
Low/high
frequency
oscillators
RAM
Memory
protection
unit (MPU)
Security
Communication Interfaces
Timers
16-bit ADC
Timers
x3 (16ch)
I C
x2
Random
number
generator
Analog
comparator
x2
Carrier
modulator
transmitter
UART
x4
Hardware
encryption
6-bit DAC
x2
Programmable
Tamper
detect
12-bit DAC
Periodic
interrupt
timers
Voltage
reference
Low power
timer
CRC
delay block
Phaselocked loop
Internal
reference
clocks
Analog
and Integrity
Clocks
2
Human-Machine
Interface (HMI)
2
I S
x1
GPIO
SPI
x2
Independent
real-time
clock
Figure 1. K11D block diagram
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 14
2.2.7 Designing with radiated emissions in mind..........15
2.2.8 Capacitance attributes.........................................15
2.3 Switching specifications...................................................15
2.3.1 Device clock specifications..................................15
2.3.2 General switching specifications......................... 16
2.4 Thermal specifications..................................................... 17
2.4.1 Thermal operating requirements......................... 17
2.4.2 Thermal attributes................................................17
3 Peripheral operating requirements and behaviors.................. 18
3.1 Core modules.................................................................. 18
3.1.1 JTAG electricals.................................................. 19
3.2 System modules.............................................................. 22
3.3 Clock modules................................................................. 22
3.3.1 MCG specifications..............................................22
3.3.2 Oscillator electrical specifications........................24
3.3.3 32 kHz oscillator electrical characteristics........... 26
3.4 Memories and memory interfaces................................... 27
3.4.1 Flash electrical specifications.............................. 27
3.4.2 EzPort switching specifications........................... 30
3.5 Security and integrity modules........................................ 31
3.5.1 DryIce Tamper Electrical Specifications.............. 31
3.6 Analog............................................................................. 31
3.6.1 ADC electrical specifications............................... 31
4
Freescale Semiconductor, Inc.
4
5
6
7
8
3.6.2 CMP and 6-bit DAC electrical specifications....... 36
3.6.3 12-bit DAC electrical characteristics....................38
3.6.4 Voltage reference electrical specifications.......... 41
3.7 Timers..............................................................................42
3.8 Communication interfaces............................................... 42
3.8.1 DSPI switching specifications (limited voltage
range).................................................................. 42
3.8.2 DSPI switching specifications (full voltage
range).................................................................. 44
3.8.3 I2C switching specifications.................................46
3.8.4 UART switching specifications............................ 46
3.8.5 I2S switching specifications.................................46
Dimensions............................................................................. 50
4.1 Obtaining package dimensions....................................... 50
Pinout...................................................................................... 50
5.1 K11 Signal Multiplexing and Pin Assignments.................50
5.2 K11 Pinouts..................................................................... 55
Ordering parts......................................................................... 56
6.1 Determining valid orderable parts....................................56
Part identification.....................................................................57
7.1 Description.......................................................................57
7.2 Format............................................................................. 57
7.3 Fields............................................................................... 57
7.4 Example...........................................................................58
7.5 Small package marking................................................... 58
Terminology and guidelines.................................................... 59
8.1 Definition: Operating requirement....................................59
8.2 Definition: Operating behavior......................................... 59
8.3 Definition: Attribute.......................................................... 60
8.4 Definition: Rating............................................................. 60
8.5 Result of exceeding a rating............................................ 60
8.6 Relationship between ratings and operating
requirements....................................................................61
8.7 Guidelines for ratings and operating requirements..........61
8.8 Definition: Typical value...................................................62
8.9 Typical value conditions.................................................. 63
9 Revision History...................................................................... 63
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
5
Freescale Semiconductor, Inc.
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
155
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VDD + 0.3
V
VAIO
Analog1,
–0.3
VDD + 0.3
V
ID
RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
VDDA
Analog supply voltage
VBAT
RTC battery supply voltage
–25
25
mA
VDD – 0.3
VDD + 0.3
V
–0.3
3.8
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
General
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.71 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.71 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
VBAT
VIH
VIL
RTC battery supply voltage
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
I/O pin DC injection current — single pin
1
mA
• VIN < VSS-0.3V (Negative current injection)
-3
—
—
+3
-25
—
—
+25
1.2
—
V
VPOR_VBAT
—
V
• VIN > VDD+0.3V (Positive current injection)
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
VRAM
VRFVBAT
Notes
VDD voltage required to retain RAM
VBAT voltage required to retain the VBAT register file
mA
1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VINVAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative
injection currents.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Notes
Table continues on the next page...
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
7
Freescale Semiconductor, Inc.
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1,
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
—
V
VDD – 0.5
—
V
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
Table continues on the next page...
8
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
0.5
V
—
100
mA
• @ full temperature range
—
1.0
μA
• @ 25 °C
—
0.1
μA
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
Notes
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
1
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
IOZ
Total Hi-Z (off-state) leakage current (all input pins)
—
4
μA
RPU
Internal pullup resistors
22
50
kΩ
2
RPD
Internal pulldown resistors
22
50
kΩ
3
1. Tested by ganged leakage method
2. Measured at Vinput = VSS
3. Measured at Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
CPU and system clocks = 50 MHz
Bus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
After a POR event, amount of time from the point
VDD reaches 1.71 V to execution of the first
instruction across the operating temperature range
of the chip.
—
Max.
Unit
Notes
μs
1
300
Table continues on the next page...
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
9
Freescale Semiconductor, Inc.
General
Table 5. Power mode transition operating behaviors (continued)
Symbol
Description
• 1.71 V/(VDD slew rate) ≤ 300 μs
Min.
Max.
—
1.7 V / (VDD
slew rate)
—
150
μs
—
150
μs
—
79
μs
—
79
μs
—
6
μs
—
5.2
μs
—
5.2
μs
• 1.71 V/(VDD slew rate) > 300 μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
Unit
Notes
1. Normal boot (FTFL_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8 V
• @ 3.0 V
IDD_RUN
Min.
2
—
12.98
14
mA
—
12.93
13.8
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8 V
3, 4
—
17.04
19.3
mA
—
17.01
18.9
mA
—
19.8
21.3
mA
• @ 3.0 V
• @ 25°C
• @ 125°C
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
7.95
9.5
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
5.88
7.4
mA
5
IDD_STOP
Stop mode current at 3.0 V
—
320
436
μA
Table continues on the next page...
10
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
•
•
•
•
Min.
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C
Typ.
Max.
360
489
410
620
Unit
Notes
610
1100
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
754
—
μA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.1
—
mA
7
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
437
—
μA
8
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
7.33
24.2
14
32
28
48
110
280
3.14
4.8
6.48
28.3
13.85
44.6
55.53
71.3
2.19
3.4
4.35
4.35
8.92
24.6
35.33
45.3
1.77
3.1
2.81
13.8
5.20
22.3
19.88
34.2
1.03
1.8
1.92
7.5
4.03
15.9
17.43
28.7
0.543
1.1
1.36
7.58
3.39
14.3
16.52
24.1
0.359
0.95
1.03
6.8
2.87
15.4
IDD_LLS
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
•
•
•
•
—
—
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
—
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 50°C
—
μA
μA
μA
μA
μA
μA
μA
Table continues on the next page...
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
11
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
• @ 70°C
• @ 105°C
IDD_VBAT
Average current when CPU is not accessing
RTC registers at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
Typ.
Max.
15.20
25.3
0.91
1.1
1.1
1.35
1.5
1.85
4.3
5.7
Unit
Notes
μA
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
3. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, and peripherals are in active operation.
4. Max values are measured with CPU executing DSP instructions
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
7. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
9. Includes 32 kHz oscillator current and RTC operation.
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
MCG in FBE mode
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFL
12
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
General
Figure 3. Run mode supply current vs. core frequency
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
13
Freescale Semiconductor, Inc.
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors 1
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
19
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
21
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
19
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
11
dBμV
IEC level
0.15–1000
L
—
VRE_IEC
3, 4
1. This data was collected on a MK20DN128VLH5 64pin LQFP device.
2. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
14
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
General
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
3. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 48 MHz, fBUS = 48MHz
4. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
50
MHz
fBUS
Bus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
Table continues on the next page...
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
15
Freescale Semiconductor, Inc.
General
Table 9. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
fLPTMR_pin
LPTMR clock
—
25
MHz
—
16
MHz
fLPTMR_ERCLK LPTMR external reference clock
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
13
ns
• 2.7 ≤ VDD ≤ 3.6V
—
7
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Port rise and fall time (low drive strength)
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
16
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
General
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
2.4.2 Thermal attributes
Board type
Symbol
Description
121 MAPBGA
Unit
Notes
Single-layer (1s)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
79
°C/W
1, 2
Four-layer (2s2p)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
46
°C/W
1, 3
Single-layer (1s)
RθJMA
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
67
°C/W
1,3
Four-layer (2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
42
°C/W
1,3
Table continues on the next page...
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
17
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Board type
Symbol
Description
121 MAPBGA
Unit
Notes
—
RθJB
Thermal
resistance,
junction to board
29
°C/W
4
—
RθJC
Thermal
resistance,
junction to case
21
°C/W
5
—
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
4
°C/W
6
NOTES:
1. Junction temperature is a function of die size, on-chip power dissipation, package
thermal resistance, mounting site (board) temperature, ambient temperature, air
flow, power dissipation of other components on the board, and board thermal
resistance.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air) with the
single layer board horizontal. Board meets JESD51-9 specification.
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuit Thermal
Test Method Environmental Conditions—Forced Convection (Moving Air) with the
board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental Conditions—Junction-to-Board. Board temperature is
measured on the top surface of the board near the package.
5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,
Microcircuits, with the cold plate temperature used for the case temperature. The
value includes the thermal resistance of the interface material between the top of
the package and the cold plate.
6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
18
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
3.1.1 JTAG electricals
Table 12. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Unit
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 13. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Operating voltage
1.71
3.6
TCLK frequency of operation
V
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
50
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
• Boundary Scan
Table continues on the next page...
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
19
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 5. Test clock input timing
20
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 6. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 7. Test Access Port timing
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
21
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 8. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 14. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
1, 2
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
(3/5) x
fints_t
—
—
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
Table continues on the next page...
22
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
Min.
Typ.
Max.
Unit
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
100
MHz
—
1200
—
µA
—
700
—
µA
2.0
—
4.0
MHz
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5,6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
8
8
9
• fvco = 48 MHz
—
120
—
ps
• fvco = 100 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
9
—
1350
—
ps
—
600
—
ps
Table continues on the next page...
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
• fvco = 48 MHz
• fvco = 100 MHz
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high-gain mode (HGO=1)
1
Table continues on the next page...
24
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• 32 kHz
—
5
—
μA
• 4 MHz
—
500
—
μA
• 8 MHz (RANGE=01)
—
600
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Notes
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Vpp5
1.
2.
3.
4.
5.
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
25
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.3.2.2
Symbol
Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.3.3 32 kHz oscillator electrical characteristics
3.3.3.1
32 kHz oscillator DC electrical specifications
Table 17. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Table continues on the next page...
26
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 17. 32kHz oscillator DC electrical specifications (continued)
Symbol
Min.
Typ.
Max.
Unit
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
Description
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.3.2
Symbol
fosc_lo
tstart
32 kHz oscillator frequency specifications
Table 18. 32 kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
1
700
—
VBAT
mV
2, 3
vec_extal32 Externally provided input clock amplitude
Notes
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 19. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
—
104
904
ms
1
thversblk256k Erase Block high-voltage time for 256 KB
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
27
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Symbol
Flash timing specifications — commands
Table 20. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
Read 1s Block execution time
Notes
—
trd1blk64k
• 64 KB data flash
—
—
0.9
ms
trd1blk256k
• 256 KB program flash
—
—
1.7
ms
trd1sec2k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
Erase Flash Block execution time
2
tersblk64k
• 64 KB data flash
—
58
580
ms
tersblk256k
• 256 KB program flash
—
122
985
ms
—
14
114
ms
tersscr
Erase Flash Sector execution time
Program Section execution time
2
—
tpgmsec512
• 512 bytes flash
—
2.4
—
ms
tpgmsec1k
• 1 KB flash
—
4.7
—
ms
tpgmsec2k
• 2 KB flash
—
9.3
—
ms
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
—
trdonce
Read Once execution time
—
—
25
μs
1
tpgmonce
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
250
2000
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
Swap Control execution time
—
tswapx01
• control code 0x01
—
200
—
μs
tswapx02
• control code 0x02
—
70
150
μs
tswapx04
• control code 0x04
—
70
150
μs
tswapx08
• control code 0x08
—
—
30
μs
Program Partition for EEPROM execution time
tpgmpart64k
• 64 KB FlexNVM
—
—
138
—
ms
Set FlexRAM Function execution time:
tsetramff
—
• Control Code 0xFF
—
70
—
μs
tsetram32k
• 32 KB EEPROM backup
—
0.8
1.2
ms
tsetram64k
• 64 KB EEPROM backup
—
1.3
1.9
ms
Byte-write to FlexRAM for EEPROM operation
Table continues on the next page...
28
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 20. Flash command timing specifications (continued)
Symbol
Description
teewr8bers
Byte-write to erased FlexRAM location
execution time
Min.
Typ.
Max.
Unit
Notes
—
175
260
μs
3
Byte-write to FlexRAM execution time:
teewr8b32k
• 32 KB EEPROM backup
teewr8b64k
• 64 KB EEPROM backup
—
—
385
1800
μs
475
2000
μs
260
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
—
Word-write to FlexRAM execution time:
—
teewr16b32k
• 32 KB EEPROM backup
—
385
1800
μs
teewr16b64k
• 64 KB EEPROM backup
—
475
2000
μs
540
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
—
Longword-write to FlexRAM execution time:
—
teewr32b32k
• 32 KB EEPROM backup
—
630
2050
μs
teewr32b64k
• 64 KB EEPROM backup
—
810
2250
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
3.4.1.3
Flash high voltage current behaviors
Table 21. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 22. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
20
100
—
years
—
Data retention after up to 1 K cycles
Table continues on the next page...
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
29
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 22. NVM reliability specifications (continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
50
—
years
—
20
100
—
years
—
10 K
50 K
—
cycles
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k
Data retention after up to 1 K cycles
nnvmcycd
Cycling endurance
5
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
—
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
—
Write endurance
3
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
35 K
175 K
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
315 K
1.6 M
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
1.27 M
6.4 M
—
writes
nnvmwree4k
• EEPROM backup to FlexRAM ratio =
4096
10 M
50 M
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ °C.
3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ °C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
3.4.2 EzPort switching specifications
Table 23. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
30
Freescale Semiconductor, Inc.
ns
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 9. EzPort Timing Diagram
3.5 Security and integrity modules
3.5.1 DryIce Tamper Electrical Specifications
Information about security-related modules is not included in this document and is
available only after a nondisclosure agreement (NDA) has been signed. To request an
NDA, please contact your local Freescale sales representative.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 24 and Table 25 are achievable on
the differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
31
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.1.1
16-bit ADC operating conditions
Table 24. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
—
• All other modes
VREFL
—
• 16-bit mode
—
8
10
pF
—
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
kΩ
—
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
VREFH
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
5
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
32
Freescale Semiconductor, Inc.
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 10. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
ADC
asynchronous
clock source
fADACK
Conditions1
• ADLPC = 1, ADHSC =
0
• ADLPC = 1, ADHSC =
1
• ADLPC = 0, ADHSC =
0
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
1.2
2.4
3.9
MHz
2.4
4.0
6.1
MHz
tADACK =
1/fADACK
3.0
5.2
7.3
MHz
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
• ADLPC = 0, ADHSC =
1
Sample Time
TUE
DNL
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
•
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