Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document number: K21P121M50SF4V2
Rev 6, 04/2014
Kinetis K21D Sub-Family Data
Sheet
50 MHz ARM® Cortex®-M4-based Microcontroller
MK21DX128AVMC5
MK21DX256AVMC5
MK21DN512AVMC5
The K21 product family members are optimized for cost-sensitive
applications requiring low-power, USB connectivity, processing
efficiency and the need for extensive tamper protection, such as
Electronic Point of Sales. This device shares the comprehensive
enablement and scalability of the Kinetis family.
This product offers:
• Up to 512 KB of flash memory with up to 64 KB of SRAM
• DryIce Tamper Detection with active/passive pin,
temperature, clock, supply voltage monitoring
• Run power consumption down to 189 μA/MHz and Static
power consumption down to 3.1 μA with full state retention
and 6 μs wakeup. Lowest Static mode down to 359 nA
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
voltage regulator
Performance
• Up to 50 MHz ARM® Cortex®-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• Up to 512 KB of program flash
• Up to 64 KB RAM
• 64 KB FlexNVM and 4 KB FlexRAM on FlexMemory
devices
System peripherals
• Multiple low-power modes
• 16-channel DMA controller
• External watchdog monitor
• Software watchdog
Clocks
• 32 kHz and 3-32 MHz crystal oscillator
• Multipurpose clock generator
Security and integrity modules
• Hardware CRC module
• Tamper detect and secure storage
• Hardware random-number generator
• Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
• 128-bit unique identification (ID) number per chip
121 BGA
8 x 8 x 1.4 mm Pitch 0.65 mm
Communication interfaces
• USB full-/low-speed On-the-Go controller
• USB Device Charger detect (USBDCD)
• Two SPI modules
• Two I2C modules
• Four UART modules
• I2S module
Timers
• 8-channel motor control/general purpose/PWM
timers
• Two 2-channel general purpose timers
• 32-bit PITs and 16-bit low-power timer
• Carrier modulator transmitter
• Real-time clock
• Programmable delay block
Analog modules
• 16-bit SAR ADC
• Two analog comparators (CMP)
• 12-bit DAC
• Voltage reference
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2013–2014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MK21DX128AVMC5
128 KB
32
64
MK21DX256AVMC5
256 KB
32
64
MK21DN512AVMC5
512 KB
64
64
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K20PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K21P121M50SF4V2RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
K21P121M50SF4V21
Package
drawing
Package dimensions are provided in package drawings.
• MAPBGA 121-pin:
98ASA00344D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Kinetis K21D Family
ARM ® Cortex™-M4
Core
Debug
interfaces
DSP
Interrupt
controller
System
Memories and Memory Interfaces
Clocks
Internal
and external
watchdogs
Program
flash
DMA
FlexMemory
Frequencylocked loop
Low-leakage
wakeup
Serial
programming
interface
Low/high
frequency
oscillators
RAM
Phaselocked loop
Internal
reference
clocks
Security
and Integrity
CRC
Analog
16-bit ADC
Timers
Communication Interfaces
2
2
FlexTimers
I Cx2
I S
Carrier
modulator
transmitter
UARTx4
USB OTG
LS/FS/HS
SPIx2
USB LS/FS
transceiver
Random
number
generator
Analog
comparator
Hardware
encryption
6-bit DAC
Tamper
detect
12-bit DAC
Periodic
interrupt
timers
USB charger
detect
Voltage
reference
Low power
timer
USB voltage
regulator
Programmable
delay block
Human-Machine
Interface (HMI)
GPIO
Independent
real-time
clock
Figure 1. K21D block diagram
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 14
2.2.7 Designing with radiated emissions in mind..........15
2.2.8 Capacitance attributes.........................................15
2.3 Switching specifications...................................................15
2.3.1 Device clock specifications..................................15
2.3.2 General switching specifications......................... 16
2.4 Thermal specifications..................................................... 17
2.4.1 Thermal operating requirements......................... 17
2.4.2 Thermal attributes................................................17
3 Peripheral operating requirements and behaviors.................. 18
3.1 Core modules.................................................................. 19
3.1.1 JTAG electricals.................................................. 19
3.2 System modules.............................................................. 22
3.3 Clock modules................................................................. 22
3.3.1 MCG specifications..............................................22
3.3.2 Oscillator electrical specifications........................24
3.3.3 32 kHz oscillator electrical characteristics........... 26
3.4 Memories and memory interfaces................................... 27
3.4.1 Flash electrical specifications.............................. 27
3.4.2 EzPort switching specifications........................... 30
3.5 Security and integrity modules........................................ 31
3.5.1 DryIce Tamper Electrical Specifications.............. 31
3.6 Analog............................................................................. 31
3.6.1 ADC electrical specifications............................... 31
3.6.2 CMP and 6-bit DAC electrical specifications....... 36
3.6.3 12-bit DAC electrical characteristics....................38
4
Freescale Semiconductor, Inc.
4
5
6
7
8
3.6.4 Voltage reference electrical specifications.......... 41
3.7 Timers..............................................................................42
3.8 Communication interfaces............................................... 42
3.8.1 USB electrical specifications............................... 42
3.8.2 USB DCD electrical specifications.......................43
3.8.3 VREG electrical specifications.............................43
3.8.4 DSPI switching specifications (limited voltage
range).................................................................. 44
3.8.5 DSPI switching specifications (full voltage
range).................................................................. 45
3.8.6 I2C switching specifications.................................47
3.8.7 UART switching specifications............................ 47
3.8.8 I2S switching specifications.................................48
Dimensions............................................................................. 51
4.1 Obtaining package dimensions....................................... 51
Pinout...................................................................................... 52
5.1 K21 Signal Multiplexing and Pin Assignments.................52
5.2 K21 Pinouts..................................................................... 56
Ordering parts......................................................................... 57
6.1 Determining valid orderable parts....................................57
Part identification.....................................................................58
7.1 Description.......................................................................58
7.2 Format............................................................................. 58
7.3 Fields............................................................................... 58
7.4 Example...........................................................................59
7.5 Small package marking................................................... 59
Terminology and guidelines.................................................... 60
8.1 Definition: Operating requirement....................................60
8.2 Definition: Operating behavior......................................... 61
8.3 Definition: Attribute.......................................................... 61
8.4 Definition: Rating............................................................. 61
8.5 Result of exceeding a rating............................................ 62
8.6 Relationship between ratings and operating
requirements....................................................................62
8.7 Guidelines for ratings and operating requirements..........63
8.8 Definition: Typical value...................................................63
8.9 Typical value conditions.................................................. 64
9 Revision History...................................................................... 65
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
5
Freescale Semiconductor, Inc.
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
155
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VDD + 0.3
V
VAIO
Analog1,
–0.3
VDD + 0.3
V
ID
VDDA
RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
VREGIN
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
General
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.71 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.71 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
VBAT
VIH
VIL
RTC battery supply voltage
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
I/O pin DC injection current — single pin
1
mA
• VIN < VSS-0.3V (Negative current injection)
-3
—
—
+3
-25
—
—
+25
1.2
—
V
VPOR_VBAT
—
V
• VIN > VDD+0.3V (Positive current injection)
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
VRAM
VRFVBAT
Notes
VDD voltage required to retain RAM
VBAT voltage required to retain the VBAT register file
mA
1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VINVAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative
injection currents.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Notes
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
7
Freescale Semiconductor, Inc.
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1,
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
—
V
VDD – 0.5
—
V
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
Table continues on the next page...
8
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
0.5
V
—
100
mA
• @ full temperature range
—
1.0
μA
• @ 25 °C
—
0.1
μA
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
Notes
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
1
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
IOZ
Total Hi-Z (off-state) leakage current (all input pins)
—
4
μA
RPU
Internal pullup resistors
22
50
kΩ
2
RPD
Internal pulldown resistors
22
50
kΩ
3
1. Tested by ganged leakage method
2. Measured at Vinput = VSS
3. Measured at Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
CPU and system clocks = 50 MHz
Bus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
After a POR event, amount of time from the point
VDD reaches 1.71 V to execution of the first
instruction across the operating temperature range
of the chip.
—
Max.
Unit
Notes
μs
1
300
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
9
Freescale Semiconductor, Inc.
General
Table 5. Power mode transition operating behaviors (continued)
Symbol
Description
• 1.71 V/(VDD slew rate) ≤ 300 μs
Min.
Max.
—
1.7 V / (VDD
slew rate)
—
150
μs
—
150
μs
—
79
μs
—
79
μs
—
6
μs
—
5.2
μs
—
5.2
μs
• 1.71 V/(VDD slew rate) > 300 μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
Unit
Notes
1. Normal boot (FTFL_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8 V
• @ 3.0 V
IDD_RUN
Min.
2
—
12.98
14
mA
—
12.93
13.8
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8 V
3, 4
—
17.04
19.3
mA
—
17.01
18.9
mA
—
19.8
21.3
mA
• @ 3.0 V
• @ 25°C
• @ 125°C
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
7.95
9.5
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
5.88
7.4
mA
5
IDD_STOP
Stop mode current at 3.0 V
—
320
436
μA
Table continues on the next page...
10
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
•
•
•
•
Min.
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C
Typ.
Max.
360
489
410
620
Unit
Notes
610
1100
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
754
—
μA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.1
—
mA
7
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
437
—
μA
8
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
7.33
24.2
14
32
28
48
110
280
3.14
4.8
6.48
28.3
13.85
44.6
55.53
71.3
2.19
3.4
4.35
4.35
8.92
24.6
35.33
45.3
1.77
3.1
2.81
13.8
5.20
22.3
19.88
34.2
1.03
1.8
1.92
7.5
4.03
15.9
17.43
28.7
0.543
1.1
1.36
7.58
3.39
14.3
16.52
24.1
0.359
0.95
1.03
6.8
2.87
15.4
IDD_LLS
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
•
•
•
•
—
—
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
—
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 50°C
—
μA
μA
μA
μA
μA
μA
μA
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
11
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
• @ 70°C
• @ 105°C
IDD_VBAT
Average current when CPU is not accessing
RTC registers at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
Typ.
Max.
15.20
25.3
0.91
1.1
1.1
1.35
1.5
1.85
4.3
5.7
Unit
Notes
μA
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
3. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, and peripherals are in active operation.
4. Max values are measured with CPU executing DSP instructions
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
7. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
9. Includes 32 kHz oscillator current and RTC operation.
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
•
MCG in FBE mode
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFL
12
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
General
Figure 3. Run mode supply current vs. core frequency
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
13
Freescale Semiconductor, Inc.
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors 1
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
19
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
21
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
19
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
11
dBμV
IEC level
0.15–1000
L
—
VRE_IEC
3, 4
1. This data was collected on a MK20DN128VLH5 64pin LQFP device.
2. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
14
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
General
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
3. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 48 MHz, fBUS = 48MHz
4. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
50
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
Notes
Normal run mode
fSYS
fBUS
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
15
Freescale Semiconductor, Inc.
General
Table 9. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
fLPTMR_pin
fLPTMR_ERCLK LPTMR external reference clock
—
16
MHz
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
13
ns
• 2.7 ≤ VDD ≤ 3.6V
—
7
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Port rise and fall time (low drive strength)
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
—
36
ns
• Slew enabled
16
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
General
Table 10. General switching specifications
Symbol
Description
• 1.71 ≤ VDD ≤ 2.7V
Min.
Max.
Unit
—
24
ns
Notes
• 2.7 ≤ VDD ≤ 3.6V
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
2.4.2 Thermal attributes
Board type
Symbol
Description
121 MAPBGA
Unit
Notes
Single-layer (1s)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
79
°C/W
1, 2
Four-layer (2s2p)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
46
°C/W
1, 3
Single-layer (1s)
RθJMA
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
67
°C/W
1,3
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
17
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Board type
Symbol
Description
121 MAPBGA
Unit
Notes
Four-layer (2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
42
°C/W
1,3
—
RθJB
Thermal
resistance,
junction to board
29
°C/W
4
—
RθJC
Thermal
resistance,
junction to case
21
°C/W
5
—
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
4
°C/W
6
NOTES:
1. Junction temperature is a function of die size, on-chip power dissipation, package
thermal resistance, mounting site (board) temperature, ambient temperature, air
flow, power dissipation of other components on the board, and board thermal
resistance.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air) with the
single layer board horizontal. Board meets JESD51-9 specification.
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuit Thermal
Test Method Environmental Conditions—Forced Convection (Moving Air) with the
board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental Conditions—Junction-to-Board. Board temperature is
measured on the top surface of the board near the package.
5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,
Microcircuits, with the cold plate temperature used for the case temperature. The
value includes the thermal resistance of the interface material between the top of
the package and the cold plate.
6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
18
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 JTAG electricals
Table 12. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 13. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
19
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J2
TCLK cycle period
1/J1
—
ns
J3
TCLK clock pulse width
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 5. Test clock input timing
20
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 6. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 7. Test Access Port timing
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
21
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 8. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 14. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
1, 2
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
(3/5) x
fints_t
—
—
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
Table continues on the next page...
22
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
Min.
Typ.
Max.
Unit
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
100
MHz
—
1200
—
µA
—
700
—
µA
2.0
—
4.0
MHz
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5,6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
8
8
9
• fvco = 48 MHz
—
120
—
ps
• fvco = 100 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
9
—
1350
—
ps
—
600
—
ps
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
• fvco = 48 MHz
• fvco = 100 MHz
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high-gain mode (HGO=1)
1
Table continues on the next page...
24
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• 32 kHz
—
5
—
μA
• 4 MHz
—
500
—
μA
• 8 MHz (RANGE=01)
—
600
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Notes
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Vpp5
1.
2.
3.
4.
5.
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
25
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.3.2.2
Symbol
Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.3.3 32 kHz oscillator electrical characteristics
3.3.3.1
32 kHz oscillator DC electrical specifications
Table 17. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Table continues on the next page...
26
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 17. 32kHz oscillator DC electrical specifications (continued)
Symbol
Min.
Typ.
Max.
Unit
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
Description
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.3.2
Symbol
fosc_lo
tstart
32 kHz oscillator frequency specifications
Table 18. 32 kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
1
700
—
VBAT
mV
2, 3
vec_extal32 Externally provided input clock amplitude
Notes
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 19. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
—
104
904
ms
1
thversblk256k Erase Block high-voltage time for 256 KB
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
27
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Symbol
Flash timing specifications — commands
Table 20. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
Read 1s Block execution time
Notes
—
trd1blk64k
• 64 KB data flash
—
—
0.9
ms
trd1blk256k
• 256 KB program flash
—
—
1.7
ms
trd1sec2k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
Erase Flash Block execution time
2
tersblk64k
• 64 KB data flash
—
58
580
ms
tersblk256k
• 256 KB program flash
—
122
985
ms
—
14
114
ms
tersscr
Erase Flash Sector execution time
Program Section execution time
2
—
tpgmsec512
• 512 bytes flash
—
2.4
—
ms
tpgmsec1k
• 1 KB flash
—
4.7
—
ms
tpgmsec2k
• 2 KB flash
—
9.3
—
ms
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
—
trdonce
Read Once execution time
—
—
25
μs
1
tpgmonce
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
250
2000
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
Swap Control execution time
—
tswapx01
• control code 0x01
—
200
—
μs
tswapx02
• control code 0x02
—
70
150
μs
tswapx04
• control code 0x04
—
70
150
μs
tswapx08
• control code 0x08
—
—
30
μs
Program Partition for EEPROM execution time
tpgmpart64k
• 64 KB FlexNVM
—
—
138
—
ms
Set FlexRAM Function execution time:
tsetramff
—
• Control Code 0xFF
—
70
—
μs
tsetram32k
• 32 KB EEPROM backup
—
0.8
1.2
ms
tsetram64k
• 64 KB EEPROM backup
—
1.3
1.9
ms
Byte-write to FlexRAM for EEPROM operation
Table continues on the next page...
28
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 20. Flash command timing specifications (continued)
Symbol
Description
teewr8bers
Byte-write to erased FlexRAM location
execution time
Min.
Typ.
Max.
Unit
Notes
—
175
260
μs
3
Byte-write to FlexRAM execution time:
teewr8b32k
• 32 KB EEPROM backup
teewr8b64k
• 64 KB EEPROM backup
—
—
385
1800
μs
475
2000
μs
260
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
—
Word-write to FlexRAM execution time:
—
teewr16b32k
• 32 KB EEPROM backup
—
385
1800
μs
teewr16b64k
• 64 KB EEPROM backup
—
475
2000
μs
540
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
—
Longword-write to FlexRAM execution time:
—
teewr32b32k
• 32 KB EEPROM backup
—
630
2050
μs
teewr32b64k
• 64 KB EEPROM backup
—
810
2250
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
3.4.1.3
Flash high voltage current behaviors
Table 21. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 22. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
20
100
—
years
—
Data retention after up to 1 K cycles
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
29
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 22. NVM reliability specifications (continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
50
—
years
—
20
100
—
years
—
10 K
50 K
—
cycles
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k
Data retention after up to 1 K cycles
nnvmcycd
Cycling endurance
5
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
—
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
—
Write endurance
3
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
35 K
175 K
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
315 K
1.6 M
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
1.27 M
6.4 M
—
writes
nnvmwree4k
• EEPROM backup to FlexRAM ratio =
4096
10 M
50 M
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ °C.
3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ °C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
3.4.2 EzPort switching specifications
Table 23. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
30
Freescale Semiconductor, Inc.
ns
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 9. EzPort Timing Diagram
3.5 Security and integrity modules
3.5.1 DryIce Tamper Electrical Specifications
Information about security-related modules is not included in this document and is
available only after a nondisclosure agreement (NDA) has been signed. To request an
NDA, please contact your local Freescale sales representative.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 24 and Table 25 are achievable on
the differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
31
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.1.1
16-bit ADC operating conditions
Table 24. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
—
• All other modes
VREFL
—
• 16-bit mode
—
8
10
pF
—
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
kΩ
—
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
VREFH
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
5
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
32
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 10. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
ADC
asynchronous
clock source
fADACK
Conditions1
• ADLPC = 1, ADHSC =
0
• ADLPC = 1, ADHSC =
1
• ADLPC = 0, ADHSC =
0
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
1.2
2.4
3.9
MHz
2.4
4.0
6.1
MHz
tADACK =
1/fADACK
3.0
5.2
7.3
MHz
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
• ADLPC = 0, ADHSC =
1
Sample Time
TUE
DNL
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• 3.6 V
Table continues on the next page...
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
43
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 34. VREG electrical specifications (continued)
Symbol
Description
• Run mode
• Standby mode
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
Min.
Typ.1
Max.
Unit
3
3.3
3.6
V
2.1
2.8
3.6
V
2.1
—
3.6
V
1.76
2.2
8.16
μF
COUT
External output capacitor
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
Notes
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
3.8.4 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 35. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
44
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
DSPI_SIN
Data
First data
Last data
DS5
DSPI_SOUT
DS6
First data
Data
Last data
Figure 17. DSPI classic SPI timing — master mode
Table 36. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DSPI_SOUT
First data
DS13
DSPI_SIN
DS12
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 18. DSPI classic SPI timing — slave mode
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
45
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.8.5 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 37. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
12.5
MHz
4 x tBUS
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
20.5
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS7
(CPOL=0)
DSPI_SIN
DS8
Data
First data
Last data
DS5
DSPI_SOUT
First data
DS6
Data
Last data
Figure 19. DSPI classic SPI timing — master mode
46
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Peripheral operating requirements and behaviors
Table 38. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
6.25
MHz
8 x tBUS
—
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
19
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DSPI_SOUT
First data
DS13
DSPI_SIN
DS12
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 20. DSPI classic SPI timing — slave mode
3.8.6 I2C switching specifications
See General switching specifications.
3.8.7 UART switching specifications
See General switching specifications.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
47
Freescale Semiconductor, Inc.
I2S switching specifications
3.8.8 I2S switching specifications
3.8.8.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 39. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 21. I2S/SAI timing — master modes
48
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
I2S switching specifications
Table 40. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
29
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
21
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 22. I2S/SAI timing — slave modes
3.8.8.2
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
49
Freescale Semiconductor, Inc.
I2S switching specifications
Table 41. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
75
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 23. I2S/SAI timing — master modes
Table 42. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
S11
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
Table continues on the next page...
50
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Dimensions
Table 42. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
Max.
Unit
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
87
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 24. I2S/SAI timing — slave modes
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
51
Freescale Semiconductor, Inc.
Pinout
If you want the drawing for this package
Then use this document number
81-pin MAPBGA
98ASA00344D
121-pin MAPBGA
98ASA00344D
169-pin MAPBGA
98ASA00628D
5 Pinout
5.1 K21 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
•
•
•
•
•
•
NOTE
The analog input signals ADC0_SE10, ADC0_SE11,
ADC0_DP1, and ADC0_DM1 are available only for K11,
K12, K21, and K22 devices and are not present on K10
and K20 devices.
The TRACE signals on PTE0, PTE1, PTE2, PTE3, and
PTE4 are available only for K11, K12, K21, and K22
devices and are not present on K10 and K20 devices.
If the VBAT pin is not used, the VBAT pin should be left
floating. Do not connect VBAT pin to VSS.
The FTM_CLKIN signals on PTB16 and PTB17 are
available only for K11, K12, K21, and K22 devices and is
not present on K10 and K20 devices. For K22D devices
this signal is on ALT4, and for K22F devices, this signal
is on ALT7.
The FTM0_CH2 signal on PTC5/LLWU_P9 is available
only for K11, K12, K21, and K22 devices and is not
present on K10 and K20 devices.
The I2C0_SCL signal on PTD2/LLWU_P13 and
I2C0_SDA signal on PTD3 are available only for K11,
K12, K21, and K22 devices and are not present on K10
and K20 devices.
52
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Pinout
121
MAP
BGA
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
E4
ADC0_SE10
ADC0_SE10
PTE0
SPI1_PCS1
UART1_TX
TRACE_
CLKOUT
I2C1_SDA
RTC_CLKOUT
E3
ADC0_SE11
ADC0_SE11
PTE1/
LLWU_P0
SPI1_SOUT
UART1_RX
TRACE_D3
I2C1_SCL
SPI1_SIN
E2
ADC0_DP1
ADC0_DP1
PTE2/
LLWU_P1
SPI1_SCK
UART1_CTS_b
TRACE_D2
F4
ADC0_DM1
ADC0_DM1
PTE3
SPI1_SIN
UART1_RTS_b
TRACE_D1
H7
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
TRACE_D0
G4
DISABLED
PTE5
SPI1_PCS2
UART3_RX
E6
VDD
VDD
G7
VSS
VSS
K3
ADC0_SE4a
ADC0_SE4a
PTE16
SPI0_PCS0
UART2_TX
FTM_CLKIN0
FTM0_FLT3
H4
ADC0_SE5a
ADC0_SE5a
PTE17
SPI0_SCK
UART2_RX
FTM_CLKIN1
LPTMR0_ALT3
A11
ADC0_SE6a
ADC0_SE6a
PTE18
SPI0_SOUT
UART2_CTS_b I2C0_SDA
A10
ADC0_SE7a
ADC0_SE7a
PTE19
SPI0_SIN
UART2_RTS_b I2C0_SCL
L6
VSS
VSS
F1
USB0_DP
USB0_DP
F2
USB0_DM
USB0_DM
G1
VOUT33
VOUT33
G2
VREGIN
VREGIN
K1
ADC0_DP0
ADC0_DP0
K2
ADC0_DM0
ADC0_DM0
L1
ADC0_DP3
ADC0_DP3
L2
ADC0_DM3
ADC0_DM3
F5
VDDA
VDDA
G5
VREFH
VREFH
G6
VREFL
VREFL
F6
VSSA
VSSA
L3
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
K5
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
L7
TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
H5
TAMPER1
TAMPER1
J5
TAMPER2
TAMPER2
L4
XTAL32
XTAL32
L5
EXTAL32
EXTAL32
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
EzPort
SPI1_SOUT
53
Freescale Semiconductor, Inc.
Pinout
121
MAP
BGA
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
K6
VBAT
VBAT
J6
JTAG_TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_CTS_ FTM0_CH5
b/
UART0_COL_b
JTAG_TCLK/
SWD_CLK
EZP_CLK
H8
JTAG_TDI/
EZP_DI
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
J7
JTAG_TDO/
TRACE_SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
TRACE_SWO
EZP_DO
H9
JTAG_TMS/
SWD_DIO
PTA3
UART0_RTS_b FTM0_CH0
J8
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
K7
DISABLED
PTA5
K8
DISABLED
L8
JTAG_TMS/
SWD_DIO
FTM0_CH1
FTM0_CH2
I2S0_TX_BCLK JTAG_TRST_b
PTA12
FTM1_CH0
I2S0_TXD0
FTM1_QD_
PHA
DISABLED
PTA13/
LLWU_P4
FTM1_CH1
I2S0_TX_FS
FTM1_QD_
PHB
K9
DISABLED
PTA14
SPI0_PCS0
UART0_TX
I2S0_RX_
BCLK
I2S0_TXD1
L9
DISABLED
PTA15
SPI0_SCK
UART0_RX
I2S0_RXD0
J10
DISABLED
PTA16
SPI0_SOUT
UART0_CTS_
b/
UART0_COL_b
I2S0_RX_FS
H10 DISABLED
PTA17
SPI0_SIN
UART0_RTS_b
I2S0_MCLK
L10
VDD
VDD
K10
VSS
VSS
USB_CLKIN
NMI_b
L11
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
K11
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
J11
RESET_b
RESET_b
ADC0_SE8
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
G10 ADC0_SE9
ADC0_SE9
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_
PHB
G9
ADC0_SE12
ADC0_SE12
PTB2
I2C0_SCL
UART0_RTS_b
FTM0_FLT3
G8
ADC0_SE13
ADC0_SE13
PTB3
I2C0_SDA
UART0_CTS_
b/
UART0_COL_b
FTM0_FLT0
D10 DISABLED
PTB10
SPI1_PCS0
UART3_RX
FTM0_FLT1
C10 DISABLED
PTB11
SPI1_SCK
UART3_TX
B11
DISABLED
PTB12
UART3_RTS_b FTM1_CH0
FTM0_CH4
FTM1_QD_
PHA
C11 DISABLED
PTB13
UART3_CTS_b FTM1_CH1
FTM0_CH5
FTM1_QD_
PHB
Freescale Semiconductor, Inc.
I2S0_RXD1
LPTMR0_ALT1
G11 ADC0_SE8
54
EZP_CS_b
FTM0_FLT2
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Pinout
121
MAP
BGA
Default
ALT0
B10
DISABLED
PTB16
SPI1_SOUT
UART0_RX
EWM_IN
FTM_CLKIN0
E9
DISABLED
PTB17
SPI1_SIN
UART0_TX
EWM_OUT_b
FTM_CLKIN1
D9
DISABLED
PTB18
FTM2_CH0
I2S0_TX_BCLK
C9
DISABLED
PTB19
FTM2_CH1
I2S0_TX_FS
B9
ADC0_SE14
ADC0_SE14
PTC0
SPI0_PCS4
PDB0_EXTRG
I2S0_TXD1
D8
ADC0_SE15
ADC0_SE15
PTC1/
LLWU_P6
SPI0_PCS3
UART1_RTS_b FTM0_CH0
I2S0_TXD0
C8
ADC0_SE4b/
CMP1_IN0
ADC0_SE4b/
CMP1_IN0
PTC2
SPI0_PCS2
UART1_CTS_b FTM0_CH1
I2S0_TX_FS
B8
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
G3
VSS
VSS
E5
VDD
VDD
A8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
CMP1_OUT
D7
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_ALT2 I2S0_RXD0
CMP0_OUT
C7
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_EXTRG
I2S0_RX_
BCLK
I2S0_MCLK
B7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB_SOF_
OUT
I2S0_RX_FS
A7
CMP0_IN2
CMP0_IN2
PTC8
I2S0_MCLK
D6
CMP0_IN3
CMP0_IN3
PTC9
I2S0_RX_
BCLK
C6
DISABLED
PTC10
I2C1_SCL
I2S0_RX_FS
C5
DISABLED
PTC11/
LLWU_P11
I2C1_SDA
I2S0_RXD1
B6
DISABLED
PTC12
A6
DISABLED
PTC13
D5
DISABLED
PTC16
C4
DISABLED
PTC17
D4
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
UART2_RTS_b
D3
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_b
C3
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
I2C0_SCL
B3
DISABLED
PTD3
SPI0_SIN
UART2_TX
I2C0_SDA
A3
ADC0_SE21
ADC0_SE21
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_b FTM0_CH4
EWM_IN
A2
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_CTS_ FTM0_CH5
b/
UART0_COL_b
EWM_OUT_b
ADC0_SE5b
ALT1
ALT2
ALT3
ALT4
ALT5
CLKOUT
ALT6
ALT7
EzPort
I2S0_TX_BCLK
FTM0_CH2
FTM2_FLT0
UART3_RX
UART3_TX
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
55
Freescale Semiconductor, Inc.
Pinout
121
MAP
BGA
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
B2
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM0_FLT0
A1
ADC0_SE22
ADC0_SE22
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
FTM0_FLT1
F3
NC
NC
H1
NC
NC
H2
NC
NC
J1
NC
NC
J2
NC
NC
J3
NC
NC
H3
NC
NC
K4
NC
NC
H6
NC
NC
J9
NC
NC
J4
NC
NC
H11 NC
NC
F11
NC
NC
E11
NC
NC
D11 NC
NC
E10
NC
NC
F10
NC
NC
F9
NC
NC
F8
NC
NC
E8
NC
NC
E7
NC
NC
F7
NC
NC
A5
NC
NC
B5
NC
NC
B4
NC
NC
A4
NC
NC
A9
NC
NC
B1
NC
NC
C2
NC
NC
C1
NC
NC
D2
NC
NC
D1
NC
NC
E1
NC
NC
56
Freescale Semiconductor, Inc.
ALT7
EzPort
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Ordering parts
5.2 K21 Pinouts
The below figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
1
2
3
4
5
6
7
8
9
10
11
A
PTD7
PTD5
PTD4/
LLWU_P14
NC
NC
PTC13
PTC8
PTC4/
LLWU_P8
NC
PTE19
PTE18
A
B
NC
PTD6/
LLWU_P15
PTD3
NC
NC
PTC12
PTC7
PTC3/
LLWU_P7
PTC0
PTB16
PTB12
B
C
NC
NC
PTD2/
LLWU_P13
PTC17
PTC11/
LLWU_P11
PTC10
PTC6/
LLWU_P10
PTC2
PTB19
PTB11
PTB13
C
D
NC
NC
PTD1
PTD0/
LLWU_P12
PTC16
PTC9
PTC5/
LLWU_P9
PTC1/
LLWU_P6
PTB18
PTB10
NC
D
E
NC
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTE0
VDD
VDD
NC
NC
PTB17
NC
NC
E
F
USB0_DP
USB0_DM
NC
PTE3
VDDA
VSSA
NC
NC
NC
NC
NC
F
G
VOUT33
VREGIN
VSS
PTE5
VREFH
VREFL
VSS
PTB3
PTB2
PTB1
PTB0/
LLWU_P5
G
H
NC
NC
NC
PTE17
TAMPER1
NC
PTE4/
LLWU_P2
PTA1
PTA3
PTA17
NC
H
J
NC
NC
NC
NC
TAMPER2
PTA0
PTA2
PTA4/
LLWU_P3
NC
PTA16
RESET_b
J
PTE16
NC
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
VBAT
PTA5
PTA12
PTA14
VSS
PTA19
K
XTAL32
EXTAL32
VSS
PTA15
VDD
PTA18
L
4
5
6
9
10
11
K
ADC0_DP0 ADC0_DM0
L
VREF_OUT/
ADC0_DP3 ADC0_DM3 CMP1_IN5/
CMP0_IN5
1
2
3
TAMPER0/
PTA13/
RTC_
LLWU_P4
WAKEUP_B
7
8
Figure 25. K21 121 MAPBGA Pinout Diagram
6 Ordering parts
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
57
Freescale Semiconductor, Inc.
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK21 and MK21
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K21
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
•
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
Table continues on the next page...
58
Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Part identification
Field
Description
Values
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
•
•
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
16 = 168 MHz
18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MK21DN512VMC5
7.5 Small package marking
In an effort to save space, small package devices use special marking on the chip.
These markings have the following format:
Q ## C F T PP
This table lists the possible values for each field in the part number for small packages
(not all combinations are valid):
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
59
Freescale Semiconductor, Inc.
Terminology and guidelines
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
##
Kinetis family
• 1# = K11/K12
• 2# = K21/K22
C
Speed
• G = 50 MHz
F
Flash memory configuration
• G = 128 KB + Flex
• H = 256 KB + Flex
• 9 = 512 KB
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
• MC = 121 MAPBGA
This tables lists some examples of small package marking along with the original part
numbers:
Original part number
Alternate part number
MK21DX128VMC5
M21GGVMC
MK21DX256VMC5
M21GHVMC
MK21DN512VMC5
M21G9VMC
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
60
Freescale Semiconductor, Inc.
Min.
0.9
Max.
1.1
Unit
V
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Terminology and guidelines
8.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating
requirements and any other specified conditions.
8.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
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Freescale Semiconductor, Inc.
Terminology and guidelines
8.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
8.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
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Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Terminology and guidelines
8.6 Relationship between ratings and operating requirements
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Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
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(m
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
63
Freescale Semiconductor, Inc.
Terminology and guidelines
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
IWP
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
Max.
70
130
Unit
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
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Freescale Semiconductor, Inc.
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
Revision History
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
9 Revision History
The following table provides a revision history for this document.
Table 43. Revision History
Rev. No.
Date
Substantial Changes
1
6/2012
Alpha customer release.
2
7/2012
•
•
•
•
•
•
Updated section "Power consumption operating behaviors".
Updated section "Flash timing specifications — program and erase".
Updated section "Flash timing specifications — commands".
Removed the 32K ratio from "Write endurance" in section "Reliability specifications".
Updated IDDstby maximum value in section "VREG electrical specifications".
Added the charts in section "Diagram: Typical IDD_RUN operating behavior".
3
8/2012
•
•
•
•
Updated section "Power consumption operating behaviors".
Updated section "EMC radiated emissions operating behaviors".
Updated section "MCG specifications".
Added applicable notes in section "Signal Multiplexing and Pin Assignments".
4
12/2012
•
•
•
•
Updated section "Power consumption operating behaviors"
Updated section "MCG specifications"
Updated section "16-bit ADC operating conditions"
Added section "Small package marking"
5
01/2014
•
•
•
•
•
Updated supported part numbers.
Updated section "Power mode transition operating behaviors"
Updated section "MCG specifications"
Updated section "Oscillator DC electrical specifications"
Updated section "Oscillator frequency specifications"
6
03/2014
• Initial public release
Kinetis K21D Sub-Family Data Sheet, Rev6, 04/2014.
65
Freescale Semiconductor, Inc.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, Freescale logo, and Kinetis are trademarks of Freescale
Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or
service names are the property of their respective owners. ARM and
Cortex are registered trademarks of ARM Limited (or its subsidiaries) in
the EU and/or elsewhere.
©2012-2014 Freescale Semiconductor, Inc.
Document number:
K21P121M50SF4V2
Revision 6, 04/2014
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