Freescale Semiconductor, Inc.
Data Sheet: Technical Data
K21P144M120SF5
Rev 4, 11/2014
Kinetis K21F Sub-Family Data
Sheet
120 MHz ARM® Cortex®-M4-based Microcontroller with FPU
The K21 product family members are optimized for cost-sensitive
applications requiring low-power, USB connectivity, processing
efficiency with floating point unit and the need for extensive
tamper protection, such as Electronic Point of Sales. It shares
the comprehensive enablement and scalability of the Kinetis
family. This product offers:
• Up to 1 MB of flash memory with up to 128 KB of SRAM
• DryIce Tamper Detection with active/passive pin,
temperature, clock, supply voltage monitoring
• Run power consumption down to 279 μA/MHz. Static
power consumption down to 5.1 μA with full state retention
and 5 μs wakeup. Lowest Static mode down to 268 nA
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
voltage regulator
Performance
• Up to 120 MHz ARM Cortex-M4-based core with DSP
instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• Up to 1 MB program flash memory and 128 KB RAM
• Up to 128 KB FlexNVM and 4 KB FlexRAM on
FlexMemory devices
• FlexBus external bus interface
System peripherals
• Multiple low-power modes; low leakage wakeup unit
• Memory protection unit with multi-master protection
• 16-channel DMA controller
• External watchdog monitor and software watchdog
Security and integrity modules
• Hardware CRC module
• Tamper detect and secure storage
• Hardware random-number generator
• Hardware encryption
• 128-bit unique identification (ID) number per chip
Analog modules
• Two 16-bit SAR ADCs
• Two 12-bit DACs
MK21FX512VLQ12
MK21FN1M0VLQ12
MK21FX512VMD12
MK21FN1M0VMD12
144 LQFP
144 BGA
20 x 20 x 1.6 mm Pitch 13 x 13 x 1.7 mm Pitch
0.5 mm
1 mm
Communication interfaces
• USB full-/low-speed On-the-Go controller
• USB Device Charger detect
• Controller Area Network (CAN) module
• Three SPI modules
• Three I2C modules
• Six UART modules
• Secure Digital host controller (SDHC)
• I2S module
Timers
• Two 8-channel Flex-Timers (PWM/Motor Control)
• Two 2-channel Flex-Timers (PWM/Quad Decoder)
• Periodic interrupt timers and 16-bit low-power timer
• Carrier modulator transmitter
• Real-time clock
• Programmable delay block
Clocks
• 3 to 32 MHz and 32 kHz crystal oscillator
• PLL, FLL, and multiple internal oscillators
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2013–2015 Freescale
Semiconductor, Inc. All rights reserved.
• Three analog comparators (CMP)
• Voltage reference
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MK21FX512VLQ12
512 KB
128
104
MK21FN1M0VLQ12
1 MB
128
104
MK21FX512VMD12
512 KB
128
104
MK21FN1M0VMD12
1 MB
128
104
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K20PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K21P144M50SF5RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
K21P144M50SF51
Package
drawing
Package dimensions are provided in package drawings.
• LQFP 144-pin:
98ASS23177W1
• MAPBGA 144-pin:
98ASA00222D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Kinetis K21D Family
ARM ® Cortex™-M4
Core
System
Memories and Memory Interfaces
Internal
and external
watchdogs
Program
flash
RAM
Clocks
Phaselocked loop
Debug
interfaces
DSP
DMA
FlexMemory
Frequencylocked loop
Interrupt
controller
Floating
point
Low-leakage
wakeup
Serial
programming
interface
Low/high
frequency
oscillators
Internal
reference
clocks
Security
and Integrity
CRC
Analog
16-bit ADC
Timers
Communication Interfaces
2
2
FlexTimers
I C
I S
Carrier
modulator
transmitter
UART
USB OTG
LS/FS/HS
SPI
USB LS/FS
transceiver
Random
number
generator
Analog
comparator
Hardware
encryption
6-bit DAC
Tamper
detect
12-bit DAC
Periodic
interrupt
timers
USB charger
detect
Voltage
reference
Low power
timer
USB voltage
regulator
Programmable
delay block
Human-Machine
Interface (HMI)
GPIO
Independent
real-time
clock
Figure 1. K20 block diagram
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1
Voltage and current operating requirements.....7
2.2.2
LVD and POR operating requirements............. 8
2.2.3
Voltage and current operating behaviors.......... 9
2.2.4
Power mode transition operating behaviors......10
2.2.5
Power consumption operating behaviors.......... 11
2.2.6
EMC radiated emissions operating behaviors...15
2.2.7
Designing with radiated emissions in mind....... 16
2.2.8
Capacitance attributes...................................... 16
2.3 Switching specifications...................................................16
2.3.1
Device clock specifications............................... 16
2.3.2
General switching specifications....................... 17
2.4 Thermal specifications..................................................... 18
2.4.1
Thermal operating requirements....................... 18
2.4.2
Thermal attributes............................................. 18
3 Peripheral operating requirements and behaviors.................. 20
3.1 Core modules.................................................................. 20
3.1.1
Debug trace timing specifications..................... 20
3.1.2
JTAG electricals................................................ 20
3.2 System modules.............................................................. 23
3.3 Clock modules................................................................. 23
3.3.1
MCG specifications........................................... 23
3.3.2
Oscillator electrical specifications..................... 26
3.3.3
32 kHz oscillator electrical characteristics.........28
3.4 Memories and memory interfaces................................... 28
4
Freescale Semiconductor, Inc.
4
5
6
7
8
3.4.1
Flash (FTFE) electrical specifications............... 28
3.4.2
EzPort switching specifications......................... 33
3.4.3
Flexbus switching specifications....................... 34
3.5 Security and integrity modules........................................ 37
3.5.1
DryIce Tamper Electrical Specifications............37
3.6 Analog............................................................................. 38
3.6.1
ADC electrical specifications.............................38
3.6.2
CMP and 6-bit DAC electrical specifications.....42
3.6.3
12-bit DAC electrical characteristics................. 44
3.6.4
Voltage reference electrical specifications........ 47
3.7 Timers..............................................................................48
3.8 Communication interfaces............................................... 48
3.8.1
USB electrical specifications............................. 48
3.8.2
USB DCD electrical specifications.................... 49
3.8.3
USB VREG electrical specifications..................49
3.8.4
CAN switching specifications............................ 50
3.8.5
DSPI switching specifications (limited voltage
range)................................................................50
3.8.6
DSPI switching specifications (full voltage
range)................................................................52
3.8.7
I2C switching specifications.............................. 53
3.8.8
UART switching specifications.......................... 54
3.8.9
SDHC specifications......................................... 54
3.8.10 I2S switching specifications.............................. 55
Dimensions............................................................................. 67
4.1 Obtaining package dimensions....................................... 67
Pinout...................................................................................... 68
5.1 K21 Signal Multiplexing and Pin Assignments.................68
5.2 K21 Pinouts..................................................................... 74
Revision History...................................................................... 76
Copyright................................................................................. 0
Legal....................................................................................... 0
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
5
Freescale Semiconductor, Inc.
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
5.5
V
VAIO
Analog1,
–0.3
VDD + 0.3
V
ID
VDDA
RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
6
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
General
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.71 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.71 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VBAT
VIH
VIL
RTC battery supply voltage
Notes
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICDIO
Digital pin (except Tamper pins) negative DC
injection current — single pin
1
• VIN < VSS-0.3V
IICAIO
IICcont
Analog2, EXTAL, and XTAL pin DC injection current
— single pin
3
mA
• VIN < VSS-0.3V (Negative current injection)
-5
—
• VIN > VDD+0.3V (Positive current injection)
—
+5
-25
—
—
+25
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
mA
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
4
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
7
Freescale Semiconductor, Inc.
General
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|
IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection
currents.
4. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
8
Freescale Semiconductor, Inc.
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
General
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Typ
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA
VDD – 0.5
—
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
—
V
—
—
100
mA
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOH_Tamper Output high voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
VBAT – 0.5
VBAT – 0.5
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
Output high voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
VOL
—
—
—
—
VBAT – 0.5
VBAT – 0.5
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
IOH_Tamper Output high current total for Tamper pins
V
—
V
V
—
—
—
—
—
100
V
mA
Output low voltage — high drive strength
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
—
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
V
—
—
100
mA
0.5
V
0.5
V
0.5
V
0.5
V
100
mA
Output low voltage — low drive strength
IOLT
Output low current total for all ports
VOL_Tamper Output low voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
—
—
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
—
—
Output low voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
—
—
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
—
—
—
—
IOL_Tamper Output low current total for Tamper pins
IIND
2,
Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
• All digital pins
—
0.002
0.5
3
μA
Table continues on the next page...
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
9
Freescale Semiconductor, Inc.
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Typ
Max.
Unit
—
0.002
0.5
μA
—
0.004
1
μA
Notes
• VIN = VDD
• All digital pins except PTD7
• PTD7
IIND
Input leakage current, digital pins
• VIL < VIN < VDD
2
• VDD = 3.6 V
—
18
26
μA
• VDD = 3.0 V
—
12
19
μA
• VDD = 2.5 V
—
8
13
μA
• VDD = 1.7 V
—
3
6
μA
Input leakage current, digital pins
• VDD < VIN < 5.5 V
—
1
50
μA
IIN_Tamper Input leakage current (per Tamper pin) for full
temperature range
—
—
1
μA
IIN_Tamper Input leakage current (per Tamper pin) at 25°C
—
—
0.025
μA
—
—
0.25
μA
—
—
0.25
μA
IIND
IOZ
Hi-Z (off-state) leakage current (per pin)
IOZ_Tamper Hi-Z (off-state) leakage current (per Tamper
pin)
1.
2.
3.
4.
5.
RPU
Internal pullup resistors (except Tamper pins)
20
35
50
kΩ
4
RPD
Internal pulldown resistors (except Tamper
pins)
20
35
50
kΩ
5
Open drain outputs must be pulled to VDD.
Measured at VDD=3.6V
Internal pull-up/pull-down resistors disabled.
Measured at VDD supply voltage = VDD min and Vinput = VSS
Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
10
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point
VDD reaches 1.71 V to execution of the first
instruction across the operating temperature range
of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
Min.
Max.
Unit
—
300
μs
—
183
μs
—
183
μs
—
105
μs
—
105
μs
—
5.0
μs
—
4.4
μs
—
4.4
μs
Notes
2.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN
Min.
2
—
33.57
36.2
mA
—
33.51
36.1
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
3, 4
—
46.36
50.1
mA
—
46.31
49.9
mA
—
57.4
—
mA
• @ 125°C
IDD_WAIT
Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
—
18.2
—
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
7.2
—
mA
5
Table continues on the next page...
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
11
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
—
1.21
—
mA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
—
1.88
—
mA
7
—
0.80
—
mA
8
• @ –40 to 25°C
—
0.528
2.25
mA
• @ 70°C
—
1.6
8
mA
• @ 105°C
—
5.2
20
mA
• @ –40 to 25°C
—
78
700
μA
• @ 70°C
—
498
2400
μA
• @ 105°C
—
1300
3600
μA
• @ –40 to 25°C
—
5.1
15
μA
• @ 70°C
—
28
80
μA
• @ 105°C
—
124
300
μA
• @ –40 to 25°C
—
3.1
7.5
μA
• @ 70°C
—
14.5
45
μA
• @ 105°C
—
63.5
195
μA
• @ –40 to 25°C
—
2.0
5
μA
• @ 70°C
—
6.9
32
μA
• @ 105°C
—
30
112
μA
• @ –40 to 25°C
—
1.25
2.1
μA
• @ 70°C
—
6.5
18.5
μA
• @ 105°C
—
37
108
μA
—
0.745
1.65
μA
—
6.03
18
μA
—
37
108
μA
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
IDD_STOP
IDD_VLPS
IDD_LLS
Stop mode current at 3.0 V
Very-low-power stop mode current at 3.0 V
Low leakage stop mode current at 3.0 V
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
Table continues on the next page...
12
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
0.268
1.25
μA
—
3.7
15
μA
—
22.9
95
μA
—
0.19
0.22
μA
—
0.49
0.64
μA
—
2.2
3.2
μA
Notes
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current with RTC and 32kHz disabled
at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current when CPU is not accessing
RTC registers
9
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
0.68
0.8
μA
—
1.2
1.56
μA
—
3.6
5.3
μA
—
0.81
0.96
μA
—
1.45
1.89
μA
—
4.3
6.33
μA
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus 40 Mhz and FlexBus clock, and 24 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Includes 32kHz oscillator current and RTC operation.
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in PEE mode at greater than 100 MHz frequencies
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
13
Freescale Semiconductor, Inc.
General
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
14
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
23
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
27
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
28
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
14
dBμV
IEC level
0.15–1000
K
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
15
Freescale Semiconductor, Inc.
General
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
120
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
60
MHz
FlexBus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
Notes
Normal run mode
fSYS
fSYS_USB
fBUS
FB_CLK
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
Table continues on the next page...
16
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
General
Table 9. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
FB_CLK
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
0.8
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
fLPTMR_ERCLK LPTMR external reference clock
fLPTMR_pin
—
16
MHz
fFlexCAN_ERCLK FlexCAN external reference clock
—
8
MHz
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous
path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous
path
16
—
ns
3
External reset pulse width (digital glitch filter
disabled)
100
—
ns
3
Mode select (EZP_CS) hold time after reset
deassertion
2
—
Bus clock
cycles
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Table continues on the next page...
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
17
Freescale Semiconductor, Inc.
General
Table 10. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
Notes
Port rise and fall time (low drive strength)
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can
be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
2.4.2 Thermal attributes
Board type
Symbol
Description
144 LQFP
144 MAPBGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
45
48
°C/W
1
Four-layer
(2s2p)
RθJA
Thermal
resistance,
36
29
°C/W
1
Table continues on the next page...
18
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
General
Board type
Symbol
Description
144 LQFP
144 MAPBGA
Unit
Notes
junction to
ambient
(natural
convection)
Single-layer
(1s)
RθJMA
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
36
38
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
30
25
°C/W
1
—
RθJB
Thermal
resistance,
junction to
board
24
16
°C/W
2
—
RθJC
Thermal
9
resistance,
junction to case
9
°C/W
3
—
ΨJT
Thermal
2
characterization
parameter,
junction to
package top
outside center
(natural
convection)
2
°C/W
4
Notes
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits
Thermal Test Method Environmental Conditions—Natural Convection (Still Air),
or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method
Standard, Microcircuits, with the cold plate temperature used for the case
temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits
Thermal Test Method Environmental Conditions—Natural Convection (Still Air).
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
19
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Tcyc
Clock period
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
—
ns
Th
Data hold
2
—
ns
Frequency dependent (limited
to 50 MHz)
Unit
MHz
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
20
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
3.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.6
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Unit
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 14. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Operating voltage
1.71
3.6
TCLK frequency of operation
V
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
21
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
22
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 15. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
Notes
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
± 0.5
±2
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
Internal reference (fast clock) current
—
25
—
µA
Iintf
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
1
,2
1
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
Table continues on the next page...
24
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
120
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
• fvco = 48 MHz
—
120
—
ps
• fvco = 120 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
9
• fvco = 48 MHz
—
1350
—
ps
• fvco = 120 MHz
—
600
—
ps
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
Lock detector detection time
8
9
Dlock
tpll_lock
8
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
45
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 20. Typical INL error vs. digital code
46
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
25
-40
85
105
125
Temperature °C
Figure 21. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 32. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
—
Operating temperature
range of the device
°C
—
100
nF
1, 2
TA
Temperature
CL
Output load capacitance
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
47
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 33. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915
1.195
1.1977
V
1
Vout
Voltage reference output — factory trim
1.1584
—
1.2376
V
1
Vout
Voltage reference output — user trim
1.193
—
1.197
V
1
Vstep
Voltage reference trim step
—
0.5
—
mV
1
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
80
mV
1
Bandgap only current
—
—
80
µA
1
µV
1, 2
Ibg
ΔVLOAD
Load regulation
• current = ± 1.0 mA
—
200
—
Tstup
Buffer startup time
—
—
100
µs
—
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 34. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
—
Table 35. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
Notes
1.173
1.225
V
—
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
48
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
3.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-todate standards, visit usb.org.
NOTE
The MCGFLLCLK does not meet the USB jitter
specifications for certification.
3.8.2 USB DCD electrical specifications
Table 36. USB0 DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
0.5
—
0.7
V
Threshold voltage for logic high
0.8
—
2.0
V
VLGC
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK
USB_DM sink current
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
0.33
0.4
V
3.8.3 USB VREG electrical specifications
Table 37. USB VREG electrical specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
VREGIN
Input supply voltage
2.7
—
5.5
V
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
125
186
μA
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
IDDoff
Quiescent current — Shutdown mode
—
650
—
nA
—
—
4
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and
temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
Table continues on the next page...
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
49
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 37. USB VREG electrical specifications
(continued)
Symbol
Description
• Run mode
• Standby mode
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
Min.
Typ.1
Max.
Unit
3
3.3
3.6
V
2.1
2.8
3.6
V
2.1
—
3.6
V
1.76
2.2
8.16
μF
COUT
External output capacitor
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
Notes
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
3.8.4 CAN switching specifications
See General switching specifications.
3.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
30
MHz
Notes
DS1
DSPI_SCK output cycle time
2 x tBUS
—
ns
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
Table continues on the next page...
50
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
Table 38. Master mode DSPI timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
Notes
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS1
DS2
DS4
DS8
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 22. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
Frequency of operation
15
MHz
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
—
17.4
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
16
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
16
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
51
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 23. DSPI classic SPI timing — slave mode
3.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 40. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
15
MHz
4 x tBUS
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
20.5
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
52
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
DSPI_PCSn
DS3
DS4
DS8
DS7
(CPOL=0)
DS1
DS2
DSPI_SCK
DSPI_SIN
Data
First data
DSPI_SOUT
Last data
DS5
DS6
First data
Data
Last data
Figure 24. DSPI classic SPI timing — master mode
Table 41. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
7.5
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
19
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DSPI_SOUT
First data
DS13
DSPI_SIN
DS12
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 25. DSPI classic SPI timing — slave mode
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
53
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.8.7 I2C switching specifications
See General switching specifications.
3.8.8 UART switching specifications
See General switching specifications.
3.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface. The
following timing specifications assume a load of 50 pF.
Table 42. SDHC switching specifications
Num
Symbol
Description
Operating voltage
Min.
Max.
Unit
1.71
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
8.3
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
54
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 26. SDHC timing
3.8.10 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =
0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or
the frame sync (I2S_FS) shown in the figures below.
Table 43. I2S master mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
S4
I2S_BCLK pulse width high/low
S5
80
—
ns
45%
55%
BCLK period
I2S_BCLK to I2S_FS output valid
—
15
ns
S6
I2S_BCLK to I2S_FS output invalid
0
—
ns
S7
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
15
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
55
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S6
S5
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 27. I2S timing — master mode
Table 44. I2S slave mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_BCLK cycle time (input)
80
—
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
4.5
—
ns
S14
I2S_FS input hold after I2S_BCLK
2
—
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
—
18
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1
21
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
56
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
I2S_FS (input)
S14
S15
S19
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 28. I2S timing — slave modes
3.8.10.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 45. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
20.5
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
57
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 29. I2S/SAI timing — master modes
Table 46. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
23.5
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
5.8
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
58
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 30. I2S/SAI timing — slave modes
3.8.10.2
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 47. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
—
ns
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
0
59
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 31. I2S/SAI timing — master modes
Table 48. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
—
ns
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
—
30
valid1
—
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
60
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 32. I2S/SAI timing — slave modes
3.8.10.3
3.8.10.3.1
Ordering parts
Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search for
the following device numbers: PK21 and MK21
3.8.10.4
3.8.10.4.1
Part identification
Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
3.8.10.4.2
Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
3.8.10.4.3
Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
61
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K21
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
•
•
•
•
•
•
•
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
•
•
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
16 = 168 MHz
18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
3.8.10.4.4
Example
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
This is an example part number:
MK21FN1M0VMD10
62
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
3.8.10.4.5
Small package marking
In an effort to save space, small package devices use special marking on the chip.
These markings have the following format:
Q ## C F T PP
This table lists the possible values for each field in the part number for small packages
(not all combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
##
Kinetis family
• 2# = K21/K22
C
Speed
• H = 120 MHz
F
Flash memory configuration
• K = 512 KB + Flex
• 1 = 1 MB
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
•
•
•
•
•
LL = 100 LQFP
MC = 121 MAPBGA
LQ = 144 LQFP
MD = 144 MAPBGA
DC = 121 XFBGA
This tables lists some examples of small package marking along with the original part
numbers:
Original part number
Alternate part number
MK21FN1M0VLQ12
M21H1VLQ
MK21FX512VMD12
M21HKVMD
3.8.10.5
3.8.10.5.1
Terminology and guidelines
Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation
and possibly decreasing the useful life of the chip.
3.8.10.5.1.1
Example
This is an example of an operating requirement:
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
63
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Symbol
VDD
Description
1.0 V core supply
voltage
3.8.10.5.2
Min.
0.9
Max.
1.1
Unit
V
Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
3.8.10.5.2.1
Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
3.8.10.5.3
Max.
130
Unit
µA
Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.8.10.5.3.1
Example
This is an example of an attribute:
Symbol
CIN_D
3.8.10.5.4
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
64
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
3.8.10.5.4.1
Example
This is an example of an operating rating:
Symbol
Description
VDD
1.0 V core supply
voltage
3.8.10.5.5
Max.
–0.3
Unit
1.2
V
Result of exceeding a rating
40
Failures in time (ppm)
Min.
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.8.10.5.6
Relationship between ratings and operating requirements
.)
)
e
Op
ing
rat
n.)
mi
(
ing
rat
rat
e
Op
ing
e
re
ir
qu
in.
t (m
ax
t (m
n
me
ing
rat
e
Op
.)
en
rem
re
i
qu
rat
e
Op
ing
g
tin
ra
ax
(m
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
g
lin
nd
Ha
n.)
mi
g(
in
rat
g(
ng
li
nd
Ha
in
rat
.)
x
ma
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.8.10.5.7
Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
65
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8.10.5.8
Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.10.5.8.1
Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
3.8.10.5.8.2
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
66
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Dimensions
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.8.10.5.9
Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
144-pin LQFP
Then use this document number
98ASS23177W
Table continues on the next page...
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
67
Freescale Semiconductor, Inc.
Pinout
If you want the drawing for this package
Then use this document number
144-pin MAPBGA
98ASA00222D
169-pin MAPBGA
98ASA00628D
5 Pinout
5.1 K21 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
•
•
•
•
•
•
144 144
MAP LQFP
BGA
D3
1
Pin Name
PTE0
NOTE
The analog input signals ADC0_DP2 and ADC0_DM2
on PTE2 and PTE3 are available only for K21 and K22
devices and are not present on K10 and K20 devices.
The TRACE signals on PTE0, PTE1, PTE2, PTE3, and
PTE4 are available only for K11, K12, K21, and K22
devices and are not present on K10 and K20 devices.
If the VBAT pin is not used, the VBAT pin should be left
floating. Do not connect VBAT pin to VSS.
The FTM_CLKIN signals on PTB16 and PTB17 are
available only for K11, K12, K21, and K22 devices and is
not present on K10 and K20 devices. For K22D devices
this signal is on ALT7, and for K22F devices, this signal
is on ALT4.
The FTM0_CH2 signal on PTC5/LLWU_P9 is available
only for K11, K12, K21, and K22 devices and is not
present on K10 and K20 devices.
The I2C0_SCL signal on PTD2/LLWU_P13 and
I2C0_SDA signal on PTD3 are available only for K11,
K12, K21, and K22 devices and are not present on K10
and K20 devices.
Default
ALT0
ADC1_SE4a
ADC1_SE4a
68
Freescale Semiconductor, Inc.
ALT1
PTE0
ALT2
SPI1_PCS1
ALT3
UART1_TX
ALT4
SDHC0_D1
ALT5
ALT6
ALT7
TRACE_
CLKOUT
I2C1_SDA
RTC_
CLKOUT
EzPort
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Pinout
144 144
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
I2C1_SCL
SPI1_SIN
D2
2
PTE1/
LLWU_P0
ADC1_SE5a
ADC1_SE5a
PTE1/
LLWU_P0
SPI1_SOUT
UART1_RX
SDHC0_D0
TRACE_D3
D1
3
PTE2/
LLWU_P1
ADC0_DP2/
ADC1_SE6a
ADC0_DP2/
ADC1_SE6a
PTE2/
LLWU_P1
SPI1_SCK
UART1_
CTS_b
SDHC0_
DCLK
TRACE_D2
E4
4
PTE3
ADC0_DM2/
ADC1_SE7a
ADC0_DM2/
ADC1_SE7a
PTE3
SPI1_SIN
UART1_
RTS_b
SDHC0_
CMD
TRACE_D1
E5
5
VDD
VDD
VDD
F6
6
VSS
VSS
VSS
E3
7
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
SDHC0_D3
TRACE_D0
E2
8
PTE5
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
FTM3_CH0
E1
9
PTE6
DISABLED
PTE6
SPI1_PCS3
UART3_
CTS_b
I2S0_MCLK
FTM3_CH1
F4
10
PTE7
DISABLED
PTE7
UART3_
RTS_b
I2S0_RXD0
FTM3_CH2
F3
11
PTE8
DISABLED
PTE8
I2S0_RXD1
UART5_TX
I2S0_RX_FS
FTM3_CH3
F2
12
PTE9
DISABLED
PTE9
I2S0_TXD1
UART5_RX
I2S0_RX_
BCLK
FTM3_CH4
F1
13
PTE10
DISABLED
PTE10
UART5_
CTS_b
I2S0_TXD0
FTM3_CH5
G4
14
PTE11
DISABLED
PTE11
UART5_
RTS_b
I2S0_TX_FS
FTM3_CH6
G3
15
PTE12
DISABLED
PTE12
I2S0_TX_
BCLK
FTM3_CH7
E6
16
VDD
VDD
VDD
F7
17
VSS
VSS
VSS
H3
18
VSS
VSS
VSS
H1
19
USB0_DP
USB0_DP
USB0_DP
H2
20
USB0_DM
USB0_DM
USB0_DM
G1
21
VOUT33
VOUT33
VOUT33
G2
22
VREGIN
VREGIN
VREGIN
J1
23
ADC0_DP1
ADC0_DP1
ADC0_DP1
J2
24
ADC0_DM1
ADC0_DM1
ADC0_DM1
K1
25
ADC1_DP1
ADC1_DP1
ADC1_DP1
K2
26
ADC1_DM1
ADC1_DM1
ADC1_DM1
L1
27
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
L2
28
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
M1
29
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
M2
30
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
EzPort
SPI1_SOUT
USB_SOF_
OUT
69
Freescale Semiconductor, Inc.
Pinout
144 144
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
H5
31
VDDA
VDDA
VDDA
G5
32
VREFH
VREFH
VREFH
G6
33
VREFL
VREFL
VREFL
H6
34
VSSA
VSSA
VSSA
K3
35
ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_SE22 ADC0_SE22 ADC0_SE22
J3
36
ADC0_SE16/ ADC0_SE16/ ADC0_SE16/
CMP1_IN2/ CMP1_IN2/ CMP1_IN2/
ADC0_SE21 ADC0_SE21 ADC0_SE21
M3
—
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
L3
—
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
L4
—
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
L5
37
TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
K5
38
TAMPER1
TAMPER1
TAMPER1
K4
39
TAMPER2
TAMPER2
TAMPER2
J4
—
TAMPER3
TAMPER3
TAMPER3
H4
—
TAMPER4
TAMPER4
TAMPER4
M4
—
TAMPER5
TAMPER5
TAMPER5
M7
40
XTAL32
XTAL32
XTAL32
M6
41
EXTAL32
EXTAL32
EXTAL32
L6
42
VBAT
VBAT
VBAT
—
43
VDD
VDD
VDD
—
44
VSS
VSS
VSS
—
45
PTE24
ADC0_SE17
ADC0_SE17
PTE24
UART4_TX
EWM_OUT_
b
—
46
PTE25
ADC0_SE18
ADC0_SE18
PTE25
UART4_RX
EWM_IN
—
47
PTE26
DISABLED
PTE26
UART4_
CTS_b
RTC_
CLKOUT
—
48
PTE27
DISABLED
PTE27
UART4_
RTS_b
—
49
PTE28
DISABLED
PTE28
70
Freescale Semiconductor, Inc.
ALT7
EzPort
USB_CLKIN
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Pinout
144 144
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
J5
50
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_
CTS_b
FTM0_CH5
JTAG_TCLK/ EZP_CLK
SWD_CLK
J6
51
PTA1
JTAG_TDI/
EZP_DI
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
K6
52
PTA2
JTAG_TDO/
TRACE_
SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
TRACE_
SWO
EZP_DO
K7
53
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
JTAG_TMS/
SWD_DIO
L7
54
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1
NMI_b
M8
55
PTA5
DISABLED
PTA5
E7
56
VDD
VDD
VDD
G7
57
VSS
VSS
VSS
J7
58
PTA6
DISABLED
J8
59
PTA7
ADC0_SE10
K8
60
PTA8
ADC0_SE11
L8
61
PTA9
M9
62
L9
USB_CLKIN
FTM0_CH2
CMP2_OUT
PTA6
FTM0_CH3
CLKOUT
ADC0_SE10
PTA7
FTM0_CH4
ADC0_SE11
PTA8
FTM1_CH0
FTM1_QD_
PHA
TRACE_D2
DISABLED
PTA9
FTM1_CH1
FTM1_QD_
PHB
TRACE_D1
PTA10
DISABLED
PTA10
FTM2_CH0
FTM2_QD_
PHA
TRACE_D0
63
PTA11
DISABLED
PTA11
FTM2_CH1
I2C2_SDA
FTM2_QD_
PHB
K9
64
PTA12
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
FTM1_CH0
I2C2_SCL
I2S0_TXD0
J9
65
PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
I2C2_SDA
I2S0_TX_FS FTM1_QD_
PHB
L10
66
PTA14
DISABLED
PTA14
SPI0_PCS0
UART0_TX
I2C2_SCL
I2S0_RX_
BCLK
L11
67
PTA15
DISABLED
PTA15
SPI0_SCK
UART0_RX
I2S0_RXD0
K10
68
PTA16
DISABLED
PTA16
SPI0_SOUT
UART0_
CTS_b
I2S0_RX_FS I2S0_RXD1
K11
69
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_
RTS_b
I2S0_MCLK
E8
70
VDD
VDD
VDD
G8
71
VSS
VSS
VSS
M12
72
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
M11
73
PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
L12
74
RESET_b
RESET_b
RESET_b
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
I2S0_TX_
BCLK
EZP_CS_b
JTAG_
TRST_b
TRACE_
CLKOUT
TRACE_D3
FTM1_QD_
PHA
I2S0_TXD1
LPTMR0_
ALT1
71
Freescale Semiconductor, Inc.
Pinout
144 144
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
K12
75
PTA24
DISABLED
PTA24
FB_A29
J12
76
PTA25
DISABLED
PTA25
FB_A28
J11
77
PTA26
DISABLED
PTA26
FB_A27
J10
78
PTA27
DISABLED
PTA27
FB_A26
H12
79
PTA28
DISABLED
PTA28
FB_A25
H11
80
PTA29
DISABLED
PTA29
FB_A24
H10
81
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
H9
82
PTB1
ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_
PHB
G12
83
PTB2
ADC0_SE12
ADC0_SE12
PTB2
I2C0_SCL
UART0_
RTS_b
FTM0_FLT3
G11
84
PTB3
ADC0_SE13
ADC0_SE13
PTB3
I2C0_SDA
UART0_
CTS_b
FTM0_FLT0
G10
85
PTB4
ADC1_SE10
ADC1_SE10
PTB4
FTM1_FLT0
G9
86
PTB5
ADC1_SE11
ADC1_SE11
PTB5
FTM2_FLT0
F12
87
PTB6
ADC1_SE12
ADC1_SE12
PTB6
FB_AD23
F11
88
PTB7
ADC1_SE13
ADC1_SE13
PTB7
FB_AD22
F10
89
PTB8
DISABLED
PTB8
F9
90
PTB9
DISABLED
PTB9
E12
91
PTB10
ADC1_SE14
ADC1_SE14
E11
92
PTB11
ADC1_SE15
ADC1_SE15
H7
93
VSS
VSS
VSS
VDD
UART3_
RTS_b
FB_AD21
SPI1_PCS1
UART3_
CTS_b
FB_AD20
PTB10
SPI1_PCS0
UART3_RX
FB_AD19
FTM0_FLT1
PTB11
SPI1_SCK
UART3_TX
FB_AD18
FTM0_FLT2
F5
94
VDD
VDD
E10
95
PTB16
DISABLED
PTB16
SPI1_SOUT
UART0_RX
FTM_CLKIN0 FB_AD17
EWM_IN
E9
96
PTB17
DISABLED
PTB17
SPI1_SIN
UART0_TX
FTM_CLKIN1 FB_AD16
EWM_OUT_
b
D12
97
PTB18
DISABLED
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_
BCLK
FB_AD15
FTM2_QD_
PHA
D11
98
PTB19
DISABLED
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS FB_OE_b
FTM2_QD_
PHB
D10
99
PTB20
DISABLED
PTB20
SPI2_PCS0
FB_AD31
CMP0_OUT
D9
100
PTB21
DISABLED
PTB21
SPI2_SCK
FB_AD30
CMP1_OUT
C12
101
PTB22
DISABLED
PTB22
SPI2_SOUT
FB_AD29
CMP2_OUT
C11
102
PTB23
DISABLED
PTB23
SPI2_SIN
SPI0_PCS5
FB_AD28
B12
103
PTC0
ADC0_SE14
ADC0_SE14
PTC0
SPI0_PCS4
PDB0_
EXTRG
FB_AD14
I2S0_TXD1
B11
104
PTC1/
LLWU_P6
ADC0_SE15
ADC0_SE15
PTC1/
LLWU_P6
SPI0_PCS3
UART1_
RTS_b
FB_AD13
I2S0_TXD0
72
Freescale Semiconductor, Inc.
FTM0_CH0
ALT7
EzPort
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Pinout
144 144
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
A12
105
PTC2
ADC0_SE4b/ ADC0_SE4b/ PTC2
CMP1_IN0
CMP1_IN0
SPI0_PCS2
UART1_
CTS_b
FTM0_CH1
FB_AD12
I2S0_TX_FS
A11
106
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
H8
107
VSS
VSS
VSS
VDD
—
108
VDD
VDD
A9
109
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
FB_AD11
CMP1_OUT
D8
110
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
I2S0_RXD0
FB_AD10
CMP0_OUT
C8
111
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9
I2S0_MCLK
B8
112
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB_SOF_
OUT
I2S0_RX_FS FB_AD8
A8
113
PTC8
ADC1_SE4b/ ADC1_SE4b/ PTC8
CMP0_IN2
CMP0_IN2
FTM3_CH4
I2S0_MCLK
FB_AD7
D7
114
PTC9
ADC1_SE5b/ ADC1_SE5b/ PTC9
CMP0_IN3
CMP0_IN3
FTM3_CH5
I2S0_RX_
BCLK
FB_AD6
C7
115
PTC10
ADC1_SE6b
ADC1_SE6b
PTC10
I2C1_SCL
FTM3_CH6
I2S0_RX_FS FB_AD5
B7
116
PTC11/
LLWU_P11
ADC1_SE7b
ADC1_SE7b
PTC11/
LLWU_P11
I2C1_SDA
FTM3_CH7
I2S0_RXD1
A7
117
PTC12
DISABLED
PTC12
UART4_
RTS_b
FB_AD27
D6
118
PTC13
DISABLED
PTC13
UART4_
CTS_b
FB_AD26
C6
119
PTC14
DISABLED
PTC14
UART4_RX
FB_AD25
B6
120
PTC15
DISABLED
PTC15
UART4_TX
FB_AD24
—
121
VSS
VSS
VSS
VDD
EzPort
FTM0_CH2
FTM2_FLT0
FB_RW_b
FTM3_FLT0
—
122
VDD
VDD
A6
123
PTC16
DISABLED
PTC16
UART3_RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_
8_b
D5
124
PTC17
DISABLED
PTC17
UART3_TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_0_
b
C5
125
PTC18
DISABLED
PTC18
UART3_
RTS_b
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b
B5
126
PTC19
DISABLED
PTC19
UART3_
CTS_b
FB_CS3_b/ FB_TA_b
FB_BE7_0_
BLS31_24_b
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
ALT7
73
Freescale Semiconductor, Inc.
Pinout
144 144
MAP LQFP
BGA
Pin Name
Default
A5
127
PTD0/
LLWU_P12
DISABLED
D4
128
PTD1
ADC0_SE5b
C4
129
PTD2/
LLWU_P13
B4
130
A4
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
PTD0/
LLWU_P12
SPI0_PCS0
UART2_
RTS_b
FTM3_CH0
FB_ALE/
FB_CS1_b/
FB_TS_b
PTD1
SPI0_SCK
UART2_
CTS_b
FTM3_CH1
FB_CS0_b
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
FTM3_CH2
FB_AD4
I2C0_SCL
PTD3
DISABLED
PTD3
SPI0_SIN
UART2_TX
FTM3_CH3
FB_AD3
I2C0_SDA
131
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
FTM0_CH4
FB_AD2
EWM_IN
A3
132
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_
CTS_b
FTM0_CH5
FB_AD1
EWM_OUT_
b
A2
133
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FB_AD0
FTM0_FLT0
M10
134
VSS
VSS
VSS
F8
135
VDD
VDD
VDD
FTM0_CH7
ADC0_SE5b
A1
136
PTD7
DISABLED
PTD7
CMT_IRO
UART0_TX
C9
137
PTD8
DISABLED
PTD8
I2C0_SCL
UART5_RX
FB_A16
B9
138
PTD9
DISABLED
PTD9
I2C0_SDA
UART5_TX
FB_A17
B3
139
PTD10
DISABLED
PTD10
UART5_
RTS_b
FB_A18
B2
140
PTD11
DISABLED
PTD11
SPI2_PCS0
UART5_
CTS_b
SDHC0_
CLKIN
FB_A19
B1
141
PTD12
DISABLED
PTD12
SPI2_SCK
FTM3_FLT0
SDHC0_D4
FB_A20
C3
142
PTD13
DISABLED
PTD13
SPI2_SOUT
SDHC0_D5
FB_A21
C2
143
PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6
FB_A22
C1
144
PTD15
DISABLED
PTD15
SPI2_PCS1
SDHC0_D7
FB_A23
M5
—
NC
NC
NC
A10
—
NC
NC
NC
B10
—
NC
NC
NC
C10
—
NC
NC
NC
EzPort
FTM0_FLT1
5.2 K21 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
74
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Pinout
1
2
3
4
5
6
7
8
9
10
11
12
A
PTD7
PTD6/
LLWU_P15
PTD5
PTD4/
LLWU_P14
PTD0/
LLWU_P12
PTC16
PTC12
PTC8
PTC4/
LLWU_P8
NC
PTC3/
LLWU_P7
PTC2
A
B
PTD12
PTD11
PTD10
PTD3
PTC19
PTC15
PTC11/
LLWU_P11
PTC7
PTD9
NC
PTC1/
LLWU_P6
PTC0
B
C
PTD15
PTD14
PTD13
PTD2/
LLWU_P13
PTC18
PTC14
PTC10
PTC6/
LLWU_P10
PTD8
NC
PTB23
PTB22
C
D
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTE0
PTD1
PTC17
PTC13
PTC9
PTC5/
LLWU_P9
PTB21
PTB20
PTB19
PTB18
D
E
PTE6
PTE5
PTE4/
LLWU_P2
PTE3
VDD
VDD
VDD
VDD
PTB17
PTB16
PTB11
PTB10
E
F
PTE10
PTE9
PTE8
PTE7
VDD
VSS
VSS
VDD
PTB9
PTB8
PTB7
PTB6
F
G
VOUT33
VREGIN
PTE12
PTE11
VREFH
VREFL
VSS
VSS
PTB5
PTB4
PTB3
PTB2
G
H
USB0_DP
USB0_DM
VSS
TAMPER4
VDDA
VSSA
VSS
VSS
PTB1
PTB0/
LLWU_P5
PTA29
PTA28
H
J
ADC0_DP1
ADC0_DM1
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
TAMPER3
PTA0
PTA1
PTA6
PTA7
PTA13/
LLWU_P4
PTA27
PTA26
PTA25
J
K
ADC1_DP1
ADC1_DM1
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
TAMPER2
TAMPER1
PTA2
PTA3
PTA8
PTA12
PTA16
PTA17
PTA24
K
L
ADC0_DP0/
ADC1_DP3
ADC0_DM0/
ADC1_DM3
DAC1_OUT/
DAC0_OUT/ CMP0_IN4/
CMP1_IN3/ CMP2_IN3/
ADC0_SE23 ADC1_SE23
TAMPER0/
RTC_
WAKEUP_B
VBAT
PTA4/
LLWU_P3
PTA9
PTA11
PTA14
PTA15
RESET_b
L
M ADC1_DP0/
ADC0_DP3
ADC1_DM0/
ADC0_DM3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
TAMPER5
NC
EXTAL32
XTAL32
PTA5
PTA10
VSS
PTA19
PTA18
M
2
3
4
5
6
7
8
9
10
11
12
1
Figure 33. K21 144 MAPBGA Pinout Diagram
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
75
Freescale Semiconductor, Inc.
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
111
110
109
PTC13
PTC8
PTC14
118
112
PTC15
119
PTC9
VSS
120
113
VDD
121
PTC10
PTC16
122
115
PTC17
123
114
PTC18
124
PTC12
PTC19
125
PTC11/LLWU_P11
PTD0/LLWU_P12
126
116
PTD1
127
117
PTD2/LLWU_P13
VSS
134
128
VDD
135
PTD3
PTD7
136
129
PTD8
137
PTD4/LLWU_P14
PTD9
138
131
PTD10
139
130
PTD11
140
PTD6/LLWU_P15
PTD12
141
PTD5
PTD13
142
132
PTD14
143
133
PTD15
144
Revision History
PTE0
1
108
VDD
PTE1/LLWU_P0
2
107
VSS
PTE2/LLWU_P1
3
106
PTC3/LLWU_P7
PTE3
4
105
PTC2
VDD
5
104
PTC1/LLWU_P6
VSS
6
103
PTC0
PTE4/LLWU_P2
7
102
PTB23
PTE5
8
101
PTB22
PTE6
9
100
PTB21
PTE7
10
99
PTB20
PTE8
11
98
PTB19
PTE9
12
97
PTB18
PTE10
13
96
PTB17
PTE11
14
95
PTB16
PTE12
15
94
VDD
VDD
16
93
VSS
VSS
17
92
PTB11
VSS
18
91
PTB10
USB0_DP
19
90
PTB9
USB0_DM
20
89
PTB8
VOUT33
21
88
PTB7
VREGIN
22
87
PTB6
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VDD
VSS
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
PTA13/LLWU_P4
PTA14
PTA15
PTA16
PTA17
VDD
VSS
PTA18
PTA19
55
RESET_b
73
PTA5
74
36
54
35
PTA4/LLWU_P3
ADC1_SE16/CMP2_IN2/ADC0_SE22
ADC0_SE16/CMP1_IN2/ADC0_SE21
53
PTA24
PTA3
75
52
34
PTA2
PTA25
VSSA
51
PTA26
76
50
77
33
PTA1
32
VREFL
PTA0
VREFH
49
PTA27
PTE28
78
48
31
PTE27
PTA28
VDDA
47
79
PTE26
30
46
PTA29
ADC1_DM0/ADC0_DM3
PTE25
80
45
29
PTE24
PTB0/LLWU_P5
ADC1_DP0/ADC0_DP3
44
81
VSS
28
43
PTB1
ADC0_DM0/ADC1_DM3
VDD
82
42
27
VBAT
PTB2
ADC0_DP0/ADC1_DP3
41
83
EXTAL32
26
40
PTB3
ADC1_DM1
XTAL32
84
39
25
TAMPER2
PTB4
ADC1_DP1
38
PTB5
85
37
86
24
TAMPER1
23
TAMPER0/RTC_WAKEUP_B
ADC0_DP1
ADC0_DM1
Figure 34. K21 144 LQFP Pinout Diagram
6 Revision History
The following table provides a revision history for this document.
76
Freescale Semiconductor, Inc.
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
Revision History
Table 49. Revision History
Rev. No.
Date
Substantial Changes
1
11/2012
Alpha customer release
2
5/2013
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated supported part numbers and document number
Updated section "Voltage and current operating behaviors"
Added DryIce Tamper Electrical Specifications
Added the following figures:
• Run mode supply current vs. core frequency
• VLPR mode supply current vs. core frequency
Updated section "Device clock specifications"
Updated section "Power consumption operating behaviors"
Updated section "Power mode transition operating behaviors"
Updated section "JTAG limited voltage range electricals"
Updated section "MCG specifications"
Updated section "Oscillator DC electrical specifications"
Updated section "16-bit ADC operating conditions"
Updated the pinouts
Added section "Alternate part numbers for small packages"
3
08/2013
• Updated section "Power consumption operating behaviors"
• Updated the "Run mode supply current vs. core frequency" figure in section
"Diagram: Typical IDD_RUN operating behavior
4
11/2014
• Updated the table "Voltage and current operating behavior"
• Format changes
Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014.
77
Freescale Semiconductor, Inc.
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Document Number K21P144M120SF5
Revision 4, 11/2014
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