NXP Semiconductors
Data Sheet: Technical Data
K22P121M120SF8
Rev. 7, 08/2016
Kinetis K22F 256 KB Flash
120 MHz ARM® Cortex®-M4-Based Microcontroller with FPU
The Kinetis K22 product family members are optimized for costsensitive applications requiring low-power, USB connectivity,
high peripheral integration and processing efficiency with floating
point unit. These devices share the comprehensive enablement
and scalability of the Kinetis family.
This product offers:
• Run power consumption down to 153 µA/MHz and static
power consumption down to 2.6 µA with full state retention
and 6 µs wakeup. Lowest static mode down to 120 nA
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
voltage regulator. USB FS device crystal-less functionality.
Performance
• 120 MHz ARM Cortex-M4 core with DSP instructions
delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• 256 KB of embedded flash and 48 KB of RAM
• Serial programming interface (EzPort)
• Preprogrammed Kinetis flashloader for one-time, insystem factory programming
System peripherals
• Flexible low-power modes, multiple wake up sources
• 16-channel DMA controller
• Independent external and software watchdog monitor
MK22FN256VDC12
MK22FN256VLL12
MK22FN256VMP12
MK22FN256VLH12
121 XFBGA (DC)
8 x 8 x 0.5 Pitch 0.65
mm
100 LQFP (LL)
14 x 14 x 1.4 Pitch 0.5
mm
64 MAPBGA (MP)
5 x 5 x 1.2 Pitch 0.5
mm
64 LQFP (LH)
10 x 10 x 1.4 Pitch 0.5
mm
Analog modules
• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)
• One 12-bit DAC
• Two analog comparators (CMP) with 6- bit DAC
• Accurate internal voltage reference
Communication interfaces
• USB LS/FS OTG 2.0 with on-chip transceiver and
USB LDO voltage regulator
• USB full-speed device crystal-less operation
• Two SPI modules
• Three UART modules and one low-power UART
• Two I2C modules: Support for up to 1 Mbps
operation
• I2S module
Clocks
• Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or Timers
3-32 MHz
• One 8-channel general purpose/ PWM timer
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
• Two 2-channel general purpose timers with
• Multi-purpose clock generator with PLL and FLL
quadrature decoder functionality
• Periodic interrupt timers
Security and integrity modules
• 16-bit low-power timer
• Hardware CRC module
• Real-time clock with independent power domain
• 128-bit unique identification (ID) number per chip
• Programmable delay block
• Hardware random-number generator
• Flash access control to protect proprietary software
Operating Characteristics
• Voltage range (including flash writes): 1.71 to 3.6 V
Human-machine interface
• Temperature range (ambient): -40 to 105°C
• Up to 70 general-purpose I/O (GPIO)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Part Number
Memory
Number of GPIOs
Flash (KB)
SRAM (KB)
MK22FN256VDC12
256
48
70
MK22FN256VLL12
256
48
66
MK22FN256VMP12
256
48
40
MK22FN256VLH12
256
48
40
Device Revision Number
Device Mask Set Number
SIM_SDID[REVID]
JTAG ID Register[PRN]
0N51M
0001
0001
Related Resources
Type
Description
Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector
KINETISKMCUSELGD
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K22FPB
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K22P121M120SF8RM
Data Sheet
The Data Sheet is this document. It includes electrical characteristics
and signal connections.
K22P121M120SF8
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_K_xN51M 1
a particular device mask set.
Package
drawing
Package dimensions are provided by part number:
• MK22FN256VDC12
• MK22FN256VLL12
• MK22FN256VMP12
• MK22FN256VLH12
Package drawing:
• 98ASA00595D
• 98ASS23308W
• 98ASA00420D
• 98ASS23234W
1. To find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision
of the device you are using.
Figure 1 shows the functional modules in the chip.
2
NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
ARM ® Cortex™-M4
Core
System
Memories and Memory Interfaces
DMA (16ch)
Program
flash
(256 KB)
Serial
programming
interface
(EzPort)
Debug
interfaces
DSP
Low-leakage
wakeup
Interrupt
controller
FPU
Internal
and external
watchdogs
RAM
(48 KB)
Clocks
Phaselocked loop
Frequencylocked loop
Low/high
frequency
oscillators
Internal
reference
clocks
Security
Analog
Timers
CRC
16-bit
ADC x2
Timers
x1 (8ch)
x2 (2ch)
Randomnumber
generator
Comparator
with 6-bit DAC
x2
Programmable
Flash access
control
and Integrity
Communication Interfaces
2
I C
x2
I S
delay block
UART
x3
USB OTG
LS/FS
12-bit DAC
Periodic
interrupt
timers
LPUART
x1
USB LS/FS
transceiver
High
performance
voltage ref
16-bit
low-power
timer
SPI
x2
USB voltage
regulator
2
Human-Machine
Interface (HMI)
Up to
70 GPIOs
Independent
real-time
clock
Figure 1. Functional block diagram
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 17
2.2.7 Designing with radiated emissions in mind..........18
2.2.8 Capacitance attributes.........................................18
2.3 Switching specifications...................................................18
2.3.1 Device clock specifications..................................18
2.3.2 General switching specifications......................... 19
2.4 Thermal specifications..................................................... 20
2.4.1 Thermal operating requirements......................... 20
2.4.2 Thermal attributes................................................20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 SWD electricals .................................................. 21
3.1.2 JTAG electricals.................................................. 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG specifications..............................................25
3.3.2 IRC48M specifications.........................................28
3.3.3 Oscillator electrical specifications........................28
3.3.4 32 kHz oscillator electrical characteristics........... 31
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash electrical specifications.............................. 31
3.4.2 EzPort switching specifications........................... 33
3.5 Security and integrity modules........................................ 34
3.6 Analog............................................................................. 34
4
NXP Semiconductors
4
5
6
7
3.6.1 ADC electrical specifications............................... 34
3.6.2 CMP and 6-bit DAC electrical specifications....... 38
3.6.3 12-bit DAC electrical characteristics....................41
3.6.4 Voltage reference electrical specifications.......... 44
3.7 Timers..............................................................................45
3.8 Communication interfaces............................................... 45
3.8.1 USB electrical specifications............................... 46
3.8.2 USB VREG electrical specifications.................... 46
3.8.3 DSPI switching specifications (limited voltage
range).................................................................. 47
3.8.4 DSPI switching specifications (full voltage
range).................................................................. 49
3.8.5 Inter-Integrated Circuit Interface (I2C) timing...... 50
3.8.6 UART switching specifications............................ 52
3.8.7 I2S/SAI switching specifications.......................... 52
Dimensions............................................................................. 58
4.1 Obtaining package dimensions....................................... 58
Pinout...................................................................................... 59
5.1 K22F Signal Multiplexing and Pin Assignments.............. 59
5.2 Recommended connection for unused analog and
digital pins........................................................................64
5.3 K22F Pinouts................................................................... 65
Part identification.....................................................................69
6.1 Description.......................................................................69
6.2 Format............................................................................. 69
6.3 Fields............................................................................... 70
6.4 Example...........................................................................70
6.5 121-pin XFBGA part marking.......................................... 71
6.6 64-pin MAPBGA part marking......................................... 71
Terminology and guidelines.................................................... 71
7.1 Definitions........................................................................ 71
7.2 Examples......................................................................... 72
7.3 Typical-value conditions.................................................. 72
7.4 Relationship between ratings and operating
requirements....................................................................73
7.5 Guidelines for ratings and operating requirements..........73
8 Revision History...................................................................... 73
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
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NXP Semiconductors
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
158
mA
VDIO
Digital input voltage
–0.3
VDD + 0.3
V
VAIO
Analog1
–0.3
VDD + 0.3
V
ID
VDDA
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
VREGIN
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
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NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
General
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
0.7 × VDD
—
V
0.75 × VDD
—
V
—
0.35 × VDD
V
—
0.3 × VDD
V
0.06 × VDD
—
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
Notes
• 1.7 V ≤ VDD ≤ 2.7 V
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VHYS
Input hysteresis
IICIO
Analog and I/O pin DC injection current — single pin
1
-3
—
mA
-25
—
mA
VDD
VDD
V
1.2
—
V
VPOR_VBAT
—
V
• VIN < VSS-0.3V (Negative current injection)
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
VODPU
Open drain pullup voltage level
VRAM
VDD voltage required to retain RAM
VRFVBAT
VBAT voltage required to retain the VBAT register file
2
1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or
greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VIO_MIN-VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
VLVW1H
• Level 1 falling (LVWV=00)
Notes
1
2.62
2.70
2.78
V
Table continues on the next page...
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
7
NXP Semiconductors
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol
Min.
Typ.
Max.
Unit
VLVW2H
Description
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
VOH
IOHT
Description
Min.
Typ.
Max.
Unit
Notes
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
VDD – 0.5
—
—
V
1
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VDD – 0.5
—
—
V
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
VDD – 0.5
—
—
V
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
VDD – 0.5
—
—
V
Output high current total for all ports
—
—
100
mA
Output high voltage — Normal drive pad except
RESET_B
Output high voltage — High drive pad except
RESET_B
1
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NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Min.
Typ.
Max.
Unit
Notes
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
—
0.5
V
1
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
0.5
V
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
V
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
—
0.5
V
Output low current total for all ports
—
—
100
mA
All pins other than high drive port pins
—
0.002
0.5
μA
High drive port pins
—
0.004
0.5
μA
Input leakage current (total all pins) for full
temperature range
—
—
1.0
μA
2
RPU
Internal pullup resistors
20
—
50
kΩ
3
RPD
Internal pulldown resistors
20
—
50
kΩ
4
VOL
VOL
VOL
IOLT
IIN
IIN
Description
Output low voltage — Normal drive pad except
RESET_B
Output low voltage — High drive pad except
RESET_B
1
Output low voltage — RESET_B
Input leakage current (per pin) for full
temperature range
1, 2
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
CPU and system clocks = 80 MHz
Bus clock = 40 MHz
Flash clock = 20 MHz
MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
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9
NXP Semiconductors
General
Table 5. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
—
140
μs
—
—
140
μs
—
—
80
μs
—
—
80
μs
—
—
—
—
—
—
5.7
μs
—
—
5.7
μs
Notes
first instruction across the operating
temperature range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS2 → RUN
6
• LLS3 → RUN
μs
6
μs
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
The current parameters in the table below are derived from code executing a while(1)
loop from flash, unless otherwise noted.
The IDD typical values represent the statistical mean at 25°C, and the IDD maximum
values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction
temperature unless otherwise noted. The maximum values represent characterized
results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol
IDDA
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
—
25.66
26.35
mA
2, 3, 4
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
@ 1.8V
Table continues on the next page...
10
NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
25.75
26.44
mA
@ 1.8V
—
23.6
24.29
mA
@ 3.0V
—
23.7
24.39
mA
@ 1.8V
—
31.9
32.59
mA
@ 3.0V
—
32.0
32.69
mA
@ 1.8V
—
15.8
16.49
mA
@ 3.0V
—
15.8
16.49
mA
@ 1.8V
—
14.00
15.50
mA
@ 3.0V
—
14.00
15.69
mA
@ 1.8V
—
15.3
15.99
mA
@ 3.0V
—
15.4
16.09
mA
—
20.4
21.09
mA
• @ 25°C
—
20.5
21.19
mA
• @ 70°C
—
20.5
21.19
mA
• @ 85°C
—
20.5
21.19
mA
• @ 105°C
—
21.4
22.09
mA
—
14.0
14.69
mA
• @ 25°C
—
14.0
14.69
mA
• @ 70°C
—
14.0
14.69
mA
• @ 85°C
—
14.0
14.69
mA
• @ 105°C
—
15.0
15.69
mA
—
8.1
8.79
mA
@ 3.0V
Notes
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
2
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
IDD_RUN
IDD_RUN
IDD_RUN
IDD_RUN
5
Run mode current in Compute operation —
CoreMark benchmark code executing from flash
3, 4, 6
Run mode current in Compute operation —
code executing from flash
6
Run mode current — all peripheral clocks
disabled, code executing from flash
7
Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
8
@ 3.0V
IDD_RUN
Run mode current — Compute operation, code
executing from flash
@ 1.8V
9
@ 3.0V
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
7
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NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
IDD_VLPR
Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
IDD_VLPR
Min.
Typ.
Max.
Unit
Notes
—
4.4
5.09
mA
10
@ 1.8V
—
0.70
0.88
mA
3, 4, 11
@ 3.0V
—
0.70
0.88
mA
0.61
0.79
Very-low-power run mode current in Compute
operation, code executing from flash
@ 1.8V
—
mA
11
@ 3.0V
—
0.61
0.79
mA
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
0.68
0.87
mA
12
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.10
1.28
mA
13
IDD_VLPW
Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
0.38
0.57
mA
14
IDD_STOP
Stop mode current at 3.0 V
@ -40°C to 25°C
—
0.27
0.35
mA
@ 70°C
—
0.32
0.47
mA
@ 85°C
—
0.32
0.51
mA
@ 105°C
—
0.45
0.77
mA
@ -40°C to 25°C
—
4.5
12.00
µA
@ 70°C
—
16.8
42.40
µA
@ 85°C
—
28.9
73.45
µA
@ 105°C
—
60.8
141.90
µA
@ -40°C to 25°C
—
2.6
3.75
µA
@ 70°C
—
6.6
12.00
µA
@ 85°C
—
10.5
17.25
µA
@ 105°C
—
21.0
40.70
µA
@ -40°C to 25°C
—
2.4
3.40
µA
@ 70°C
—
5.3
8.90
µA
@ 85°C
—
5.1
10.05
µA
@ 105°C
—
15.9
28.85
µA
@ -40°C to 25°C
—
1.9
2.30
µA
@ 70°C
—
4.8
8.10
µA
@ 85°C
—
7.6
11.30
µA
IDD_VLPS
IDD_LLS3
IDD_LLS2
Very-low-power stop mode current at 3.0 V
Low leakage stop mode 3 current at 3.0 V
Low leakage stop mode 2 current at 3.0 V
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
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NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
15.3
27.65
µA
@ -40°C to 25°C
—
1.7
2.10
µA
@ 70°C
—
3.4
4.85
µA
@ 85°C
—
5.1
8.80
µA
@ 105°C
—
9.8
15.70
µA
@ -40°C to 25°C
—
0.71
0.96
µA
@ 70°C
—
1.79
2.10
µA
@ 85°C
—
2.9
4.70
µA
@ 105°C
—
5.7
8.10
µA
@ -40°C to 25°C
—
0.40
0.56
µA
@ 70°C
—
1.39
1.70
µA
@ 85°C
—
2.5
4.25
µA
@ 105°C
—
5.3
7.50
µA
@ -40°C to 25°C
—
0.12
0.38
µA
@ 70°C
—
1.05
1.38
µA
@ 85°C
—
2.20
3.95
µA
@ 105°C
—
4.9
7.10
µA
@ -40°C to 25°C
—
0.18
0.21
µA
@ 70°C
—
0.66
0.86
µA
@ 85°C
—
1.52
2.24
µA
@ 105°C
—
2.92
4.30
µA
• @ -40°C to 25°C
—
0.59
0.70
µA
• @ 70°C
—
1.00
1.3
µA
• @ 85°C
—
1.76
2.59
µA
• @ 105°C
—
3.00
4.42
µA
—
0.71
0.84
µA
@ 105°C
Notes
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
IDD_VBAT
IDD_VBAT
Average current with RTC and 32kHz disabled
at 3.0 V
Average current when CPU is not accessing
RTC registers
@ 1.8V
15
@ 3.0V
• @ -40°C to 25°C
Table continues on the next page...
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13
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• @ 70°C
—
1.22
1.59
µA
• @ 85°C
—
2.08
3.06
µA
• @ 105°C
—
3.50
5.15
µA
Notes
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All
peripheral clocks disabled.
3. Cache on and prefetch on, low compiler optimization.
4. Coremark benchmark compiled using IAR 7.2 with optimization level low.
5. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All
peripheral clocks enabled.
6. 80 MHz core and system clock, 40 MHz bus clock, and 26.67 MHz flash clock. MCG configured for PEE mode. Compute
operation.
7. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All
peripheral clocks disabled.
8. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
9. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. Compute
operation.
10. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.
11. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute operation. Code
executing from flash.
12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
15. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders—typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
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NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
General
Table 7. Low power mode peripheral adders—typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
VLLS1
440
490
540
560
570
580
VLLS3
440
490
540
560
570
580
LLS
490
490
540
560
570
680
VLPS
510
560
560
560
610
680
STOP
510
560
560
560
610
680
48 Mhz internal reference clock
350
350
350
350
350
350
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
22
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432
357
388
475
532
810
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
66
66
66
66
66
66
µA
214
237
246
254
260
268
entering all modes with the crystal
enabled.
I48MIRC
MCGIRCLK (4 MHz internal reference
clock)
>OSCERCLK (4 MHz external crystal)
nA
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42
42
42
42
42
42
µA
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
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15
NXP Semiconductors
General
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz. MCG in PEE mode at frequencies
greater than 100 MHz.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 3. Run mode supply current vs. core frequency
16
NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors for 64 LQFP package
Parame Conditions
ter
VEME
Clocks
Frequency range
Level
(Typ.)
Unit
Notes
dBuV
1, 2, 3
Device configuration,
FSYS = 120 MHz
test conditions and EM
FBUS = 60 MHz
testing per standard IEC
External crystal = 8 MHz
61967-2.
150 kHz–50 MHz
14
50 MHz–150 MHz
23
150 MHz–500 MHz
23
Supply voltages:
• VREGIN (USB) =
5.0 V
• VDD = 3.3 V
500 MHz–1000 MHz
9
IEC level
L
4
Temp = 25°C
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. Measurements were performed on the 64LQFP device, MK22FN512VLH12 .
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17
NXP Semiconductors
General
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
4. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to nxp.com
• Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed run mode
fSYS
System and core clock
—
120
MHz
fBUS
Bus clock
—
60
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
80
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
50
MHz
fFLASH
Flash clock
—
26.67
MHz
fLPTMR
LPTMR clock
—
25
MHz
—
4
MHz
fSYS_USB
fBUS
VLPR mode1
fSYS
System and core clock
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Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
General
Table 10. Device clock specifications (continued)
Symbol
Min.
Max.
Unit
Bus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
—
16
MHz
fBUS
fLPTMR_pin
Description
fLPTMR_ERCLK LPTMR external reference clock
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
50
—
ns
4
Mode select (EZP_CS) hold time after reset
deassertion
2
—
Bus clock
cycles
Port rise and fall time
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
5
—
—
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
10
ns
5
ns
30
ns
16
ns
—
—
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
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19
NXP Semiconductors
General
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Notes
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Board
type
Symbol
Descripti
on
121
XFBGA
100 LQFP
64 LQFP
64
MAPBGA
Unit
Notes
Single-layer RθJA
(1s)
Thermal
44.4
resistance,
junction to
ambient
(natural
convection)
61
67
47.3
°C/W
1
Four-layer
(2s2p)
Thermal
27.0
resistance,
junction to
ambient
(natural
convection)
48
48
38.9
°C/W
2
Single-layer RθJMA
(1s)
Thermal
37.2
resistance,
junction to
ambient
(200 ft./min.
air speed)
51
55
40.1
°C/W
3
Four-layer
(2s2p)
Thermal
23.7
resistance,
junction to
ambient
(200 ft./min.
air speed)
42
42
35.3
°C/W
3
RθJA
RθJMA
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NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Board
type
Symbol
Descripti
on
121
XFBGA
100 LQFP
64 LQFP
64
MAPBGA
Unit
Notes
—
RθJB
Thermal
resistance,
junction to
board
23.5
34
31
35.4
°C/W
4
—
RθJC
Thermal
resistance,
junction to
case
17.4
16
16
29.2
°C/W
5
—
ΨJT
Thermal
0.2
characteriz
ation
parameter,
junction to
package
top outside
center
(natural
convection)
3
3
0.4
°C/W
6
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 13. SWD full voltage range electricals
Symbol
S1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
33
MHz
SWD_CLK frequency of operation
• Serial wire debug
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 13. SWD full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
S2
SWD_CLK cycle period
1/S1
—
ns
S3
SWD_CLK clock pulse width
15
—
ns
• Serial wire debug
S4
SWD_CLK rise and fall times
—
3
ns
S9
SWD_DIO input data setup time to SWD_CLK rise
8
—
ns
S10
SWD_DIO input data hold time after SWD_CLK rise
1.4
—
ns
S11
SWD_CLK high to SWD_DIO data valid
—
25
ns
S12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
S2
S3
S3
SWD_CLK (input)
S4
S4
Figure 5. Serial wire clock input timing
SWD_CLK
S9
SWD_DIO
S10
Input data valid
S11
SWD_DIO
Output data valid
S12
SWD_DIO
S11
SWD_DIO
Output data valid
Figure 6. Serial wire data timing
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NXP Semiconductors
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Peripheral operating requirements and behaviors
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
1
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
19
ns
J12
TCLK low to TDO high-Z
—
19
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 15. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
15
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
33
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
1.4
—
ns
J7
TCLK low to boundary scan output data valid
—
27
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 15. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J8
TCLK low to boundary scan output high-Z
—
27
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
26.2
ns
J12
TCLK low to TDO high-Z
—
26.2
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
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NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
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25
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 16. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Δfints_t
Total deviation of internal reference frequency
(slow clock) over voltage and temperature
—
+0.5/-0.7
±2
%
31.25
—
39.0625
kHz
—
± 0.3
± 0.6
%fdco
1
fints_t
Internal reference frequency (slow clock) —
user trimmed
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
± 1.5
%fdco
1
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
—
+1/-2
±5
%fintf_ft
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
fintf_ft
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
Table continues on the next page...
26
NXP Semiconductors
Kinetis K22F 256 KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
95.98
—
MHz
Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire
—
—
180
—
ps
—
150
FLL target frequency acquisition time
—
—
1
ms
48.0
—
120
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
—
120
—
ps
—
75
—
ps
—
1350
—
ps
—
600
—
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
• fvco = 48 MHz
8
8
9
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
9
• fvco = 100 MHz
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
150 × 10-6
+ 1075(1/
fpll_ref)
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2.0 V
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