NXP Semiconductors
Data Sheet: Technical Data
K24P144M120SF5
Rev. 7, 11/2016
Kinetis K24F Sub-Family Data
Sheet
120 MHz ARM® Cortex®-M4-based Microcontroller with FPU
The K24 product family members are optimized for cost-sensitive
applications requiring low-power, USB connectivity, and up to
256 KB of embedded SRAM. These devices share the
comprehensive enablement and scalability of the Kinetis family.
This product offers:
• Run power consumption down to 250 μA/MHz. Static
power consumption down to 5.8 μA with full state retention
and 5 μs wakeup. Lowest Static mode down to 339 nA
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
Vreg, with USB device crystal-less operation
Performance
• Up to 120 MHz ARM® Cortex®-M4 core with DSP
instructions and floating point unit
Memories and memory interfaces
• Up to 1 MB program flash memory and 256 KB RAM
• FlexBus external bus interface
System peripherals
• Multiple low-power modes, low-leakage wake-up unit
• Memory protection unit with multi-master protection
• 16-channel DMA controller
• External watchdog monitor and software watchdog
Security and integrity modules
• Hardware CRC module
• Hardware random-number generator
• Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
• 128-bit unique identification (ID) number per chip
Analog modules
• Two 16-bit SAR ADCs
• Two 12-bit DACs
• Three analog comparators (CMP)
• Voltage reference
MK24FN1M0VLQ12
MK24FN1M0VLL12
MK24FN1M0VDC12
121 XFBGA
8 x 8 x 0.5 mm Pitch
0.65 mm
144 LQFP
20 x 20 x 1.6 mm Pitch
0.5 mm
100 QFP
14 x 14 x 1.7 mm Pitch 0.5 mm
Communication interfaces
• USB full-/low-speed On-the-Go controller
• Controller Area Network (CAN) module
• Three SPI modules
• Three I2C modules. Support for up to 1 Mbit/s
• Six UART modules
• Secure Digital Host Controller (SDHC)
• I2S module
Timers
• Two 8-channel Flex-Timers (PWM/Motor control)
• Two 2-channel FlexTimers (PWM/Quad decoder)
• 32-bit PITs and 16-bit low-power timers
• Real-time clock
• Programmable delay block
Clocks
• 3 to 32 MHz and 32 kHz crystal oscillator
• PLL, FLL, and multiple internal oscillators
• 48 MHz Internal Reference Clock (IRC48M)
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MK24FN1M0VLL12
1 MB
256
66
MK24FN1M0VDC12
1 MB
256
83
MK24FN1M0VLQ12
1 MB
256
100
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type
Description
Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K60PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K24P144M120SF5RM 1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
K24P144M120SF51
Package
drawing
Package dimensions are provided in package drawings.
• 100-pin LQFP:
98ASS233081
• XFBGA 121-pin:
98ASA00595D1
• LQFP 144-pin:
98ASS23177W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Kinetis K24 Family
ARM ® Cortex™-M4
Core
System
Memories and Memory Interfaces
Clocks
Internal
and external
watchdogs
Program
flash
RAM
Phaselocked loop
Serial
programming
interface
FlexBus
Frequencylocked loop
Debug
interfaces
DSP
DMA
Interrupt
controller
Floating
point
Low-leakage
wakeup
Low/high
frequency
oscillators
Memory
Protection
Internal
reference
clocks
Communication Interfaces
Security
Analog
Timers
CRC
16-bit ADC
x2
Timers
x2 (8ch)
x2 (2ch)
I C
x3
I S
x1
Random
number
generator
Analog
comparator
x3
Programmable
delay block
UART
x6
USB OTG
LS/FS
Hardware
encryption
6-bit DAC
x3
Periodic
interrupt
timers
SPI
x3
USB LS/FS
transceiver
12-bit DAC
x2
Low power
timer
SDHC
x1
USB charger
detect
Voltage
reference
Independent
real-time
clock
CAN
x1
USB voltage
regulator
and Integrity
2
Human-Machine
Interface (HMI)
2
GPIO
Figure 1. K24 block diagram
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1
Voltage and current operating requirements.....6
2.2.2
LVD and POR operating requirements............. 8
2.2.3
Voltage and current operating behaviors.......... 8
2.2.4
Power mode transition operating behaviors......10
2.2.5
Power consumption operating behaviors.......... 11
2.2.6
EMC radiated emissions operating behaviors...16
2.2.7
Designing with radiated emissions in mind....... 17
2.2.8
Capacitance attributes...................................... 17
2.3 Switching specifications...................................................17
2.3.1
Device clock specifications............................... 17
2.3.2
General switching specifications....................... 18
2.4 Thermal specifications..................................................... 19
2.4.1
Thermal operating requirements....................... 19
2.4.2
Thermal attributes............................................. 20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1
Debug trace timing specifications..................... 21
3.1.2
JTAG electricals................................................ 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1
MCG specifications........................................... 25
3.3.2
IRC48M specifications...................................... 27
3.3.3
Oscillator electrical specifications..................... 28
3.3.4
32 kHz oscillator electrical characteristics.........30
3.4 Memories and memory interfaces................................... 31
3.4.1
Flash (FTFE) electrical specifications............... 31
3.4.2
EzPort switching specifications......................... 33
3.4.3
Flexbus switching specifications....................... 34
3.5 Security and integrity modules........................................ 37
3.6 Analog............................................................................. 37
3.6.1
ADC electrical specifications.............................38
4
NXP Semiconductors
4
5
6
7
8
3.6.2
CMP and 6-bit DAC electrical specifications.....42
3.6.3
12-bit DAC electrical characteristics................. 44
3.6.4
Voltage reference electrical specifications........ 47
3.7 Timers..............................................................................48
3.8 Communication interfaces............................................... 48
3.8.1
USB electrical specifications............................. 49
3.8.2
USB DCD electrical specifications.................... 49
3.8.3
USB VREG electrical specifications..................49
3.8.4
CAN switching specifications............................ 50
3.8.5
DSPI switching specifications (limited voltage
range)................................................................50
3.8.6
DSPI switching specifications (full voltage
range)................................................................52
3.8.7
Inter-Integrated Circuit Interface (I2C) timing....54
3.8.8
UART switching specifications.......................... 55
3.8.9
SDHC specifications......................................... 56
3.8.10 I2S switching specifications.............................. 56
Dimensions............................................................................. 62
4.1 Obtaining package dimensions....................................... 62
Pinout...................................................................................... 63
5.1 K24 Signal Multiplexing and Pin Assignments.................63
5.2 Unused analog interfaces................................................ 69
5.3 K24 Pinouts..................................................................... 70
Ordering parts......................................................................... 73
6.1 Determining valid orderable parts....................................73
Part identification.....................................................................74
7.1 Description.......................................................................74
7.2 Format............................................................................. 74
7.3 Fields............................................................................... 74
7.4 Example...........................................................................75
Terminology and guidelines.................................................... 75
8.1 Definitions........................................................................ 75
8.2 Examples......................................................................... 76
8.3 Typical-value conditions.................................................. 76
8.4 Relationship between ratings and operating
requirements....................................................................77
8.5 Guidelines for ratings and operating requirements..........77
9 Revision History...................................................................... 78
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
Solder temperature, leaded
—
245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
5
NXP Semiconductors
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
mA
–0.3
5.5
V
–0.3
VBAT + 0.3
V
Analog1, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Maximum current single pin limit (applies to all digital pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
VDRTC_WAKEU RTC Wakeup input voltage
P
VAIO
ID
VDDA
Analog supply voltage
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VREGIN
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VBAT
VIH
VIL
RTC battery supply voltage
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICDIO
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
IICAIO
IICcont
1
Analog2, EXTAL, and XTAL pin DC injection current
— single pin
3
mA
• VIN < VSS-0.3V (Negative current injection)
-5
—
• VIN > VDD+0.3V (Positive current injection)
—
+5
-25
—
—
+25
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
mA
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
Notes
VBAT voltage required to retain the VBAT register file
4
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VINVAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative
injection currents.
4. Open drain outputs must be pulled to VDD.
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
7
NXP Semiconductors
General
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
Notes
Output high voltage — high drive strength
Table continues on the next page...
8
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
V
—
100
mA
VBAT – 0.5
—
V
VBAT – 0.5
—
V
VBAT – 0.5
—
V
VBAT – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
0.5
V
—
100
mA
—
0.5
V
—
0.5
V
—
0.5
V
—
0.5
V
—
100
mA
Notes
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOH_RTC_WA Output high voltage — high drive strength
KEUP
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
Output high voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
IOH_RTC_WAK Output high current total for RTC_WAKEUP pins
EUP
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
Output low current total for all ports
VOL_RTC_WA Output low voltage — high drive strength
KEUP
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
Output low voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
IOL_RTC_WAK Output low current total for RTC_WAKEUP pins
EUP
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
1
IIN
Input leakage current (per pin) at 25°C
—
0.025
μA
1
IIN_RTC_WAK Input leakage current (per RTC_WAKEUP pin) for full
temperature range
EUP
—
1
μA
IIN_RTC_WAK Input leakage current (per RTC_WAKEUP pin) at
25°C
EUP
—
0.025
μA
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
9
NXP Semiconductors
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
IOZ
Description
Hi-Z (off-state) leakage current (per pin)
IOZ_RTC_WAK Hi-Z (off-state) leakage current (per RTC_WAKEUP
pin)
EUP
Min.
Max.
Unit
—
0.25
μA
—
0.25
μA
Notes
RPU
Internal pullup resistors (except RTC_WAKEUP pins)
20
50
kΩ
2
RPD
Internal pulldown resistors (except RTC_WAKEUP
pins)
20
50
kΩ
3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
10
NXP Semiconductors
Min.
Max.
Unit
—
300
μs
—
156
μs
—
156
μs
—
78
μs
—
78
μs
—
4.8
μs
—
4.5
μs
—
4.5
μs
Notes
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard
deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN
Min.
2
—
31.1
36.65
mA
—
31
36.75
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
—
42.7
48.35
mA
• @ 25°C
—
40
41.60
mA
• @ 105°C
—
48.33
51.50
mA
• @ 1.8V
• @ 3.0V
IDD_WAIT
Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
—
17.9
—
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
6.9
—
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
—
1.0
—
mA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
—
1.7
—
mA
7
—
0.678
—
mA
8
• @ –40 to 25°C
—
0.49
1.24
mA
• @ 70°C
—
1.18
4.3
mA
• @ 105°C
—
3.0
12.5
mA
• @ –40 to 25°C
—
57
139.31
μA
• @ 70°C
—
291
679.33
μA
• @ 105°C
—
927.3
1869.85
μA
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
IDD_STOP
IDD_VLPS
IDD_LLS
Stop mode current at 3.0 V
Very-low-power stop mode current at 3.0 V
Low leakage stop mode current at 3.0 V
9
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
11
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• @ –40 to 25°C
—
5.8
10.48
μA
• @ 70°C
—
26.7
47.99
μA
• @ 105°C
—
114.9
196.49
μA
• @ –40 to 25°C
—
4.4
5.54
μA
• @ 70°C
—
21
36.46
μA
• @ 105°C
—
90.2
150.17
μA
• @ –40 to 25°C
—
2.1
2.34
μA
• @ 70°C
—
6.84
10.36
μA
• @ 105°C
—
29.4
46.74
μA
• @ –40 to 25°C
—
0.817
0.86
μA
• @ 70°C
—
3.97
5.77
μA
• @ 105°C
—
21.3
33.99
μA
—
0.52
0.62
μA
—
3.67
5.7
μA
—
21.20
34.9
μA
—
0.339
0.412
μA
—
3.36
4.2
μA
—
20.3
29.9
μA
—
0.16
0.19
μA
—
0.55
0.72
μA
—
2.5
3.68
μA
—
0.18
0.21
μA
—
0.66
0.86
μA
—
2.92
4.30
μA
Notes
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current with RTC and 32 kHz disabled
• @ 1.8 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
Table continues on the next page...
12
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_VBAT
Average current when CPU is not accessing
RTC registers
Typ.
Max.
Unit
Notes
10
• @ 1.8 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
0.59
0.70
μA
—
1.0
1.30
μA
—
3.0
4.42
μA
—
0.71
0.84
μA
—
1.22
1.59
μA
—
3.5
5.15
μA
• @ 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 Mhz FlexBus clock, and 20 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus clock, 30 MHz Flexbus clock, and 20 MHz flash clock. MCG configured
for PEE mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Data reflects devices with 256 KB of RAM.
10. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
13
NXP Semiconductors
General
Table 7. Low power mode peripheral adders — typical value (continued)
Symbol
Description
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
VLPS
Temperature (°C)
Unit
-40
25
50
70
85
105
440
490
540
560
570
580
440
490
540
560
570
580
490
490
540
560
570
680
510
560
560
560
610
680
510
560
560
560
610
680
nA
STOP
I48MIRC
48 Mhz internal reference clock
350
350
350
350
350
350
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
22
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432
357
388
475
532
810
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
66
66
66
66
66
66
µA
OSCERCLK (4 MHz external crystal)
214
237
246
254
260
268
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42
42
42
42
42
42
µA
MCGIRCLK (4 MHz internal reference
clock)
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
14
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Run Mode Current Consumption vs Core Frequency
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
40.00E-03
35.00E-03
Current Consumption on VDD (A)
30.00E-03
25.00E-03
All Peripheral Clk Gates
20.00E-03
ALLOFF
ALLON
15.00E-03
10.00E-03
5.00E-03
000.00E+00
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-2
'1-2-3
'1-2-4
'1-2-5
1
2
4
6.25
12.5
25
50
75
100
120
Clk Ratio
Core-BusFlaxbus-Flash
Core Freq (MHz)
Figure 3. Run mode supply current vs. core frequency
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
15
NXP Semiconductors
General
Very Low Power Run (VLPR) Current vs Core Frequency
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
1.40E-03
1.20E-03
Current Consumption on VDD (A)
1.00E-03
800.00E-06
All Peripheral Clk Gates
ALLOFF
ALLON
600.00E-06
400.00E-06
200.00E-06
000.00E+00
'1-1-2
'1-1-1
'1-2-4
1
'1-1-4
'1-1-2
'1-2-4
2
'1-1-4
Clk Ratio
Core-Bus-Flash
Core Freq (MHz)
4
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
144 LQFP
VRE1
Radiated emissions voltage, band 1
0.15–50
16
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
22
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
21
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
16
dBμV
IEC level
0.15–1000
L
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
16
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
120
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
60
MHz
FlexBus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
—
4
MHz
Notes
Normal run mode
fSYS
fBUS
FB_CLK
VLPR
fSYS
System and core clock
mode1
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
17
NXP Semiconductors
General
Table 10. Device clock specifications (continued)
Symbol
Min.
Max.
Unit
Bus clock
—
4
MHz
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
0.8
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
fLPTMR_ERCLK LPTMR external reference clock
—
16
MHz
fFlexCAN_ERCLK FlexCAN external reference clock
—
8
MHz
fBUS
FB_CLK
fLPTMR_pin
Description
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, timers, and I2C signals.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
2
—
Bus clock
cycles
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength) - 3 V
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
8
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
18
ns
• 2.7 ≤ VDD ≤ 3.6V
—
12
ns
• Slew enabled
Port rise and fall time (high drive strength) - 5 V
4
• Slew disabled
Table continues on the next page...
18
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 11. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
• 1.71 ≤ VDD ≤ 2.7V
—
6
ns
• 2.7 ≤ VDD ≤ 3.6V
—
4
ns
• 1.71 ≤ VDD ≤ 2.7V
—
24
ns
• 2.7 ≤ VDD ≤ 3.6V
—
14
ns
Notes
• Slew enabled
Port rise and fall time (low drive strength) - 3 V
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
24
ns
• 2.7 ≤ VDD ≤ 3.6V
—
16
ns
• Slew enabled
Port rise and fall time (low drive strength) - 5 V
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
17
ns
• 2.7 ≤ VDD ≤ 3.6V
—
10
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
20
ns
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 25 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
TJ
TA
Description
Min.
Max.
Unit
Die junction temperature
–40
125
°C
–40
105
°C
Ambient
temperature1
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
19
NXP Semiconductors
General
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 13. Thermal attributes
Board type
Symbol
Description
144 LQFP
121 XFBGA
100 LQFP
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
51
33.3
51
°C/W
1
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
43
21.1
39
°C/W
1
Single-layer
(1s)
RθJMA
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
42
26.2
41
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
36
17.8
32
°C/W
1
—
RθJB
Thermal
resistance,
junction to
board
30
16.3
24
°C/W
2
—
RθJC
Thermal
resistance,
junction to
case
11
12
11
°C/W
3
—
ΨJT
Thermal
2
characterizati
on parameter,
junction to
package top
outside center
(natural
convection)
0.2
2
°C/W
4
20
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 14. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
1.5
—
ns
Th
Data hold
1
—
ns
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
21
NXP Semiconductors
Peripheral operating requirements and behaviors
TRACE_CLKOUT
Ts
Ts
Th
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
3.1.2 JTAG electricals
Table 15. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.6
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 16. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
22
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 16. JTAG full voltage range electricals (continued)
Symbol
J1
Description
Min.
Max.
TCLK frequency of operation
Unit
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
2.9
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
23
NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
24
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 17. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Iints
Internal reference (slow clock) current
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
± 0.5
±2
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
Internal reference (fast clock) current
—
25
—
µA
Iintf
1
,2
1
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
25
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
120
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
8
8
9
• fvco = 48 MHz
—
120
—
ps
• fvco = 120 MHz
—
80
—
ps
PLL accumulated jitter over 1µs (RMS)
9
Table continues on the next page...
26
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• fvco = 48 MHz
—
1350
—
ps
• fvco = 120 MHz
—
600
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
10-6
—
150 ×
+ 1075(1/
fpll_ref)
Notes
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V
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