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MK30DX256VMC7

MK30DX256VMC7

  • 厂商:

    NXP(恩智浦)

  • 封装:

    LFBGA121

  • 描述:

    IC MCU 32B 256KB FLASH 121MAPBGA

  • 数据手册
  • 价格&库存
MK30DX256VMC7 数据手册
Freescale Semiconductor Data Sheet: Technical Data Document Number: K30P100M72SF1 Rev. 3, 11/2012 K30P100M72SF1 K30 Sub-Family Supports: MK30DX128VLL7, MK30DX256VLL7, MK30DX64VMC7, MK30DX128VMC7, MK30DX256VMC7 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator • System peripherals – Multiple low-power modes to provide power optimization based on application requirements – 16-channel DMA controller, supporting up to 63 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit • Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip • Human-machine interface – Segment LCD controller supporting up to 36 frontplanes and 8 backplanes, or 40 frontplanes and 4 backplanes, depending on the package size – Low-power hardware touch sensor interface (TSI) – General-purpose input/output • Analog modules – Two 16-bit SAR ADCs – Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – 12-bit DAC – Three analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference • Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timer – Two 2-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock • Communication interfaces – Controller Area Network (CAN) module – Two SPI modules – Two I2C modules – Five UART modules – I2S module Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................3 5.4.2 Thermal attributes.................................................20 1.1 Determining valid orderable parts......................................3 6 Peripheral operating requirements and behaviors....................22 2 Part identification......................................................................3 6.1 Core modules....................................................................22 2.1 Description.........................................................................3 6.1.1 Debug trace timing specifications.........................22 2.2 Format...............................................................................3 6.1.2 JTAG electricals....................................................22 2.3 Fields.................................................................................3 6.2 System modules................................................................25 2.4 Example............................................................................4 6.3 Clock modules...................................................................25 3 Terminology and guidelines......................................................4 6.3.1 MCG specifications...............................................25 3.1 Definition: Operating requirement......................................4 6.3.2 Oscillator electrical specifications.........................27 3.2 Definition: Operating behavior...........................................5 6.3.3 32 kHz Oscillator Electrical Characteristics...........30 3.3 Definition: Attribute............................................................5 6.4 Memories and memory interfaces.....................................30 3.4 Definition: Rating...............................................................6 6.4.1 Flash electrical specifications................................30 3.5 Result of exceeding a rating..............................................6 6.4.2 EzPort Switching Specifications............................35 3.6 Relationship between ratings and operating requirements......................................................................6 6.5 Security and integrity modules..........................................36 6.6 Analog...............................................................................36 3.7 Guidelines for ratings and operating requirements............7 6.6.1 ADC electrical specifications.................................36 3.8 Definition: Typical value.....................................................7 6.6.2 CMP and 6-bit DAC electrical specifications.........43 3.9 Typical value conditions....................................................8 6.6.3 12-bit DAC electrical characteristics.....................46 4 Ratings......................................................................................9 6.6.4 Voltage reference electrical specifications............49 4.1 Thermal handling ratings...................................................9 6.7 Timers................................................................................50 4.2 Moisture handling ratings..................................................9 6.8 Communication interfaces.................................................50 4.3 ESD handling ratings.........................................................9 6.8.1 CAN switching specifications................................50 4.4 Voltage and current operating ratings...............................9 6.8.2 DSPI switching specifications (limited voltage 5 General.....................................................................................10 range)....................................................................51 5.1 AC electrical characteristics..............................................10 6.8.3 DSPI switching specifications (full voltage range).52 5.2 Nonswitching electrical specifications...............................10 6.8.4 I2C switching specifications..................................54 5.2.1 Voltage and current operating requirements.........10 6.8.5 UART switching specifications..............................54 5.2.2 LVD and POR operating requirements.................11 6.8.6 I2S/SAI Switching Specifications..........................54 5.2.3 Voltage and current operating behaviors..............12 5.2.4 Power mode transition operating behaviors..........13 6.9.1 TSI electrical specifications...................................58 5.2.5 Power consumption operating behaviors..............14 6.9.2 LCD electrical characteristics................................59 5.2.6 Designing with radiated emissions in mind...........18 7 Dimensions...............................................................................60 5.2.7 Capacitance attributes..........................................18 7.1 Obtaining package dimensions.........................................60 5.3 Switching specifications.....................................................19 8 Pinout........................................................................................61 6.9 Human-machine interfaces (HMI)......................................58 5.3.1 Device clock specifications...................................19 8.1 K30 Signal Multiplexing and Pin Assignments..................61 5.3.2 General switching specifications...........................19 8.2 K30 Pinouts.......................................................................66 5.4 Thermal specifications.......................................................20 9 Revision History........................................................................68 5.4.1 Thermal operating requirements...........................20 K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 2 Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PK30 and MK30 . 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification K## Kinetis family • K30 A Key attribute • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 3 Terminology and guidelines Field Description Values FFF Program flash memory size • • • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQFP (12 mm x 12 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • • • • • 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 2.4 Example This is an example part number: MK30DN512ZVMD10 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 4 Freescale Semiconductor, Inc. Terminology and guidelines 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit µA 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 5 Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. –0.3 Max. 1.2 Unit V 3.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 6 Freescale Semiconductor, Inc. Terminology and guidelines 3.6 Relationship between ratings and operating requirements e Op ing rat r ( ng ati in. t (m ) n. mi rat e Op ing ) t (m e ir qu re n me ing rat e Op ax .) e ir qu re n me ing rat e Op ng ati ax (m .) r Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) g lin nd Ha in rat n.) mi g( nd Ha g lin ing rat ax (m .) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ Handling (power off) ∞ 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 7 Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 8 Freescale Semiconductor, Inc. Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105°C -100 +100 mA ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol VDD Description Min. Max. Unit Digital supply voltage –0.3 3.8 V Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 9 General Symbol IDD Description Max. Unit — 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V Maximum current single pin limit (applies to all digital pins) –25 25 mA VDD – 0.3 VDD + 0.3 V –0.3 3.8 V ID Digital supply current Min. VDDA Analog supply voltage VBAT RTC battery supply voltage 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have CL=30pF loads, • are configured for fast slew rate (PORTx_PCRn[SRE]=0), and • are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins • have their passive filter disabled (PORTx_PCRn[PFE]=0) 5.2 Nonswitching electrical specifications K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 10 Freescale Semiconductor, Inc. General 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V 0.06 × VDD — V -5 — mA VBAT VIH VIL RTC battery supply voltage Input high voltage Input low voltage VHYS Input hysteresis IICDIO Digital pin negative DC injection current — single pin • VIN < VSS-0.3V IICAIO IICcont 3 mA • VIN < VSS-0.3V (Negative current injection) -5 — • VIN > VDD+0.3V (Positive current injection) — +5 -25 — — +25 1.2 — V VPOR_VBAT — V Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Positive current injection VRFVBAT 1 Analog2, EXTAL, and XTAL pin DC injection current — single pin • Negative current injection VRAM Notes VDD voltage required to retain RAM VBAT voltage required to retain the VBAT register file mA 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 11 General 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V — ±80 — mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) Low-voltage warning thresholds — low range 1 VLVW1L • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V — ±60 — mV VHYSL Low-voltage inhibit reset/recover hysteresis — low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 12 Freescale Semiconductor, Inc. General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA VDD – 0.5 — V • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 — V — 100 mA • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA — 0.5 V • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA — 0.5 V Notes Output high voltage — high drive strength Output high voltage — low drive strength IOHT Output high current total for all ports VOL Output low voltage — high drive strength Output low voltage — low drive strength IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 1 IIN Input leakage current (per pin) at 25°C — 0.025 μA 1 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 2 RPD Internal pulldown resistors 20 50 kΩ 3 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 72 MHz • Bus clock = 36 MHz • Flash clock = 24 MHz K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 13 General Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VLLS1 → RUN • VLLS2 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN Min. Max. Unit Notes — 300 μs 1 — 112 μs — 74 μs — 73 μs — 5.9 μs — 5.8 μs — 4.2 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Typ. Max. Unit Notes — — See note mA 1 Run mode current — all peripheral clocks disabled, code executing from flash • @ 1.8V • @ 3.0V IDD_RUN Min. 2 — 21.5 25 mA — 21.5 30 mA Run mode current — all peripheral clocks enabled, code executing from flash • @ 1.8V 3, 4 — 31 34 mA — 31 34 mA — 32 39 mA • @ 3.0V • @ 25°C • @ 125°C IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 12.5 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 7.2 — mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 0.996 — mA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.46 — mA 7 Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 14 Freescale Semiconductor, Inc. General Table 6. Power consumption operating behaviors (continued) Symbol Description IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled IDD_STOP Stop mode current at 3.0 V IDD_VLPS IDD_LLS IDD_VLLS3 IDD_VLLS2 IDD_VLLS1 IDD_VBAT Min. Typ. Max. Unit Notes — 0.61 — mA 8 • @ –40 to 25°C — 0.35 0.567 mA • @ 70°C — 0.384 0.793 mA • @ 105°C — 0.628 1.2 mA • @ –40 to 25°C — 5.9 32.7 μA • @ 70°C — 26.1 59.8 μA • @ 105°C — 98.1 188 μA Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V 9 • @ –40 to 25°C — 2.6 8.6 μA • @ 70°C — 10.3 29.1 μA • @ 105°C — 42.5 92.5 μA Very low-leakage stop mode 3 current at 3.0 V 9 • @ –40 to 25°C — 1.9 5.8 μA • @ 70°C — 6.9 12.1 μA • @ 105°C — 28.1 41.9 μA • @ –40 to 25°C — 1.59 5.5 μA • @ 70°C — 4.3 9.5 μA • @ 105°C — 17.5 34 μA • @ –40 to 25°C — 1.47 5.4 μA • @ 70°C — 2.97 8.1 μA • @ 105°C — 12.41 32 μA — 0.19 0.22 μA — 0.49 0.64 μA — 2.2 3.2 μA Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Average current with RTC and 32kHz disabled at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 15 General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. IDD_VBAT Average current when CPU is not accessing RTC registers Typ. Max. Unit Notes 10 • @ 1.8V • @ –40 to 25°C • @ 70°C • @ 105°C — 0.57 0.67 μA — 0.90 1.2 μA — 2.4 3.5 μA — 0.67 0.94 μA — 1.0 1.4 μA — 2.7 3.9 μA • @ 3.0V • @ –40 to 25°C • @ 70°C • @ 105°C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEE mode. All peripheral clocks disabled. 3. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25MHz core, system, bus and flash clock. MCG configured for FEI mode. 6. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 128 KB of RAM. 10. Includes 32kHz oscillator current and RTC operation. 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 16 Freescale Semiconductor, Inc. General Figure 2. Run mode supply current vs. core frequency K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 17 General Figure 3. VLPR mode supply current vs. core frequency 5.2.6 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.7 Capacitance attributes Table 7. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 18 Freescale Semiconductor, Inc. General 5.3 Switching specifications 5.3.1 Device clock specifications Table 8. Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode fSYS System and core clock — 72 MHz fBUS Bus clock — 50 MHz fFLASH Flash clock — 25 MHz fLPTMR LPTMR clock — 25 MHz VLPR mode1 fSYS System and core clock — 4 MHz fBUS Bus clock — 4 MHz fFLASH Flash clock — 0.5 MHz fERCLK External reference clock — 16 MHz LPTMR clock — 25 MHz LPTMR external reference clock — 16 MHz — 8 MHz fLPTMR_pin fLPTMR_ERCLK fFlexCAN_ERCLK FlexCAN external reference clock fI2S_MCLK I2S master clock — 12.5 MHz fI2S_BCLK I2S bit clock — 4 MHz 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CAN, CMT, and I2C signals. Table 9. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) — Asynchronous path 100 — ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) — Asynchronous path 16 — ns 3 External reset pulse width (digital glitch filter disabled) 100 — ns 3 Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 19 General Table 9. General switching specifications (continued) Symbol Description Mode select (EZP_CS) hold time after reset deassertion Min. Max. Unit 2 — Bus clock cycles Port rise and fall time (high drive strength) Notes 4 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 12 ns • 2.7 ≤ VDD ≤ 3.6V — 6 ns • 1.71 ≤ VDD ≤ 2.7V — 36 ns • 2.7 ≤ VDD ≤ 3.6V — 24 ns • Slew enabled Port rise and fall time (low drive strength) 5 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 12 ns • 2.7 ≤ VDD ≤ 3.6V — 6 ns • 1.71 ≤ VDD ≤ 2.7V — 36 ns • 2.7 ≤ VDD ≤ 3.6V — 24 ns • Slew enabled 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75pF load 5. 15pF load 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 10. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 20 Freescale Semiconductor, Inc. General 5.4.2 Thermal attributes Board type Symbol Description Single-layer (1s) RθJA Four-layer (2s2p) 100 LQFP Unit Notes Thermal 74 resistance, junction to ambient (natural convection) 52 °C/W 1, 2 RθJA Thermal 42 resistance, junction to ambient (natural convection) 40 °C/W 1, 3 Single-layer (1s) RθJMA Thermal 62 resistance, junction to ambient (200 ft./ min. air speed) 42 °C/W 1,3 Four-layer (2s2p) RθJMA Thermal 38 resistance, junction to ambient (200 ft./ min. air speed) 34 °C/W 1,3 — RθJB Thermal resistance, junction to board 23 25 °C/W 4 — RθJC Thermal resistance, junction to case 19 12 °C/W 5 — ΨJT Thermal 4 characterization parameter, junction to package top outside center (natural convection) 2 °C/W 6 1. 2. 3. 4. 5. 6. 121 MAPBGA Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions—Forced Convection (Moving Air) with the board horizontal. For the LQFP, the board meets the JESD51-7 specification. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 21 Peripheral operating requirements and behaviors 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug trace timing specifications Table 11. Debug trace operating behaviors Symbol Description Min. Max. Unit Tcyc Clock period Frequency dependent MHz Twl Low pulse width 2 — ns Twh High pulse width 2 — ns Tr Clock and data rise time — 3 ns Tf Clock and data fall time — 3 ns Ts Data setup 3 — ns Th Data hold 2 — ns Figure 4. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 5. Trace data specifications K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 22 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.1.2 JTAG electricals Table 12. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 25 • Serial Wire Debug 0 50 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 20 — ns • Serial Wire Debug 10 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J2 TCLK cycle period J3 TCLK clock pulse width Table 13. JTAG full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V TCLK frequency of operation • Boundary Scan 0 10 • JTAG and CJTAG 0 20 • Serial Wire Debug 0 40 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.5 — ns — 3 ns J2 TCLK cycle period J3 TCLK clock pulse width J4 MHz TCLK rise and fall times Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 23 Peripheral operating requirements and behaviors Table 13. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z J13 TRST assert time J14 TRST setup time (negation) to TCLK high — 22.1 ns 100 — ns 8 — ns J2 J3 J3 TCLK (input) J4 J4 Figure 6. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 7. Boundary scan (JTAG) timing K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 24 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 8. Test Access Port timing TCLK J14 J13 TRST Figure 9. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors 6.3.1 MCG specifications Table 14. MCG specifications Symbol Description Min. Typ. Max. Unit — 32.768 — kHz 31.25 — 39.0625 kHz Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.6 %fdco 1 Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM only — ± 0.2 ± 0.5 %fdco 1 fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C fints_t Internal reference frequency (slow clock) — user trimmed Notes Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — +0.5/-0.7 — %fdco 1 Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — ± 0.3 ± 0.3 %fdco 1 fintf_ft Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C — 4 — MHz fintf_t Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C 3 — 5 MHz floc_low Loss of external clock minimum frequency — RANGE = 00 (3/5) x fints_t — — kHz floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 (16/5) x fints_t — — kHz 31.25 — 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.98 — MHz FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 2, 3 640 × ffll_ref Mid range (DRS=01) 1280 × ffll_ref Mid-high range (DRS=10) 1920 × ffll_ref High range (DRS=11) 2560 × ffll_ref fdco_t_DMX32 DCO output frequency Low range (DRS=00) 4, 5 732 × ffll_ref Mid range (DRS=01) 1464 × ffll_ref Mid-high range (DRS=10) 2197 × ffll_ref High range (DRS=11) 2929 × ffll_ref Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 26 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 14. MCG specifications (continued) Symbol Jcyc_fll Description FLL period jitter • fVCO = 48 MHz • fVCO = 98 MHz tfll_acquire FLL target frequency acquisition time Min. Typ. Max. Unit — 180 — — 150 — — — 1 ms 48.0 — 100 MHz — 1060 — µA — 600 — µA 2.0 — 4.0 MHz Notes ps 6 PLL fvco VCO operating frequency Ipll PLL operating current • PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) Ipll PLL operating current • PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) fpll_ref PLL reference frequency range Jcyc_pll PLL period jitter (RMS) Jacc_pll 7 8 • fvco = 48 MHz — 120 — ps • fvco = 100 MHz — 50 — ps PLL accumulated jitter over 1µs (RMS) 8 • fvco = 48 MHz — 1350 — ps • fvco = 100 MHz — 600 — ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock 7 Lock detector detection time — — 10-6 150 × + 1075(1/ fpll_ref) s 9 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 27 Peripheral operating requirements and behaviors 6.3.2.1 Oscillator DC electrical specifications Table 15. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Supply current — high gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ — 0 — kΩ RS 2, 4 Series resistor — high-frequency, high-gain mode (HGO=1) Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 28 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 15. Oscillator DC electrical specifications (continued) Symbol Vpp5 1. 2. 3. 4. 5. Description Min. Typ. Max. Unit Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V Notes VDD=3.3 V, Temperature =25 °C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Symbol Oscillator frequency specifications Table 16. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency — low frequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — high frequency mode (low range) (MCG_C2[RANGE]=01) 3 — 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz fec_extal Input clock frequency (external clock mode) — — 50 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 750 — ms Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — 250 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms tcst Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 29 Peripheral operating requirements and behaviors 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3.3 32 kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 32 kHz oscillator DC electrical specifications Table 17. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VBAT Supply voltage 1.71 — 3.6 V Internal feedback resistor — 100 — MΩ Cpara Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation — 0.6 — V RF 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 Symbol fosc_lo tstart 32kHz oscillator frequency specifications Table 18. 32kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal — 32.768 — kHz Crystal start-up time — 1000 — ms 1 700 — VBAT mV 2, 3 vec_extal32 Externally provided input clock amplitude Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 6.4 Memories and memory interfaces 6.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 30 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 19. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 thversscr Notes Longword Program high-voltage time — 7.5 18 μs Sector Erase high-voltage time — 13 113 ms 1 thversblk32k Erase Block high-voltage time for 32 KB — 52 452 ms 1 thversblk256k Erase Block high-voltage time for 256 KB — 104 904 ms 1 Notes 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Symbol Flash timing specifications — commands Table 20. Flash command timing specifications Description Min. Typ. Max. Unit Read 1s Block execution time trd1blk32k • 32 KB data flash — — 0.5 ms trd1blk256k • 256 KB program flash — — 1.7 ms trd1sec1k Read 1s Section execution time (data flash sector) — — 60 μs 1 trd1sec2k Read 1s Section execution time (program flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs Erase Flash Block execution time 2 tersblk32k • 32 KB data flash — 55 465 ms tersblk256k • 256 KB program flash — 122 985 ms — 14 114 ms tersscr Erase Flash Sector execution time 2 Program Section execution time tpgmsec512p • 512 B program flash — 2.4 — ms tpgmsec512d • 512 B data flash — 4.7 — ms tpgmsec1kp • 1 KB program flash — 4.7 — ms tpgmsec1kd • 1 KB data flash — 9.3 — ms trd1all Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 25 μs Program Once execution time — 65 — μs Erase All Blocks execution time — 175 1500 ms tpgmonce tersall 1 2 Table continues on the next page... K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 31 Peripheral operating requirements and behaviors Table 20. Flash command timing specifications (continued) Symbol tvfykey Description Verify Backdoor Access Key execution time Min. Typ. Max. Unit Notes — — 30 μs 1 Swap Control execution time tswapx01 • control code 0x01 — 200 — μs tswapx02 • control code 0x02 — 70 150 μs tswapx04 • control code 0x04 — 70 150 μs tswapx08 • control code 0x08 — — 30 μs — 70 — ms Program Partition for EEPROM execution time tpgmpart32k • 32 KB FlexNVM Set FlexRAM Function execution time: tsetramff • Control Code 0xFF — 50 — μs tsetram8k • 8 KB EEPROM backup — 0.3 0.5 ms tsetram32k • 32 KB EEPROM backup — 0.7 1.0 ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time — 175 260 μs 3 Byte-write to FlexRAM execution time: teewr8b8k • 8 KB EEPROM backup — 340 1700 μs teewr8b16k • 16 KB EEPROM backup — 385 1800 μs teewr8b32k • 32 KB EEPROM backup — 475 2000 μs Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 175 260 μs Word-write to FlexRAM execution time: teewr16b8k • 8 KB EEPROM backup — 340 1700 μs teewr16b16k • 16 KB EEPROM backup — 385 1800 μs teewr16b32k • 32 KB EEPROM backup — 475 2000 μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 360 540 μs Longword-write to FlexRAM execution time: teewr32b8k • 8 KB EEPROM backup — 545 1950 μs teewr32b16k • 16 KB EEPROM backup — 630 2050 μs teewr32b32k • 32 KB EEPROM backup — 810 2250 μs 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 32 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.4.1.3 Flash high voltage current behaviors Table 21. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 6.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 2.5 6.0 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 22. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles 2 Data Flash tnvmretd10k Data retention after up to 10 K cycles 5 50 — years tnvmretd1k Data retention after up to 1 K cycles 20 100 — years nnvmcycd Cycling endurance 10 K 50 K — cycles 2 FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance 5 50 — years tnvmretee10 Data retention up to 10% of write endurance 20 100 — years Write endurance 3 nnvmwree16 • EEPROM backup to FlexRAM ratio = 16 35 K 175 K — writes nnvmwree128 • EEPROM backup to FlexRAM ratio = 128 315 K 1.6 M — writes nnvmwree512 • EEPROM backup to FlexRAM ratio = 512 1.27 M 6.4 M — writes nnvmwree4k • EEPROM backup to FlexRAM ratio = 4096 10 M 50 M — writes nnvmwree8k • EEPROM backup to FlexRAM ratio = 8192 20 M 100 M — writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM. 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 33 Peripheral operating requirements and behaviors The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = EEPROM – 2 × EEESPLIT × EEESIZE EEESPLIT × EEESIZE × Write_efficiency × nnvmcycd where • Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycd — data flash cycling endurance (the following graph assumes 10,000 cycles) K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 34 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 10. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 23. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V EP1 EZP_CK frequency of operation (all commands except READ) — fSYS/2 MHz EP1a EZP_CK frequency of operation (READ command) — fSYS/8 MHz EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns EP7 EZP_CK low to EZP_Q output valid — 16 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns EP9 EZP_CS negation to EZP_Q tri-state — 12 ns K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 35 Peripheral operating requirements and behaviors EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 11. EzPort Timing Diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 24 and Table 25 are achievable on the differential pins ADCx_DP0, ADCx_DM0. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 26 and Table 27. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. K30 Sub-Family Data Sheet, Rev. 3, 11/2012. 36 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.1.1 16-bit ADC operating conditions Table 24. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.6 V ΔVDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage • 16-bit differential mode VREFL — 31/32 * VREFH V • All other modes VREFL — • 16-bit mode — 8 10 • 8-/10-/12-bit modes — 4 5 — 2 5 CADIN RADIN RAS Input capacitance Input resistance Notes VREFH pF kΩ Analog source resistance 13-/12-bit modes fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13 bit modes No ADC hardware averaging 3 5 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16-bit mode No ADC hardware averaging 5 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1ns. 4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool K30 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc. 37 Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection Z AS R AS ADC SAR ENGINE R ADIN V ADIN C AS V AS R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 12. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current fADACK ADC asynchronous clock source Sample Time TUE DNL INL EFS Conditions1 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 •
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