Freescale Semiconductor
Data Sheet: Technical Data
K60 Sub-Family
Document Number K60P144M150SF3
Rev. 6, 09/2015
K60P144M150SF3
Supports the following:
MK60FX512VLQ15,
MK60FN1M0VLQ15,
MK60FX512VMD15,
MK60FN1M0VMD15
Key features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 150 MHz ARM® Cortex®-M4 core with
DSP instructions delivering 1.25 Dhrystone
MIPS per MHz
• Memories and memory interfaces
– Up to 1024 KB program flash memory on nonFlexMemory devices
– Up to 512 KB program flash memory on
FlexMemory devices
– Up to 512 KB FlexNVM on FlexMemory devices
– 16 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– NAND flash controller interface
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 32-channel DMA controller, supporting up to
128 request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– Hardware random-number generator
– Hardware encryption supporting DES, 3DES,
AES, MD5, SHA-1, and SHA-256 algorithms
– 128-bit unique identification (ID) number per
chip
• Human-machine interface
– Low-power hardware touch sensor interface
(TSI)
– General-purpose input/output
• Analog modules
– Four 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Two 12-bit DACs
– Four analog comparators (CMP) containing a 6bit DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Two 8-channel motor control/general
purpose/PWM timers
– Two 2-channel quadrature decoder/general
purpose timers
– IEEE 1588 timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012–2015 Freescale Semiconductor, Inc.
• Communication interfaces
– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
– USB high-/full-/low-speed On-the-Go controller with ULPI interface
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– USB Device Charger detect (USBDCD)
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital Host Controller (SDHC)
– Two I2S modules
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Table of Contents
1 Ordering parts........................................................................... 5
6.2 System modules................................................................ 27
1.1 Determining valid orderable parts......................................5
6.3 Clock modules................................................................... 27
2 Part identification...................................................................... 5
6.3.1
MCG specifications.............................................27
2.1 Description.........................................................................5
6.3.2
Oscillator electrical specifications....................... 30
2.2 Format............................................................................... 5
6.3.3
32 kHz oscillator electrical characteristics.......... 32
2.3 Fields................................................................................. 5
6.4 Memories and memory interfaces..................................... 32
2.4 Example............................................................................ 6
6.4.1
Flash (FTFE) electrical specifications.................32
3 Terminology and guidelines...................................................... 6
6.4.2
EzPort switching specifications...........................37
3.1 Definitions..........................................................................6
6.4.3
NFC specifications..............................................38
3.2 Examples...........................................................................6
6.4.4
Flexbus switching specifications.........................41
3.3 Typical-value conditions.................................................... 7
6.5 Security and integrity modules.......................................... 44
3.4 Relationship between ratings and operating
6.6 Analog............................................................................... 44
requirements......................................................................7
6.6.1
ADC electrical specifications.............................. 44
3.5 Guidelines for ratings and operating requirements............8
6.6.2
CMP and 6-bit DAC electrical specifications...... 52
4 Ratings...................................................................................... 8
6.6.3
12-bit DAC electrical characteristics................... 54
4.1 Thermal handling ratings................................................... 8
6.6.4
Voltage reference electrical specifications..........57
4.2 Moisture handling ratings.................................................. 9
6.7 Timers................................................................................58
4.3 ESD handling ratings.........................................................9
6.8 Communication interfaces................................................. 58
4.4 Voltage and current operating ratings............................... 9
6.8.1
Ethernet switching specifications........................58
5 General..................................................................................... 10
6.8.2
USB electrical specifications...............................60
5.1 AC electrical characteristics.............................................. 10
6.8.3
USB DCD electrical specifications......................61
5.2 Nonswitching electrical specifications............................... 10
6.8.4
USB VREG electrical specifications................... 61
5.2.1
Voltage and current operating requirements...... 10
6.8.5
ULPI timing specifications...................................62
5.2.2
LVD and POR operating requirements............... 11
6.8.6
CAN switching specifications..............................63
5.2.3
Voltage and current operating behaviors............12
6.8.7
DSPI switching specifications (limited voltage
5.2.4
Power mode transition operating behaviors....... 14
5.2.5
Power consumption operating behaviors............15
5.2.6
EMC radiated emissions operating behaviors.... 18
5.2.7
Designing with radiated emissions in mind.........19
6.8.9
Inter-Integrated Circuit Interface (I2C) timing..... 66
5.2.8
Capacitance attributes........................................ 19
6.8.10
UART switching specifications............................67
5.3 Switching specifications.....................................................19
6.8.11
SDHC specifications........................................... 67
6.8.12
I2S/SAI switching specifications......................... 68
5.3.1
Device clock specifications................................. 19
5.3.2
General switching specifications.........................20
5.4 Thermal specifications.......................................................22
range)................................................................. 63
6.8.8
DSPI switching specifications (full voltage
range)................................................................. 64
6.9 Human-machine interfaces (HMI)......................................75
6.9.1
TSI electrical specifications................................ 75
5.4.1
Thermal operating requirements.........................22
7 Dimensions............................................................................... 76
5.4.2
Thermal attributes...............................................22
7.1 Obtaining package dimensions......................................... 76
6 Peripheral operating requirements and behaviors.................... 23
8 Pinout........................................................................................ 76
6.1 Core modules.................................................................... 23
8.1 Pins with active pull control after reset.............................. 76
6.1.1
Debug trace timing specifications....................... 23
8.2 K60 Signal Multiplexing and Pin Assignments.................. 77
6.1.2
JTAG electricals..................................................24
8.3 K60 pinouts....................................................................... 83
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3
9 Revision History........................................................................ 85
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Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK60 and MK60
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K60
A
Key attribute
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
• 512 = 512 KB
• 1M0 = 1 MB
Table continues on the next page...
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Terminology and guidelines
Field
Description
Values
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
• 15 = 150 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK60FN1M0VLQ15
3 Terminology and guidelines
3.1 Definitions
Key terms are defined in the following table:
Term
Rating
Definition
A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent
chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement
A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
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Terminology and guidelines
3.2 Examples
EX
A
M
PL
E
Operating rating:
EX
AM
PL
E
Operating requirement:
EX
AM
PL
E
Operating behavior that includes a typical value:
3.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
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Ratings
3.4 Relationship between ratings and operating requirements
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Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
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- No permanent failure
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Expected permanent failure
–∞
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Expected permanent failure
–∞
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Handling (power off)
3.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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Ratings
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage1
–0.3
3.8
V
IDD
Digital supply current
—
300
mA
VDIO
Digital input voltage (except RESET, EXTAL0/XTAL0, and
EXTAL1/XTAL1) 2
–0.3
5.5
V
VAIO
Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input
voltage
–0.3
VDD + 0.3
V
Maximum current single pin limit (applies to all digital pins)
–25
25
mA
ID
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
VDDA
USB0_DP input voltage
–0.3
3.63
V
VUSB1_DP
USB1_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
VUSB1_DM
USB1_DM input voltage
–0.3
3.63
V
VREGIN
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
Analog supply voltage
1. It applies for all port pins.
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General
2. It covers digital pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
Notes
Table continues on the next page...
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General
Table 1. Voltage and current operating requirements (continued)
Symbol
Min.
Max.
Unit
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
VHYS
Input hysteresis (digital pins)
0.06 × VDD
—
V
IICDIO
Digital pin negative DC injection current —
single pin
-5
—
mA
VBAT
VIH
VIL
Description
RTC battery supply voltage
Notes
Input high voltage (digital pins)
Input low voltage (digital pins)
1
• VIN < VSS-0.3V
IICAIO
Analog2, EXTAL0/XTAL0, and EXTAL1/
XTAL1 pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current
injection)
• VIN > VDD+0.3V (Positive current
injection)
IICcont
Contiguous pin DC injection current —
regional limit, includes sum of negative
injection currents or sum of positive injection
currents of 16 contiguous pins
• Negative current injection
3
mA
-5
—
—
+5
-25
—
—
+25
mA
• Positive current injection
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
VBAT voltage required to retain the VBAT
register file
4
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection
current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
4. Open drain outputs must be pulled to VDD.
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General
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
2.62
2.70
2.78
V
2.72
2.80
2.88
V
2.82
2.90
2.98
V
2.92
3.00
3.08
V
—
±80
—
mV
1.54
1.60
1.66
V
1.74
1.80
1.86
V
1.84
1.90
1.96
V
1.94
2.00
2.06
V
2.04
2.10
2.16
V
—
±60
—
mV
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
VLVW2L
VLVW3L
VLVW4L
VHYSL
1
• Level 4 falling (LVWV=11)
VHYSH
VLVW1L
Notes
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
1
• Level 4 falling (LVWV=11)
Low-voltage inhibit reset/recover hysteresis —
low range
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period
900
1000
1100
μs
factory trimmed
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Typ.
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
VDD – 0.5
—
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
Output high voltage — high drive strength
Max.
Unit
Notes
—
—
V
V
Table continues on the next page...
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General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Typ.
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
Output high current total for all ports
—
—
100
mA
Output high current total for fast digital ports
—
—
100
mA
0.5
V
0.5
V
0.5
V
0.5
V
Output high voltage — low drive strength
IOHT
IOHT_io60
VOL
IOLT_io60
IINA
Unit
Notes
—
Output low voltage — high drive strength
—
V
V
—
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
—
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
—
—
Output low voltage — low drive strength
IOLT
Max.
—
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
—
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1 mA
—
—
Output low current total for all ports
—
—
100
mA
Output low current total for fast digital ports
—
—
100
mA
1, 2
Input leakage current, analog pins and digital
pins configured as analog inputs
• VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32,
EXTAL, XTAL
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32
IIND
—
0.002
0.5
μA
—
0.004
1.5
μA
—
0.075
10
μA
Input leakage current, digital pins
2, 3
• VSS ≤ VIN ≤ VIL
• All digital pins
—
0.002
0.5
μA
—
0.002
0.5
μA
—
0.004
1
μA
• VIN = VDD
• All digital pins except PTD7
• PTD7
IIND
2, 3,
Input leakage current, digital pins
4
• VIL < VIN < VDD
IIND
• VDD = 3.6 V
—
18
26
μA
• VDD = 3.0 V
—
12
19
μA
• VDD = 2.5 V
—
8
13
μA
• VDD = 1.7 V
—
3
6
μA
Input leakage current, digital pins
• VDD < VIN < 5.5 V
ZIND
2, 3
—
1
50
μA
2,
Input impedance examples, digital pins
—
—
48
5
kΩ
Table continues on the next page...
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General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• VDD = 3.6 V
—
—
55
kΩ
• VDD = 3.0 V
—
—
57
kΩ
• VDD = 2.5 V
—
—
85
kΩ
Notes
• VDD = 1.7 V
RPU
Internal pullup resistors
20
—
50
kΩ
6
RPD
Internal pulldown resistors
20
—
50
kΩ
7
1.
2.
3.
4.
5.
Analog pins are defined as pins that do not have an associated general purpose I/O port function.
Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
Internal pull-up/pull-down resistors disabled.
Characterized, not tested in production.
Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. See
Figure 2.
6. Measured at VDD supply voltage = VDD min and Vinput = VSS
7. Measured at VDD supply voltage = VDD min and Vinput = VDD
Figure 2. 5 V Tolerant Input IIND Parameter
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
•
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
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General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Max.
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
Unit
Notes
1
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
μs
—
300
—
1.7 V / (VDD
slew rate)
—
160
μs
—
114
μs
—
114
μs
—
5.0
μs
—
5
μs
—
4.8
μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
IDD_RUN
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
2
• @ 1.8V
—
58.01
83.95
mA
• @ 3.0V
—
57.93
84.14
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
3
• @ 1.8V
—
89.26
116.53
mA
• @ 3.0V
—
89.23
117.26
mA
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
40.18
65.25
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
—
18.08
42.96
mA
4
IDD_STOP
Stop mode current at 3.0 V
—
1.25
1.62
mA
—
2.93
4.39
mA
• @ –40 to 25°C
Table continues on the next page...
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15
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
• @ 70°C
Min.
Typ.
Max.
Unit
—
7.08
10.74
mA
Notes
• @ 105°C
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
1.03
4.48
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.58
4.96
mA
5
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
0.64
4.29
mA
5
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
—
0.22
0.38
mA
• @ 70°C
—
0.78
1.33
mA
• @ 105°C
—
2.18
3.56
mA
• @ –40 to 25°C
—
0.22
0.37
mA
• @ 70°C
—
0.78
1.33
mA
• @ 105°C
—
2.16
3.52
mA
• @ –40 to 25°C
—
4.09
5.58
μA
• @ 70°C
—
20.98
28.93
μA
• @ 105°C
—
84.95
111.15
μA
• @ –40 to 25°C
—
2.68
4.22
μA
• @ 70°C
—
8.8
10.74
μA
• @ 105°C
—
37.28
43.61
μA
• @ –40 to 25°C
—
2.46
4.02
μA
• @ 70°C
—
7.04
8.99
μA
• @ 105°C
—
30.68
37.04
μA
IDD_LLS
IDD_VLLS3
IDD_VLLS2
IDD_VLLS1
IDD_VBAT
Low leakage stop mode current at 3.0 V
Very low-leakage stop mode 3 current at 3.0 V
Very low-leakage stop mode 2 current at 3.0 V
Very low-leakage stop mode 1 current at 3.0 V
Average current when CPU is not accessing
RTC registers at 3.0 V
6
• @ –40 to 25°C
—
0.89
1.10
μA
• @ 70°C
—
1.28
1.85
μA
• @ 105°C
—
3.10
4.30
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled, but peripherals are not in active operation.
4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode.
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General
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. Includes 32kHz oscillator current and RTC operation.
5.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies. MCG in PEE mode at greater than 100 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
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17
General
Figure 4. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 256MAPBGA
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
1, 2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
21
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
24
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
29
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
28
dBμV
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 72 MHz, fBUS = 72 MHz
3. Determined according to IEC Standard JESD78, IC Latch-Up Test
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General
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
Input capacitance: fast digital pins
—
9
pF
CIN_D_io60
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
150
MHz
fSYS_USBFS
System and core clock when Full Speed USB in
operation
20
—
MHz
fSYS_USBHS
System and core clock when High Speed USB in
operation
60
—
MHz
fENET
System and core clock when ethernet in operation
Notes
Normal run mode
fSYS
• 10 Mbps
• 100 Mbps
MHz
5
—
50
—
Bus clock
—
75
MHz
FlexBus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
—
4
MHz
fBUS
FB_CLK
VLPR
fSYS
System and core clock
mode1
Table continues on the next page...
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19
General
Table 9. Device clock specifications (continued)
Symbol
Min.
Max.
Unit
Bus clock
—
4
MHz
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
0.5
MHz
fLPTMR
LPTMR clock
—
4
MHz
fBUS
FB_CLK
Description
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
2
—
Bus clock
cycles
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
14
ns
• 2.7 ≤ VDD ≤ 3.6V
—
8
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Port rise and fall time (low drive strength)
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
14
ns
• 2.7 ≤ VDD ≤ 3.6V
—
8
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
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General
Table 10. General switching specifications (continued)
Symbol
tio50
Description
Min.
Max.
Unit
Notes
6
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
7
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
3
ns
—
• 1.71 ≤ VDD ≤ 2.7V
—
28
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
14
ns
—
• Slew enabled
tio50
7
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
18
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
9
ns
—
• 1.71 ≤ VDD ≤ 2.7V
—
48
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
—
• Slew enabled
tio60
6
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
6
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
3
ns
—
• 1.71 ≤ VDD ≤ 2.7V
—
28
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
14
ns
—
• Slew enabled
tio60
7
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
18
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
—
• 1.71 ≤ VDD ≤ 2.7V
—
48
ns
—
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
—
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
6. 25 pF load
7. 15 pF load
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General
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
TA
Description
Min.
Max.
Unit
Die junction temperature
–40
125
°C
–40
105
°C
Ambient
temperature1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
5.4.2 Thermal attributes
Board type
Symbol
Description
144 LQFP
144 MAPBGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
45
resistance,
junction to
ambient (natural
convection)
50
°C/W
1, 2
Four-layer
(2s2p)
RθJA
Thermal
36
resistance,
junction to
ambient (natural
convection)
30
°C/W
1,2, 3
Single-layer
(1s)
RθJMA
Thermal
36
resistance,
junction to
ambient (200 ft./
min. air speed)
41
°C/W
1,3
Four-layer
(2s2p)
RθJMA
Thermal
30
resistance,
junction to
ambient (200 ft./
min. air speed)
27
°C/W
1,3
—
RθJB
Thermal
resistance,
junction to
board
24
17
°C/W
4
—
RθJC
Thermal
resistance,
junction to case
9
10
°C/W
5
—
ΨJT
Thermal
2
characterization
2
°C/W
6
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Peripheral operating requirements and behaviors
Board type
Symbol
Description
144 LQFP
144 MAPBGA
Unit
Notes
parameter,
junction to
package top
outside center
(natural
convection)
NOTES:
1. Junction temperature is a function of die size, on-chip power dissipation, package
thermal resistance, mounting site (board) temperature, ambient temperature, air flow,
power dissipation of other components on the board, and board thermal resistance.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air) with the
single layer board horizontal. Board meets JESD51-9 specification.
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuit Thermal
Test Method Environmental Conditions—Forced Convection (Moving Air) with the
board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental Conditions—Junction-to-Board. Board temperature is
measured on the top surface of the board near the package.
5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,
Microcircuits, with the cold plate temperature used for the case temperature. The
value includes the thermal resistance of the interface material between the top of the
package and the cold plate.
6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 12. Debug trace operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
—
ns
Th
Data hold
2
—
ns
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 13. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.4
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Table 14. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
—
3
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.4
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
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Peripheral operating requirements and behaviors
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
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Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
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Peripheral operating requirements and behaviors
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 4.5
—
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Δfdco_t
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
2, 3
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
4, 5
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
ps
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol
Description
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
Min.
Typ.
Max.
Unit
Notes
—
150
—
—
—
1
ms
6
8
—
16
MHz
PLL0,1
fpll_ref
PLL reference frequency range
fvcoclk_2x
VCO output frequency
fvcoclk
PLL output frequency
fvcoclk_90
180
90
PLL quadrature output frequency
Ipll
PLL0 operating current
• VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 23)
Ipll
PLL0 operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 45)
Ipll
PLL1 operating current
• VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 23)
Ipll
PLL1 operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 45)
tpll_lock
Lock detector detection time
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
90
—
—
—
360
180
180
MHz
MHz
MHz
—
2.8
—
mA
—
4.7
—
mA
—
2.3
—
mA
—
3.6
—
mA
—
—
100 × 10-6
+ 1075(1/
fpll_ref)
s
7
7
7
8
9
• fvco = 180 MHz
—
100
—
ps
• fvco = 360 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
10
• fvco = 180 MHz
—
600
—
ps
• fvco = 360 MHz
—
300
—
ps
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. Accumulated jitter depends on VCO frequency and VDIV.
K60 Sub-Family, Rev.6, 09/2015.
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29
Peripheral operating requirements and behaviors
6.3.2 Oscillator electrical specifications
6.3.2.1
Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 16. Oscillator DC electrical specifications (continued)
Symbol
Vpp5
1.
2.
3.
4.
5.
Description
Min.
Typ.
Max.
Unit
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
6.3.2.2
Symbol
Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
60
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
1000
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
500
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1
2, 3
4, 5
1. Frequencies less than 8 MHz are not in the PLL range.
2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
3. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
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Peripheral operating requirements and behaviors
4. Proper PC board layout procedures must be followed to achieve specifications.
5. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz oscillator electrical characteristics
6.3.3.1
32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2
Symbol
fosc_lo
tstart
32 kHz oscillator frequency specifications
Table 19. 32 kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
1
700
—
VBAT
mV
2, 3
vec_extal32 Externally provided input clock amplitude
Notes
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
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6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm8
thversscr
Notes
Program Phrase high-voltage time
—
7.5
18
μs
Erase Flash Sector high-voltage time
—
13
113
ms
1
thversblk128k Erase Flash Block high-voltage time for 128 KB
—
104
1808
ms
1
thversblk256k Erase Flash Block high-voltage time for 256 KB
—
208
3616
ms
1
Notes
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Symbol
Flash timing specifications — commands
Table 21. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
Read 1s Block execution time
trd1blk128k
• 128 KB data flash
—
—
0.5
ms
trd1blk256k
• 256 KB program flash
—
—
1.0
ms
256 KB data flash
trd1sec4k
Read 1s Section execution time (4 KB flash)
—
—
100
μs
1
tpgmchk
Program Check execution time
—
—
80
μs
1
trdrsrc
Read Resource execution time
—
—
40
μs
1
tpgm8
Program Phrase execution time
—
70
150
μs
Erase Flash Block execution time
2
tersblk128k
• 128 KB data flash
—
110
925
ms
tersblk256k
• 256 KB program flash
—
220
1850
ms
Erase Flash Sector execution time
—
15
115
ms
Program Section execution time (4KB flash)
—
20
—
ms
256 KB data flash
tersscr
tpgmsec4k
2
Read 1s All Blocks execution time
trd1allx
• FlexNVM devices
—
—
3.4
ms
trd1alln
• Program flash only devices
—
—
3.4
ms
Read Once execution time
—
—
30
μs
Program Once execution time
—
70
—
μs
tersall
Erase All Blocks execution time
—
650
5600
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
trdonce
tpgmonce
1
Swap Control execution time
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
tswapx01
• control code 0x01
—
200
—
μs
tswapx02
• control code 0x02
—
70
150
μs
tswapx04
• control code 0x04
—
70
150
μs
tswapx08
• control code 0x08
—
—
30
μs
Notes
Program Partition for EEPROM execution time
tpgmpart64k
• 64 KB EEPROM backup
—
235
—
ms
tpgmpart256k
• 256 KB EEPROM backup
—
240
—
ms
• Control Code 0xFF
—
205
—
μs
tsetram64k
• 64 KB EEPROM backup
—
1.6
2.5
ms
tsetram128k
• 128 KB EEPROM backup
—
2.7
3.8
ms
tsetram256k
• 256 KB EEPROM backup
—
4.8
6.2
ms
—
140
225
μs
Set FlexRAM Function execution time:
tsetramff
t eewr8bers
Byte-write to erased FlexRAM location execution
time
3
Byte-write to FlexRAM execution time:
teewr8b64k
• 64 KB EEPROM backup
—
400
1700
μs
teewr8b128k
• 128 KB EEPROM backup
—
450
1800
μs
teewr8b256k
• 256 KB EEPROM backup
—
525
2000
μs
—
140
225
μs
t eewr16bers 16-bit write to erased FlexRAM location
execution time
16-bit write to FlexRAM execution time:
teewr16b64k
• 64 KB EEPROM backup
—
400
1700
μs
teewr16b128k
• 128 KB EEPROM backup
—
450
1800
μs
teewr16b256k
• 256 KB EEPROM backup
—
525
2000
μs
—
180
275
μs
teewr32bers 32-bit write to erased FlexRAM location
execution time
32-bit write to FlexRAM execution time:
teewr32b64k
• 64 KB EEPROM backup
—
475
1850
μs
teewr32b128k
• 128 KB EEPROM backup
—
525
2000
μs
teewr32b256k
• 256 KB EEPROM backup
—
600
2200
μs
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
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Peripheral operating requirements and behaviors
6.4.1.3
Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
6.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current
adder during high
voltage flash
programming
operation
—
3.5
7.5
mA
Average current
adder during high
voltage flash erase
operation
—
1.5
4.0
mA
Reliability specifications
Table 23. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
tnvmretd10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretd1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycd
Cycling endurance
10 K
50 K
—
cycles
2
Data Flash
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
20 K
50 K
—
cycles
nnvmcycee
Cycling endurance for EEPROM backup
Write endurance
2
3
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
70 K
175 K
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
630 K
1.6 M
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
2.5 M
6.4 M
—
writes
nnvmwree2k
• EEPROM backup to FlexRAM ratio = 2,048
10 M
25 M
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values assume all 16bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.
K60 Sub-Family, Rev.6, 09/2015.
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Peripheral operating requirements and behaviors
6.4.1.5
Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that can
be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Writes_subsystem =
EEPROM – 2 × EEESPLIT × EEESIZE
EEESPLIT × EEESIZE
× Write_efficiency × n nvmcycee
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
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Peripheral operating requirements and behaviors
Figure 11. EEPROM backup writes to FlexRAM
6.4.2 EzPort switching specifications
Table 24. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
16
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
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Peripheral operating requirements and behaviors
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 12. EzPort Timing Diagram
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• TH is the flash clock high time and
• TL is flash clock low time,
which are defined as:
T NFC = T L + T H =
T input clock
SCALER
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SCALER =
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,
means TH = TL. In case the reciprocal of SCALER is not an integer:
T L = (1 + SCALER / 2) x
T NFC
2
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Peripheral operating requirements and behaviors
T H = (1 – SCALER / 2) x
T NFC
2
For example, if SCALER is 0.2, then TH = TL = TNFC/2.
TNFC
TH
TL
However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC.
TNFC
TH
TL
NOTE
The reciprocal of SCALER must be a multiple of 0.5. For
example, 1, 1.5, 2, 2.5, etc.
Table 25. NFC specifications
Num
Description
Min.
Max.
Unit
tCLS
NFC_CLE setup time
2TH + TL – 1
—
ns
tCLH
NFC_CLE hold time
TH + TL – 1
—
ns
tCS
NFC_CEn setup time
2TH + TL – 1
—
ns
tCH
NFC_CEn hold time
TH + TL
—
ns
tWP
NFC_WP pulse width
TL – 1
—
ns
tALS
NFC_ALE setup time
2TH + TL
—
ns
tALH
NFC_ALE hold time
TH + TL
—
ns
tDS
Data setup time
TL – 1
—
ns
tDH
Data hold time
TH – 1
—
ns
tWC
Write cycle time
TH + TL – 1
—
ns
tWH
NFC_WE hold time
TH – 1
—
ns
tRR
Ready to NFC_RE low
4TH + 3TL + 90
—
ns
tRP
NFC_RE pulse width
TL + 1
—
ns
tRC
Read cycle time
TL + TH – 1
—
ns
tREH
NFC_RE high hold time
TH – 1
—
ns
tIS
Data input setup time
11
—
ns
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39
Peripheral operating requirements and behaviors
NFC_CLE
tCLS
tCLH
NFC_CEn
tCS
tWP
tCH
NFC_WE
tDS
tDH
NFC_IOn
Figure 13. Command latch cycle timing
NFC_ALE
tALS
tALH
NFC_CEn
tCS
tWP
tCH
NFC_WE
tDS
NFC_IOn
tDH
address
Figure 14. Address latch cycle timing
tCS
tCH
tWC
NFC_CEn
tWP
tWH
tDS
tDH
NFC_WE
NFC_IOn
data
data
data
Figure 15. Write data latch cycle timing
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Peripheral operating requirements and behaviors
tCH
tRC
NFC_CEn
tREH
tRP
NFC_RE
tIS
NFC_IOn
data
data
data
tRR
NFC_RB
Figure 16. Read data latch cycle timing in non-fast mode
tCH
tRC
NFC_CEn
tRP
tREH
NFC_RE
tIS
NFC_IOn
data
data
data
tRR
NFC_RB
Figure 17. Read data latch cycle timing in fast mode
6.4.4 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 26. Flexbus limited voltage range switching specifications
Num
FB1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
FB_CLK
MHz
Clock period
20
—
ns
Notes
Table continues on the next page...
K60 Sub-Family, Rev.6, 09/2015.
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41
Peripheral operating requirements and behaviors
Table 26. Flexbus limited voltage range switching specifications (continued)
Num
Description
Min.
Max.
Unit
Notes
FB2
Address, data, and control output valid
—
11.5
ns
1
FB3
Address, data, and control output hold
0.5
—
ns
1
FB4
Data and FB_TA input setup
8.5
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 27. Flexbus full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
—
FB_CLK
MHz
1/FB_CLK
—
ns
—
13.5
ns
1
Frequency of operation
Notes
FB1
Clock period
FB2
Address, data, and control output valid
FB3
Address, data, and control output hold
0
—
ns
1
FB4
Data and FB_TA input setup
13.7
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
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Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB5
FB_A[Y]
Address
FB4
FB2
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 18. FlexBus read timing diagram
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Peripheral operating requirements and behaviors
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 19. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
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Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 28 and Table 29 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 30 and
Table 31.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1
16-bit ADC operating conditions
Table 28. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 ×
VREFH
V
• All other modes
VREFL
—
• 16-bit mode
—
8
10
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
CADIN
RADIN
RAS
Input capacitance
Input series
resistance
Notes
VREFH
pF
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
5
No ADC hardware averaging
37.037
—
461.467
ksps
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Peripheral operating requirements and behaviors
Table 28. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 20. ADC input impedance equivalency diagram
6.6.1.2
16-bit ADC electrical characteristics
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
IDDA_ADC Supply current
fADACK
ADC asynchronous
clock source
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Sample Time
TUE
DNL
INL
EFS
EQ
ENOB
Conditions1
Min.
Typ.2
Max.
Unit
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN = VDDA5
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
•
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