NXP Semiconductors
Data Sheet: Technical Data
K63P144M120SF5
Rev. 7, 11/2016
Kinetis K63F Sub-Family Data
Sheet
MK63FN1M0VLQ12
MK63FN1M0VMD12
120 MHz ARM® Cortex®-M4-based Microcontroller with FPU
The K63 product family members are optimized for cost-sensitive
applications requiring low-power, USB/Ethernet connectivity, up
to 256 KB of embedded SRAM and the need for extensive
tamper protection, such as Electronic Point of Sales. These
devices share the comprehensive enablement and scalability of
the Kinetis family.
This product offers:
144 LQFP
144 MAPBGA
20 x 20 x 1.6 mm Pitch 13 x 13 x 1.46 mm
• Run power consumption down to 250 μA/MHz. Static
0.5 mm
Pitch 1 mm
power consumption down to 5.8 μA with full state retention
and 5 μs wakeup. Lowest Static mode down to 339 nA
• DryIce Tamper Detection with active/passive pin,
temperature, clock, supply voltage monitoring
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO Vreg, with USB device crystal-less operation
• 10/100 Mbit/s Ethernet MAC with MII and RMII interfaces
Performance
• Up to 120 MHz ARM® Cortex®-M4 core with DSP
instructions and floating point unit
Memories and memory interfaces
• Up to 1 MB program flash memory and 256 KB RAM
• FlexBus external bus interface
System peripherals
• Multiple low-power modes, low-leakage wake-up unit
• Memory protection unit with multi-master protection
• 16-channel DMA controller
• External watchdog monitor and software watchdog
Security and integrity modules
• Hardware CRC module
• Tamper detect and secure storage
• Hardware random-number generator
• Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
• 128-bit unique identification (ID) number per chip
Analog modules
• Two 16-bit SAR ADCs
• Two 12-bit DACs
• Three analog comparators (CMP)
• Voltage reference
Communication interfaces
• Ethernet controller with MII and RMII interface
• USB full-/low-speed On-the-Go controller
• Controller Area Network (CAN) module
• Three SPI modules
• Three I2C modules. Support for up to 1 Mbit/s
• Six UART modules
• Secure Digital Host Controller (SDHC)
• I2S module
Timers
• Two 8-channel Flex-Timers (PWM/Motor control)
• Two 2-channel FlexTimers (PWM/Quad decoder)
• IEEE 1588 timers
• 32-bit PITs and 16-bit low-power timers
• Real-time clock
• Programmable delay block
Clocks
• 3 to 32 MHz and 32 kHz crystal oscillator
• PLL, FLL, and multiple internal oscillators
• 48 MHz Internal Reference Clock (IRC48M)
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash
SRAM (KB)
MK63FN1M0VLQ12
1 MB
256
100
MK63FN1M0VMD12
1 MB
256
95
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type
Description
Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K60PB 1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K63P144M120SF5RM 1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
K63P144M120SF51
Package
drawing
Package dimensions are provided in package drawings.
• LQFP 144-pin:
98ASS23177W1
• MAPBGA 144-pin:
98ASA00222D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Kinetis K63 Family
ARM ® Cortex™-M4
Core
System
Memories and Memory Interfaces
Clocks
Internal
and external
watchdogs
Program
flash
RAM
Phaselocked loop
Serial
programming
interface
External
bus
Frequencylocked loop
Debug
interfaces
DSP
Memory
protection
Interrupt
controller
Floatingpoint unit
DMA
Low/high
frequency
oscillators
Low-leakage
wakeup
Internal
reference
clocks
Security
Analog
Timers
CRC
16-bit ADC
x2
Timers
x2 (8ch)
x2 (2ch)
Random
number
generator
Analog
comparator
x3
Hardware
encryption
6-bit DAC
x3
Tamper
detect
12-bit DAC
x2
and Integrity
Voltage
reference
Programmable
delay block
Periodic
interrupt
timers
Low power
timer
Independent
real-time
clock
Communication Interfaces
2
I C
x3
I S
UART
x6
Secure
Digital
SPI
x3
USB OTG
LS/FS
CAN
x1
USB LS/FS
transceiver
IEEE 1588
Ethernet
USB charger
detect
IEEE 1588
Timers
2
Human-Machine
Interface (HMI)
GPIO
USB voltage
regulator
Figure 1. K63 block diagram
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1
Voltage and current operating requirements.....6
2.2.2
LVD and POR operating requirements............. 8
2.2.3
Voltage and current operating behaviors.......... 8
2.2.4
Power mode transition operating behaviors......10
2.2.5
Power consumption operating behaviors.......... 10
2.2.6
EMC radiated emissions operating behaviors...16
2.2.7
Designing with radiated emissions in mind....... 17
2.2.8
Capacitance attributes...................................... 17
2.3 Switching specifications...................................................17
2.3.1
Device clock specifications............................... 17
2.3.2
General switching specifications....................... 18
2.4 Thermal specifications..................................................... 19
2.4.1
Thermal operating requirements....................... 19
2.4.2
Thermal attributes............................................. 20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1
Debug trace timing specifications..................... 21
3.1.2
JTAG electricals................................................ 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1
MCG specifications........................................... 25
3.3.2
IRC48M specifications...................................... 27
3.3.3
Oscillator electrical specifications..................... 28
3.3.4
32 kHz oscillator electrical characteristics.........30
3.4 Memories and memory interfaces................................... 31
3.4.1
Flash (FTFE) electrical specifications............... 31
3.4.2
EzPort switching specifications......................... 33
3.4.3
Flexbus switching specifications....................... 34
3.5 Security and integrity modules........................................ 37
3.5.1
DryIce Tamper Electrical Specifications............37
3.6 Analog............................................................................. 38
3.6.1
ADC electrical specifications.............................38
4
NXP Semiconductors
4
5
6
7
8
3.6.2
CMP and 6-bit DAC electrical specifications.....42
3.6.3
12-bit DAC electrical characteristics................. 44
3.6.4
Voltage reference electrical specifications........ 47
3.7 Timers..............................................................................48
3.8 Communication interfaces............................................... 48
3.8.1
Ethernet switching specifications...................... 49
3.8.2
USB electrical specifications............................. 51
3.8.3
USB DCD electrical specifications.................... 51
3.8.4
USB VREG electrical specifications..................52
3.8.5
CAN switching specifications............................ 52
3.8.6
DSPI switching specifications (limited voltage
range)................................................................53
3.8.7
DSPI switching specifications (full voltage
range)................................................................54
3.8.8
Inter-Integrated Circuit Interface (I2C) timing....56
3.8.9
UART switching specifications.......................... 58
3.8.10 SDHC specifications......................................... 58
3.8.11 I2S switching specifications.............................. 59
Dimensions............................................................................. 65
4.1 Obtaining package dimensions....................................... 65
Pinout...................................................................................... 65
5.1 K63 Signal Multiplexing and Pin Assignments.................65
5.2 Unused analog interfaces................................................ 72
5.3 K63 Pinouts..................................................................... 72
Ordering parts......................................................................... 74
6.1 Determining valid orderable parts....................................74
Part identification.....................................................................75
7.1 Description.......................................................................75
7.2 Format............................................................................. 75
7.3 Fields............................................................................... 75
7.4 Example...........................................................................76
Terminology and guidelines.................................................... 76
8.1 Definitions........................................................................ 76
8.2 Examples......................................................................... 77
8.3 Typical-value conditions.................................................. 77
8.4 Relationship between ratings and operating
requirements....................................................................78
8.5 Guidelines for ratings and operating requirements..........78
9 Revision History...................................................................... 79
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
Solder temperature, leaded
—
245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
5
NXP Semiconductors
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
5.5
V
VAIO
Analog1,
–0.3
VDD + 0.3
V
ID
VDDA
RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VREGIN
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
General
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VBAT
VIH
VIL
RTC battery supply voltage
Notes
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICDIO
Digital pin (except Tamper pins) negative DC
injection current — single pin
1
• VIN < VSS-0.3V
IICAIO
IICcont
Analog2, EXTAL, and XTAL pin DC injection current
— single pin
3
mA
• VIN < VSS-0.3V (Negative current injection)
-5
—
• VIN > VDD+0.3V (Positive current injection)
—
+5
-25
—
—
+25
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
mA
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
4
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VINVAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative
injection currents.
4. Open drain outputs must be pulled to VDD.
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
7
NXP Semiconductors
General
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
Notes
Output high voltage — high drive strength
Table continues on the next page...
8
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA
VDD – 0.5
—
V
Notes
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
V
—
100
mA
VBAT – 0.5
—
V
VBAT – 0.5
—
V
VBAT – 0.5
—
V
VBAT – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
0.5
V
—
100
mA
—
0.5
V
—
0.5
V
—
0.5
V
—
0.5
V
Output low current total for Tamper pins
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
1
IIN
Input leakage current (per pin) at 25°C
—
0.025
μA
1
IIN_Tamper
Input leakage current (per Tamper pin) for full
temperature range
—
1
μA
IIN_Tamper
Input leakage current (per Tamper pin) at 25°C
—
0.025
μA
Hi-Z (off-state) leakage current (per pin)
—
0.25
μA
Hi-Z (off-state) leakage current (per Tamper pin)
—
0.25
μA
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOH_Tamper Output high voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
Output high voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
IOH_Tamper
Output high current total for Tamper pins
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
Output low current total for all ports
VOL_Tamper Output low voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
Output low voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
IOL_Tamper
IOZ
IOZ_Tamper
Table continues on the next page...
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
9
NXP Semiconductors
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
RPU
Internal pullup resistors (except Tamper pins)
20
50
kΩ
2
RPD
Internal pulldown resistors (except Tamper pins)
20
50
kΩ
3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
10
NXP Semiconductors
Min.
Max.
Unit
—
300
μs
—
156
μs
—
156
μs
—
78
μs
—
78
μs
—
4.8
μs
—
4.5
μs
—
4.5
μs
Notes
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
General
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard
deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN
Min.
2
—
31.1
36.65
mA
—
31
36.75
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
—
42.7
48.35
mA
• @ 25°C
—
40
41.60
mA
• @ 105°C
—
48.33
51.50
mA
• @ 1.8V
• @ 3.0V
IDD_WAIT
Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
—
17.9
—
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
6.9
—
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
—
1.0
—
mA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
—
1.7
—
mA
7
—
0.678
—
mA
8
• @ –40 to 25°C
—
0.49
1.24
mA
• @ 70°C
—
1.18
4.3
mA
• @ 105°C
—
3.0
12.5
mA
• @ –40 to 25°C
—
57
139.31
μA
• @ 70°C
—
291
679.33
μA
• @ 105°C
—
927.3
1869.85
μA
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
IDD_STOP
IDD_VLPS
IDD_LLS
Stop mode current at 3.0 V
Very-low-power stop mode current at 3.0 V
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
9
—
5.8
10.48
μA
—
26.7
47.99
μA
Table continues on the next page...
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
11
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
114.9
196.49
μA
• @ –40 to 25°C
—
4.4
5.54
μA
• @ 70°C
—
21
36.46
μA
• @ 105°C
—
90.2
150.17
μA
• @ –40 to 25°C
—
2.1
2.34
μA
• @ 70°C
—
6.84
10.36
μA
• @ 105°C
—
29.4
46.74
μA
• @ –40 to 25°C
—
0.817
0.86
μA
• @ 70°C
—
3.97
5.77
μA
• @ 105°C
—
21.3
33.99
μA
—
0.52
0.62
μA
—
3.67
5.7
μA
—
21.20
34.9
μA
—
0.339
0.412
μA
—
3.36
4.2
μA
—
20.3
29.9
μA
—
0.16
0.19
μA
—
0.55
0.72
μA
—
2.5
3.68
μA
—
0.18
0.21
μA
—
0.66
0.86
μA
—
2.92
4.30
μA
• @ 70°C
Notes
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current with RTC and 32 kHz disabled
• @ 1.8 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current when CPU is not accessing
RTC registers
12
NXP Semiconductors
10
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 6. Power consumption operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
• @ –40 to 25°C
—
0.59
0.70
μA
• @ 70°C
—
1.0
1.30
μA
• @ 105°C
—
3.0
4.42
μA
• @ –40 to 25°C
—
0.71
0.84
μA
• @ 70°C
—
1.22
1.59
μA
• @ 105°C
—
3.5
5.15
μA
Notes
• @ 1.8 V
• @ 3.0 V
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 Mhz FlexBus clock, and 20 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus clock, 30 MHz Flexbus clock, and 20 MHz flash clock. MCG configured
for PEE mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Data reflects devices with 256 KB of RAM.
10. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
440
490
540
560
570
580
VLLS1
Table continues on the next page...
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
13
NXP Semiconductors
General
Table 7. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
VLLS3
440
490
540
560
570
580
LLS
490
490
540
560
570
680
VLPS
510
560
560
560
610
680
STOP
510
560
560
560
610
680
48 Mhz internal reference clock
350
350
350
350
350
350
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
22
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432
357
388
475
532
810
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
66
66
66
66
66
66
µA
OSCERCLK (4 MHz external crystal)
214
237
246
254
260
268
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42
42
42
42
42
42
µA
I48MIRC
MCGIRCLK (4 MHz internal reference
clock)
2.2.5.1
nA
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
14
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Run Mode Current Consumption vs Core Frequency
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
40.00E-03
35.00E-03
Current Consumption on VDD (A)
30.00E-03
25.00E-03
All Peripheral Clk Gates
20.00E-03
ALLOFF
ALLON
15.00E-03
10.00E-03
5.00E-03
000.00E+00
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-2
'1-2-3
'1-2-4
'1-2-5
1
2
4
6.25
12.5
25
50
75
100
120
Clk Ratio
Core-BusFlaxbus-Flash
Core Freq (MHz)
Figure 3. Run mode supply current vs. core frequency
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
15
NXP Semiconductors
General
Very Low Power Run (VLPR) Current vs Core Frequency
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
1.40E-03
1.20E-03
Current Consumption on VDD (A)
1.00E-03
800.00E-06
All Peripheral Clk Gates
ALLOFF
ALLON
600.00E-06
400.00E-06
200.00E-06
000.00E+00
'1-1-2
'1-1-1
'1-2-4
1
'1-1-4
'1-1-2
'1-2-4
2
'1-1-4
Clk Ratio
Core-Bus-Flash
Core Freq (MHz)
4
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
144 LQFP
VRE1
Radiated emissions voltage, band 1
0.15–50
16
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
22
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
21
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
16
dBμV
IEC level
0.15–1000
L
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
16
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
120
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Notes
Normal run mode
fSYS
fENET
System and core clock when ethernet in operation
• 10 Mbps
• 100 Mbps
fBUS
FB_CLK
fFLASH
MHz
5
—
50
—
Bus clock
—
60
MHz
FlexBus clock
—
50
MHz
Flash clock
—
25
MHz
Table continues on the next page...
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
17
NXP Semiconductors
General
Table 10. Device clock specifications (continued)
Symbol
Description
fLPTMR
LPTMR clock
VLPR
Min.
Max.
Unit
—
25
MHz
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
0.8
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
fLPTMR_ERCLK LPTMR external reference clock
—
16
MHz
fFlexCAN_ERCLK FlexCAN external reference clock
—
8
MHz
FB_CLK
fLPTMR_pin
Notes
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, timers, and I2C signals.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
2
—
Bus clock
cycles
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength) - 3 V
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
8
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
—
18
ns
• Slew enabled
Table continues on the next page...
18
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 11. General switching specifications (continued)
Symbol
Description
• 1.71 ≤ VDD ≤ 2.7V
Min.
Max.
Unit
—
12
ns
Notes
• 2.7 ≤ VDD ≤ 3.6V
Port rise and fall time (high drive strength) - 5 V
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
6
ns
• 2.7 ≤ VDD ≤ 3.6V
—
4
ns
• 1.71 ≤ VDD ≤ 2.7V
—
24
ns
• 2.7 ≤ VDD ≤ 3.6V
—
14
ns
• Slew enabled
Port rise and fall time (low drive strength) - 3 V
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
24
ns
• 2.7 ≤ VDD ≤ 3.6V
—
16
ns
• Slew enabled
Port rise and fall time (low drive strength) - 5 V
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
17
ns
• 2.7 ≤ VDD ≤ 3.6V
—
10
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
20
ns
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 25 pF load
5. 15 pF load
2.4 Thermal specifications
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
19
NXP Semiconductors
General
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature1
–40
105
°C
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 13. Thermal attributes
Board type
Symbol
Description
144 LQFP
144 MAPBGA
Unit
Notes
Single-layer (1s) RθJA
Thermal
51
resistance,
junction to
ambient (natural
convection)
38.1
°C/W
1
Four-layer
(2s2p)
Thermal
43
resistance,
junction to
ambient (natural
convection)
21.6
°C/W
1
Single-layer (1s) RθJMA
Thermal
42
resistance,
junction to
ambient (200 ft./
min. air speed)
30.8
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal
36
resistance,
junction to
ambient (200 ft./
min. air speed)
18
°C/W
1
—
RθJB
Thermal
resistance,
junction to
board
16.5
°C/W
2
—
RθJC
Thermal
11
resistance,
junction to case
8.9
°C/W
3
—
ΨJT
Thermal
2
characterization
parameter,
junction to
package top
0.9
°C/W
4
RθJA
20
NXP Semiconductors
30
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 13. Thermal attributes
Board type
Symbol
Description
144 LQFP
144 MAPBGA
Unit
Notes
outside center
(natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 14. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
1.5
—
ns
Th
Data hold
1
—
ns
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
21
NXP Semiconductors
Peripheral operating requirements and behaviors
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Ts
Th
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
3.1.2 JTAG electricals
Table 15. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.6
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
22
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 15. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Table 16. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
2.9
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
23
NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
24
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 17. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Iints
Internal reference (slow clock) current
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
± 0.5
±2
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
Internal reference (fast clock) current
—
25
—
µA
Iintf
1
,2
1
Table continues on the next page...
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
25
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
120
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
8
8
9
• fvco = 48 MHz
—
120
—
ps
• fvco = 120 MHz
—
80
—
ps
PLL accumulated jitter over 1µs (RMS)
9
Table continues on the next page...
26
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• fvco = 48 MHz
—
1350
—
ps
• fvco = 120 MHz
—
600
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
10-6
—
150 ×
+ 1075(1/
fpll_ref)
Notes
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
45
NXP Semiconductors
Peripheral operating requirements and behaviors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 19. Typical INL error vs. digital code
46
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
25
-40
85
105
125
Temperature °C
Figure 20. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 35. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
—
Operating temperature
range of the device
°C
—
100
nF
1, 2
TA
Temperature
CL
Output load capacitance
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
47
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 36. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature= 25 °C
1.192
1.195
1.198
V
1
Vout
Voltage reference output with user trim at
nominal VDDA and temperature= 25 °C
1.1945
1.195
1.1955
V
1
Vstep
Voltage reference trim step
—
0.5
—
mV
1
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
2
15
mV
1
Ibg
Bandgap only current
—
60
80
µA
1
Ilp
Low-power buffer current
—
180
360
uA
1
Ihp
High-power buffer current
—
480
960
mA
1
µV
1, 2
—
ΔVLOAD
Load regulation
• current = ± 1.0 mA
Tstup
Buffer startup time
—
200
—
—
—
100
µs
35
ms
2
mV
Tchop_osc_st Internal bandgap start-up delay with chop
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
0.5
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 37. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
—
Table 38. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
Notes
1.173
1.225
V
—
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
48
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
3.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
3.8.1.1
MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range
of transceiver devices.
Table 39. MII signal switching specifications
Symbol
—
MII1
Description
RXCLK frequency
RXCLK pulse width high
Min.
Max.
Unit
—
25
MHz
35%
65%
RXCLK
period
MII2
RXCLK pulse width low
35%
65%
RXCLK
period
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
5
—
ns
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
TXCLK frequency
—
25
MHz
35%
65%
TXCLK
—
MII5
TXCLK pulse width high
period
MII6
TXCLK pulse width low
35%
65%
TXCLK
period
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
2
—
ns
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
MII6
MII5
TXCLK (input)
MII8
MII7
TXD[n:0]
Valid data
TXEN
Valid data
TXER
Valid data
Figure 21. RMII/MII transmit signal timing diagram
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
49
NXP Semiconductors
Peripheral operating requirements and behaviors
MII2
MII1
MII3
MII4
RXCLK (input)
RXD[n:0]
Valid data
RXDV
Valid data
RXER
Valid data
Figure 22. RMII/MII receive signal timing diagram
3.8.1.2
RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range
of transceiver devices.
Table 40. RMII signal switching specifications
Num
—
Description
EXTAL frequency (RMII input clock RMII_CLK)
Min.
Max.
Unit
—
50
MHz
RMII1
RMII_CLK pulse width high
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
4
—
ns
RMII4
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
2
—
ns
RMII7
RMII_CLK to TXD[1:0], TXEN invalid
4
—
ns
RMII8
RMII_CLK to TXD[1:0], TXEN valid
—
15
ns
3.8.1.3
MDIO serial management timing specifications
Table 41. MDIO serial management channel signal timing
Num
Characteristic
Symbol
Min
Max
Unit
E10
MDC cycle time
tMDC
400
—
ns
E11
MDC pulse width
40
60
% tMDC
E12
MDC to MDIO output valid
—
375
ns
E13
MDC to MDIO output invalid
25
—
ns
E14
MDIO input to MDC setup
10
—
ns
E15
MDIO input to MDC hold
0
—
ns
50
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
E10
E11
MDC (Output)
E11
E12
E13
MDIO (Output)
Valid Data
E14
MDIO (Input)
E15
Valid Data
Figure 23. MDIO serial management channel timing diagram
3.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-todate standards, visit usb.org.
NOTE
The MCGPLLCLK meets the USB jitter and signaling rate
specifications for certification with the use of an external
clock/crystal for both Device and Host modes.
The MCGFLLCLK does not meet the USB jitter or
signaling rate specifications for certification.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the
USB clock recovery mode is enabled. It does not meet the
USB signaling rate specifications for certification in Host
mode operation.
3.8.3 USB DCD electrical specifications
Table 42. USB0 DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
0.5
—
0.7
V
Threshold voltage for logic high
0.8
—
2.0
V
VLGC
Table continues on the next page...
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51
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 42. USB0 DCD electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK
USB_DM sink current
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
0.33
0.4
V
3.8.4 USB VREG electrical specifications
Table 43. USB VREG electrical specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
VREGIN
Input supply voltage
2.7
—
5.5
V
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
125
186
μA
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
IDDoff
Quiescent current — Shutdown mode
—
650
—
nA
—
—
4
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
VReg33out
Regulator output voltage — Input supply
(VREGIN) > 3.6 V
3
3.3
3.6
V
2.1
2.8
3.6
V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
• Run mode
• Standby mode
VReg33out
Notes
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
3.8.5 CAN switching specifications
See General switching specifications.
52
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
3.8.6 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 44. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
30
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS7
DS1
DS2
DS4
DS8
First data
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 24. DSPI classic SPI timing — master mode
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
53
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 45. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
151
MHz
4 x tBUS
—
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,
when bus clock is 60MHz, SPI clock should not be greater than 10MHz
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DSPI_SOUT
First data
DS13
DSPI_SIN
DS12
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 25. DSPI classic SPI timing — slave mode
54
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
3.8.7 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 46. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
15
MHz
4 x tBUS
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
21
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS4
DS8
First data
DSPI_SOUT
DS1
DS2
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 26. DSPI classic SPI timing — master mode
Table 47. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
1.71
3.6
V
Table continues on the next page...
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55
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 47. Slave mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
—
7.5
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
23.5
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
4
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
21
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 27. DSPI classic SPI timing — slave mode
3.8.8 Inter-Integrated Circuit Interface (I2C) timing
Table 48. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
Unit
SCL Clock Frequency
fSCL
0
100
0
4001
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
µs
LOW period of the SCL clock
tLOW
4.7
—
1.25
—
µs
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
µs
Data hold time for I2C bus devices
tHD; DAT
02
3.453
04
0.92
µs
Table continues on the next page...
56
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Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 48. I 2C timing (continued)
Characteristic
Symbol
Standard Mode
Minimum
Data set-up time
tSU; DAT
Rise time of SDA and SCL signals
tr
Fall time of SDA and SCL signals
tf
2505
—
Fast Mode
Maximum
Minimum
Maximum
—
1003, 6
1000
Unit
—
ns
7
300
ns
6
20 +0.1Cb
—
300
20 +0.1Cb
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
Table 49. I 2C 1 Mbps timing
Characteristic
Symbol
Minimum
Maximum
Unit
MHz
SCL Clock Frequency
fSCL
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
µs
LOW period of the SCL clock
tLOW
0.5
—
µs
HIGH period of the SCL clock
tHIGH
0.26
—
µs
Set-up time for a repeated START condition
tSU; STA
0.26
—
µs
Data hold time for I2C bus devices
tHD; DAT
0
—
µs
Data set-up time
tSU; DAT
50
Rise time of SDA and SCL signals
tr
—
ns
,2
120
ns
2
120
ns
20 +0.1Cb
Fall time of SDA and SCL signals
tf
20 +0.1Cb
Set-up time for STOP condition
tSU; STO
0.26
—
µs
Bus free time between STOP and START
condition
tBUF
0.5
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins
across the full voltage range.
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
57
NXP Semiconductors
Peripheral operating requirements and behaviors
2. Cb = total capacitance of the one bus line in pF.
SDA
tf
tSU; DAT
tr
tLOW
tf
tHD; STA
tr
tSP
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
tSU; STO
SR
P
S
Figure 28. Timing definition for devices on the I2C bus
3.8.9 UART switching specifications
See General switching specifications.
3.8.10 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 50. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
8.3
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5.5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
58
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 29. SDHC timing
3.8.11 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =
0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or
the frame sync (I2S_FS) shown in the figures below.
Table 51. I2S master mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
S4
I2S_BCLK pulse width high/low
S5
80
—
ns
45%
55%
BCLK period
I2S_BCLK to I2S_FS output valid
—
15
ns
S6
I2S_BCLK to I2S_FS output invalid
0
—
ns
S7
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
17
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
59
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S6
S5
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 30. I2S timing — master mode
Table 52. I2S slave mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_BCLK cycle time (input)
80
—
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
5
—
ns
S14
I2S_FS input hold after I2S_BCLK
2
—
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
—
19.5
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_BCLK
5
—
ns
S18
I2S_RXD hold after I2S_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1
21
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
60
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
I2S_FS (input)
S14
S15
S19
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 31. I2S timing — slave modes
3.8.11.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 53. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
22.5
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
61
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 32. I2S/SAI timing — master modes
Table 54. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
7
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
25.5
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 3
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
5.8
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
62
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 33. I2S/SAI timing — slave modes
3.8.11.2
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 55. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
63
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 34. I2S/SAI timing — master modes
Table 56. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
11
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
11
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
64
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Dimensions
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 35. I2S/SAI timing — slave modes
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
144-pin LQFP
98ASS23177W
144-pin MAPBGA
98ASA00222D
5 Pinout
5.1 K63 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
65
NXP Semiconductors
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
—
M3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
—
L3
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
—
L4
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
—
J4
TAMPER3
TAMPER3
TAMPER3
—
H4
TAMPER4
TAMPER4
TAMPER4
—
M4
TAMPER5
TAMPER5
TAMPER5
—
M5
NC
NC
NC
—
A10
NC
NC
NC
—
B10
NC
NC
NC
—
C10 NC
NC
NC
1
D3
PTE0
ADC1_SE4a
ADC1_SE4a
PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
TRACE_
CLKOUT
I2C1_SDA
RTC_
CLKOUT
2
D2
PTE1/
LLWU_P0
ADC1_SE5a
ADC1_SE5a
PTE1/
LLWU_P0
SPI1_SOUT
UART1_RX
SDHC0_D0
TRACE_D3
I2C1_SCL
SPI1_SIN
3
D1
PTE2/
LLWU_P1
ADC0_DP2/
ADC1_SE6a
ADC0_DP2/
ADC1_SE6a
PTE2/
LLWU_P1
SPI1_SCK
UART1_
CTS_b
SDHC0_
DCLK
TRACE_D2
4
E4
PTE3
ADC0_DM2/
ADC1_SE7a
ADC0_DM2/
ADC1_SE7a
PTE3
SPI1_SIN
UART1_
RTS_b
SDHC0_
CMD
TRACE_D1
5
E5
VDD
VDD
VDD
6
F6
VSS
VSS
VSS
7
E3
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
SDHC0_D3
TRACE_D0
8
E2
PTE5
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
FTM3_CH0
9
E1
PTE6
DISABLED
PTE6
SPI1_PCS3
UART3_
CTS_b
I2S0_MCLK
FTM3_CH1
10
F4
PTE7
DISABLED
PTE7
UART3_
RTS_b
I2S0_RXD0
FTM3_CH2
11
F3
PTE8
DISABLED
PTE8
I2S0_RXD1
UART5_TX
I2S0_RX_FS
FTM3_CH3
12
F2
PTE9
DISABLED
PTE9
I2S0_TXD1
UART5_RX
I2S0_RX_
BCLK
FTM3_CH4
13
F1
PTE10
DISABLED
PTE10
UART5_
CTS_b
I2S0_TXD0
FTM3_CH5
14
G4
PTE11
DISABLED
PTE11
UART5_
RTS_b
I2S0_TX_FS
FTM3_CH6
15
G3
PTE12
DISABLED
PTE12
I2S0_TX_
BCLK
FTM3_CH7
66
NXP Semiconductors
EzPort
SPI1_SOUT
USB_SOF_
OUT
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
16
E6
VDD
VDD
VDD
17
F7
VSS
VSS
VSS
18
H3
VSS
VSS
VSS
19
H1
USB0_DP
USB0_DP
USB0_DP
20
H2
USB0_DM
USB0_DM
USB0_DM
21
G1
VOUT33
VOUT33
VOUT33
22
G2
VREGIN
VREGIN
VREGIN
23
J1
ADC0_DP1
ADC0_DP1
ADC0_DP1
24
J2
ADC0_DM1
ADC0_DM1
ADC0_DM1
25
K1
ADC1_DP1
ADC1_DP1
ADC1_DP1
26
K2
ADC1_DM1
ADC1_DM1
ADC1_DM1
27
L1
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
28
L2
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
29
M1
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
30
M2
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
31
H5
VDDA
VDDA
VDDA
32
G5
VREFH
VREFH
VREFH
33
G6
VREFL
VREFL
VREFL
34
H6
VSSA
VSSA
VSSA
35
K3
ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_SE22 ADC0_SE22 ADC0_SE22
36
J3
ADC0_SE16/ ADC0_SE16/ ADC0_SE16/
CMP1_IN2/ CMP1_IN2/ CMP1_IN2/
ADC0_SE21 ADC0_SE21 ADC0_SE21
37
L5
TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
38
K5
TAMPER1
TAMPER1
TAMPER1
39
K4
TAMPER2
TAMPER2
TAMPER2
40
M7
XTAL32
XTAL32
XTAL32
41
M6
EXTAL32
EXTAL32
EXTAL32
42
L6
VBAT
VBAT
VBAT
43
—
VDD
VDD
VDD
44
—
VSS
VSS
VSS
45
—
PTE24
ADC0_SE17
ADC0_SE17
PTE24
UART4_TX
I2C0_SCL
EWM_OUT_
b
46
—
PTE25
ADC0_SE18
ADC0_SE18
PTE25
UART4_RX
I2C0_SDA
EWM_IN
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
EzPort
67
NXP Semiconductors
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
EzPort
47
—
PTE26
DISABLED
PTE26
ENET_1588_ UART4_
CLKIN
CTS_b
48
—
PTE27
DISABLED
PTE27
UART4_
RTS_b
49
—
PTE28
DISABLED
PTE28
50
J5
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
JTAG_TCLK/ EZP_CLK
SWD_CLK
51
J6
PTA1
JTAG_TDI/
EZP_DI
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
52
K6
PTA2
JTAG_TDO/
TRACE_
SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
TRACE_
SWO
EZP_DO
53
K7
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
JTAG_TMS/
SWD_DIO
54
L7
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1
NMI_b
55
M8
PTA5
DISABLED
PTA5
56
E7
VDD
VDD
VDD
57
G7
VSS
VSS
VSS
58
J7
PTA6
DISABLED
59
J8
PTA7
ADC0_SE10
60
K8
PTA8
ADC0_SE11
61
L8
PTA9
62
M9
63
USB_CLKIN
RTC_
CLKOUT
ALT7
FTM0_CH2
RMII0_
RXER/
MII0_RXER
CMP2_OUT
I2S0_TX_
BCLK
USB_CLKIN
JTAG_
TRST_b
PTA6
FTM0_CH3
TRACE_
CLKOUT
ADC0_SE10
PTA7
FTM0_CH4
TRACE_D3
ADC0_SE11
PTA8
FTM1_CH0
DISABLED
PTA9
FTM1_CH1
PTA10
DISABLED
PTA10
L9
PTA11
DISABLED
PTA11
64
K9
PTA12
CMP2_IN0
CMP2_IN0
PTA12
65
J9
PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
66
L10
PTA14
DISABLED
68
NXP Semiconductors
FTM1_QD_
PHA
TRACE_D2
MII0_RXD3
FTM1_QD_
PHB
TRACE_D1
FTM2_CH0
MII0_RXD2
FTM2_QD_
PHA
TRACE_D0
FTM2_CH1
MII0_RXCLK I2C2_SDA
FTM2_QD_
PHB
CAN0_TX
FTM1_CH0
RMII0_
RXD1/
MII0_RXD1
I2C2_SCL
I2S0_TXD0
PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
RMII0_
RXD0/
MII0_RXD0
I2C2_SDA
I2S0_TX_FS FTM1_QD_
PHB
PTA14
SPI0_PCS0
UART0_TX
RMII0_CRS_ I2C2_SCL
DV/
MII0_RXDV
I2S0_RX_
BCLK
EZP_CS_b
FTM1_QD_
PHA
I2S0_TXD1
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
67
L11
PTA15
DISABLED
PTA15
SPI0_SCK
UART0_RX
RMII0_
TXEN/
MII0_TXEN
I2S0_RXD0
68
K10
PTA16
DISABLED
PTA16
SPI0_SOUT
UART0_
CTS_b/
UART0_
COL_b
RMII0_TXD0/
MII0_TXD0
I2S0_RX_FS I2S0_RXD1
69
K11
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_
RTS_b
RMII0_TXD1/
MII0_TXD1
I2S0_MCLK
70
E8
VDD
VDD
VDD
71
G8
VSS
VSS
VSS
72
M12 PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
73
M11 PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
LPTMR0_
ALT1
74
L12
RESET_b
RESET_b
RESET_b
75
K12
PTA24
DISABLED
PTA24
MII0_TXD2
FB_A29
76
J12
PTA25
DISABLED
PTA25
MII0_TXCLK
FB_A28
77
J11
PTA26
DISABLED
PTA26
MII0_TXD3
FB_A27
78
J10
PTA27
DISABLED
PTA27
MII0_CRS
FB_A26
79
H12 PTA28
DISABLED
PTA28
MII0_TXER
FB_A25
80
H11 PTA29
DISABLED
PTA29
MII0_COL
FB_A24
81
H10 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
RMII0_MDIO/
MII0_MDIO
FTM1_QD_
PHA
82
H9
PTB1
ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1
I2C0_SDA
FTM1_CH1
RMII0_MDC/
MII0_MDC
FTM1_QD_
PHB
83
G12 PTB2
ADC0_SE12
ADC0_SE12
PTB2
I2C0_SCL
UART0_
RTS_b
ENET0_
1588_TMR0
FTM0_FLT3
84
G11 PTB3
ADC0_SE13
ADC0_SE13
PTB3
I2C0_SDA
UART0_
CTS_b/
UART0_
COL_b
ENET0_
1588_TMR1
FTM0_FLT0
85
G10 PTB4
ADC1_SE10
ADC1_SE10
PTB4
ENET0_
1588_TMR2
FTM1_FLT0
86
G9
PTB5
ADC1_SE11
ADC1_SE11
PTB5
ENET0_
1588_TMR3
FTM2_FLT0
87
F12
PTB6
ADC1_SE12
ADC1_SE12
PTB6
FB_AD23
88
F11
PTB7
ADC1_SE13
ADC1_SE13
PTB7
FB_AD22
89
F10
PTB8
DISABLED
PTB8
90
F9
PTB9
DISABLED
PTB9
91
E12
PTB10
ADC1_SE14
ADC1_SE14
92
E11
PTB11
ADC1_SE15
ADC1_SE15
93
H7
VSS
VSS
VSS
UART3_
RTS_b
FB_AD21
SPI1_PCS1
UART3_
CTS_b
FB_AD20
PTB10
SPI1_PCS0
UART3_RX
FB_AD19
FTM0_FLT1
PTB11
SPI1_SCK
UART3_TX
FB_AD18
FTM0_FLT2
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
EzPort
69
NXP Semiconductors
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
94
F5
VDD
VDD
95
E10
PTB16
DISABLED
PTB16
SPI1_SOUT
UART0_RX
FTM_CLKIN0 FB_AD17
EWM_IN
96
E9
PTB17
DISABLED
PTB17
SPI1_SIN
UART0_TX
FTM_CLKIN1 FB_AD16
EWM_OUT_
b
97
D12 PTB18
DISABLED
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_
BCLK
FB_AD15
FTM2_QD_
PHA
98
D11 PTB19
DISABLED
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS FB_OE_b
FTM2_QD_
PHB
99
D10 PTB20
DISABLED
PTB20
SPI2_PCS0
FB_AD31
CMP0_OUT
100
D9
PTB21
DISABLED
PTB21
SPI2_SCK
FB_AD30
CMP1_OUT
101
C12 PTB22
DISABLED
PTB22
SPI2_SOUT
FB_AD29
CMP2_OUT
102
C11 PTB23
DISABLED
PTB23
SPI2_SIN
SPI0_PCS5
103
B12
PTC0
ADC0_SE14
ADC0_SE14
PTC0
SPI0_PCS4
PDB0_
EXTRG
USB_SOF_
OUT
FB_AD14
I2S0_TXD1
104
B11
PTC1/
LLWU_P6
ADC0_SE15
ADC0_SE15
PTC1/
LLWU_P6
SPI0_PCS3
UART1_
RTS_b
FTM0_CH0
FB_AD13
I2S0_TXD0
105
A12
PTC2
ADC0_SE4b/ ADC0_SE4b/ PTC2
CMP1_IN0
CMP1_IN0
SPI0_PCS2
UART1_
CTS_b
FTM0_CH1
FB_AD12
I2S0_TX_FS
106
A11
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
107
H8
VSS
VSS
VSS
108
—
VDD
VDD
VDD
109
A9
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
FB_AD11
CMP1_OUT
110
D8
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
I2S0_RXD0
FB_AD10
CMP0_OUT
111
C8
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9
I2S0_MCLK
112
B8
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB_SOF_
OUT
I2S0_RX_FS FB_AD8
113
A8
PTC8
ADC1_SE4b/ ADC1_SE4b/ PTC8
CMP0_IN2
CMP0_IN2
FTM3_CH4
I2S0_MCLK
FB_AD7
114
D7
PTC9
ADC1_SE5b/ ADC1_SE5b/ PTC9
CMP0_IN3
CMP0_IN3
FTM3_CH5
I2S0_RX_
BCLK
FB_AD6
115
C7
PTC10
ADC1_SE6b
ADC1_SE6b
PTC10
I2C1_SCL
FTM3_CH6
I2S0_RX_FS FB_AD5
116
B7
PTC11/
LLWU_P11
ADC1_SE7b
ADC1_SE7b
PTC11/
LLWU_P11
I2C1_SDA
FTM3_CH7
I2S0_RXD1
117
A7
PTC12
DISABLED
PTC12
UART4_
RTS_b
FB_AD27
118
D6
PTC13
DISABLED
PTC13
UART4_
CTS_b
FB_AD26
119
C6
PTC14
DISABLED
PTC14
UART4_RX
FB_AD25
120
B6
PTC15
DISABLED
PTC15
UART4_TX
FB_AD24
121
—
VSS
VSS
70
NXP Semiconductors
ALT7
EzPort
VDD
FB_AD28
FTM0_CH2
FTM2_FLT0
FB_RW_b
FTM3_FLT0
VSS
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Pinout
144 144
LQFP MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
122
—
VDD
VDD
123
A6
PTC16
DISABLED
PTC16
UART3_RX
ENET0_
1588_TMR0
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_
8_b
124
D5
PTC17
DISABLED
PTC17
UART3_TX
ENET0_
1588_TMR1
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_0_
b
125
C5
PTC18
DISABLED
PTC18
UART3_
RTS_b
ENET0_
1588_TMR2
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b
126
B5
PTC19
DISABLED
PTC19
UART3_
CTS_b
ENET0_
1588_TMR3
FB_CS3_b/ FB_TA_b
FB_BE7_0_
BLS31_24_b
127
A5
PTD0/
LLWU_P12
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
UART2_
RTS_b
FTM3_CH0
FB_ALE/
FB_CS1_b/
FB_TS_b
128
D4
PTD1
ADC0_SE5b
PTD1
SPI0_SCK
UART2_
CTS_b
FTM3_CH1
FB_CS0_b
129
C4
PTD2/
LLWU_P13
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
FTM3_CH2
FB_AD4
I2C0_SCL
130
B4
PTD3
DISABLED
PTD3
SPI0_SIN
UART2_TX
FTM3_CH3
FB_AD3
I2C0_SDA
131
A4
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
FTM0_CH4
FB_AD2
EWM_IN
SPI1_PCS0
132
A3
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
FB_AD1
EWM_OUT_
b
SPI1_SCK
133
A2
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FB_AD0
FTM0_FLT0
SPI1_SOUT
134
M10 VSS
VSS
VSS
135
F8
VDD
VDD
VDD
136
A1
PTD7
DISABLED
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
FTM0_FLT1
SPI1_SIN
137
C9
PTD8
DISABLED
PTD8
I2C0_SCL
UART5_RX
FB_A16
138
B9
PTD9
DISABLED
PTD9
I2C0_SDA
UART5_TX
FB_A17
139
B3
PTD10
DISABLED
PTD10
UART5_
RTS_b
FB_A18
140
B2
PTD11
DISABLED
PTD11
SPI2_PCS0
UART5_
CTS_b
SDHC0_
CLKIN
FB_A19
141
B1
PTD12
DISABLED
PTD12
SPI2_SCK
FTM3_FLT0
SDHC0_D4
FB_A20
142
C3
PTD13
DISABLED
PTD13
SPI2_SOUT
SDHC0_D5
FB_A21
143
C2
PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6
FB_A22
EzPort
VDD
ADC0_SE5b
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
71
NXP Semiconductors
Pinout
144 144
LQFP MAP
BGA
144
C1
Pin Name
PTD15
Default
DISABLED
ALT0
ALT1
PTD15
ALT2
ALT3
SPI2_PCS1
ALT4
ALT5
SDHC0_D7
ALT6
ALT7
EzPort
FB_A23
5.2 Unused analog interfaces
Table 57. Unused analog interfaces
Module name
Pins
Recommendation if unused
ADC
ADC0_DP1, ADC0_DM1, ADC1_DP1,
ADC1_DM1, ADC0_DP0/ADC1_DP3,
ADC0_DM0/ADC1_DM3, ADC1_DP0/
ADC0_DP3, ADC1_DM0/ADC0_DM3,
ADC1_SE16/ADC0_SE22,
ADC0_SE16/ADC0_SE21,
ADC1_SE18
Ground
DAC 1
DAC0_OUT, DAC1_OUT
Float
USB
VREGIN, USB0_GND,
USB0_DM, USB0_DP
VOUT332
Connect VREGIN and VOUT33
together and tie to ground through a 10
kΩ resistor. Do not tie directly to
ground, as this causes a latch-up risk.
Float
1. Unused DAC signals do not apply to all parts. See the Pinout section for details.
2. USB0_VBUS and USB0_GND are board level signals
5.3 K63 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
72
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
111
110
109
PTC13
PTC8
PTC14
118
112
PTC15
119
PTC9
VSS
120
113
VDD
121
PTC10
PTC16
122
115
PTC17
123
114
PTC18
124
PTC12
PTC19
125
PTC11/LLWU_P11
PTD0/LLWU_P12
126
116
PTD1
127
117
PTD2/LLWU_P13
VSS
134
128
VDD
135
PTD3
PTD7
136
129
PTD8
137
PTD4/LLWU_P14
PTD9
138
131
PTD10
139
130
PTD11
140
PTD6/LLWU_P15
PTD12
141
PTD5
PTD13
142
132
PTD14
143
133
PTD15
144
Pinout
PTE0
1
108
VDD
PTE1/LLWU_P0
2
107
VSS
PTE2/LLWU_P1
3
106
PTC3/LLWU_P7
PTE3
4
105
PTC2
VDD
5
104
PTC1/LLWU_P6
VSS
6
103
PTC0
PTE4/LLWU_P2
7
102
PTB23
PTE5
8
101
PTB22
PTE6
9
100
PTB21
PTE7
10
99
PTB20
PTE8
11
98
PTB19
PTE9
12
97
PTB18
PTE10
13
96
PTB17
PTE11
14
95
PTB16
PTE12
15
94
VDD
VDD
16
93
VSS
VSS
17
92
PTB11
VSS
18
91
PTB10
USB0_DP
19
90
PTB9
USB0_DM
20
89
PTB8
VOUT33
21
88
PTB7
VREGIN
22
87
PTB6
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VDD
VSS
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
PTA13/LLWU_P4
PTA14
PTA15
PTA16
PTA17
VDD
VSS
PTA18
PTA19
55
RESET_b
73
PTA5
74
36
54
35
PTA4/LLWU_P3
ADC1_SE16/CMP2_IN2/ADC0_SE22
ADC0_SE16/CMP1_IN2/ADC0_SE21
53
PTA24
PTA3
75
52
34
PTA2
PTA25
VSSA
51
PTA26
76
50
77
33
PTA1
32
VREFL
PTA0
VREFH
49
PTA27
PTE28
78
48
31
PTE27
PTA28
VDDA
47
79
PTE26
30
46
PTA29
ADC1_DM0/ADC0_DM3
PTE25
80
45
29
PTE24
PTB0/LLWU_P5
ADC1_DP0/ADC0_DP3
44
81
VSS
28
43
PTB1
ADC0_DM0/ADC1_DM3
VDD
82
42
27
VBAT
PTB2
ADC0_DP0/ADC1_DP3
41
83
EXTAL32
26
40
PTB3
ADC1_DM1
XTAL32
84
39
25
TAMPER2
PTB4
ADC1_DP1
38
PTB5
85
37
86
24
TAMPER1
23
TAMPER0/RTC_WAKEUP_B
ADC0_DP1
ADC0_DM1
Figure 36. K63 144 LQFP Pinout Diagram
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
73
NXP Semiconductors
Ordering parts
1
2
3
4
5
6
7
8
9
10
11
12
A
PTD7
PTD6/
LLWU_P15
PTD5
PTD4/
LLWU_P14
PTD0/
LLWU_P12
PTC16
PTC12
PTC8
PTC4/
LLWU_P8
NC
PTC3/
LLWU_P7
PTC2
A
B
PTD12
PTD11
PTD10
PTD3
PTC19
PTC15
PTC11/
LLWU_P11
PTC7
PTD9
NC
PTC1/
LLWU_P6
PTC0
B
C
PTD15
PTD14
PTD13
PTD2/
LLWU_P13
PTC18
PTC14
PTC10
PTC6/
LLWU_P10
PTD8
NC
PTB23
PTB22
C
D
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTE0
PTD1
PTC17
PTC13
PTC9
PTC5/
LLWU_P9
PTB21
PTB20
PTB19
PTB18
D
E
PTE6
PTE5
PTE4/
LLWU_P2
PTE3
VDD
VDD
VDD
VDD
PTB17
PTB16
PTB11
PTB10
E
F
PTE10
PTE9
PTE8
PTE7
VDD
VSS
VSS
VDD
PTB9
PTB8
PTB7
PTB6
F
G
VOUT33
VREGIN
PTE12
PTE11
VREFH
VREFL
VSS
VSS
PTB5
PTB4
PTB3
PTB2
G
H
USB0_DP
USB0_DM
VSS
TAMPER4
VDDA
VSSA
VSS
VSS
PTB1
PTB0/
LLWU_P5
PTA29
PTA28
H
J
ADC0_DP1
ADC0_DM1
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
TAMPER3
PTA0
PTA1
PTA6
PTA7
PTA13/
LLWU_P4
PTA27
PTA26
PTA25
J
K
ADC1_DP1
ADC1_DM1
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
TAMPER2
TAMPER1
PTA2
PTA3
PTA8
PTA12
PTA16
PTA17
PTA24
K
L
ADC0_DP0/
ADC1_DP3
ADC0_DM0/
ADC1_DM3
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
TAMPER0/
RTC_
WAKEUP_B
VBAT
PTA4/
LLWU_P3
PTA9
PTA11
PTA14
PTA15
RESET_b
L
M ADC1_DP0/
ADC0_DP3
ADC1_DM0/
ADC0_DM3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
TAMPER5
NC
EXTAL32
XTAL32
PTA5
PTA10
VSS
PTA19
PTA18
M
2
3
4
5
6
7
8
9
10
11
12
1
Figure 37. K63 144 MAPBGA Pinout Diagram
6 Ordering parts
74
NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MK63
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K63 = Ethernet, Tamper, and high RAM
density
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
Table continues on the next page...
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NXP Semiconductors
Terminology and guidelines
Field
Description
Values
• 1M0 = 1 MB
• 2M0 = 2 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
•
•
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
16 = 168 MHz
18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MK63FN1M0VMD12
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
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NXP Semiconductors
Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016
Terminology and guidelines
Term
Rating
Definition
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
8.2 Examples
EX
AM
PL
E
Operating rating:
EX
AM
PL
E
Operating requirement:
EX
AM
PL
E
Operating behavior that includes a typical value:
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NXP Semiconductors
Terminology and guidelines
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
Supply voltage
3.3
V
8.4 Relationship between ratings and operating requirements
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Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
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Operating (power on)
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Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
Handling (power off)
∞
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
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Revision History
9 Revision History
The following table provides a revision history for this document.
Table 58. Revision History
Rev. No.
Date
Substantial Changes
2
01/2014
3
04/2014
• Format changes
4
09/2014
• Updated Table 6 "Power consumption operating behavior."
• Updated Table 17 "IRC48M specifications
• Updated Table 35 "VREF full-range operating behavior"
5
12/2014
• Updated Table 6 "Power consumption operating behavior."
• Added a note to the section "Power consumption operating behaviors."
6
08/2015
• Added a footnote to the maximum SCL clock frequency value in the table "I2C
timing"
• Changed the title of the table "I2C 1 MHZ timing" to "I2C 1 Mbps timing"
• Added a footnote and updated the table "IRC48M specifications" for open loop total
deviation of IRC48M frequency at high voltage and low voltage.
• Added a footnote on the ambient temperature entry to the section "Thermal
operating requirements."
• Added a note to the section "Power consumption operating behaviors" and updated
values in the table "Power consumption operating behaviors."
• Added a note to the maximum frequency value in the table "Slave mode DSPI timing
(limited voltage range)."
• Redeveloped the section "Terminology and guidelines."
7
10/2016
• Updated the values of IDD_STOP and IDD_VLLS0 in the table "Power consumption
operating behaviors"
Initial public release.
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NXP Semiconductors
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Information in this document is provided solely to enable system and software
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may vary over time. All operating parameters, including “typicals,” must be
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Document Number K63P144M120SF5
Revision 7, 11/2016
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