KE02 Sub-Family Reference Manual
Supports: MKE02Z16VLC4(R), MKE02Z32VLC4(R),
MKE02Z64VLC4(R), MKE02Z16VLD4(R), MKE02Z32VLD4(R),
MKE02Z64VLD4(R), MKE02Z32VLH4(R), MKE02Z64VLH4(R),
MKE02Z32VQH4(R), MKE02Z64VQH4(R), MKE02Z16VFM4(R),
MKE02Z32VFM4(R), and MKE02Z64VFM4(R)
Document Number: MKE02P64M40SF0RM
Rev 3, Nov. 2014
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Contents
Section number
Title
Page
Chapter 1
About This Document
1.1
1.2
Overview.........................................................................................................................................................................33
1.1.1
Purpose.............................................................................................................................................................33
1.1.2
Audience.......................................................................................................................................................... 33
Conventions.................................................................................................................................................................... 33
1.2.1
Numbering systems..........................................................................................................................................33
1.2.2
Typographic notation....................................................................................................................................... 34
1.2.3
Special terms.................................................................................................................................................... 34
Chapter 2
Introduction
2.1
Overview.........................................................................................................................................................................35
2.2
Module functional categories..........................................................................................................................................35
2.2.1
ARM Cortex-M0+ core modules..................................................................................................................... 36
2.2.2
System modules............................................................................................................................................... 37
2.2.3
Memories and memory interfaces....................................................................................................................37
2.2.4
Clocks...............................................................................................................................................................38
2.2.5
Security and integrity modules........................................................................................................................ 38
2.2.6
Analog modules............................................................................................................................................... 38
2.2.7
Timer modules................................................................................................................................................. 39
2.2.8
Communication interfaces............................................................................................................................... 39
2.2.9
Human-machine interfaces.............................................................................................................................. 40
2.2.10
Orderable part numbers....................................................................................................................................40
Chapter 3
Chip Configuration
3.1
Introduction.....................................................................................................................................................................43
3.2
Module to Module Interconnects.................................................................................................................................... 43
3.2.1
Interconnection overview.................................................................................................................................43
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Section number
3.3
Page
3.2.2
Analog reference options................................................................................................................................. 45
3.2.3
ACMP0 output capture.................................................................................................................................... 45
3.2.4
UART0_TX modulation.................................................................................................................................. 45
3.2.5
UART0_RX capture........................................................................................................................................ 46
3.2.6
UART0_RX filter............................................................................................................................................ 46
3.2.7
RTC capture..................................................................................................................................................... 47
3.2.8
FTM2 software synchronization...................................................................................................................... 47
3.2.9
ADC hardware trigger......................................................................................................................................47
Core Modules..................................................................................................................................................................48
3.3.1
3.3.2
3.3.3
ARM Cortex-M0+ core configuration............................................................................................................. 48
3.3.1.1
ARM Cortex M0+ core ............................................................................................................... 49
3.3.1.2
Buses, interconnects, and interfaces............................................................................................ 49
3.3.1.3
System Tick Timer.......................................................................................................................50
3.3.1.4
Core privilege levels.................................................................................................................... 50
3.3.1.5
Caches.......................................................................................................................................... 50
Nested Vectored Interrupt Controller (NVIC) configuration...........................................................................50
3.3.2.1
Interrupt priority levels................................................................................................................ 51
3.3.2.2
Non-maskable interrupt................................................................................................................51
3.3.2.3
Interrupt channel assignments......................................................................................................51
Asynchronous wakeup interrupt controller (AWIC) configuration................................................................. 54
3.3.3.1
3.4
Title
Wakeup sources........................................................................................................................... 54
System Modules..............................................................................................................................................................55
3.4.1
SIM configuration............................................................................................................................................ 55
3.4.2
PMC configuration...........................................................................................................................................56
3.4.3
MCM configuration......................................................................................................................................... 57
3.4.4
Crossbar-light switch configuration.................................................................................................................57
3.4.4.1
Crossbar-Light switch master assignments..................................................................................58
3.4.4.2
Crossbar switch slave assignments.............................................................................................. 58
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Section number
3.4.5
3.5
3.6
Peripheral bridge configuration....................................................................................................................... 59
3.4.5.1
Number of peripheral bridges...................................................................................................... 59
3.4.5.2
Memory maps.............................................................................................................................. 59
3.5.1
CRC configuration........................................................................................................................................... 60
3.5.2
Watchdog configuration...................................................................................................................................60
3.5.2.1
WDOG clocks.............................................................................................................................. 61
3.5.2.2
WDOG operation......................................................................................................................... 61
Clock Modules................................................................................................................................................................ 62
ICS configuration............................................................................................................................................. 62
3.6.1.1
3.6.2
Clock gating................................................................................................................................. 63
OSC configuration........................................................................................................................................... 63
Memories and Memory Interfaces.................................................................................................................................. 64
3.7.1
3.8
Page
System Security.............................................................................................................................................................. 60
3.6.1
3.7
Title
Flash memory configuration............................................................................................................................ 64
3.7.1.1
Flash and EEPROM memory sizes.............................................................................................. 65
3.7.1.2
Flash memory map.......................................................................................................................66
3.7.1.3
Flash security............................................................................................................................... 66
3.7.1.4
Erase all flash contents.................................................................................................................66
3.7.2
Flash memory controller configuration............................................................................................................67
3.7.3
SRAM configuration........................................................................................................................................67
3.7.3.1
SRAM sizes..................................................................................................................................68
3.7.3.2
SRAM ranges............................................................................................................................... 68
Analog.............................................................................................................................................................................70
3.8.1
12-bit analog-to-digital converter (ADC) configuration..................................................................................70
3.8.1.1
ADC instantiation information.....................................................................................................70
3.8.1.2
ADC0 connections/channel assignment.......................................................................................71
3.8.1.3
ADC analog supply and reference connections........................................................................... 72
3.8.1.4
Temperature sensor and bandgap.................................................................................................72
3.8.1.5
Alternate clock............................................................................................................................. 72
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Section number
3.8.2
3.9
Title
Page
ACMP configuration........................................................................................................................................73
3.8.2.1
ACMP overview.......................................................................................................................... 74
3.8.2.2
ACMP interconnections............................................................................................................... 74
3.8.2.3
ACMP in Stop mode.................................................................................................................... 75
Timers............................................................................................................................................................................. 75
3.9.1
3.9.2
3.9.3
FlexTimer configuration.................................................................................................................................. 75
3.9.1.1
FTM overview..............................................................................................................................76
3.9.1.2
FTM clock options....................................................................................................................... 77
3.9.1.3
FTM interconnections.................................................................................................................. 77
3.9.1.4
FTM interrupts............................................................................................................................. 78
PIT configuration............................................................................................................................................. 78
3.9.2.1
PIT overview................................................................................................................................79
3.9.2.2
PIT interconnections.................................................................................................................... 79
RTC configuration........................................................................................................................................... 79
3.9.3.1
RTC overview.............................................................................................................................. 80
3.9.3.2
RTC interconnections.................................................................................................................. 80
3.10 Communication interfaces.............................................................................................................................................. 81
3.10.1
SPI configuration............................................................................................................................................. 81
3.10.1.1
3.10.2
I2C configuration............................................................................................................................................. 82
3.10.2.1
3.10.3
SPI overview................................................................................................................................ 81
I2C overview................................................................................................................................82
UART configuration........................................................................................................................................ 82
3.10.3.1
UART overview........................................................................................................................... 83
3.10.3.2
UART interconnection................................................................................................................. 83
3.11 Human-machine interfaces (HMI)..................................................................................................................................84
3.11.1
GPIO configuration..........................................................................................................................................84
3.11.1.1
3.11.2
GPIO overview............................................................................................................................ 84
KBI configuration............................................................................................................................................ 85
3.11.2.1
KBI overview............................................................................................................................... 85
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Section number
3.11.2.2
3.11.3
Title
Page
KBI assignments.......................................................................................................................... 85
IRQ configuration............................................................................................................................................ 86
3.11.3.1
IRQ assignment............................................................................................................................86
Chapter 4
Memory Map
4.1
Introduction.....................................................................................................................................................................87
4.2
System memory map.......................................................................................................................................................87
4.3
Bit Manipulation Engine.................................................................................................................................................88
4.4
System ROM memory map............................................................................................................................................ 88
4.5
4.6
4.4.1
Entry (ROM_ENTRYn)...................................................................................................................................90
4.4.2
End of Table Marker Register (ROM_TABLEMARK).................................................................................. 91
4.4.3
System Access Register (ROM_SYSACCESS).............................................................................................. 91
4.4.4
Peripheral ID Register (ROM_PERIPHIDn)................................................................................................... 92
4.4.5
Component ID Register (ROM_COMPIDn)................................................................................................... 92
Peripheral bridge (AIPS-Lite) memory map...................................................................................................................93
4.5.1
Read-after-write sequence and required serialization of memory operations..................................................93
4.5.2
Peripheral Bridge (AIPS-Lite) Memory Map.................................................................................................. 94
Private Peripheral Bus (PPB) memory map....................................................................................................................97
Chapter 5
Clock Distribution
5.1
Introduction.....................................................................................................................................................................99
5.2
Programming model........................................................................................................................................................99
5.3
High-level device clocking diagram............................................................................................................................... 99
5.4
Clock definitions.............................................................................................................................................................101
5.4.1
Device clock summary.....................................................................................................................................101
5.4.2
Clock distribution.............................................................................................................................................102
5.5
Internal clocking sources................................................................................................................................................ 103
5.6
External clock sources.................................................................................................................................................... 104
5.7
Clock gating.................................................................................................................................................................... 105
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Section number
5.8
Title
Page
Module clocks.................................................................................................................................................................105
Chapter 6
Reset and Boot
6.1
Introduction.....................................................................................................................................................................109
6.2
Reset................................................................................................................................................................................109
6.2.1
Power-on reset (POR)...................................................................................................................................... 109
6.2.2
System reset sources........................................................................................................................................ 110
6.2.3
6.3
6.2.2.1
External pin reset (RESET)..........................................................................................................110
6.2.2.2
Low-voltage detect (LVD)...........................................................................................................111
6.2.2.3
Watchdog timer............................................................................................................................111
6.2.2.4
ICS loss-of-clock (LOC).............................................................................................................. 111
6.2.2.5
Stop mode acknowledge error (SACKERR) .............................................................................. 112
6.2.2.6
Software reset (SW)..................................................................................................................... 112
6.2.2.7
Lockup reset (LOCKUP)............................................................................................................. 112
6.2.2.8
MDM-AP system reset request.................................................................................................... 112
MCU resets...................................................................................................................................................... 112
6.2.3.1
POR Only .................................................................................................................................... 112
6.2.3.2
Chip POR .................................................................................................................................... 113
6.2.3.3
Early Chip Reset ......................................................................................................................... 113
6.2.3.4
Chip Reset ................................................................................................................................... 113
Boot.................................................................................................................................................................................113
6.3.1
Boot sources..................................................................................................................................................... 113
6.3.2
Boot sequence.................................................................................................................................................. 114
Chapter 7
Power Management
7.1
Introduction.....................................................................................................................................................................115
7.2
Power modes...................................................................................................................................................................115
7.3
Entering and exiting power modes................................................................................................................................. 116
7.4
Module operation in low-power modes.......................................................................................................................... 116
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Section number
Title
Page
Chapter 8
Security
8.1
Introduction.....................................................................................................................................................................119
8.2
Flash security.................................................................................................................................................................. 119
8.3
Security interactions with other modules........................................................................................................................120
8.3.1
Security interactions with debug......................................................................................................................120
Chapter 9
Debug
9.1
Introduction.....................................................................................................................................................................121
9.2
Debug port pin descriptions............................................................................................................................................ 121
9.3
SWD status and control registers....................................................................................................................................122
9.3.1
MDM-AP status register.................................................................................................................................. 123
9.3.2
MDM-AP Control register............................................................................................................................... 124
9.4
Debug resets....................................................................................................................................................................125
9.5
Debug in low-power modes............................................................................................................................................ 125
9.6
Debug and security......................................................................................................................................................... 126
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction.....................................................................................................................................................................127
10.2 Pinout.............................................................................................................................................................................. 127
10.2.1
Signal multiplexing and pin assignments.........................................................................................................127
10.2.2
Device pin assignment..................................................................................................................................... 130
10.3 Module signal description tables.................................................................................................................................... 132
10.3.1
Core modules................................................................................................................................................... 132
10.3.2
System modules............................................................................................................................................... 132
10.3.3
Clock modules..................................................................................................................................................133
10.3.4
Analog.............................................................................................................................................................. 133
10.3.5
Timer modules................................................................................................................................................. 134
10.3.6
Communication Interfaces............................................................................................................................... 134
10.3.7
Human-machine interfaces (HMI)................................................................................................................... 136
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Section number
Title
Page
Chapter 11
Port Control (PORT)
11.1 Introduction.....................................................................................................................................................................137
11.2 Port data and data direction.............................................................................................................................................139
11.3 Internal pullup enable..................................................................................................................................................... 140
11.4 Input glitch filter setting..................................................................................................................................................140
11.5 High current drive........................................................................................................................................................... 141
11.6 Pin behavior in Stop mode..............................................................................................................................................141
11.7 Port data registers............................................................................................................................................................142
11.7.1
Port Filter Register (PORT_IOFLT)................................................................................................................142
11.7.2
Port Pullup Enable Low Register (PORT_PUEL)........................................................................................... 145
11.7.3
Port Pullup Enable High Register (PORT_PUEH)..........................................................................................150
11.7.4
Port High Drive Enable Register (PORT_HDRVE)........................................................................................154
Chapter 12
System Integration Module (SIM)
12.1 Introduction.....................................................................................................................................................................157
12.1.1
Features............................................................................................................................................................ 157
12.2 Memory map and register definition...............................................................................................................................157
12.2.1
System Reset Status and ID Register (SIM_SRSID).......................................................................................158
12.2.2
System Options Register (SIM_SOPT)........................................................................................................... 161
12.2.3
Pin Selection Register (SIM_PINSEL)............................................................................................................164
12.2.4
System Clock Gating Control Register (SIM_SCGC).....................................................................................166
12.2.5
Universally Unique Identifier Low Register (SIM_UUIDL).......................................................................... 169
12.2.6
Universally Unique Identifier High Register (SIM_UUIDH)......................................................................... 170
12.2.7
BUS Clock Divider Register (SIM_BUSDIV)................................................................................................ 170
12.3 Functional description.....................................................................................................................................................171
Chapter 13
Power Management Controller (PMC)
13.1 Introduction.....................................................................................................................................................................173
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Page
13.2 Low voltage detect (LVD) system..................................................................................................................................173
13.2.1
Power-on reset (POR) operation...................................................................................................................... 174
13.2.2
LVD reset operation.........................................................................................................................................174
13.2.3
LVD enabled in Stop mode..............................................................................................................................174
13.2.4
Low-voltage warning (LVW).......................................................................................................................... 175
13.3 Bandgap reference.......................................................................................................................................................... 175
13.4 Memory map and register descriptions...........................................................................................................................175
13.4.1
System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................176
13.4.2
System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................177
Chapter 14
Miscellaneous Control Module (MCM)
14.1 Introduction.....................................................................................................................................................................179
14.1.1
Features............................................................................................................................................................ 179
14.2 Memory map/register descriptions................................................................................................................................. 179
14.2.1
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)....................................................................180
14.2.2
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)................................................................ 180
14.2.3
Platform Control Register (MCM_PLACR)....................................................................................................181
Chapter 15
Peripheral Bridge (AIPS-Lite)
15.1 Introduction.....................................................................................................................................................................185
15.1.1
Features............................................................................................................................................................ 185
15.1.2
General operation............................................................................................................................................. 185
15.2 Functional description.....................................................................................................................................................186
15.2.1
Access support................................................................................................................................................. 186
Chapter 16
Watchdog Timer (WDOG)
16.1 Introduction.....................................................................................................................................................................187
16.1.1
Features............................................................................................................................................................ 187
16.1.2
Block diagram.................................................................................................................................................. 188
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16.2 Memory map and register definition...............................................................................................................................189
16.2.1
Watchdog Control and Status Register 1 (WDOG_CS1)................................................................................ 189
16.2.2
Watchdog Control and Status Register 2 (WDOG_CS2)................................................................................ 191
16.2.3
Watchdog Counter Register: High (WDOG_CNTH)...................................................................................... 192
16.2.4
Watchdog Counter Register: Low (WDOG_CNTL)....................................................................................... 192
16.2.5
Watchdog Timeout Value Register: High (WDOG_TOVALH)..................................................................... 193
16.2.6
Watchdog Timeout Value Register: Low (WDOG_TOVALL)...................................................................... 193
16.2.7
Watchdog Window Register: High (WDOG_WINH)..................................................................................... 194
16.2.8
Watchdog Window Register: Low (WDOG_WINL)...................................................................................... 194
16.3 Functional description.....................................................................................................................................................195
16.3.1
16.3.2
Watchdog refresh mechanism.......................................................................................................................... 195
16.3.1.1
Window mode.............................................................................................................................. 196
16.3.1.2
Refreshing the Watchdog.............................................................................................................196
16.3.1.3
Example code: Refreshing the Watchdog.................................................................................... 197
Configuring the Watchdog...............................................................................................................................197
16.3.2.1
Reconfiguring the Watchdog....................................................................................................... 198
16.3.2.2
Unlocking the Watchdog............................................................................................................. 198
16.3.2.3
Example code: Reconfiguring the Watchdog.............................................................................. 198
16.3.3
Clock source.....................................................................................................................................................199
16.3.4
Using interrupts to delay resets........................................................................................................................ 200
16.3.5
Backup reset..................................................................................................................................................... 200
16.3.6
Functionality in debug and low-power modes................................................................................................. 200
16.3.7
Fast testing of the watchdog.............................................................................................................................201
16.3.7.1
Testing each byte of the counter.................................................................................................. 201
16.3.7.2
Entering user mode...................................................................................................................... 202
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction.....................................................................................................................................................................203
17.1.1
Overview.......................................................................................................................................................... 204
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Title
Page
17.1.2
Features............................................................................................................................................................ 204
17.1.3
Modes of operation.......................................................................................................................................... 205
17.2 Memory map and register definition...............................................................................................................................205
17.3 Functional description.....................................................................................................................................................205
17.3.1
17.3.2
17.3.3
BME decorated stores...................................................................................................................................... 206
17.3.1.1
Decorated store logical AND (AND)...........................................................................................208
17.3.1.2
Decorated store logical OR (OR).................................................................................................209
17.3.1.3
Decorated store logical XOR (XOR)........................................................................................... 210
17.3.1.4
Decorated store bit field insert (BFI)........................................................................................... 211
BME decorated loads....................................................................................................................................... 213
17.3.2.1
Decorated load: load-and-clear 1 bit (LAC1).............................................................................. 216
17.3.2.2
Decorated Load: Load-and-Set 1 Bit (LAS1).............................................................................. 217
17.3.2.3
Decorated load unsigned bit field extract (UBFX)...................................................................... 218
Additional details on decorated addresses and GPIO accesses........................................................................219
17.4 Application information..................................................................................................................................................220
Chapter 18
Flash Memory Module (FTMRH)
18.1 Introduction.....................................................................................................................................................................223
18.2 Feature.............................................................................................................................................................................223
18.2.1
Flash memory features..................................................................................................................................... 224
18.2.2
EEPROM features............................................................................................................................................224
18.2.3
Other flash module features............................................................................................................................. 224
18.3 Functional description.....................................................................................................................................................224
18.3.1
Modes of operation.......................................................................................................................................... 224
18.3.1.1
Wait mode.................................................................................................................................... 225
18.3.1.2
Stop mode.................................................................................................................................... 225
18.3.2
Flash and EEPROM memory map...................................................................................................................225
18.3.3
Flash and EEPROM initialization after system reset.......................................................................................225
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18.3.4
18.3.5
Title
Page
Flash and EEPROM command operations.......................................................................................................226
18.3.4.1
Writing the FCLKDIV register.................................................................................................... 227
18.3.4.2
Command write sequence............................................................................................................ 229
Flash and EEPROM interrupts.........................................................................................................................231
18.3.5.1
Description of flash and EEPROM interrupt operation............................................................... 231
18.3.6
Protection......................................................................................................................................................... 232
18.3.7
Security............................................................................................................................................................ 237
18.3.8
18.3.9
18.3.7.1
Unsecuring the MCU using backdoor key access........................................................................237
18.3.7.2
Unsecuring the MCU using SWD................................................................................................238
18.3.7.3
Mode and security effects on flash and EEPROM command availability...................................239
Flash and EEPROM commands.......................................................................................................................239
18.3.8.1
Flash and EEPROM commands...................................................................................................239
18.3.8.2
EEPROM commands................................................................................................................... 240
18.3.8.3
Allowed simultaneous flash and EEPROM operations............................................................... 240
Flash and EEPROM command summary........................................................................................................ 241
18.3.9.1
Erase Verify All Blocks command.............................................................................................. 241
18.3.9.2
Erase Verify Block command...................................................................................................... 242
18.3.9.3
Erase Verify Flash Section command.......................................................................................... 243
18.3.9.4
Read once command.................................................................................................................... 244
18.3.9.5
Program Flash command............................................................................................................. 245
18.3.9.6
Program Once command..............................................................................................................246
18.3.9.7
Erase All Blocks command..........................................................................................................247
18.3.9.8
Erase flash block command......................................................................................................... 248
18.3.9.9
Erase flash sector command.........................................................................................................248
18.3.9.10
Unsecure flash command............................................................................................................. 249
18.3.9.11
Verify backdoor access key command.........................................................................................250
18.3.9.12
Set user margin level command................................................................................................... 250
18.3.9.13
Set factory margin level command.............................................................................................. 252
18.3.9.14
Erase verify EEPROM section command.................................................................................... 253
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18.3.9.15
Program EEPROM command...................................................................................................... 254
18.3.9.16
Erase EEPROM sector command................................................................................................ 255
18.4 Memory map and register definition...............................................................................................................................256
18.4.1
Flash Clock Divider Register (FTMRH_FCLKDIV)...................................................................................... 256
18.4.2
Flash Security Register (FTMRH_FSEC)....................................................................................................... 257
18.4.3
Flash CCOB Index Register (FTMRH_FCCOBIX)........................................................................................ 258
18.4.4
Flash Configuration Register (FTMRH_FCNFG)........................................................................................... 259
18.4.5
Flash Error Configuration Register (FTMRH_FERCNFG)............................................................................ 260
18.4.6
Flash Status Register (FTMRH_FSTAT)........................................................................................................ 260
18.4.7
Flash Error Status Register (FTMRH_FERSTAT)..........................................................................................261
18.4.8
Flash Protection Register (FTMRH_FPROT)................................................................................................. 262
18.4.9
EEPROM Protection Register (FTMRH_EEPROT)....................................................................................... 264
18.4.10 Flash Common Command Object Register:High (FTMRH_FCCOBHI)........................................................265
18.4.11 Flash Common Command Object Register: Low (FTMRH_FCCOBLO)...................................................... 265
18.4.12 Flash Option Register (FTMRH_FOPT)......................................................................................................... 265
Chapter 19
Flash Memory Controller (FMC)
19.1 Introduction.....................................................................................................................................................................267
19.1.1
Overview.......................................................................................................................................................... 267
19.1.2
Features............................................................................................................................................................ 267
19.2 Modes of operation......................................................................................................................................................... 268
19.3 External signal description..............................................................................................................................................268
19.4 Memory map and register descriptions...........................................................................................................................268
19.5 Functional description.....................................................................................................................................................268
Chapter 20
Internal Clock Source (ICS)
20.1 Introduction.....................................................................................................................................................................271
20.1.1
Features............................................................................................................................................................ 271
20.1.2
Block diagram.................................................................................................................................................. 272
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20.1.3
Title
Page
Modes of operation.......................................................................................................................................... 272
20.1.3.1
FLL engaged internal (FEI)......................................................................................................... 272
20.1.3.2
FLL engaged external (FEE)........................................................................................................272
20.1.3.3
FLL bypassed internal (FBI)........................................................................................................273
20.1.3.4
FLL bypassed internal low power (FBILP)................................................................................. 273
20.1.3.5
FLL bypassed external (FBE)...................................................................................................... 273
20.1.3.6
FLL bypassed external low power (FBELP)............................................................................... 273
20.1.3.7
Stop (STOP)................................................................................................................................. 273
20.2 External signal description..............................................................................................................................................274
20.3 Register definition...........................................................................................................................................................274
20.3.1
ICS Control Register 1 (ICS_C1).................................................................................................................... 274
20.3.2
ICS Control Register 2 (ICS_C2).................................................................................................................... 275
20.3.3
ICS Control Register 3 (ICS_C3).................................................................................................................... 276
20.3.4
ICS Control Register 4 (ICS_C4).................................................................................................................... 277
20.3.5
ICS Status Register (ICS_S)............................................................................................................................ 277
20.4 Functional description.....................................................................................................................................................278
20.4.1
Operational modes........................................................................................................................................... 278
20.4.1.1
FLL engaged internal (FEI)......................................................................................................... 279
20.4.1.2
FLL engaged external (FEE)........................................................................................................279
20.4.1.3
FLL bypassed internal (FBI)........................................................................................................280
20.4.1.4
FLL bypassed internal low power (FBILP)................................................................................. 280
20.4.1.5
FLL bypassed external (FBE)...................................................................................................... 280
20.4.1.6
FLL bypassed external low power (FBELP)............................................................................... 281
20.4.1.7
Stop.............................................................................................................................................. 281
20.4.2
Mode switching................................................................................................................................................281
20.4.3
Bus frequency divider...................................................................................................................................... 282
20.4.4
Low-power field usage.....................................................................................................................................282
20.4.5
Internal reference clock....................................................................................................................................282
20.4.6
Fixed frequency clock...................................................................................................................................... 282
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20.4.7
Title
Page
FLL lock and clock monitor.............................................................................................................................283
20.4.7.1
FLL clock lock............................................................................................................................. 283
20.4.7.2
External reference clock monitor................................................................................................. 283
20.5 Initialization/application information............................................................................................................................. 284
20.5.1
Initializing FEI mode....................................................................................................................................... 284
20.5.2
Initializing FBI mode....................................................................................................................................... 284
20.5.3
Initializing FEE mode...................................................................................................................................... 284
20.5.4
Initializing FBE mode...................................................................................................................................... 285
Chapter 21
Oscillator (OSC)
21.1 Introduction.....................................................................................................................................................................287
21.1.1
Overview.......................................................................................................................................................... 287
21.1.2
Features and modes.......................................................................................................................................... 287
21.1.3
Block diagram.................................................................................................................................................. 287
21.2 Signal description............................................................................................................................................................288
21.3 External crystal / resonator connections......................................................................................................................... 289
21.4 External clock connections............................................................................................................................................. 290
21.5 Memory map and register descriptions...........................................................................................................................291
21.5.1
OSC Control Register (OSC_CR)....................................................................................................................291
21.6 Functional description.....................................................................................................................................................292
21.6.1
21.6.2
OSC module states........................................................................................................................................... 292
21.6.1.1
Off................................................................................................................................................ 293
21.6.1.2
Oscillator startup.......................................................................................................................... 294
21.6.1.3
Oscillator stable............................................................................................................................294
21.6.1.4
External clock mode.....................................................................................................................294
OSC module modes......................................................................................................................................... 294
21.6.2.1
Low-frequency, high-gain mode..................................................................................................295
21.6.2.2
Low-frequency, low-power mode................................................................................................295
21.6.2.3
High-frequency, high-gain mode................................................................................................. 295
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21.6.2.4
Title
Page
High-frequency, low-power mode............................................................................................... 296
21.6.3
Counter.............................................................................................................................................................296
21.6.4
Reference clock pin requirements....................................................................................................................296
Chapter 22
Cyclic Redundancy Check (CRC)
22.1 Introduction.....................................................................................................................................................................297
22.1.1
Features............................................................................................................................................................ 297
22.1.2
Block diagram.................................................................................................................................................. 297
22.1.3
Modes of operation.......................................................................................................................................... 298
22.1.3.1
Run mode..................................................................................................................................... 298
22.1.3.2
Low-power modes (Wait or Stop)............................................................................................... 298
22.2 Memory map and register descriptions...........................................................................................................................298
22.2.1
CRC Data register (CRC_DATA)................................................................................................................... 299
22.2.2
CRC Polynomial register (CRC_GPOLY)...................................................................................................... 300
22.2.3
CRC Control register (CRC_CTRL)................................................................................................................300
22.3 Functional description.....................................................................................................................................................301
22.3.1
CRC initialization/reinitialization.................................................................................................................... 301
22.3.2
CRC calculations..............................................................................................................................................302
22.3.3
22.3.2.1
16-bit CRC................................................................................................................................... 302
22.3.2.2
32-bit CRC................................................................................................................................... 302
Transpose feature............................................................................................................................................. 303
22.3.3.1
22.3.4
Types of transpose....................................................................................................................... 303
CRC result complement................................................................................................................................... 305
Chapter 23
Interrupt (IRQ)
23.1 Introduction.....................................................................................................................................................................307
23.2 Features........................................................................................................................................................................... 307
23.2.1
Pin configuration options................................................................................................................................. 308
23.2.2
Edge and level sensitivity................................................................................................................................ 309
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Page
23.3 Interrupt pin request register...........................................................................................................................................309
23.3.1
Interrupt Pin Request Status and Control Register (IRQ_SC)......................................................................... 309
Chapter 24
Analog-to-digital converter (ADC)
24.1 Introduction.....................................................................................................................................................................311
24.1.1
Features............................................................................................................................................................ 311
24.1.2
Block Diagram................................................................................................................................................. 312
24.2 External Signal Description............................................................................................................................................ 312
24.2.1
Analog Power (VDDA)................................................................................................................................... 313
24.2.2
Analog Ground (VSSA)...................................................................................................................................313
24.2.3
Voltage Reference High (VREFH).................................................................................................................. 313
24.2.4
Voltage Reference Low (VREFL)................................................................................................................... 313
24.2.5
Analog Channel Inputs (ADx)......................................................................................................................... 313
24.3 ADC Control Registers................................................................................................................................................... 314
24.3.1
Status and Control Register 1 (ADC_SC1)......................................................................................................314
24.3.2
Status and Control Register 2 (ADC_SC2)......................................................................................................316
24.3.3
Status and Control Register 3 (ADC_SC3)......................................................................................................318
24.3.4
Status and Control Register 4 (ADC_SC4)......................................................................................................319
24.3.5
Conversion Result Register (ADC_R)............................................................................................................. 320
24.3.6
Compare Value Register (ADC_CV).............................................................................................................. 321
24.3.7
Pin Control 1 Register (ADC_APCTL1)......................................................................................................... 322
24.4 Functional description.....................................................................................................................................................322
24.4.1
Clock select and divide control........................................................................................................................ 323
24.4.2
Input select and pin control.............................................................................................................................. 323
24.4.3
Hardware trigger.............................................................................................................................................. 324
24.4.4
Conversion control........................................................................................................................................... 324
24.4.4.1
Initiating conversions................................................................................................................... 324
24.4.4.2
Completing conversions...............................................................................................................325
24.4.4.3
Aborting conversions................................................................................................................... 325
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24.4.4.4
Power control............................................................................................................................... 325
24.4.4.5
Sample time and total conversion time........................................................................................ 326
24.4.5
Automatic compare function............................................................................................................................327
24.4.6
FIFO operation................................................................................................................................................. 328
24.4.7
MCU wait mode operation...............................................................................................................................331
24.4.8
MCU Stop mode operation.............................................................................................................................. 332
24.4.8.1
Stop mode with ADACK disabled...............................................................................................332
24.4.8.2
Stop mode with ADACK enabled................................................................................................332
24.5 Initialization information................................................................................................................................................ 333
24.5.1
24.5.2
ADC module initialization example................................................................................................................ 333
24.5.1.1
Initialization sequence..................................................................................................................333
24.5.1.2
Pseudo-code example...................................................................................................................334
ADC FIFO module initialization example.......................................................................................................334
24.5.2.1
Pseudo-code example...................................................................................................................335
24.6 Application information..................................................................................................................................................336
24.6.1
24.6.2
External pins and routing................................................................................................................................. 336
24.6.1.1
Analog supply pins.......................................................................................................................336
24.6.1.2
Analog reference pins.................................................................................................................. 336
24.6.1.3
Analog input pins......................................................................................................................... 337
Sources of error................................................................................................................................................ 338
24.6.2.1
Sampling error..............................................................................................................................338
24.6.2.2
Pin leakage error.......................................................................................................................... 338
24.6.2.3
Noise-induced errors.................................................................................................................... 338
24.6.2.4
Code width and quantization error...............................................................................................339
24.6.2.5
Linearity errors.............................................................................................................................340
24.6.2.6
Code jitter, non-monotonicity, and missing codes.......................................................................340
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Page
Chapter 25
Analog comparator (ACMP)
25.1 Introduction.....................................................................................................................................................................343
25.1.1
Features............................................................................................................................................................ 343
25.1.2
Modes of operation.......................................................................................................................................... 343
25.1.3
25.1.2.1
Operation in Wait mode............................................................................................................... 344
25.1.2.2
Operation in Stop mode............................................................................................................... 344
25.1.2.3
Operation in Debug mode............................................................................................................ 344
Block diagram.................................................................................................................................................. 344
25.2 External signal description..............................................................................................................................................345
25.3 Memory map and register definition...............................................................................................................................345
25.3.1
ACMP Control and Status Register (ACMPx_CS)..........................................................................................346
25.3.2
ACMP Control Register 0 (ACMPx_C0)........................................................................................................ 347
25.3.3
ACMP Control Register 1 (ACMPx_C1)........................................................................................................ 347
25.3.4
ACMP Control Register 2 (ACMPx_C2)........................................................................................................ 348
25.4 Functional description.....................................................................................................................................................348
25.5 Setup and operation of ACMP........................................................................................................................................349
25.6 Resets.............................................................................................................................................................................. 350
25.7 Interrupts......................................................................................................................................................................... 350
Chapter 26
FlexTimer Module (FTM)
26.1 Introduction.....................................................................................................................................................................351
26.1.1
FlexTimer philosophy...................................................................................................................................... 351
26.1.2
Features............................................................................................................................................................ 352
26.1.3
Modes of operation.......................................................................................................................................... 353
26.1.4
Block diagram.................................................................................................................................................. 354
26.2 FTM signal descriptions................................................................................................................................................. 356
26.3 Memory map and register definition...............................................................................................................................356
26.3.1
Memory map.................................................................................................................................................... 356
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26.3.2
Register descriptions........................................................................................................................................ 356
26.3.3
Status And Control (FTMx_SC)...................................................................................................................... 360
26.3.4
Counter (FTMx_CNT)..................................................................................................................................... 362
26.3.5
Modulo (FTMx_MOD).................................................................................................................................... 362
26.3.6
Channel (n) Status And Control (FTMx_CnSC)..............................................................................................363
26.3.7
Channel (n) Value (FTMx_CnV)..................................................................................................................... 365
26.3.8
Counter Initial Value (FTMx_CNTIN)............................................................................................................366
26.3.9
Capture And Compare Status (FTMx_STATUS)............................................................................................ 367
26.3.10 Features Mode Selection (FTMx_MODE)...................................................................................................... 369
26.3.11 Synchronization (FTMx_SYNC)..................................................................................................................... 370
26.3.12 Initial State For Channels Output (FTMx_OUTINIT).....................................................................................373
26.3.13 Output Mask (FTMx_OUTMASK)................................................................................................................. 374
26.3.14 Function For Linked Channels (FTMx_COMBINE).......................................................................................376
26.3.15 Deadtime Insertion Control (FTMx_DEADTIME)......................................................................................... 381
26.3.16 FTM External Trigger (FTMx_EXTTRIG)..................................................................................................... 382
26.3.17 Channels Polarity (FTMx_POL)...................................................................................................................... 384
26.3.18 Fault Mode Status (FTMx_FMS).....................................................................................................................386
26.3.19 Input Capture Filter Control (FTMx_FILTER)............................................................................................... 388
26.3.20 Fault Control (FTMx_FLTCTRL)................................................................................................................... 389
26.3.21 Configuration (FTMx_CONF)......................................................................................................................... 391
26.3.22 FTM Fault Input Polarity (FTMx_FLTPOL)...................................................................................................392
26.3.23 Synchronization Configuration (FTMx_SYNCONF)......................................................................................394
26.3.24 FTM Inverting Control (FTMx_INVCTRL)....................................................................................................396
26.3.25 FTM Software Output Control (FTMx_SWOCTRL)...................................................................................... 397
26.3.26 FTM PWM Load (FTMx_PWMLOAD)......................................................................................................... 399
26.4 Functional description.....................................................................................................................................................400
26.4.1
Clock source.....................................................................................................................................................401
26.4.1.1
26.4.2
Counter clock source....................................................................................................................401
Prescaler........................................................................................................................................................... 402
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26.4.3
26.4.4
Title
Page
Counter.............................................................................................................................................................402
26.4.3.1
Up counting..................................................................................................................................402
26.4.3.2
Up-down counting........................................................................................................................405
26.4.3.3
Free running counter.................................................................................................................... 406
26.4.3.4
Counter reset................................................................................................................................ 407
26.4.3.5
When the TOF bit is set............................................................................................................... 407
Input Capture mode..........................................................................................................................................407
26.4.4.1
Filter for Input Capture mode...................................................................................................... 409
26.4.5
Output Compare mode..................................................................................................................................... 410
26.4.6
Edge-Aligned PWM (EPWM) mode............................................................................................................... 411
26.4.7
Center-Aligned PWM (CPWM) mode............................................................................................................ 413
26.4.8
Combine mode................................................................................................................................................. 415
26.4.8.1
26.4.9
Asymmetrical PWM.................................................................................................................... 422
Complementary mode...................................................................................................................................... 422
26.4.10 Registers updated from write buffers...............................................................................................................423
26.4.10.1
CNTIN register update.................................................................................................................423
26.4.10.2
MOD register update....................................................................................................................424
26.4.10.3
CnV register update..................................................................................................................... 424
26.4.11 PWM synchronization......................................................................................................................................425
26.4.11.1
Hardware trigger.......................................................................................................................... 425
26.4.11.2
Software trigger............................................................................................................................426
26.4.11.3
Boundary cycle and loading points.............................................................................................. 427
26.4.11.4
MOD register synchronization.....................................................................................................428
26.4.11.5
CNTIN register synchronization.................................................................................................. 431
26.4.11.6
C(n)V and C(n+1)V register synchronization..............................................................................432
26.4.11.7
OUTMASK register synchronization.......................................................................................... 432
26.4.11.8
INVCTRL register synchronization.............................................................................................435
26.4.11.9
SWOCTRL register synchronization........................................................................................... 436
26.4.11.10 FTM counter synchronization...................................................................................................... 438
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26.4.12 Inverting........................................................................................................................................................... 441
26.4.13 Software output control....................................................................................................................................443
26.4.14 Deadtime insertion........................................................................................................................................... 445
26.4.14.1
Deadtime insertion corner cases.................................................................................................. 446
26.4.15 Output mask..................................................................................................................................................... 448
26.4.16 Fault control..................................................................................................................................................... 449
26.4.16.1
Automatic fault clearing...............................................................................................................451
26.4.16.2
Manual fault clearing................................................................................................................... 451
26.4.16.3
Fault inputs polarity control......................................................................................................... 452
26.4.17 Polarity control.................................................................................................................................................452
26.4.18 Initialization..................................................................................................................................................... 453
26.4.19 Features priority............................................................................................................................................... 453
26.4.20 Channel trigger output..................................................................................................................................... 454
26.4.21 Initialization trigger..........................................................................................................................................455
26.4.22 Capture Test mode........................................................................................................................................... 457
26.4.23 Dual Edge Capture mode................................................................................................................................. 458
26.4.23.1
One-Shot Capture mode...............................................................................................................459
26.4.23.2
Continuous Capture mode............................................................................................................460
26.4.23.3
Pulse width measurement.............................................................................................................460
26.4.23.4
Period measurement..................................................................................................................... 462
26.4.23.5
Read coherency mechanism.........................................................................................................464
26.4.24 Debug mode..................................................................................................................................................... 465
26.4.25 Intermediate load..............................................................................................................................................466
26.4.26 Global time base (GTB)................................................................................................................................... 468
26.4.26.1
Enabling the global time base (GTB).......................................................................................... 469
26.5 Reset overview................................................................................................................................................................470
26.6 FTM Interrupts................................................................................................................................................................471
26.6.1
Timer Overflow Interrupt.................................................................................................................................472
26.6.2
Channel (n) Interrupt........................................................................................................................................472
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26.6.3
Title
Page
Fault Interrupt.................................................................................................................................................. 472
Chapter 27
Periodic Interrupt Timer (PIT)
27.1 Introduction.....................................................................................................................................................................473
27.1.1
Block diagram.................................................................................................................................................. 473
27.1.2
Features............................................................................................................................................................ 474
27.2 Signal description............................................................................................................................................................474
27.3 Memory map/register description................................................................................................................................... 475
27.3.1
PIT Module Control Register (PIT_MCR)...................................................................................................... 475
27.3.2
Timer Load Value Register (PIT_LDVALn)...................................................................................................476
27.3.3
Current Timer Value Register (PIT_CVALn)................................................................................................. 477
27.3.4
Timer Control Register (PIT_TCTRLn).......................................................................................................... 477
27.3.5
Timer Flag Register (PIT_TFLGn)..................................................................................................................478
27.4 Functional description.....................................................................................................................................................479
27.4.1
General operation............................................................................................................................................. 479
27.4.1.1
Timers.......................................................................................................................................... 479
27.4.1.2
Debug mode................................................................................................................................. 480
27.4.2
Interrupts.......................................................................................................................................................... 480
27.4.3
Chained timers................................................................................................................................................. 481
27.5 Initialization and application information.......................................................................................................................481
27.6 Example configuration for chained timers......................................................................................................................482
Chapter 28
Real-Time Counter (RTC)
28.1 Introduction.....................................................................................................................................................................485
28.2 Features........................................................................................................................................................................... 485
28.2.1
28.2.2
Modes of operation.......................................................................................................................................... 485
28.2.1.1
Wait mode.................................................................................................................................... 485
28.2.1.2
Stop modes................................................................................................................................... 486
Block diagram.................................................................................................................................................. 486
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28.3 External signal description..............................................................................................................................................486
28.4 Register definition...........................................................................................................................................................487
28.4.1
RTC Status and Control Register (RTC_SC).................................................................................................. 487
28.4.2
RTC Modulo Register (RTC_MOD)............................................................................................................... 489
28.4.3
RTC Counter Register (RTC_CNT)................................................................................................................ 489
28.5 Functional description.....................................................................................................................................................490
28.5.1
RTC operation example................................................................................................................................... 491
28.6 Initialization/application information............................................................................................................................. 492
Chapter 29
Serial Peripheral Interface (SPI)
29.1 Introduction.....................................................................................................................................................................493
29.1.1
Features............................................................................................................................................................ 493
29.1.2
Modes of operation.......................................................................................................................................... 494
29.1.3
Block diagrams................................................................................................................................................ 495
29.1.3.1
SPI system block diagram............................................................................................................495
29.1.3.2
SPI module block diagram........................................................................................................... 495
29.2 External signal description..............................................................................................................................................497
29.2.1
SPSCK — SPI Serial Clock.............................................................................................................................497
29.2.2
MOSI — Master Data Out, Slave Data In....................................................................................................... 498
29.2.3
MISO — Master Data In, Slave Data Out....................................................................................................... 498
29.2.4
SS — Slave Select............................................................................................................................................498
29.3 Memory map/register definition..................................................................................................................................... 499
29.3.1
SPI Control Register 1 (SPIx_C1)................................................................................................................... 499
29.3.2
SPI Control Register 2 (SPIx_C2)................................................................................................................... 501
29.3.3
SPI Baud Rate Register (SPIx_BR)................................................................................................................. 502
29.3.4
SPI Status Register (SPIx_S)........................................................................................................................... 503
29.3.5
SPI Data Register (SPIx_D)............................................................................................................................. 504
29.3.6
SPI Match Register (SPIx_M)..........................................................................................................................505
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Section number
Title
Page
29.4 Functional description.....................................................................................................................................................505
29.4.1
General............................................................................................................................................................. 505
29.4.2
Master mode.....................................................................................................................................................506
29.4.3
Slave mode....................................................................................................................................................... 507
29.4.4
SPI clock formats............................................................................................................................................. 509
29.4.5
SPI baud rate generation.................................................................................................................................. 512
29.4.6
Special features................................................................................................................................................ 512
29.4.7
29.4.6.1
SS Output..................................................................................................................................... 512
29.4.6.2
Bidirectional mode (MOMI or SISO).......................................................................................... 513
Error conditions................................................................................................................................................514
29.4.7.1
29.4.8
29.4.9
Mode fault error........................................................................................................................... 514
Low-power mode options................................................................................................................................ 515
29.4.8.1
SPI in Run mode.......................................................................................................................... 515
29.4.8.2
SPI in Wait mode......................................................................................................................... 515
29.4.8.3
SPI in Stop mode..........................................................................................................................516
Reset.................................................................................................................................................................516
29.4.10 Interrupts.......................................................................................................................................................... 517
29.4.10.1
MODF.......................................................................................................................................... 517
29.4.10.2
SPRF............................................................................................................................................ 517
29.4.10.3
SPTEF.......................................................................................................................................... 518
29.4.10.4
SPMF........................................................................................................................................... 518
29.4.10.5
Asynchronous interrupt in low-power modes.............................................................................. 518
29.5 Initialization/application information............................................................................................................................. 518
29.5.1
Initialization sequence......................................................................................................................................518
29.5.2
Pseudo-Code Example..................................................................................................................................... 519
Chapter 30
Inter-Integrated Circuit (I2C)
30.1 Introduction.....................................................................................................................................................................523
30.1.1
Features............................................................................................................................................................ 523
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30.1.2
Modes of operation.......................................................................................................................................... 524
30.1.3
Block diagram.................................................................................................................................................. 524
30.2 I2C signal descriptions....................................................................................................................................................525
30.3 Memory map/register definition..................................................................................................................................... 526
30.3.1
I2C Address Register 1 (I2Cx_A1).................................................................................................................. 526
30.3.2
I2C Frequency Divider register (I2Cx_F)........................................................................................................ 527
30.3.3
I2C Control Register 1 (I2Cx_C1)................................................................................................................... 528
30.3.4
I2C Status register (I2Cx_S)............................................................................................................................ 529
30.3.5
I2C Data I/O register (I2Cx_D)....................................................................................................................... 531
30.3.6
I2C Control Register 2 (I2Cx_C2)................................................................................................................... 532
30.3.7
I2C Programmable Input Glitch Filter register (I2Cx_FLT)........................................................................... 533
30.3.8
I2C Range Address register (I2Cx_RA).......................................................................................................... 534
30.3.9
I2C SMBus Control and Status register (I2Cx_SMB)..................................................................................... 534
30.3.10 I2C Address Register 2 (I2Cx_A2).................................................................................................................. 536
30.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)......................................................................................536
30.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL).......................................................................................537
30.4 Functional description.....................................................................................................................................................537
30.4.1
I2C protocol..................................................................................................................................................... 537
30.4.1.1
START signal.............................................................................................................................. 538
30.4.1.2
Slave address transmission...........................................................................................................538
30.4.1.3
Data transfers............................................................................................................................... 539
30.4.1.4
STOP signal................................................................................................................................. 539
30.4.1.5
Repeated START signal...............................................................................................................539
30.4.1.6
Arbitration procedure................................................................................................................... 540
30.4.1.7
Clock synchronization..................................................................................................................540
30.4.1.8
Handshaking.................................................................................................................................541
30.4.1.9
Clock stretching........................................................................................................................... 541
30.4.1.10
I2C divider and hold values......................................................................................................... 541
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30.4.2
Title
Page
10-bit address................................................................................................................................................... 542
30.4.2.1
Master-transmitter addresses a slave-receiver............................................................................. 543
30.4.2.2
Master-receiver addresses a slave-transmitter............................................................................. 543
30.4.3
Address matching.............................................................................................................................................544
30.4.4
System management bus specification............................................................................................................ 545
30.4.4.1
Timeouts.......................................................................................................................................545
30.4.4.2
FAST ACK and NACK............................................................................................................... 547
30.4.5
Resets............................................................................................................................................................... 547
30.4.6
Interrupts.......................................................................................................................................................... 547
30.4.6.1
Byte transfer interrupt.................................................................................................................. 548
30.4.6.2
Address detect interrupt............................................................................................................... 548
30.4.6.3
Stop Detect Interrupt.................................................................................................................... 549
30.4.6.4
Exit from low-power/stop modes.................................................................................................549
30.4.6.5
Arbitration lost interrupt.............................................................................................................. 549
30.4.6.6
Timeout interrupt in SMBus........................................................................................................ 549
30.4.7
Programmable input glitch filter...................................................................................................................... 550
30.4.8
Address matching wake-up.............................................................................................................................. 550
30.5 Initialization/application information............................................................................................................................. 551
Chapter 31
Universal Asynchronous Receiver/Transmitter (UART)
31.1 Introduction.....................................................................................................................................................................555
31.1.1
Features............................................................................................................................................................ 555
31.1.2
Modes of operation.......................................................................................................................................... 555
31.1.3
Block diagram.................................................................................................................................................. 556
31.2 UART signal descriptions...............................................................................................................................................558
31.2.1
Detailed signal descriptions............................................................................................................................. 558
31.3 Register definition...........................................................................................................................................................558
31.3.1
UART Baud Rate Register: High (UARTx_BDH)..........................................................................................559
31.3.2
UART Baud Rate Register: Low (UARTx_BDL)........................................................................................... 560
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Section number
Title
Page
31.3.3
UART Control Register 1 (UARTx_C1)......................................................................................................... 561
31.3.4
UART Control Register 2 (UARTx_C2)......................................................................................................... 562
31.3.5
UART Status Register 1 (UARTx_S1)............................................................................................................ 564
31.3.6
UART Status Register 2 (UARTx_S2)............................................................................................................ 565
31.3.7
UART Control Register 3 (UARTx_C3)......................................................................................................... 567
31.3.8
UART Data Register (UARTx_D)...................................................................................................................568
31.4 Functional description.....................................................................................................................................................569
31.4.1
Baud rate generation........................................................................................................................................ 569
31.4.2
Transmitter functional description................................................................................................................... 570
31.4.2.1
31.4.3
Send break and queued idle......................................................................................................... 571
Receiver functional description....................................................................................................................... 572
31.4.3.1
Data sampling technique.............................................................................................................. 573
31.4.3.2
Receiver wake-up operation.........................................................................................................573
31.4.4
Interrupts and status flags................................................................................................................................ 575
31.4.5
Baud rate tolerance...........................................................................................................................................576
31.4.6
31.4.5.1
Slow data tolerance...................................................................................................................... 576
31.4.5.2
Fast data tolerance........................................................................................................................577
Additional UART functions.............................................................................................................................578
31.4.6.1
8- and 9-bit data modes................................................................................................................ 579
31.4.6.2
Stop mode operation.................................................................................................................... 579
31.4.6.3
Loop mode................................................................................................................................... 579
31.4.6.4
Single-wire operation................................................................................................................... 580
Chapter 32
General-Purpose Input/Output (GPIO)
32.1 Introduction.....................................................................................................................................................................581
32.1.1
Features............................................................................................................................................................ 581
32.1.2
Modes of operation.......................................................................................................................................... 581
32.1.3
GPIO signal descriptions................................................................................................................................. 582
32.1.3.1
Detailed signal description...........................................................................................................582
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Section number
Title
Page
32.2 Memory map and register definition...............................................................................................................................583
32.2.1
GPIO/FGPIO register bits assignment............................................................................................................. 583
32.2.2
Port Data Output Register (GPIOx_PDOR).....................................................................................................584
32.2.3
Port Set Output Register (GPIOx_PSOR)........................................................................................................585
32.2.4
Port Clear Output Register (GPIOx_PCOR)....................................................................................................586
32.2.5
Port Toggle Output Register (GPIOx_PTOR)................................................................................................. 586
32.2.6
Port Data Input Register (GPIOx_PDIR).........................................................................................................587
32.2.7
Port Data Direction Register (GPIOx_PDDR).................................................................................................587
32.2.8
Port Input Disable Register (GPIOx_PIDR).................................................................................................... 588
32.3 FGPIO memory map and register definition.................................................................................................................. 588
32.3.1
GPIO/FGPIO register bits assignment............................................................................................................. 588
32.3.2
Port Data Output Register (FGPIOx_PDOR).................................................................................................. 590
32.3.3
Port Set Output Register (FGPIOx_PSOR)..................................................................................................... 590
32.3.4
Port Clear Output Register (FGPIOx_PCOR)................................................................................................. 591
32.3.5
Port Toggle Output Register (FGPIOx_PTOR)............................................................................................... 591
32.3.6
Port Data Input Register (FGPIOx_PDIR).......................................................................................................592
32.3.7
Port Data Direction Register (FGPIOx_PDDR).............................................................................................. 592
32.3.8
Port Input Disable Register (FGPIOx_PIDR).................................................................................................. 593
32.4 Functional description.....................................................................................................................................................593
32.4.1
General-purpose input......................................................................................................................................593
32.4.2
General-purpose output....................................................................................................................................593
32.4.3
IOPORT........................................................................................................................................................... 594
Chapter 33
Keyboard Interrupts (KBI)
33.1 Introduction.....................................................................................................................................................................595
33.1.1
Features............................................................................................................................................................ 595
33.1.2
Modes of Operation......................................................................................................................................... 595
33.1.2.1
KBI in Wait mode........................................................................................................................ 595
33.1.2.2
KBI in Stop modes....................................................................................................................... 596
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Section number
33.1.3
Title
Page
Block Diagram................................................................................................................................................. 596
33.2 External signals description............................................................................................................................................ 596
33.3 Register definition...........................................................................................................................................................597
33.4 Memory Map and Registers............................................................................................................................................597
33.4.1
KBI Status and Control Register (KBIx_SC).................................................................................................. 598
33.4.2
KBIx Pin Enable Register (KBIx_PE)............................................................................................................. 598
33.4.3
KBIx Edge Select Register (KBIx_ES)........................................................................................................... 599
33.5 Functional Description....................................................................................................................................................599
33.5.1
Edge-only sensitivity........................................................................................................................................600
33.5.2
Edge and level sensitivity................................................................................................................................ 600
33.5.3
KBI Pullup Resistor......................................................................................................................................... 600
33.5.4
KBI initialization..............................................................................................................................................600
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Chapter 1
About This Document
1.1 Overview
1.1.1 Purpose
This document describes the features, architecture, and programming model of the
Freescale KE02 microcontroller.
1.1.2 Audience
This document is primarily for system architects and software application developers
who are using or considering using the KE02 microcontroller in a system.
1.2 Conventions
1.2.1 Numbering systems
The following suffixes identify different numbering systems:
This suffix
Identifies a
b
Binary number. For example, the binary equivalent of the
number 5 is written 101b. In some cases, binary numbers are
shown with the prefix 0b.
d
Decimal number. Decimal numbers are followed by this suffix
only when the possibility of confusion exists. In general,
decimal numbers are shown without a suffix.
h
Hexadecimal number. For example, the hexadecimal
equivalent of the number 60 is written 3Ch. In some cases,
hexadecimal numbers are shown with the prefix 0x.
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33
Conventions
1.2.2 Typographic notation
The following typographic notation is used throughout this document:
Example
Description
placeholder, x
Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as
placeholders for single letters and numbers.
code
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction
mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type
is also used for example code. Instruction mnemonics and directives in text and tables are
shown in all caps; for example, BSR.
SR[SCM]
A mnemonic in brackets represents a named field in a register. This example refers to the
Scaling Mode (SCM) field in the Status Register (SR).
REVNO[6:4], XAD[7:0]
Numbers in brackets and separated by a colon represent either:
• A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.
1.2.3 Special terms
The following terms have special meanings:
Term
Meaning
asserted
Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted
Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved
Refers to a memory space, register, or field that is either
reserved for future use or for which, when written to, the
module or chip behavior is unpredictable.
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Chapter 2
Introduction
2.1 Overview
This chapter provides an overview of the Kinetis KE02 product family of ARM®
Cortex®-M0+ MCUs. It also presents high-level descriptions of the modules available on
the devices covered by this document.
2.2 Module functional categories
The modules on this device are grouped into functional categories. The following
sections describe the modules assigned to each category in more detail.
Table 2-1. Module functional categories
Module category
Description
ARM Cortex-M0+ core
• 32-bit MCU core from ARM’s Cortex-M class, 1.77 CoreMark®/MHz from
single-cycle access memories, up to 40 MHz CPU frequency
System
•
•
•
•
•
•
Memories
• Internal memories include:
• Up to 64 KB flash memory
• Up to 256 B EEPROM memory
• Up to 4 KB SRAM
Clocks
• External crystal oscillator or resonator
• Low range: 31.25–39.0625 kHz
• High range: 4– 20 MHz
• External square wave input clock
• Internal clock references
• 31.25 to 39.0625 kHz oscillator
• 1 kHz LPO oscillator
• Frequency-locked loop (FLL) range: 32–40 MHz
System integration module (SIM)
Power management and mode controllers (PMC)
Miscellaneous control module (MCM)
Bit manipulation engine (BME)
Peripheral bridge (AIPS)
Watchdog (WDOG)
Table continues on the next page...
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Module functional categories
Table 2-1. Module functional categories (continued)
Module category
Description
Security
• Watchdog (WDOG) with independent clock source
• Cyclic redundancy check (CRC) module for error detection
Analog
• One 12-bit analog-to-digital converters (ADC) with up to 16 channels
• Two analog comparators (ACMP) with internal 6-bit digital-to-analog
converter (DAC)
Timers
•
•
•
•
•
Communications
• Two 8-bit serial peripheral interfaces (SPI)
• One inter-integrated circuit (I2C) module
• Up to three universal asynchronous receiver/transmitter (UART) modules
Human-Machine Interfaces (HMI)
• General purpose input/output (GPIO) controller
• Two keyboard Interrupt (KBI)
• Interrupt (IRQ)
One 6-channel FlexTimer (FTM) with full function
Two 2-channel FTMs with basic TPM function
2-channel periodic interrupt timer (PIT)
Real time clock (RTC)
System tick timer (SysTick)
2.2.1 ARM Cortex-M0+ core modules
The following core modules are available on this device.
Table 2-2. Core modules
Module
Description
ARM Cortex-M0+
The ARM Cortex-M0+ is the newest member of the Cortex M Series of processors
targeting microcontroller applications focused on very cost sensitive, deterministic,
interrupt driven environments. The Cortex M0+ processor is based on the ARMv6
Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its
predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4
cores.
The ARM Cortex-M0+ improvements include an ARMv6 Thumb-2 DSP, ported
from the ARMv6-A/R profile architectures, that provide 32-bit instructions with
SIMD (single instruction multiple data) DSP style multiply-accumulates and
saturating arithmetic to support single cycle 32x32 multiplier.
Nested vectored interrupt controller
(NVIC)
The ARMv6-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to ARM
internal sources with the others mapping to MCU-defined interrupts.
Asynchronous wakeup interrupt
controller (AWIC)
The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Table continues on the next page...
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Chapter 2 Introduction
Table 2-2. Core modules (continued)
Module
Description
Single-cycle I/O port (IOPORT)
For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor
implements a dedicated single-cycle I/O port. On this device, fast GPIO (FGPIO) is
implemented on IOPORT interface.
Debug interfaces
Most of this device's debug is based on the ARM CoreSight™ architecture. One
debug interface is supported:
• Serial Wire Debug (SWD)
2.2.2 System modules
The following system modules are available on this device.
Table 2-3. System modules
Module
Description
System integration module (SIM)
The SIM includes integration logic and several module configuration settings.
Power management controller (PMC)
The PMC provides the user with multiple power options. Multiple modes are
supported that allow the user to optimize power consumption for the level of
functionality needed. Includes power-on-reset (POR) and integrated low voltage
detect (LVD) with reset (brownout) capability and selectable LVD trip points.
Miscellaneous control module (MCM)
The MCM includes integration logic and details.
Peripheral bridge (AIPS-Lite)
The peripheral bridge converts the ARM AHB interface to an interface to access a
majority of peripherals on the device.
Watchdog (WDOG)
The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 1 kHz low-power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.
Bit manipulation engine (BME)
The BME provides hardware support for atomic read-modify-write memory
operations to the peripheral address space in Cortex-M0+ based microcontrollers.
2.2.3 Memories and memory interfaces
The following memories and memory interfaces are available on this device.
Table 2-4. Memories and memory interfaces
Module
Description
Flash memory (FTMRH)
Flash memory — up to 64 KB of the non-volatile flash memory that can execute
program code.
EEPROM memory - 256 B of EEPROM memory with byte access
Flash memory controller (FMC)
FMC is a memory acceleration unit that provides an interface between Cortex M0+
core and the 32-bit program flash memory. The FMC contains one 32-bit
Table continues on the next page...
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Module functional categories
Table 2-4. Memories and memory interfaces (continued)
Module
Description
speculation buffer and one 32-byte cache that can accelerate instruction fetch and
flash access.
SRAM
Up to 4 KB internal system RAM, supporting bit operation through BME module or
aliased bit-band domain.
2.2.4 Clocks
The following clock modules are available on this device.
Table 2-5. Clock modules
Module
Description
Internal Clock Source (ICS)
ICS module containing an internal reference clock (ICSIRCLK) and a frequencylocked-loop (FLL).
System oscillator (OSC)
The system oscillator, in conjunction with an external crystal or resonator,
generates a reference clock for the MCU.
Low-Power Oscillator (LPO)
The PMC module contains a 1 kHz low-power oscillator which acts as a standalone
low-frequency clock source in all modes.
2.2.5 Security and integrity modules
The following security and integrity modules are available on this device:
Table 2-6. Security and integrity modules
Module
Description
Cyclic Redundancy Check (CRC)
CRC generates 16/32-bit CRC code for error detection.
Watchdog (WDOG)
The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 1 kHz low-power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.
2.2.6 Analog modules
The following analog modules are available on this device:
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Chapter 2 Introduction
Table 2-7. Analog modules
Module
Description
Analog-to-digital converters (ADC)
12-bit successive-approximation ADC module with up to 16 channels.
Analog comparators (ACMP)
Two comparators with support of analog input voltages across the full range of the
supply voltage and CPU interrupt. ACMP0 is further capable to trigger FTM update.
6-bit digital-to-analog converters (DAC)
64-tap resistor ladder network which provides a selectable voltage reference for
comparator.
2.2.7 Timer modules
The following timer modules are available on this device:
Table 2-8. Timer modules
Module
Description
FlexTimer modules (FTM)
• Selectable FTM source clock, programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up
or up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM
modes
• Operation of FTM channels as pairs with equal outputs, pairs with
complementary outputs, or independent channels with independent outputs
• Deadtime insertion is available for each complementary pair
• Software control of PWM outputs
• Up to two fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture, reference compare, overflowed
counter, or detected fault condition
Periodic interrupt timers (PIT)
•
•
•
•
Real-time counter (RTC)
• 16-bit up-counter
• 16-bit modulo match limit
• Software controllable periodic interrupt on match
• Software selectable clock sources for input to prescaler with programmable
16-bit prescaler
• Bus clock
• IRC clock (31.25~39.0625 kHz)
• LPO (~1 kHz)
• System oscilator output clock
One general purpose interrupt timer
Interrupt timers for triggering ADC conversions
32-bit counter resolution
Clocked by bus clock frequency
2.2.8 Communication interfaces
The following communication interfaces are available on this device:
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Module functional categories
Table 2-9. Communication modules
Module
Description
Serial peripheral interface (SPI)
Two SPIs synchronous serial bus for communication to an external device.
Inter-integrated circuit (I2C)
One I2C module for inter device communications. Also supports the System
Management Bus (SMBus) Specification, version 2.
Universal asynchronous receiver/
transmitters (UART)
Up to three asynchronous serial bus communication interfaces (UART) modules
with optional 13-bit break, full duplex non-return to zero (NRZ), and LIN extension
support.
2.2.9 Human-machine interfaces
The following human-machine interfaces (HMI) are available on this device:
Table 2-10. HMI modules
Module
Description
General purpose input/output (GPIO)
Up to 57 general purpose input or output (GPIO) pins.
Keyboard Interrupts (KBI)
Two KBI modules to support pin interrupts.
Interrupt (IRQ)
IRQ module provides a maskable interrupt input.
2.2.10 Orderable part numbers
The following table summarizes the part numbers of the devices covered by this
document.
Table 2-11. Orderable part numbers summary
Freescale part number
CPU
frequency
Pin count
Package
Total flash
memory
RAM
Temperature range
MKE02Z16VLC4(R)
40 MHz
32
LQFP
16 KB
2 KB
-40 to 105 °C
MKE02Z32VLC4(R)
40 MHz
32
LQFP
32 KB
4 KB
-40 to 105 °C
MKE02Z64VLC4(R)
40 MHz
32
LQFP
64 KB
4 KB
-40 to 105 °C
MKE02Z16VLD4(R)
40 MHz
44
LQFP
16 KB
2 KB
-40 to 105 °C
MKE02Z32VLD4(R)
40 MHz
44
LQFP
32 KB
4 KB
-40 to 105 °C
MKE02Z64VLD4(R)
40 MHz
44
LQFP
64 KB
4 KB
-40 to 105 °C
MKE02Z32VLH4(R)
40 MHz
64
LQFP
32 KB
4 KB
-40 to 105 °C
MKE02Z64VLH4(R)
40 MHz
64
LQFP
64 KB
4 KB
-40 to 105 °C
MKE02Z32VQH4(R)
40 MHz
64
QFP
32 KB
4 KB
-40 to 105 °C
MKE02Z64VQH4(R)
40 MHz
64
QFP
64 KB
4 KB
-40 to 105 °C
MKE02Z16VFM4(R)
40 MHz
32
QFN
16 KB
2 KB
-40 to 105 °C
Table continues on the next page...
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Chapter 2 Introduction
Table 2-11. Orderable part numbers summary (continued)
Freescale part number
CPU
frequency
Pin count
Package
Total flash
memory
RAM
Temperature range
MKE02Z32VFM4(R)
40 MHz
32
QFN
32 KB
4 KB
-40 to 105 °C
MKE02Z64VFM4(R)
40 MHz
32
QFN
64 KB
4 KB
-40 to 105 °C
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Module functional categories
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Chapter 3
Chip Configuration
3.1 Introduction
This chapter provides details on the individual modules of the microcontroller. It
includes:
• Module block diagrams showing immediate connections within the device
• Specific module-to-module interactions not necessarily discussed in the individual
module chapters
• Links for more information
3.2 Module to Module Interconnects
3.2.1 Interconnection overview
The following table captures the module-to-module interconnections for this device.
Table 3-1. Module-to-module interconnects
Peripheral
Signal
—
to Peripheral
Use Case
Control
Comm
ent
FTM2
INITTRG,
MatchTRG
to
ADC (Trigger)
ADC Triggering
SIM_SOPT[ADHWT]
—
PIT0
TIF0
to
ADC (Trigger)
ADC Triggering
SIM_SOPT[ADHWT]
—
RTC
RTC Overflow
to
ADC (Trigger)
ADC Triggering
SIM_SOPT[ADHWT]
—
RTC
RTC Overflow
to
FTM1_CH1
FTM capture input
SIM_SOPT[RTCC]
—
ACMP0
CMP0_OUT
to
FTM1_CH0
FTM capture input
SIM_SOPT[ACIC]
—
ACMP0
CMP0_OUT
to
UART0_RxD
UART0_RxD filter
SIM_SOPT[RXDFE]
—
UART0
UART0_TxD
to
Modulated by
FTM0 CH0
UART modulation
SIM_SOPT[TXDME]
—
Table continues on the next page...
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Module to Module Interconnects
Table 3-1. Module-to-module interconnects (continued)
Peripheral
Signal
—
to Peripheral
Use Case
Control
Comm
ent
UART0
UART0_RxD
to
Tagged by FTM0
CH1
UART modulation
SIM_SOPT[RXDCE]
—
ACMP0
CMP0_OUT
to
FTM2 Trigger0
FTM2 Trigger input
FTM2_SYNC[TRIG0]
—
FTM0
FTM0 CH0
Output
to
FTM2 Trigger1
FTM2 Trigger input
FTM2_SYNC[TRIG1]
—
FTM2
FTMSYNC
to
FTM2 Trigger2
FTM2 Trigger input
FTM2_SYNC[TRIG2]
—
ACMP0
CMP0_OUT
to
FTM2 Fault0
FTM2 fault input
FTM2_FLTCTRL[FAULT0EN]
—
External pin
EXTRG_IN
to
FTM2 Fault1
FTM2 fault input
FTM2_FLTCTRL[FAULT1EN]
PTA6
External pin
EXTRG_IN
to
FTM2 Fault2
FTM2 fault input
FTM2_FLTCTRL[FAULT2EN]
PTA7
ACIC
RTCC
ch0
FTM1
ovf
ADC trg
UART0
ovf
01
PITch0
10
11
FTM0
+
ch1
RTC
00
RXDFE
ACMP0
1
-
0
rxd
UART0_RX
txd
0
1
ch0
ch1
1
FTM0_CH1
0
0
ovf
BUS CLK
ADHWT
DELAY
1
2N
BUSREF
1
inittrg
fault0
matchtrg fault1
fault2
FTM2 fault3
trigger0
trigger1
trigger2
FTMSYNC
UART0_TX
FTM2_FLT1
FTM2_FLT2
RXDCE
TXDME
CLKOE
BUSOUT
Figure 3-1. System interconnection diagram
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Chapter 3 Chip Configuration
3.2.2 Analog reference options
Several analog blocks have selectable reference voltages as shown in Table 3-2. These
options allow analog peripherals to share or have separate analog references. Care must
be taken when selecting analog references to avoid cross talk noise.
Table 3-2. Analog reference options
Module
12-bit ADC
ACMP0
ACMP1
Reference option
Comment/ reference selection
• VREFH
• VREFL
VREFH is internally connected to VDDA, VREFL has a dedicated pin.
• VDDA
• Bandgap
Selected by ACMP0_C1[DACREF] or ACMP1_C1[DACREF]
3.2.3 ACMP0 output capture
When SIM_SOPT[ACIC] is set, the output of ACMP0 is connected to FTM1 input
channel0, and could be captured by FTM1 timer. The FTM1_CH0 pin is released to other
shared function.
3.2.4 UART0_TX modulation
UART0_TX can be modulated by FTM0 channel 0 output. When SIM_SOPT[TXDME]
is set, the UART0_TX is gated by FTM0 channel0 output through an AND gate, and then
mapped to UART0_TX pinout. When this field is clear, the UART0_TX is directly
mapped on the pinout. To enable IR modulation function, both FTM0_CH0 and UART
must be active. The FTM0_CNT and FTM0_MOD registers specify the period of the
PWM, and the FTM0_C0V register specifies the duty cycle of the PWM. Then, when
SIM_SOPT[TXDME] is enabled, each data transmitted via UART0_TX from UART0 is
modulated by the FTM0 channel 0 output, and the FTM0_CH0 pin is released to other
shared functions.
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Module to Module Interconnects
UART0
TX
0
UART0_TX
1
FTM0_CH0
PORT LOGIC
TXDME
Figure 3-2. IR modulation diagram
3.2.5 UART0_RX capture
UART0_RX pin is selectable connected to UART0 module directly or tagged to FTM0
channel 1. When SIM_SOPT[RXDCE] is set, the UART0_RX pin is connected to both
UART0 and FTM0 channel 1, and the FTM0_CH1 pin is released to other shared
functions. When this field is clear, the UART0_RX pin is connected to UART0 only.
UART0
FTM0_CH1
RX
UART0_RX
1
0
FTM0_CH1
RXDCE
Figure 3-3. UART0_RX capture function diagram
3.2.6 UART0_RX filter
When SIM_SOPT[RXDFE] is clear, the UART0_RX pin is connected to UART0 module
directly. When this field is correctly set, the ACMP0 output can be connected to the
receive channel of UART0. To enable UART0_RX filter function, both UART0 and
ACMP0 must be active. If this function is active, the UART0 external UART0_RX pin is
released to other shared functions regardless of the configuration of UART0 pin
reassignment. When UART0_RX capture function is active, the ACMP0 output is
injected to FTM0 channel 1 as well.
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Chapter 3 Chip Configuration
RX
UART0
0
1
UART0_RX
ACMP0
+
To UART0_RX
Capture Function
RXDFE
From Internal or External
Reference Voltage
Figure 3-4. IR demodulation diagram
3.2.7 RTC capture
RTC overflow may be captured by FTM1 channel 1 by setting SIM_SOPT[RTCC].
When this field is set, the RTC overflow is connected to FTM1 channel 1 for capture, and
the FTM1_CH1 pin is released to other shared functions.
3.2.8 FTM2 software synchronization
FTM2 contains three synchronization input triggers, one of which is a software trigger by
writing 1 to SIM_SOPT[FTMSYNC]. Writing 0 to this field takes no effect. This field is
always read 0.
3.2.9 ADC hardware trigger
ADC module may initiate a conversion via a hardware trigger. The following table shows
the available ADC hardware trigger sources by setting SIM_SOPT[ADHWT].
Table 3-3. ADC hardware trigger setting
ADHWT
ADC hardware trigger
00
RTC overflow
01
PIT ch0 overflow
10
FTM2 init trigger with 8-bit programmable delay
11
FTM2 match trigger with 8-bit programmable delay
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Core Modules
When ADC hardware trigger selects the output of FTM2 triggers, an 8-bit delay block
will be enabled. This logic delays any trigger from FTM2 with an 8-bit counter whose
value is specified by SIM_SOPT[DELAY]. The reference clock to this module is the bus
clock with selectable predivider specified by SIM_SOPT[BUSREF].
3.3 Core Modules
3.3.1 ARM Cortex-M0+ core configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at arm.com.
Debug
Crossbar
switch
Interrupts
ARM Cortex-M0+
Core
Figure 3-5. Core configuration
Table 3-4. Reference links to related information
Topic
Related module
Reference
Full description
ARM Cortex-M0+ core,
r0p0
ARM Cortex-M0+ Technical Reference Manual, r0p0
System memory map
System memory map
Clocking
Clock distribution
Power management
Power management
System/instruction/data
bus module
Crossbar switch
Crossbar switch
Debug
Serial Wire Debug
(SWD)
Debug
Interrupts
Nested Vectored
Interrupt Controller
(NVIC)
NVIC
Miscellaneous Control
Module (MCM)
MCM
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Chapter 3 Chip Configuration
3.3.1.1 ARM Cortex M0+ core
The ARM Cortex M0+ parameter settings are as follows:
Table 3-5. ARM Cortex-M0+ parameter settings
Parameter
Verilog name
Value
Description
Arch Clock Gating
ACG
1 = Present
DAP Slave Port
Support
AHBSLV
1
DAP ROM Table Base
BASEADDR
0xF000_2003
Endianess
BE
0
Little endian control for data transfers
Breakpoints
BKPT
2
Implements 2 breakpoints
Debug Support
DBG
1 = Present
—
Halt Event Support
HALTEV
1 = Present
—
I/O Port
IOP
1 = Present
Implements single-cycle ld/st accesses to special
addr space
IRQ Mask Enable
IRQDIS
0x0
—
Debug Port Protocol
JTAGnSW
0 = SWD
Core Memory
Protection
MPU
0 = Absent
Number of IRQs
NUMIRQ
32
Reset all regs
RAR
0 = Standard
Do not force all registers to be async reset
Multiplier
SMUL
0 = Fast Mul
Implements single-cycle multiplier
Multi-drop Support
SWMD
0 = Absent
Do not include serial wire support for multi-drop
System Tick Timer
SYST
1 = Present
Implements system tick timer (for CM4
compatibility)
DAP Target ID
TARGETID
0
Implements architectural clock gating
Supports any AHB debug access port (like the
CM4 DAP)
Base address for DAP ROM table
SWD protocol, not JTAG
No MPU
Assume full NVIC request vector
—
User/Privileged
USER
1 = Present
Implements processor operating modes
Vector Table Offset
Register
VTOR
1 = Present
Implements relocation of exception vector table
WIC Support
WIC
1 = Present
Implements WIC interface
WIC Requests
WICLINES
34
Exact number of wakeup IRQs is 34
Watchpoints
WPT
2
Implements 2 watchpoints
For details on the ARM Cortex-M0+ processor core see the ARM website: arm.com.
3.3.1.2 Buses, interconnects, and interfaces
The ARM Cortex-M0+ core has two bus interfaces:
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Core Modules
• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to
peripherals and all system memory, which includes flash and RAM.
• Single 32-bit I/O port bus (IOPORT) interfacing to the FGPIO with 1-cycle loads
and stores.
3.3.1.3 System Tick Timer
The CLKSOURCE field in SysTick Control and Status register selects either the core
clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS
field in the SysTick Calibration Value Register is always zero.
3.3.1.4 Core privilege levels
The core on this device is implemented with both privileged and unprivileged levels. The
ARM documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term...
it also means this term...
Privileged
Supervisor
Unprivileged or user
User
3.3.1.5 Caches
This device does not have processor related cache memories, but the flash controller has
an internal 32-byte cache for flash access.
3.3.2 Nested Vectored Interrupt Controller (NVIC) configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at arm.com.
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Chapter 3 Chip Configuration
ARM Cortex-M0+
core
Interrupts
Module
Nested Vectored
Interrupt Controller
(NVIC)
PPB
Module
Module
Figure 3-6. NVIC configuration
Table 3-6. Reference links to related information
Topic
Related module
Reference
Full description
Nested Vectored
Interrupt Controller
(NVIC)
ARM Cortex-M0+ Technical Reference Manual
System memory map
—
System memory map
Clocking
—
Clock distribution
Power management
Power management
Private Peripheral Bus
(PPB)
ARM Cortex-M0+ core
ARM Cortex-M0+ core
3.3.2.1 Interrupt priority levels
This device supports four priority levels for interrupts. Therefore in the NVIC, each
source in the IPR registers contains two bits. For example, IPR0 is shown below:
31
R
W
30
IRQ3
29
28
27
26
25
24
0
0
0
0
0
0
23
22
IRQ2
21
20
19
18
17
16
0
0
0
0
0
0
15
14
IRQ1
13
12
11
10
9
8
0
0
0
0
0
0
7
6
IRQ0
5
4
3
2
1
0
0
0
0
0
0
0
3.3.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin, which the NMI signal is multiplexed on, must be configured for the NMI
function to generate the non-maskable interrupt request.
3.3.2.3 Interrupt channel assignments
The interrupt vector assignments are defined in the following table.
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Core Modules
• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
Table 3-8. Interrupt vector assignments
Address
IRQ1
Vector
NVIC
IPR
register
number2
Source module
Source description
ARM Core System Handler Vectors
0x0000_0000
0
—
—
ARM core
Initial Stack Pointer
0x0000_0004
1
—
—
ARM core
Initial Program Counter
0x0000_0008
2
—
—
ARM core
Non-maskable Interrupt (NMI)
0x0000_000C
3
—
—
ARM core
Hard Fault
0x0000_0010
4
—
—
—
—
0x0000_0014
5
—
—
—
—
0x0000_0018
6
—
—
—
—
0x0000_001C
7
—
—
—
—
0x0000_0020
8
—
—
—
—
0x0000_0024
9
—
—
—
—
0x0000_0028
10
—
—
—
—
0x0000_002C
11
—
—
ARM core
Supervisor call (SVCall)
0x0000_0030
12
—
—
—
—
0x0000_0034
13
—
—
—
—
0x0000_0038
14
—
—
ARM core
Pendable request for system service
(PendableSrvReq)
0x0000_003C
15
—
—
ARM core
System tick timer (SysTick)
0x0000_0040
16
0
0
—
—
0x0000_0044
17
1
0
—
—
0x0000_0048
18
2
0
—
—
0x0000_004C
19
3
0
—
—
0x0000_0050
20
4
1
—
—
0x0000_0054
21
5
1
FTMRH
Command complete and error interrupt
0x0000_0058
22
6
1
PMC
Low-voltage warning
0x0000_005C
23
7
1
IRQ
External interrupt
Single interrupt vector for all sources
Non-Core Vectors
0x0000_0060
24
8
2
I2C0
0x0000_0064
25
9
2
—
—
0x0000_0068
26
10
2
SPI0
Single interrupt vector for all sources
0x0000_006C
27
11
2
SPI1
Single interrupt vector for all sources
0x0000_0070
28
12
3
UART0
Status and error
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-8. Interrupt vector assignments (continued)
Address
IRQ1
Vector
0x0000_0074
29
13
NVIC
IPR
register
number2
Source module
Source description
3
UART1
Status and error
Status and error
0x0000_0078
30
14
3
UART23
0x0000_007C
31
15
3
ADC0
ADC conversion complete interrupt
0x0000_0080
32
16
4
ACMP0
Analog comparator 0 interrupt
0x0000_0084
33
17
4
FTM0
Single interrupt vector for all sources
0x0000_0088
34
18
4
FTM1
Single interrupt vector for all sources
0x0000_008C
35
19
4
FTM2
Single interrupt vector for all sources
0x0000_0090
36
20
5
RTC
RTC overflow
0x0000_0094
37
21
5
ACMP1
Analog comparator 1 interrupt
0x0000_0098
38
22
5
PIT_CH0
PIT CH0 overflow
0x0000_009C
39
23
5
PIT_CH1
PIT CH1 overflow
0x0000_00A0
40
24
6
KBI0
Keyboard interrupt0
0x0000_00A4
41
25
6
KBI1
Keyboard interrupt1
0x0000_00A8
42
26
6
—
0x0000_00AC
43
27
6
ICS
Clock loss of lock
0x0000_00B0
44
28
7
WDOG
Watchdog timeout
0x0000_00B4
45
29
7
—
0x0000_00B8
46
30
7
—
0x0000_00BC
47
31
7
—
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4
3. 32-pin LQFP and QFN packages do not have this module.
3.3.2.3.1
Determining the field and register location for configuring a
particular interrupt
Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the
SPI0 row from Interrupt priority levels.
Table 3-9. Interrupt vector assignments
Address
0x0000_0068
IRQ1
Vector
26
10
NVIC IPR
register
number2
2
Source module
SPI0
Source description
Single interrupt vector for all sources
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4.
• The NVIC registers you would use to configure the interrupt are:
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Core Modules
• NVICIPR2
• To determine the particular IRQ's field location within these particular registers:
• NVICIPR2 field starting location = 8 * (IRQ mod 4) + 6 = 22
Since the NVICIPR fields are 2-bit wide (4 priority levels), the NVICIPR2 field
range is bits 22–23.
Therefore, the field locations NVICIPR2[23:22] are used to configure the SPI0 interrupts.
3.3.3 Asynchronous wakeup interrupt controller (AWIC)
configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at arm.com.
Nested vectored
interrupt controller
(NVIC)
Clock logic
Wake-up
requests
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Module
Module
Figure 3-7. Asynchronous wake-up interrupt controller configuration
Table 3-10. Reference links to related information
Topic
Related module
Reference
System memory map
System memory map
Clocking
Clock distribution
Power management
Power management
Interrupt control
Wake-up requests
Nested vectored
interrupt controller
(NVIC)
NVIC
AWIC wake-up sources
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Chapter 3 Chip Configuration
3.3.3.1 Wakeup sources
The device uses the following internal and external inputs to the AWIC module.
Table 3-11. AWIC stop wakeup sources
Wake-up source
Description
Available system resets
RESET pin when LPO is its clock source
Low-voltage warning
Power management controller
IRQ
IRQ pin
Pin interrupts
KBI - Any enabled pin interrupt is capable of waking the system.
ADC
The ADC is functional in Stop mode when using internal clock source.
ACMP
Interrupt in normal
I2C
Address match wake-up
SPI
SPI slave mode interrupt
UART
UART active edge detect at UART_RX pin
RTC
Alarm interrupt
Non-maskable interrupt
NMI pin
3.4 System Modules
3.4.1 SIM configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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System Modules
Peripheral
bridge
Register
access
System integration
module (SIM)
Figure 3-8. SIM configuration
Table 3-12. Reference links to related information
Topic
Related module
Reference
Full description
SIM
SIM
System memory map
—
System memory map
Clocking
—
Clock distribution
Power management
—
Power management
3.4.2 PMC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge
Register access
Power Management
Controller (PMC)
Figure 3-9. PMC configuration
Table 3-13. Reference links to related information
Topic
Related module
Reference
Full description
PMC
PMC
System memory map
—
System memory map
Clocking
—
Clock distribution
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Chapter 3 Chip Configuration
3.4.3 MCM configuration
ARM Cortex-M0+
core
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Transfers
Miscellaneous
Control Module
(MCM)
Figure 3-10. MCM configuration
Table 3-14. Reference links to related information
Topic
Related module
Reference
Full description
Miscellaneous Control
module (MCM)
MCM
System memory map
—
System memory map
Clocking
—
Clock distribution
Power management
—
Power management
Private Peripheral Bus
(PPB)
ARM Cortex-M0+ core
ARM Cortex-M0+ core
Transfer
Flash memory
controller
Flash memory controller
3.4.4 Crossbar-light switch configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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System Modules
GPIO
controller
Crossbar Switch
M0
S0
Flash
controller
IOPORT
S1
SRAML
S2
BME
SRAMU
Master Modules
Peripheral
bridge
Peripherals
Slave Modules
Figure 3-11. Crossbar-Light switch integration
Table 3-15. Reference links to related information
Topic
Related module
Reference
System memory map
—
System memory map
Clocking
—
Clock Distribution
Crossbar switch master ARM Cortex-M0+ core
ARM Cortex-M0+ core
Crossbar switch slave
Flash memory
controller
Flash memory controller
Crossbar switch slave
SRAM controller
SRAM configuration
Crossbar switch slave
Peripheral bridge
Peripheral bridge
2-ported peripheral
GPIO controller
GPIO controller
3.4.4.1 Crossbar-Light switch master assignments
The masters connected to the crossbar switch are assigned as follows:
Master module
ARM core unified bus
Master port number
0
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Chapter 3 Chip Configuration
3.4.4.2 Crossbar switch slave assignments
This device contains 3 slaves connected to the crossbar switch.
The slave assignment is as follows:
Slave module
Slave port number
Flash memory controller
0
SRAM controller
1
Peripheral bridge
2
3.4.5 Peripheral bridge configuration
Transfers
AIPS-Lite
peripheral bridge
Transfers
Peripherals
Crossbar switch
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-12. Peripheral bridge configuration
Table 3-16. Reference links to related information
Topic
Related module
Reference
Full description
Peripheral bridge
(AIPS-Lite)
Peripheral bridge (AIPS-Lite)
System memory map
—
System memory map
Clocking
—
Clock distribution
3.4.5.1 Number of peripheral bridges
This device contains one peripheral bridge.
3.4.5.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this
device. See AIPS-Lite Memory Map for the memory slot assignment for each module.
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System Security
3.5 System Security
3.5.1 CRC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge
Register
access
CRC
Figure 3-13. CRC configuration
Table 3-17. Reference links to related information
Topic
Related module
Reference
Full description
CRC
CRC
System memory map
—
System memory map
Power management
—
Power management
3.5.2 Watchdog configuration
This section summarizes how the module has been configured in the chip.
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Chapter 3 Chip Configuration
Peripheral
bridge
System integration
module
Register
access
WDOG
Figure 3-14. Watchdog configuration
Table 3-18. Reference links to related information
Topic
Related module
Reference
Full description
Watchdog (WDOG)
Watchdog (WDOG)
Clocking
—
Clock distribution
Power management
—
Power management
Programming model
System Integration
Module (SIM)
SIM
3.5.2.1 WDOG clocks
The watchdog has four selectable clock sources:
• 1 kHz internal low power oscillator (LPOCLK)
• Internal 32 kHz reference clock (ICSIRCLK)
• External clock (OSCERCLK)
• Bus clock
3.5.2.2 WDOG operation
The WDOG module provides a fail-safe mechanism to ensure the system can be reset to a
known state of operation in case of system failure, such as the CPU clock stopping or
there being a run away condition in the software code. The watchdog counter runs
continuously off a selectable clock source and expects to be serviced (refreshed)
periodically. If it is not, it resets the system.
After any reset, the WDOG watchdog is enabled. If the WDOG watchdog is not used in
an application, it can be disabled by clearing WDOG_CS1[EN].
The refresh write sequence is a write of 0xA602 followed by a write of 0xB480 to the
WDOG_CNTH:L registers. The write of the 0xB480 must occur within 16 bus clocks
after the write of 0xA602; otherwise, the watchdog resets the MCU.
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Clock Modules
The watchdog counter has four clock source options selected by programming
WDOG_CS2[CLK]. The clock source options are the bus clock, internal 1 kHz clock,
external clock, or an internal 32 kHz clock source.
The refresh timeout time is defined by WDOG_TOVALH:L. In addition, if window
mode is used, software must not start the refresh sequence until after the time value set in
the WDOG_WINH:L registers.
An optional fixed prescaler for all clock sources allows for longer timeout periods. When
WDOG_CS2[PRES] is set, the clock source is prescaled by 256 before clocking the
watchdog counter.
The watchdog counter registers CNTH:L provide access to the value of the free-running
watchdog counter. The software can read the counter registers at any time but cannot
write directly to the watchdog counter. The refresh sequence resets the watchdog counter
to 0x0000. Write to the WDOG_CNTH:L registers of 0xC520 followed by 0xD928
within 16 bus clocks start the unlock sequence. On completing the unlock sequence, the
user must reconfigure the watchdog within 128 bus clocks; otherwise, the watchdog
forces a reset to the MCU.
By default, the watchdog is not functional in Debug mode, Wait mode, or Stop mode.
Setting WDOG_CS1[DBG], WDOG_CS1[WAIT] or WDOG_CS1[STOP] can activate
the watchdog in Debug, Wait or Stop modes.
3.6 Clock Modules
3.6.1 ICS configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration
Peripheral
bridge
System integration
module (SIM)
System
oscillator
Register
access
ICS
Figure 3-15. ICS configuration
Table 3-19. Reference links to related information
Topic
Related module
Reference
Full description
ICS
ICS
System memory map
—
System memory map
Clocking
—
Clock distribution
Power management
—
Power management
3.6.1.1 Clock gating
This family of devices includes clock gating control for each peripheral, that is, the clock
to each peripheral can explicitly be gated on or off, using clock-gate control bits in the
SIM_SCGC register.
3.6.2 OSC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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Memories and Memory Interfaces
Peripheral
bridge
System oscillator
Module signals
Signal multiplexing
ICS
Register
access
Figure 3-16. OSC configuration
Table 3-20. Reference links to related information
Topic
Related module
Reference
Full description
OSC
OSC
System memory map
—
System memory map
Clocking
—
Clock distribution
Power management
—
Power management
Full description
ICS
ICS
3.7 Memories and Memory Interfaces
3.7.1 Flash memory configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration
Peripheral bus
controller 0
Flash memory
controller
Register
access
Transfers
Flash memory
Figure 3-17. Flash memory configuration
Table 3-21. Reference links to related information
Topic
Related module
Reference
Full description
Flash memory
Flash memory
System memory map
—
System memory map
Clocking
—
Clock Distribution
Transfers
Flash memory
controller
Flash memory controller
Register access
Peripheral bridge
Peripheral bridge
3.7.1.1 Flash and EEPROM memory sizes
The devices covered in this document contain one flash block consisting of up to 128
sectors of 512 bytes and one EEPROM block consisting of 128 sectors of 2 bytes.
The amounts of flash and EEPROM memory for the devices covered in this document
are:
Table 3-22. KE02 flash and EEPROM memory size
Device
EEPROM (B)
Flash (KB)
Block 0 (flash) address
range
MKE02Z16VLC4(R)
256
16
0x0000_0000 – 0x0000_3FFF
MKE02Z32VLC4(R)
256
32
0x0000_0000 – 0x0000_7FFF
MKE02Z64VLC4(R)
256
64
0x0000_0000 – 0x0000_FFFF
MKE02Z16VLD4(R)
256
16
0x0000_0000 – 0x0000_3FFF
MKE02Z32VLD4(R)
256
32
0x0000_0000 – 0x0000_7FFF
MKE02Z64VLD4(R)
256
64
0x0000_0000 – 0x0000_FFFF
MKE02Z32VLH4(R)
256
32
0x0000_0000 – 0x0000_7FFF
MKE02Z64VLH4(R)
256
64
0x0000_0000 – 0x0000_FFFF
MKE02Z32VQH4(R)
256
32
0x0000_0000 – 0x0000_7FFF
MKE02Z64VQH4(R)
256
64
0x0000_0000 – 0x0000_FFFF
Table continues on the next page...
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Memories and Memory Interfaces
Table 3-22. KE02 flash and EEPROM memory size (continued)
Device
EEPROM (B)
Flash (KB)
Block 0 (flash) address
range
MKE02Z16VFM4(R)
256
16
0x0000_0000 – 0x0000_3FFF
MKE02Z32VFM4(R)
256
32
0x0000_0000 – 0x0000_7FFF
MKE02Z64VFM4(R)
256
64
0x0000_0000 – 0x0000_FFFF
3.7.1.2 Flash memory map
The flash memory and the flash registers are located at different base addresses as shown
in the figure found here.
The base address for each is specified in System memory map.
Flash memory base address
Registers
Flash base address
Flash configuration field
Flash
Figure 3-18. Flash memory map
The on-chip flash memory is implemented in a portion of the allocated Flash range to
form a contiguous block in the memory map beginning at address 0x0000_0000. See
Flash and EEPROM memory sizes for details of supported ranges.
Access to the flash memory ranges outside the amount of flash on the device causes the
bus cycle to be terminated with an error followed by the appropriate response in the
requesting bus master.
3.7.1.3 Flash security
For information on how flash security is implemented on this device, see Chip Security.
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Chapter 3 Chip Configuration
3.7.1.4 Erase all flash contents
In addition to software, the entire flash memory may be erased external to the flash
memory via the SW-DP debug port by setting MDM-AP CONTROL[0] (bit 0 of the
MDM-AP Control register). MDM-AP STATUS[0] (bit 0 of the MDM-AP Status
register) is set to indicate the mass erase command has been accepted. MDM-AP
CONTROL[0] is cleared when the mass erase completes.
3.7.2 Flash memory controller configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
See Platform Control Register (MCM_PLACR) register description for details on the
reset configuration of the FMC.
Transfers
Flash memory
controller
Transfers
Flash memory
Crossbar switch
MCM
Figure 3-19. Flash memory controller configuration
Table 3-23. Reference links to related information
Topic
Related module
Reference
Full description
Flash memory
controller
Flash memory controller
System memory map
System memory map
Clocking
Clock Distribution
Transfers
Flash memory
Flash memory
Transfers
Crossbar switch
Crossbar Switch
Register access
MCM
MCM
3.7.3 SRAM configuration
This section summarizes how the module has been configured in the chip.
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Memories and Memory Interfaces
Transfers
SRAM upper
crossbar
Cortex-M0+
core
switch
SRAM
controller
SRAM lower
Figure 3-20. SRAM configuration
Table 3-24. Reference links to related information
Topic
Related module
Reference
Full description
SRAM
SRAM
System memory map
—
System memory map
Clocking
—
Clock Distribution
ARM Cortex-M0+ core
—
ARM Cortex-M0+ core
3.7.3.1 SRAM sizes
The SRAM supports single cycle access (zero wait states) at all core speeds.
The amounts of SRAM for the devices covered in this document are:
Table 3-25. SRAM size
Freescale part number
SRAM
MKE02Z16VLC4(R)
2 KB
MKE02Z32VLC4(R)
4 KB
MKE02Z64VLC4(R)
4 KB
MKE02Z16VLD4(R)
2 KB
MKE02Z32VLD4(R)
4 KB
MKE02Z64VLD4(R)
4 KB
MKE02Z32VLH4(R)
4 KB
MKE02Z64VLH4(R)
4 KB
MKE02Z32VQH4(R)
4 KB
MKE02Z64VQH4(R)
4 KB
MKE02Z16VFM4(R)
2 KB
MKE02Z32VFM4(R)
4 KB
MKE02Z64VFM4(R)
4 KB
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Chapter 3 Chip Configuration
3.7.3.2 SRAM ranges
The on-chip SRAM is split into two ranges; 1/4 is allocated to SRAM_L and 3/4 is
allocated to SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]
SRAM size * (3/4)
SRAM size *(1/4)
This is illustrated in the following figure.
0x2000_0000 – SRAM_size/4
SRAM_L
0x1FFF_FFFF
0x2000_0000
SRAM_U
0x2000_0000 + SRAM_size(3/4) - 1
Figure 3-21. SRAM blocks memory map
For example, for a device containing 4 KB of SRAM the ranges are:
• SRAM_L: 0x1FFF_FC00 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_0BFF
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Analog
3.8 Analog
3.8.1 12-bit analog-to-digital converter (ADC) configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge
Transfers
Other peripherals
Signal multiplexing
Register
access
Module signals
SAR ADC
Figure 3-22. 12-bit SAR ADC configuration
Table 3-26. Reference links to related information
Topic
Related module
Reference
Full description
12-bit SAR ADC
12-bit SAR ADC
System memory map
—
System memory map
Clocking
—
Clock distribution
Power management
—
Power management
3.8.1.1 ADC instantiation information
This device contains one 12-bit successive approximation ADC with up to 16 channels.
Table 3-27. ADC channels
Freescale part number
ADC channels
MKE02Z16VLC4(R)
12
MKE02Z32VLC4(R)
12
MKE02Z64VLC4(R)
12
MKE02Z16VLD4(R)
12
MKE02Z32VLD4(R)
12
MKE02Z64VLD4(R)
12
MKE02Z32VLH4(R)
16
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-27. ADC channels (continued)
Freescale part number
ADC channels
MKE02Z64VLH4(R)
16
MKE02Z32VQH4(R)
16
MKE02Z64VQH4(R)
16
MKE02Z16VFM4(R)
12
MKE02Z32VFM4(R)
12
MKE02Z64VFM4(R)
12
The ADC supports both software and hardware triggers. The ADC hardware trigger,
ADHWT, is selectable from FTM2 init trigger, FTM2 match trigger, RTC overflow, or
PITCH0 overflow. The hardware trigger can be configured to cause a hardware trigger in
MCU Run, Wait, and Stop modes.
The hardware trigger sources details are listed in the Module-to-Module section.
3.8.1.2 ADC0 connections/channel assignment
The ADC channel assignments for the device are shown in following table. Reserved
channels convert to an unknown value.
Table 3-28. ADC channel assigement
ADCH
Channel
Input
00000
AD0
PTA0/ADP0
00001
AD1
PTA1/ADP1
00010
AD2
PTA6/ADP2
00011
AD3
PTA7/ADP3
00100
AD4
PTB0/ADP4
00101
AD5
PTB1/ADP5
00110
AD6
PTB2/ADP6
00111
AD7
PTB3/ADP7
01000
AD8
PTC0/ADP8
01001
AD9
PTC1/ADP9
01010
AD10
PTC2/ADP10
01011
AD11
PTC3/ADP11
01100
AD12
PTF4/ADP12
01101
AD13
PTF5/ADP13
01110
AD14
PTF6/ADP14
01111
AD15
PTF7/ADP15
10000
AD16
Vss
Table continues on the next page...
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Analog
Table 3-28. ADC channel assigement (continued)
ADCH
Channel
Input
10001
AD17
Vss
10010
AD18
Vss
10011
AD19
Vss
10100
AD20
Reserved
10101
AD21
Reserved
10110
AD22
Temperature Sensor
10111
AD23
Bandgap
11000
AD24
Reserved
11001
AD25
Reserved
11010
AD26
Reserved
11011
AD27
Reserved
11100
AD28
Reserved
11101
AD29
VREFH
11110
AD30
VREFL
11111
Module disabled
None
3.8.1.3 ADC analog supply and reference connections
This device includes dedicated VDDA and VREFL pins.
The VREFH pin of this device is internally connected to VDDA.
The VSSA pin of this device is internally connected to VSS.
3.8.1.4 Temperature sensor and bandgap
The ADC module integrates an on-chip temperature sensor. Following actions must be
performed to use this temperature sensor.
• Configure ADC for long sample with a maximum of 1 MHz clock
• Convert the bandgap voltage reference channel (AD23)
• By converting the digital value of the bandgap voltage reference channel using
the value of VBG, the user can determine VDD.
• Convert the temperature sensor channel (AD22)
• By using the calculated value of VDD, convert the digital value of AD22 into a
voltage, VTEMP
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Chapter 3 Chip Configuration
3.8.1.5 Alternate clock
The ADC module is capable of performing conversions using the MCU bus clock, the
bus clock divided by 2, the local asynchronous clock (ADACK) within the module, or the
alternate clock, ALTCLK. The alternate clock for the devices is the external oscillator
output (OSC_OUT).
The selected clock source must run at a frequency such that the ADC conversion clock
(ADCK) runs at a frequency within its specified range (fADCK) after being divided down
from the ALTCLK input as determined by ADC_SC3[ADIV].
ALTCLK is active while the MCU is in Wait mode provided the conditions described
above are met. This allows ALTCLK to be used as the conversion clock source for the
ADC while the MCU is in Wait mode.
ALTCLK cannot be used as the ADC conversion clock source while the MCU is in Stop
mode.
3.8.2 ACMP configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge 0
Other peripherals
ACMP
Module signals
Signal multiplexing
Register
access
Figure 3-23. ACMP configuration
Table 3-29. Reference links to related information
Topic
Related module
Reference
Full description
Analog comparator
(ACMP)
Comparator
System memory map
—
System memory map
Clocking
—
Clock distribution
Power management
—
Power management
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Analog
3.8.2.1 ACMP overview
The device contains two analog comparator modules (ACMP) which provide a circuit for
comparing two analog input voltages or for comparing one analog input voltage to an
internal reference voltage. The comparator circuit is used to operate across the full range
of the supply voltage (rail-to-rail operation).
The ACMP features four different inputs muxed with both positive and negative inputs to
the ACMP. One is fixed connected to built-in DAC output, the others are externally
mapped on pinouts.
The ACMP modules support internal bandgap reference voltage. When using the
bandgap reference, the user must enable the PMC bandgap buffer first.
The ACMP modules can continue to operate in Wait and Stop mode if enabled, and can
wake the MCU when a compare event occurs.
3.8.2.2 ACMP interconnections
The ACMP0 output can be configured to connect with FTM1 input capture channel 0 by
setting SIM_SOPT[ACIC]. With ACIC field asserted, the FTM1_CH0 pin is not
available externally regardless of the configuration of the FTM1 module for channel 0.
ACMP0 output can be directly ejected to UART0_RX by setting SIM_SOPT[RXDCE].
In this mode, UART0_RX pinout does not work. Any external signal tagged to ACMP0
inputs can be regarded as input pins.
The following table shows the input connections to the ACMP0 and ACMP1:
Table 3-30. ACMP0 input connections
ACMP0 channel
Connection
0
PTA0/ACMP0_IN0
1
PTA1/ACMP0_IN1
2
PTC4/ACMP0_IN2
3
DAC output
Table 3-31. ACMP1 input connections
ACMP1 channel
Connection
0
PTA6/ACMP1_IN0
1
PTA7/ACMP1_IN1
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-31. ACMP1 input connections (continued)
ACMP1 channel
Connection
2
PTB4/ACMP1_IN2
3
DAC output
3.8.2.3 ACMP in Stop mode
ACMP continues to operate in Stop mode if enabled. If ACMPx_SC[ACOPE] is enabled,
comparator output will operate as in the normal operating mode and will control
ACMPx_OUT pin. The MCU is brought out of Stop mode when a compare event occurs
and ACMPx_CS[ACIE] is enabled; ACMPx_CS[ACF] flag sets accordingly.
3.9 Timers
3.9.1 FlexTimer configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bus
controller 0
Transfers
Other peripherals
FlexTimer
Module signals
Signal multiplexing
Register
access
Figure 3-24. FlexTimer configuration
Table 3-32. Reference links to related information
Topic
Related module
Reference
Full description
FlexTimer
FlexTimer
System memory map
—
System memory map
Clocking
—
Clock distribution
Power management
—
Power management
Signal multiplexing
Port control
Signal multiplexing
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Timers
3.9.1.1 FTM overview
The FTM timer contains up to six channels which support input capture, output compare
and the generation of PWM signals to control electric motor and power management
applications. FTM time reference is a 16-bit counter which can be used as an unsigned or
signed counter.
This device contains up to three FTM modules of one 6-channel FTM with full functions
and two 2-channel FTM with basic TPM functions. Each FTM module can use
independent external clock input. The table below summarizes the configuration of FTM
modules.
Table 3-33. FTM modules features
Feature
FTM0/FTM1
FTM2
Number of channels
2
6
Initial counting value
no
yes
Periodic TOF
no
yes
Input capture mode
yes
yes
Channel input filter
no
channels 0, 1, 2 and 3
Output compare mode
yes
yes
Edge-Aligned PWM (EPWM)
yes
yes
Center-Aligned PWM (CPWM)
yes
yes
Combine mode
no
yes
Complementary mode
no
yes
PWM synchronization
no
yes
Inverting
no
yes
Software output control (SWOC)
no
yes
Deadtime insertion
no
yes
Output mask
no
yes
Fault control
no
yes
Number of fault inputs
0
3
Fault input filter
no
fault inputs 0, 1 and 2
Polarity control
no
yes
Initialization
no
yes
Channel match trigger
no
yes
Initialization trigger
no
yes
Capture test mode
no
yes
DMA
no
no
Dual edge capture mode
no
yes
Quadrature decoder mode
no
no
Quadrature decoder input filter
no
no
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-33. FTM modules features (continued)
Feature
Debug modes
Intermediary load
Global time base
enable1
Registers available
FTM0/FTM1
FTM2
no
yes
no
yes
no
yes
FTM_SC, FTM_CNT,
FTM_SC, FTM_CNT, FTM_MOD, FTM_C0SC,
FTM_MOD,
FTM_C0V, FTM_C1SC, and FTM_C1V,
FTM_C0SC, FTM_C0V, FTM_C2SC, FTM_C2V, FTM_C3SC, FTM_C3V,
FTM_C1SC, and
FTM_C4SC, FTM_C4V, FTM_C5SC, FTM_C5V,
FTM_C1V,
FTM_CNTIN, FTM_STATUS, FTM_MODE,
FTM_EXTTRIG
FTM_SYNC, FTM_OUTINIT, FTM_OUTMASK,
FTM_COMBINE, FTM_DEADTIME,
FTM_EXTTRIG, FTM_POL, FTM_FMS,
FTM_FILTER, FTM_FLTCTRL, FTM_CONF,
FTM_FLTPOL, FTM_SYNCONF,
FTM_INVCTRL, FTM_SWOCTRL, and
FTM_PWMLOAD
1. The global time base (GTB) feature allows the synchronization of multiple FTM modules on a chip. It requires the GTB
function supported by all the related FTM modules. On this device, only one FTM module (FTM2) supports the GTB
function, so the GTB function is actually not usable.
3.9.1.2 FTM clock options
The selectable FTM source clock can be the system clock, the fixed frequency clock, or
an external clock. The selected control source is controlled by FTMx_SC[CLKS].
• When FTMx_SC[CLKS] = 00, no clock is selected (this in effect, disables the FTM
counter).
• When FTMx_SC[CLKS] = 01, the bus clock is selected.
• When FTMx_SC[CLKS] = 10, the fixed frequency clock(ICSFFCLK) is selected.
• When FTMx_SC[CLKS] = 11, the external clock is selected.
NOTE
Because the 32-pin LQFP and QFN packages have no
FTM2_CLK or FTM1_CLK, do not set FTMx_SC[CLKS]
(x=1,2) as 11.
3.9.1.3 FTM interconnections
FTM0 has following interconnections:
• UART0_TX signal can be modulated by FTM0 channel 0 PWM output.
• UART0_RX signal can be tagged by FTM0 channel 1 input capture function by
writing 1 to SIM_SOPT[RXDCE].
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Timers
FTM1 has following interconnections:
• ACMP0 output can be internally connected to FTM1 channel 0 capture input by
writing 1 to SIM_SOPT[ACIC].
• RTC overflow can be connected to FTM1 channel 1 capture input by writing 1 to
SIM_SOPT[RTCC].
FTM2 supports three PWM synchronization sources:
• Trigger0 is connected to the output of ACMP0 .
• Trigger1 is connected to FTM0 channel 0 output.
• Trigger2 is a software trigger by writing 1 to SIM_SOPT[FTMSYNC].
FTM2 supports four FTM fault sources:
•
•
•
•
Fault 0 is connected to ACMP0 output.
Fault1 is connected to PTA6.
Fault 2 is connected to PTA7.
Fault 3 is not used.
3.9.1.4 FTM interrupts
The FlexTimer has multiple sources of interrupt. However, either source can generate a
single interrupt request to the interrupt controller. When an FTM interrupt occurs, read
the FTM status registers to determine the exact interrupt source.
3.9.2 PIT configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration
Peripheral
bridge
Register
access
Periodic interrupt
timer
Figure 3-25. PIT configuration
Table 3-34. Reference links to related information
Topic
Related module
Reference
Full description
PIT
PIT
System memory map
—
System memory map
Clocking
—
Clock Distribution
Power management
—
Power management
3.9.2.1 PIT overview
The PIT module is an array of timers that can be used to raise interrupts and triggers.
This device contains one PIT module with two channels and supporting chained timer
mode.
3.9.2.2 PIT interconnections
The PIT channel 0 trigger output can be used as ADC hardware trigger by setting
SIM_SOPT[ADHWT].
3.9.3 RTC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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Timers
Peripheral
bridge
Module signals
Real-time clock
Signal multiplexing
Register
access
Figure 3-26. RTC configuration
Table 3-35. Reference links to related information
Topic
Related module
Reference
Full description
RTC
RTC
System memory map
—
System memory map
Clocking
—
Clock Distribution
Power management
—
Power management
3.9.3.1 RTC overview
The real-time counter (RTC) used on this device consists of one 16-bit counter, one 16bit comparator, several binary-based and decimal-based prescaler dividers, four clock
sources, and one programmable periodic interrupt. This module can be used for time-ofday, calendar or any task scheduling functions. It can also serve as a cyclic wake-up from
low-power modes without external components.
3.9.3.2 RTC interconnections
Four software selectable clock sources are available for input to prescaler with selectable
binary-based and decimal-based divider values
•
•
•
•
1 kHz internal low-power oscillator (LPOCLK)
External clock (OSCERCLK)
32 kHz internal reference clock (ICSIRCLK)
Bus clock
RTC overflow trigger can be used as hardware trigger for ADC by configuring
SIM_SOPT[ADHWT] and may also be captured by FTM1 channel1 by configuring the
SIM_SOPT[RTCC].
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Chapter 3 Chip Configuration
3.10 Communication interfaces
3.10.1 SPI configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge
Register
access
SPI
Module signals
Signal
multiplexing
Figure 3-27. SPI configuration
Table 3-36. Reference links to related information
Topic
Related module
Reference
Full description
SPI
SPI
System memory map
—
System memory map
Clocking
—
Clock Distribution
3.10.1.1 SPI overview
This device contains two SPI modules that support 8-bit data length.
The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial
communication between the MCU and peripheral devices. These peripheral devices can
include other microcontrollers, analog-to-digital converters, shift registers, sensors,
memories, etc.
The SPI runs at a baud rate up to the bus clock divided by two in master mode and up to
the bus clock divided by 4 in slave mode. Software can poll the status flags, or SPI
operation can be interrupt-driven.
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Communication interfaces
3.10.2 I2C configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge
I2 C
Module signals
Signal multiplexing
Register
access
Figure 3-28. I2C configuration
Table 3-37. Reference links to related information
Topic
Related module
Reference
Full description
I2C
I2C
System memory map
—
System memory map
Clocking
—
Clock Distribution
Power management
—
Power management
3.10.2.1 I2C overview
This device contains an inter-integrated circuit (I2C) module providing a method of
communication between a number of devices. The interface is designed to operate up to
100 kbit/s with maximum bus loading and timing. The device is capable of operating at
higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are
limited by a maximum bus capacitance of 400 pF.
3.10.3 UART configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration
Peripheral
bridge
Module signals
UART
Signal multiplexing
Register
access
Figure 3-29. UART configuration
Table 3-38. Reference links to related information
Topic
Related module
Reference
Full description
UART
UART
System memory map
—
System memory map
Clocking
—
Clock Distribution
Power management
—
Power management
3.10.3.1 UART overview
This device includes up to three universal asynchronous receiver/transmitter (UART)
modules. The 32-pin LQFP and QFN packages have two UART modules and all the
other packages have three UART modules. Typically, these systems are used to connect
to the RS232 serial input/output port of a personal computer or workstation. They can
also be used to communicate with other embedded controllers.
A flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard
baud rates beyond 115.2 kbaud. Transmit and receive within the same UART use a
common baud rate, and each UART module has a separate baud rate generator.
This UART system offers many advanced features not commonly found on other
asynchronous serial I/O peripherals on other embedded controllers. The receiver employs
an advanced data sampling technique that ensures reliable communication and noise
detection. Hardware parity, receiver wakeup, and double buffering on transmit and
receive are also included.
3.10.3.2 UART interconnection
UART0 can implement infrared functions through following tricks:
UART0_TX Modulation:
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Human-machine interfaces (HMI)
• UART0_TX output can be modulated by FTM0 channel 0 PWM output.
UART0_RX Tag:
• UART0_RX input can be tagged to FTM0 channel 1 or filtered by ACMP0 module
3.11 Human-machine interfaces (HMI)
3.11.1 GPIO configuration
Peripheral
bridge
Register access
Module signals
GPIO controller
Signal multiplexing
ARM Cortex -M0+
Core
Register
access
Figure 3-30. GPIO configuration
Table 3-39. Reference links to related information
Topic
Related module
Reference
Full description
GPIO
GPIO
System memory map
—
System memory map
Clocking
—
Clock Distribution
Power management
—
Power management
Crossbar switch
Crossbar switch
Crossbar switch
3.11.1.1 GPIO overview
The GPIO is multi-ported and can be accessed directly by the core with zero wait states at
base address 0xF800_0000 (FGPIO). It can also be accessed by the core through the
crossbar/AIPS interface at 0x400F_F000 and at an aliased slot (15) at address
0x4000_F000. All BME operations to the GPIO space can be accomplished referencing
the aliased slot (15) at address 0x4000_F000. Only some of the BME operations can be
accomplished referencing GPIO at address 0x400F_F000.
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Chapter 3 Chip Configuration
3.11.2 KBI configuration
Peripheral
bridge
Register access
Module signals
KBI
Signal multiplexing
ARM Cortex -M0+
Core
Register
access
Figure 3-31. KBI configuration
Table 3-40. Reference links to related information
Topic
Related module
Reference
Full description
KBI
KBI
System memory map
—
System memory map
Clocking
—
Clock Distribution
Power management
—
Power management
Crossbar switch
Crossbar switch
Crossbar switch
3.11.2.1 KBI overview
This device has two keyboard interrupt modules (KBI) with up to 16 keyboard interrupt
inputs grouped in two KBI modules available depending on package.
3.11.2.2 KBI assignments
The KBI port assignments is shown by the following table.
NOTE
32-pin LQFP and QFN packages have no KBI1_P4 to
KBI1_P7.
Table 3-41. KBI port assignment
KBI
Port pin
KBI
Port pin
KBI0_P0
PTA0
KBI1_P0
PTD0
KBI0_P1
PTA1
KBI1_P1
PTD1
Table continues on the next page...
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Human-machine interfaces (HMI)
Table 3-41. KBI port assignment (continued)
KBI
Port pin
KBI
Port pin
KBI0_P2
PTA2
KBI1_P2
PTD2
KBI0_P3
PTA3
KBI1_P3
PTD3
KBI0_P4
PTB0
KBI1_P4
PTD4
KBI0_P5
PTB1
KBI1_P5
PTD5
KBI0_P6
PTB2
KBI1_P6
PTD6
KBI0_P7
PTB3
KBI1_P7
PTD7
3.11.3 IRQ configuration
Peripheral
bridge
Register access
Module signals
IRQ
Signal multiplexing
ARM Cortex -M0+
Core
Register
access
Figure 3-32. IRQ configuration
Table 3-42. Reference links to related information
Topic
Related module
Reference
Full description
IRQ
IRQ
System memory map
—
System memory map
Clocking
—
Clock Distribution
Power management
—
Power management
Crossbar switch
Crossbar switch
Crossbar switch
3.11.3.1 IRQ assignment
The IRQ is assigned to pin PTA5 by default .
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Chapter 4
Memory Map
4.1 Introduction
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. This chapter describes the memory and peripheral
locations within that memory space.
4.2 System memory map
The following table shows the high-level device memory map.
Table 4-1. System memory map
System 32-bit address range
0x0000_0000–0x07FF_FFFF1
Destination slave
Program flash and read-only data
Access
Cortex-M0+ core
(Includes exception vectors in first 196 bytes)
0x0800_0000–0x0FFF_FFFF
Reserved
—
0x1000_0000–0x1000_00FF2
EEPROM
Cortex-M0+ core
0x1000_0100–0x1FFF_FBFF
Reserved
—
0x1FFF_FC00–0x1FFF_FFFF3
SRAM_L: Lower SRAM
Cortex-M0+ core
0x2000_0000–0x2000_0BFF
SRAM_U: Upper SRAM
Cortex-M0+ core
0x2000_0C00–0x3FFF_FFFF
Reserved
–
0x4000_0000–0x4007_FFFF
AIPS Peripherals
Cortex-M0+ core
0x4008_0000–0x400F_EFFF
Reserved
–
0x400F_F000–0x400F_FFFF
General-purpose input/output (GPIO)
Cortex-M0+ core
0x4010_0000–0x43FF_FFFF
Reserved
–
0x4400_0000–0x5FFF_FFFF
Bit Manipulation Engine (BME) access to AIPS Peripherals for Cortex-M0+ core
slots 0–1274
0x6000_0000–0xDFFF_FFFF
Reserved
–
0xE000_0000–0xE00F_FFFF
Private Peripherals
Cortex-M0+ core
0xE010_0000–0xEFFF_FFFF
Reserved
–
Table continues on the next page...
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Bit Manipulation Engine
Table 4-1. System memory map (continued)
System 32-bit address range
Destination slave
Access
0xF000_0000–0xF000_0FFF
Reserved
–
0xF000_1000–0xF000_1FFF
Reserved
–
0xF000_2000–0xF000_2FFF
System ROM table5
Cortex-M0+ core
0xF000_3000–0xF000_3FFF
Miscellaneous Control Module (MCM)
Cortex-M0+ core
0xF000_4000–0xF7FF_FFFF
Reserved
–
0xF800_0000–0xFFFF_FFFF
IOPORT: FGPIO (single cycle fast GPIO)
Cortex-M0+ core
1. The program flash always begins at 0x0000_0000 but the end of implemented flash varies depending on the amount of
flash implemented for a particular device. See Flash and EEPROM memory sizes for details.
2. The EEPROM supports only byte access.
3. This range varies depending on SRAM sizes. See SRAM sizes for details.
4. Includes BME operations to GPIO at slot 15 (based at 0x4000_F000).
5. This device implements a system ROM table which is used to redirect to ARM Cortex M0+ (Flycatcher) ROM table in
CoreSight debug system. See System ROM memory map for details.
4.3 Bit Manipulation Engine
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modifywrite memory operations to the peripheral address space. By combining the basic load
and store instruction support in the Cortex-M instruction set architecture with the concept
of decorated storage provided by the BME, the resulting implementation provides a
robust and efficient read-modify-write capability to this class of ultra low-end
microcontrollers. See Bit Manipulation Engine (BME) for a detailed description of its
functionality.
4.4 System ROM memory map
The system ROM table is optionally required by ARM CoreSight debug infrastructure to
discover the components on the chip.
For core configurations like that supported by Cortex-M0+, ARM recommends that a
debugger identifies and connects to the debug components using the CoreSight debug
infrastructure.
ARM recommends that a debugger follows the flow as shown in the following figure to
discover the components in the CoreSight debug infrastructure. In this case, a debugger
reads the peripheral and component ID registers for each CoreSight component in the
CoreSight system.
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Chapter 4 Memory Map
CoreSight access port
Base pointer
Redirection from the
+ System ROM table, if implemented
+
Flycatcher ROM table
CoreSight ID
Pointers
System control space
+ Data watchpoint unit
+
+ Breakpoint unit
+
CoreSight ID
CoreSight ID
CoreSight ID
Flycatcher CPUID
Watchpoint control
Breakpoint control
Debug control
+ Optional component
+
Figure 4-1. CoreSight discovery process
Following table shows the Freescale system ROM table memory map. It includes the
ROM entry, peripheral ID and component ID required by ARM CoreSight debug
infrastructure.
NOTE
This device contains only standard ARM M0+ core debug
components which defined in Flycatcher ROM table. No
custom-built debug components are included.
ROM memory map
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
F000_2000
Entry (ROM_ENTRY0)
32
R
See section
4.4.1/90
F000_2004
End of Table Marker Register (ROM_TABLEMARK)
32
R
0000_0000h
4.4.2/91
F000_2FCC System Access Register (ROM_SYSACCESS)
32
R
0000_0001h
4.4.3/91
F000_2FD0 Peripheral ID Register (ROM_PERIPHID4)
32
R
See section
4.4.4/92
F000_2FD4 Peripheral ID Register (ROM_PERIPHID5)
32
R
See section
4.4.4/92
F000_2FD8 Peripheral ID Register (ROM_PERIPHID6)
32
R
See section
4.4.4/92
F000_2FDC Peripheral ID Register (ROM_PERIPHID7)
32
R
See section
4.4.4/92
F000_2FE0 Peripheral ID Register (ROM_PERIPHID0)
32
R
See section
4.4.4/92
F000_2FE4 Peripheral ID Register (ROM_PERIPHID1)
32
R
See section
4.4.4/92
F000_2FE8 Peripheral ID Register (ROM_PERIPHID2)
32
R
See section
4.4.4/92
Table continues on the next page...
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System ROM memory map
ROM memory map (continued)
Absolute
address
(hex)
Width
Access
(in bits)
Register name
Reset value
Section/
page
F000_2FEC Peripheral ID Register (ROM_PERIPHID3)
32
R
See section
4.4.4/92
F000_2FF0
Component ID Register (ROM_COMPID0)
32
R
See section
4.4.5/92
F000_2FF4
Component ID Register (ROM_COMPID1)
32
R
See section
4.4.5/92
F000_2FF8
Component ID Register (ROM_COMPID2)
32
R
See section
4.4.5/92
F000_2FFC Component ID Register (ROM_COMPID3)
32
R
See section
4.4.5/92
4.4.1 Entry (ROM_ENTRYn)
The System ROM Table begins with "n" relative 32-bit addresses, one for each debug
component present in the device and terminating with an all-zero value signaling the end
of the table at the "n+1"-th value.
It is hardwired to specific values used during the auto-discovery process by an external
debug agent.
Address: F000_2000h base + 0h offset + (4d × i), where i=0d to 0d
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENTRY
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
ROM_ENTRYn field descriptions
Field
ENTRY
Description
ENTRY
Entry 0 (CM0+ ROM Table) is hardwired to 0xF00F_D003.
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Chapter 4 Memory Map
4.4.2 End of Table Marker Register (ROM_TABLEMARK)
This register indicates end of table marker. It is hardwired to specific values used during
the auto-discovery process by an external debug agent.
Address: F000_2000h base + 4h offset = F000_2004h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MARK
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ROM_TABLEMARK field descriptions
Field
Description
MARK
Hardwired to 0x0000_0000
4.4.3 System Access Register (ROM_SYSACCESS)
This register indicates system access. It is hardwired to specific values used during the
auto-discovery process by an external debug agent.
Address: F000_2000h base + FCCh offset = F000_2FCCh
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SYSACCESS
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ROM_SYSACCESS field descriptions
Field
SYSACCESS
Description
Hardwired to 0x0000_0001
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System ROM memory map
4.4.4 Peripheral ID Register (ROM_PERIPHIDn)
These registers indicate the peripheral IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: F000_2000h base + FD0h offset + (4d × i), where i=0d to 7d
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PERIPHID
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
ROM_PERIPHIDn field descriptions
Field
Description
PERIPHID
Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.
4.4.5 Component ID Register (ROM_COMPIDn)
These registers indicate the component IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: F000_2000h base + FF0h offset + (4d × i), where i=0d to 3d
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COMPID
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
ROM_COMPIDn field descriptions
Field
COMPID
Description
Component ID
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to 0x0000_0005; ID3 to
0x0000_00B1.
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Chapter 4 Memory Map
4.5 Peripheral bridge (AIPS-Lite) memory map
The Peripheral Bridge memory map is accessible via one slave port on the crossbar in the
0x4000_0000–0x400F_FFFF region. The device implements one peripheral bridge that
defines a 1024 KB address space.
The three regions associated with this space are:
• A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for onplatform peripheral devices. The AIPS controller generates unique module enables
for all 32 spaces.
• A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for offplatform modules. The AIPS controller generates unique module enables for all 96
spaces.
• The last slot is a 4 KB region beginning at 0x400F_F000 for accessing the GPIO
module. The GPIO slot (slot 128) is an alias of slot 15. This block is also directly
interfaced to the core and provides direct access without incurring wait states
associated with accesses via the AIPS controller.
Modules that are disabled via their clock gate control bits in the SIM registers disable the
associated AIPS slots. Access to any address within an unimplemented or disabled
peripheral bridge slot results in a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a
small range within the 4 KB slots that is implemented. Accessing an address that is not
implemented in the peripheral results in a transfer error termination.
4.5.1 Read-after-write sequence and required serialization of
memory operations
In some situations, a write to a peripheral must be completed fully before a subsequent
action can occur. Examples of such situations include:
• Exiting an interrupt service routine (ISR)
• Changing a mode
• Configuring a function
In these situations, the application software must perform a read-after-write sequence to
guarantee the required serialization of the memory operations:
1. Write the peripheral register.
2. Read the written peripheral register to verify the write.
3. Continue with subsequent operations.
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Peripheral bridge (AIPS-Lite) memory map
4.5.2 Peripheral Bridge (AIPS-Lite) Memory Map
NOTE
• Slots 0-95 and 128 are 32-bit data width modules, with the
exception that slots 32,49,82 are 8-bit data width modules
(Flash memory, IRQ, WDOG)
• Slots 96-127 are 8-bit data width modules.
Table 4-21. Peripheral bridge 0 slot assignments
System 32-bit base address
Slot
number
Module
0x4000_0000
0
—
0x4000_1000
1
—
0x4000_2000
2
—
0x4000_3000
3
—
0x4000_4000
4
—
0x4000_5000
5
—
0x4000_6000
6
—
0x4000_7000
7
—
0x4000_8000
8
—
0x4000_9000
9
—
0x4000_A000
10
—
0x4000_B000
11
—
0x4000_C000
12
—
0x4000_D000
13
—
0x4000_E000
14
—
0x4000_F000
15
GPIO controller (aliased to 0x400F_F000)
0x4001_0000
16
—
0x4001_1000
17
—
0x4001_2000
18
—
0x4001_3000
19
—
0x4001_4000
20
—
0x4001_5000
21
—
0x4001_6000
22
—
0x4001_7000
23
—
0x4001_8000
24
—
0x4001_9000
25
—
0x4001_A000
26
—
0x4001_B000
27
—
0x4001_C000
28
—
Table continues on the next page...
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Chapter 4 Memory Map
Table 4-21. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
Slot
number
Module
0x4001_D000
29
—
0x4001_E000
30
—
0x4001_F000
31
—
0x4002_0000
32
Flash memory (FTMRH)
0x4002_1000
33
—
0x4002_2000
34
—
0x4002_3000
35
—
0x4002_4000
36
—
0x4002_5000
37
—
0x4002_6000
38
—
0x4002_7000
39
—
0x4002_8000
40
—
0x4002_9000
41
—
0x4002_A000
42
—
0x4002_B000
43
—
0x4002_C000
44
—
0x4002_D000
45
—
0x4002_E000
46
—
0x4002_F000
47
—
0x4003_0000
48
—
0x4003_1000
49
IRQ controller (IRQ)
0x4003_2000
50
Cyclic Redundancy Check (CRC)
0x4003_3000
51
—
0x4003_4000
52
—
0x4003_5000
53
—
0x4003_6000
54
—
0x4003_7000
55
Periodic interrupt timers (PIT)
0x4003_8000
56
Flex timer 0 (FTM0)
0x4003_9000
57
Flex timer 1 (FTM1)
0x4003_A000
58
Flex timer 2 (FTM2)
0x4003_B000
59
Analog-to-digital converter (ADC)
0x4003_C000
60
—
0x4003_D000
61
Real time clock (RTC)
0x4003_E000
62
—
0x4003_F000
63
—
0x4004_0000
64
—
0x4004_1000
65
—
0x4004_2000
66
—
0x4004_3000
67
—
Table continues on the next page...
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Peripheral bridge (AIPS-Lite) memory map
Table 4-21. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
Slot
number
Module
0x4004_4000
68
—
0x4004_5000
69
—
0x4004_6000
70
—
0x4004_7000
71
—
0x4004_8000
72
System integration module (SIM)
0x4004_9000
73
Port controller
0x4004_A000
74
—
0x4004_B000
75
—
0x4004_C000
76
—
0x4004_D000
77
—
0x4004_E000
78
—
0x4004_F000
79
—
0x4005_0000
80
—
0x4005_1000
81
—
0x4005_2000
82
Watchdog (WDOG)
0x4005_3000
83
—
0x4005_4000
84
—
0x4005_5000
85
—
0x4005_6000
86
—
0x4005_7000
87
—
0x4005_8000
88
—
0x4005_9000
89
—
0x4005_A000
90
—
0x4005_B000
91
—
0x4005_C000
92
—
0x4005_D000
93
—
0x4005_E000
94
—
0x4005_F000
95
—
0x4006_0000
96
—
0x4006_1000
97
—
0x4006_2000
98
—
0x4006_3000
99
—
0x4006_4000
100
Internal clock source (ICS)
0x4006_5000
101
System oscillator (OSC)
0x4006_6000
102
I2C0
0x4006_7000
103
—
0x4006_8000
104
—
0x4006_9000
105
—
0x4006_A000
106
Universal asynchronous receiver/transmitter 0 (UART0)
Table continues on the next page...
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Chapter 4 Memory Map
Table 4-21. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
Slot
number
Module
0x4006_B000
107
Universal asynchronous receiver/transmitter 1 (UART1)
0x4006_C000
108
Universal asynchronous receiver/transmitter 2 (UART2)1
0x4006_D000
109
—
0x4006_E000
110
—
0x4006_F000
111
—
0x4007_0000
112
—
0x4007_1000
113
—
0x4007_2000
114
—
0x4007_3000
115
Analog comparator 0 (ACMP0)
0x4007_4000
116
Analog comparator 1 (ACMP1)
0x4007_5000
117
—
0x4007_6000
118
Serial peripheral interface 0 (SPI0)
0x4007_7000
119
Serial peripheral interface 1 (SPI1)
0x4007_8000
120
—
0x4007_9000
121
Keyboard interrupt 0 (KBI0)
0x4007_A000
122
Keyboard interrupt 1 (KBI1)
0x4007_B000
123
—
0x4007_C000
124
—
0x4007_D000
125
Power management controller (PMC)
0x4007_E000
126
—
0x4007_F000
127
—
0x400F_F000
128
GPIO controller
1. This module does not exist in 32-pin LQFP or QFN packages.
4.6 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined ARM bus architecture and provides access to select
processor-local modules. These resources are only accessible from the core; other system
masters do not have access to them.
Table 4-22. PPB memory map
System 32-bit Address Range
Resource
0xE000_0000–0xE000_DFFF
Reserved
0xE000_E000–0xE000_EFFF
System Control Space
(SCS)
Additional Range Detail
Resource
0xE000_E000–0xE000_E00F
Reserved
0xE000_E010–0xE000_E0FF
SysTick
0xE000_E100–0xE000_ECFF
NVIC
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Private Peripheral Bus (PPB) memory map
Table 4-22. PPB memory map (continued)
System 32-bit Address Range
Resource
0xE000_F000–0xE00F_EFFF
Reserved
0xE00F_F000–0xE00F_FFFF
Core ROM Space (CRS)
Additional Range Detail
Resource
0xE000_ED00–0xE000_ED8F
System Control Block
0xE000_ED90–0xE000_EDEF
Reserved
0xE000_EDF0–0xE000_EEFF
Debug
0xE000_EF00–0xE000_EFFF
Reserved
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Chapter 5
Clock Distribution
5.1 Introduction
This chapter presents the clock architecture for the device, the overview of the clocks and
includes a terminology section.
The Cortex M0+ resides within a synchronous core platform, where the processor and
bus masters, flash and peripherals clocks can be configured independently.
The ICS module will be used for main system clock generation. The ICS module controls
which clock sources (internal references, external crystals or external clock signals)
generate the source of the system clocks.
5.2 Programming model
The selection and multiplexing of system clock sources is controlled and programmed via
the ICS module. The setting of clock dividers and module clock gating for the system are
programmed via the SIM module. See those sections for detailed register and bit
descriptions.
5.3 High-level device clocking diagram
This device contains following on-chip clock sources:
• Internal Clock Source (ICS) module: The main clock source generator providing bus
clock and other reference clocks to peripherals
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High-level device clocking diagram
• System Oscillator (OSC) module: The system oscillator providing reference clock to
internal clock source (ICS), the real-time clock counter clock module (RTC), and
other MCU sub-systems
• Low-Power Oscillator (LPO) module: The on-chip low-power oscillator providing 1
kHz reference clock to RTC and Watchdog (WDOG)
Figure 5-1 shows how clocks from the ICS and OSC modules are distributed to the
microcontroller’s other function units. Some modules in the microcontroller have
selectable clock input.
The following registers of the system oscillator, ICS, and SIM modules control the
multiplexers, dividers, and clock gates shown in the figure:
Table 5-1. Registers controlling multiplexers, dividers, and clock gate
OSC
ICS
SIM
Multiplexers
OSC_CR
ICS_C1
SIM_SOPT
Dividers
—
ICS_C2
SIM_BUSDIV
Clock gates
OSC_CR
ICS_C1
SIM_SCGC
SIM
ICS
CG
ICSIRCLK
ICSFFCLK
32 kHz IRC
1/2
CG
RTC / WDOG
CG
FTM
CG
Core clock
Plat clock
System clock
CG
Bus clock
Flash clock
CG
RTC / WDOG / ADC
FLL
IREFS
ICSFLLCLK
RDIV
BDIV
ICSOUTCLK
CLKS
BUSDIV
CLK_GEN
System oscillator
EXTAL
XTAL
OSCCLK
OSC
logic
OSCERCLK
XTAL_CLK
OSCOS
PMC
1 kHz LPO
LPOCLK
RTC / WDOG
CG — Clock gate
Note: See subsequent sections for details on where these clocks are used.
Figure 5-1. Clocking diagram
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Chapter 5 Clock Distribution
5.4 Clock definitions
The following table describes the clocks in Figure 5-1.
Table 5-2. Clock definitions
Clock name
Core clock
Description
ICSOUTCLK divided by BDIV.
It is the CPU HCLK which clocks the ARM Cortex-M0+ core.
Platform clock
ICSOUTCLK divided by BDIV.
It's the free-running FCLK which clocks the crossbar switch and NVIC.
System clock
ICSOUTCLK divided by BDIV.
It clocks the bus masters directly.
Bus clock
System clock divided by BUSDIV.
It clocks the bus slaves and peripherals.
Flash clock
Flash memory clock.
On this device, it is derived from Bus clock.
Debug clock
Debug logic clock.
On this device, it is derived from Platform clock.
SWD clock
DAP interface clock.
SWD clock is typically driven by an external debugger and completely
asynchronous to Core clock and Platform clock.
ICSIRCLK
ICS output of the internal 32 kHz IRC reference clock.
ICSIRCLK can be selected as the clock source of RTC or WDOG modules.
ICSOUTCLK
ICS output of either IRC, ICSFLLCLK or ICS's external reference clock that sources the core,
system, bus, and flash clock.
ICSFLLCLK
FLL output clock, FLL locks the frequency to 1024 times the internal or external reference
frequency
ICSFFCLK
ICS output of the fixed frequency clock.
ICSFFCLK can be selected as clock source for the FTM modules. The frequency of
the ICSFFCLK is determined by the setting of the ICS.
OSCCLK (OSC_OUT)
OSCERCLK
LPOCLK
System oscillator output of the internal oscillator or sourced directly from EXTAL. Used as
ICS external reference clock
System oscillator output sourced from OSCCLK that can be selected as the clock source of
RTC, WDOG or ADC modules
PMC 1 kHz output.
The LPOCLK can be selected as the clock source to the RTC or WDOG modules.
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Clock definitions
5.4.1 Device clock summary
The following table provides more information regarding the on-chip clocks.
Table 5-3. Clock summary
Clock name
Run mode frequency
Clock source
Clock is disabled when…
Core clock
Up to 40 MHz
ICSOUTCLK clock
divider
In Wait and Stop modes
Platform clock
Up to 40 MHz
ICSOUTCLK clock
divider
In Stop mode
System clock
Up to 40 MHz
ICSOUTCLK clock
divider
In Stop mode
Bus clock
Up to 20 MHz
ICSOUTCLK clock
divider
In Stop mode
Debug clock
Up to 20 MHz
Derive from Platform
clock
Debug not enabled
SWD clock
Up to 20MHz
SWD_CLK pin
Input from external clock, so will not be
disabled.
Flash clock
Up to 20 MHz
ICSOUTCLK clock
divider
In Stop mode
31.25–39.0625 kHz IRC
IRC
ICS_C1[IRCLKEN]=0,
Internal reference
(ICSIRCLK)
or
In Stop mode and ICS_C1[IREFSTEN]=0
External reference
(OSCERCLK)
DC up to 40 MHz (bypass),
System OSC
OSC_CR[OSCEN]=0,
31.25–39.0625 kHz
or
or
In Stop mode and OSC_CR[OSCSTEN]=0
4–20 MHz (crystal)
FLL out clock
32-40 MHz
(ICSFLLCLK)
System OSC
In Stop mode,
or IRC
or
FLL not enabled
ICS Fixed Frequency 31.25–39.0625 kHz
clock (ICSFFCLK)
LPOCLK
1 kHz
System OSC
In Stop mode
or IRC
PMC
Available in all power modes
5.4.2 Clock distribution
The following figure shows a simplified clock distribution diagram
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Chapter 5 Clock Distribution
LPOCLK
1-kHz
LPO
EXTAL
XTAL
OSCCLK
OSC
ICSIRCLK
WDG
RTC
ADC
ACMP0
ACMP1
UART0
UART1
UART2
SPI0
SPI1
FTM0
FTM1
FTM2
PIT
CRC
IIC
CPU
NVIC
AWIC
DEBUG
DAP
RAM
FLASH
FMC
RGPIO
AIPS
BUS_CLK
32 kHz
IRC
ICSFFCLK
1/2
FLL
CORE_CLK
ICSOUTCLK
CLK_GEN
PLAT_CLK
SYS_CLK
FLASH_CLK
ICS
Figure 5-2. High-level clock distribution diagram
NOTE
Clock divide and gating are not shown in clock distribution
diagram.
32-pin LQFP and QFN packages do not have UART2 module.
5.5 Internal clocking sources
The internal clock sources on this device are as following:
• On-chip RC oscillator range of 31.25–39.0625 kHz as the reference of FLL input.
• On-chip internal 1 kHz oscillator as the low-frequency low-power source for RTC
and WDOG according to specific use case requirement.
The following table shows the frequency availability of this device:
Table 5-4. ICS Bus Frequency Availability with Internal Reference
Reference
FEI (high range)
ICSOUTCLK
BDIV = 0
32 MHz ~ 40 MHz
BDIV = 1
16 MHz ~ 20 MHz
BDIV = 2
8 MHz ~ 10 MHz
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External clock sources
Table 5-4. ICS Bus Frequency Availability with Internal Reference
(continued)
Reference
ICSOUTCLK
BDIV = 4
4 MHz ~ 5 MHz
BDIV = 8
2 MHz ~ 2.5 MHz
BDIV = 16
1 MHz ~ 1.25 MHz
BDIV = 32
500 kHz ~ 625 kHz
BDIV = 64
250 kHz ~ 312.5 kHz
BDIV = 128
125 kHz ~ 156.25 kHz
5.6 External clock sources
This device supports the following two external clock sources:
• External square wave input clock up to DC-40MHz.
• External crystal oscillator or resonator:
• Low-range: 31.25–39.0625 kHz
• High-range: 4–20 MHz
NOTE
The external square wave input clock is only used when the
OSC module is working under external clock mode (bypass).
With the external square wave clock source, the user can use
FBE mode with FLL disabled to achieve lower power
consumption or precise clock source.
The following table shows the frequency availability of this device when sourcing from
OSC clock. OSC external clock mode is not shown.
Table 5-5. OSC frequency availability
ICS configuration
External reference
RDIV
FBE
31.25 kHz ~ 39.0625 kHz
̶
4 MHz ~ 20 MHz
̶
FEE
31.25 kHz ~ 39.0625 kHz
RDIV = 1
62.5 kHz ~ 78.125 kHz
RDIV = 2
125 kHz ~ 56.25 kHz
RDIV = 4
250 kHz ~ 312.5 kHz
RDIV = 8
500 kHz ~ 625 kHz
RDIV = 16
1 MHz ~ 1.25 MHz
RDIV = 32
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Chapter 5 Clock Distribution
Table 5-5. OSC frequency availability (continued)
ICS configuration
External reference
RDIV
2 MHz ~ 2.5 MHz
RDIV = 64
4 MHz ~ 5 MHz
RDIV = 128
8 MHz ~ 10 MHz
RDIV = 256
16 MHz ~ 20 MHz
RDIV = 512
5.7 Clock gating
The clock to each module can be individually gated on and off using the System Clock
Gating Control Register (SIM_SCGC). Prior to initializing a module, set the
corresponding bit in System Clock Gating Control Register (SIM_SCGC) to enable the
clock. Before turning off the clock, make sure to disable the module.
Any bus access to a peripheral that has its clock disabled generates an error termination.
5.8 Module clocks
The following table summarizes the clocks associated with each module.
Table 5-6. Module clocks
Module
Bus interface clock
Internal clocks
I/O interface clocks
Core modules
ARM Cortex-M0+ core
Platform clock
Core clock
—
NVIC
Platform clock
—
—
DAP
Platform clock
—
SWD_CLK
System modules
Port control
Bus clock
—
—
Crossbar Switch
Platform clock
—
—
Peripheral bridges
System clock
Bus clock
—
PMC, SIM
Bus clock
LPOCLK
—
MCM
Platform clock
—
—
CRC
Bus clock
—
—
Watchdog timer
Bus clock
Bus clock
—
LPOCLK
ICSIRCLK
OSCERCLK
Clocks
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Module clocks
Table 5-6. Module clocks (continued)
Module
Bus interface clock
Internal clocks
I/O interface clocks
ICS
Bus clock
ICSOUTCLK
—
ICSFLLCLK
ICSIRCLK
OSCERCLK
OSC
Bus clock
OSCERCLK
—
Flash Controller
System clock
—
—
Flash memory
Flash clock
—
—
SRAM
Platform clock
—
—
Bus clock
—
Memory and memory interfaces
Analog
ADC
Bus clock
OSCERCLK
ADACK
ACMP0
Bus clock
—
—
ACMP1
Bus clock
—
—
Timers
PIT
Bus clock
—
—
FTM0
Bus clock
Bus clock
FTM0_CLK
FTM1
Bus clock
FTM2
Bus clock
RTC
Bus clock
ICSFFCLK
Bus clock
FTM1_CLK1
ICSFFCLK
Bus clock
FTM2_CLK2
ICSFFCLK
Bus clock
RTCO
LPOCLK
ICSIRCLK
OSCERCLK
Communication interfaces
SPI0
Bus clock
—
SPI0_SCK
SPI1
Bus clock
—
SPI1_SCK
I2C0
Bus clock
—
I2C0_SCL
UART0
Bus clock
—
—
UART1
Bus clock
—
—
UART23
Bus clock
—
—
Human-machine interfaces
GPIO
System clock
—
—
KBI0
Bus clock
—
—
KBI1
Bus clock
—
—
1. 32-pin LQFP and QFN packages do not have FTM1_CLK.
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Chapter 5 Clock Distribution
2. 32-pin LQFP and QFN packages do not have FTM2_CLK.
3. 32-pin LQFP and QFN packages do not have UART2.
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Module clocks
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Chapter 6
Reset and Boot
6.1 Introduction
The following reset sources are supported in this MCU:
Table 6-1. Reset sources
Reset sources
POR reset
System resets
Description
• Power-on reset (POR)
•
•
•
•
•
•
•
•
External pin reset (PIN)
Low-voltage detect (LVD)
Watchdog (WDOG) timer
ICS loss of clock (LOC) reset
Stop mode acknowledge error (SACKERR)
Software reset (SW)
Lockup reset (LOCKUP)
MDM DAP system reset
Each of the system reset sources has an associated bit in the System Reset Status and ID
Register (SIM_SRSID).
The MCU can exit and reset in functional mode where the CPU is executing code
(default) or the CPU is in a debug halted state. There are several boot options that can be
configured. See Boot for more details.
6.2 Reset
This section discusses basic reset mechanisms and sources. Some modules that cause
resets can be configured to cause interrupts instead. Consult the individual peripheral
chapters for more information.
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Reset
6.2.1 Power-on reset (POR)
When power is initially applied to the MCU or when the supply voltage drops below the
power-on reset voltage level (VPOR), the POR circuit causes a POR reset condition.
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has
risen above the LVD low threshold (VLVDL). POR and LVD fields of the System Reset
Status and ID Register (SIM_SRSID). (SIM_SRSID[POR] and SIM_SRSID[LVD]) are
set following a POR.
6.2.2 System reset sources
Resetting the MCU provides a way to start processing from a known set of initial
conditions. System reset begins with the on-chip regulator in full regulation and system
clocking generation from an internal reference. When the processor exits reset, it
performs the following:
• Reads the start SP (SP_main) from vector-table offset 0
• Reads the start program counter (PC) from vector-table offset 4
• The Link Register (LR) is set to 0xFFFF_FFFF.
The on-chip peripheral modules are disabled and the non-analog I/O pins are initially
configured as disabled (except that the SWD_DIO/SWD_CLK, NMI and RESET pins
could be enabled after system reset according to the System Options Register
(SIM_SOPT) setting). The pins with analog functions assigned to them default to their
analog function after reset.
6.2.2.1 External pin reset (RESET)
This pin has an internal pullup resistor. Asserting RESET wakes the device from any
mode.
After POR reset, the PTA5 pin functions as RESET. SIM_SOPT[RSTPE] must be
programmed to enable the other functions. When this field is clear, this pin can function
as PTA5 or other alternative functions.
6.2.2.1.1
Reset pin filter
The RESET/IRQ pin filter supports filtering from both the 1 kHz LPO clock and the bus
clock. It can be used as a simple low-pass filter to filter any glitch that is introduced from
the pin of RESET/IRQ.
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Chapter 6 Reset and Boot
The glitch width threshold can be adjusted easily by setting Port Filter Register
(PORT_IOFLT) between 1~4096 BUSCLKs (or 1~128 LPOCLKs). This configurable
glitch filter can replace an on-board external analog filter, and greatly improve the EMC
performance. Setting Port Filter Register (PORT_IOFLT) can configure the filter of the
whole port.
6.2.2.2 Low-voltage detect (LVD)
This device includes a system to protect against low-voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. This
system consists of a power-on reset (POR) circuit, and an LVD circuit with a user
selectable trip voltage, either high (VLVDH) or low (VLVDL).
The LVD circuit is enabled when PMC_SPMSC1[LVDE] is set and the trip voltage is
selected by PMC_SPMSC2[LVDV]. The LVD is disabled upon entering the stop modes
unless PMC_SPMSC1[LVDSE] is set or in Serial Wire Debug (SWD) mode. If
PMC_SPMSC1[LVDSE] and PMC_SPMSC1[LVDE] are both set, the current
consumption will be higher in Stop mode with the LVD enabled.
6.2.2.3 Watchdog timer
The watchdog timer (WDOG) monitors the operation of the system by expecting periodic
communication from the software. This communication is generally known as servicing
(or refreshing) the watchdog. If this periodic refreshing does not occur, the watchdog
issues a system reset. The WDOG reset causes SIM_SRSID[WDOG] to set.
6.2.2.4 ICS loss-of-clock (LOC)
The ICS on this chip supports external reference clock monitor with reset capability.
In FBE, FBELP, or FEE modes, if 1 is written to ICS_C4[CME], the clock monitor is
enabled. If the external reference falls below a certain frequency, such as floc_high or
floc_low depending on OSC_CR[RANGE], the MCU will reset. SIM_SRSID[LOC] will
be set to indicate the error.
In FBELP or FBILP modes, the FLL is not on, so the external reference clock monitor
will not function even if 1 is written to ICS_C4[CME].
External reference clock monitor uses FLL as the internal reference clock. The FLL must
be functional before ICS_C4[CME] is set.
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Reset
6.2.2.5 Stop mode acknowledge error (SACKERR)
This reset is generated if the core attempts to enter Stop mode, but not all modules
acknowledge Stop mode within 1025 cycles of the 1 kHz LPO clock.
A module might not acknowledge the entry to Stop mode if an error condition occurs.
The error can be caused by a failure of an external clock input to a module.
6.2.2.6 Software reset (SW)
The SYSRESETREQ field in the NVIC application interrupt and reset control register
can be set to force a software reset on the device. (See ARM's NVIC documentation for
the full description of the register fields, especially the VECTKEY field requirements.)
Setting SYSRESETREQ generates a software reset request. This reset forces a system
reset of all major components except for the debug module.
6.2.2.7 Lockup reset (LOCKUP)
The LOCKUP gives immediate indication of seriously errant kernel software. This is the
result of the core being locked because of an unrecoverable exception following the
activation of the processor’s built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes SIM_SRSID[LOCKUP]
to set.
6.2.2.8 MDM-AP system reset request
Set the System Reset Request field in the MDM-AP Control register to initiate a system
reset. This is the primary method for resets via the SWD interface. The system reset is
held until this bit is cleared.
Set the Core Hold Reset field in the MDM-AP Control register to hold the core in reset as
the rest of the chip comes out of system reset.
6.2.3 MCU resets
A variety of resets are generated by the MCU to reset different modules.
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Chapter 6 Reset and Boot
6.2.3.1 POR Only
The POR Only reset asserts on the POR reset source only. It resets the PMC and RTC.
The POR Only reset also causes all other reset types to occur.
6.2.3.2 Chip POR
The Chip POR asserts on POR and LVD reset sources. It resets the Reset Pin Filter
registers and parts of the SIM and ICS.
The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur.
6.2.3.3 Early Chip Reset
The Early Chip Reset asserts on all reset sources. It resets only the flash memory module
and ARM platform. It negates before flash memory initialization begins ("earlier" than
when the Chip Reset negates).
6.2.3.4 Chip Reset
Chip Reset asserts on all reset sources and only negates after the RESET pin has also
negated. It resets the remaining modules (the modules not reset by other reset types).
6.3 Boot
This section describes the boot sequence, including sources and options.
Some configuration information such as clock trim values stored in factory programmed
flash locations is auto-loaded.
6.3.1 Boot sources
The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR1 )
to relocate the exception vector table. This device supports booting from internal flash
and RAM.
1.
VTOR: refer to Vector Table Offset Register in the ARMv6-M Architecture Reference Manual.
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Boot
This device supports booting from internal flash with the reset vectors located at
addresses 0x0 (initial SP_main), 0x4 (initial PC), and RAM with relocating the exception
vector table to RAM.
6.3.2 Boot sequence
At power-up, the on-chip regulator holds the system in a POR state until the input supply
is above the POR threshold. The system continues to be held in this static state until the
internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The Reset Controller logic then controls a sequence to exit reset.
1. A system reset is held on internal logic, the RESET pin is driven out low (about 4.2
µs), and the ICS is enabled in its default clocking mode.
2. The RESET pin is released. If RESET pin continues to be asserted (an indication of a
slow rise time on the RESET pin or external drive in low), the system continues to be
held in reset. Once the RESET pin is detected high, the core clock is enabled and the
system is released from reset.
3. The NVM starts internal initialization. Flash Controller is released from reset and
begins initialization operations while the core is still halted before the flash
initialization completes.
4. When the flash Initialization completes(16 µs) , the core sets up the stack, program
counter (PC), and link register (LR). The processor reads the start SP (SP_main)
from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR
is set to 0xFFFF_FFFF. The CPU begins execution at the PC location.
Subsequent system resets follow this same reset flow.
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Chapter 7
Power Management
7.1 Introduction
This chapter describes the various chip power modes and functionality of the individual
modules in these modes.
7.2 Power modes
The power management controller (PMC) provides the user with multiple power options.
The different modes of operation are supported to allow the user to optimize power
consumption for the level of functionality needed.
The device supports Run, Wait, and Stop modes which are easy to use for customers both
from different power consumption level and functional requirement. I/O states are held in
all the modes.
• Run mode—CPU clocks can be run at full speed and the internal supply is fully
regulated.
• Wait mode—CPU shuts down to conserve power; system clocks and bus clock are
running and full regulation is maintained.
• Stop mode—LVD optional enabled, and voltage regulator is in standby.
The three modes of operation are Run, Wait, and Stop. The WFI instruction invokes both
Wait and Stop modes for the chip.
Table 7-1. Chip power modes
Power mode
Normal RUN
Description
Allows maximum performance of chip. Default mode out of
reset; on-chip voltage regulator is on.
Core mode
Normal recover
method
Run
—
Table continues on the next page...
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Entering and exiting power modes
Table 7-1. Chip power modes (continued)
Power mode
Description
Core mode
Normal recover
method
Normal Wait via
WFI
Allows peripherals to function while the core is in Sleep mode,
reducing power. NVIC remains sensitive to interrupts;
peripherals continue to be clocked.
Sleep
Interrupt
Normal Stop via
WFI
Places chip in static state. Lowest power mode that retains all
registers while optionally maintaining LVD protection. NVIC is
disabled; AWIC is used to wake up from interrupt; peripheral
clocks are stopped.
Sleep Deep
Interrupt
7.3 Entering and exiting power modes
The WFI instruction invokes Wait and Stop modes for the chip. The processor exits the
low-power mode via an interrupt.
NOTE
The WFE instruction can have the side effect of entering a lowpower mode, but that is not its intended usage. See ARM
documentation for more on the WFE instruction.
7.4 Module operation in low-power modes
The following table illustrates the functionality of each module while the chip is in each
of the low-power modes. The standard behavior is shown with some exceptions.
Table 7-2. Module operation in low-power modes
Modules
Run
Wait
Stop
Core modules
CPU
On
Standby
Standby
NVIC
On
On
Standby
Full regulation
Full regulation
Loose regulation
WDOG
On
On
Optional on
LVD
On
On
Optional on
CRC
On
On
Standby
System modules
PMC
Clock
ICS
On
On
Optional on
OSC
On
On
Optional on
LPO
On
On
Always on
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Table 7-2. Module operation in low-power modes (continued)
Modules
Run
Wait
Stop
On
On
Standby
On
Standby1
Standby
Memory
Flash
RAM
Timer
FTM
On
On
Standby
PIT
On
On
Standby
RTC
On
On
Optional on
ADC
On
On
Optional on
ACMP
On
On
Optional on
Analog
Communication interfaces
UART
On
On
Standby
SPI
On
On
Standby3
IIC
On
On
Standby4
Human-machine interfaces
KBI
On
On
Standby
IRQ
On
On
Standby4
I/O
On
On
State held
1. SRAM enable signal disables internal clock signal and masks the address and data inputs when held low, RAM clock at
chip can be active in Wait mode.
2. Supports slave mode receive and wake-up in Stop mode
3. Supports address match wake-up in Stop mode
4. Supports pin interrupt wake-up in Stop mode
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Module operation in low-power modes
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Chapter 8
Security
8.1 Introduction
This device implements security based on the mode selected from the flash module. The
following sections provide an overview of flash security and details of the effects of
security on non-flash modules.
8.2 Flash security
The flash module provides security information to the MCU based on the state held by
the FTMRH_FSEC[SEC ]. The MCU, in turn, confirms the security request and limits
access to flash resources. During reset, the flash module initializes the Flash Security
Register (FTMRH_FSEC) using data read from the security byte of the flash
configuration field.
NOTE
The security features apply only to external accesses: CPU
accesses to the flash are not affected by the status of Flash
Security Register (FTMRH_FSEC).
In the unsecured state all flash commands are available on the programming interfaces
either from the debug port (SWD) or user code execution. When the flash is secured
(FTMRH_FSEC[SEC ] = 00, 01, or 11), the programmer interfaces are only allowed to
launch mass erase operations. Additionally, in this mode, the debug port has no access to
memory locations.
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Security interactions with other modules
8.3 Security interactions with other modules
The flash security settings are used by the system to determine what resources are
available. The following sections describe the interactions between modules and the flash
security settings or the impact that the flash security has on non-flash modules.
8.3.1 Security interactions with debug
When flash security is active, the SWD port cannot access the memory resources of the
MCU.
Although most debug functions are disabled, the debugger can write to the Flash Mass
Erase in Progress field of the MDM-AP Control Register to trigger a mass erase (Erase
All Blocks) command. A mass erase via the debugger is allowed even when some
memory locations are protected.
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Chapter 9
Debug
9.1 Introduction
This device's debug is based on the ARM CoreSight architecture and is configured to
provide the maximum flexibility as allowed by the restrictions of the pinout and other
available resources.
It provides register and memory accessibility from the external debugger interface, basic
run/halt control plus 2 breakpoints and 2 watchpoints.
This device supports only one debug interface, Serial Wire Debug (SWD).
9.2 Debug port pin descriptions
The debug port pins default to their SWD functionality after power-on-reset (POR).
Table 9-1. Serial wire debug pin description
Pin Name
Type
SWD_CLK
Input
SWD_DIO
Input / Output
Description
Serial Wire Clock. This pin is the clock for debug logic when in the Serial
Wire Debug mode. 1
Serial Wire Debug Data input/output. The SWD_DIO pin is used by an
external debug tool for communication and device control. This pin is
pulled up internally.
1. The pad library of this device does not support on-chip pull down; the SWD_CLK pin supports only pullup controlled by
PORT_PUEL[PTCPE4] bit, external pulldown resistor is required to fully support SWD protocol.
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SWD status and control registers
9.3 SWD status and control registers
Through the ARM Debug Access Port (DAP), the debugger has access to the status and
control elements, implemented as registers on the DAP bus as shown in Figure 9-1. These
registers provide additional control and status for low-power mode recovery and typical
run-control scenarios. The status register bits also provide a means for the debugger to
get updated status of the core without having to initiate a bus transaction across the
crossbar switch, thus remaining less intrusive during a debug session.
A miscellaneous debug module (MDM) is implemented on this device, which contains
the DAP control and status registers. It is important to note that these DAP control and
status registers are not memory-mapped within the system memory map and are only
accessible via the Debug Access Port using SWD. The MDM-AP is accessible as Debug
Access Port 1 with the available registers shown in the table below.
Table 9-2. MDM-AP register summary
Address
Register
Description
0x0100_0000
Status
See MDM-AP status register
0x0100_0004
Control
See MDM-AP Control register
0x0100_00FC
IDR
Read-only identification register that
always reads as 0x001C_0020
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Chapter 9 Debug
DPACC
APACC
A[3:2]
RnW
Debug Port
0x0C
See the ARM Debug Interface v5p1 Supplement.
RnW
Bus Matrix
IDR
Status
MDM -AP
Control
AHB Access Port
(AHB -AP)
Internal Bus
A[3:2]
SELECT[31:24] (APSEL) selects the AP
SELECT[7:4] (APBANKSEL) selects the bank
A[3:2] from the APACC selects the register
within the bank
AHB-AP
SELECT[31:24] = 0x00 selects the AHB-AP
See ARM documentation for further details
Access Port
A[7:4]
0x00
Data[31:0]
0x3F
APSEL
Decode
SW-DP
Generic
Debug Port
(DP)
0x01
0x08
Data[31:0]
RnW
Read Buffer (RDBUFF)
AP Select (SELECT)
0x04
A[3:2]
Control/Status (CTRL/STAT)
Debug Port ID Register (IDCODE) 0x00
DP Registers
Data[31:0]
MDM-AP
SELECT[31:24] = 0x01 selects the MDM-AP
SELECT[7:4] = 0x0 selects the bank with Status and Ctrl
A[3:2] = 2’b00 selects the Status Register
A[3:2] = 2’b01 selects the Control Register
SELECT[7:4] = 0xF selects the bank with IDR
A[3:2] = 2’b11 selects the IDR Register
(IDR register reads 0x001C_0020)
See Control and Status Register Descriptions
Figure 9-1. MDM AP addressing
9.3.1 MDM-AP status register
Table 9-3. MDM-AP status register assignments
Bit
Name
Description
0
Flash Mass Erase Acknowledge
The Flash Mass Erase Acknowledge field is cleared after POR reset. The
field is also cleared at launch of a mass erase command due to write of
Flash Mass Erase in Progress field in MDM AP Control Register. The
Flash Mass Erase Acknowledge is set after Flash control logic has started
the mass erase operation.
1
Flash Ready
Indicates that flash memory has been initialized and debugger can be
configured even if system is continuing to be held in reset via the
debugger.
0 Flash is under initialization.
Table continues on the next page...
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SWD status and control registers
Table 9-3. MDM-AP status register assignments (continued)
Bit
Name
Description
1 Flash is ready.
2
System Security
Indicates the security state. When secure, the debugger does not have
access to the system bus or any memory mapped peripherals. This field
indicates when the part is locked and no system bus access is possible.
NOTE: This bit is not valid until Flash Ready bit set.
0 Device is unsecured.
1 Device is secured.
3
System Reset
Indicates the system reset state.
0 System is in reset.
1 System is not in reset.
4
Reserved
5 – 15
16
Reserved for future use
Always read 0.
Core Halted
Indicates the core has entered Debug Halt mode
0 Core is not halted.
1 Core is halted.
17
Core SLEEPDEEP
SLEEPDEEP=1 indicates the core has entered Stop mode.
18
Core SLEEPING
SLEEPING=1 indicates the core has entered Wait mode.
Reserved for future use
Always reads 0.
19 – 31
9.3.2 MDM-AP Control register
Table 9-4. MDM-AP Control register assignments
Bit
Secure1
Name
Description
0
Flash Mass Erase in Progress
Y
Set to cause mass erase. Cleared by hardware after mass erase
operation completes.
1
Debug Disable
N
Set to disable debug. Clear to allow debug operation. When set, it
overrides the C_DEBUGEN field within the DHCSR2 and forces to
disable Debug logic.
2
Debug Request
N
Set to force the core to halt.
If the core is in Stop or Wait mode, this field can be used to wake the
core and transition to a halted state.
3
System Reset Request
Y
Set to force a system reset. The system remains held in reset until
this field is cleared. When this bit is set, RESET pin does not reflect
the status of system reset and does not keep low.
4
Core Hold
N
Configuration field to control core operation at the end of system
reset sequencing.
0 Normal operation—release the core from reset along with the rest
of the system at the end of system reset sequencing.
Table continues on the next page...
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Chapter 9 Debug
Table 9-4. MDM-AP Control register assignments (continued)
Bit
Secure1
Name
Description
1 Suspend operation—hold the core in reset at the end of reset
sequencing. Once the system enters this suspended state, clearing
this control bit immediately releases the core from reset and CPU
operation begins.
5– 31
Reserved for future use
N
1. Command available in secure mode
2. DHCSR: refer to the Debug Halting Control and Status Register in the ARMv6-M Architecture Reference Mannual.
9.4 Debug resets
The debug system receives the following sources of reset:
• System POR reset
Conversely, the debug system is capable of generating system reset using the following
mechanism:
• A system reset in the DAP control register which allows the debugger to hold the
system in reset.
• Writing 1 to the SYSRESETREQ field in the NVIC Application Interrupt and Reset
Control register
• A system reset in the DAP control register which allows the debugger to hold the
core in reset.
9.5 Debug in low-power modes
In low-power modes in which the debug modules are kept static or powered off, the
debugger cannot gather any debug data for the duration of the low-power mode.
• If the debugger is held static, the debug port returns to full functionality as soon as
the low-power mode exits and the system returns to a state with active debug.
• If the debugger logic is powered off, the debugger is reset on recovery and must be
reconfigured once the low-power mode is exited.
The active debug will prevent the chip from entering low-power mode. In case the chip is
already in low-power mode, a debug request from MDM-AP control register will wake
the chip from low-power mode.
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Debug and security
9.6 Debug and security
When flash security is enabled, the debug port capabilities are limited in order to prevent
exploitation of secure data. In the secure state, the debugger still has access to the status
register and can determine the current security state of the device. In the case of a secure
device, the debugger has the capability of performing only a mass erase operation.
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Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction
To optimize functionality in small packages, pins have several functions available via
signal multiplexing. This chapter illustrates which of this device's signals are multiplexed
on which external pin.
The Pin Selection Register (SIM_PINSEL) controls which signal is present on the
external pin. Refer to that register to find the detailed control operation of a specific
multiplexed pin.
10.2 Pinout
10.2.1 Signal multiplexing and pin assignments
These MCUs support up to 57 general-purpose I/O pins, which are shared with on-chip
peripheral functions (FTM, ADC, UART, SPI, I2C, KBI, etc.).
When a port pin is configured as general-purpose input, or when a peripheral uses the
port pin as an input, the software can enable a pullup device.
When a high-current drive port pin is configured as general-purpose output, or when a
peripheral uses the port pin as an output, the software can select alternative drive
strengths.
For information about controlling these pins as general-purpose I/O pins, see the Port
control (PORT). For information about how and when on-chip peripheral systems use
these pins, see the appropriate module chapter.
Immediately after reset, all pins are configured as high-impedance general-purpose IO
with internal pullup devices disabled.
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Pinout
Table 10-1. Pin availability by package pin-count
Pin Number
Lowest Priority Highest
64-QFP/
LQFP
44-LQFP
32LQFP/QFN
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
1
1
PTD1
KBI1_P1
FTM2_CH3
SPI1_MOSI
—
KBI1_P0
FTM2_CH2
SPI1_SCK
—
2
2
2
PTD01
3
—
—
PTH7
—
—
—
—
4
—
—
PTH6
—
—
—
—
5
3
—
PTE7
—
FTM2_CLK
—
FTM1_CH1
6
4
—
PTH2
—
BUSOUT
—
FTM1_CH0
7
5
3
—
—
—
—
VDD
8
6
4
—
—
—
VDDA
VREFH
9
7
5
—
—
—
—
VREFL
10
8
6
—
—
—
VSSA
VSS
11
9
7
PTB7
—
I2C0_SCL
—
EXTAL
12
10
8
PTB6
—
I2C0_SDA
—
XTAL
13
11
—
—
—
—
—
VSS
14
—
—
PTH11
—
FTM2_CH1
—
—
15
—
—
PTH01
—
FTM2_CH0
—
—
16
—
—
PTE6
—
—
—
—
17
—
—
PTE5
—
—
—
—
9
PTB51
FTM2_CH5
SPI0_PCS0
ACMP1_OUT
—
FTM2_CH4
SPI0_MISO
NMI
ACMP1_IN2
—
—
ADC0_SE11
18
12
19
13
10
PTB41
20
14
11
PTC3
FTM2_CH3
21
15
12
PTC2
FTM2_CH2
—
—
ADC0_SE10
22
16
—
PTD7
KBI1_P7
UART2_TX
—
—
23
17
—
PTD6
KBI1_P6
UART2_RX
—
—
24
18
—
PTD5
KBI1_P5
—
—
—
25
19
13
PTC1
—
FTM2_CH1
—
ADC0_SE9
26
20
14
PTC0
—
FTM2_CH0
—
ADC0_SE8
27
—
—
PTF7
—
—
—
ADC0_SE15
28
—
—
PTF6
—
—
—
ADC0_SE14
29
—
—
PTF5
—
—
—
ADC0_SE13
30
—
—
PTF4
—
—
—
ADC0_SE12
31
21
15
PTB3
KBI0_P7
SPI0_MOSI
FTM0_CH1
ADC0_SE7
32
22
16
PTB2
KBI0_P6
SPI0_SCK
FTM0_CH0
ADC0_SE6
33
23
17
PTB1
KBI0_P5
UART0_TX
—
ADC0_SE5
34
24
18
PTB0
KBI0_P4
UART0_RX
—
ADC0_SE4
35
—
—
PTF3
—
—
—
—
36
—
—
PTF2
—
—
—
—
37
25
19
PTA7
—
FTM2_FLT2
ACMP1_IN1
ADC0_SE3
38
26
20
PTA6
—
FTM2_FLT1
ACMP1_IN0
ADC0_SE2
Table continues on the next page...
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Chapter 10 Signal Multiplexing and Signal Descriptions
Table 10-1. Pin availability by package pin-count (continued)
Pin Number
Lowest Priority Highest
64-QFP/
LQFP
44-LQFP
32LQFP/QFN
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
39
—
—
PTE4
—
—
—
—
40
27
—
—
—
—
—
VSS
41
28
—
—
—
—
—
VDD
42
—
—
PTF1
—
—
—
—
43
—
—
PTF0
—
—
—
—
44
29
—
PTD4
KBI1_P4
—
—
—
45
30
21
PTD3
KBI1_P3
SPI1_PCS0
—
—
46
31
22
PTD2
KBI1_P2
SPI1_MISO
—
—
47
32
23
PTA3
KBI0_P3
UART0_TX
I2C0_SCL
—
KBI0_P2
UART0_RX
I2C0_SDA
—
48
33
24
PTA22
49
34
25
PTA1
KBI0_P1
FTM0_CH1
ACMP0_IN1
ADC0_SE1
50
35
26
PTA0
KBI0_P0
FTM0_CH0
ACMP0_IN0
ADC0_SE0
51
36
27
PTC7
—
UART1_TX
—
—
52
37
28
PTC6
—
UART1_RX
—
—
53
—
—
PTE3
—
SPI0_PCS0
—
—
54
38
—
PTE2
—
SPI0_MISO
—
—
55
—
—
PTG3
—
—
—
—
56
—
—
PTG2
—
—
—
—
57
—
—
PTG1
—
—
—
—
58
—
—
PTG0
—
—
—
—
—
PTE11
—
SPI0_MOSI
—
—
59
39
60
40
—
PTE01
—
SPI0_SCK
FTM1_CLK
—
61
41
29
PTC5
—
FTM1_CH1
—
RTCO
62
42
30
PTC4
RTCO
FTM1_CH0
ACMP0_IN2
SWD_CLK
63
43
31
PTA5
IRQ
FTM0_CLK
—
RESET
64
44
32
PTA4
—
ACMP0_OUT
—
SWD_DIO
1. This is a high-current drive pin when operated as output.
2. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. Table 10-1
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
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Pinout
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
PTE3
PTC6
PTC7
PTA0
PTA1
52
51
50
49
PTE2
PTG1
57
54
PTG0
58
53
PTE11
59
PTG2
PTE01
PTG3
PTC5
60
55
PTC4
62
61
56
PTA4
PTA5
64
63
10.2.2 Device pin assignment
PTD1 1
1
48
PTA22
PTD0 1
2
47
PTA32
PTD2
PTH7
3
46
PTH6
4
45
PTD3
PTE7
5
44
PTD4
PTH2
VDD
6
43
PTF0
7
42
PTF1
8
41
VDD
9
40
VSS
10
39
PTE4
PTA6
VDDA/VREFH
VREFL
VSSA/VSS
PTB7
PTB6
11
38
12
37
PTA7
VSS
13
36
PTF2
27
28
29
PTF7
PTF6
PTF5
32
26
PTC0
PTB2
25
PTC1
31
24
PTD5
30
23
PTD6
PTF4
22
PTD7
PTB3
21
PTC2
PTB1
19
33
20
16
PTB4 1
PTC3
PTB0
PTE6
17
PTF3
34
18
35
15
PTE5
14
PTB5 1
PTH11
PTH01
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 10-1. 64-pin QFP/LQFP packages
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PTC6
PTC7
PTA0
PTA1
36
35
34
PTE2
38
37
PTE01
PTE11
PTC5
41
39
PTC4
42
40
PTA4
PTA5
43
44
Chapter 10 Signal Multiplexing and Signal Descriptions
PTB0
23
PTB1
22
24
11
21
10
VSS
PTB2
PTA7
PTB3
PTA6
PTB7
PTB6
20
26
25
PTC0
8
9
19
VSS
18
VDD
27
PTC1
28
7
PTD5
6
VREFL
VSSA/VSS
17
PTD4
PTD6
29
16
5
PTD7
PTD3
VDD
VDDA/VREFH
15
30
14
4
PTC2
PTH2
PTC3
3
31
PTA32
PTE7
13
PTA22
32
12
33
2
PTB5 1
1
PTD0 1
PTB4 1
PTD1 1
PTD2
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
PTC6
PTA0
PTA1
26
25
PTC5
29
PTC7
PTC4
30
28
PTA5
31
27
PTA4
32
Figure 10-2. 44-pin LQFP package
PTD1 1
1
24
PTA22
PTD0 1
2
23
PTA32
VDD
VDDA/VREFH
3
22
PTD2
4
21
PTD3
13
14
15
16
PTB3
PTB2
PTB1
PTC0
17
PTC1
8
11
PTB0
PTB6
12
PTA7
18
PTC3
19
7
PTC2
6
PTB7
10
PTA6
PTB4 1
20
9
5
PTB5 1
VREFL
VSSA/VSS
1. High source/sink current pins
2. True open drain pins
Figure 10-3. 32-pin LQFP package
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PTD1 1
PTC6
PTC7
PTA0
PTA1
26
25
PTC5
29
27
PTC4
30
28
PTA4
PTA5
32
31
Module signal description tables
24
PTA22
2
23
PTA32
3
22
PTD2
1
16
PTB2
PTB1
15
17
PTB3
8
14
PTB0
PTB6
PTC0
PTA7
18
13
19
7
12
6
PTB7
PTC2
PTA6
PTC1
20
11
5
PTC3
PTD3
VREFL
VSSA/VSS
9
21
10
4
PTB5 1
VDD
VDDA/VREFH
PTB4 1
PTD0 1
1. High source/sink current pins
2. True open drain pins
Figure 10-4. 32-pin QFN package
10.3 Module signal description tables
The following sections correlate the chip-level signal name with the signal name used in
the module's chapter. They also briefly describe the signal function and direction.
10.3.1 Core modules
Table 10-2. SWD signal descriptions
Chip signal name
Module signal
name
Description
I/O
SWD_DIO
SWD_DIO
Serial Wire Debug Data input/output. The SWD_DIO pin is used by
an external debug tool for communication and device control. This
pin is pulled up internally.
Input /
Output
SWD_CLK
SWD_CLK
Serial Wire Clock. This pin is the clock for debug logic when in the
Serial Wire Debug mode. 1
Input
1. The pad library of this device does not support on-chip pull down; the SWD_CLK pin supports only pullup controlled by
PORT_PUEL[PTCPE4] bit, external pulldown resistor is required to fully support SWD protocol.
10.3.2 System modules
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Chapter 10 Signal Multiplexing and Signal Descriptions
Table 10-3. System signal descriptions
Chip signal name
Module signal
name
NMI
—
Description
Non-maskable interrupt
I/O
I
NOTE: Driving the NMI signal low forces a non-maskable
interrupt, if the NMI function is selected on the
corresponding pin.
RESET
—
Reset bidirectional signal
I/O
VDD
—
MCU power
I
VSS
—
MCU ground
I
10.3.3 Clock modules
Table 10-4. OSC signal descriptions
Chip signal name
Module signal
name
EXTAL
EXTAL
XTAL
XTAL
Description
I/O
External clock/oscillator input
Analog
input
Oscillator output
Analog
output
10.3.4 Analog
Table 10-5. ADC0 signal descriptions
Chip signal name
Module signal
name
ADC0_SEn
AD15-AD0
VDDA/VREFH
VDDA/VREFH
VREFL
VREFL
Description
I/O
Analog channel inputs
I
Analog power supply / voltage reference high
I
Voltage reference low
I
Table 10-6. ACMP0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
ACMP0_INn
ACMP0_IN[2:0]
Analog voltage inputs
I
ACMP0_OUT
ACMP0_OUT
Comparator output
O
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Module signal description tables
Table 10-7. ACMP1 signal descriptions
Chip signal name
Module signal
name
Description
I/O
ACMP1_INn
ACMP1_IN[2:0]
Analog voltage inputs
I
ACMP1_OUT
ACMP1_OUT
Comparator output
O
10.3.5 Timer modules
Table 10-8. FTM0 signal descriptions
Chip signal name
Module signal
name
FTM0_CLK
EXTCLK
FTM0_CH[1:0]
CHn
Description
FTM external clock
FTM channel
I/O
I
I/O
Table 10-9. FTM1 signal descriptions
Chip signal name
Module signal
name
FTM1_CLK1
EXTCLK
FTM1_CH[1:0]
CHn
Description
FTM external clock
FTM channel
I/O
I
I/O
1. 32-pin LQFP and QFN packages do not have this signal.
Table 10-10. FTM2 signal descriptions
Chip signal name
Module signal
name
Description
FTM2_CLK1
EXTCLK
FTM2_CH[5:0]
CHn
FTM channel
I/O
FTM2_FLT1
FAULT1
Fault input (1)
I
FTM2_FLT2
FAULT2
Fault input (2)
I
FTM external clock
I/O
I
1. 32-pin LQFP and QFN packages do not have this signal.
Table 10-11. RTC signal descriptions
Chip signal name
Module signal
name
RTCO
RTCO
Description
I/O
RTC clock output
O
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Chapter 10 Signal Multiplexing and Signal Descriptions
10.3.6 Communication Interfaces
Table 10-12. SPI0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
SPI0_MISO
MISO
Master Data In, Slave Data Out
I/O
SPI0_MOSI
MOSI
Master Data Out, Slave Data In
I/O
SPI0_SCK
SPSCK
SPI Serial Clock
I/O
SPI0_PCS0
SS
Slave Select
I/O
Table 10-13. SPI1 signal descriptions
Chip signal name
Module signal
name
Description
I/O
SPI1_MISO
MISO
Master Data In, Slave Data Out
I/O
SPI1_MOSI
MOSI
Master Data Out, Slave Data In
I/O
SPI1_SCK
SPSCK
SPI Serial Clock
I/O
SPI1_PCS0
SS
Slave Select
I/O
Table 10-14. I2C0 signal descriptions
Chip signal name
Module signal
name
I2C0_SCL
SCL
I2C0_SDA
SDA
Description
I/O
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the
I2C
system.
I/O
I/O
Table 10-15. UART0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
UART0_TX
TxD
Transmit data
I/O
UART0_RX
RxD
Receive data
I
Table 10-16. UART1 signal descriptions
Chip signal name
Module signal
name
Description
I/O
UART1_TX
TxD
Transmit data
I/O
UART1_RX
RxD
Receive data
I
NOTE
32-pin LQFP and QFN packages do not have UART2 module.
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Module signal description tables
Table 10-17. UART2 signal descriptions
Chip signal name
Module signal
name
Description
I/O
UART2_TX
TxD
Transmit data
I/O
UART2_RX
RxD
Receive data
I
10.3.7 Human-machine interfaces (HMI)
Table 10-18. GPIO signal descriptions
Chip signal name
Module signal
name
PTA[7:0]
PORTA7-PORTA0
PTB[7:0]
General-purpose input/output
I/O
PORTA15-PORTA8 General-purpose input/output
I/O
1
PORTA23-PORTA16 General-purpose input/output
I/O
1
PORTA31-PORTA24 General-purpose input/output
I/O
PTD[7:0]
PTF[7:0]
I/O
1
PTC[7:0]
PTE[7:0]
Description
1
General-purpose input/output
I/O
1
PORTB15-PORTB8 General-purpose input/output
I/O
1
PORTB23-PORTB16 General-purpose input/output
I/O
1
PORTB31-PORTB24 General-purpose input/output
I/O
PTG[7:0]
PTH[7:0]
PORTB7-PORTB0
1. The available GPIO pins depend on the specific package. See the signal multiplexing section for which exact GPIO signals
are available.
Table 10-19. KBI0 signal descriptions
Chip signal name
Module signal
name
KBI0_Pn
KBI0Pn
Description
I/O
Keyboard interrupt pins, n can be 0 ~ 7
I/O
Table 10-20. KBI1 signal descriptions
Chip signal name
Module signal
name
KBI1_Pn
KBI1Pn
Description
I/O
Keyboard interrupt pins, n can be 0 ~ 71
I/O
1. For 32-pin LQFP and QFN packages, n can be 0 ~ 3.
Table 10-21. IRQ signal descriptions
Chip signal name
Module signal
name
IRQ
IRQ
Description
IRQ input
I/O
I
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Chapter 11
Port Control (PORT)
11.1 Introduction
This device has eight sets of I/O ports, which include up to 57 general-purpose I/O pins.
Not all pins are available on all devices.
Many of the I/O pins are shared with on-chip peripheral functions. The peripheral
modules have priority over the I/O, so when a peripheral is enabled, the associated I/O
functions are disabled.
After reset, the shared peripheral functions are disabled so that the pins are controlled by
the parallel I/O except PTA4, PTA5, PTB4 and PTC4 that are default to SWD_DIO,
SWD_CLK, NMI and RESET function. All of the parallel I/O are configured as highimpedance (Hi-Z). The pin control functions for each pin are configured as follows:
• input disabled (GPIOx_PIDR[PID] = 1),
• output disabled ( GPIOx_PDDR[PDD] = 0), and
• internal pullups disabled (PORT_PUE(L/H)[PTxPEn] = 0).
Additionally, the parallel I/O that support high drive capability are disabled (HDRVE =
0x00) after reset.
The following three figures show the structures of each I/O pin.
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Introduction
PORT_PUE(L/H)[PTxPEn]
GPIOx_PDDR[PDD]
GPIOx_PDOR[PDO]
GPIOx_PIDR[PID]
1
CPU read GPIOx_PDIR[PDI]
0 (except RESET/NMI)
Glitch filter
PORT_IOFLT
0
Figure 11-1. Normal I/O structure
GPIOx_PDDR[PDD]
PORT_PUE(L/H)[PTxPEn]
GPIOx_PDOR[PDO]
GPIOx_PIDR[PID]
CPU read GPIOx_PDIR[PDI]
1
0 (except RESET/NMI)
Glitch filter
PORT_IOFLT
0
Figure 11-2. SDA(PTA2)/SCL(PTA3) structure
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Chapter 11 Port Control (PORT)
PORT_PUE(L/H)[PTxPEn]
GPIOx_PDDR[PDD]
GPIOx_PDOR[PDO]
GPIOx_PIDR[PID]
HDRVE
1
CPU read GPIOx_PDIR[PDI]
0 (except RESET/NMI)
Glitch filter
PORT_IOFLT
0
Figure 11-3. High drive I/O structure
11.2 Port data and data direction
Reading and writing of parallel I/O is accomplished through the port data registers
(GPIOx_PDIR/PDOR). The direction, input or output, is controlled through the input
disable register (GPIOx_PIDR) and data direction register (GPIOx_PDDR).
After reset, all parallel I/O default to the Hi-Z state. The corresponding bit in port data
direction register (GPIOx_PDDR) or input disable register (GPIOx_PIDR) must be
configured for output or input operation. Each port pin has an input disable bit and an
output enable bit. When GPIOx_PIDR[PID] = 0, a read from GPIOx_PDIR returns the
input value of the associated pin; when GPIOx_PIDR[PID] = 1, a read from
GPIOx_PDIR[PDI] returns 0 except for RESET/NMI.
NOTE
The GPIOx_PDDR must be clear when the corresponding pin is
used as input function to avoid contention. If set the
corresponding GPIOx_PDDR and GPIOx_PIDR bits at same
time, read from GPIOx_PDIR will always read the pin status.
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Internal pullup enable
When a peripheral module or system function is in control of a port pin, the data direction
register bit still controls what is returned for reads of the port data register, even though
the peripheral system has overriding control of the actual pin direction.
When a shared analog function is enabled for a pin, all digital pin functions are disabled.
A read of the port data register returns a value of 0 for any bits that have shared analog
functions enabled. In general, whenever a pin is shared with both an alternate digital
function and an analog function, the analog function has priority such that if both of the
digital and analog functions are enabled, the analog function controls the pin.
A write of valid data to a port data register must occur before setting the output enable bit
of an associated port pin. This ensures that the pin will not be driven with an incorrect
data value.
11.3 Internal pullup enable
An internal pullup device can be enabled for each port pin by setting the corresponding
bit in one of the pullup enable registers (PORT_PUE(L/H)). The internal pullup device is
disabled if the pin is configured as an output by the parallel I/O control logic, or by any
shared peripheral function, regardless of the state of the corresponding pullup enable
register bit. The internal pullup device is also disabled if the pin is controlled by an
analog function.
NOTE
When configuring I2C0 to use "SDA(PTA2/PTB6) and
SCL(PTA3/PTB7)" pins, and if an application uses internal
pullups instead of external pullups, the internal pullups remain
at present setting when the pins are configured as outputs, but
they are automatically disabled to save power when the output
values are low.
11.4 Input glitch filter setting
A filter is implemented for each port pin that is configured as a digital input. It can be
used as a simple low-pass filter to filter any glitch that is introduced from the pins of
GPIO, IRQ,RESET, NMI and KBI. The glitch width threshold can be adjusted easily by
setting PORT_IOFLT[FLTDIVn] between 1~4096 BUSCLKs (or 1~128 LPOCLKs).
This configurable glitch filter can take the place of an on board external analog filter, and
greatly improve the EMC performance because any glitch will not be wrongly sampled or
ignored.
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Chapter 11 Port Control (PORT)
Setting register PORT_IOFLT can configure the filters of the whole port or peripheral
inputs. For example, setting PORT_IOFLT[FLTA] will affect all PTAn pins.
Glitches that are shorter than the selected clock period will be filtered out; Glitches that
are more than twice the selected clock period will not be filtered out. It will pass to
internal circuitry.
Pass to
internal rate
100%
0
Input high/low width
1(FLTxxx period)
2(FLTxxx period)
Note: FLTxxx is contents in register PORT_IOFLT.
Figure 11-4. Input glitch filter
11.5 High current drive
Output high sink/source current drive can be enabled by setting the corresponding bit in
the HDRVE register for PTH1, PTH0, PTE1, PTE0, PTD1, PTD0, PTB5 and PTB4.
These pins can used as output and input; the pins output high sink/source current when
they are operated as output.
• High-current drive function is disabled, if the pin is configured as an input by the
parallel I/O control logic.
• When configured as any shared peripheral function, high-current drive function still
works on these pins, but only when they are configured as outputs.
11.6 Pin behavior in Stop mode
In Stop mode, all I/O is maintained because internal logic circuitry stays powered up.
Upon recovery, normal I/O function is available to the user.
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Port data registers
11.7 Port data registers
PORT memory map
Absolute
address
(hex)
Width
Access
(in bits)
Register name
Reset value
Section/
page
4004_9000
Port Filter Register (PORT_IOFLT)
32
R/W
00C0_0000h
11.7.1/142
4004_9004
Port Pullup Enable Low Register (PORT_PUEL)
32
R/W
0010_0000h
11.7.2/145
4004_9008
Port Pullup Enable High Register (PORT_PUEH)
32
R/W
0000_0000h
11.7.3/150
4004_900C
Port High Drive Enable Register (PORT_HDRVE)
32
R/W
0000_0000h
11.7.4/154
11.7.1 Port Filter Register (PORT_IOFLT)
This register sets the filters for input pins. Configure the high/low level glitch width
threshold. Glitches that are shorter than the selected clock period will be filtered out;
glitches that are more than twice the selected clock period will not be filtered out and will
pass to internal circuitry.
Address: 4004_9000h base + 0h offset = 4004_9000h
Bit
R
W
31
Reset
0
Bit
R
W
15
Reset
0
30
29
28
FLTDIV3
27
0
0
14
13
FLTH
0
0
12
11
FLTG
0
26
FLTDIV2
0
25
0
23
22
21
20
19
18
17
16
FLTNMI
FLTKBI1
FLTKBI0
FLTRST
0
0
0
1
1
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
FLTF
0
24
FLTDIV1
FLTE
0
0
FLTD
0
0
FLTC
0
0
FLTB
0
0
0
0
FLTA
0
0
0
PORT_IOFLT field descriptions
Field
31–29
FLTDIV3
Description
Filter Division Set 3
Port Filter Division Set 3
000
001
010
011
100
101
110
111
LPOCLK
LPOCLK/2
LPOCLK/4
LPOCLK/8
LPOCLK/16
LPOCLK/32
LPOCLK/64
LPOCLK/128
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Chapter 11 Port Control (PORT)
PORT_IOFLT field descriptions (continued)
Field
28–26
FLTDIV2
Description
Filter Division Set 2
Port Filter Division Set 2
000
001
010
011
100
101
110
111
25–24
FLTDIV1
BUSCLK/32
BUSCLK/64
BUSCLK/128
BUSCLK/256
BUSCLK/512
BUSCLK/1024
BUSCLK/2048
BUSCLK/4096
Filter Division Set 1
Port Filter Division Set 1
00
01
10
11
BUSCLK/2
BUSCLK/4
BUSCLK/8
BUSCLK/16
23–22
FLTNMI
Filter Selection for Input from NMI
21–20
FLTKBI1
Filter Selection for Input from KBI1
19–18
FLTKBI0
Filter selection for Input from KBI0
17–16
FLTRST
Filter Selection for Input from RESET/IRQ
15–14
FLTH
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
No filter.
Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.
Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.
FLTDIV3
No filter
Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.
Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.
FLTDIV3
No filter.
Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.
Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.
FLTDIV3
No filter.
Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.
Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.
FLTDIV3
Filter Selection for Input from PTH
00
01
BUSCLK
FLTDIV1
Table continues on the next page...
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Port data registers
PORT_IOFLT field descriptions (continued)
Field
Description
10
11
FLTDIV2
FLTDIV3
13–12
FLTG
Filter Selection for Input from PTG
11–10
FLTF
Filter Selection for Input from PTF
9–8
FLTE
Filter Selection for Input from PTD
7–6
FLTD
Filter Selection for Input from PTD
5–4
FLTC
Filter Selection for Input from PTC
3–2
FLTB
Filter Selection for Input from PTB
FLTA
Filter Selection for Input from PTA
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
BUSCLK
FLTDIV1
FLTDIV2
FLTDIV3
BUSCLK
FLTDIV1
FLTDIV2
FLTDIV3
BUSCLK
FLTDIV1
FLTDIV2
FLTDIV3
BUSCLK
FLTDIV1
FLTDIV2
FLTDIV3
BUSCLK
FLTDIV1
FLTDIV2
FLTDIV3
BUSCLK
FLTDIV1
FLTDIV2
FLTDIV3
BUSCLK
FLTDIV1
FLTDIV2
FLTDIV3
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Chapter 11 Port Control (PORT)
11.7.2 Port Pullup Enable Low Register (PORT_PUEL)
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
PTDPE7
PTDPE6
PTDPE5
PTDPE4
PTDPE3
PTDPE2
PTDPE1
PTDPE0
PTCPE7
PTCPE6
PTCPE5
PTCPE4
PTCPE3
PTCPE2
PTCPE1
PTCPE0
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
PTAPE7
PTAPE6
PTAPE5
PTAPE4
PTAPE3
PTAPE2
PTAPE1
PTAPE0
Address: 4004_9000h base + 4h offset = 4004_9004h
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PORT_PUEL field descriptions
Field
31
PTDPE7
Description
Pull Enable for Port D Bit 7
This control field determines if the internal pullup device is enabled for the associated PTD pin. For port D
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
30
PTDPE6
Pull Enable for Port D Bit 6
This control field determines if the internal pullup device is enabled for the associated PTD pin. For port D
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
29
PTDPE5
This control field determines if the internal pullup device is enabled for the associated PTD pin. For port D
pins that are configured as outputs or Hi-Z, this field has no effect.
Pullup is disabled for port D bit 5.
Pullup is enabled for port D bit 5.
Pull Enable for Port D Bit 4
This control bit determines if the internal pullup device is enabled for the associated PTD pin. For port D
pins that are configured as outputs or Hi-Z, these bits have no effect.
0
1
27
PTDPE3
Pullup is disabled for port D bit 6.
Pullup is enabled for port D bit 6.
Pull Enable for Port D Bit 5
0
1
28
PTDPE4
Pullup is disabled for port D bit 7.
Pullup is enabled for port D bit 7.
Pullup is disabled for port D bit 4.
Pullup is enabled for port D bit 4.
Pull Enable for Port D Bit 3
Table continues on the next page...
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Port data registers
PORT_PUEL field descriptions (continued)
Field
Description
This control field determines if the internal pullup device is enabled for the associated PTD pin. For port D
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
26
PTDPE2
Pull Enable for Port D Bit 2
This control field determines if the internal pullup device is enabled for the associated PTD pin. For port D
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
25
PTDPE1
This control field determines if the internal pullup device is enabled for the associated PTD pin. For port D
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTD pin. For port D
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTC pin. For port C
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTC pin. For port C
pins that are configured as outputs or Hi-Z, this field has no effect.
Pullup is disabled for port C bit 6.
Pullup is enabled for port C bit 6.
Pull Enable for Port C Bit 5
This control field determines if the internal pullup device is enabled for the associated PTC pin. For port C
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
20
PTCPE4
Pullup is disabled for port C bit 7.
Pullup is enabled for port C bit 7.
Pull Enable for Port C Bit 6
0
1
21
PTCPE5
Pullup is disabled for port D bit 0.
Pullup is enabled for port D bit 0.
Pull Enable for Port C Bit 7
0
1
22
PTCPE6
Pullup is disabled for port D bit 1.
Pullup is enabled for port D bit 1.
Pull Enable for Port D Bit 0
0
1
23
PTCPE7
Pullup is disabled for port D bit 2.
Pullup is enabled for port D bit 2.
Pull Enable for Port D Bit 1
0
1
24
PTDPE0
Pullup is disabled for port D bit 3.
Pullup is enabled for port D bit 3.
Pullup is disabled for port C bit 5.
Pullup is enabled for port C bit 5.
Pull Enable for Port C Bit 4
This control field determines if the internal pullup device is enabled for the associated PTC pin. For port C
pins that are configured as outputs or Hi-Z, this field has no effect.
Table continues on the next page...
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Chapter 11 Port Control (PORT)
PORT_PUEL field descriptions (continued)
Field
Description
0
1
19
PTCPE3
Pull Enable for Port C Bit 3
This control field determines if the internal pullup device is enabled for the associated PTC pin. For port C
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
18
PTCPE2
This control field determines if the internal pullup device is enabled for the associated PTC pin. For port C
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTC pin. For port C
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTC pin. For port C
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTB pin. For port B
pins that are configured as outputs or Hi-Z, this field has no effect.
Pullup is disabled for port B bit 7.
Pullup is enabled for port B bit 7.
Pull Enable for Port B Bit 6
This control field determines if the internal pullup device is enabled for the associated PTB pin. For port B
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
13
PTBPE5
Pullup is disabled for port C bit 0.
Pullup is enabled for port C bit 0.
Pull Enable for Port B Bit 7
0
1
14
PTBPE6
Pullup is disabled for port C bit 1.
Pullup is enabled for port C bit 1.
Pull Enable for Port C Bit 0
0
1
15
PTBPE7
Pullup is disabled for port C bit 2.
Pullup is enabled for port C bit 2.
Pull Enable for Port C Bit 1
0
1
16
PTCPE0
Pullup is disabled for port C bit 3.
Pullup is enabled for port C bit 3.
Pull Enable for Port C Bit 2
0
1
17
PTCPE1
Pullup is disabled for port C bit 4.
Pullup is enabled for port C bit 4.
Pullup is disabled for port B bit 6.
Pullup is enabled for port B bit 6.
Pull Enable for Port B Bit 5
This control field determines if the internal pullup device is enabled for the associated PTB pin. For port B
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
Pullup is disabled for port B bit 5.
Pullup is enabled for port B bit 5.
Table continues on the next page...
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Port data registers
PORT_PUEL field descriptions (continued)
Field
12
PTBPE4
Description
Pull Enable for Port B Bit 4
This control field determines if the internal pullup device is enabled for the associated PTB pin. For port B
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
11
PTBPE3
Pull Enable for Port B Bit 3
This control field determines if the internal pullup device is enabled for the associated PTB pin. For port B
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
10
PTBPE2
This control field determines if the internal pullup device is enabled for the associated PTB pin. For port B
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTB pin. For port B
pins that are configured as outputs or Hi-Z, tthis field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTB pin. For port B
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured as outputs or Hi-Z, this field has no effect.
Pullup is disabled for port A bit 7.
Pullup is enabled for port A bit 7.
Pull Enable for Port A Bit 6
This control field determines if the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
5
PTAPE5
Pullup is disabled for port B bit 0.
Pullup is enabled for port B bit 0.
Pull Enable for Port A Bit 7
0
1
6
PTAPE6
Pullup is disabled for port B bit 1.
Pullup is enabled for port B bit 1.
Pull Enable for Port B Bit 0
0
1
7
PTAPE7
Pullup is disabled for port B bit 2.
Pullup is enabled for port B bit 2.
Pull Enable for Port B Bit 1
0
1
8
PTBPE0
Pullup is disabled for port B bit 3.
Pullup is enabled for port B bit 3.
Pull Enable for Port B Bit 2
0
1
9
PTBPE1
Pullup is disabled for port B bit 4.
Pullup is enabled for port B bit 4.
Pullup is disabled for port A bit 6.
Pullup is enabled for port A bit 6.
Pull Enable for Port A Bit 5
Table continues on the next page...
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Chapter 11 Port Control (PORT)
PORT_PUEL field descriptions (continued)
Field
Description
This control field determines if the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
4
PTAPE4
Pull Enable for Port A Bit 4
This control field determines if the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
3
PTAPE3
Pullup is disabled for port A bit 5.
Pullup is enabled for port A bit 5.
Pullup is disabled for port A bit 4.
Pullup is enabled for port A bit 4.
Pull Enable for Port A Bit 3
This control field determines if the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured as outputs or Hi-Z, this field has no effect.
NOTE: When configuring to use this pin as output high for IIC, the internal pullup device remains active
when PTAPE3 is set. It is automatically disabled to save power when output low.
0
1
2
PTAPE2
Pullup is disabled for port A bit 3.
Pullup is enabled for port A bit 3.
Pull Enable for Port A Bit 2
This control field determines if the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured as outputs or Hi-Z, this field has no effect.
NOTE: When configuring to use this pin as output high for IIC, the internal pullup device remains active
when PTAPE2 is set. It is automatically disabled to save power when output low.
0
1
1
PTAPE1
Pull Enable for Port A Bit 1
This control field determines if the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
0
PTAPE0
Pullup is disabled for port A bit 2.
Pullup is enabled for port A bit 2.
Pullup is disabled for port A bit 1.
Pullup is enabled for port A bit 1.
Pull Enable for Port A Bit 0
This control field determines if the internal pullup device is enabled for the associated PTA pin. For port A
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
Pullup is disabled for port A bit 0.
Pullup is enabled for port A bit 0.
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Port data registers
11.7.3 Port Pullup Enable High Register (PORT_PUEH)
Address: 4004_9000h base + 8h offset = 4004_9008h
Bit
29
28
27
26
23
22
21
20
W
PTHPE2
PTHPE1
PTHPE0
PTGPE3
PTGPE2
PTGPE1
PTGPE0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
PTFPE2
PTFPE1
PTFPE0
PTEPE7
PTEPE6
PTEPE5
PTEPE4
PTEPE3
PTEPE2
PTEPE1
PTEPE0
16
PTFPE3
17
PTFPE4
18
PTFPE5
0
19
PTHPE6
24
PTFPE6
0
25
PTHPE7
30
PTFPE7
R
31
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PORT_PUEH field descriptions
Field
31
PTHPE7
Description
Pull Enable for Port H Bit 7
This control field determines if the internal pullup device is enabled for the associated PTH pin. For port H
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
30
PTHPE6
Pullup is disabled for port H bit 7.
Pullup is enabled for port H bit 7.
Pull Enable for Port H Bit 6
This control field determines if the internal pullup device is enabled for the associated PTH pin. For port H
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
Pullup is disabled for port H bit 6.
Pullup is enabled for port H bit 6.
29–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
PTHPE2
Pull Enable for Port H Bit 2
This control field determines if the internal pullup device is enabled for the associated PTH pin. For port H
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
25
PTHPE1
Pullup is disabled for port H bit 2.
Pullup is enabled for port H bit 2.
Pull Enable for Port H Bit 1
This control field determines if the internal pullup device is enabled for the associated PTH pin. For port H
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
Pullup is disabled for port H bit 1.
Pullup is enabled for port H bit 1.
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Chapter 11 Port Control (PORT)
PORT_PUEH field descriptions (continued)
Field
24
PTHPE0
Description
Pull Enable for Port H Bit 0
This control field determines if the internal pullup device is enabled for the associated PTH pin. For port H
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
Pullup is disabled for port H bit 0.
Pullup is enabled for port H bit 0.
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19
PTGPE3
Pull Enable for Port G Bit 3
This control field determines if the internal pullup device is enabled for the associated PTG pin. For port G
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
18
PTGPE2
Pull Enable for Port G Bit 2
This control field determines if the internal pullup device is enabled for the associated PTG pin. For port G
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
17
PTGPE1
This control field determines if the internal pullup device is enabled for the associated PTG pin. For port G
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTG pin. For port G
pins that are configured as outputs or Hi-Z, this field has no effect.
Pullup is disabled for port G bit 0.
Pullup is enabled for port G bit 0.
Pull Enable for Port F Bit 7
This control field determines if the internal pullup device is enabled for the associated PTF pin. For port F
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
14
PTFPE6
Pullup is disabled for port G bit 1.
Pullup is enabled for port G bit 1.
Pull Enable for Port G Bit 0
0
1
15
PTFPE7
Pullup is disabled for port G bit 2.
Pullup is enabled for port G bit 2.
Pull Enable for Port G Bit 1
0
1
16
PTGPE0
Pullup is disabled for port G bit 3.
Pullup is enabled for port G bit 3.
Pullup is disabled for port F bit 7.
Pullup is enabled for port F bit 7.
Pull Enable for Port F Bit 6
This control field determines if the internal pullup device is enabled for the associated PTF pin. For port F
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
Pullup is disabled for port F bit 6.
Pullup is enabled for port F bit 6.
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Port data registers
PORT_PUEH field descriptions (continued)
Field
13
PTFPE5
Description
Pull Enable for Port F Bit 5
This control field determines if the internal pullup device is enabled for the associated PTF pin. For port F
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
12
PTFPE4
Pull Enable for Port F Bit 4
This control field determines if the internal pullup device is enabled for the associated PTF pin. For port F
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
11
PTFPE3
This control field determines if the internal pullup device is enabled for the associated PTF pin. For port F
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTF pin. For port F
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTF pin. For port F
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTF pin. For port F
pins that are configured as outputs or Hi-Z, this field has no effect.
Pullup is disabled for port F bit 0.
Pullup is enabled for port F bit 0.
Pull Enable for Port E Bit 7
This control field determines if the internal pullup device is enabled for the associated PTE pin. For port E
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
6
PTEPE6
Pullup is disabled for port F bit 1.
Pullup is enabled for port F bit 1.
Pull Enable for Port F Bit 0
0
1
7
PTEPE7
Pullup is disabled for port F bit 2.
Pullup is enabled for port F bit 2.
Pull Enable for Port F Bit 1
0
1
8
PTFPE0
Pullup is disabled for port F bit 3.
Pullup is enabled for port F bit 3.
Pull Enable for Port F Bit 2
0
1
9
PTFPE1
Pullup is disabled for port F bit 4.
Pullup is enabled for port F bit 4.
Pull Enable for Port F Bit 3
0
1
10
PTFPE2
Pullup is disabled for port F bit 5.
Pullup is enabled for port F bit 5.
Pullup is disabled for port E bit 7.
Pullup is enabled for port E bit 7.
Pull Enable for Port E Bit 6
Table continues on the next page...
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Chapter 11 Port Control (PORT)
PORT_PUEH field descriptions (continued)
Field
Description
This control field determines if the internal pullup device is enabled for the associated PTE pin. For port E
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
5
PTEPE5
Pull Enable for Port E Bit 5
This control field determines if the internal pullup device is enabled for the associated PTE pin. For port E
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
4
PTEPE4
This control field determines if the internal pullup device is enabled for the associated PTE pin. For port E
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTE pin. For port E
pins that are configured as outputs or Hi-Z, this field has no effect.
This control field determines if the internal pullup device is enabled for the associated PTE pin. For port E
pins that are configured as outputs or Hi-Z, this field has no effect.
Pullup is disabled for port E bit 2.
Pullup is enabled for port E bit 2.
Pull Enable for Port E Bit 1
This control field determines if the internal pullup device is enabled for the associated PTE pin. For port E
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
0
PTEPE0
Pullup is disabled for port E bit 3.
Pullup is enabled for port E bit 3.
Pull Enable for Port E Bit 2
0
1
1
PTEPE1
Pullup is disabled for port E bit 4.
Pullup is enabled for port E bit 4.
Pull Enable for Port E Bit 3
0
1
2
PTEPE2
Pullup is disabled for port E bit 5.
Pullup is enabled for port E bit 5.
Pull Enable for Port E Bit 4
0
1
3
PTEPE3
Pullup is disabled for port E bit 6.
Pullup is enabled for port E bit 6.
Pullup is disabled for port E bit 1.
Pullup is enabled for port E bit 1.
Pull Enable for Port E Bit 0
This control field determines if the internal pullup device is enabled for the associated PTE pin. For port E
pins that are configured as outputs or Hi-Z, this field has no effect.
0
1
Pullup is disabled for port E bit 0.
Pullup is enabled for port E bit 0.
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Port data registers
11.7.4 Port High Drive Enable Register (PORT_HDRVE)
Address: 4004_9000h base + Ch offset = 4004_900Ch
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
R
PTH1 PTH0 PTE1 PTE0 PTD1 PTD0 PTB5 PTB4
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PORT_HDRVE field descriptions
Field
31–8
Reserved
7
PTH1
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
High Current Drive Capability of PTH1
This read/write field enables the high-current drive capability of PTH1.
0
1
6
PTH0
High Current Drive Capability of PTH0
This read/write field enables the high current drive capability of PTH0.
0
1
5
PTE1
This read/write field enables the high current drive capability of PTE1.
This read/write field enables the high current drive capability of PTE0.
PTE0 is disabled to offer high current drive capability.
PTE0 is enable to offer high current drive capability.
High Current Drive Capability of PTD1
This read/write field enables the high current drive capability of PTD1.
0
1
2
PTD0
PTE1 is disabled to offer high current drive capability.
PTE1 is enabled to offer high current drive capability.
High Current Drive Capability of PTE0
0
1
3
PTD1
PTH0 is disabled to offer high current drive capability.
PTH0 is enabled to offer high current drive capability.
High Current Drive Capability of PTE1
0
1
4
PTE0
PTH1 is disabled to offer high current drive capability.
PTH1 is enabled to offer high current drive capability.
PTD1 is disabled to offer high current drive capability.
PTD1 is enable to offer high current drive capability.
High Current Drive Capability of PTD0
This read/write field enables the high current drive capability of PTD0
Table continues on the next page...
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Chapter 11 Port Control (PORT)
PORT_HDRVE field descriptions (continued)
Field
Description
0
1
1
PTB5
High Current Drive Capability of PTB5
This read/write field enables the high current drive capability of PTB5
0
1
0
PTB4
PTD0 is disabled to offer high current drive capability.
PTD0 is enabled to offer high current drive capability.
PTB5 is disabled to offer high current drive capability.
PTB5 is enabled to offer high current drive capability.
High Current Drive Capability of PTB4
This read/write field enables the high current drive capability of PTB4
0
1
PTB4 is disabled to offer high current drive capability.
PTB4 is enabled to offer high current drive capability.
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Port data registers
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Chapter 12
System Integration Module (SIM)
12.1 Introduction
The system integration module (SIM) provides system control and chip configuration
registers.
12.1.1 Features
The features of the SIM module are listed below.
•
•
•
•
Reset status and device ID information
System interconnection configuration and special pin enable
Pin re-map control
System clock gating control and bus clock divide
12.2 Memory map and register definition
The SIM module contains many fields for selecting the clock source and dividers for
various module clocks.
SIM memory map
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4004_8000
System Reset Status and ID Register (SIM_SRSID)
32
R
See section
12.2.1/158
4004_8004
System Options Register (SIM_SOPT)
32
R/W
See section
12.2.2/161
4004_8008
Pin Selection Register (SIM_PINSEL)
32
R/W
0000_0000h
12.2.3/164
4004_800C
System Clock Gating Control Register (SIM_SCGC)
32
R/W
0000_3000h
12.2.4/166
4004_8010
Universally Unique Identifier Low Register (SIM_UUIDL)
32
R
Undefined
12.2.5/169
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Memory map and register definition
SIM memory map (continued)
Absolute
address
(hex)
Width
Access
(in bits)
Register name
Reset value
Section/
page
4004_8014
Universally Unique Identifier High Register (SIM_UUIDH)
32
R
Undefined
12.2.6/170
4004_8018
BUS Clock Divider Register (SIM_BUSDIV)
32
R/W
See section
12.2.7/170
12.2.1 System Reset Status and ID Register (SIM_SRSID)
Address: 4004_8000h base + 0h offset = 4004_8000h
Bit
31
30
29
28
27
FAMID
R
26
25
24
23
22
SUBFAMID
21
20
19
18
RevID
17
16
PINID
Reset
LVD
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SACKERR
0
MDMAP
SW
LOCKUP
0
POR
PIN
WDOG
LOC
LVD
W
0
0
0
0
0
0
0
0
0
0
0
0
0
1
u*
0
0
0
0
0
0
1
1
0
0
0
R
0
W
Reset
LVD
0
0
0
0
0
0
0
0
* Notes:
• RevID field: Decided by device revision number.
• PINID field: Decided by device pin number.
• u = Unaffected by reset.
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Chapter 12 System Integration Module (SIM)
SIM_SRSID field descriptions
Field
31–28
FAMID
27–24
SUBFAMID
Description
Kinetis family ID
0000
other
KE0x family.
Reserved.
Kinetis sub-family ID
0010
other
KEx2 sub-family
Reserved
23–20
RevID
Device Revision Number
19–16
PINID
Device Pin ID
0000
0001
0010
0011
0100
0101
0110
0111
1000
1010
other
8-pin
16-pin
20-pin
24-pin
32-pin
44-pin
48-pin
64-pin
80-pin
100-pin
Reserved
15–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
SACKERR
Stop Mode Acknowledge Error Reset
Indicates that after an attempt to enter Stop mode, a reset has been caused by the failure of one or more
IICs to acknowledge within approximately one second to enter stop mode.
0
1
Reset is not caused by peripheral failure to acknowledge attempt to enter Stop mode.
Reset is caused by peripheral failure to acknowledge attempt to enter Stop mode.
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
MDMAP
MDM-AP System Reset Request
Indicates a reset has been caused by the host debugger system setting of the System Reset Request field
in the MDM-AP Control Register.
0
1
10
SW
Software
Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and
Reset Control Register in the ARM core.
0
1
9
LOCKUP
Reset is not caused by host debugger system setting of the System Reset Request bit.
Reset is caused by host debugger system setting of the System Reset Request bit.
Reset is not caused by software setting of SYSRESETREQ bit.
Reset caused by software setting of SYSRESETREQ bit
Core Lockup
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Memory map and register definition
SIM_SRSID field descriptions (continued)
Field
Description
Indicates a reset has been caused by the ARM core indication of a LOCKUP event.
0
1
8
Reserved
7
POR
Reset is not caused by core LOCKUP event.
Reset is caused by core LOCKUP event.
This field is reserved.
This read-only field is reserved and always has the value 0.
Power-On Reset
Causes reset by the power-on detection logic. When the internal supply voltage is ramping up, the lowvoltage reset (LVR) status field is also set at that time, to indicate that the reset has occurred while the
internal supply was below the LVR threshold.
NOTE: This bit POR to 1, LVR to uncertain value and reset to 0 at any other conditions.
0
1
6
PIN
External Reset Pin
Causes reset by an active low-level on the external reset pin.
0
1
5
WDOG
2
LOC
Causes reset by the WDOG timer timing out. This reset source may be blocked by WDOG_CS1[EN] = 0.
Reset is not caused by WDOG timeout.
Reset is caused by WDOG timeout.
This field is reserved.
This read-only field is reserved and always has the value 0.
Internal Clock Source Module Reset
Causes reset by an ICS module reset.
0
1
1
LVD
Reset is not caused by external reset pin.
Reset came from external reset pin.
Watchdog (WDOG)
0
1
4–3
Reserved
Reset not caused by POR.
POR caused reset.
Reset is not caused by the ICS module.
Reset is caused by the ICS module.
Low Voltage Detect
If PMC_SPMSC1[LVDRE] is set in Run mode or both PMC_SPMSC1[LVDRE] and
PMC_SPMSC1[LVDSE] are set in Stop mode, and the supply drops below the LVD trip voltage, an LVD
reset will occur. This field is also set by POR.
NOTE: This field is reset to 1 on POR and LVR, and reset to 0 on other reset.
0
1
0
Reserved
Reset is not caused by LVD trip or POR.
Reset is caused by LVD trip or POR.
This field is reserved.
This read-only field is reserved and always has the value 0.
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Chapter 12 System Integration Module (SIM)
12.2.2 System Options Register (SIM_SOPT)
NOTE
RSTPE and NMIE are write-once only on each reset.
Address: 4004_8000h base + 4h offset = 4004_8004h
31
30
29
28
27
26
25
24
23
22
21
DLYACT
R
20
19
18
17
16
0
CLKOE
Bit
DELAY
BUSREF
W
Reset
POR/
LVD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
ADHWT
0
0
0
0
0
0
0
0
0
0
0
0
RSTPE
0
0
0
SWDE
ACIC
RTCC
RXDCE
0
0
RXDFE
0
0
FTMSYNC
W
Reset
POR/
LVD
0
0
TXDME
R
NMIE
1
1
u*
1
u*
1
0
0
* Notes:
• u = Unaffected by reset.
SIM_SOPT field descriptions
Field
31–24
DELAY
Description
FTM2 Trigger Delay
Specifies the delay from FTM2 initial or match trigger to ADC hardware trigger when 1 is written to
ADHWT. The 8-bit modulo value allows the delay from 0 to 255 upon the BUSREF clock settings. This is a
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SIM_SOPT field descriptions (continued)
Field
Description
one-shot counter that starts ticking when the trigger arrives and stops ticking when the counter value
reaches the modulo value that is defined.
23
DLYACT
FTM2 Trigger Delay Active
This read-only field specifies the status if the FTM2 initial or match delay is active. This field is set when an
FTM2 trigger arrives and the delay counter is ticking. Otherwise, this field will be clear.
0
1
22–20
Reserved
19
CLKOE
The delay is inactive.
The delay is active.
This field is reserved.
This read-only field is reserved and always has the value 0.
Bus Clock Output Enable
Enables bus clock output on PTH2
NOTE: 32-pin LQFP and QFN packages have no PTH2/BUSOUT/FTM1_CH0 pin, setting this bit does
not take effect.
0
1
18–16
BUSREF
BUS Clock Output select
Enables bus clock output on PTH2 via an optional prescaler.
000
001
010
011
100
101
110
111
15
TXDME
Enables the UART0_TX output modulated by FTM0 channel 0.
UART0_TX output is connected to pinout directly.
UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout.
FTM2 Synchronization Select
Generates a PWM synchronization trigger to the FTM2 module if 1 is written to this field.
0
1
13
RXDFE
Bus
Bus divided by 2
Bus divided by 4
Bus divided by 8
Bus divided by 16
Bus divided by 32
Bus divided by 64
Bus divided by 128
UART0_TX Modulation Select
0
1
14
FTMSYNC
Bus clock output is disabled on PTH2.
Bus clock output is enabled on PTH2.
No synchronization triggered.
Generates a PWM synchronization trigger to the FTM2 modules.
UART0_RX Filter Select
Enables the UART0_RX input to be filtered by ACMP. When this function is enabled, any signal tagged
with ACMP inputs can be regarded UART0.
0
1
UART0_RX input signal is connected to UART0 module directly.
UART0_RX input signal is filtered by ACMP, then injected to UART0.
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SIM_SOPT field descriptions (continued)
Field
12
RXDCE
Description
UART0_RX Capture Select
Enables the UART0_RX to be captured by FTM0 channel 1.
0
1
11
ACIC
Analog Comparator to Input Capture Enable
Connects the output of ACMP0 to FTM1 input channel 0.
0
1
10
RTCC
Allows the Real-time Counter (RTC) overflow to be captured by FTM1 channel 1.
3
SWDE
Selects the ADC hardware trigger source. All trigger sources start ADC conversion on rising-edge.
Single Wire Debug Port Pin Enable
Enables the PTA4/ACMP0_OUT/SWD_DIO pin to function as SWD_DIO, and PTC4/RTCO/FTM1_CH0/
ACMP0_IN2/SWD_CLK pin function as SWD_CLK. When clear, the two pins function as PTA4 and PTC4.
This pin defaults to the SWD_DIO and SWD_CLK function following any MCU reset.
1
PTA4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTC4/RTCO/FTM1_CH0/
ACMP0_IN2/SWD_CLK as PTC4, RTCO, FTM1_CH0, or ACMP0_IN2 function.
PTA4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTC4/RTCO/FTM1CH0/ACMP0_IN2/
SWD_CLK as SWD_CLK function.
RESET Pin Enable
This write-once field can be written after any reset. When RSTPE is set, the PTA5/IRQ/FTM0_CLK/
RESET pin functions as RESET. When clear, the pin functions as one of its alternative functions. This pin
defaults to RESET following an MCU POR. Other resets will not affect this field. When RSTPE is set, an
internal pullup device on RESET is enabled.
0
1
1
NMIE
RTC overflow as the ADC hardware trigger
PIT overflow as the ADC hardware trigger
FTM2 init trigger with 8-bit programmable delay
FTM2 match trigger with 8-bit programmable delay
This field is reserved.
This read-only field is reserved and always has the value 0.
0
2
RSTPE
RTC overflow is not connected to FTM1 input channel 1.
RTC overflow is connected to FTM1 input channel 1.
ADC Hardware Trigger Source
00
01
10
11
7–4
Reserved
ACMP0 output is not connected to FTM1 input channel 0.
ACMP0 output is connected to FTM1 input channel 0.
Real-Time Counter Capture
0
1
9–8
ADHWT
UART0_RX input signal is connected to the UART0 module only.
UART0_RX input signal is connected to the UART0 module and FTM0 channel 1.
PTA5/IRQ/FTM0_CLK/RESET pin functions as PTA5, IRQ, or FTM0_CLK.
PTA5/IRQ/FTM0_CLK/RESET pin functions as RESET.
NMI Pin Enable
This write-once field can be written after any reset. When NMIE is set, the PTB4/FTM2_CH4/
SPI0_MISO/NMI/ACMP1_IN2 pin functions as NMI. When clear, the pin functions as one of its alternative
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SIM_SOPT field descriptions (continued)
Field
Description
functions. This pin defaults to NMI following an MCU POR. Other resets will not affect this bit. When NMIE
is set, an internal pullup device on NMI is enabled.
0
1
0
Reserved
PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 pin functions as PTB4, FTM2_CH4, SPI0_MISO, or
ACMP1_IN2.
PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 pin functions as NMI.
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.3 Pin Selection Register (SIM_PINSEL)
Address: 4004_8000h base + 8h offset = 4004_8008h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
R
W
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
W
RTCPS
0
I2C0PS
0
SPI0PS
0
UART0PS
0
FTM0PS0
0
FTM0PS1
0
FTM1PS0
0
FTM1PS1
0
FTM2PS0
0
FTM2PS1
0
FTM2PS2
0
FTM2PS3
Reset
Reset
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
SIM_PINSEL field descriptions
Field
Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
FTM2PS3
FTM2_CH3 Port Pin Select
Selects the FTM2_CH3 channel pinout.
0
1
14
FTM2PS2
FTM2_CH2 Port Pin Select
Selects the FTM2_CH2 channel pinout.
0
1
13
FTM2PS1
FTM2_CH3 channels are mapped on PTC3.
FTM2_CH3 channels are mapped on PTD1.
FTM2_CH2 channels are mapped on PTC2.
FTM2_CH2 channels are mapped on PTD0.
FTM2_CH1 Port Pin Select
Selects the FTM2_CH1 channel pinout.
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SIM_PINSEL field descriptions (continued)
Field
Description
0
1
12
FTM2PS0
FTM2_CH0 Port Pin Select
Selects the FTM2_CH0 channel pinout.
0
1
11
FTM1PS1
Selects the FTM1_CH1 channel pinout.
Selects the FTM1_CH0 channel pinout.
Selects the FTM0_CH1 channel pinout.
Selects the FTM0_CH0 channel pinout.
Selects the UART0 pinouts.
UART0_RX and UART0_TX are mapped on PTB0 and PTB1.
UART0_RX and UART0_TX are mapped on PTA2 and PTA3.
SPI0 Pin Select
Selects the SPI0 Pinouts.
0
1
5
I2C0PS
FTM0_CH0 channels are mapped on PTA0.
FTM0_CH0 channels are mapped on PTB2.
UART0 Pin Select
0
1
6
SPI0PS
FTM0_CH1 channels are mapped on PTA1.
FTM0_CH1 channels are mapped on PTB3.
FTM0_CH0 Port Pin Select
0
1
7
UART0PS
FTM1_CH0 channels are mapped on PTC4.
FTM1_CH0 channels are mapped on PTH2.
FTM0_CH1 Port Pin Select
0
1
8
FTM0PS0
FTM1_CH1 channels are mapped on PTC5.
FTM1_CH1 channels are mapped on PTE7.
FTM1_CH0 Port Pin Select
0
1
9
FTM0PS1
FTM2_CH0 channels are mapped on PTC0.
FTM2_CH0 channels are mapped on PTH0.
FTM1_CH1 Port Pin Select
0
1
10
FTM1PS0
FTM2_CH1 channels are mapped on PTC1.
FTM2_CH1 channels are mapped on PTH1.
SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTB2, PTB3, PTB4, and
PTB5.
SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTE0, PTE1, PTE2, and
PTE3.
I2C0 Port Pin Select
Selects the I2C0 port pins.
0
1
I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively.
I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively.
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Memory map and register definition
SIM_PINSEL field descriptions (continued)
Field
Description
4
RTCPS
RTCO Pin Select
Selects the RTCO port pins.
0
1
Reserved
RTCO is mapped on PTC4.
RTCO is mapped on PTC5.
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.4 System Clock Gating Control Register (SIM_SCGC)
Address: 4004_8000h base + Ch offset = 4004_800Ch
0
0
0
0
0
Bit
15
14
13
12
11
FLASH
Reset
0
0
1
1
0
21
KBI0
0
0
0
0
0
10
9
8
7
6
5
0
0
CRC
0
22
0
0
0
20
19
18
17
16
0
UART0
Reset
W
23
KBI1
IRQ
SWD
24
0
ADC
0
25
UART1
0
W
R
26
SPI1
SPI0
I2C
0
0
0
0
0
0
4
3
2
1
0
PIT
RTC
0
0
FTM0
27
UART2
28
FTM1
29
ACMP0
30
ACMP1
R
31
FTM2
Bit
0
0
0
0
0
0
0
SIM_SCGC field descriptions
Field
31
ACMP1
Description
ACMP1 Clock Gate Control
Controls the clock gate to the ACMP1 module.
0
1
30
ACMP0
ACMP0 Clock Gate Control
Controls the clock gate to the ACMP0 module.
0
1
29
ADC
Bus clock to the ACMP1 module is disabled.
Bus clock to the ACMP1 module is enabled.
Bus clock to the ACMP0 module is disabled.
Bus clock to the ACMP0 module is enabled.
ADC Clock Gate Control
Controls the clock gate to the ADC module.
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SIM_SCGC field descriptions (continued)
Field
Description
0
1
28
Reserved
27
IRQ
This field is reserved.
This read-only field is reserved and always has the value 0.
IRQ Clock Gate Control
Controls the clock gate to the IRQ module.
0
1
26
Reserved
25
KBI1
KBI1 Clock Gate Control
Controls the clock gate to the KBI1 module.
22
UART2
Bus clock to the KBI1 module is disabled.
Bus clock to the KBI1 module is enabled.
KBI0 Clock Gate Control
Controls the clock gate to the KBI0 module.
0
1
23
Reserved
Bus clock to the IRQ module is disabled.
Bus clock to the IRQ module is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
24
KBI0
Bus clock to the ADC module is disabled.
Bus clock to the ADC module is enabled.
Bus clock to the KBI0 module is disabled.
Bus clock to the KBI0 module is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
UART2 Clock Gate Control
Controls the clock gate to the UART2 module.
NOTE: 32-pin LQFP and QFN packages have only UART0 and UART1, and this bit is reserved.
0
1
21
UART1
UART1 Clock Gate Control
Ccontrols the clock gate to the UART1 module.
0
1
20
UART0
Bus clock to the UART1 module is disabled.
Bus clock to the UART1 module is enabled.
UART0 Clock Gate Control
Controls the clock gate to the UART0 module.
0
1
19
SPI1
Bus clock to the UART2 module is disabled.
Bus clock to the UART2 module is enabled.
Bus clock to the UART0 module is disabled.
Bus clock to the UART0 module is enabled.
SPI1 Clock Gate Control
Controls the clock gate to the SPI1 module.
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SIM_SCGC field descriptions (continued)
Field
Description
0
1
18
SPI0
SPI0 Clock Gate Control
Controls the clock gate to the SPI0 module.
0
1
17
I2C
13
SWD
Controls the clock gate to the I2C module.
SWD (single wire debugger) Clock Gate Control
Controls the clock gate to the SWD module.
10
CRC
Controls the clock gate to the flash module.
7
FTM2
CRC Clock Gate Control
Controls the clock gate to the CRC module.
Bus clock to the CRC module is disabled.
Bus clock to the CRC module is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
FTM2 Clock Gate Control
Controls the clock gate to the FTM2 module.
0
1
6
FTM1
Bus clock to the flash module is disabled.
Bus clock to the flash module is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
9–8
Reserved
Bus clock to the SWD module is disabled.
Bus clock to the SWD module is enabled.
Flash Clock Gate Control
0
1
11
Reserved
Bus clock to the IIC module is disabled.
Bus clock to the IIC module is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
12
FLASH
Bus clock to the SPI0 module is disabled.
Bus clock to the SPI0 module is enabled.
I2C Clock Gate Control
0
1
16–14
Reserved
Bus clock to the SPI1 module is disabled.
Bus clock to the SPI1 module is enabled.
Bus clock to the FTM2 module is disabled.
Bus clock to the FTM2 module is enabled.
FTM1 Clock Gate Control
Controls the clock gate to the FTM1 module.
0
1
Bus clock to the FTM1 module is disabled.
Bus clock to the FTM1 module is enabled.
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Chapter 12 System Integration Module (SIM)
SIM_SCGC field descriptions (continued)
Field
Description
5
FTM0
FTM0 Clock Gate Control
Controls the clock gate to the FTM0 module.
0
1
4–2
Reserved
Bus clock to the FTM0 module is disabled.
Bus clock to the FTM0 module is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
1
PIT
PIT Clock Gate Control
Controls the clock gate to the PIT module.
0
1
0
RTC
Bus clock to the PIT module is disabled.
Bus clock to the PIT module is enabled.
RTC Clock Gate Control
Controls the clock gate to the RTC module.
0
1
Bus clock to the RTC module is disabled.
Bus clock to the RTC module is enabled.
12.2.5 Universally Unique Identifier Low Register (SIM_UUIDL)
The read-only SIM_UUIDL register contains a series of number to identify the unique
device in the family.
Address: 4004_8000h base + 10h offset = 4004_8010h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID[31:0]
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
SIM_UUIDL field descriptions
Field
ID[31:0]
Description
Universally Unique Identifier
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Memory map and register definition
12.2.6 Universally Unique Identifier High Register (SIM_UUIDH)
The read-only SIM_UUIDH register contains a series of number to identify the unique
device in the family.
Address: 4004_8000h base + 14h offset = 4004_8014h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID[63:32]
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
SIM_UUIDH field descriptions
Field
Description
ID[63:32]
Universally Unique Identifier
12.2.7 BUS Clock Divider Register (SIM_BUSDIV)
This register sets the divide value for the bus clock.
If user wants to use 40 MHz core clock , this bit must be set to 1 before changing
ICS_C2[BDIV]=0x000.
Address: 4004_8000h base + 18h offset = 4004_8018h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
R
W
Reset
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BUSDIV
0
R
W
Reset
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
u*
0
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Chapter 12 System Integration Module (SIM)
* Notes:
• u = Unaffected by reset.
SIM_BUSDIV field descriptions
Field
Description
31–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
BUSDIV
BUS Clock Divider
Sets the divide value for the bus clock.
0
1
Bus clock is same as ICSOUTCLK.
Bus clock is ICSOUTCLK divided by 2.
12.3 Functional description
See Introduction section.
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Functional description
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Chapter 13
Power Management Controller (PMC)
13.1 Introduction
This chapter describes the functionality of the individual modules in the chip’s lowpower modes and the operation of Power Management Controller module.
13.2 Low voltage detect (LVD) system
This device includes a system to protect against low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. This
system consists of a power-on reset (POR) circuit and an LVD circuit with a user
selectable trip voltage, either high (VLVDH) or low (VLVDL). The LVD circuit is enabled
when SPMSC1[LVDE] is set and the trip voltage is selected by SPMSC2[LVDV]. The
LVD is disabled upon entering the Stop mode unless SPMSC1[LVDSE] is set. If
SPMSC1[LVDSE] and SPMSC1[LVDE] are both set, the current consumption will be
greater in Stop mode with the LVD system enabled.
The following figure presents the block diagram of the low-voltage detect (LVD) system.
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Low voltage detect (LVD) system
vDD
LVDV:LVWV
R1
LVD0
-
LVD1
LVD
+
LVW0
LVW1
LVW2
-
LVW3
LVW
+
vBG
Bandgap
R7
vss
Figure 13-1. Low voltage detect (LVD) block diagram
13.2.1 Power-on reset (POR) operation
When power is initially applied to the MCU, or when the supply voltage drops below the
VPOR level, the POR circuit will cause a reset condition. As the supply voltage rises, the
LVD circuit will hold the chip in reset until the supply has risen above the VLVDL level.
Both the SIM_SRSID[POR] and SIM_SRSID[LVD] are set following a POR.
13.2.2 LVD reset operation
The LVD can be configured to generate a reset upon detection of a low-voltage condition
by setting SPMSC1[LVDRE] to 1. After an LVD reset has occurred, the LVD system
will hold the MCU in reset until the supply voltage has risen above the level determined
by LVDV. SIM_SRSID[LVD] is set following either an LVD reset or POR.
13.2.3 LVD enabled in Stop mode
The LVD system is capable of generating a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in Stop (both SPMSC1[LVDE] and
SPMSC1[LVDSE] set to 1) at the time the CPU executes a STOP instruction, then the
voltage regulator remains active during Stop mode.
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Chapter 13 Power Management Controller (PMC)
13.2.4 Low-voltage warning (LVW)
The LVD system has a low voltage warning flag to indicate that the supply voltage is
approaching the LVW voltage. When a low voltage condition is detected and the LVD
circuit is configured for interrupt operation (SPMSC1[LVDE] set, SPMSC1[LVWIE]
set), SPMSC1[LVWF] will be set and LVW interrupt will occur. There are four userselectable trip voltages for the LVW upon each LVDV configuration. The trip voltage is
selected by SPMSC2[LVWV].
13.3 Bandgap reference
This device includes an on-chip bandgap reference (≈1.2 V) connected to the ADC
channel. The bandgap reference voltage will not drop under the full operating voltage
even when the operating voltage is falling. This reference voltage acts as an ideal
reference voltage for accurate measurements.
13.4 Memory map and register descriptions
PMC memory map
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4007_D000
System Power Management Status and Control 1 Register
(PMC_SPMSC1)
8
R/W
1Ch
13.4.1/176
4007_D001
System Power Management Status and Control 2 Register
(PMC_SPMSC2)
8
R/W
00h
13.4.2/177
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Memory map and register descriptions
13.4.1 System Power Management Status and Control 1 Register
(PMC_SPMSC1)
This high-page register contains status and control bits to support the low-voltage
detection function, and to enable the bandgap voltage reference for use by the ADC
module. This register must be written during the user's reset initialization program to set
the desired controls, even if the desired settings are the same as the reset settings.
Address: 4007_D000h base + 0h offset = 4007_D000h
Bit
Read
7
6
LVWF
0
Write
Reset
LVWACK
0
5
4
3
2
LVWIE
LVDRE
LVDSE
LVDE
0
1
1
1
0
1
0
0
0
BGBE
0
PMC_SPMSC1 field descriptions
Field
7
LVWF
Description
Low-Voltage Warning Flag
Indicates the low-voltage warning status.
NOTE: LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply
is already below VLVW. LVWF may be 1 after power-on-reset, therefore, to use LVW interrupt
function, before enabling LVWIE, LVWF must be cleared by writing LVWACK first.
0
1
6
LVWACK
5
LVWIE
Low-Voltage Warning Acknowledge
If LVWF = 1, a low-voltage condition has occurred. To acknowledge this low-voltage warning, write 1 to
LVWACK, which automatically clears LVWF to 0 if the low-voltage warning is no longer present.
Low-Voltage Warning Interrupt Enable
Enables hardware interrupt requests for LVWF.
0
1
4
LVDRE
Low-voltage warning is not present.
Low-voltage warning is present or was present.
Hardware interrupt is disabled (use polling).
Requests a hardware interrupt when LVWF = 1.
Low-Voltage Detect Reset Enable
This write-once bit enables LVD events to generate a hardware reset (provided LVDE = 1).
NOTE: This field can be written only one time after reset. Additional writes are ignored.
If LVDRE = 0, use LVW to monitor status because no flag was assert.
0
1
3
LVDSE
LVD events do not generate hardware resets.
Forces an MCU reset when an enabled low-voltage detect event occurs.
Low-Voltage Detect Stop Enable
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Chapter 13 Power Management Controller (PMC)
PMC_SPMSC1 field descriptions (continued)
Field
Description
Provided LVDE = 1, this read/write field determines whether the low-voltage detect function operates
when the MCU is in Stop mode.
0
1
2
LVDE
Low-voltage detect is disabled during Stop mode.
Low-voltage detect is enabled during Stop mode.
Low-Voltage Detect Enable
This write-once bit enables low-voltage detect logic and qualifies the operation of other fields in this
register.
NOTE: This field can be written only one time after reset. Additional writes are ignored.
0
1
1
Reserved
0
BGBE
LVD logic is disabled.
LVD logic is enabled.
This field is reserved.
Bandgap Buffer Enable
Enables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its
internal channels or bandgap selected as ACMP's reference.
0
1
Bandgap buffer is disabled.
Bandgap buffer is enabled.
13.4.2 System Power Management Status and Control 2 Register
(PMC_SPMSC2)
This register is used to report the status of the low-voltage warning function, and to
configure the Stop mode behavior of the MCU. This register should be written during the
user's reset initialization program to set the desired controls, even if the desired settings
are the same as the reset settings.
Address: 4007_D000h base + 1h offset = 4007_D001h
Bit
7
Read
Write
Reset
0
6
LVDV
0
0
5
4
3
2
LVWV
0
1
0
0
0
0
0
0
0
PMC_SPMSC2 field descriptions
Field
7
Reserved
6
LVDV
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Low-Voltage Detect Voltage Select
This write-once bit selects the low-voltage detect (LVD) trip point setting. See data sheet for details.
Table continues on the next page...
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Memory map and register descriptions
PMC_SPMSC2 field descriptions (continued)
Field
Description
0
1
5–4
LVWV
Low-Voltage Warning Voltage Select
Selects the low-voltage warning (LVW) trip point voltage. See data sheet for details.
00
01
10
11
Reserved
Low trip point is selected (VLVD = VLVDL).
High trip point is selected (VLVD = VLVDH).
Low trip point is selected (VLVW = VLVW1).
Middle 1 trip point is selected (VLVW = VLVW2).
Middle 2 trip point is selected (VLVW = VLVW3).
High trip point is selected (VLVW = VLVW4).
This field is reserved.
This read-only field is reserved and always has the value 0.
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Chapter 14
Miscellaneous Control Module (MCM)
14.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control
functions.
14.1.1 Features
The MCM includes the following features:
• Program-visible information on the platform configuration
• Flash controller speculation buffer and cache configurations
14.2 Memory map/register descriptions
The memory map and register descriptions found here describe the registers using byte
addresses. The registers can be written only when in supervisor mode.
MCM memory map
Absolute
address
(hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
F000_3008
Crossbar Switch (AXBS) Slave Configuration
(MCM_PLASC)
16
R
0007h
14.2.1/180
F000_300A
Crossbar Switch (AXBS) Master Configuration
(MCM_PLAMC)
16
R
0001h
14.2.2/180
32
R/W
0000_0800h
14.2.3/181
F000_300C Platform Control Register (MCM_PLACR)
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Memory map/register descriptions
14.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
PLASC is a 16-bit read-only register identifying the presence/absence of bus slave
connections to the device’s crossbar switch.
Address: F000_3000h base + 8h offset = F000_3008h
Bit
15
14
13
12
Read
11
10
9
8
7
6
5
4
0
3
2
1
0
0
1
1
1
ASC
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
MCM_PLASC field descriptions
Field
Description
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
ASC
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's
slave input port.
0
1
A bus slave connection to AXBS input port n is absent.
A bus slave connection to AXBS input port n is present.
14.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master
connections to the device's crossbar switch.
Address: F000_3000h base + Ah offset = F000_300Ah
Bit
15
14
13
12
Read
11
10
9
8
7
6
5
4
0
3
2
1
0
0
0
0
1
AMC
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
MCM_PLAMC field descriptions
Field
15–8
Reserved
AMC
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input
port.
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Chapter 14 Miscellaneous Control Module (MCM)
MCM_PLAMC field descriptions (continued)
Field
Description
0
1
A bus master connection to AXBS input port n is absent
A bus master connection to AXBS input port n is present
14.2.3 Platform Control Register (MCM_PLACR)
The speculation buffer and cache in the flash memory controller is configurable via
PLACR[15:10 ].
The speculation buffer is enabled only for instructions after reset. It is possible to have
these states for the speculation buffer:
DFCS
EFDS
Description
0
0
Speculation buffer is on for instruction
and off for data.
0
1
Speculation buffer is on for instruction
and on for data.
1
X
Speculation buffer is off.
The cache in flash controller is enabled and caching both instruction and data type fetches
after reset. It is possible to have these states for the cache:
DFCC
DFCIC
DFCDA
Description
0
0
0
Cache is on for both
instruction and data.
0
0
1
Cache is on for instruction
and off for data.
0
1
0
Cache is off for instruction
and on for data.
0
1
1
Cache is off for both
instruction and data.
1
X
X
Cache is off.
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Memory map/register descriptions
Address: F000_3000h base + Ch offset = F000_300Ch
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
R
ESFC
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
DFCS
EFDS
DFCC
DFCIC
DFCDA
0
0
0
0
1
W
Reset
0
CFCC
0
R
0
0
0
0
0
0
MCM_PLACR field descriptions
Field
31–17
Reserved
16
ESFC
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Enable Stalling Flash Controller
Enables stalling flash controller when flash is busy.
When software needs to access the flash memory while a flash memory resource is being manipulated by
a flash command, software can enable a stall mechanism to avoid a read collision. The stall mechanism
allows software to execute code from the same block on which flash operations are being performed.
However, software must ensure the sector the flash operations are being performed on is not the same
sector from which the code is executing.
ESFC enables the stall mechanism. This bit must be set only just before the flash operation is executed
and must be cleared when the operation completes.
0
1
15
DFCS
Disable Flash Controller Speculation
Disables flash controller speculation.
0
1
14
EFDS
Disable stalling flash controller when flash is busy.
Enable stalling flash controller when flash is busy.
Enable flash controller speculation.
Disable flash controller speculation.
Enable Flash Data Speculation
Enables flash data speculation.
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Chapter 14 Miscellaneous Control Module (MCM)
MCM_PLACR field descriptions (continued)
Field
Description
0
1
13
DFCC
Disable Flash Controller Cache
Disables flash controller cache.
0
1
12
DFCIC
Disables flash controller instruction caching.
Reserved
Enable flash controller instruction caching.
Disable flash controller instruction caching.
Disable Flash Controller Data Caching
Disables flash controller data caching.
0
1
10
CFCC
Enable flash controller cache.
Disable flash controller cache.
Disable Flash Controller Instruction Caching
0
1
11
DFCDA
Disable flash data speculation.
Enable flash data speculation.
Enable flash controller data caching
Disable flash controller data caching.
Clear Flash Controller Cache
Writing a 1 to this field clears the cache. Writing a 0 to this field is ignored. This field always reads as 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
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Memory map/register descriptions
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Chapter 15
Peripheral Bridge (AIPS-Lite)
15.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.
The peripheral bridge occupies 64 MB of the address space, which is divided into
peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes
separate clock enable inputs for each of the slots to accommodate slower peripherals.
15.1.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
15.1.2 General operation
The slave devices connected to the peripheral bridge are modules which contain a
programming model of control and status registers. The system masters read and write
these registers through the peripheral bridge. The peripheral bridge performs a bus
protocol conversion of the master transactions and generates the following as inputs to
the peripherals:
• Module enables
• Module addresses
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Functional description
• Transfer attributes
• Byte enables
• Write data
The peripheral bridge selects and captures read data from the peripheral interface and
returns it to the crossbar switch.
The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is
allocated one or more 4-KB block(s) of the memory map.
The AIPS-Lite module uses the data width of accessed peripheral to perform proper data
byte lane routing; bus decomposition (bus sizing) is performed when the access size is
larger than the peripheral's data width.
15.2 Functional description
The peripheral bridge functions as a bus protocol translator between the crossbar switch
and the slave peripheral bus.
The peripheral bridge manages all transactions destined for the attached slave devices and
generates select signals for modules on the peripheral bus by decoding accesses within
the attached address space.
15.2.1 Access support
All combinations of access size and peripheral data port width are supported. An access
that is larger than the target peripheral's data width will be decomposed to multiple,
smaller accesses. Bus decomposition is terminated by a transfer error caused by an access
to an empty register area.
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Chapter 16
Watchdog Timer (WDOG)
16.1 Introduction
The Watchdog Timer (WDOG) module is an independent timer that is available for
system use. It provides a safety feature to ensure that software is executing as planned
and that the CPU is not stuck in an infinite loop or executing unintended code. If the
WDOG module is not serviced (refreshed) within a certain period, it resets the MCU.
16.1.1 Features
Features of the WDOG module include:
• Configurable clock source inputs independent from the bus clock
• Internal 32 kHz RC oscillator
• Internal 1 kHz RC oscillator
• External clock source
• Programmable timeout period
• Programmable 16-bit timeout value
• Optional fixed 256 clock prescaler when longer timeout periods are needed
• Robust write sequence for counter refresh
• Refresh sequence of writing 0x02A6 and then 0x80B4 within 16 bus clocks
• Window mode option for the refresh mechanism
• Programmable 16-bit window value
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Introduction
• Provides robust check that program flow is faster than expected
• Early refresh attempts trigger a reset.
• Optional timeout interrupt to allow post-processing diagnostics
• Interrupt request to CPU with interrupt vector for an interrupt service routine
(ISR)
• Forced reset occurs 128 bus clocks after the interrupt vector fetch.
• Configuration bits are write-once-after-reset to ensure watchdog configuration cannot
be mistakenly altered.
• Robust write sequence for unlocking write-once configuration bits
• Unlock sequence of writing 0x20C5 and then 0x28D9 within 16 bus clocks for
allowing updates to write-once configuration bits
• Software must make updates within 128 bus clocks after unlocking and before
WDOG closing unlock window.
16.1.2 Block diagram
The following figure provides a block diagram of the WDOG module.
16-bit Timeout Value Register
0x02A6
0x80B4
Refresh Sequence
Write Control
32K CLK
MUX
1K CLK
Compare Logic
Counter
Overflow
16-bit Counter Register
Counter
Reset
MUX
BUS CLK
EXT CLK
Control
Logic
128 Bus
Clock Delay
MUX
Backup Reset
CPU Reset
256
Compare Logic
EN
UPDATE
16-bit Window Register
Window
Protect
IRQ Interrupt
128 Bus Cycle
Disable Protect
0x20C5 Control Status
0x28D9 Bit Write Control
CLK
PRES WIN
INT
Figure 16-1. WDOG block diagram
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Chapter 16 Watchdog Timer (WDOG)
16.2 Memory map and register definition
NOTE
If the device uses half-word to access WDOG_CNT,
WDOG_TOVAL and WDOG_WIN, the transposed 16-bit
bytes must follow the format of LowByte:HighByte. So 8-bit
R/W is preferred.
WDOG memory map
Absolute
address
(hex)
Width
Access
(in bits)
Register name
Reset value
Section/
page
4005_2000
Watchdog Control and Status Register 1 (WDOG_CS1)
8
R/W
80h
16.2.1/189
4005_2001
Watchdog Control and Status Register 2 (WDOG_CS2)
8
R/W
01h
16.2.2/191
4005_2002
Watchdog Counter Register: High (WDOG_CNTH)
8
R
00h
16.2.3/192
4005_2003
Watchdog Counter Register: Low (WDOG_CNTL)
8
R
00h
16.2.4/192
4005_2004
Watchdog Timeout Value Register: High (WDOG_TOVALH)
8
R/W
00h
16.2.5/193
4005_2005
Watchdog Timeout Value Register: Low (WDOG_TOVALL)
8
R/W
04h
16.2.6/193
4005_2006
Watchdog Window Register: High (WDOG_WINH)
8
R/W
00h
16.2.7/194
4005_2007
Watchdog Window Register: Low (WDOG_WINL)
8
R/W
00h
16.2.8/194
16.2.1 Watchdog Control and Status Register 1 (WDOG_CS1)
This section describes the function of Watchdog Control and Status Register 1.
NOTE
TST is cleared (0:0) on POR only. Any other reset does not
affect the value of this field.
Address: 4005_2000h base + 0h offset = 4005_2000h
Bit
Read
Write
Reset
7
6
5
EN
INT
UPDATE
1
0
0
4
3
TST
0
0
2
1
0
DBG
WAIT
STOP
0
0
0
WDOG_CS1 field descriptions
Field
7
EN
Description
Watchdog Enable
This write-once bit enables the watchdog counter to start counting.
0
1
Watchdog disabled.
Watchdog enabled.
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Memory map and register definition
WDOG_CS1 field descriptions (continued)
Field
6
INT
Description
Watchdog Interrupt
This write-once bit configures the watchdog to generate an interrupt request upon a reset-triggering event
(timeout or illegal write to the watchdog), prior to forcing a reset. After the interrupt vector fetch, the reset
occurs after a delay of 128 bus clocks.
0
1
5
UPDATE
Allow updates
This write-once bit allows software to reconfigure the watchdog without a reset.
0
1
4–3
TST
Watchdog interrupts are disabled. Watchdog resets are not delayed.
Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks.
Updates not allowed. After the initial configuration, the watchdog cannot be later modified without
forcing a reset.
Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks
after performing the unlock write sequence.
Watchdog Test
Enables the fast test mode. The test mode allows software to exercise all bits of the counter to
demonstrate that the watchdog is functioning properly. See the Fast testing of the watchdog section.
This write-once field is cleared (0:0) on POR only. Any other reset does not affect the value of this field.
00
01
10
11
2
DBG
Debug Enable
This write-once bit enables the watchdog to operate when the chip is in debug mode.
0
1
1
WAIT
Watchdog disabled in chip debug mode.
Watchdog enabled in chip debug mode.
Wait Enable
This write-once bit enables the watchdog to operate when the chip is in wait mode.
0
1
0
STOP
Watchdog test mode disabled.
Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software
should use this setting to indicate that the watchdog is functioning normally in user mode.
Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with
WDOG_TOVALL.
Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with
WDOG_TOVALH.
Watchdog disabled in chip wait mode.
Watchdog enabled in chip wait mode.
Stop Enable
This write-once bit enables the watchdog to operate when the chip is in stop mode.
0
1
Watchdog disabled in chip stop mode.
Watchdog enabled in chip stop mode.
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Chapter 16 Watchdog Timer (WDOG)
16.2.2 Watchdog Control and Status Register 2 (WDOG_CS2)
This section describes the function of the watchdog control and status register 2.
Address: 4005_2000h base + 1h offset = 4005_2001h
Bit
Read
Write
Reset
7
WIN
6
5
FLG
0
w1c
0
0
0
4
3
2
1
0
PRES
0
0
0
CLK
0
0
1
WDOG_CS2 field descriptions
Field
7
WIN
Description
Watchdog Window
This write-once bit enables window mode. See the Window mode section.
0
1
6
FLG
Watchdog Interrupt Flag
This bit is an interrupt indicator when INT is set in control and status register 1. Write 1 to clear it.
0
1
5
Reserved
4
PRES
CLK
No interrupt occurred.
An interrupt occurred.
This field is reserved.
This read-only field is reserved and always has the value 0.
Watchdog Prescalar
This write-once bit enables a fixed 256 pre-scaling of watchdog counter reference clock. (The block
diagram shows this clock divider option.)
0
1
3–2
Reserved
Window mode disabled.
Window mode enabled.
256 prescalar disabled.
256 prescalar enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Watchdog Clock
This write-once field indicates the clock source that feeds the watchdog counter. See the Clock source
section.
00
01
10
11
Bus clock.
1 kHz internal low-power oscillator (LPOCLK).
32 kHz internal oscillator (ICSIRCLK).
External clock source.
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Memory map and register definition
16.2.3 Watchdog Counter Register: High (WDOG_CNTH)
This section describes the watchdog counter registers: high (CNTH) and low (CNTL)
combined.
The watchdog counter registers CNTH and CNTL provide access to the value of the freerunning watchdog counter. Software can read the counter registers at any time.
Software cannot write directly to the watchdog counter; however, two write sequences to
these registers have special functions:
1. The refresh sequence resets the watchdog counter to 0x0000. See the Refreshing the
Watchdog section.
2. The unlock sequence allows the watchdog to be reconfigured without forcing a reset
(when WDOG_CS1[UPDATE] = 1). See the Example code: Reconfiguring the
Watchdog section.
NOTE
All other writes to these registers are illegal and force a reset.
Address: 4005_2000h base + 2h offset = 4005_2002h
Bit
7
6
5
4
Read
3
2
1
0
0
0
0
0
CNTHIGH
Write
Reset
0
0
0
0
WDOG_CNTH field descriptions
Field
CNTHIGH
Description
High byte of the Watchdog Counter
16.2.4 Watchdog Counter Register: Low (WDOG_CNTL)
See the description of the WDOG_CNTH register.
Address: 4005_2000h base + 3h offset = 4005_2003h
Bit
7
6
5
4
Read
3
2
1
0
0
0
0
0
CNTLOW
Write
Reset
0
0
0
0
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Chapter 16 Watchdog Timer (WDOG)
WDOG_CNTL field descriptions
Field
CNTLOW
Description
Low byte of the Watchdog Counter
16.2.5 Watchdog Timeout Value Register: High (WDOG_TOVALH)
This section describes the watchdog timeout value registers: high (WDOG_TOVALH)
and low (WDOG_TOVALL) combined. WDOG_TOVALH and WDOG_TOVALL
contains the 16-bit value used to set the timeout period of the watchdog.
The watchdog counter (WDOG_CNTH and WDOG_CNTL) is continuously compared
with the timeout value (WDOG_TOVALH and WDOG_TOVALL). If the counter
reaches the timeout value, the watchdog forces a reset.
NOTE
Do not write 0 to the Watchdog Timeout Value Register,
otherwise, the watchdog always generates a reset.
Address: 4005_2000h base + 4h offset = 4005_2004h
Bit
Read
Write
Reset
7
6
5
4
3
2
1
0
0
0
0
0
TOVALHIGH
0
0
0
0
WDOG_TOVALH field descriptions
Field
TOVALHIGH
Description
High byte of the timeout value
16.2.6 Watchdog Timeout Value Register: Low (WDOG_TOVALL)
See the description of the WDOG_TOVALH register.
NOTE
All the bits reset to 0 in read.
Address: 4005_2000h base + 5h offset = 4005_2005h
Bit
Read
Write
Reset
7
6
5
4
3
2
1
0
0
1
0
0
TOVALLOW
0
0
0
0
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Memory map and register definition
WDOG_TOVALL field descriptions
Field
TOVALLOW
Description
Low byte of the timeout value
16.2.7 Watchdog Window Register: High (WDOG_WINH)
This section describes the watchdog window registers: high (WDOG_WINH) and low
(WDOG_WINL) combined. When window mode is enabled (WDOG_CS2[WIN] is set),
WDOG_WINH and WDOG_WINL determine the earliest time that a refresh sequence is
considered valid. See the Watchdog refresh mechanism section.
WDOG_WINH and WDOG_WINL must be less than WDOG_TOVALH and
WDOG_TOVALL.
Address: 4005_2000h base + 6h offset = 4005_2006h
Bit
Read
Write
Reset
7
6
5
4
3
2
1
0
0
0
0
0
WINHIGH
0
0
0
0
WDOG_WINH field descriptions
Field
WINHIGH
Description
High byte of Watchdog Window
16.2.8 Watchdog Window Register: Low (WDOG_WINL)
See the description of the WDOG_WINH register.
Address: 4005_2000h base + 7h offset = 4005_2007h
Bit
Read
Write
Reset
7
6
5
4
3
2
1
0
0
0
0
0
WINLOW
0
0
0
0
WDOG_WINL field descriptions
Field
WINLOW
Description
Low byte of Watchdog Window
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Chapter 16 Watchdog Timer (WDOG)
16.3 Functional description
The WDOG module provides a fail safe mechanism to ensure the system can be reset to a
known state of operation in case of system failure, such as the CPU clock stopping or
there being a run away condition in the software code. The watchdog counter runs
continuously off a selectable clock source and expects to be serviced (refreshed)
periodically. If it is not, it resets the system.
The timeout period, window mode, and clock source are all programmable but must be
configured within 128 bus clocks after a reset.
16.3.1 Watchdog refresh mechanism
The watchdog resets the MCU if the watchdog counter is not refreshed. A robust refresh
mechanism makes it very unlikely that the watchdog can be refreshed by runaway code.
To refresh the watchdog counter, software must execute a refresh write sequence before
the timeout period expires. In addition, if window mode is used, software must not start
the refresh sequence until after the time value set in the WDOG_WINH and
WDOG_WINL registers. See the following figure.
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Functional description
WDOG counter
WDOG_TOVALH and
WDOG_TOVALL
WDOG_WINH and
WDOG_WINL
Refresh opportunity
in window mode
0
Refresh opportunity (not in window mode)
Time
Figure 16-10. Refresh opportunity for the Watchdog counter
16.3.1.1 Window mode
Software finishing its main control loop faster than expected could be an indication of a
problem. Depending on the requirements of the application, the WDOG can be
programmed to force a reset when refresh attempts are early.
When Window mode is enabled, the watchdog must be refreshed after the counter has
reached a minimum expected time value; otherwise, the watchdog resets the MCU. The
minimum expected time value is specified in the WDOG_WINH:L registers. Setting
CS1[WIN] enables Window mode.
16.3.1.2 Refreshing the Watchdog
The refresh write sequence is a write of 0x02A6 followed by a write of 0x80B4 to the
WDOG_CNTH and WDOG_CNTL registers. The write of the 0x80B4 must occur within
16 bus clocks after the write of 0x02A6; otherwise, the watchdog resets the MCU.
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Chapter 16 Watchdog Timer (WDOG)
Note
Before starting the refresh sequence, disable global interrupts.
Otherwise, an interrupt could effectively invalidate the refresh
sequence if writing the four bytes takes more than 16 bus
clocks. Re-enable interrupts when the sequence is finished.
16.3.1.3 Example code: Refreshing the Watchdog
The following code segment shows the refresh write sequence of the WDOG module.
NOTE
The following example code combines the 8-bit
WDOG_CNTH and WDOG_CNTL as one 16-bit
WDOG_CNT, the 8-bit WDOG_TOVALH and
WDOG_TOVALL as one 16-bit WDOG_TOVAL,
WDOG_WINH and WDOG_WINL as WDOG_WIN and uses
16-bit access.
/* Refresh watchdog */
for (;;) // main loop
{
...
DisableInterrupts; // disable global interrupt
WDOG_CNT = 0x02A6; // write the 1st refresh word
WDOG_CNT = 0x80B4; // write the 2nd refresh word to refresh counter
EnableInterrupts; // enable global interrupt
}
...
16.3.2 Configuring the Watchdog
All watchdog control bits, timeout value, and window value are write-once after reset.
This means that after a write has occurred they cannot be changed unless a reset occurs.
This provides a robust mechanism to configure the watchdog and ensure that a runaway
condition cannot mistakenly disable or modify the watchdog configuration after
configured.
This is guaranteed by the user configuring the window and timeout value first, followed
by the other control bits, and ensuring that CS1[UPDATE] is also set to 0. The new
configuration takes effect only after all registers except WDOG_CNTH:L are written
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Functional description
once after reset. Otherwise, the WDOG uses the reset values by default. If window mode
is not used (CS2[WIN] is 0), writing to WDOG_WINH:L is not required to make the new
configuration take effect.
16.3.2.1 Reconfiguring the Watchdog
In some cases (such as when supporting a bootloader function), users may want to
reconfigure or disable the watchdog without forcing a reset first. By setting
CS1[UPDATE] to a 1 on the initial configuration of the watchdog after a reset, users can
reconfigure the watchdog at any time by executing an unlock sequence. (Conversely, if
CS1[UPDATE] remains 0, the only way to reconfigure the watchdog is by initiating a
reset.) The unlock sequence is similar to the refresh sequence but uses different values.
16.3.2.2 Unlocking the Watchdog
The unlock sequence is a write to the WDOG_CNTH:L registers of 0x20C5 followed by
0x28D9 within 16 bus clocks at any time after the watchdog has been configured. On
completing the unlock sequence, the user must reconfigure the watchdog within 128 bus
clocks; otherwise, the watchdog forces a reset to the MCU.
NOTE
Due to 128 bus clocks requirement for reconfiguring the
watchdog, some delays must be inserted before executing
STOP or WAIT instructions after reconfiguring the watchdog.
This ensures that the watchdog's new configuration takes effect
before MCU enters low power mode. Otherwise, the MCU may
not be waken up from low power mode.
16.3.2.3 Example code: Reconfiguring the Watchdog
The following code segment shows an example reconfiguration of the WDOG module.
/* Initialize watchdog with ~1-kHz clock source, ~1s time-out */
DisableInterrupts; // disable global interrupt
WDOG_CNT = 0x20C5; // write the 1st unlock word
WDOG_CNT = 0x28D9; // write the 2nd unlock word
WDOG_TOVAL = 1000; // setting timeout value
WDOG_CS2 = WDOG_CS2_CLK_MASK; // setting 1-kHz clock source
WDOG_CS1 = WDOG_CS1_EN_MASK; // enable counter running
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EnableInterrupts; // enable global interrupt
16.3.3 Clock source
The watchdog counter has four clock source options selected by programming
CS2[CLK]:
• bus clock
• internal Low-Power Oscillator (LPO) running at approximately 1 kHz (This is the
default source.)
• internal 32 kHz clock
• external clock
The options allow software to select a clock source independent of the bus clock for
applications that need to meet more robust safety requirements. Using a clock source
other than the bus clock ensures that the watchdog counter continues to run if the bus
clock is somehow halted; see Backup reset.
An optional fixed prescaler for all clock sources allows for longer timeout periods. When
CS2[PRES] is set, the clock source is prescaled by 256 before clocking the watchdog
counter.
The following table summarizes the different watchdog timeout periods available.
Table 16-10. Watchdog timeout availability
Reference clock
Internal ~1 kHz (LPO)
Internal ~32 kHz
1 MHz (from bus or external)
20 MHz (from bus or external)
Prescaler
Watchdog time-out availability
Pass through
~1 ms–65.5 s1
÷256
~256 ms–16,777 s
Pass through
~31.25 µs–2.048 s
÷256
~8 ms–524.3 s
Pass through
1 µs–65.54 ms
÷256
256 µs–16.777 s
Pass through
50 ns–3.277 ms
÷256
12.8 µs–838.8 ms
1. The default timeout value after reset is approximately 4 ms.
NOTE
When the programmer switches clock sources during
reconfiguration, the watchdog hardware holds the counter at
zero for 2.5 periods of the previous clock source and 2.5
periods of the new clock source after the configuration time
period (128 bus clocks) ends. This delay ensures a smooth
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Functional description
transition before restarting the counter with the new
configuration.
16.3.4 Using interrupts to delay resets
When interrupts are enabled (CS1[INT] = 1), the watchdog first generates an interrupt
request upon a reset triggering event (such as a counter timeout or invalid refresh
attempt). The watchdog delays forcing a reset for 128 bus clocks to allow the interrupt
service routine (ISR) to perform tasks, such as analyzing the stack to debug code.
When interrupts are disabled (CS1[INT] = 0), the watchdog does not delay forcing a
reset.
16.3.5 Backup reset
NOTE
A clock source other than the bus clock must be used as the
reference clock for the counter; otherwise, the backup reset
function is not available.
The backup reset function is a safeguard feature that independently generates a reset in
case the main WDOG logic loses its clock (the bus clock) and can no longer monitor the
counter. If the watchdog counter overflows twice in succession (without an intervening
reset), the backup reset function takes effect and generates a reset.
16.3.6 Functionality in debug and low-power modes
By default, the watchdog is not functional in Active Background mode, Wait mode, or
Stop mode. However, the watchdog can remain functional in these modes as follows:
• For Active Background mode, set CS1[DBG]. (This way the watchdog is functional
in Active Background mode even when the CPU is held by the Debug module.)
• For Wait mode, set CS1[WAIT].
• For Stop mode, set CS1[STOP].
NOTE
The watchdog can not generate interrupt in Stop mode even if
CS1[STOP] is set and will not wake the MCU from Stop mode.
It can generate reset during Stop mode.
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For Active Background mode and Stop mode, in addition to the
above configurations, a clock source other than the bus clock
must be used as the reference clock for the counter; otherwise,
the watchdog cannot function.
16.3.7 Fast testing of the watchdog
Before executing application code in safety critical applications, users are required to test
that the watchdog works as expected and resets the MCU. Testing every bit of a 16-bit
counter by letting it run to the overflow value takes a relatively long time (64 kHz
clocks).
To help minimize the startup delay for application code after reset, the watchdog has a
feature to test the watchdog more quickly by splitting the counter into its constituent
byte-wide stages. The low and high bytes are run independently and tested for timeout
against the corresponding byte of the timeout value register. (For complete coverage
when testing the high byte of the counter, the test feature feeds the input clock via the 8th
bit of the low byte, thus ensuring that the overflow connection from the low byte to the
high byte is tested.)
Using this test feature reduces the test time to 512 clocks (not including overhead, such as
user configuration and reset vector fetches). To further speed testing, use a faster clock
(such as the bus clock) for the counter reference.
On a power-on reset, the POR bit in the system reset register is set, indicating the user
should perform the WDOG fast test.
16.3.7.1 Testing each byte of the counter
The test procedure follows these steps:
1. Program the preferred watchdog timeout value in the WDOG_TOVALH and
WDOG_TOVALL registers during the watchdog configuration time period.
2. Select a byte of the counter to test using the WDOG_CS1[TST] = 10b for the low
byte; WDOG_CS1[TST] = 11b for the high byte.
3. Wait for the watchdog to timeout. Optionally, in the idle loop, increment RAM
locations as a parallel software counter for later comparison. Because the RAM is not
affected by a watchdog reset, the timeout period of the watchdog counter can be
compared with the software counter to verify the timeout period has occurred as
expected.
4. The watchdog counter times out and forces a reset.
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Functional description
5. Confirm the WDOG flag in the system reset register is set, indicating that the
watchdog caused the reset. (The POR flag remains clear.)
6. Confirm that WDOG_CS1[TST] shows a test (10b or 11b) was performed.
If confirmed, the count and compare functions work for the selected byte. Repeat the
procedure, selecting the other byte in step 2.
NOTE
WDOG_CS1[TST] is cleared by a POR only and not affected
by other resets.
16.3.7.2 Entering user mode
After successfully testing the low and high bytes of the watchdog counter, the user can
configure WDOG_CS1[TST] to 01b to indicate the watchdog is ready for use in
application user mode. Thus if a reset occurs again, software can recognize the reset
trigger as a real watchdog reset caused by runaway or faulty application code.
As an ongoing test when using the default 1-kHz clock source, software can periodically
read the WDOG_CNTH and WDOG_CNTL registers to ensure the counter is being
incremented.
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Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modifywrite memory operations to the peripheral address space in Cortex-M0+ based
microcontrollers.
This architectural capability is also known as "decorated storage" as it defines a
mechanism for providing additional semantics for load and store operations to memorymapped peripherals beyond just the reading and writing of data values to the addressed
memory locations. In the BME definition, the "decoration", that is, the additional
semantic information, is encoded into the peripheral address used to reference the
memory.
By combining the basic load and store instructions of the ARM Cortex-M instruction set
architecture (v6M, v7M) with the concept of decorated storage provided by the BME, the
resulting implementation provides a robust and efficient read-modify-write capability to
this class of ultra low-end microcontrollers. The resulting architectural capability defined
by this core platform function is targeted at the manipulation of n-bit fields in peripheral
registers and is consistent with I/O hardware addressing in the Embedded C standard. For
most BME commands, a single core read or write bus cycle is converted into an atomic
read-modify-write, that is, an indivisible "read followed by a write" bus sequence.
BME decorated references are only available on system bus transactions generated by the
processor core and targeted at the standard 512 KB peripheral address space based at
0x4000_00001. The decoration semantic is embedded into address bits[28:19], creating a
448 MB space at addresses 0x4400_0000–0x5FFF_FFFF for AIPS; these bits are
stripped out of the actual address sent to the peripheral bus controller and used by the
BME to define and control its operation.
1.
To be perfectly accurate, the peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000 plus a 4
KB space based at 0x400F_F000 for GPIO accesses. This organization provides compatibility with the Kinetis K Family.
Attempted accesses to the memory space located between 0x4008_0000 - 0x400F_EFFF are error terminated due to an
illegal address.
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Introduction
17.1.1 Overview
The following figure is a generic block diagram of the processor core and platform for
this class of ultra low-end microcontrollers.
Cortex-M0+ Core
Dbg
CM0+ Core Platform
Fetch
NVIC
AGU
Dec
Rn
LD/ST
SHFT
ALU
MUL
IO Port
32
PRAM
RAM
Array
GPIO
m0
s1
AXBS
-Lite
32
s2
BME
PBRIDGE
Slave
Peripherals
s0
FMC
32
NVM
Array
Note: BME can be accessed only by the core.
Figure 17-1. Cortex-M0+ core platform block diagram
As shown in the block diagram, the BME module interfaces to a switch AHB slave port
as its primary input and sources an AHB bus output to the Peripheral Bridge (PBRIDGE)
controller. The BME hardware microarchitecture is a 2-stage pipeline design matching
the protocol of the AMBA-AHB system bus interfaces. The PBRIDGE module converts
the AHB system bus protocol into the IPS/APB protocol used by the attached slave
peripherals.
17.1.2 Features
The key features of the BME include:
• Lightweight implementation of decorated storage for selected address spaces
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Chapter 17 Bit Manipulation Engine (BME)
•
•
•
•
•
•
•
•
•
Additional access semantics encoded into the reference address
Resides between a switch slave port and a peripheral bridge bus controller
Two-stage pipeline design matching the AHB system bus protocol
Combinationally passes non-decorated accesses to peripheral bridge bus controller
Conversion of decorated loads and stores from processor core into atomic readmodify-writes
Decorated loads support unsigned bit field extracts, load-and-{set,clear} 1-bit
operations
Decorated stores support bit field inserts, logical AND, OR, and XOR operations
Support for byte, halfword and word-sized decorated operations
Supports minimum signal toggling on AHB output bus to reduce power dissipation
17.1.3 Modes of operation
The BME module does not support any special modes of operation. As a memorymapped device located on a crossbar slave AHB system bus port, BME responds strictly
on the basis of memory addresses for accesses to the peripheral bridge bus controller.
All functionality associated with the BME module resides in the core platform's clock
domain; this includes its connections with the crossbar slave port and the PBRIDGE bus
controller.
17.2 Memory map and register definition
The BME module provides a memory-mapped capability and does not include any
programming model registers.
The exact set of functions supported by the BME are detailed in the Functional
description.
The peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000
plus a 4 KB space based at 0x400F_F000 for GPIO accesses; the decorated address space
is mapped to the 448 MB region located at 0x4400_0000–0x5FFF_FFFF.
17.3 Functional description
Information found here details the specific functions supported by the BME.
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Functional description
Recall the combination of the basic load and store instructions of the Cortex-M
instruction set architecture (v6M, v7M) plus the concept of decorated storage provided by
the BME, the resulting implementation provides a robust and efficient read-modify-write
capability to this class of ultra low-end microcontrollers. The resulting architectural
capability defined by this core platform function is targeted at the manipulation of n-bit
fields in peripheral registers and is consistent with I/O hardware addressing in the
Embedded C standard. For most BME commands, a single core read or write bus cycle is
converted into an atomic read-modify-write, that is, an indivisible "read followed by a
write" bus sequence.
Consider decorated store operations first, then decorated loads.
17.3.1 BME decorated stores
The functions supported by the BME's decorated stores include three logical operators
(AND, OR, XOR) plus a bit field insert.
For all these operations, BME converts a single decorated AHB store transaction into a 2cycle atomic read-modify-write sequence, where the combined read-modify operation is
performed in the first AHB data phase, and then the write is performed in the second
AHB data phase.
A generic timing diagram of a decorated store showing a peripheral bit field insert
operation is shown as follows:
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CYCLE RULER
x
x+1
x+2
x+3
hclk
BME AHB Input Bus
mx_haddr
next
5..v_wxyz
mx_hattr
next
mx_hwrite
next
mx_hwdata
wdata
mx_hrdata
mx_hready
BME AHB Output Bus
sx_haddr
400v_wxyz
400v_wxyz
next
sx_hattr
next
sx_hwrite
next
sx_hwdata
wdata bfi rdata
sx_hrdata
rdata
sx_hready
BME States + Datapath
control_state_dp1
control_state_dp2
reg_addr_data_dp
5..v_wxyz
wdata bfi rdata
Figure 17-2. Decorated store: bit field insert timing diagram
All the decorated store operations follow the same execution template shown in Figure
17-2, a two-cycle read-modify-write operation:
1. Cycle x, 1st AHB address phase: Write from input bus is translated into a read
operation on the output bus using the actual memory address (with the decoration
removed) and then captured in a register.
2. Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual)
memory address is output
3. Cycle x+1, 1st AHB data phase: Memory read data is modified using the input bus
write data and the function defined by the decoration and captured in a data register;
the input bus cycle is stalled.
4. Cycle x+2, 2nd AHB data phase: Registered write data is sourced onto the output
write data bus.
NOTE
Any wait states inserted by the slave device are simply passed
through the BME back to the master input bus, stalling the
AHB transaction cycle for cycle.
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17.3.1.1 Decorated store logical AND (AND)
This command performs an atomic read-modify-write of the referenced memory location.
1. First, the location is read;
2. It is then modified by performing a logical AND operation using the write data
operand sourced for the system bus cycle
3. Finally, the result of the AND operation is written back into the referenced memory
location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit). The core performs the required write data lane replication on byte and
halfword transfers.
31 30 29 28 27 26 25 24 23 22
ioandb 0
*
ioandh 0
*
ioandw 0
*
21 20 19 18 17 16 15 14 13 12
11 10
9
*
0
0
1
-
-
-
-
-
-
mem_addr
*
0
0
1
-
-
-
-
-
-
*
0
0
1
-
-
-
-
-
-
mem_addr
mem_addr
8
7
6
5
4
3
2
0
1
0
0
0
Figure 17-3. Decorated store address: logical AND
See Figure 17-3 where addr[30:29] = 10 for peripheral, addr[28:26] = 001 specifies the
AND operation, and mem_addr[19:0] specifies the address offset into the space based at
0x4000_0000 for peripherals. The "-" indicates an address bit "don't care".
The decorated AND write operation is defined in the following pseudo-code as:
ioand(accessAddress, wdata)
tmp
= mem[accessAddress & 0xE00FFFFF, size]
tmp
= tmp & wdata
mem[accessAddress & 0xE00FFFFF, size] = tmp
//
//
//
//
decorated store AND
memory read
modify
memory write
where the operand size is defined as b(yte, 8-bit), h(alfword, 16-bit) and w(ord, 32bit). This notation is used throughout the document.
In the cycle definition tables, the notations AHB_ap and AHB_dp refer to the address and
data phases of the BME AHB transaction. The cycle-by-cycle BME operations are
detailed in the following table.
Table 17-1. Cycle definitions of decorated store: logical AND
Pipeline stage
Cycle
x
BME AHB_ap
Forward addr to memory;
Decode decoration; Convert
x+1
Recirculate captured addr +
attr to memory as slave_wt
x+2
Table continues on the next page...
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Chapter 17 Bit Manipulation Engine (BME)
Table 17-1. Cycle definitions of decorated store: logical AND (continued)
Pipeline stage
Cycle
x
x+1
x+2
master_wt to slave_rd;
Capture address, attributes
BME AHB_dp
Perform memory read; Form
(rdata & wdata) and capture
destination data in register
Perform write sending
registered data to memory
17.3.1.2 Decorated store logical OR (OR)
This command performs an atomic read-modify-write of the referenced memory location.
1. First, the location is read.
2. It is then modified by performing a logical OR operation using the write data operand
sourced for the system bus cycle.
3. Finally, the result of the OR operation is written back into the referenced memory
location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit). The core performs the required write data lane replication on byte and
halfword transfers.
31 30 29 28 27 26 25 24 23 22
21 20 19 18 17 16 15 14 13 12
ioorb
0
*
*
ioorh
0
*
ioorw
0
*
0
1
*
0
*
0
11 10
9
0
-
-
-
-
-
-
mem_addr
1
0
-
-
-
-
-
-
1
0
-
-
-
-
-
-
mem_addr
mem_addr
8
7
6
5
4
3
2
1
0
0
0
0
Figure 17-4. Decorated address store: logical OR
See Figure 17-4,where addr[30:29] =10 for peripheral, addr[28:26] = 010 specifies the
OR operation, and mem_addr[19:0] specifies the address offset into the space based at
0x4000_0000 for peripherals. The "-" indicates an address bit "don't care".
The decorated OR write operation is defined in the following pseudo-code as:
ioor(accessAddress, wdata)
// decorated store OR
tmp
= mem[accessAddress & 0xE00FFFFF, size]
tmp
= tmp | wdata
mem[accessAddress & 0xE00FFFFF, size] = tmp
// memory read
// modify
// memory write
The cycle-by-cycle BME operations are detailed in the following table.
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Table 17-2. Cycle definitions of decorated store: logical OR
Pipeline stage
Cycle
x
BME AHB_ap
x+1
Forward addr to memory;
Decode decoration; Convert
master_wt to slave_rd;
Capture address, attributes
BME AHB_dp
x+2
Recirculate captured addr +
attr to memory as slave_wt
Perform memory read; Form
(rdata | wdata) and capture
destination data in register
Perform write sending
registered data to memory
17.3.1.3 Decorated store logical XOR (XOR)
This command performs an atomic read-modify-write of the referenced memory location.
1. First, the location is read.
2. It is then modified by performing a logical XOR (exclusive-OR) operation using the
write data operand sourced for the system bus cycle.
3. Finally, the result of the XOR operation is written back into the referenced memory
location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit). The core performs the required write data lane replication on byte and
halfword transfers.
31 30 29 28 27 26 25 24 23 22
21 20 19 18 17 16 15 14 13 12
ioxorb
0
*
*
ioxorh
0
*
ioxorw
0
*
11 10
9
0
1
1
-
-
-
-
-
-
mem_addr
*
0
1
1
-
-
-
-
-
-
*
0
1
1
-
-
-
-
-
-
mem_addr
mem_addr
8
7
6
5
4
3
2
1
0
0
0
0
Figure 17-5. Decorated address store: logical XOR
See Figure 17-5, where addr[30:29] =10 for peripheral, addr[28:26] = 011 specifies the
XOR operation, and mem_addr[19:0] specifies the address offset into the peripheral
space based at 0x4000_0000 for peripherals. The "-" indicates an address bit "don't care".
The decorated XOR write operation is defined in the following pseudo-code as:
ioxor(accessAddress, wdata)
// decorated store XOR
tmp
= mem[accessAddress & 0xE00FFFFF, size]
tmp
= tmp ^ wdata
mem[accessAddress & 0xE00FFFFF, size] = tmp
// memory read
// modify
// memory write
The cycle-by-cycle BME operations are detailed in the following table.
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Chapter 17 Bit Manipulation Engine (BME)
Table 17-3. Cycle definitions of decorated store: logical XOR
Pipeline Stage
Cycle
x
BME AHB_ap
Forward addr to memory;
Decode decoration; Convert
master_wt to slave_rd;
Capture address, attributes
BME AHB_dp
x+1
x+2
Recirculate captured addr +
attr to memory as slave_wt
Perform memory read; Form
(rdata ^ wdata) and capture
destination data in register
Perform write sending
registered data to memory
17.3.1.4 Decorated store bit field insert (BFI)
This command inserts a bit field contained in the write data operand, defined by LSB
position (b) and the bit field width (w+1), into the memory "container" defined by the
access size associated with the store instruction using an atomic read-modify-write
sequence.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit).
NOTE
For the word sized operation, the maximum bit field width is 16
bits. The core performs the required write data lane replication
on byte and halfword transfers.
The BFI operation can be used to insert a single bit into a peripheral. For this case, the w
field is simply set to 0, indicating a bit field width of 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
iobfib
0
iobfih
0
iobfiw
0
9
*
1
-
-
b
b b
-
w w w
mem_addr
*
*
1
-
b
b
b b
w w w w
mem_addr
*
*
1
b b
w w w w
mem_addr
*
b
b
b
8
7
6
5
4
3
2
1
0
0
0
0
Figure 17-6. Decorated address store: bit field insert
where addr[30:29] =10 for peripheral,addr[28] = 1 signals a BFI operation, addr[27:23] is
"b", the LSB identifier, addr[22:19] is "w", the bit field width minus 1 identifier, and
addr[18:0] specifies the address offset into the peripheral space based at 0x4000_0000 for
peripherals. The "-" indicates an address bit "don't care". Note, unlike the other decorated
store operations, BFI uses addr[19] as the least significant bit in the "w" specifier and not
as an address bit.
KE02 Sub-Family Reference Manual, Rev. 3, Nov. 2014
Freescale Semiconductor, Inc.
211
Functional description
The decorated BFI write operation is defined in the following pseudo-code as:
iobfi(accessAddress, wdata)
// decorated bit field insert
tmp
mask
tmp
// memory read
// generate bit mask
// modify
= mem[accessAddress & 0xE007FFFF, size]
= ((1
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