MKE14Z256VLL7

NXP Semiconductors Data Sheet: Technical Data KE1xZP100M72SF0 Rev. 4.2, 03/2021 Kinetis KE1xZ with up to 256 KB Flash Up to 72 MHz ARM® Cortex®-M0+ Based Microcontroller MKE1xZ256VLL7 MKE1xZ256VLH7 MKE1xZ128VLL7 MKE1xZ128VLH7 Kinetis KE1xZ256 MCUs are the leading parts for the KE1xZ familiy based on ARM® Cortex®-M0+ core. Providing up to 256 KB flash, up to 32 KB RAM, and the complete set of analog/ digital features, KE1xZ extends Kinetis E family to higher performance and broader scalability. Robust TSI provides highlevel stability and accuracy to customer's HMI system. 1 Msps ADC and FlexTimer help build a perfect solution for BLDC motor control systems. 100 LQFP (LL) 14x14x1.4 mm P 0.5 Core Processor and System • ARM® Cortex®-M0+ core, supports up to 72 MHz frequency • ARM Core based on the ARMv6 Architecture and Thumb®-2 ISA • Configurable Nested Vectored Interrupt Controller (NVIC) • Memory-Mapped Divide and Square Root module (MMDVSQ) • 8-channel DMA controller extended up to 63 channels with DMAMUX Reliability, safety and security • Flash Access Control (FAC) • Cyclic Redundancy Check (CRC) generator module • 128-bit unique identification (ID) number • Internal watchdog (WDOG) with independent clock source • External watchdog monitor (EWM) module • ADC self calibration feature • On-chip clock loss monitoring Human-machine interface (HMI) • Supports up to 32 interrupt request (IRQ) sources • Up to 89 GPIO pins with interrupt functionality • Touch sensing input (TSI) module 64 LQFP (LH) 10x10x1.4 mm P 0.5 Memory and memory interfaces • Up to 256 KB program flash • Up to 32 KB SRAM • 32 KB FlexNVM for data flash and with EEPROM emulation • 2 KB FlexRAM for EEPROM emulation • 128 Bytes flash cache • Boot ROM with built in bootloader Mixed-signal analog • 2× 12-bit analog-to-digital converter (ADC) with up to 16 channel analog inputs per module, up to 1 Msps • 2× high-speed analog comparators (CMP) with internal 8-bit digital to analog converter (DAC); the 8-bit DAC of CMP0 supports an output option to pad with a buffer Timing and control • 3× Flex Timers (FTM) for PWM generation, offering up to 8 standard channels • 1× 16-bit Low-Power Timer (LPTMR) with flexible wake up control • 1× Programmable Delay Block (PDB) with flexible trigger system • 1× 32-bit Low-power Periodic Interrupt Timer (LPIT) with 4 channels • Real timer clock (RTC) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Clock interfaces Connectivity and communications interfaces • 4 - 40 MHz fast external oscillator (OSC) • 3× low-power universal asynchronous receiver/ • 32 kHz slow external oscillator (OSC32) transmitter (LPUART) modules with DMA support • 48 - 60 MHz high-accuracy (up to ±1%) fast internal and low power availability reference clock (FIRC) for normal Run • 2× low-power serial peripheral interface (LPSPI) • 8 MHz / 2 MHz high-accuracy (up to ±3%) slow internal modules with DMA support and low power reference clock (SIRC) for low-speed Run availability • 128 kHz low power oscillator (LPO) • 2× low-power inter-integrated circuit (LPI2C) • Low-power FLL (LPFLL) modules with DMA support and low power • Up to 60 MHz DC external square wave input clock availability • System clock generator (SCG) • FlexIO module for flexible and high performance • Real time counter (RTC) serial interfaces Power management Debug functionality • Low-power ARM Cortex-M0+ core with excellent • Serial Wire Debug (SWD) debug interface energy efficiency • Debug Watchpoint and Trace (DWT) • Power management controller (PMC) with multiple • Micro Trace Buffer (MTB) power modes: Run, Wait, Stop, VLPR, VLPW and Operating Characteristics VLPS • Voltage range: 2.7 to 5.5 V • Supports clock gating for unused modules, and specific • Ambient temperature range: –40 to 105 °C peripherals remain working in low power modes • POR, LVD/LVR Related Resources Type Description Resource Selector Guide The Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. KE1xZ256PB 1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KE1xZP100M72SF0RM 1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document: KE1xZP100M72SF0 Chip Errata The chip mask set Errata provides additional or corrective information for Kinetis_E_1N36S 1 a particular device mask set. Kinetis_E_2N36S 1 Package drawing Package dimensions are provided in package drawings. 100-LQFP: 98ASS23308W 64-LQFP: 98ASS23234W 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Kinetis KE1xZ Sub-Family ARM ® Cortex ® -M0+ Core System eDMA Debug interfaces MMDVSQ DMAMUX Memories and Memory Interfaces Program flash RAM Clocks OSC FIRC FlexMemory Boot ROM SIRC TRGMUX Interrupt controller LPFLL WDOG OSC32 EWM LPO Human-Machine Interface (HMI) Security Analog Timers Communication Interfaces CRC 12-bit ADC x2 FlexTimer 8ch x1 4ch x2 LPI C x2 GPIO upto 89 FAC CMP x2 PDB x1 LPUART x3 High drive I/O (8 pins) (within CMP0, output capable) LPIT, 4ch LPSPI x2 Digital filters (port E) PMC LPTMR FlexIO TSI, 25ch (optional) and Integrity 8-bit DAC x1 2 SRTC PWT Figure 1. Functional block diagram Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 3 NXP Semiconductors Table of Contents 1 Ordering information............................................................... 5 2 Overview................................................................................. 5 2.1 System features...............................................................6 2.1.1 ARM Cortex-M0+ core...................................... 6 2.1.2 NVIC..................................................................7 2.1.3 AWIC.................................................................7 2.1.4 Memory............................................................. 8 2.1.5 Reset and boot..................................................8 2.1.6 Clock options.....................................................10 2.1.7 Security............................................................. 11 2.1.8 Power management.......................................... 12 2.1.9 Debug controller................................................13 2.2 Peripheral features.......................................................... 13 2.2.1 eDMA and DMAMUX........................................ 13 2.2.2 FTM...................................................................14 2.2.3 ADC...................................................................14 2.2.4 CMP.................................................................. 15 2.2.5 RTC...................................................................16 2.2.6 LPIT...................................................................16 2.2.7 PDB...................................................................17 2.2.8 LPTMR.............................................................. 17 2.2.9 CRC.................................................................. 17 2.2.10 LPUART............................................................ 18 2.2.11 LPSPI................................................................ 18 2.2.12 LPI2C................................................................ 19 2.2.13 FlexIO................................................................20 2.2.14 Port control and GPIO.......................................20 3 Memory map........................................................................... 22 4 Pinouts.................................................................................... 24 4.1 KE1xZ Signal Multiplexing and Pin Assignments............ 24 4.2 Port control and interrupt summary................................. 27 4.3 Module Signal Description Tables................................... 28 4.4 Pinout diagram................................................................ 33 4.5 Package dimensions....................................................... 35 5 Electrical characteristics..........................................................40 5.1 Terminology and guidelines.............................................40 5.1.1 Definitions......................................................... 40 5.1.2 Examples.......................................................... 40 4 NXP Semiconductors 5.1.3 5.1.4 Typical-value conditions....................................41 Relationship between ratings and operating requirements..................................................... 41 5.1.5 Guidelines for ratings and operating requirements..................................................... 42 5.2 Ratings............................................................................ 42 5.2.1 Thermal handling ratings...................................42 5.2.2 Moisture handling ratings.................................. 43 5.2.3 ESD handling ratings........................................ 43 5.2.4 Voltage and current operating ratings............... 43 5.3 General............................................................................ 44 5.3.1 Nonswitching electrical specifications............... 44 5.3.2 Switching specifications.................................... 54 5.3.3 Thermal specifications...................................... 57 5.4 Peripheral operating requirements and behaviors...........60 5.4.1 System modules................................................60 5.4.2 Clock interface modules....................................60 5.4.3 Memories and memory interfaces.....................67 5.4.4 Security and integrity modules.......................... 69 5.4.5 Analog............................................................... 70 5.4.6 Communication interfaces.................................76 5.4.7 Human-machine interfaces (HMI)..................... 80 5.4.8 Debug modules................................................. 80 6 Design considerations.............................................................81 6.1 Hardware design considerations..................................... 82 6.1.1 Printed circuit board recommendations.............82 6.1.2 Power delivery system...................................... 82 6.1.3 Analog design................................................... 82 6.1.4 Digital design.....................................................83 6.1.5 Crystal oscillator................................................86 6.2 Software considerations.................................................. 87 7 Part identification.....................................................................88 7.1 Description.......................................................................88 7.2 Format............................................................................. 88 7.3 Fields............................................................................... 88 7.4 Example...........................................................................89 8 Revision history.......................................................................89 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Ordering information 1 Ordering information The following chips are available for ordering. Table 1. Ordering information Product Memory Package IO and ADC channel GPIOs ADC (INT/HD channel )1 s HMI Part number Flash (KB) SRAM (KB) FlexNVM/ FlexRAM (KB) Pin count Packag e GPIOs TSI MKE15Z256VLL7 256 32 32/2 100 LQFP 89 89/8 16+12 Yes MKE15Z256VLH7 256 32 32/2 64 LQFP 58 58/8 16+11 Yes MKE15Z128VLL7 128 16 32/2 100 LQFP 89 89/8 16+12 Yes MKE15Z128VLH7 128 16 32/2 64 LQFP 58 58/8 16+11 Yes MKE14Z256VLL7 256 32 32/2 100 LQFP 89 89/8 16+12 No MKE14Z256VLH7 256 32 32/2 64 LQFP 58 58/8 16+11 No MKE14Z128VLL7 128 16 32/2 100 LQFP 89 89/8 16+12 No MKE14Z128VLH7 128 16 32/2 64 LQFP 58 58/8 16+11 No 1. INT: interrupt pin numbers; HD: high drive pin numbers 2 Overview The following figure shows the system diagram of this device. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 5 NXP Semiconductors Overview M0 unified bus for core NVIC eDMA M2 DMA MUX FMC Flash upto 256 KB S0 8 KB ROM S1 SRAM upto 32 KB S2 MUX Peripheral Bridge 0 (Bus Clock - Max 24 MHz) CM0+ core Crossabar Switch (Platform Clock - Max 72 MHz) IOPORT Debug (SWD) Slave Master Cortex M0+ various peripheral blocks System Clock Generator (SCG) Clock Source Fast IRC SOSC Slow IRC LPFLL OSC32 LPO Figure 2. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. 2.1 System features The following sections describe the high-level system features. 6 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Overview 2.1.1 ARM Cortex-M0+ core The enhanced ARM Cortex M0+ is the member of the Cortex-M Series of processors targeting microcontroller cores focused on very cost sensitive, low power applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality including support for simple program trace capability. The processor supports the ARMv6-M instruction set (Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It is upward compatible with other Cortex-M profile processors. 2.1.2 NVIC The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority levels for interrupts. In the NVIC, each source in the IPR registers contains 2 bits. It also differs in number of interrupt sources and supports 32 interrupt vectors. The Cortex-M family uses a number of methods to improve interrupt latency to up to 15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and VLPW modes. 2.1.3 AWIC The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous wake-up events in Stop mode and signal to clock control logic to resume system clocking. After clock restarts, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. The AWIC can be used to wake MCU core from Partial Stop, Stop and VLPS modes. Wake-up sources for this SoC are listed as below: Table 2. AWIC Stop and VLPS Wake-up Sources Wake-up source Description Available system resets RESET pin, WDOG , loss of clock(LOC) reset and loss of lock (LOL) reset Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx ADCx is optional functional with clock source from SIRC or OSC CMPx Functional in Stop/VLPS modes with clock source from SIRC or OSC LPI2C Functional in Stop/VLPS modes with clock source from SIRC or OSC LPUART Functional in Stop/VLPS modes with clock source from SIRC or OSC Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 7 NXP Semiconductors Overview Table 2. AWIC Stop and VLPS Wake-up Sources (continued) Wake-up source Description LPSPI Functional in Stop/VLPS modes with clock source from SIRC or OSC LPIT Functional in Stop/VLPS modes with clock source from SIRC or OSC FlexIO Functional in Stop/VLPS modes with clock source from SIRC or OSC LPTMR Functional in Stop/VLPS modes RTC Functional in Stop/VLPS modes SCG Functional in Stop mode (Only SIRC) TSI Touch sense wakeup NMI Non-maskable interrupt 2.1.4 Memory This device has the following features: • Upto 256 KB of embedded program flash memory. • Upto 32 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states. • The non-volatile memory is divided into several arrays: • 32 KB of embedded data flash memory • 2 KB of Emulated EEPROM • 8 KB ROM (built-in bootloader to support UART, I2C, and SPI interfaces) The program flash memory contains a 16-byte flash configuration field that stores default protection settings and security information. The page size of program flash is 1 KB. The protection setting can protect 32 regions of the program flash memory from unintended erase or program operations. The security circuitry prevents unauthorized access to RAM or flash contents from debug port. 2.1.5 Reset and boot The following table lists all the reset sources supported by this device. NOTE In the following table, Y means the specific module, except for the registers, bits or conditions mentioned in the footnote, 8 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Overview is reset by the corresponding Reset source. N means the specific module is not reset by the corresponding Reset source. Table 3. Reset source Reset sources Descriptions Modules PMC SIM SMC RCM Reset WDO SCG pin is G negated RTC LPTM R Other s POR reset Power-on reset (POR) Y Y Y Y Y Y Y Y Y Y System resets Low-voltage detect (LVD) Y1 Y Y Y Y Y Y N Y Y External pin reset (RESET) Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y Watchdog (WDOG) reset Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y Multipurpose clock generator loss of clock (LOC) reset Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y Multipurpose clock generator loss of lock (LOL) reset Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y Stop mode acknowledge error (SACKERR) Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y Software reset (SW) Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y Lockup reset (LOCKUP) Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y MDM DAP system reset Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y Debug reset Y1 Y2 Y3 Y4 Y Y5 Y6 N N Y Debug reset 1. 2. 3. 4. 5. 6. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV] Except SIM_SOPT1 Except SMC_PMPROT, SMC_PMCTRL_RUM, SMC_PMCTRL_STOPM, SMC_STOPCTRL, SMC_PMSTAT Except RCM_RPC, RCM_MR, RCM_FM, RCM_SRIE, RCM_SRS, RCM_SSRS Except WDOG_CS[TST] Except SCG_CSR and SCG_FIRCSTAT This device supports booting from: • internal flash • boot ROM Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 9 NXP Semiconductors Overview POR or Reset N RCM[FORCEROM] =00 Y FOPT[BOOTPIN_OPT]=0 N Y BOOTCFG0 pin=0 Y N N FOPT[BOOTSRC _SEL]=10/11 Y Boot from ROM Boot from Flash Figure 3. Boot flow chart The blank chip is default to boot from ROM and remaps the vector table to ROM base address, otherwise, it remaps to flash address. 2.1.6 Clock options The SCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory . The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The following figure is a high level block diagram of the clock generation. For more details on the clock operation and configuration, see the Clocking chapter in the Reference Manual. 10 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Overview 00 01 PWT 10 11 TCLK0 TCLK1 TCLK2 00 SIM_CHIPCTL[PWTCLKSEL] 01 10 11 FTMx SIM_FTMOPT0[FTMxCLKSEL] Fast IRC Slow IRC SCG_LPFLLTCFG[TRIMSRC] 48 MHz 01 00 10 11 SCG TRIMDIV Core LPFLL GPIOC DMAMUX eDMA PDB 0011 default start up 8MHz/2MHz RAM 0101 (SCG_LFLLTCFG) DIVCORE CORE_CLK/SYS_CLK 0010 PCC 0001 Other CRC 8-bit DAC ACMPx TSI SYS_CLK SCG_xCCR[SCS] (x=R, V, H) FLL_CLK FLLDIV2 SIRC_CLK SIRCDIV2 PCC_xxx[CGC] DIVSLOW FLLDIV2_CLK BUS_CLK/FLASH_CLK BUSOUT Flash SIRCDIV2_CLK Async clock FIRC_CLK SCG_SOSCCFG[EREFS] FIRCDIV2 FIRCDIV2_CLK 0 SOSC_CLK EXTAL XTAL High Range OSC 1 OSC SCG_CLKOUTCNFG [CLKOUTSEL] OSC32_CR[ROSCEREFS] Low Range OSC XTAL32 PCC_xxx[PCS] SCG_SOSCCSR [SOSCERCLKEN] 00 01 10 WDOG CLKOUT CLKOUTDIV 11 SIM_CHIPCTL[CLKOUTSEL] OSC32 ÷128 1kHz 1 LPO_CLK LPTMR OSC32_CLK RTC EWM RTC_CLKOUT PMC 00 01 10 11 RTC_CLKIN ADCx FlexIO LPIT LPI2Cx LPUARTx LPSPIx SCG CLKOUT 1 LPO128K SOSCDIV2_CLK Other 0000 0001 0011 0010 0101 0 EXTAL32 SOSCDIV2 Peripheral Registers 32kHz 0 PORT Control RTC_CR[LPOS] SIM_CHIPCTL[RTC32KCLKSEL] Figure 4. Clocking block diagram 2.1.7 Security Security state can be enabled via programming flash configure field (0x40e). After enabling device security, the SWD port cannot access the memory resources of the MCU. External interface SWD port 2.1.7.1 Security Can't access memory source by SWD interface Unsecure the debugger can write to the Flash Mass Erase in Progress field of the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command Flash Access Control (FAC) The FAC is a native or third-party configurable memory protection scheme optimized to allow end users to utilize software libraries while offering programmable restrictions to these libraries. The flash memory is divided into equal size segments that provide protection to proprietary software libraries. The protection of these segments is controlled as the FAC provides a cycle-by-cycle evaluation of the access Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 11 NXP Semiconductors Overview rights for each transaction routed to the on-chip flash memory. Configurability allows an increasing number of protected segments while supporting two levels of vendors adding their proprietary software to a device. 2.1.8 Power management The Power Management Controller (PMC) expands upon ARM’s operational modes of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can be used to optimize current consumption for a wide range of applications. The WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current configuration. For more information on ARM’s operational modes, See the ARM® Cortex® User Guide. The PMC provides Normal Run (RUN), and Very Low Power Run (VLPR) configurations in ARM’s Run operation mode. In these modes, the MCU core is active and can access all peripherals. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The configuration that matches the power versus performance requirements of the application can be selected. The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive, all of the peripherals can be enabled and operate as programmed. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The PMC provides Stop (Stop), Very Low Power Stop (VLPS) configurations in ARM’s Deep Sleep operational mode. In these modes, the MCU core and most of the peripherals are disabled. Depending on the requirements of the application, different portions of the analog, logic, and memory can be retained or disabled to conserve power. The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up Interrupt Controller (AWIC) are used to wake up the MCU from low power states. The NVIC is used to wake up the MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU core from STOP and VLPS modes. For additional information regarding operational modes, power management, the NVIC, AWIC, please refer to the Reference Manual. The following table provides information about the state of the peripherals in the various operational modes and the modules that can wake MCU from low power modes. 12 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Overview Table 5. Peripherals states in different operational modes Core mode Run mode Sleep mode Deep sleep Device mode Descriptions Run In Run mode, all device modules are operational. Very Low Power Run In VLPR mode, all device modules are operational at a reduced frequency except the Low Voltage Detect (LVD) monitor, which is disabled. Wait In Wait mode, all peripheral modules are operational. The MCU core is placed into Sleep mode. Very Low Power Wait In VLPW mode, all peripheral modules are operational at a reduced frequency except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU core is placed into Sleep mode. Stop In Stop mode, most peripheral clocks are disabled and placed in a static state. Stop mode retains all registers and SRAMs while maintaining Low Voltage Detection protection. In Stop mode, the ADC, CMP, LPTMR, RTC, and pin interrupts are operational. The NVIC is disabled, but the AWIC can be used to wake up from an interrupt. Very Low Power Stop In VLPS mode, the contents of the SRAM are retained. The CMP (low speed), ADC, OSC, RTC, LPTMR, LPIT, FlexIO, LPUART, LPI2C,LPSPI, and DMA are operational, LVD and NVIC are disabled, AWIC is used to wake up from interrupt. NOTE When the MCU is in HSRUN or VLP mode, user cannot write FlexRAM (EEPROM), and cannot launch an FTFE command including flash programming/erasing. 2.1.9 Debug controller This device has extensive debug capabilities including run control and tracing capabilities. The standard ARM debug port supports SWD interface. 2.2 Peripheral features The following sections describe the features of each peripherals of the chip. 2.2.1 eDMA and DMAMUX The eDMA is a highly programmable data-transfer engine optimized to minimize any required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 13 NXP Semiconductors Overview transferred data itself. The DMA controller in this device implements 8 channels which can be routed from up to 63 DMA request sources through DMA MUX module. Main features of eDMA are listed below: • All data movement via dual-address transfers: read from source, write to destination • 8-channel implementation that performs complex data transfers with minimal intervention from a host processor • Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations • Channel activation via one of three methods • Fixed-priority and round-robin channel arbitration • Channel completion reported via programmable interrupt requests • Programmable support for scatter/gather DMA processing • Support for complex data structures 2.2.2 FTM This device contains three FlexTimer modules. The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. Several key enhancements of this module are made: • Signed up counter • Deadtime insertion hardware • Fault control inputs • Enhanced triggering functionality • Initialization and polarity control 2.2.3 ADC This device contains two 12-bit SAR ADC modules. The ADC module supports hardware triggers from FTM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features: 14 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Overview • • • • • • • • • • • • • Linear successive approximation algorithm with up to 12-bit resolution Up to 16 single-ended external analog inputs Support 12-bit, 10-bit, and 8-bit single-ended output modes Single or continuous conversion Configurable sample time and conversion speed/power Input clock selectable from up to four sources Operation in low-power modes for lower noise Selectable hardware conversion trigger Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value Temperature sensor Hardware average function Selectable Voltage reference: from external or alternate Self-Calibration mode 2.2.3.1 Temperature sensor This device contains one temperature sensor internally connected to the input channel of AD26, see ADC electrical characteristics for details of the linearity factor. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed application information of the temperature sensor. 2.2.4 CMP There aretwo analog comparators on this device. • Each CMP has its own independent 8-bit DAC. • Each CMP supports up to 6 analog inputs from external pins. • Each CMP is able to convert an internal reference from the bandgap. • Each CMP supports the round-robin sampling scheme. In summary, this allow the CMP to operate independently in VLPS and Stop modes, whilst being triggered periodically to sample up to 8 inputs. Only if an input changes state is a full wakeup generated. The CMP has the following features: • Inputs may range from rail to rail • Programmable hysteresis control • Selectable interrupt on rising-edge, falling-edge, or both rising and falling edges of the comparator output • Selectable inversion on comparator output Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 15 NXP Semiconductors Overview • Capability to produce a wide range of outputs such as sampled, windowed, or digitally filtered • External hysteresis can be used at the same time that the output filter is used for internal functions • Two software selectable performance levels: Shorter propagation delay at the expense of higher power, and Low power with longer propagation delay • DMA transfer support • Functional in all power modes available on this MCU • The window and filter functions are not available in STOP mode • Integrated 8-bit DAC with selectable supply reference source and can be power down to conserve power 2.2.5 RTC The RTC is an always powered-on block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator, or clock directly from RTC_CLKIN pin. RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers. The RTC module has the following features • 32-bit seconds counter with roll-over protection and 32-bit alarm • 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm • Register write protection with register lock mechanism • 1 Hz square wave or second pulse output with optional interrupt 2.2.6 LPIT The Low Power Periodic Interrupt Timer (LPIT) is a multi-channel timer module generating independent pre-trigger and trigger outputs. These timer channels can operate individually or can be chained together. The LPIT can operate in low power modes if configured to do so. The pre-trigger and trigger outputs can be used to trigger other modules on the device. This device contains one LPIT module with four channels. The LPIT generates periodic trigger events to the DMAMUX. 16 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Overview 2.2.7 PDB The Programmable Delay Block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved. The PDB can optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in the CMP block. The PDB module has the following capabilities: • trigger input sources and one software trigger source • 1 DAC refresh trigger output, for this device • configurable PDB channels for ADC hardware trigger • 1 pulse output, for this device 2.2.8 LPTMR The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features: • 16-bit time counter or pulse counter with compare • Optional interrupt can generate asynchronous wakeup from any low-power mode • Hardware trigger output • Counter supports free-running mode or reset on compare • Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter 2.2.9 CRC This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 17 NXP Semiconductors Overview The CRC module has the following features: • Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register • Programmable initial seed value and polynomial • Option to transpose input data or output data (the CRC result) bitwise or bytewise. • Option for inversion of final CRC result • 32-bit CPU register programming interface 2.2.10 LPUART This product contains three Low-Power UART modules, and can work in Stop and VLPS modes. The module also supports 4× to 32× data oversampling rate to meet different applications. The LPUART module has the following features: • Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4× to 32× • Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode • Interrupt, DMA or polled operation • Hardware parity generation and checking • Programmable 8-bit, 9-bit or 10-bit character length • Programmable 1-bit or 2-bit stop bits • Three receiver wakeup methods • Idle line wakeup • Address mark wakeup • Receive data match • Automatic address matching to reduce ISR overhead: • Address mark matching • Idle line address matching • Address match start, address match end • Optional 13-bit break character generation / 11-bit break character detection • Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters • Selectable transmitter output and receiver input polarity 18 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Overview 2.2.11 LPSPI This device contains two LPSPI modules. The LPSPI is a low power Serial Peripheral Interface (SPI) module that supports an efficient interface to an SPI bus as a master and/or a slave. The LPSPI can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPSPI module has the following features: • Command/transmit FIFO of 4 words • Receive FIFO of 4 words • Host request input can be used to control the start time of an SPI bus transfer 2.2.12 LPI2C This device contains two LPI2C modules. The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master and/or a slave. The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPI2C implements logic support for standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The LPI2C module also complies with the System Management Bus (SMBus) Specification, version 2. The LPI2C modules have the following features: • Standard, Fast, Fast+ and Ultra Fast modes are supported • HS-mode supported in slave mode • Multi-master support including synchronization and arbitration • Clock stretching • General call, 7-bit and 10-bit addressing • Software reset, START byte and Device ID require software support • For master mode: • command/transmit FIFO of 4 words • receive FIFO of 4 words • For slave mode: • separate I2C slave registers to minimize software overhead due to master/ slave switching • support for 7-bit or 10-bit addressing, address range, SMBus alert and general call address • transmit/receive data register supporting interrupt or DMA requests Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 19 NXP Semiconductors Overview 2.2.13 FlexIO The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. The FlexIO module has the following features: • Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using remains enabled • Four 32-bit double buffered shift registers with transmit, receive, and data match modes, and continuous data transfer • The timing of the shifter's shift, load and store events are controlled by the highly flexible 16-bit timer assigned to the shifter • Two or more shifters can be concatenated to support large data transfer sizes • Each 16-bit timers operates independently, supports for reset, enable and disable on a variety of internal or external trigger conditions with programmable trigger polarity • Flexible pin configuration supporting output disabled, open drain, bidirectional output data and output mode • Supports interrupt, DMA or polled transmit/receive operation 2.2.14 Port control and GPIO The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. The following figure shows the basic I/O pad structure. Pseudo open-drain pins have the p-channel output driver disabled when configured for open-drain operation. None of the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above VDD. NOTE The RESET_b pin is also a normal I/O pad with pseudo opendrain. 20 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Overview IBE=1 whenever MUX≠000 IFE IBE LPF MUX Digital input ESD Bus VDD RPULL PE PS Analog input Digital output DSE Figure 5. I/O simplified block diagram The PORT module has the following features: • all PIN support interrupt enable • Configurable edge (rising, falling, or both) or level sensitive interrupt type • Support DMA request • Asynchronous wake-up in low-power modes • Configurable pullup, pulldown, and pull-disable on select pins • Configurable high and low drive strength on selected pins • Configurable passive filter on selected pins • Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions • Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features: • Port Data Input register visible in all digital pin-multiplexing modes • Port Data Output register with corresponding set/clear/toggle registers • Port Data Direction register • GPIO support single-cycle access via fast GPIO. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 21 NXP Semiconductors Memory map 3 Memory map This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. For more details of the system memory and peripheral locations, see the Memory Map chapter in the Reference Manual. 22 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Memory map 0x4000_0000 Note: The size of Flash and SRAM varies for devices with different part numbers. See "Ordering information" in DataSheet for details. 0x0000_0000 Flash * 0x0003_FFFF 0x0000_0000 Code space 0x0800_0000 0x1000_0000 0x1000_8000 0x1400_0000 0x1400_0800 0x1800_0000 0x1C00_0000 Reserved Reserved FlexRAM Reserved Reserved Data Space 0x2400_0000 0x1C00_0000 0x1C00_0000 ROM 0x1C00_3FFF 0x1C00_3FFF Reserved 0x1FF0_0000 0x2010_0000 0x2200_0000 Reserved FlexNVM Boot ROM 0x1C00_4000 0x07FF_FFFF Reserved Aliased to SRAM_U bit-band region 0x1FF0_0000 SRAM_L 0x2000_0000 0x200F_FFFF SRAM_U Reserved 0x4000_0000 Public peripheral 0x4010_0000 0x4400_0000 0x4000_0000 AIPS peripherals Reserved BME 0x6000_0000 Reserved 0x4008_0000 0x400F_F000 0x400F_FFFF 0xE000_0000 0xE000_E000 0xE000_0000 Private peripheral Reserved GPIO Reserved System control space 0xE000_F000 Reserved 0xE00F_F000 0xE010_0000 Reserved 0xE00F_FFFF 0xF000_0000 0xF000_1000 0xF000_0000 0xF000_2000 Private peripheral bus 0xFFFF_FFFF 0xF000_3000 0xF000_4000 Core ROM table MTB MTBDWT ROM Table Reserved Reserved eDMA DMA TCD Reserved GPIO controller(aliased to 400F_F000) Reserved Flash memory unit DMAMUX0 Reserved 0x4002_7000 0x4002_8000 0x4002_C000 0x4002_D000 0x4002_E000 0x4003_2000 LPSPI0 0x4003_3000 0x4003_6000 Reserved 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_D000 0x4003_E000 0x4004_0000 0x4004_1000 0x4004_5000 0x4004_6000 0x4004_8000 0x4004_9000 0x4004_A000 0x4004_B000 0x4004_C000 0x4004_D000 0x4004_E000 0x4005_2000 0x4005_3000 0x4005_6000 0x4005_7000 0x4005_A000 0x4005_B000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_3000 0x4006_4000 0x4006_5000 0x4006_6000 0x4006_7000 0x4006_8000 0x4006_A000 ADC1 Reserved LPSPI1 Reserved CRC PDB0 LPIT0 FTM0 FTM1 FTM2 ADC0 Reserved RTC Reserved LPTMR0 Reserved TSI0 Reserved SIM PORT A PORT B PORT C PORT D PORT E Reserved WDOG Reserved PWT Reserved FlexIO0 Reserved OSC32 EWM TRGMUX0 TRGMUX1 SCG PCC LPI2C0 LPI2C1 Reserved 0x4006_B000 MCM 0x4006_C000 0x4006_D000 LPUART2 MMDVSQ 0x4007_3000 CMP0 Reserved 0xFFFF_FFFF 0x4000_F000 0x4001_0000 0x4002_0000 0x4002_1000 0x4002_2000 AIPS-Lite LPUART0 LPUART1 0xF000_5000 0xF800_0000 0x4000_1000 0x4000_2000 0x4000_8000 0x4000_9000 0x4000_A000 IOPORT 0x4007_4000 0x4007_5000 0x4007_D000 0x4007_E000 0x4007_F000 Reserved CMP1 Reserved PMC SMC RCM 0x4007_FFFF Figure 6. Memory map Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 23 NXP Semiconductors Pinouts 4 Pinouts 4.1 KE1xZ Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE On this device, there are several special ADC channels which support hardware interleave between multiple ADCs. Taking ADC0_SE4 and ADC1_SE14 channels as an example, these two channels can work independently, but they can also be hardware interleaved. In the hardware interleaved mode, a signal on the pin PTB0 can be sampled by both ADC0 and ADC1. The interleaved mode is enabled by SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits. For more information, see "ADC Hardware Interleaved Channels" in the ADC chapter of Reference Manual. 100 64 LQFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 10 VREFL/ VSS VREFL/ VSS 1 — PTE16 DISABLED PTE16 FXIO_D3 TRGMUX_ OUT7 2 — PTE15 DISABLED PTE15 FXIO_D2 TRGMUX_ OUT6 3 1 PTD1 TSI0_CH5 TSI0_CH5 PTD1 FTM0_CH3 LPSPI1_SIN FTM2_CH1 FXIO_D1 TRGMUX_ OUT2 4 2 PTD0 TSI0_CH4 TSI0_CH4 PTD0 FTM0_CH2 LPSPI1_SCK FTM2_CH0 FXIO_D0 TRGMUX_ OUT1 5 3 PTE11 TSI0_CH3 TSI0_CH3 PTE11 PWT_IN1 LPTMR0_ ALT1 FXIO_D5 TRGMUX_ OUT5 6 4 PTE10 TSI0_CH2 TSI0_CH2 PTE10 CLKOUT FXIO_D4 TRGMUX_ OUT4 7 — PTE13 DISABLED 8 5 PTE5 TSI0_CH0 TSI0_CH0 PTE5 TCLK2 FTM2_QD_ PHA FTM2_CH3 FXIO_D7 EWM_IN 9 6 PTE4 TSI0_CH1 TSI0_CH1 PTE4 BUSOUT FTM2_QD_ PHB FTM2_CH2 FXIO_D6 EWM_OUT_b 24 NXP Semiconductors VREFL/ VSS PTE13 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Pinouts 100 64 LQFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 10 7 VDD VDD VDD 11 8 VDDA VDDA VDDA 12 9 VREFH VREFH VREFH 13 — VREFL VREFL VREFL 14 — VSS VSS VSS 15 11 PTB7 EXTAL EXTAL PTB7 LPI2C0_SCL 16 12 PTB6 XTAL XTAL PTB6 LPI2C0_SDA 17 — PTE14 DISABLED PTE14 FTM0_FLT1 18 13 PTE3 TSI0_CH24 PTE3 FTM0_FLT0 LPUART2_ RTS 19 — PTE12 DISABLED PTE12 FTM0_FLT3 LPUART2_TX 20 — PTD17 DISABLED PTD17 FTM0_FLT2 LPUART2_RX 21 14 PTD16 DISABLED PTD16 FTM0_CH1 22 15 PTD15 DISABLED PTD15 FTM0_CH0 23 16 PTE9 DAC0_OUT PTE9 FTM0_CH7 24 — PTD14 DISABLED PTD14 CLKOUT 25 — PTD13 DISABLED PTD13 RTC_CLKOUT 26 17 PTE8 ACMP0_IN3/ TSI0_CH11 ACMP0_IN3/ TSI0_CH11 PTE8 FTM0_CH6 27 18 PTB5 TSI0_CH9 TSI0_CH9 PTB5 FTM0_CH5 LPSPI0_PCS1 TRGMUX_IN0 ACMP1_OUT 28 19 PTB4 ACMP1_IN2/ TSI0_CH8 ACMP1_IN2/ TSI0_CH8 PTB4 FTM0_CH4 LPSPI0_SOUT TRGMUX_IN1 29 20 PTC3 ADC0_SE11/ ACMP0_IN4/ EXTAL32 ADC0_SE11/ ACMP0_IN4/ EXTAL32 PTC3 FTM0_CH3 30 21 PTC2 ADC0_SE10/ ACMP0_IN5/ XTAL32 ADC0_SE10/ ACMP0_IN5/ XTAL32 PTC2 FTM0_CH2 31 22 PTD7 TSI0_CH10 TSI0_CH10 PTD7 LPUART2_TX FTM2_FLT3 32 23 PTD6 TSI0_CH7 TSI0_CH7 PTD6 LPUART2_RX FTM2_FLT2 33 24 PTD5 TSI0_CH6 TSI0_CH6 PTD5 FTM2_CH3 LPTMR0_ ALT2 34 — PTD12 DISABLED PTD12 FTM2_CH2 LPI2C1_HREQ LPUART2_ RTS 35 — PTD11 DISABLED PTD11 FTM2_CH1 FTM2_QD_ PHA LPUART2_ CTS 36 — PTD10 DISABLED PTD10 FTM2_CH0 FTM2_QD_ PHB 37 — VSS VSS VSS 38 — VDD VDD VDD 39 25 PTC1 ADC0_SE9/ ACMP1_IN3/ TSI0_CH23 ADC0_SE9/ ACMP1_IN3/ TSI0_CH23 PTC1 FTM0_CH1 TSI0_CH24 DAC0_OUT Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 TRGMUX_IN6 LPUART2_ CTS PWT_IN2 TRGMUX_IN7 25 NXP Semiconductors Pinouts 100 64 LQFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 40 26 PTC0 ADC0_SE8/ ACMP1_IN4/ TSI0_CH22 ADC0_SE8/ ACMP1_IN4/ TSI0_CH22 PTC0 FTM0_CH0 41 — PTD9 ACMP1_IN5 ACMP1_IN5 PTD9 LPI2C1_SCL FTM2_FLT3 42 — PTD8 DISABLED PTD8 LPI2C1_SDA FTM2_FLT2 43 27 PTC17 ADC0_SE15 ADC0_SE15 PTC17 FTM1_FLT3 LPI2C1_SCLS 44 28 PTC16 ADC0_SE14 ADC0_SE14 PTC16 FTM1_FLT2 LPI2C1_SDAS 45 29 PTC15 ADC0_SE13 ADC0_SE13 PTC15 FTM1_CH3 46 30 PTC14 ADC0_SE12 ADC0_SE12 PTC14 FTM1_CH2 47 31 PTB3 ADC0_SE7/ TSI0_CH21 ADC0_SE7/ TSI0_CH21 PTB3 FTM1_CH1 LPSPI0_SIN FTM1_QD_ PHA TRGMUX_IN2 48 32 PTB2 ADC0_SE6/ TSI0_CH20 ADC0_SE6/ TSI0_CH20 PTB2 FTM1_CH0 LPSPI0_SCK FTM1_QD_ PHB TRGMUX_IN3 49 — PTC13 DISABLED PTC13 50 — PTC12 DISABLED PTC12 51 — PTC11 DISABLED PTC11 52 — PTC10 DISABLED PTC10 53 33 PTB1 ADC0_SE5 ADC0_SE5 PTB1 LPUART0_TX LPSPI0_SOUT TCLK0 54 34 PTB0 ADC0_SE4 ADC0_SE4 PTB0 LPUART0_RX LPSPI0_PCS0 LPTMR0_ ALT3 55 35 PTC9 DISABLED PTC9 LPUART1_TX LPUART0_ RTS 56 36 PTC8 DISABLED PTC8 LPUART1_RX LPUART0_ CTS 57 37 PTA7 ADC0_SE3/ ACMP1_IN1 ADC0_SE3/ ACMP1_IN1 PTA7 FTM0_FLT2 58 38 PTA6 ADC0_SE2/ ACMP1_IN0 ADC0_SE2/ ACMP1_IN0 PTA6 FTM0_FLT1 59 39 PTE7 DISABLED PTE7 FTM0_CH7 60 40 VSS VSS VSS 61 41 VDD VDD VDD 62 — PTA17 DISABLED PTA17 FTM0_CH6 63 — PTB17 DISABLED PTB17 FTM0_CH5 LPSPI1_PCS3 64 — PTB16 DISABLED PTB16 FTM0_CH4 LPSPI1_SOUT 65 — PTB15 DISABLED PTB15 FTM0_CH3 LPSPI1_SIN 66 — PTB14 ADC1_SE9 ADC1_SE9 PTB14 FTM0_CH2 LPSPI1_SCK 67 42 PTB13 ADC1_SE8 ADC1_SE8 PTB13 FTM0_CH1 68 43 PTB12 ADC1_SE7 ADC1_SE7 PTB12 FTM0_CH0 69 44 PTD4 ADC1_SE6 ADC1_SE6 PTD4 FTM0_FLT3 70 45 PTD3 NMI_b ADC1_SE3 PTD3 LPSPI1_PCS0 FXIO_D5 TRGMUX_IN4 NMI_b 71 46 PTD2 ADC1_SE2 ADC1_SE2 PTD2 LPSPI1_SOUT FXIO_D4 TRGMUX_IN5 72 47 PTA3 ADC1_SE1 ADC1_SE1 PTA3 LPI2C0_SCL LPUART0_TX 26 NXP Semiconductors RTC_CLKIN LPSPI1_PCS1 PWT_IN3 LPUART1_ RTS LPUART1_ CTS EWM_OUT_b EWM_IN Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Pinouts 100 64 LQFP LQFP Pin Name Default ALT0 ADC1_SE0 ALT1 ALT2 ALT3 ALT4 PTA2 LPI2C0_SDA EWM_OUT_b ALT5 ALT6 ALT7 73 48 PTA2 ADC1_SE0 LPUART0_RX 74 — PTB11 DISABLED PTB11 LPI2C0_HREQ 75 — PTB10 DISABLED PTB10 LPI2C0_SDAS 76 — PTB9 DISABLED PTB9 LPI2C0_SCLS 77 — PTB8 DISABLED PTB8 78 49 PTA1 ADC0_SE1/ ACMP0_IN1/ TSI0_CH18 ADC0_SE1/ ACMP0_IN1/ TSI0_CH18 PTA1 FTM1_CH1 LPI2C0_SDAS FXIO_D3 FTM1_QD_ PHA LPUART0_ RTS TRGMUX_ OUT0 79 50 PTA0 ADC0_SE0/ ACMP0_IN0/ TSI0_CH17 ADC0_SE0/ ACMP0_IN0/ TSI0_CH17 PTA0 FTM2_CH1 LPI2C0_SCLS FXIO_D2 FTM2_QD_ PHA LPUART0_ CTS TRGMUX_ OUT3 80 51 PTC7 ADC1_SE5/ TSI0_CH16 ADC1_SE5/ TSI0_CH16 PTC7 LPUART1_TX 81 52 PTC6 ADC1_SE4/ TSI0_CH15 ADC1_SE4/ TSI0_CH15 PTC6 LPUART1_RX 82 — PTA16 DISABLED PTA16 FTM1_CH3 LPSPI1_PCS2 83 — PTA15 DISABLED PTA15 FTM1_CH2 LPSPI0_PCS3 84 53 PTE6 ADC1_SE11 ADC1_SE11 PTE6 LPSPI0_PCS2 85 54 PTE2 ADC1_SE10/ TSI0_CH19 ADC1_SE10/ TSI0_CH19 PTE2 LPSPI0_SOUT LPTMR0_ ALT3 86 — VSS VSS VSS 87 — VDD VDD VDD 88 — PTA14 DISABLED PTA14 FTM0_FLT0 89 55 PTA13 DISABLED PTA13 90 56 PTA12 DISABLED PTA12 91 57 PTA11 DISABLED PTA11 LPUART0_RX FXIO_D1 92 58 PTA10 DISABLED PTA10 LPUART0_TX 93 59 PTE1 TSI0_CH14 TSI0_CH14 PTE1 LPSPI0_SIN LPI2C0_HREQ LPI2C1_SCL 94 60 PTE0 TSI0_CH13 TSI0_CH13 PTE0 LPSPI0_SCK TCLK1 95 61 PTC5 TSI0_CH12 TSI0_CH12 PTC5 FTM2_CH0 RTC_CLKOUT LPI2C1_HREQ 96 62 PTC4 SWD_CLK ACMP0_IN2 PTC4 FTM1_CH0 RTC_CLKOUT 97 63 PTA5 RESET_b PTA5 98 64 PTA4 SWD_DIO PTA4 ACMP0_OUT 99 — PTA9 DISABLED PTA9 FXIO_D7 100 — PTA8 DISABLED PTA8 FXIO_D6 LPUART1_ RTS PWT_IN3 LPUART1_ CTS EWM_IN BUSOUT LPI2C1_SCLS LPI2C1_SDAS Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 FXIO_D0 LPI2C1_SDA FTM1_FLT2 FTM2_QD_ PHB EWM_IN FTM1_QD_ PHB TCLK1 SWD_CLK RESET_b EWM_OUT_b SWD_DIO FTM1_FLT3 27 NXP Semiconductors Pinouts 4.2 Port control and interrupt summary The following table provides more information regarding the Port Control and Interrupt configurations. Table 6. Ports summary Feature Port A Port B Port C Port D Port E Pull select control Yes Yes Yes Yes Yes Pull select at reset PTA4/PTA5=Pull up, Others=No No PTC4=Pull down, Others=No PTD3=Pull up, Others=No No Pull enable control Yes Yes Yes Yes Yes Pull enable at reset PTA4/ PTA5=Enabled; Others=Disabled Disabled PTC4=Enabled; Others=Disabled PTD3=Enabled; Others=Disabled Disabled Passive filter enable control PTA5=Yes; Others=No No No PTD3=Yes; Others=No No Passive filter enable at reset PTA5=Enabled; Others=Disabled Disabled Disabled Disabled Disabled Open drain enable I2C and UART control Tx=Enabled; Others=Disabled I2C and UART Tx=Enabled; Others=Disabled I2C and UART Tx=Enabled; Others=Disabled I2C and UART Tx=Enabled; Others=Disabled I2C and UART Tx=Enabled; Others=Disabled Open drain enable Disabled at reset Disabled Disabled Disabled Disabled Drive strength enable control No PTB4/PTB5 only No PTD0/PTD1/ PTE0/PTE1 only PTD15/PTD16 only Drive strength enable at reset Disabled Disabled Disabled Disabled Disabled Pin mux control Yes Yes Yes Yes Yes Pin mux at reset PTA4/PTA5=ALT7; ALT0 Others=ALT0 PTC4=ALT7; Others=ALT0 PTD3=ALT7; Others=ALT0 ALT0 Yes Yes Yes Yes Yes Interrupt and DMA Yes request Yes Yes Yes Yes No No No Yes Lock bit Digital glitch filter No 4.3 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. 28 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Pinouts 4.3.1 Core Modules Table 7. SWD Signal Descriptions Chip signal name Module signal name Description I/O SWD_CLK SWD_CLK Serial Wire Clock I SWD_DIO SWD_DIO Serial Wire Data I/O 4.3.2 System Modules Table 8. System Signal Descriptions Chip signal name Module signal name Description I/O NMI_b — Non-maskable interrupt NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin. RESET_b — Reset bidirectional signal VDD — MCU power I VSS — MCU ground I I I/O Table 9. EWM Signal Descriptions Chip signal name Module signal name EWM_IN EWM_in EWM_OUT_b EWM_out Description I/O EWM input for safety status of external safety circuits. The polarity of EWM_IN is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM reset out signal O 4.3.3 Clock Modules Table 10. OSC (in SCG) Signal Descriptions Chip signal name Module signal name EXTAL EXTAL XTAL XTAL Description I/O External clock/Oscillator input I Oscillator output O Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 29 NXP Semiconductors Pinouts Table 11. RTC Oscillator (OSC32) Signal Descriptions Chip signal name Module signal name EXTAL32 EXTAL32 XTAL32 XTAL32 Description I/O 32.768 kHz oscillator input I 32.768 kHz oscillator output O 4.3.4 Analog Table 12. ADC0 Signal Descriptions Chip signal name Module signal name ADC0_SE[15:0] AD[15:0] VREFH Description I/O Single-Ended Analog Channel Inputs I VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I Table 13. ADC1 Signal Descriptions Chip signal name Module signal name ADC1_SE[11:0] AD[11:0] VREFH Description I/O Single-Ended Analog Channel Inputs I VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I Table 14. ACMP0 Signal Descriptions Chip signal name Module signal name Description I/O ACMP0_IN[5:0] IN[5:0] Analog voltage inputs I ACMP0_OUT CMPO Comparator output O DAC0_OUT — DAC output O Table 15. ACMP1 Signal Descriptions Chip signal name Module signal name Description I/O ACMP1_IN[5:0] IN[5:0] Analog voltage inputs I ACMP1_OUT CMPO Comparator output O 30 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Pinouts 4.3.5 Timer Modules Table 16. LPTMR0 Signal Descriptions Chip signal name Module signal name Description LPTMR0_ALT[3:1] LPTMR_ALTn Pulse Counter Input pin I/O I Table 17. RTC Signal Descriptions Chip signal name Module signal name Description I/O RTC_CLKOUT RTC_CLKOUT 1 Hz square-wave output or 32 kHz clock O Table 18. FTM0 Signal Descriptions Chip signal name Module signal name Description I/O FTM0_CH[7:0] CHn FTM channel (n), where n can be 7-0 I/O FTM0_FLT[3:0] FAULTj Fault input (j), where j can be 3-0 I TCLK[2:0] EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. I Table 19. FTM1 Signal Descriptions Chip signal name Module signal name Description I/O FTM1_CH[3:0] CHn FTM channel (n), where n can be 3-0 I/O FTM1_FLT[3:2] FAULTj Fault input (j), where j can be 3-2 I TCLK[2:0] EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. I Table 20. FTM2 Signal Descriptions Chip signal name FTM2_CH[3:0] Module signal name Description CHn I/O FTM channel (n), where n can be 3-0 I/O FTM2_FLT[3:2] FAULTj Fault input (j), where j can be 3-2 I TCLK[2:0] EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. I Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 31 NXP Semiconductors Pinouts 4.3.6 Communication Interfaces Table 21. LPSPIn Signal Descriptions Chip signal name Module signal name Description I/O LPSPIn_SOUT SOUT Serial Data Out O LPSPIn_SIN SIN Serial Data In I LPSPIn_SCK SCK Serial Clock I/O LPSPIn_PCS[3:0] PCS[3:0] Peripheral Chip Select 0-3 I/O Table 22. LPI2Cn Signal Descriptions Chip signal name Module signal name Description I/O LPI2Cn_SCL SCL Bidirectional serial clock line of the I2C system. I/O LPI2Cn_SDA SDA Bidirectional serial data line of the I2C system. I/O LPI2Cn_HREQ HREQ Host request, can initiate an LPI2C master transfer if asserted and the I2C bus is idle. LPI2Cn_SCLS SCLS Secondary I2C clock line. I/O LPI2Cn_SDAS SDAS Secondary I2C data line. I/O I Table 23. LPUARTn Signal Descriptions Chip signal name Module signal name Description I/O LPUARTn_TX LPUART_TXD Transmit data I/O LPUARTn_RX LPUART_RXD Receive data I LPUARTn_CTS LPUART_CTS Clear to send I LPUARTn_RTS LPUART_RTS Request to send O Table 24. FlexIO Signal Descriptions Chip signal name Module signal name FXIO_D[7:0] FXIO_D[7:0] 32 NXP Semiconductors Description I/O Bidirectional FlexIO Shifter and Timer pin inputs/outputs I/O Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Pinouts 4.3.7 Human-Machine Interfaces (HMI) Table 25. GPIO Signal Descriptions Chip signal name Module signal name Description I/O PTA[17:0] PORTA17–PORTA0 General-purpose input/output I/O PTB[17:0] PORTB17–PORTB0 General-purpose input/output I/O PTC[17:0] PORTC17–PORTC0 General-purpose input/output I/O PTD[17:0] PORTD17–PORTD0 General-purpose input/output I/O PTE[16:0] PORTE16–PORTE0 General-purpose input/output I/O Table 26. TSI0 Signal Descriptions Chip signal name Module signal name TSI0_CH[24:0] TSI[24:0] Description I/O TSI sensing pins or GPIO pins I/O 4.4 Pinout diagram The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous table of Pin Assignments. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 33 NXP Semiconductors PTA11 PTA12 PTA13 PTA14 VDD VSS PTE2 PTE6 PTA15 PTA16 PTC6 PTC7 92 91 90 89 88 87 86 85 84 83 82 81 80 PTB9 PTA10 93 PTB8 PTE1 94 76 PTE0 95 77 PTC5 96 PTA0 PTC4 97 PTA1 PTA5 98 79 PTA4 99 78 PTA8 PTA9 100 Pinouts PTE16 1 75 PTB10 PTE15 2 74 PTB11 PTD1 3 73 PTA2 PTD0 4 72 PTA3 PTE11 5 71 PTD2 PTE10 6 70 PTD3 PTE13 7 69 PTD4 PTE5 8 68 PTB12 PTE4 9 67 PTB13 VDD 10 66 PTB14 VDDA 11 65 PTB15 VREFH 12 64 PTB16 VREFL 13 63 PTB17 44 45 46 47 48 49 50 PTC16 PTC15 PTC14 PTB3 PTB2 PTC13 PTC12 PTC11 43 51 42 25 PTD8 PTD13 PTC17 PTC10 PTD9 PTD14 41 PTB1 52 40 53 24 PTC0 23 39 PTE9 PTC1 PTB0 38 54 VDD 22 37 PTC9 PTD15 36 55 VSS 21 PTD10 PTC8 PTD16 35 56 PTD11 20 34 PTA7 PTD17 PTD12 57 33 19 PTD5 PTE12 32 PTA6 31 58 PTD6 18 PTD7 PTE7 PTE3 PTC2 59 30 17 29 VSS PTE14 28 60 PTB4 16 PTC3 VDD PTB6 27 PTA17 61 26 62 15 PTB5 14 PTE8 VSS PTB7 Figure 7. 100 LQFP Pinout Diagram 34 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 PTA4 PTA5 PTC4 PTC5 PTE0 PTE1 PTA10 PTA11 PTA12 PTA13 PTE2 PTE6 PTC6 PTC7 PTA0 PTA1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinouts VREFH 9 40 VSS VREFL / VSS 10 39 PTE7 PTB7 11 38 PTA6 PTB6 12 37 PTA7 PTE3 13 36 PTC8 PTD16 14 35 PTC9 PTD15 15 34 PTB0 PTE9 16 33 PTB1 32 VDD PTB2 41 31 8 PTB3 VDDA 30 PTB13 PTC14 42 29 7 PTC15 VDD 28 PTB12 PTC16 43 27 6 PTC17 PTE4 26 PTD4 PTC0 44 25 5 PTC1 PTE5 24 PTD3 PTD5 45 23 4 PTD6 PTE10 22 PTD2 PTD7 46 21 3 PTC2 PTE11 20 PTA3 PTC3 47 19 2 PTB4 PTD0 18 PTA2 PTB5 48 17 1 PTE8 PTD1 Figure 8. 64 LQFP Pinout Diagram 4.5 Package dimensions The following figures show the dimensions of the package options for the devices supported by this document. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 35 NXP Semiconductors Pinouts Figure 9. 100-pin LQFP package dimensions 1 36 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Pinouts Figure 10. 100-pin LQFP package dimensions 2 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 37 NXP Semiconductors Pinouts Figure 11. 64-pin LQFP package dimensions 1 38 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Pinouts Figure 12. 64-pin LQFP package dimensions 2 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 39 NXP Semiconductors Electrical characteristics 5 Electrical characteristics 5.1 Terminology and guidelines 5.1.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. 40 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 5.1.2 Examples EX AM PL E Operating rating: EX AM PL E Operating requirement: EX AM PL E Operating behavior that includes a typical value: 5.1.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 5.0 V Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 41 NXP Semiconductors Electrical characteristics 5.1.4 Relationship between ratings and operating requirements O a gr tin ra pe g tin ( ) in. (m nt me n.) mi t era Op ing e uir req g tin era Op t en em uir q e r ax (m .) rat pe ing g tin ra ax (m .) O Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) dli n Ha ng ng i rat x.) ) in. (m li nd Ha ng i rat a (m ng Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 5.1.5 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 5.2 Ratings 5.2.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 42 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 5.2.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.2.3 ESD handling ratings Symbol Description VHBM Electrostatic discharge voltage, human body model VCDM Electrostatic discharge voltage, charged-device model ILAT Min. Max. Unit Notes − 6000 6000 V 1 2 All pins except the corner pins − 500 500 V Corner pins only − 750 750 V Latch-up current at ambient temperature upper limit − 100 100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 5.2.4 Voltage and current operating ratings NOTE Functional operating conditions appear in the "DC electrical specifications". Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. Table 27. Voltage and current operating ratings Symbol Description VDD Supply voltage IDD Digital supply current Min. Max. –0.3 1 — 5.8 60 Unit V mA Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 43 NXP Semiconductors Electrical characteristics Table 27. Voltage and current operating ratings (continued) Symbol VIO ID VDDA Description IO pin input voltage Min. Max. Unit VSS – 0.3 VDD + 0.3 V –25 25 mA VDD – 0.1 VDD + 0.1 V Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage 1. 60s lifetime - No restrictions, i.e. the part can switch. 10 hours lifetime - Device in reset, i.e. the part cannot switch. 5.3 General 5.3.1 Nonswitching electrical specifications 5.3.1.1 Voltage and current operating requirements Table 28. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 2.7 5.5 V VDDA Analog supply voltage 2.7 5.5 V VDD – VDDA VDD-to-VDDA differential voltage – 0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage – 0.1 0.1 V IICIO IICcont VODPU Notes DC injection current — single pin VIN < VSS - 0.3 V (Negative current injection) −3 — mA VIN > VDD + 0.3 V (Positive current injection) — +3 mA Contiguous pin DC injection current — regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins − 25 + 25 mA Open drain pullup voltage level VDD VDD V 1 2 1. All pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VSS – 0.3V or greater than VDD + 0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VSS – 0.3V–VIN)/|IICIO|. The positive injection current limiting resistor is calculated as R=[VIN–(VDD + 0.3V)]/|IICIO|. The actual resistor values should be an order of magnitude higher to tolerate transient voltages. 2. Open drain outputs must be pulled to VDD. 44 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 5.3.1.2 DC electrical specifications at 3.3 V Range and 5.0 V Range Table 29. DC electrical specifications Symbol VDD Parameter I/O Supply Voltage 1 Value Unit Min Typ Max 2.7 3.3 4 V Notes @ VDD = 3.3 V @ VDD = 5.0 V Vih 4 — 5.5 V 0.7 × VDD — VDD + 0.3 V 0.65 × VDD — VDD + 0.3 V VSS − 0.3 — 0.3 × VDD V VSS − 0.3 — 0.35 × VDD V 0.06 × VDD — — V 2.8 — — mA @ VDD = 5.0 V 4.8 — — mA Normal drive I/O current sink capability measured when pad = 0.8 V 2.4 — — mA @ VDD = 5.0 V 4.4 — — mA High drive I/O current source capability measured when pad = (VDD − 0.8 V), 2 10.8 — — mA @ VDD = 5.0 V 18.5 — — mA 3 High drive I/O current sink capability measured when pad = 0.8 V4 10.1 — — mA 18.5 — — mA 3 — — 300 nA Input Buffer High Voltage @ VDD = 3.3 V @ VDD = 5.0 V Vil Input Buffer Low Voltage @ VDD = 3.3 V @ VDD = 5.0 V Vhys Ioh_5 Input Buffer Hysteresis Normal drive I/O current source capability measured when pad = (VDD − 0.8 V) @ VDD = 3.3 V Iol_5 @ VDD = 3.3 V Ioh_20 @ VDD = 3.3 V Iol_20 @ VDD = 3.3 V @ VDD = 5.0 V I_leak VOH IOHT Hi-Z (Off state) leakage current (per pin) Output high voltage 5, 6 7 Normal drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = − 2.8 mA) VDD – 0.8 — — V Normal drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = − 4.8 mA) VDD – 0.8 — — V High drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = − 10.8 mA) VDD – 0.8 — — V High drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = − 18.5 mA) VDD – 0.8 — — V — — 100 mA Output high current total for all ports Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 45 NXP Semiconductors Electrical characteristics Table 29. DC electrical specifications (continued) Symbol Parameter Value Min VOL IOLT IIN Typ Unit Notes Max Output low voltage 7 Normal drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = − 2.8 mA) — — 0.8 V Normal drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = − 4.8 mA) — — 0.8 V High drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = − 10.8 mA) — — 0.8 V High drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = − 18.5 mA) — — 0.8 V Output low current total for all ports — — 100 mA Input leakage current (per pin) for full temperature range 8, 7 @ VDD = 3.3 V All pins other than high drive port pins — 0.002 0.5 μA High drive port pins — 0.004 0.5 μA Input leakage current (per pin) for full temperature range @ VDD = 5.5 V RPU All pins other than high drive port pins — 0.005 0.5 μA High drive port pins — 0.010 0.5 μA Internal pull-up resistors 20 — 65 kΩ @ VDD = 5.0 V 20 — 50 kΩ Internal pull-down resistors 20 — 65 kΩ 20 — 50 kΩ 9 @ VDD = 3.3 V RPD 10 @ VDD = 3.3 V @ VDD = 5.0 V 1. Max power supply ramp rate is 500 V/ms. 2. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_5 value given above. 3. The 20 mA I/O pin is capable of switching a 50 pF load at up to 40 MHz. 4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_5 value given above. 5. Refers to the current that leaks into the core when the pad is in Hi-Z (Off state). 6. Maximum pin leakage current at the ambient temperature upper limit. 7. PTD0, PTD1, PTD15, PTD16, PTB4, PTB5, PTE0 and PTE1 I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 8. Refers to the pin leakage on the GPIOs when they are OFF. 9. Measured at VDD supply voltage = VDD min and input V = VSS 10. Measured at VDD supply voltage = VDD min and input V = VDD 46 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 5.3.1.3 Voltage regulator electrical characteristics VSS VDD C DEC VDD VDDA 64 LQFP Package VREFH CREF VSS C DEC VDD C DEC VREFL 100 LQFP Package C DEC VREFH CREF C DEC C DEC VDDA VDD C DEC VDD VSS VREFL / VSS VSS VDD VSS C DEC Figure 13. Pinout decoupling Table 30. Voltage regulator electrical characteristics Symbol Description Min. Typ. Max. Unit CREF, 1, 2 ADC reference high decoupling capacitance — 100 — nF CDEC2, 3 Recommended decoupling capacitance — 100 — nF 1. For improved ADC performance it is recommended to use 1 nF X7R/C0G and 10 nF X7R ceramics in parallel. 2. The capacitors should be placed as close as possible to the VREFH/VREFL pins or corresponding VDD/VSS pins. 3. The requirement and value of of CDEC will be decided by the device application requirement. 5.3.1.4 LVR, LVD and POR operating requirements Table 31. VDD supply LVR, LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Rising and Falling VDD POR detect voltage 1.1 1.6 2.0 V VLVRX LVRX falling threshold (RUN and STOP modes) 2.53 2.58 2.64 V — 45 — mV 1.97 2.12 2.44 V VLVRX_HYST VLVRX_LP LVRX hysteresis LVRX falling threshold (VLPS/VLPR modes) VLVRX_LP_HYST LVRX hysteresis (VLPS/VLPR modes) VLVD VLVD_HYST VLVW VLVW_HYST VBG — 40 — mV Falling low-voltage detect threshold 2.8 2.88 3 V LVD hysteresis — 50 — mV 4.19 4.31 4.5 Falling low-voltage warning threshold LVW hysteresis Bandgap voltage reference Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 68 0.97 1.00 1 1 V mV 1.03 Notes 1 V 47 NXP Semiconductors Electrical characteristics 1. Rising threshold is the sum of falling threshold and hysteresis voltage. 5.3.1.5 Power mode transition operating behaviors Table 32. Power mode transition operating behaviors Description System Clock Core, Bus, Flash frequency (MHz) Typ. (μs)1 Min. Max. (μs)2 STOP→RUN FIRC 48, 24, 24 — 7.15 11.8 STOP→RUN FLL 72, 24, 24 — 7.51 13.4 VLPS→RUN FIRC 48, 24, 24 — 7.15 11.8 VLPS→RUN FLL 72, 24, 24 — 9.8 15.9 RUN→VLPR FLL→SIRC 72, 24, 24→4, 1, 1 — 13.6 14.4 VLPR→RUN SIRC→FIRC 4, 1, 1→48, 24, 24 — 24 30.7 VLPR→RUN SIRC→FLL 4, 1, 1→72, 24, 24 — 27 35.7 WAIT→RUN FIRC 48, 24, 24 — 0.660 0.760 WAIT→RUN FLL 72, 24, 24 — 0.516 0.653 VLPW→VLPR SIRC 4, 1, 1 — 20.7 24.9 VLPS→VLPR SIRC 4, 1, 1 — 17.9 22.8 VLPW→RUN FIRC (reset value) 48, 24, 24 (reset value) — 127 146 tPOR3 FIRC (reset value) 48, 24, 24 (reset value) — 111 127 1. Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V. 2. Max value is mean+6×sigma of tested values at the worst case of ambient temperature range and VDD 2.7 V to 5.5 V. 3. After a POR event, the amount of time from the point VDD reaches the reference voltage 2.7 V to execution of the first instruction, across the operating temperature range of the chip. 5.3.1.6 Power consumption The following table shows the power consumption targets for the device in various modes of operations. NOTE The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 33. Power consumption operating behaviors Mode RUN Symbol IDD_RUN Clock Configura tion LPFLL Description Temperat ure Running CoreMark in Flash in Compute 25 ℃ Operation mode. 105 ℃ Core@72MHz, bus @24MHz, flash @24MHz, VDD=5V Min Typ Max1 — 11.19 11.43 — 11.70 12.00 Unit mA Table continues on the next page... 48 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics Table 33. Power consumption operating behaviors (continued) Mode Symbol Clock Configura tion LPFLL LPFLL Description Temperat ure Running CoreMark in Flash all peripheral 25 ℃ clock disabled. 105 ℃ Core@72MHz, bus @24MHz, flash @24MHz, VDD=5V Min Typ Max1 — 12.15 12.41 — 12.67 12.99 25 ℃ — 13.53 13.82 105 ℃ — 14.07 14.43 25 ℃ — 8.81 9.00 105 ℃ — 9.26 9.49 25 ℃ — 10.22 10.44 105 ℃ — 10.67 10.94 Running CoreMark in Flash in Compute 25 ℃ Operation mode. 105 ℃ Core@48MHz, bus @24MHz, flash @24MHz, VDD=5V — 8.50 8.69 — 8.88 9.08 Running CoreMark in Flash all peripheral 25 ℃ clock disabled. 105 ℃ Core@48MHz, bus @24MHz, flash @24MHz, VDD=5V — 9.37 9.58 — 9.76 9.98 25 ℃ — 10.51 10.75 105 ℃ — 10.90 11.15 25 ℃ — 7.00 7.16 105 ℃ — 7.41 7.58 — 1070 1136 — 1110 1178 — 1180 1253 Running CoreMark in Flash, all peripheral clock enabled. Unit Core@72MHz, bus@24MHz, flash @24MHz, VDD=5V LPFLL Running While(1) loop in Flash, all peripheral clock disabled. Core@72MHz, bus@24MHz, flash @24MHz, VDD=5V LPFLL Running While(1) loop in Flash all peripheral clock enabled. Core@72MHz , bus@24MHz, flash @24MHz, VDD=5V IRC48M IRC48M IRC48M Running CoreMark in Flash, all peripheral clock enabled. Core@48MHz, bus@24MHz, flash @24MHz, VDD=5V IRC48M Running While(1) loop in Flash, all peripheral clock disabled. Core@48MHz, bus@24MHz, flash @24MHz, VDD=5V VLPR IDD_VLPR IRC8M Very Low Power Run Core Mark in Flash 25 ℃ in Compute Operation mode. μA Core@4MHz, bus @1MHz, flash @1MHz, VDD=5V IRC8M Very Low Power Run Core Mark in Flash 25 ℃ all peripheral clock disabled. Core@4MHz, bus @1MHz, flash @1MHz, VDD=5V IRC8M Very Low Power Run Core Mark in Flash 25 ℃ all peripheral clock enabled. Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 49 NXP Semiconductors Electrical characteristics Table 33. Power consumption operating behaviors (continued) Mode Symbol Clock Configura tion Description Temperat ure Min Typ Max1 Unit Core@4MHz, bus @1MHz, flash @1MHz, VDD=5V 25 ℃ — 747 793 25 ℃ — 813 863 25 ℃ — 585 621 25 ℃ — 641 680 LPFLL core disabled, system@72MHz, bus 25 ℃ @24MHz, flash disabled (flash doze enabled), VDD=5 V, all peripheral clocks disabled — 5.95 6.09 IRC48M core disabled, system@48 MHz, bus 25 ℃ @24MHz, flash disabled (flash doze enabled), VDD=5 V, all peripheral clocks disabled — 4.86 4.97 IRC8M Very Low Power Wait current, core disabled system@4MHz, bus and flash@1MHz, all peripheral clocks disabled, VDD=5V 25 ℃ — 657 698 IRC2M Very Low Power Wait current, core disabled system@2MHz, bus and flash@1MHz, all peripheral clocks disabled, VDD=5V 25 ℃ — 550 584 - Stop mode current, VDD=5V, clock bias enabled 2 25 ℃ and below — 27 37 50 ℃ — 45 63 85 ℃ — 135 189 105 ℃ — 269 377 25 ℃ and below — 26 36 50 ℃ — 47 66 85 ℃ — 146 204 IRC8M Very Low Power Run While(1) loop in Flash all peripheral clock disabled. Core@4MHz, bus @1MHz, flash @1MHz, VDD=5V IRC8M Very Low Power Run While(1) loop in Flash all peripheral clock enabled. Core@4MHz, bus @1MHz, flash @1MHz, VDD=5V IRC2M Very Low Power Run While(1) loop in Flash all peripheral clock disabled. Core@2MHz, bus @1MHz, flash @1MHz, VDD=5V IRC2M Very Low Power Run While(1) loop in Flash all peripheral clock enabled. Core@2MHz, bus @1MHz, flash @1MHz, VDD=5V WAIT VLPW STOP STOP IDD_WAIT IDD_VLPW IDD_STOP IDD_STOP - Stop mode current, VDD=5V, clock bias disabled 2 mA μA μA μA Table continues on the next page... 50 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics Table 33. Power consumption operating behaviors (continued) Mode Symbol Clock Configura tion Description Temperat ure 105 ℃ VLPS IDD_VLPS VLPS IDD_VLPS - - Min Max1 Typ — 277 388 — 27 37 50 ℃ — 45 64 85 ℃ — 134 187 105 ℃ — 267 375 — 21 29 50 ℃ — 29 41 85 ℃ — 66 92 105 ℃ — 109 153 Very Low Power Stop current, VDD=5V, 25 ℃ and clock bias enabled 2 below Very Low Power Stop current, VDD=5V, 25 ℃ and clock bias disabled 2 below Unit μA μA 1. These values are based on characterization but not covered by test limits in production. 2. PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode. NOTE CoreMark benchmark compiled using IAR 7.40 with optimization level high, optimized for balanced. 5.3.1.6.1 Low power mode peripheral current adder — typical value Symbol ILPTMR Description Typical LPTMR peripheral adder measured by placing the device in VLPS mode with LPTMR enabled using LPO. Includes LPO power consumption. 366 nA ICMP CMP peripheral adder measured by placing the device in VLPS mode with CMP enabled using the 8-bit DAC and a single external input for compare. 8-bit DAC enabled with half VDDA voltage, low speed mode. Includes 8-bit DAC power consumption. 16 μA IRTC RTC peripheral adder measured by placing the device in VLPS mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC counter enabled. Includes EXTAL32 (32 kHz external crystal) power consumption. 312 nA ILPUART LPUART peripheral adder measured by placing the device in VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. (SIRC 8 MHz) 79 μA IFTM FTM peripheral adder measured by placing the device in VLPW mode with selected clock source, outputting the edge aligned PWM of 100 Hz frequency. 45 μA Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 51 NXP Semiconductors Electrical characteristics Symbol Description Typical IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in VLPS mode. ADC is configured for low power mode using SIRC clock source, 8-bit resolution and continuous conversions. 484 μA ILPI2C LPI2C peripheral adder measured by placing the device in VLPS mode with selected clock source sending START and Slave address, waiting for RX data. Includes the DMA power consumption. 179 μA ILPIT LPIT peripheral adder measured by placing the device in VLPS mode with internal SIRC 8 MHz enabled in Stop mode. Includes selected clock source power consumption. 18 μA ILPSPI LPSPI peripheral adder measured by placing the device in VLPS mode with selected clock source, output data on SOUT pin with SCK 500 kbit/s. Includes the DMA power consumption. 565 μA 5.3.1.6.2 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • • • • SCG in SOSC for both Run and VLPR modes No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFE Run mode Current vs Core Freq Temperature = 25, VDD= 5V 12.00E-03 Current Consumption(A) 10.00E-03 8.00E-03 Clock Gates 6.00E-03 ALLOFF ALLON 4.00E-03 2.00E-03 000.00E+00 1 2 4 6 1-1 12 24 48 72 1-2 1-3 Core Freq Core : Flash Figure 14. Run mode supply current vs. core frequency 52 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics VLPR Current Vs Core Freq Temperature = 25, VDD= 5V 900.00E-06 Current Consumption (A) 800.00E-06 700.00E-06 Clock Gates 600.00E-06 ALLOFF 500.00E-06 ALLON 400.00E-06 300.00E-06 200.00E-06 100.00E-06 000.00E+00 1 2 4 1-1 1-2 1-4 Core Freq Core : Flash Figure 15. VLPR mode supply current vs. core frequency 5.3.1.7 EMC performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components, and MCU software operation play a significant role in the EMC performance. The system designer can consult the following applications notes, available on http://www.nxp.com for advice and guidance specifically targeted at optimizing EMC performance. • AN2321: Designing for Board Level Electromagnetic Compatibility • AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers • AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers • AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications • AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems 5.3.1.7.1 EMC radiated emissions operating behaviors EMC measurements to IC-level IEC standards are available from NXP on request. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 53 NXP Semiconductors Electrical characteristics 5.3.1.7.2 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions. 1. Go to http://www.nxp.com. 2. Perform a keyword search for “EMC design”. 3. Select the "Documents" category and find the application notes. 5.3.1.8 Symbol Capacitance attributes Table 34. Capacitance attributes Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF NOTE Please refer to External Oscillator electrical specifications for EXTAL/XTAL pins. 5.3.2 Switching specifications 5.3.2.1 Device clock specifications Table 35. Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode fSYS System and core clock — 72 MHz fBUS Bus clock — 24 MHz fFLASH Flash clock — 25 MHz fLPTMR LPTMR clock — 48 MHz VLPR / VLPW mode1 fSYS System and core clock — 4 MHz fBUS Bus clock — 1 MHz fFLASH Flash clock — 1 MHz fERCLK External reference clock — 16 MHz fLPTMR LPTMR clock — 13 MHz 1. The frequency limitations in VLPR / VLPW mode here override any frequency specification listed in the timing specification for any other module. 54 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 5.3.2.2 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 16. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume that the output pins have the following characteristics. • CL=30 pF loads • Normal drive strength 5.3.2.3 General AC specifications These general purpose specifications apply to all signals configured for GPIO, UART, and timers. Table 36. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1, 2 External RESET and NMI pin interrupt pulse width — Asynchronous path 100 — ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, passive filter disabled) — Asynchronous path 50 — ns 4 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater of synchronous and asynchronous timing must be met. 3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be recognized. 4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 55 NXP Semiconductors Electrical characteristics 5.3.2.4 AC specifications at 3.3 V range Table 37. Functional pad AC specifications Characteristic Symbol Min I/O Supply Voltage Vdd 1 2.7 Typ Max Unit 4 V 1. Max power supply ramp rate is 500 V/ms. Prop Delay (ns) 1 Name Normal drive I/O pad Drive Load (pF) Max Min Max 17.5 5 17 25 28 9 32 50 19 5 17 25 26 9 33 50 4 1.2 3 0.5 High drive I/O pad CMOS Input Rise/Fall Edge (ns) 2 3 1. Propagation delay measured from 50% of core side input to 50% of the output. 2. Edges measured using 20% and 80% of the VDD supply. 3. Input slope = 2 ns. NOTE All measurements were taken accounting for 150 mV drop across VDD and VSS. 5.3.2.5 AC specifications at 5 V range Table 38. Functional pad AC specifications Characteristic Symbol Min I/O Supply Voltage Vdd 1 4 Typ Max Unit 5.5 V 1. Max power supply ramp rate is 500 V/ms. Prop Delay (ns) 1 Name Normal drive I/O pad High drive I/O pad CMOS Input 3 Rise/Fall Edge (ns) 2 Drive Load (pF) Max Min Max 12 3.6 10 25 18 8 17 50 13 3.6 10 25 19 8 19 50 3 1.2 2.8 0.5 1. As measured from 50% of core side input to 50% of the output. 2. Edges measured using 20% and 80% of the VDD supply. 3. Input slope = 2 ns. 56 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics NOTE All measurements were taken accounting for 150 mV drop across VDD and VSS. 5.3.3 Thermal specifications 5.3.3.1 Symbol Thermal operating requirements Table 39. Thermal operating requirements Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + RΘJA × chip power dissipation. 5.3.3.2 5.3.3.2.1 Thermal attributes Description The tables in the following sections describe the thermal characteristics of the device. NOTE Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting side (board) temperature, ambient temperature, air flow, power dissipation or other components on the board, and board thermal resistance. 5.3.3.2.2 Thermal characteristics for the 64-pin LQFP package Table 40. Thermal characteristics for the 64-pin LQFP package Rating Conditions Symbol Value Unit Thermal resistance, Junction to Ambient (Natural Convection)1, 2 Single layer board (1s) RθJA 62 °C/W Thermal resistance, Junction to Ambient (Natural Convection)1, 2 Four layer board (2s2p) RθJA 44 °C/W Thermal resistance, Junction to Ambient (@200 ft/min)1, 3 Single layer board (1s) RθJMA 50 °C/W Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 57 NXP Semiconductors Electrical characteristics Table 40. Thermal characteristics for the 64-pin LQFP package (continued) Rating Conditions Symbol Value Unit Thermal resistance, Junction to Ambient (@200 ft/min)1, 3 Four layer board (2s2p) RθJMA 37 °C/W Thermal resistance, Junction to Board4 — RθJB 26 °C/W Thermal resistance, Junction to Case 5 — RθJC 14 °C/W Thermal resistance, Junction to Package Top6 Natural Convection ψJT 2 °C/W 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. 3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 5.3.3.2.3 Thermal characteristics for the 100-pin LQFP package Table 41. Thermal characteristics for the 100-pin LQFP package Rating Conditions Symbol Value Unit Thermal resistance, Junction to Ambient (Natural Convection)1, 2 Single layer board (1s) RθJA 59 °C/W Thermal resistance, Junction to Ambient (Natural Convection)1, 2 Four layer board (2s2p) RθJA 46 °C/W Thermal resistance, Junction to Ambient (@200 ft/min)1, 3 Single layer board (1s) RθJMA 49 °C/W Thermal resistance, Junction to Ambient (@200 ft/min)1, 3 Four layer board (2s2p) RθJMA 40 °C/W Thermal resistance, Junction to Board4 — RθJB 31 °C/W 5 — RθJC 16 °C/W Natural Convection ψJT 2 °C/W Thermal resistance, Junction to Case Thermal resistance, Junction to Package Top6 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. 3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 58 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 5.3.3.2.4 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from this equation: TJ = TA + (RθJA × PD) where: • TA = ambient temperature for the package (°C) • RθJA = junction to ambient thermal resistance (°C/W) • PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where: • RθJA = junction to ambient thermal resistance (°C/W) • RθJC = junction to case thermal resistance (°C/W) • RθCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 59 NXP Semiconductors Electrical characteristics To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: TJ = TT + (ΨJT × PD) where: • TT = thermocouple temperature on top of the package (°C) • ΨJT = thermal characterization parameter (°C/W) • PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 5.4 Peripheral operating requirements and behaviors 5.4.1 System modules There are no specifications necessary for the device's system modules. 5.4.2 Clock interface modules 5.4.2.1 5.4.2.1.1 Oscillator electrical specifications External Oscillator electrical specifications 60 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics Single input buffer (EXTAL32 WAVE) mux ref_clk Differential input comparator (VLP mode) Peak detector LP mode Driver (VLP mode) Pull down resistor (OFF) ESD PAD 300 ohms ESD PAD 300 ohms EXTAL32 pin XTAL32 pin Series resistor for current limitation C1 Crystal or resonator C2 Figure 17. Oscillator connections scheme (OSC32) Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 61 NXP Semiconductors Electrical characteristics Single input buffer (EXTAL WAVE) mux ref_clk Differential input comparator (HG/LP mode) Peak detector LP mode Driver (HG/LP mode) Pull down resistor (OFF) ESD PAD 300 ohms ESD PAD 40 ohms XTAL pin EXTAL pin 1M ohms Feedback Resistor 1 C1 Crystal or resonator Series resistor for current limitation C2 NOTE: 1. 1M Feedback resistor is needed only for HG mode. Figure 18. Oscillator connections scheme (OSC) NOTE Data values in the following "External Oscillator electrical specifications" tables are from simulation. Table 42. External Oscillator electrical specifications (OSC32) Symbol Description Min. VDD Supply voltage IDDOSC32 Supply current gmXOSC32 Oscillator transconductance VIH Input high voltage — EXTAL32 pin in external clock mode Typ. Max. Unit 2.7 — 5.5 V — 500 — nA 6 — 9 µA/V 0.7 × VDD — VDD+0.3 V Notes 1 Table continues on the next page... 62 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics Table 42. External Oscillator electrical specifications (OSC32) (continued) Symbol Description Min. Typ. Max. Unit 0.65 × VDD — VDD+0.3 V VSS –0.3 — 0.3 × VDD V VSS –0.3 — 0.35 × VDD V Notes @VDD=3.3 V @VDD=5.0 V VIL Input low voltage — EXTAL32 pin in external clock mode @VDD=3.3 V @VDD=5.0 V C1 EXTAL32 load capacitance — — — 2 C2 XTAL32 load capacitance — — — 2 RF Feedback resistor — — — MΩ RS Series resistor — — — kΩ — 0.6 — V Vpp_OSC32 Peak-to-peak amplitude of oscillation (oscillator mode) 3 1. Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator, loading capacitance. 2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator manufacturers' recommendation. Please check the crystal datasheet for the recommended values. And also consider the parasitic capacitance of package and board. 3. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. Table 43. External Oscillator electrical specifications (OSC) Symbol Description Min. Typ. Max. Unit VDD Supply voltage 2.7 — 5.5 V IDDOSC IDDOSC gmXOSC Supply current — low-gain mode (low-power mode) (HGO=0) Notes 1 4 MHz — 200 — µA 8 MHz — 300 — µA 16 MHz — 1.2 — mA 24 MHz — 1.6 — mA 32 MHz — 2 — mA 40 MHz — 2.6 — mA 32 kHz — 25 — µA 4 MHz — 1 — mA 8 MHz — 1.2 — mA 16 MHz — 3.5 — mA 24 MHz — 5 — mA 32 MHz — 5.5 — mA 40 MHz — 6 — mA Supply current — high-gain mode (HGO=1) 1 Fast external crystal oscillator transconductance Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 63 NXP Semiconductors Electrical characteristics Table 43. External Oscillator electrical specifications (OSC) (continued) Symbol Description Min. Typ. Max. Unit 32 kHz, Low Frequency Range, High Gain (32 kHz) 15 — 45 µA / V Medium Frequency Range (4-8 MHz) 2.2 — 9.7 mA / V High Frequency Range (8-40 MHz) 16 37 mA / V Notes VIH Input high voltage — EXTAL pin in external clock mode 1.75 — VDD V VIL Input low voltage — EXTAL pin in external clock mode VSS — 1.20 V C1 EXTAL load capacitance — — — 2 C2 XTAL load capacitance — — — 2 RF Feedback resistor RS Vpp 3 Low-frequency, high-gain mode (32 kHz) — 10 — MΩ Medium/high-frequency, low-gain mode (low-power mode) (4-8 MHz, 8-40 MHz) — — — MΩ Medium/high-frequency, high-gain mode (4-8 MHz, 8-40 MHz) — 1 — MΩ Low-frequency, high-gain mode (32 kHz) — 200 — kΩ Medium/high-frequency, low-gain mode (low-power mode) (4-8 MHz, 8-40 MHz) — 0 — kΩ Medium/high-frequency, high-gain mode (4-8 MHz, 8-40 MHz) — 0 — kΩ Series resistor Peak-to-peak amplitude of oscillation (oscillator mode) 4 Low-frequency, high-gain mode — 3.3 — V Medium/high-frequency, low-gain mode — 1.0 — V Medium/high-frequency, high-gain mode — 3.3 — V 1. Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator, loading capacitance. 2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator manufacturers' recommendation. Please check the crystal datasheet for the recommended values. And also consider the parasitic capacitance of package and board. 3. When low power mode is selected, RF is integrated and must not be attached externally. 4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 5.4.2.1.2 External Oscillator frequency specifications Table 44. External Oscillator frequency specifications (OSC32) Symbol Description fosc32_lo tdc_extal32 Min. Typ. Max. Unit Oscillator crystal or resonator frequency — lowfrequency mode 30 — 40 kHz Input clock duty cycle (external clock mode) 40 50 60 % Notes Table continues on the next page... 64 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics Table 44. External Oscillator frequency specifications (OSC32) (continued) Symbol Description fec_extal32 tcst32 Min. Typ. Max. Unit Input clock frequency (external clock mode) — — 40 kHz Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 2000 — ms Notes 1 1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve specifications. Table 45. External Oscillator frequency specifications (OSC) Symbol Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency — Low Frequency, High Gain Mode 32 — 40 kHz fosc_me Oscillator crystal or resonator frequency — Medium Frequency 4 — 8 MHz fosc_hi Oscillator crystal or resonator frequency — High Frequency 8 — 40 tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % fec_extal Input clock frequency (external clock mode) — — 50 MHz Crystal startup time — 32 kHz Low Frequency, High-Gain Mode — 500 — ms Crystal startup time — 8 MHz Medium Frequency, Low-Power Mode — 1.5 — Crystal startup time — 8 MHz Medium Frequency, High-Gain Mode — 2.5 — Crystal startup time — 40 MHz High Frequency, Low-Power Mode — 2 — Crystal startup time — 40 MHz High Frequency, High-Gain Mode — 2.5 — tcst Notes 1 1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve specifications. 5.4.2.2 5.4.2.2.1 System Clock Generation (SCG) specifications Fast internal RC Oscillator (FIRC) electrical specifications Table 46. Fast internal RC Oscillator electrical specifications Symbol Parameter Value Min. FFIRC Fast internal reference frequency — IVDD Supply current — Typ. 48 400 Unit Max. — MHz 500 µA Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 65 NXP Semiconductors Electrical characteristics Table 46. Fast internal RC Oscillator electrical specifications (continued) Symbol FUntrimmed ΔFOL Parameter Value IRC frequency (untrimmed) TJIT Min. Typ. Max. FIRC× (1-0.3) — FIRC× (1+0.3) MHz — ±0.5 ±1 %FFIRC — 3 µs2 35 150 ps Open loop total deviation of IRC frequency over voltage and temperature1 Regulator enable TStartup Unit Startup time Period jitter (RMS) — 1. The limit is respected across process, voltage and full temperature range. 2. Startup time is defined as the time between clock enablement and clock availability for system use. 5.4.2.2.2 Slow internal RC oscillator (SIRC) electrical specifications Table 47. Slow internal RC oscillator (SIRC) electrical specifications Symbol Parameter FSIRC Value Slow internal reference frequency Unit Min. Typ. Max. — 2 — MHz 8 IVDD FUntrimmed ΔFOL Supply current — 23 — µA IRC frequency (untrimmed) — — — MHz Regulator enable — — ±3 %FSIRC Startup time — 6 — µs2 Open loop total deviation of IRC frequency over voltage and temperature1 TStartup 1. The limit is respected across process, voltage and full temperature range. 2. Startup time is defined as the time between clock enablement and clock availability for system use. 5.4.2.2.3 Low Power Oscillator (LPO) electrical specifications Table 48. Low Power Oscillator (LPO) electrical specifications Symbol Parameter Min. Typ. Max. Unit 113 128 139 kHz FLPO Internal low power oscillator frequency ILPO Current consumption 1 3 7 µA Startup Time — — 20 µs Tstartup 5.4.2.2.4 LPFLL electrical specifications 66 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics Table 49. LPFLL electrical specifications Symbol Parameter Min. Typ. Max. Unit Iavg Power consumption 240 μA Tstart Start-up time 3.6 μs ΔFol Frequency accuracy over temperature and voltage in open loop after process trimmed –10 — 10 % ΔFcl Frequency accuracy in closed loop –1 1 — 11 % 1. ΔFcl is dependent on reference clock accuracy. For example, if locked to crystal oscillator, ΔFcl is typically limited by trimming ability of the module itself; if locked to other clock source which has 3% accuracy, then ΔFcl can only be ±3%. 5.4.3 Memories and memory interfaces 5.4.3.1 Flash memory module (FTFE) electrical specifications This section describes the electrical characteristics of the flash memory module (FTFE). 5.4.3.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 50. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm8 Program Phrase high-voltage time — 7.5 18 μs thversscr Erase Flash Sector high-voltage time Notes — 13 113 ms 1 thversblk32k Erase Flash Block high-voltage time for 32 KB — 26 226 ms 1 thversblk256k Erase Flash Block high-voltage time for 256 KB — 208 1808 ms 1 Notes 1. Maximum time based on expectations at cycling end-of-life. 5.4.3.1.2 Symbol Flash timing specifications — commands Table 51. Flash command timing specifications Description Min. Typ. Max. Unit Read 1s Block execution time trd1blk32k • 32 KB data flash — — 0.3 ms trd1blk256k • 256 KB program flash — — 1.8 ms Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 67 NXP Semiconductors Electrical characteristics Table 51. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes trd1sec2k Read 1s Section execution time (2 KB flash) — — 75 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs Erase Flash Block execution time 2 tersblk32k • 32 KB data flash — 28 240 ms tersblk256k • 256 KB program flash — 220 1850 ms Erase Flash Sector execution time — 15 115 ms tpgmsec512 Program Section execution time (512B flash) — 2.5 — ms — 2.2 ms tersscr 2 trd1all Read 1s All Blocks execution time — trdonce Read Once execution time — — 30 μs Program Once execution time — 90 — μs tersall Erase All Blocks execution time — 250 2100 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 250 2100 ms 2 tpgmonce 1 Program Partition for EEPROM execution time tpgmpart24k • 24 KB EEPROM backup — 69 — ms tpgmpart32k • 32 KB EEPROM backup — 70 — ms • Control Code 0xFF — 50 — μs tsetram24k • 24 KB EEPROM backup — 0.6 1.1 ms tsetram32k • 32 KB EEPROM backup — 0.8 1.2 ms Set FlexRAM Function execution time: tsetramff Byte-write to FlexRAM execution time: teewr8b24k • 24 KB EEPROM backup — 370 1625 μs teewr8b32k • 32 KB EEPROM backup — 385 1700 μs 16-bit write to FlexRAM execution time: teewr16b24k • 24 KB EEPROM backup — 370 1625 μs teewr16b32k • 32 KB EEPROM backup — 385 1700 μs — 360 1500 μs teewr32bers 32-bit write to erased FlexRAM location execution time 32-bit write to FlexRAM execution time: teewr32b24k • 24 KB EEPROM backup — 600 1950 μs teewr32b32k • 32 KB EEPROM backup — 630 2000 μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 68 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 5.4.3.1.3 Flash high voltage current behaviors Table 52. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 5.4.3.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 3.5 7.5 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 53. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles tnvmretd10k Data retention after up to 10 K cycles 5 50 — years tnvmretd1k Data retention after up to 1 K cycles 20 100 — years nnvmcycd Cycling endurance 10 K 50 K — cycles 2 Data Flash 2 FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance 5 50 — years tnvmretee10 Data retention up to 10% of write endurance 20 100 — years 20 K 50 K — cycles nnvmcycee Cycling endurance for EEPROM backup Write endurance 2 3 nnvmwree16 • EEPROM backup to FlexRAM ratio = 16 140 K 400 K — writes nnvmwree128 • EEPROM backup to FlexRAM ratio = 128 1.26 M 3.2 M — writes nnvmwree512 • EEPROM backup to FlexRAM ratio = 512 5M 12.8 M — writes nnvmwree1k • EEPROM backup to FlexRAM ratio = 1,024 10 M 25 M — writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C. 3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ 125 °C influenced by the cycling endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 69 NXP Semiconductors Electrical characteristics 5.4.4 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 5.4.5 Analog 5.4.5.1 5.4.5.1.1 ADC electrical specifications 12-bit ADC operating conditions Table 54. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 2.7 — 5.5 V ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 2.5 VDDA VDDA + 100m V 3 VREFL ADC reference voltage low − 100 0 100 mV 3 VADIN Input voltage VREFL — VREFH V — — 5 kΩ RS Source impedendance fADCK < 4 MHz Notes RSW1 Channel Selection Switch Impedance — 0.5 1.2 kΩ RAD Sampling Switch Impedance — 2 5 kΩ CP1 Pin Capacitance — 3 — pF CP2 Analog Bus Capacitance — — 5 pF CS Sampling capacitance — 4 5 pF fADCK ADC conversion clock frequency 2 40 50 MHz 4, 5 Crate ADC conversion rate 20 — 1200 Ksps 7 No ADC hardware averaging6 Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. Clock and compare cycle need to be set according the guidelines in the block guide. 70 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 5. ADC conversion will become less reliable above maximum frequency. 6. When using ADC hardware averaging, refer to the device Reference Manual to determine the most appropriate setting for AVGS. 7. Max ADC conversion rate of 1200 Ksps is with 10-bit mode Figure 19. ADC input impedance equivalency diagram 5.4.5.1.2 12-bit ADC electrical characteristics NOTE All the parameters in the table are given assuming system clock as the clocking source for ADC. NOTE For ADC signals adjacent to VDD/VSS or the XTAL pins some degradation in the ADC performance may be observed. NOTE All values guarantee the performance of the ADC for the multiple ADC input channel pins. When using the ADC to monitor the internal analogue parameters, please assume minor degradation. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 71 NXP Semiconductors Electrical characteristics Table 55. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Min. Typ.2 Max. 3 Unit Notes Supply current at 2.7 to 5.5 V 927 975 μA @ 5V 1023 μA 4 Sample Time 275 — Refer to the device's Reference Manual ns Symbol Description IDDA_ADC Conditions1 TUE Total unadjusted error at 2.7 to 5.5 V — ±4.5 ±6.11 LSB5 6 DNL Differential nonlinearity at 2.7 to 5.5 V — ±0.8 ±1.07 LSB5 6 INL Integral non-linearity at 2.7 to 5.5 V — ±1.4 ±3.54 LSB5 6 EFS Full-scale error at 2.7 to 5.5 V — –2 -3.60 LSB5 VADIN = VDDA6 EZS Zero-scale error at 2.7 to 5.5 V — –2.7 -4.24 LSB5 EQ Quantization error at 2.7 to 5.5 V — — ±0.5 LSB5 Effective number of bits at 2.7 to 5.5 V — 11.3 — bits 7 — 70 — dB SINAD = 6.02 × ENOB + 1.76 ENOB SINAD Signal-to-noise plus distortion at 2.7 to 5.5 V See ENOB EIL Input leakage error at 2.7 to 5.5 V VTEMP_S Temp sensor slope at 2.7 to 5.5 V VTEMP25 Temp sensor voltage at 25 °C 2.7 to 5.5 V 1. 2. 3. 4. 5. 6. 7. 8. 9. IIn × RAS Across the full temperature range of the device mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) 1.492 1.564 1.636 mV/°C 8, 9 730 740.5 751 mV 8, 9 All accuracy numbers assume the ADC is calibrated with VREFH = VDDA Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 48 MHz unless otherwise stated. These values are based on characterization but not covered by test limits in production. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 1 LSB = (VREFH - VREFL)/2N ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Input data is 100 Hz sine wave. ADC conversion clock < 40 MHz. ADC conversion clock < 3 MHz The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed application information of the temperature sensor. 72 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics 5.4.5.2 CMP with 8-bit DAC electrical specifications Table 56. Comparator with 8-bit DAC electrical specifications Symbol Description VDD Supply voltage IDDHS Supply current, High-speed Supply current, Low-speed Typ. 1 Max. Unit 2.7 — 5.5 V mode2 μA within ambient temperature range IDDLS Min. — 145 200 mode2 μA within ambient temperature range — 5 10 VAIN Analog input voltage 0 0 - VDDX VDDX VAIO Analog input offset voltage, High-speed mode -25 ±1 25 within ambient temperature range VAIO tDHSB Propagation delay, High-speed -40 Propagation delay, Low-speed Propagation delay, High-speed — 0.5 2 — 70 400 ns Initialization delay, High-speed mode Initialization delay, Low-speed µs — 1 5 μs — 1.5 3 mode3 μs — 10 30 — 0 — Analog comparator hysteresis, Hyst0 (VAIO) within ambient temperature range VHYST1 µs 3 within ambient temperature range VHYST0 200 Propagation delay, Low-speed mode4 within ambient temperature range tIDLS 30 mode4 within ambient temperature range tIDHS 40 ns — within ambient temperature range tDLSS ±4 mode3 within ambient temperature range tDHSS mV mode3 within ambient temperature range tDLSB mV Analog input offset voltage, Low-speed mode within ambient temperature range mV Analog comparator hysteresis, Hyst1, High-speed mode within ambient temperature range V mV — 16 53 — 11 30 Analog comparator hysteresis, Hyst1, Low-speed mode within ambient temperature range VHYST2 Analog comparator hysteresis, Hyst2, High-speed mode within ambient temperature range mV — 32 90 — 22 53 Analog comparator hysteresis, Hyst2, Low-speed mode within ambient temperature range Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 73 NXP Semiconductors Electrical characteristics Table 56. Comparator with 8-bit DAC electrical specifications (continued) Symbol Description VHYST3 Analog comparator hysteresis, Hyst3, High-speed mode within ambient temperature range Min. Typ. 1 Max. Unit mV — 48 133 within ambient temperature range — 33 80 8-bit DAC current adder (enabled) — 10 16 μA Analog comparator hysteresis, Hyst3, Low-speed mode IDAC8b 1. 2. 3. 4. 5. INL 8-bit DAC integral non-linearity –0.6 — 0.5 LSB5 DNL 8-bit DAC differential non-linearity –0.5 — 0.5 LSB Typical values assumed at VDDA = 5.0 V, Temp = 25 ℃, unless otherwise stated. Difference at input > 200mV Applied ± (100 mV + Hyst) around switch point Applied ± (30 mV + 2 × Hyst) around switch point 1 LSB = Vreference/256 Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 74 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Figure 22. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 0) Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 75 NXP Semiconductors Electrical characteristics Figure 23. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 1) 5.4.6 Communication interfaces 5.4.6.1 LPUART electrical specifications Refer to General AC specifications for LPUART specifications. 5.4.6.2 LPSPI electrical specifications The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins. Table 57. LPSPI master mode timing Num. Symbol Description Min. Max. Unit Note 1 fSPSCK Frequency of SPSCK fperiph/2048 fperiph/2 Hz 1 2 tSPSCK SPSCK period 2 x tperiph 2048 x tperiph ns 2 3 tLead Enable lead time 1/2 — tSPSCK — 4 tLag Enable lag time 1/2 — tSPSCK — Table continues on the next page... 76 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics Table 57. LPSPI master mode timing (continued) Num. Symbol Description 5 tWSPSCK Clock (SPSCK) high or low time 6 tSU 7 tHI 8 tv 9 10 11 Min. Max. Unit Note tperiph - 30 1024 x tperiph ns — Data setup time (inputs) 18 — ns — Data hold time (inputs) 0 — ns — Data valid (after SPSCK edge) — 15 ns — tHO Data hold time (outputs) 0 — ns — tRI Rise time input — tperiph - 25 ns — tFI Fall time input tRO Rise time output — 25 ns — tFO Fall time output 1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz. 2. tperiph = 1/fperiph NOTE High drive pin should be used for fast bit rate. SS1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 11 10 11 5 6 7 MSB IN2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) 4 5 SPSCK (CPOL=1) (OUTPUT) MISO (INPUT) 10 MSB OUT2 BIT 6 . . . 1 9 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 24. LPSPI master mode timing (CPHA = 0) Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 77 NXP Semiconductors Electrical characteristics SS1 (OUTPUT) 2 3 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 5 6 MISO (INPUT) 11 4 10 11 7 MSB IN2 BIT 6 . . . 1 LSB IN 9 8 MOSI (OUTPUT) 10 PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 PORT DATA MASTER LSB OUT 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 25. LPSPI master mode timing (CPHA = 1) Table 58. LPSPI slave mode timing Num. Symbol Description Min. Max. Unit Note 1 fSPSCK Frequency of SPSCK 0 fperiph/2 Hz 1 2 tSPSCK SPSCK period 2 x tperiph — ns 2 3 tLead 4 tLag Enable lead time 1 — tperiph — Enable lag time 1 — tperiph — 5 tWSPSCK tperiph - 30 — ns — 6 tSU Data setup time (inputs) 2.5 — ns — 7 tHI Data hold time (inputs) 3.5 — ns — 8 ta Slave access time — tperiph ns 3 9 tdis Slave MISO disable time — tperiph ns 4 10 tv Data valid (after SPSCK edge) — 31 ns — 11 tHO Data hold time (outputs) 0 — ns — 12 tRI Rise time input — tperiph - 25 ns — tFI Fall time input tRO Rise time output — 25 ns — tFO Fall time output 13 1. 2. 3. 4. Clock (SPSCK) high or low time fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz. tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state 38 78 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Electrical characteristics SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 MISO (OUTPUT) see note SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN Figure 26. LPSPI slave mode timing (CPHA = 0) SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note 8 MOSI (INPUT) SLAVE 13 12 13 11 10 MISO (OUTPUT) 12 MSB OUT 6 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN Figure 27. LPSPI slave mode timing (CPHA = 1) 5.4.6.3 Symbol fSCL LPI2C Table 59. LPI2C specifications Description SCL clock frequency Min. Max. Unit Notes Standard mode (Sm) 0 100 kHz 1, 2, 3 Fast mode (Fm) 0 400 Fast mode Plus (Fm+) 0 1000 Ultra Fast mode (UFm) 0 5000 High speed mode (Hs-mode) 0 3400 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 79 NXP Semiconductors Electrical characteristics 1. Hs-mode is only supported in slave mode. 2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum bus loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more information on the required pull-up devices, see I2C Bus Specification. 3. See the section "General switching specifications". 5.4.7 Human-machine interfaces (HMI) 5.4.7.1 Touch sensing input (TSI) electrical specifications Table 60. TSI electrical specifications Symbol Description Value Unit Min Typ Max IDD_EN Power consumption in operation mode — 500 600 µA IDD_DIS Power consumption in disable mode — 20 355 nA VBG Internal bandgap reference voltage — 1.21 — V VPRE Internal bias voltage — 1.51 — V CI Internal integration capacitance — 90 — pF FCLK Internal main clock frequency — 16 — MHz 5.4.8 Debug modules 5.4.8.1 Symbol VDDA S1 SWD electricals Table 61. SWD full voltage range electricals Description Min. Max. Unit Operating voltage 2.7 5.5 V 0 25 MHz SWD_CLK frequency of operation Table continues on the next page... 80 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Design considerations Table 61. SWD full voltage range electricals (continued) Symbol Description Min. Max. Unit S2 SWD_CLK cycle period 1/S1 — ns S3 SWD_CLK clock pulse width 15 — ns S4 SWD_CLK rise and fall times — 3 ns S9 SWD_DIO input data setup time to SWD_CLK rise 8 — ns S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 — ns S11 SWD_CLK high to SWD_DIO data valid — 25 ns S12 SWD_CLK high to SWD_DIO high-Z 5 — ns S2 S3 S3 SWD_CLK (input) S4 S4 Figure 28. Serial wire clock input timing SWD_CLK S9 SWD_DIO S10 Input data valid S11 SWD_DIO Output data valid S12 SWD_DIO S11 SWD_DIO Output data valid Figure 29. Serial wire data timing 6 Design considerations Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 81 NXP Semiconductors Design considerations 6.1 Hardware design considerations This device contains protective circuitry to guard against damage due to high static voltage or electric fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. 6.1.1 Printed circuit board recommendations • Place connectors or cables on one edge of the board and do not place digital circuits between connectors. • Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground. Consider to add ferrite bead or inductor to some sensitive lines. • Physically isolate analog circuits from digital circuits if possible. • Place input filter capacitors as close to the MCU as possible. • For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages. 6.1.2 Power delivery system Consider the following items in the power delivery system: • Use a plane for ground. • Use a plane for MCU VDD supply if possible. • Always route ground first, as a plane or continuous surface, and never as sequential segments. • Always route the power net as star topology, and make each power trace loop as minimum as possible. • Route power next, as a plane or traces that are parallel to ground traces. • Place bulk capacitance, 10 μF or more, at the entrance of the power plane. • Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL. • The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins. 82 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021  Design considerations  6.1.3 Analog design Each ADC input must have an RC filter as shown in the following figure. The maximum value of R must be RAS max if fast sampling and high resolution are   required. The value of C must be chosen to ensure that the RC time constant is very small compared to the sample period. MCU 5 Input signal 1 4 2 1 R ADCx 2 C MCU EXT Figure 30. RC circuit for ADC input  2 1  High voltage measurement circuits require voltage division, current limiting, and over-voltage protection as shown the following figure. divider formed by 1 The 2 voltage ADCx Analog input R1 – R4 must yield a voltage less than or equal to VREFH. The current must be R  limited to less than the injection current limit. External clamp Cdiodes can be added here to protect against transient over-voltages. D EXT 1 2 1 R2 R4 1 2 2 ADCx 2 C 2 R3 R5 2 1 MCU VDD 2 1 1 High voltage input R1 3 1 BAT54SW Figure 31. High voltage measurement with an ADC input MCU 2 SWD_DIO SWD_CLK RESET_b 1 RESET_b RESET_b 0.1uF 1 6.1.4 Digital design 2 4 6 8 10 2 0.1uF 1 3 5 7 9 HDR_5X2 2 1 C 2 1 1 VDD NOTE For more details of ADC related usage, refer to AN5250: VDD How to Increase the Analog-to-Digital Converter Accuracy 10k VDD in an Application. J1 10k 10k 2 Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V). 83 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors Supervisor Chip VDD MCU 2 1 2 EXTAL EXTAL XTAL 1 1 2 RS RF 2 RF 1 CRYSTAL The RESET_b1pinR5is a2pseudo open-drain I/O pin that has an internal pullup Cx 1 2 ADCx 2 C resistor. An external RC circuit is recommended to filter noise as shown in the CRYSTAL following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the BAT54SW 2 C recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to reject spurious noise. 1 1 2 3 R4 1 2 2  BAT54SW  VDD 1 2 2 NMI_b 1 10k RESET_b RESET_b Figure 32. Reset circuit RESET_b 0.1uF 1 2 When anSupervisor external supervisor chipVDD is connected toMCU the RESET_b pin, a series Chip 10k resistor must be used to avoid damaging the supervisor chip or the RESET_b pin, as shown in the following figure. The series resistor value (RS below) must be in 10k the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength. The 1 2 supervisor chip must have an active high, open-drain OUT RESET_b output. 2 RS 0.1uF Supervisor Chip  MCU VDD 1  1 Active high, open drain 2  10k    2 RS RESET_b 0.1uF 2 Active high, open drain  1 1 OUT 2  Figure 33. Reset signal connection to external reset chip 84  NXP Semiconductors  Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 2 10k SWD_DIO SWD_CLK 2 10k HDR_5X2  VDD 1 MCU 2 1 RESET_b 1 2 1 0.1uF 10k 1 2 4 6 8 10 VDD 1 J1 10k RESET_b RESET_b  HDR_5X2 10k SWD_DIO SWD_CLK 2  VDD 2 4 6 8 10 2 J1 MCU VDD 1 10k 1 3 5 7 9 MCU VDD 1  RS 2 CRYST 2 1 1 1 ADCx 3 1  2 2 OSCILLATOR 2 • RESET_b 1pin R5 XTAL 1 EXTAL CAUTION 1 2 MCU VDD Do not provide power to I/O pins prior to VDD, especially the RF MCU VDD RESET_b pin. R4 OSCILLAT OSCILLATOR 1 Design considerations 2 2 C C 1 R R 2 ADCx 1 1 2 1 3 5 7 9 Analog Analog inputinput OSCILLATOR • NMI pin 2 RF XTAL 1 1 1 MCU EXTAL XTAL 2 RF EXTAL 1 RS 2 RF RS RS 2 RESONATOR 2 2 2 1 3 1 2 2 Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low 1 2 2 1 level on this pin will trigger non-maskable interrupt.1 When this pin is enabled as CRYSTAL CRYSTAL the NMI function, an external pull-up resistor Cx (10 kΩ) as shown Cy in the following figure is recommended for robustness. DCx If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is required to disable the NMI function by remapping to another function. The NMI function is disabled by programming the FOPT[NMI_DIS] bit to zero. MCU MCU VDD 1 1 VDD NMI_b 1 RESET_b 2 10k 2 10k 2 0.1uF • Debug interface 1 1 0.1uF 2 RS 2 10k 2 Figure 34. NMI pin biasing This MCU MCU uses the standard ARM SWD interface protocol as shown in the following figure. While pull-up or pull-down resistors are not required (SWD_DIO has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ pull resistors are recommended for system robustness. The RESET_b RESET_b pin recommendations mentioned above must also be considered. VDD Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 XTAL Design considerations 1 EXTAL OSCILLATOR 1 OSCILLATOR 85 NXP Semiconductors 1 2 C 2 2 2 1 1 R4 R3 BAT54SW Design considerations VDD 1 1 1 10k 2 SWD_DIO SWD_CLK RESET_b RESET_b RESET_b 0.1uF 1 2 0.1uF 2 4 6 8 10 1 1 3 5 7 9 C J1 2 10k VDD MCU VDD 2 HDR_5X2 2 10k Supervisor Chip MCU VDD 1 • Unused pin Figure 35. SWD debug interface RESET_b 1 2 Unused GPIO pins must be left floating (no electrical connections) with the MUX 10k field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables1the digital 2 OUT input path to the MCU. RS Active high, 0.1uF 2 open drain 6.1.5 Crystal oscillator B When using an external crystal or ceramic resonator as the frequency reference for the MCU clock system, refer to the following table and diagrams. The feedback resistor, RF, is incorporated internally with the low power oscillators. An external feedback is required when using high gain (HGO=1) mode. The series resistor, RS, is required in high gain (HGO=1) mode when the crystal or resonator frequency is below 2 MHz. Otherwise, the low power oscillator (HGO=0) must not have any series resistance; and the high frequency, high gain oscillator with a 4 3 frequency above 2 MHz does not require any series resistance. OSC32 EXTAL32 XTAL32 2 1 1 CRYSTAL 1 2 Figure 36. RTC Oscillator (OSC32) module connection – Diagram 1 2 1 1 Cx Cy CRYSTAL Cx 2 86 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 5 1 2 RF 1 1 NXP Semiconductors Cy 2 RF RS 4 1 A RS 1 Design considerations Table 62. External crystal/resonator connections Oscillator mode Low frequency (32.768 kHz), high gain Diagram 3 High frequency (1-32 MHz), low power Diagram 2 High frequency (1-32 MHz), high gain 3 Diagram 3 3 Cx 2 CRYSTAL 2 1 1 CRYSTAL RESONATOR 2 2 RS 1 3 2 Cy RESONATOR Figure 38. Crystal connection – Diagram 3 1 1 RF 2 MCU VDD 10k 3 2 2 MCU 1 RS CRYSTAL Cx Cy 2 1 1 1 2 2 RF 2 CRYSTAL XTAL RS 2 Cx 2 1 1 1 1 CRYSTAL RS 1 RF EXTAL XTAL 2 RF 2 1 1 1 OSCILLATOR 2 RS 2 2 XTAL 1 EXTAL 2 RS 1 RESONATOR 1 RF EXTAL 2 XTAL 3 RESONATOR 2 RF XTAL OSCILLATOR 1 2 1 EXTAL EXTAL XTAL 1 Cy Cy 2 OSCILLATOR 3 Figure 37. Crystal connection – Diagram 2 OSCILLATOR OSCILLATOR OSCILLATOR EXTAL 1 XTAL XTAL 2 2 Cx 1 CRYSTAL 2 CRYSTAL 21 1 EXTAL EXTAL 2 2 CRYSTAL XTAL XTAL EXTAL 1 1 2 EXTAL OSCILLATOR 1 XTAL OSCILLATOR OSCILLATOR 1 XTAL EXTAL 1 OSCILLATOR OSCILLATOR 1 EXTAL 2 1 OSCILLATOR 10k NOTE For PCB layout, the user could consider to add the guard ring to the crystal oscillator circuit. 2 2 2 2 4 DD 1 RESET_b 2 0.1uF NMI_b MCU 1 VDD 6.2 10kSoftware considerations MCU NMI_b All Kinetis MCUs are supported by comprehensive NXP and third-party hardware and software enablement solutions, which can reduce development costs and time to RESET_b market. Featured software and tools are listed below. Visit http://www.nxp.com/ kinetis/sw for more information and supporting collateral. 1 2 DD 2 10k 1 2 Oscillator mode 0.1uF Evaluation and Prototyping Hardware • Freedom Development Platform: http://www.nxp.com/freedom Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 87 NXP Semiconductors Part identification IDEs for Kinetis MCUs • Kinetis Design Studio IDE: http://www.nxp.com/kds • Partner IDEs: http://www.nxp.com/kide Run-time Software • Kinetis SDK: http://www.nxp.com/ksdk • Kinetis Bootloader: http://www.nxp.com/kboot • ARM mbed Development Platform: http://www.nxp.com/mbed For all other partner-developed software and tools, visit http://www.nxp.com/partners. 7 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KE## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Table 63. Part number fields description Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification KE## Kinetis family • KE15, KE14 A Key attribute • Z = Cortex-M0+ Table continues on the next page... 88 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 Revision history Table 63. Part number fields description (continued) Field Description Values FFF Program flash memory size • 128 = 128 KB • 256 = 256 KB R Silicon revision • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 PP Package identifier • LH = 64 LQFP (10 mm x 10 mm) • LL = 100 LQFP (14 mm x 14 mm) CC Maximum CPU frequency (MHz) • 7 = 72 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 7.4 Example This is an example part number: MKE15Z256VLL7 8 Revision history The following table provides a revision history for this document. Table 64. Revision history Rev. No. Date 2 09/2016 Substantial Changes Initial public release. (public release) 2.1 10/2016 • Updated the max value of "Frequency of operation", in the "LPSPI slave mode timing" table. • Minor correction: VDDE symbol should be VDD, in the "DC electrical specifications" table. • Minor update in the "Clocking block diagram" figure. • Minor update in the "Analog design" section. 06/2017 • Updated the "Voltage and current operating ratings" section. • Minor update in the "Pinout decoupling" figure. • Fixed the "Description" collumn of STOP and VLPS mode rows, in the "Power consumption operating behaviors" table. 08/2017 • Minor update in the "Clock interfaces" section of the feature list, on the front matter cover pages. (internal version) 2.2 (internal version) 2.3 (internal version) Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 89 NXP Semiconductors Revision history Table 64. Revision history (continued) Rev. No. Date Substantial Changes • Some updates in the "External Oscillator electrical specifications (OSC32)" and "External Oscillator electrical specifications (OSC)" tables. • Some updates in the "External Oscillator frequency specifications (OSC32)" and "External Oscillator frequency specifications (OSC)" tables. 3 07/2018 • Updated the figure "Memory map". • Minor updates in the figures "Oscillator connections scheme (OSC32)" and "Oscillator connections scheme (OSC)". • Some updates of VIH and VIL in the "External Oscillator electrical specifications (OSC32)" and "External Oscillator electrical specifications (OSC)" tables, and minor editorial fix. • Updated the table "Fast internal RC Oscillator electrical specifications": FIRC is trimmed to 48 MHz only, in this device. • Updated the figure "ADC input impedance equivalency diagram". • Corrected the unit as uA, in the IDDA_ADC row of the table "12-bit ADC characteristics". • Footnote updated in the tables "LPSPI master mode timing" and "LPSPI slave mode timing". • Corrected the minimum and the maximum values of VLVRX in the "VDD supply LVR, LVD and POR operating requirements" table. • Updated the "Voltage and current operating requirements" table. 06/2019 • Corrected the "Clock interfaces" section in the cover page: FIRC is trimmed to 48 MHz only in this device. Up to 50 MHz DC external square wave input clock. • Minor fix in Figure 4. • Note added after Table 5. • Statement restored in the section RTC : The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator, or clock directly from RTC_CLKIN pin. • Minor fix in Table 23. • Some major updates in Table 54. • Some minor updates in tables "LPSPI master mode timing" and "LPSPI slave mode timing", including the footnotes, in the section LPSPI electrical specifications. 07/2020 • Minor correction in the FTM channel numbers of the "Module Signal Description Tables" section. • Minor correction in the "Functional block diagram" figure after the cover page: GPIO and TSI blocks. • Minor correction in the "Ordering information" table: ADC channels collumn. 03/2021 • Added errata for Mask 2N36S, in the "Related Resources" table of cover page. (public release) 4 (public release) 4.1 (internal version) 4.2 (public release) 90 NXP Semiconductors Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 How To Reach Us Home Page: nxp.com Web Support: nxp.com/support Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 03/ 2021 Document identifier: KE1xZP100M72SF0