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MKL03Z8VFK4

MKL03Z8VFK4

  • 厂商:

    NXP(恩智浦)

  • 封装:

    UFQFN24

  • 描述:

    IC MCU 32BIT 8KB FLASH 24QFN

  • 数据手册
  • 价格&库存
MKL03Z8VFK4 数据手册
NXP Semiconductors Data Sheet: Technical Data Document Number: KL03P24M48SF0 Rev. 5.1 08/2017 Kinetis KL03 32 KB Flash 48 MHz Cortex-M0+ Based Microcontroller Supports ultra low power 48 MHz devices with up to 32 KB Flash. World's smallest MCU based on ARM® technology. Ideal solution for Internet of Things edge nodes design with ultra small form factor and ultra low power consumption. The products offers: • Tiny footprint packages, including 1.6 x 2.0 mm2 WLCSP • Run power consumption as low as 50 µA/MHz • Static power consumption as low as 2.2 µA with 7.5 µs wakeup time for full retention and lowest static mode down to 77 nA in deep sleep • Highly integrated peripherals, including new boot ROM and high accurate internal voltage reference, etc Core • ARM® Cortex®-M0+ core up to 48 MHz Memories • Up to 32 KB program flash memory • 2 KB SRAM • 8 KB ROM with build-in bootloader • 16 bytes regfile System peripherals • Nine low-power modes to provide power optimization based on application requirements • COP Software watchdog • Low-leakage wakeup unit • SWD debug interface and Micro Trace Buffer • Bit Manipulation Engine Clocks • 48 MHz high accuracy internal reference clock • 8/2 MHz low power internal reference clock • 32 kHz to 40 kHz crystal oscillator • 1 kHz LPO clock Operating Characteristics • Voltage range: 1.71 to 3.6 V • Flash write voltage range: 1.71 to 3.6 V MKL03ZxxVFG4 MKL03ZxxVFK4 MKL03Z32CAF4R MKL03Z32CBF4R 16-pin QFN (FG) 3 x 3 x 0.65 Pitch 0.5 mm 24-pin QFN (FK) 4 x 4 x 0.65 Pitch 0.5 mm 20 WLCSP 2 x 1.61 x 0.56 Pitch 0.4 mm(AF) 2 x 1.61 x 0.32 Pitch 0.4 mm (BF) • Temperature range (ambient): -40 to 105°C for QFN packages; -40 to 85°C for WLCSP packages Human-machine interface • General-purpose input/output up to 22 Communication interfaces • One 8-bit SPI module • One LPUART module • One I2C module supporting up to 1 Mbit/s, with double buffer Analog Modules • 12-bit SAR ADC with internal voltage reference, up to 818 ksps and 7 channels • High-speed analog comparator containing a 6-bit DAC and programmable reference input • 1.2 V voltage reference (Vref) Timers • Two 2-channel Timer/PWM modules • One low-power timer • Real time clock Security and integrity modules • 80-bit unique identification number per chip NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Ordering Information1 Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL03Z8VFG4(R) 8 2 14 MKL03Z16VFG4(R) 16 2 14 MKL03Z32VFG4(R) 32 2 14 MKL03Z32CAF4R 32 2 18 MKL03Z32CBF4R 32 2 18 MKL03Z8VFK4(R) 8 2 22 MKL03Z16VFK4(R) 16 2 22 MKL03Z32VFK4(R) 32 2 22 1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. Related Resources Type Description Resource Selector Guide The Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to KL03PB1 enable quick evaluation of a device for design suitability. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL03P24M48SF0RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. KL03P24M48SF01 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KL03Z_xN86K2 Package drawing Package dimensions are provided in package drawings. QFN 16-pin: 98ASA00525D1 QFN 24-pin: 98ASA00602D1 WLCSP 20-pin: 98ASA00676D1 WLCSP 20-pin (ultra thin): 98ASA00964D1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the “x” replaced by the revision of the device you are using. Figure 1 shows the functional modules in the chip. 2 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 Kinetis KL03 Family ARM Cortex-M0+ Core System Internal watchdog SWD interfaces BME Interrupt controller Memories and Memory Interfaces Program flash RAM ROM Clocks Low frequency oscillator Internal reference clocks LPO MTB Register file Security Analog Timers Unique ID 12-bit ADC x1 Timers 2x2ch and Integrity Analog comparator with 6-bit DAC x1 Low Power Timer Communication Interfaces 2 I C x1 Human-Machine Interface (HMI) GPIOs with interrupt Low power UART x1 RTC VREF SPI x1 Figure 1. Functional block diagram Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 3 NXP Semiconductors Table of Contents 1 Ratings.................................................................................... 5 1.1 Thermal handling ratings................................................. 5 1.2 Moisture handling ratings................................................ 5 1.3 ESD handling ratings....................................................... 5 1.4 Voltage and current operating ratings............................. 6 2 General................................................................................... 6 2.1 AC electrical characteristics.............................................6 2.2 Nonswitching electrical specifications..............................7 2.2.1 Voltage and current operating requirements....... 7 2.2.2 LVD and POR operating requirements................7 2.2.3 Voltage and current operating behaviors.............8 2.2.4 Power mode transition operating behaviors........ 9 2.2.5 2.2.6 2.2.7 Power consumption operating behaviors............ 10 EMC radiated emissions operating behaviors..... 24 EMC Radiated Emissions Web Search Procedure boilerplate.......................................... 25 2.2.8 Capacitance attributes.........................................25 2.3 Switching specifications...................................................25 2.3.1 Device clock specifications..................................25 2.3.2 General switching specifications......................... 26 2.4 Thermal specifications..................................................... 26 2.4.1 Thermal operating requirements......................... 26 2.4.2 Thermal attributes................................................27 3 Peripheral operating requirements and behaviors.................. 27 3.1 Core modules.................................................................. 27 3.1.1 SWD electricals .................................................. 28 3.2 System modules.............................................................. 29 3.3 Clock modules................................................................. 29 3.3.1 MCG-Lite specifications.......................................29 3.3.2 Oscillator electrical specifications........................30 3.4 Memories and memory interfaces................................... 31 3.4.1 Flash electrical specifications.............................. 31 3.5 Security and integrity modules........................................ 33 4 NXP Semiconductors 4 5 6 7 8 9 3.6 Analog............................................................................. 33 3.6.1 ADC electrical specifications............................... 33 3.6.2 CMP and 6-bit DAC electrical specifications....... 37 3.6.3 Voltage reference electrical specifications.......... 39 3.7 Timers..............................................................................40 3.8 Communication interfaces............................................... 40 3.8.1 SPI switching specifications................................ 41 3.8.2 Inter-Integrated Circuit Interface (I2C) timing...... 45 3.8.3 UART...................................................................47 Dimensions............................................................................. 47 4.1 Obtaining package dimensions....................................... 47 Pinout...................................................................................... 48 5.1 KL03 signal multiplexing and pin assignments................ 48 5.2 KL03 pinouts....................................................................49 Ordering parts......................................................................... 51 6.1 Determining valid orderable parts....................................51 Part identification.....................................................................51 7.1 Description.......................................................................51 7.2 Format............................................................................. 52 7.3 Fields............................................................................... 52 7.4 Example...........................................................................52 Terminology and guidelines.................................................... 53 8.1 Definition: Operating requirement....................................53 8.2 Definition: Operating behavior......................................... 53 8.3 Definition: Attribute.......................................................... 54 8.4 Definition: Rating............................................................. 54 8.5 Result of exceeding a rating............................................ 55 8.6 Relationship between ratings and operating requirements....................................................................55 8.7 Guidelines for ratings and operating requirements..........55 8.8 Definition: Typical value...................................................56 8.9 Typical value conditions.................................................. 57 Revision history.......................................................................57 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2. QFN packages moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Table 3. WLCSP packages moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 1 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 4. ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model –500 +500 V 2 Latch-up current at ambient temperature of 105 °C –100 +100 mA 3 ILAT Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 5 NXP Semiconductors General 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 1.4 Voltage and current operating ratings Table 5. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA VIO IO pin input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDD – 0.3 VDD + 0.3 V ID VDDA Analog supply voltage 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal Low High 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. • CL=30 pF loads 6 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General • Slew rate disabled • Normal drive strength 2.2 Nonswitching electrical specifications 2.2.1 Voltage and current operating requirements Table 6. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage Notes 1.71 3.6 V — VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V — VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V — VIH VIL Input high voltage • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V Input low voltage — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V 0.06 × VDD — V –5 — mA Input hysteresis IICIO IO pin negative DC injection current—single pin • VIN < VSS–0.3V Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins • Negative current injection VRAM — • 2.7 V ≤ VDD ≤ 3.6 V VHYS IICcont — VDD voltage required to retain RAM — 1 — –25 — mA 1.2 — V — 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 7 NXP Semiconductors General 2.2.2 LVD and POR operating requirements Table 7. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit Notes VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V — VLVDH Falling low-voltage detect threshold — high range (LVDV = 01) 2.48 2.56 2.64 V — Low-voltage warning thresholds — high range VLVW1H • Level 1 falling (LVWV = 00) VLVW2H • Level 2 falling (LVWV = 01) VLVW3H • Level 3 falling (LVWV = 10) VLVW4H • Level 4 falling (LVWV = 11) VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1 2.62 2.70 2.78 V 2.72 2.80 2.88 V 2.82 2.90 2.98 V 2.92 3.00 3.08 V — ±60 — mV — 1.54 1.60 1.66 V — Low-voltage warning thresholds — low range VLVW1L • Level 1 falling (LVWV = 00) VLVW2L • Level 2 falling (LVWV = 01) VLVW3L • Level 3 falling (LVWV = 10) VLVW4L • Level 4 falling (LVWV = 11) VHYSL Low-voltage inhibit reset/recover hysteresis — low range 1 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.16 V — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 8. Voltage and current operating behaviors Symbol VOH Description Min. Unit Output high voltage — Normal drive pad (except RESET) • 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA VOH Max. Notes 1, 2 VDD – 0.5 — V VDD – 0.5 — V Output high voltage — High drive pad (except RESET) 1, 2 VDD – 0.5 — V VDD – 0.5 — V Table continues on the next page... 8 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General Table 8. Voltage and current operating behaviors (continued) Symbol Description Min. Max. Unit Notes — 100 mA — • 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA IOHT Output high current total for all ports VOL Output low voltage — Normal drive pad VOL IOLT 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — 0.5 V Output low voltage — High drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — 0.5 V Output low current total for all ports — 100 mA — IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 41 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA — RPU Internal pullup resistors 20 50 kΩ 4 1. I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • HIRC clock mode VLLSx→RUN recovery uses LIRC clock mode at the default CPU and system frequency of 8 MHz, and a bus and flash clock frequency of 4 MHz. Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 9 NXP Semiconductors General Table 9. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit Note — — 300 μs 1 — • VLLS0 → RUN — 152 166 μs — • VLLS1 → RUN — 152 166 μs — • VLLS3 → RUN — 93 104 μs — • VLPS → RUN — 7.5 8 μs — • STOP → RUN — 7.5 8 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors Table 10. KL03 QFN packages power consumption operating behaviors Symbol IDDA Description Analog supply current IDD_RUNCO Running CoreMark in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUNCO Running While(1) loop in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Min. Typ. Max.1 Unit Notes — — See note mA 2 3 — 5.49 5.71 — 5.62 5.84 mA 3 — 5.16 5.37 — 5.27 5.48 mA 3 — 6.03 6.27 — 6.16 6.41 Run mode current—48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V mA 3 Table continues on the next page... 10 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General Table 10. KL03 QFN packages power consumption operating behaviors (continued) Symbol IDD_RUN Min. Typ. Max.1 Unit • at 25 °C — 3.71 3.86 mA • at 105 °C — 3.81 3.96 Description Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 12 MHz core/6 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in flash all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V Notes 3 — 2.47 2.57 — 2.58 2.68 mA 3 — 6.43 6.69 — 6.56 6.82 mA — — 5.71 5.94 — 5.82 6.05 mA — — 3.3 3.43 — 3.4 3.54 mA — — 2.28 2.37 — 2.38 2.48 mA — — 6.1 6.34 — 6.22 6.47 mA — — 3.14 3.23 — 3.27 3.36 mA — — 3.54 3.63 — 3.67 3.76 mA Table continues on the next page... Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 11 NXP Semiconductors General Table 10. KL03 QFN packages power consumption operating behaviors (continued) Symbol Description Min. Typ. Max.1 Unit Notes • at 25 °C • at 105 °C IDD_VLPRCO Very-low-power run While(1) loop in flash in compute operation mode— 2 MHz LIRC mode, 2 MHz core/0.5 MHz flash, VDD = 3.0 V • at 25 °C IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in compute operation mode— 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C IDD_VLPRCO Very-low-power run While(1) loop in SRAM in compute operation mode:—2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C IDD_VLPR IDD_VLPR IDD_VLPR IDD_VLPR IDD_VLPR IDD_VLPR IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V — — 500 750 μA — — 188 217 μA — — 82 123 μA — — 503 754 μA — — 60 90 μA — — 516 774 μA — — 209 350 μA — — 229 370 μA — — 93 140 μA — — 31 81 μA Table continues on the next page... 12 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General Table 10. KL03 QFN packages power consumption operating behaviors (continued) Symbol Description Min. Typ. Max.1 Unit Notes • at 25 °C IDD_VLPR IDD_WAIT IDD_WAIT Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C Wait mode current—core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V Wait mode current—core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V — — 103 154 μA — — 1.4 1.94 mA — — 1.02 1.24 mA IDD_VLPW Very-low-power wait mode current, core disabled, 4 MHz system/ 1 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 121 181 μA — IDD_VLPW Very-low-power wait mode current, core disabled, 2 MHz system/ 0.5 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 59 97 μA — IDD_VLPW Very-low-power wait mode current, core disabled, 125 kHz system/ 31.25 kHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 28 42 μA — IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12 MHz bus and flash, VDD = 3.0 V — — 1.53 2.03 mA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, flash doze enabled, 12 MHz bus, VDD = 3.0 V — — IDD_STOP Stop mode current at 3.0 V • at 25 °C and below • at 85 °C • at 105 °C Very-low-power stop mode current at 3.0 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C IDD_VLPS Very-low-power stop mode current at 1.8 V • at 25 °C and below • at 50 °C 1.18 mA — • at 50 °C IDD_VLPS 0.881 — 158 175.7 — 164 179.48 — 187 199.54 — 219 236.43 μA — — 2.2 2.71 — 3.9 6.63 — 13.9 18.25 — 28.4 36.59 μA — — 2.2 2.674 — 3.8 6.44 Table continues on the next page... Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 13 NXP Semiconductors General Table 10. KL03 QFN packages power consumption operating behaviors (continued) Symbol Min. Typ. Max.1 Unit • at 85 °C — 13.2 17.37 μA • at 105 °C — 27.8 35.54 Description IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 1.8 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V • at 25 °C and below • at 50°C • at 85°C • at 105 °C IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V • at 25 °C and below • at 50°C • at 85°C • at 105 °C IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V • at 25 °C and below • at 50°C • at 85°C • at 105 °C Notes — — 1.08 1.17 — 1.4 1.52 — 3.45 3.96 — 7.02 8.19 μA — — 1.47 1.56 — 1.82 1.94 — 3.93 4.44 — 7.6 8.77 μA — — 1.33 1.42 — 1.65 1.77 — 3.56 4.07 — 6.92 8.09 μA — — 566 690 — 788 839 — 2270 2600 — 4980 5820 nA — — 969 1059 — 1200 1251 — 2740 3070 — 5610 6450 nA — — 826 916 — 1040 1091 — 2400 2730 — 4910 5750 nA Table continues on the next page... 14 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General Table 10. KL03 QFN packages power consumption operating behaviors (continued) Symbol Description Min. IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 1) at 3 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C Typ. Max.1 Unit Notes — — 265 373 — 467 512.9 — 1920 2256 — 4540 5395 nA 4 — 77 350 — 255 465.70 — 1640 1994 — 4080 4956 nA 1. The maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). 2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 3. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high, optimized for balanced. 4. No brownout Table 11. KL03 WLCSP package power consumption operating behaviors Symbol IDDA Description Analog supply current IDD_RUNCO Running CoreMark in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V • at 25 °C • at 85 °C IDD_RUNCO Running While(1) loop in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V • at 25 °C • at 85 °C IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 85 °C Min. Typ. Max.1 Unit Notes — — See note mA 2 3 — 5.49 5.71 — 5.59 5.81 mA 3 — 5.16 5.37 — 5.24 5.45 mA 3 — 6.03 6.27 — 6.13 6.38 mA Table continues on the next page... Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 15 NXP Semiconductors General Table 11. KL03 WLCSP package power consumption operating behaviors (continued) Symbol Description Min. IDD_RUN Run mode current—48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V • at 25 °C • at 85 °C IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 12 MHz core/6 MHz flash, VDD = 3.0 V • at 25 °C • at 85 °C IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 85 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in flash all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C Typ. Max.1 Unit Notes 3 — 3.71 3.86 — 3.78 3.93 mA 3 — 2.47 2.57 — 2.55 2.65 mA 3 — 6.43 6.69 — 6.53 6.79 mA — — 5.71 5.94 — 5.79 6.02 mA • at 85 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V • at 25 °C — — 3.3 3.43 — 3.37 3.50 mA • at 85 °C IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V • at 25 °C • at 85 °C IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C — — 2.28 2.37 — 2.35 2.44 mA — — 6.1 6.34 — 6.19 6.44 mA • at 85 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V — — 3.14 3.23 — 3.24 3.33 mA Table continues on the next page... 16 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General Table 11. KL03 WLCSP package power consumption operating behaviors (continued) Symbol Description Min. Typ. Max.1 Unit Notes • at 25 °C • at 85 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C — — 3.54 3.63 — 3.64 3.73 mA • at 85 °C IDD_VLPRCO Very-low-power run While(1) loop in flash in compute operation mode— 2 MHz LIRC mode, 2 MHz core/0.5 MHz flash, VDD = 3.0 V • at 25 °C IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in compute operation mode— 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C IDD_VLPRCO Very-low-power run While(1) loop in SRAM in compute operation mode:—2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C IDD_VLPR IDD_VLPR IDD_VLPR IDD_VLPR IDD_VLPR IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C — — 500 750 μA — — 188 217 μA — — 82 123 μA — — 503 754 μA — — 60 90 μA — — 516 774 μA — — 209 350 μA — — 229 Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM in all 370 μA — Table continues on the next page... Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 17 NXP Semiconductors General Table 11. KL03 WLCSP package power consumption operating behaviors (continued) Symbol Description peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C IDD_VLPR IDD_VLPR IDD_WAIT IDD_WAIT Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C Wait mode current—core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V Wait mode current—core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V Min. Typ. Max.1 Unit — 93 140 μA Notes — — 31 81 μA — — 103 154 μA — — 1.4 1.94 mA — — 1.02 1.24 mA IDD_VLPW Very-low-power wait mode current, core disabled, 4 MHz system/ 1 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 121 181 μA — IDD_VLPW Very-low-power wait mode current, core disabled, 2 MHz system/ 0.5 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 59 97 μA — IDD_VLPW Very-low-power wait mode current, core disabled, 125 kHz system/ 31.25 kHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 28 42 μA — IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12 MHz bus and flash, VDD = 3.0 V — — 1.53 2.03 mA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, flash doze enabled, 12 MHz bus, VDD = 3.0 V — — IDD_STOP Stop mode current at 3.0 V • at 25 °C and below 1.18 mA — • at 50 °C • at 85 °C IDD_VLPS 0.881 Very-low-power stop mode current at 3.0 V • at 25 °C and below — 158 175.7 — 164 179.48 — 187 199.54 μA — — 2.2 2.71 — 3.9 6.63 Table continues on the next page... 18 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General Table 11. KL03 WLCSP package power consumption operating behaviors (continued) Symbol Description • at 50 °C Min. Typ. Max.1 Unit — 13.9 18.25 μA Notes • at 85 °C IDD_VLPS Very-low-power stop mode current at 1.8 V • at 25 °C and below • at 50 °C • at 85 °C IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V • at 25 °C and below — — 2.2 2.674 — 3.8 6.44 — 13.2 17.37 — μA — 1.08 1.17 • at 50 °C — 1.4 1.52 • at 85 °C — 3.45 3.96 IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V • at 25 °C and below • at 50 °C • at 85 °C IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 1.8 V • at 25 °C and below • at 50 °C • at 85 °C IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V • at 25 °C and below • at 50°C • at 85°C IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V • at 25 °C and below • at 50°C • at 85°C IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V • at 25 °C and below • at 50°C • at 85°C IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V μA — — 1.47 1.56 — 1.82 1.94 — 3.93 4.44 μA — — 1.33 1.42 — 1.65 1.77 — 3.56 4.07 μA — — 566 690 — 788 839 — 2270 2600 nA — — 969 1059 — 1200 1251 — 2740 3070 nA — — 826 916 — 1040 1091 — 2400 2730 nA — — 265 373 Table continues on the next page... Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 19 NXP Semiconductors General Table 11. KL03 WLCSP package power consumption operating behaviors (continued) Symbol Min. Typ. Max.1 • at 25 °C and below — 467 512.9 • at 50 °C — 1920 2256 Description Unit Notes nA • at 85 °C IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 1) at 3 V • at 25 °C and below • at 50 °C • at 85 °C 4 — 77 350 — 255 465.70 — 1640 1994 nA 1. The maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). 2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 3. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high, optimized for balanced. 4. No brownout Table 12. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 1051 ILIRC8MHz 8 MHz internal reference clock (LIRC) adder. Measured by entering STOP or VLPS mode with 8 MHz LIRC enabled, MCG_SC[FCRDIV]=000b, MCG_MC[LIRC_DIV2]=000b. 68 68 68 68 68 68 µA ILIRC2MHz 2 MHz internal reference clock (LIRC) adder. Measured by entering STOP mode with the 2 MHz LIRC enabled, MCG_SC[FCRDIV]=000b, MCG_MC[LIRC_DIV2]=000b. 27 27 27 27 27 27 µA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. • VLLS1 • VLLS3 • VLPS • STOP 340 410 460 470 480 600 340 410 460 490 530 600 340 420 480 570 610 850 340 420 480 570 610 850 30 30 30 85 100 200 ILPTMR LPTMR peripheral adder measured by placing the device in VLLS1 mode with LPTMR enabled using LPO. nA nA Table continues on the next page... 20 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General Table 12. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 1051 ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 15 15 15 15 15 15 µA IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 340 440 440 480 520 620 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. • LIRC8M (8 MHz internal reference clock) • LIRC2M (2 MHz internal reference clock) 85 85 85 85 85 85 µA 28 28 28 28 28 28 ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. • LIRC8M (8 MHz internal reference clock) • LIRC2M (2 MHz internal reference clock) µA 93 93 93 93 93 93 35 35 35 35 35 35 IBG Bandgap adder when BGEN bit is set and device is placed in VLPx or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 340 340 340 340 340 340 µA 1. For QFN packages only. Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 21 NXP Semiconductors General 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • • • • MCG-Lite in HIRC for run mode, and LIRC for VLPR mode No GPIOs toggled Code execution from flash For the ALLOFF curve, all peripheral clocks are disabled except FTFA Run Mode Current vs Core Frequency Temperature=25, VDD=3, MCG Mode=HIRC, while loop located in Flash 7.00E-03 6.00E-03 Current Consumption on VDD (A) 5.00E-03 All Peripheral CLK Gates 4.00E-03 ALLOFF ALLON 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 '1-1 '1-1 '1-1 1-1 '1-2 3 6 8 12 24 48 CLK Ratio Flash - Core Core Freq (MHz) Figure 3. Run mode supply current vs. core frequency (loop located in flash) 22 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General Run Mode Current vs Core Frequency Temperature=25, VDD=3, MCG Mode=HIRC, while loop located in SRAM 4.00E-03 3.50E-03 Current Consumption on VDD (A) 3.00E-03 2.50E-03 All Peripheral CLK Gates 2.00E-03 ALLOFF ALLON 1.50E-03 1.00E-03 500.00E-06 000.00E+00 '1-1 '1-1 '1-1 '1-1 1-1 '1-2 3 6 8 12 24 48 CLK Ratio Flash - Core Core Freq (MHz) Figure 4. Run mode supply current vs. core frequency (loop located in SRAM) Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 23 NXP Semiconductors General VLPR Mode Current vs Core Frequency Temperature=25, VDD=3, MCG=LIRC8M, while loop in SRAM 250.00E-06 Current Consumption on VDD (A) 200.00E-06 150.00E-06 All Peripheral CLK Gates ALLOFF ALLON 100.00E-06 50.00E-06 CLK Ratio Flash - Core Core Freq (MHz) 000.00E+00 '1-1 '1-2 '1-4 1 2 4 Figure 5. VLPR mode current vs. core frequency (loop in SRAM) 2.2.6 EMC radiated emissions operating behaviors Table 13. EMC radiated emissions operating behaviors for 24-pin QFN package Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15–50 5 dBμV VRE2 Radiated emissions voltage, band 2 50–150 7 dBμV VRE3 Radiated emissions voltage, band 3 150–500 5 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 5 dBμV IEC/SAE level 0.15–1000 N — VRE_IEC 2, 3 1. Determined according to IEC 61967-2 (and SAE J1752/3) radiated radio frequency (RF) emissions measurement standard. Typical Configuration: Appendix B: DUT Software Configuration—2. Typical Configuration. 2. VDD = 3.3 V, TA = 25 °C, firc48m = 48 MHz, fSYS = 48 MHz, fBUS = 24 MHz 3. IEC/SAE Level Maximums: N≤12 dBµV, M≤18 dBµV, L≤24 dBµV, K≤30 dBµV, I ≤ 36 dBµV, H ≤ 42 dBµV, G≤48 dBµV. 24 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 General 2.2.7 EMC Radiated Emissions Web Search Procedure boilerplate To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.nxp.com. 2. Perform a keyword search for "EMC design" 2.2.8 Capacitance attributes Table 14. Capacitance attributes Symbol CIN Description Input capacitance Min. Max. Unit — 7 pF Min. Max. Unit 2.3 Switching specifications 2.3.1 Device clock specifications Table 15. Device clock specifications Symbol Description Normal run mode fSYS System and core clock — 48 MHz fBUS Bus clock — 24 MHz fFLASH Flash clock — 24 MHz fLPTMR LPTMR clock — 24 MHz VLPR and VLPS modes1 fSYS System and core clock — 4 MHz fBUS Bus clock — 1 MHz Flash clock — 1 MHz — 24 MHz MHz fFLASH clock2 fLPTMR LPTMR fERCLK External reference clock — 16 fERCLK External reference clock — 32.768 kHz — 16 MHz TPM asynchronous clock — 8 MHz UART0 asynchronous clock — 8 MHz fLPTMR_ERCLK LPTMR external reference clock fTPM fUART0 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 25 NXP Semiconductors General 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 16. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1 External RESET and NMI pin interrupt pulse width — Asynchronous path 100 — ns 2 GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2 Port rise and fall time — 36 ns 3 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 17. Thermal operating requirements of WLCSP package Symbol Description Min. Max. Unit TJ Die junction temperature –40 95 °C TA Ambient temperature –40 85 °C Note 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + RθJA × chip power dissipation. Table 18. Thermal operating requirements of other packages Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C Note 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + RθJA × chip power dissipation. 26 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 Peripheral operating requirements and behaviors 2.4.2 Thermal attributes Table 19. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 16 QFN 20 WLCSP 24 QFN Unit Notes Thermal resistance, junction to ambient (natural convection) 64.2 69.8 60.7 °C/W 1,2 RθJA Thermal resistance, junction to ambient (natural convection) 53.3 57.5 48.5 °C/W 1,2,3 Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 55.4 62.03 51.0 °C/W 1,3 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 48.9 54.3 43.6 °C/W 1,3 — RθJB Thermal resistance, junction to board 33.5 51.64 30.4 °C/W 4 — RθJC Thermal resistance, junction to case 20.9 0.73 9.8 °C/W 5 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 0.2 0.2 0.2 °C/W 6 — ΨJB Thermal characterization parameter, junction to package bottom outside center (natural convection) 22.4 ― 21.8 °C/W 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. 3 Peripheral operating requirements and behaviors 3.1 Core modules Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 27 NXP Semiconductors Peripheral operating requirements and behaviors 3.1.1 SWD electricals Table 20. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 25 MHz 1/J1 — ns 20 — ns SWD_CLK frequency of operation • Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width • Serial wire debug J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 6. Serial wire clock input timing 28 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 Peripheral operating requirements and behaviors SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 7. Serial wire data timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG-Lite specifications Table 21. HIRC48M specification Symbol Description Min. Typ. Max. Unit Notes VDD Supply voltage 1.71 — 3.6 V — IDD48M Supply current — 400 500 μA — firc48m Internal reference frequency — 48 — MHz — Δfirc48m_ol_lv total deviation of IRC48M frequency at low voltage (VDD=1.71V-1.89V) over temperature — %firc48m — ± 0.5 ±1.5 Table continues on the next page... Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 29 NXP Semiconductors Peripheral operating requirements and behaviors Table 21. HIRC48M specification (continued) Symbol Description Min. Δfirc48m_ol_hv total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over temperature Jcyc_irc48m tirc48mst Typ. Max. Unit Notes — — ± 0.5 ±1.0 %firc48m Period Jitter (RMS) — 35 150 ps — Startup time — 2 3 μs 1 1. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by setting MCG_MC[HIRCEN] = 1. See reference manual for details. Table 22. LIRC8M/2M specification Symbol Description Min. Typ. Max. Unit Notes VDD Supply voltage 1.08 — 1.47 V — T Temperature range -40 — 125 °C — IDD_2M Supply current in 2 MHz mode — 14 17 µA — IDD_8M Supply current in 8 MHz mode — 30 35 µA — fIRC_2M Output frequency — 2 — MHz — fIRC_8M Output frequency — 8 — MHz — fIRC_T_2M Output frequency range (trimmed) — — ±3 %fIRC VDD≥1.89 V fIRC_T_8M Output frequency range (trimmed) — — ±3 %fIRC VDD≥1.89 V Tsu_2M Startup time — — 12.5 µs — Tsu_8M Startup time — — 12.5 µs — 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 23. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit Notes VDD Supply voltage 1.71 — 3.6 V — IDDOSC Supply current — low-power mode • 32 kHz 1 — 500 — nA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode — — — MΩ 2, 4 RS Series resistor — low-frequency, low-power mode — — — kΩ — Table continues on the next page... 30 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 Peripheral operating requirements and behaviors Table 23. Oscillator DC electrical specifications (continued) Symbol 5 Vpp 1. 2. 3. 4. 5. Description Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode Min. Typ. Max. Unit Notes — 0.6 — V — VDD=3.3 V, Temperature =25 °C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Symbol fosc_lo tdc_extal tcst Oscillator frequency specifications Table 24. Oscillator frequency specifications Description Min. Typ. Max. Unit Notes Oscillator crystal or resonator frequency — low frequency mode 32 — 40 kHz — Input clock duty cycle (external clock mode) 40 50 60 % — Crystal startup time — 32 kHz low-frequency, low-power mode — 750 — ms 1, 2 1. Proper PC board layout procedures must be followed to achieve specifications. 2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 25. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes thvpgm4 Longword Program high-voltage time — 7.5 18 μs — thversscr Sector Erase high-voltage time — 13 113 ms 1 thversall Erase All high-voltage time — 52 452 ms 1 Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 31 NXP Semiconductors Peripheral operating requirements and behaviors 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications — commands Table 26. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersscr Erase Flash Sector execution time — 14 114 ms 2 trd1all Read 1s All Blocks execution time — — 0.5 ms — trdonce Read Once execution time — — 25 μs 1 Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 61 500 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tpgmonce 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 27. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 3.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 2.5 6.0 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 28. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years — tnvmretp1k Data retention after up to 1 K cycles 20 100 — years — nnvmcycp Cycling endurance 10 K 50 K — cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C. 32 NXP Semiconductors Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 Peripheral operating requirements and behaviors 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications All ADC channels meet the 12-bit single-ended accuracy specifications. 3.6.1.1 12-bit ADC operating conditions Table 29. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 — 3.6 V — ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V 3 VREFL ADC reference voltage low VSSA VSSA VSSA V 3 VADIN Input voltage VREFL — VREFH V — CADIN Input capacitance — 4 5 pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) • 8-bit / 10-bit / 12-bit modes 12-bit modes 4 fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion ≤ 12-bit mode clock frequency 1.0 — 18.0 MHz Crate ADC conversion ≤ 12-bit modes rate No ADC hardware averaging 5 6 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017 33 NXP Semiconductors Peripheral operating requirements and behaviors 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 8. ADC input impedance equivalency diagram 3.6.1.2 12-bit ADC electrical characteristics Table 30. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1. Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 IDDA_ADC Supply current fADACK ADC asynchronous clock source Sample Time TUE Total unadjusted error See Reference Manual chapter for sample times • 12-bit modes — ±6 — •
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