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MKL05Z32VFM4R

MKL05Z32VFM4R

  • 厂商:

    NXP(恩智浦)

  • 封装:

    VFQFN32_EP

  • 描述:

    IC MCU 32BIT 32KB FLASH 32QFN

  • 数据手册
  • 价格&库存
MKL05Z32VFM4R 数据手册
Freescale Semiconductor, Inc. Data Sheet: Technical Data KL05P48M48SF1 Rev 4 03/2014 Kinetis KL05 32 KB Flash 48 MHz Cortex-M0+ Based Microcontroller Designed with efficiency in mind. Features a size efficient, small package, energy efficient ARM Cortex-M0+ 32-bit performance. Shares the comprehensive enablement and scalability of the Kinetis family. This product offers: • Run power consumption down to 45 μA/MHz in very low power run mode • Static power consumption down to 2 μA with full state retention and 4 μs wakeup • Ultra-efficient Cortex-M0+ processor running up to 48MHz with industry leading throughput • Memory option is up to 32 KB Flash and 4 KB RAM • Energy-saving architecture is optimized for low power with 90 nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller Performance • 48 MHz ARM® Cortex®-M0+ core Memories and memory interfaces • Up to 32 KB program flash memory • Up to 4 KB SRAM MKL05ZxxVFK4 MKL05ZxxVLC4 MKL05ZxxVFM4 MKL05ZxxVLF4 24-pin QFN (FK) 32-pin QFN (FM) 4 x 4 x 1 Pitch 0.5 mm 5 x 5 x 1 Pitch 0.5 mm 32-pin LQFP (LC) 7 x 7 x 1.4 Pitch 0.8 mm 48-pin LQFP (LF) 7 x 7 x 1.4 Pitch 0.5 mm Human-machine interface • Low-power hardware touch sensor interface (TSI) • Up to 41 general-purpose input/output (GPIO) Communication interfaces • One 8-bit SPI module • One low power UART module • One I2C module System peripherals • Nine low-power modes to provide power optimization based on application requirements Analog Modules • COP Software watchdog • 12-bit SAR ADC • 4-channel DMA controller, supporting up to 63 request • 12-bit DAC sources • Analog comparator (CMP) containing a 6-bit DAC • Low-leakage wakeup unit and programmable reference input • SWD debug interface and Micro Trace Buffer • Bit Manipulation Engine Timers • Six channel Timer/PWM (TPM) Clocks • One 2-channel Timer/PWM module • 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator • Periodic interrupt timers • Multi-purpose clock source • 16-bit low-power timer (LPTMR) • 1 kHz LPO clock • Real time clock Operating Characteristics • Voltage range: 1.71 to 3.6 V • Flash write voltage range: 1.71 to 3.6 V • Temperature range (ambient): -40 to 105°C Security and integrity modules • 80-bit unique identification number per chip Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2014 Freescale Semiconductor, Inc. All rights reserved. Ordering Information Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL05Z8VFK4 8 1 22 MKL05Z16VFK4 16 2 22 MKL05Z32VFK4 32 4 22 MKL05Z8VLC4 8 1 28 MKL05Z16VLC4 16 2 28 MKL05Z32VLC4 32 4 28 MKL05Z8VFM4 8 1 28 MKL05Z16VFM4 16 2 28 MKL05Z32VFM4 32 4 28 MKL05Z16VLF4 16 2 41 MKL05Z32VLF4 32 4 41 Related Resources Type Description Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal connections. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Package drawing Package dimensions are provided in package drawings. 2 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Table of Contents 1 Ratings..................................................................................4 1.1 Thermal handling ratings...............................................4 1.2 Moisture handling ratings...............................................4 1.3 ESD handling ratings.....................................................4 1.4 Voltage and current operating ratings............................4 2 General.................................................................................5 2.1 AC electrical characteristics...........................................5 2.2 Nonswitching electrical specifications............................5 2.2.1 Voltage and current operating requirements......5 2.2.2 LVD and POR operating requirements..............6 2.2.3 Voltage and current operating behaviors...........7 2.2.4 Power mode transition operating behaviors.......8 2.2.5 Power consumption operating behaviors...........9 2.2.6 EMC performance..............................................15 2.2.7 Capacitance attributes.......................................16 2.3 Switching specifications.................................................16 2.3.1 Device clock specifications................................16 2.3.2 General switching specifications........................17 2.4 Thermal specifications...................................................17 2.4.1 Thermal operating requirements........................17 2.4.2 Thermal attributes..............................................17 3 Peripheral operating requirements and behaviors................18 3.1 Core modules................................................................18 3.1.1 SWD electricals .................................................18 3.2 System modules............................................................19 3.3 Clock modules...............................................................20 3.3.1 MCG specifications............................................20 3.3.2 Oscillator electrical specifications......................21 3.4 Memories and memory interfaces.................................23 3.4.1 Flash electrical specifications............................23 3.5 Security and integrity modules.......................................25 3.6 Analog............................................................................25 3.6.1 ADC electrical specifications..............................25 Kinetis KL05 32 KB Flash, Rev4 03/2014. 4 5 6 7 8 9 3.6.2 CMP and 6-bit DAC electrical specifications......28 3.6.3 12-bit DAC electrical characteristics..................30 3.7 Timers............................................................................33 3.8 Communication interfaces.............................................33 3.8.1 SPI switching specifications...............................33 3.8.2 Inter-Integrated Circuit Interface (I2C) timing.....38 3.8.3 UART.................................................................39 3.9 Human-machine interfaces (HMI)..................................39 3.9.1 TSI electrical specifications................................39 Dimensions...........................................................................40 4.1 Obtaining package dimensions......................................40 Pinout....................................................................................40 5.1 KL05 signal multiplexing and pin assignments..............40 5.2 KL05 pinouts..................................................................42 Ordering parts.......................................................................46 6.1 Determining valid orderable parts..................................46 Part identification...................................................................46 7.1 Description.....................................................................46 7.2 Format...........................................................................47 7.3 Fields.............................................................................47 7.4 Example.........................................................................47 Terminology and guidelines..................................................48 8.1 Definition: Operating requirement..................................48 8.2 Definition: Operating behavior.......................................48 8.3 Definition: Attribute........................................................48 8.4 Definition: Rating...........................................................49 8.5 Result of exceeding a rating..........................................49 8.6 Relationship between ratings and operating requirements..................................................................49 8.7 Guidelines for ratings and operating requirements........50 8.8 Definition: Typical value.................................................50 8.9 Typical value conditions.................................................51 Revision history.....................................................................52 3 Freescale Semiconductor, Inc. Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2. Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 3. ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model –500 +500 V 2 Latch-up current at ambient temperature of 105 °C –100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA VIO IO pin input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDD – 0.3 VDD + 0.3 V ID VDDA Analog supply voltage 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. • CL=30 pF loads • Slew rate disabled • Normal drive strength 2.2 Nonswitching electrical specifications Kinetis KL05 32 KB Flash, Rev4 03/2014. 5 Freescale Semiconductor, Inc. General 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V — VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V — VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V — VIH VIL Input high voltage — • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V Input low voltage — • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V 0.06 × VDD — V –3 — mA — +3 VHYS Input hysteresis IICIO IO pin negative DC injection current—single pin — 1 • VIN < VSS–0.3V (negative current injection) • VIN < VSS–0.3V (positive current injection) IICcont Notes Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection • Positive current injection — –25 — mA — +25 VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V — 1. All IO pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VIO_MIN (=VSS-0.3V) and VIN is less than VIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. The positive injection current limiting resistor is calculated as R=(VIN-VIO_MAX)/|IICIO|. Select the larger of these two calculated resistances. 2. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 6. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit Notes VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V — VLVDH Falling low-voltage detect threshold — high range (LVDV = 01) 2.48 2.56 2.64 V — Low-voltage warning thresholds — high range 1 Table continues on the next page... 6 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General Table 6. VDD supply LVD and POR operating requirements (continued) Symbol Min. Typ. Max. Unit VLVW1H Description • Level 1 falling (LVWV = 00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV = 01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV = 10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V — ±60 — mV — 1.54 1.60 1.66 V — VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) Notes Low-voltage warning thresholds — low range VLVW1L • Level 1 falling (LVWV = 00) VLVW2L • Level 2 falling (LVWV = 01) VLVW3L • Level 3 falling (LVWV = 10) VLVW4L • Level 4 falling (LVWV = 11) VHYSL Low-voltage inhibit reset/recover hysteresis — low range 1 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.16 V — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 7. Voltage and current operating behaviors Symbol VOH Description Min. Unit Output high voltage — Normal drive pad (except RESET) • 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA VOH Max. 1, 2 VDD – 0.5 — V VDD – 0.5 — V Output high voltage — High drive pad (except RESET_b) • 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA IOHT Output high current total for all ports VOL Output low voltage — Normal drive pad Notes 1, 2 VDD – 0.5 — V VDD – 0.5 — V — 100 mA 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — 0.5 V Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 7 Freescale Semiconductor, Inc. General Table 7. Voltage and current operating behaviors (continued) Symbol VOL Description Min. Max. Unit Notes Output low voltage — High drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA — • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA 0.5 V — 0.5 V Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 41 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ IOLT 4 1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz. Table 8. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit — — 300 μs — 95 115 μs • VLLS0 → RUN 1 • VLLS1 → RUN Table continues on the next page... 8 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit — 93 115 μs — 42 53 μs — 4 4.6 μs — 4 4.4 μs — 4 4.4 μs • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors Symbol IDDA Description Analog supply current IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash Min. Typ. Max.1 Unit Notes — — See note mA 2 3 — 4.0 4.3 mA • at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code executing from flash 3 — 4.9 5.3 mA • at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code executing from flash • at 3.0 V • at 25 °C 3, 4 mA — 5.7 5.8 — 6.0 6.2 • at 125 °C IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V 3 — 2.7 2.9 mA Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 9 Freescale Semiconductor, Inc. General Table 9. Power consumption operating behaviors (continued) Symbol Description Min. IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus / flash disabled (flash doze enabled) • at 3.0 V IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code executing from flash • at 3.0 V IDD_VLPR IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code executing from flash • at 3.0 V Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code executing from flash • at 3.0 V IDD_VLPW Very low power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V IDD_STOP • at 50 °C • at 70 °C • at 85 °C • at 105 °C • at 50 °C • at 70 °C • at 85 °C • at 105 °C Unit Notes 3 — 2.2 2.3 mA 3 — 1.5 1.7 mA 5 — 182 253 μA 5 — 213 284 μA 4, 5 — 243 313 μA 5 — 111 170 — 257 277 — 265 285 — 278 303 — 295 326 — 353 412 — 2.25 5.76 — 4.08 8.27 — 8.10 14.52 — 14.18 23.78 — 37.07 58.58 Very-low-power stop mode current • at 3.0 V • at 25 °C IDD_LLS Max.1 Stop mode current • at 3.0 V • at 25 °C IDD_VLPS Typ. μA μA μA Low-leakage stop mode current • at 3.0 V Table continues on the next page... 10 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General Table 9. Power consumption operating behaviors (continued) Symbol Min. Typ. Max.1 Unit • at 25 °C — 1.72 2.01 μA • at 50 °C — 2.52 3.18 • at 70 °C — 4.32 5.94 • at 85 °C — 7.18 10.00 • at 105 °C — 18.67 25.65 — 1.16 1.36 — 1.78 2.27 — 3.23 4.38 — 5.57 7.53 — 14.80 19.74 — 0.64 0.81 — 1.14 1.50 — 2.35 3.20 — 4.37 5.80 — 12.40 16.13 — 0.38 0.54 — 0.88 1.23 — 2.10 2.95 — 4.14 5.59 — 12.00 15.73 Description IDD_VLLS3 Very-low-leakage stop mode 3 current • at 3.0 V • at 25 °C • at 50 °C • at 70 °C • at 85 °C • at 105 °C IDD_VLLS1 Very-low-leakage stop mode 1 current • at 3.0 V • at 25°C • at 50°C • at 70°C • at 85°C • at 105°C IDD_VLLS0 Very-low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) • at 3.0 V • at 25 °C • at 50 °C • at 70 °C • at 85 °C Notes μA μA μA • at 105 °C IDD_VLLS0 Very-low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) • at 3.0 V • at 25 °C • at 50 °C • at 70 °C • at 85 °C • at 105 °C 6 — 0.30 0.45 — 0.79 1.12 — 2.01 2.82 — 4.05 5.45 — 11.96 15.63 μA 1. Data based on characterization results. Kinetis KL05 32 KB Flash, Rev4 03/2014. 11 Freescale Semiconductor, Inc. General 2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. 6. No brownout Table 10. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 µA IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 µA IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 uA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. • VLLS1 • VLLS3 • LLS • VLPS • STOP 440 490 540 560 570 580 440 490 540 560 570 580 490 490 540 560 570 680 510 560 560 560 610 680 510 560 560 560 610 680 nA ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 µA IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 432 357 388 475 532 810 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. • MCGIRCLK (4 MHz internal reference clock) • OSCERCLK (4 MHz external crystal) 66 66 66 66 66 66 µA 214 237 246 254 260 268 Table continues on the next page... 12 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General Table 10. Low power mode peripheral adders — typical value (continued) Symbol ITPM Description TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. • MCGIRCLK (4 MHz internal reference clock) • OSCERCLK (4 MHz external crystal) Temperature (°C) Unit -40 25 50 70 85 105 86 86 86 86 86 86 235 256 265 274 280 287 µA IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 µA 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • • • • MCG in FBE for run mode, and BLPE for VLPR mode No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFA Kinetis KL05 32 KB Flash, Rev4 03/2014. 13 Freescale Semiconductor, Inc. General Run Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 7.00E-03 6.00E-03 Current Consumption on VDD (A) 5.00E-03 4.00E-03 All Peripheral CLK Gates All Off All On 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 1 2 3 4 6 12 24 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 2. Run mode supply current vs. core frequency 14 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General VLPR Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 350.00E-06 300.00E-06 Current Consumption on VDD (A) 250.00E-06 200.00E-06 All Peripheral CLK Gates All Off All On 150.00E-06 100.00E-06 50.00E-06 000.00E+00 '1-1 '1-2 1 '1-2 '1-4 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. VLPR mode current vs. core frequency 2.2.6 EMC performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation play a significant role in EMC performance. The system designer must consult the following Freescale applications notes, available on freescale.com for advice and guidance specifically targeted at optimizing EMC performance. • AN2321: Designing for Board Level Electromagnetic Compatibility • AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers • AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers Kinetis KL05 32 KB Flash, Rev4 03/2014. 15 Freescale Semiconductor, Inc. General • AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications • AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems 2.2.7 Capacitance attributes Table 11. Capacitance attributes Symbol CIN Description Input capacitance Min. Max. Unit — 7 pF Min. Max. Unit 2.3 Switching specifications 2.3.1 Device clock specifications Table 12. Device clock specifications Symbol Description Normal run mode fSYS System and core clock — 48 MHz fBUS Bus clock — 24 MHz fFLASH Flash clock — 24 MHz fLPTMR LPTMR clock — 24 MHz VLPR and VLPS modes1 fSYS System and core clock — 4 MHz fBUS Bus clock — 1 MHz Flash clock — 1 MHz — 24 MHz — 16 MHz — 16 MHz Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) — 16 MHz TPM asynchronous clock — 8 MHz UART0 asynchronous clock — 8 MHz fFLASH clock2 fLPTMR LPTMR fERCLK External reference clock fLPTMR_ERCLK LPTMR external reference clock fosc_hi_2 fTPM fUART0 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 16 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. General 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 13. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1 External RESET and NMI pin interrupt pulse width — Asynchronous path 100 — ns 2 GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2 Port rise and fall time — 36 ns 3 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 14. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C 2.4.2 Thermal attributes Table 15. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) RθJA Description 48 LQFP 32 LQFP 32 QFN 24 QFN Thermal resistance, junction to ambient (natural convection) 82 88 97 Thermal resistance, junction to ambient (natural convection) 58 59 34 Unit Notes 110 °C/W 1 42 °C/W Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 17 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 15. Thermal attributes (continued) Board type Symbol Single-layer (1S) RθJMA Four-layer (2s2p) Description 48 LQFP 32 LQFP 32 QFN 24 QFN Unit Notes Thermal resistance, junction to ambient (200 ft./min. air speed) 70 74 81 92 °C/W RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 52 52 28 36 °C/W — RθJB Thermal resistance, junction to board 36 35 13 18 °C/W 2 — RθJC Thermal resistance, junction to case 27 26 2.3 3.7 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 8 8 8 10 °C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 SWD electricals Table 16. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 25 MHz 1/J1 — ns SWD_CLK frequency of operation • Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width Table continues on the next page... 18 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 16. SWD full voltage range electricals (continued) Symbol Description Min. Max. Unit 20 — ns • Serial wire debug J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 4. Serial wire clock input timing SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 5. Serial wire data timing Kinetis KL05 32 KB Flash, Rev4 03/2014. 19 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 17. MCG specifications Symbol Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C — 32.768 — kHz fints_t Internal reference frequency (slow clock) — user trimmed 31.25 — 39.0625 kHz — ± 0.3 ± 0.6 %fdco 1 Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using C3[SCTRIM] and C4[SCFTRIM] Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — +0.5/-0.7 ±3 %fdco 1, 2 Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70 °C — ± 0.4 ± 1.5 %fdco 1, 2 Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25 °C — 4 — MHz Δfintf_ft Frequency deviation of internal reference clock (fast clock) over temperature and voltage — factory trimmed at nominal VDD and 25 °C — +1/-2 ±3 %fintf_ft fintf_t Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C 3 — 5 MHz fintf_ft floc_low Loss of external clock minimum frequency — RANGE = 00 (3/5) x fints_t — — kHz floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 (16/5) x fints_t — — kHz 31.25 — 39.0625 kHz 20 20.97 25 MHz 40 41.94 48 MHz — 23.99 — MHz — 47.97 — MHz 2 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 3, 4 640 × ffll_ref Mid range (DRS = 01) 1280 × ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS = 00) 5, 6 732 × ffll_ref Mid range (DRS = 01) Table continues on the next page... 20 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 17. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes — 180 — ps 7 — — 1 ms 8 1464 × ffll_ref Jcyc_fll FLL period jitter • fVCO = 48 MHz tfll_acquire FLL target frequency acquisition time 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 18. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Supply current — high gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA — 3 — mA — 4 — mA Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 21 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 18. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes • 24 MHz • 32 MHz Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, lowpower mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V RS 2, 4 Series resistor — high-frequency, high-gain mode (HGO=1) 5 Vpp 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 22 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors 3.3.2.2 Symbol Oscillator frequency specifications Table 19. Oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — high-frequency mode (low range) (MCG_C2[RANGE]=01) 3 — 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz fec_extal Input clock frequency (external clock mode) — — 48 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — — ms Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms fosc_lo tcst Description Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Kinetis KL05 32 KB Flash, Rev4 03/2014. 23 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 Notes Longword Program high-voltage time — 7.5 18 μs thversscr Sector Erase high-voltage time — 13 113 ms 1 thversall Erase All high-voltage time — 52 452 ms 1 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications — commands Table 21. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec1k tpgmchk Read 1s Section execution time (flash sector) — — 60 μs 1 Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs tersscr Erase Flash Sector execution time — 14 114 ms trd1all Read 1s All Blocks execution time — — 0.5 ms trdonce Read Once execution time — — 25 μs Program Once execution time — 65 — μs tersall Erase All Blocks execution time — 61 500 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tpgmonce 2 1 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 3.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 2.5 6.0 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 23. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash Table continues on the next page... 24 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Min. Typ.1 Max. Unit tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles Symbol Description Notes 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C. 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications All ADC channels meet the 12-bit single-ended accuracy specifications. 3.6.1.1 12-bit ADC operating conditions Table 24. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.6 V ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V 3 VREFL ADC reference voltage low VSSA VSSA VSSA V 3 VADIN Input voltage VREFL — VREFH V CADIN Input capacitance — 4 5 pF RADIN Input series resistance — 2 5 kΩ • 8-bit / 10-bit / 12-bit modes Notes Table continues on the next page... Kinetis KL05 32 KB Flash, Rev4 03/2014. 25 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 24. 12-bit ADC operating conditions (continued) Symbol Description Conditions RAS Analog source resistance (external) 12-bit modes Min. Typ.1 Max. Unit Notes 4 fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion ≤ 12-bit mode clock frequency 1.0 — 18.0 MHz Crate ADC conversion ≤ 12-bit modes rate No ADC hardware averaging 5 6 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/ CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE VADIN CAS VAS RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 6. ADC input impedance equivalency diagram 26 Freescale Semiconductor, Inc. Kinetis KL05 32 KB Flash, Rev4 03/2014. Peripheral operating requirements and behaviors 3.6.1.2 12-bit ADC electrical characteristics Table 25. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current ADC asynchronous clock source fADACK Conditions1 • ADLPC = 1, ADHSC = 0 • ADLPC = 1, ADHSC = 1 • ADLPC = 0, ADHSC = 0 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 1.2 2.4 3.9 MHz 2.4 4.0 6.1 MHz tADACK = 1/ fADACK 3.0 5.2 7.3 MHz 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA5 • ADLPC = 0, ADHSC = 1 Sample Time TUE DNL INL EFS See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 •
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