Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document Number: KL17P64M48SF6
Rev. 6, 02/2016
Kinetis KL17 Microcontroller
MKL17Z128Vxx4
MKL17Z256Vxx4
MKL17Z256CAL4R
48 MHz ARM® Cortex®-M0+ and 128/256 KB Flash
The KL17 series is optimized for cost-sensitive and batterypowered applications requiring low-power general-purpose
connectivity. The product offers:
• Embedded ROM with boot loader for flexible program
upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
• Down to 54uA/MHz in very low power run mode and
1.96uA in deep sleep mode (RAM + RTC retained)
Core Processor
• ARM® Cortex®-M0+ core up to 48 MHz
Memories
• 128/256 KB program flash memory
• 32 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin Serial Wire Debug (SWD) programming and
debug interface
• Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller
Clocks
• 48MHz high accuracy (up to 0.5%) internal reference
clock
• 8MHz/2MHz high accuracy (up to 3%) internal
reference clock
• 1KHz reference clock active under all low-power
modes (except VLLS0)
• 32–40KHz and 3–32MHz crystal oscillator
© 2014–2016 Freescale Semiconductor, Inc. All rights reserved.
32 and 48 QFN
36 WLCSP
5x5 mm P 0.5 mm 7x7
2.8x2.7 mm P 0.4 mm
mm P 0.5 mm
64 LQFP
10x10 mm P 0.5 mm
64 BGA
5x5 mm P 0.5 mm
Peripherals
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1
Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of
additional UART, IrDA, SPI, I2C, I2S, PWM and
other serial modules, etc.
• One serial audio interface I2S
• One 16-bit 818 ksps ADC module with high
accuracy internal voltage reference (Vref) and up to
16 channels
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
• One 12-bit DAC
• 1.2 V internal voltage reference
Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
Operating Characteristics
Security and Integrity
• Voltage range: 1.71 to 3.6 V
• 80-bit unique identification number per chip
• Flash write voltage range: 1.71 to 3.6 V
• Advanced flash security
• Temperature range: –40 to 85 °C for WLCSP package
I/O
and –40 to 105 °C for other packages
• Up to 54 general-purpose input/output pins (GPIO)
Packages
and 6 high-drive pad
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm
Low Power
thickness
• Down to 54uA/MHz in very low power run mode
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm
• Down to 1.96uA in VLLS3 mode (RAM + RTC
thickness
retained)
• 48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness
• Six flexible static modes
• 32 QFN 5mm x 5mm, 0.5mm pitch, 0.65mm thickness
• 36 WLCSP 2.8mm x 2.7mm, 0.4mm pitch, 0.6mm
thickness
Ordering Information
Product
Memory
Package
IO and ADC channel
Part number
Marking (Line1/
Line2)
Flash
(KB)
SRAM
(KB)
Pin
count
Package
GPIOs
GPIOs
(INT/HD)1
ADC
channels
(SE/DP)
MKL17Z128VFM4
M17P7V
128
32
32
QFN
28
19/6
11/2
MKL17Z256VFM4
M17P8V
256
32
32
QFN
28
19/6
11/2
MKL17Z128VFT4
M17P7V
128
32
48
QFN
40
24/6
18/3
MKL17Z256VFT4
M17P8V
256
32
48
QFN
40
24/6
18/3
MKL17Z128VLH4
MKL17Z128V//LH4
128
32
64
LQFP
54
31/6
20/4
MKL17Z256VLH4
MKL17Z256V//LH4
256
32
64
LQFP
54
31/6
20/4
MKL17Z128VMP4
M17P7V
128
32
64
MAPBGA
54
31/6
20/4
MKL17Z256VMP4
M17P8V
256
32
64
MAPBGA
54
31/6
20/4
MKL17Z256CAL4R
MKL17Z256CAL4
256
32
36
WLCSP
26
23/6
7/0
1. INT: interrupt pin numbers; HD: high drive pin numbers
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KL1XPB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KL17P64M48SF6RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_L_1N71K1
a particular device mask set.
Table continues on the next page...
2
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Related Resources (continued)
Type
Package
drawing
Description
Package dimensions are provided in package drawings.
Resource
64-LQFP: 98ASS23234W1 64MAPBGA: 98ASA00420D, 132QFN: 98ASA00615D1 48-QFN:
98ASA00616D, 136-WLCSP:
98ASA00949D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 20
2.2.7 Designing with radiated emissions in mind..........21
2.2.8 Capacitance attributes.........................................21
2.3 Switching specifications...................................................21
2.3.1 Device clock specifications..................................21
2.3.2 General switching specifications......................... 22
2.4 Thermal specifications..................................................... 22
2.4.1 Thermal operating requirements......................... 22
2.4.2 Thermal attributes................................................23
3 Peripheral operating requirements and behaviors.................. 24
3.1 Core modules.................................................................. 24
3.1.1 SWD electricals .................................................. 24
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG-Lite specifications.......................................25
3.3.2 Oscillator electrical specifications........................27
3.4 Memories and memory interfaces................................... 29
3.4.1 Flash electrical specifications.............................. 29
3.5 Security and integrity modules........................................ 31
3.6 Analog............................................................................. 31
4
Freescale Semiconductor, Inc.
4
5
6
7
8
9
3.6.1 ADC electrical specifications............................... 31
3.6.2 Voltage reference electrical specifications.......... 36
3.6.3 CMP and 6-bit DAC electrical specifications....... 37
3.6.4 12-bit DAC electrical characteristics....................39
3.7 Timers..............................................................................42
3.8 Communication interfaces............................................... 42
3.8.1 SPI switching specifications................................ 42
3.8.2 I2C....................................................................... 47
3.8.3 UART...................................................................48
3.8.4 I2S/SAI switching specifications.......................... 49
Dimensions............................................................................. 53
4.1 Obtaining package dimensions....................................... 53
Pinouts and Packaging........................................................... 54
5.1 KL17 signal multiplexing and pin assignments................ 54
5.2 KL17 Family Pinouts........................................................57
5.3 Recommended connection for unused analog and
digital pins........................................................................61
Ordering parts......................................................................... 62
6.1 Determining valid orderable parts....................................62
Part identification.....................................................................62
7.1 Description.......................................................................62
7.2 Format............................................................................. 63
7.3 Fields............................................................................... 63
7.4 Example...........................................................................63
Terminology and guidelines.................................................... 64
8.1 Definitions........................................................................ 64
8.2 Examples......................................................................... 64
8.3 Typical-value conditions.................................................. 65
8.4 Relationship between ratings and operating
requirements....................................................................65
8.5 Guidelines for ratings and operating requirements..........66
Revision History...................................................................... 66
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
–2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
–500
+500
V
2
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
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General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
mA
VIO
IO pin input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
ID
VDDA
Analog supply voltage
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
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Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
General
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-3
—
mA
-25
—
mA
VIH
VIL
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
IO pin negative DC injection current — single pin
1
• VIN < VSS-0.3V
IICcont
Notes
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
• Negative current injection
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
2
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
—
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
1
Table continues on the next page...
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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General
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol
Min.
Typ.
Max.
Unit
VLVW1H
Description
• Level 1 falling (LVWV = 00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV = 01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV = 10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV = 11)
2.92
3.00
3.08
V
—
±60
—
mV
—
1.54
1.60
1.66
V
—
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
VLVW1L
• Level 1 falling (LVWV = 00)
VLVW2L
• Level 2 falling (LVWV = 01)
VLVW3L
• Level 3 falling (LVWV = 10)
VLVW4L
• Level 4 falling (LVWV = 11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
1
1.74
1.80
1.86
V
1.84
1.90
1.96
V
1.94
2.00
2.06
V
2.04
2.10
2.16
V
—
±40
—
mV
—
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
—
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
—
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol
VOH
VOH
Description
Min.
Unit
Output high voltage — normal drive pad
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
—
V
Output high voltage — high drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
—
V
—
100
mA
—
0.5
V
—
0.5
V
Output high current total for all ports
VOL
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
Notes
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
IOHT
VOL
Max.
Output low voltage — high drive pad
1
1
—
0.5
V
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
General
Table 7. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
2
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
2
IIN
Input leakage current (total all pins) for full
temperature range
—
64
μA
2
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
Notes
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
IOLT
3
1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the
associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 8. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
—
152
166
μs
—
152
166
μs
—
93
104
μs
—
7.5
8
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
Table continues on the next page...
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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General
Table 8. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
7.5
8
μs
—
7.5
8
μs
Notes
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_FOPT[LPBOOT]=11)
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while (1) test is executed with flash cache enabled.
NOTE
The data at 105 °C are for QFN, LQFP and MAPBGA
packages only.
Table 9. Power consumption operating behaviors
Symbol
IDDA
Description
Analog supply current
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
2
—
5.76
6.40
—
6.04
6.68
—
3.21
3.85
—
3.49
4.13
mA
mA
2
—
6.45
7.09
—
6.75
7.39
Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable, 24
MHz core/12 MHz flash, VDD = 3.0 V
mA
2
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
General
Table 9. Power consumption operating behaviors (continued)
Symbol
IDD_RUN
Description
Min.
Typ.
Max.
• at 25 °C
—
3.95
4.59
• at 105 °C
—
4.23
4.87
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 12
MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock disable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock disable,
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock enable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
Unit
Notes
mA
2
—
2.68
3.32
—
2.96
3.60
mA
2
—
8.08
8.72
—
8.39
9.03
—
3.90
4.54
—
4.21
4.85
—
2.66
3.30
—
2.94
3.58
—
2.03
2.67
—
2.31
2.95
—
5.52
6.16
—
5.83
6.47
—
5.29
5.93
—
5.56
6.20
—
6.91
7.55
—
7.19
7.91
mA
mA
mA
mA
mA
mA
mA
Table continues on the next page...
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_VLPRCO Very Low Power Run Core Mark in Flash in
Compute Operation mode: Core@4MHz, Flash
@1MHz, VDD = 3.0 V
• at 25 °C
—
826
907
μA
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode, 4
MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
405
486
μA
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode, 2
MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
154
235
μA
—
108
189
μA
—
39
120
μA
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
249
330
μA
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
337
418
μA
—
416
497
μA
—
494
575
μA
—
166
247
μA
Notes
• at 25 °C
• at 105 °C
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
50
131
μA
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
208
289
μA
Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.81
1.89
mA
Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.22
1.39
mA
IDD_VLPW Very-low-power wait mode current, core disabled,
4 MHz system/ 1 MHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
—
172
182
μA
IDD_VLPW Very-low-power wait mode current, core disabled,
2 MHz system/ 0.5 MHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
—
69
76
μA
IDD_VLPW Very-low-power wait mode current, core disabled,
125 kHz system/ 31.25 kHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
—
36
40
μA
—
1.81
2.06
mA
—
1.00
1.25
mA
—
161.93
171.82
—
181.45
191.96
—
236.29
271.17
—
390.33
465.58
—
3.31
5.14
—
10.43
17.68
—
34.14
61.06
—
104.38
164.44
—
3.21
5.22
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V
• at 25 °C
IDD_VLPR
IDD_WAIT
IDD_WAIT
Notes
IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12
MHz bus and flash, VDD = 3.0 V
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
IDD_STOP
Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at 1.8 V
• at 25 °C and below
μA
μA
Table continues on the next page...
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General
Table 9. Power consumption operating behaviors (continued)
Symbol
IDD_LLS
Description
Min.
Typ.
Max.
• at 50 °C
—
10.26
17.62
• at 85 °C
—
33.49
60.19
• at 105 °C
—
102.92
162.20
—
2.06
3.33
—
4.72
6.85
—
8.13
13.30
—
13.34
24.70
—
41.08
52.43
—
2.46
3.73
—
5.12
7.25
—
8.53
11.78
—
13.74
18.91
—
41.48
52.83
Low-leakage stop mode current, all peripheral
disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_LLS
Low-leakage stop mode current with RTC current,
at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_LLS
Low-leakage stop mode current with RTC current,
at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
Unit
Notes
μA
μA
μA
3
—
2.35
2.70
—
4.91
6.75
—
8.32
11.78
—
13.44
18.21
—
40.47
51.85
—
1.45
1.85
—
3.37
4.39
—
5.76
8.48
—
9.72
14.30
—
30.41
37.50
μA
μA
3
—
2.05
2.45
—
3.97
4.99
—
6.36
9.08
—
10.32
14.73
—
31.01
38.10
μA
Table continues on the next page...
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Freescale Semiconductor, Inc.
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General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
• at 25 °C and below
Min.
Typ.
Max.
—
1.96
2.36
—
3.86
5.67
—
6.23
8.53
—
10.21
13.37
—
30.25
37.02
—
0.66
0.80
—
1.78
3.87
—
2.55
4.26
—
4.83
6.64
—
16.42
20.49
—
1.26
1.40
—
2.38
4.47
—
3.15
4.86
—
5.43
7.24
—
17.02
21.09
—
1.96
2.28
—
2.78
3.37
—
4.85
6.88
—
15.78
18.81
—
0.35
0.47
• at 50 °C
—
1.25
1.44
• at 70 °C
—
2.53
3.24
• at 85 °C
—
4.40
5.24
• at 105 °C
—
16.09
19.29
• at 105 °C
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
• at 25 °C and below
μA
μA
3
1.30
• at 85°C
μA
3
1.16
• at 70°C
Notes
3
—
• at 50°C
Unit
μA
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
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Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors
Symbol
Description
Min.
Typ.
Max.
• at 25 °C and below
—
0.18
0.28
• at 50 °C
—
1.09
1.31
• at 70 °C
—
2.25
2.94
• at 85 °C
—
4.25
5.10
• at 105 °C
—
15.95
19.10
Unit
Notes
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIRC8MHz
8 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
93
93
93
93
93
93
µA
IIRC2MHz
2 MHz internal reference clock (IRC)
adder. Measured by entering STOP mode
with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
29
29
29
29
29
29
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
224
230
238
245
253
µA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
• VLLS1
440
490
540
560
570
580
440
490
540
560
570
580
490
490
540
560
570
680
510
560
560
560
610
680
510
560
560
560
610
680
30
30
30
85
100
200
• VLLS3
• LLS
• VLPS
• STOP
ILPTMR
nA
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
Table continues on the next page...
16
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
-40
25
50
70
Unit
85
105
nA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare. Includes
6-bit DAC power consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source waiting for RX
data at 115200 baud rate. Includes
selected clock source power consumption.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source configured for
output compare generating 100 Hz clock
signal. No load is placed on the I/O
generating the clock signal. Includes
selected clock source and I/O switching
currents.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
22
22
22
22
22
22
µA
114
114
114
114
114
114
µA
34
34
34
34
34
34
147
147
147
147
147
147
42
42
42
42
42
42
µA
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx or VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
330
330
330
330
330
330
µA
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
No GPIOs toggled
Code execution from flash
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
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General
Figure 2. Run mode supply current vs. core frequency
18
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Kinetis KL17 Microcontroller, Rev. 6, 02/2016
General
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
19
Freescale Semiconductor, Inc.
Current
ionon
onVDD
VDD
(A)
CurrentC
Consumpt
onsumption
(A)
General
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP
package
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
11
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
12
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
10
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
6
dBμV
IEC level
0.15–1000
N
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
20
Freescale Semiconductor, Inc.
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General
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = IRC48M, fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol
CIN
Description
Input capacitance
Min.
Max.
Unit
—
7
pF
Min.
Max.
Unit
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Normal run mode
fSYS
System and core clock1
—
48
MHz
fBUS
Bus clock1
—
24
MHz
—
24
MHz
—
24
MHz
clock1
fFLASH
Flash
fLPTMR
LPTMR clock
VLPR and VLPS
modes2
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
fFLASH
Flash clock
—
1
MHz
fLPTMR
LPTMR clock3
—
24
MHz
Table continues on the next page...
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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General
Table 13. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
—
16
MHz
Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
—
16
MHz
TPM asynchronous clock
—
8
MHz
LPUART0/1 asynchronous clock
—
8
MHz
fLPTMR_ERCLK LPTMR external reference clock
fosc_hi_2
fTPM
fLPUART0/1
1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher
than the specified maximum frequency when IRC 48MHz is used as the clock source.
2. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
3. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
—
36
ns
3
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements for WLCSP package
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
95
°C
TA
Ambient temperature
–40
85
°C
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Notes
1
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
General
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
Table 16. Thermal operating requirements for other packages
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Notes
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
2.4.2 Thermal attributes
Table 17. Thermal attributes
Board type
Symbo
l
Single-layer (1S)
RθJA
Four-layer (2s2p)
RθJA
Single-layer (1S)
Description
48
QFN
32
QFN
64
LQFP
64
MAPB
GA
36
WLCS
P
Unit
Notes
Thermal resistance,
junction to ambient
(natural convection)
86
101
70
50.3
77.6
°C/W
1
Thermal resistance,
junction to ambient
(natural convection)
29
33
51
42.9
38.9
°C/W
RθJMA
Thermal resistance,
junction to ambient (200
ft./min. air speed)
71
84
58
41.4
69.6
°C/W
Four-layer (2s2p)
RθJMA
Thermal resistance,
junction to ambient (200
ft./min. air speed)
24
28
45
38.0
35.6
°C/W
—
RθJB
Thermal resistance,
junction to board
12
13
33
39.6
34.8
°C/W
2
—
RθJC
Thermal resistance,
junction to case
1.7
1.7
20
27.3
0.37
°C/W
3
—
ΨJT
Thermal characterization
parameter, junction to
package top outside
center (natural convection)
2
3
4
0.4
0.2
°C/W
4
—
ΨJB
Thermal characterization
parameter, junction to
package bottom (natural
convection)
-
-
-
12.6
-
°C/W
5
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
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Peripheral operating requirements and behaviors
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
5. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 18. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 4. Serial wire clock input timing
24
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Peripheral operating requirements and behaviors
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 5. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications
Table 19. IRC48M specification
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD
Supply current
—
400
500
µA
—
fIRC
Output frequency
—
48
—
MHz
—
Δfirc48m_ol_lv
Open loop total deviation of IRC48M
frequency at low voltage
(VDD=1.71V-1.89V) over temperature
—
± 0.5
± 1.5
%firc48m
Δfirc48m_ol_hv
Open loop total deviation of IRC48M
frequency at high voltage
(VDD=1.89V-3.6V) over temperature
—
± 0.5
± 1.0
%firc48m
1
1
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 19. IRC48M specification (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Tj
Period jitter (RMS)
—
35
150
ps
—
Tsu
Startup time
—
2
3
µs
—
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean +/-3sigma).
Table 20. IRC8M/2M specification
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_2M
Supply current in 2 MHz mode
—
14
17
µA
—
IDD_8M
Supply current in 8 MHz mode
—
30
35
µA
—
fIRC_2M
Output frequency
—
2
—
MHz
—
fIRC_8M
Output frequency
—
8
—
MHz
—
fIRC_T_2M
Output frequency range (trimmed)
—
—
±3
%fIRC
—
fIRC_T_8M
Output frequency range (trimmed)
—
—
±3
%fIRC
—
Tsu_2M
Startup time
—
—
12.5
µs
—
Tsu_8M
Startup time
—
—
12.5
µs
—
26
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Peripheral operating requirements and behaviors
Figure 6. IRC8M Frequency Drift vs Temperature curve
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 21. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
—
1.2
—
mA
Table continues on the next page...
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 21. Oscillator DC electrical specifications (continued)
Symbol
Description
• 24 MHz
Min.
Typ.
Max.
Unit
—
1.5
—
mA
Notes
• 32 MHz
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
Cy
XTAL load capacitance
—
—
—
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, lowpower mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
RS
2, 3
2, 3
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
28
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Peripheral operating requirements and behaviors
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2
Symbol
Oscillator frequency specifications
Table 22. Oscillator frequency specifications
Min.
Typ.
Max.
Unit
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency —
high-frequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
fosc_lo
tcst
Description
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
29
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
—
52
452
ms
1
Unit
Notes
thversblk128k Erase Block high-voltage time for 128 KB
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Symbol
Flash timing specifications — commands
Table 24. Flash command timing specifications
Description
Min.
Typ.
Max.
Read 1s Block execution time
trd1blk128k
• 128 KB program flash
1
—
—
1.7
ms
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
Erase Flash Block execution time
tersblk128k
• 128 KB program flash
2
—
88
600
ms
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
175
1300
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tersallu
Erase All Blocks Unsecure execution time
—
175
1300
ms
2
tpgmonce
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
30
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Peripheral operating requirements and behaviors
3.4.1.3
Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 26. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
Using differential inputs can achieve better system accuracy than using single-end
inputs.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
31
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.1.1
16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
3
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
3
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 ×
VREFH
V
—
• All other modes
VREFL
—
• 16-bit mode
—
8
10
pF
—
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
kΩ
—
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
VREFH
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
24
MHz
5
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
5
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
4
6
20.000
—
1200
ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
6
37.037
—
461.467
ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH can act as VREF_OUT when VREFV1 module is enabled.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
32
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 6, 02/2016
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 7. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
IDDA_ADC Supply current
ADC asynchronous
clock source
fADACK
Sample Time
TUE
DNL
INL
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
•
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