MKL17Z64VFM4

Freescale Semiconductor, Inc. Data Sheet: Technical Data Document Number: KL17P64M48SF2 Rev. 5, 04/2015 Kinetis KL17 Microcontroller MKL17Z32Vxx4(R) MKL17Z64Vxx4(R) 48 MHz ARM® Cortex®-M0+ and 32/64 KB Flash The KL17 series is optimized for cost-sensitive and batterypowered applications requiring low-power general purpose connectivity. The product offers: • Embedded ROM with boot loader for flexible program upgrade • High accuracy internal voltage and clock reference • FlexIO to support any standard and customized serial peripheral emulation • Hardware CRC module • Down to 46 µA/MHz in very low power run mode and 1.68 µA in stop mode (RAM + RTC retained) Core Processor • ARM® Cortex®-M0+ core up to 48 MHz Memories • 32/64 KB program flash memory • 8/16 KB SRAM • 16 KB ROM with build-in bootloader • 32-byte backup register System • 4-channel asynchronous DMA controller • Watchdog • Low-leakage wakeup unit • Two-pin SWD (serial wire debug) programming and debug interface • Micro trace buffer • Bit manipulation engine • Interrupt controller Clocks • 48 MHz high accuracy (up to 0.5%) internal reference clock • 8 MHz high accuracy (up to 3%) internal reference clock • 1 kHz reference clock active under all low power modes (except VLLS0) • 32–40 kHz and 3–32 MHz crystal oscillator © 2014–2015 Freescale Semiconductor, Inc. All rights reserved. 64 LQFP (LH) 10x10x1.6 mm P .5 36 XFBGA (DA) 3.5x3.5x.5 mm P .5 48 & 32 QFN(FT&FM) 64 MAPBGA (MP) 7x7x.65 mm P .5(FT) 5x5x1.23 mm P .5 mm 5x5x.65 mm P .5(FM) Peripherals • One UART module supporting ISO7816, operating up to 1.5 Mbit/s • Two low-power UART modules supporting asynchronous operation in low-power modes • Two I2C modules supporting up to 1 Mbit/s • Two 16-bit SPI modules supporting up to 24 Mbit/s for SPI1 and 12 Mbit/s for SPI0 • One FlexIO module supporting emulation of additional UART, SPI, I2C, I2S, PWM and other serial modules, etc. • One 16-bit ADC module with high accurate internal voltage reference, up to 20 channels and up to 818 ksps at equal to or less than 13-bit mode • High-speed analog comparator containing a 6-bit DAC for programmable reference input Timers • One 6-channel Timer/PWM module • Two 2-channel Timer/PWM modules • One low-power timer • Periodic interrupt timer • Real time clock Operating Characteristics Security and Integrity • 80-bit unique identification number per chip • Advanced flash security • Hardware CRC module • Voltage range: 1.71 to 3.6 V • Flash write voltage range: 1.71 to 3.6 V • Temperature range: –40 to 105 °C Packages • 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm thickness • 36 XFBGA 3.5mm x 3.5mm, 0.5mm pitch, 0.5mm thickness • 32 QFN 5mm x 5mm, 0.5mm pitch, 0.65mm thickness • 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm thickness (Package Your Way) • 48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness (Package Your Way) I/O • Up to 54 general-purpose input/output pins Low Power • Down to 46 µA/MHz in very low power run mode • Down to 1.68 µA in stop mode (RAM + RTC retained) • Six flexible static modes NOTE The 48 QFN and 64 MAPBGA packages supporting MKLx7ZxxVFT4 and MKLx7ZxxVMP4 part numbers for this product are not yet available. However, these packages are included in Package Your Way program for Kinetis MCUs. Visit Freescale.com/KPYW for more details. Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to KL1xPB1 enable quick evaluation of a device for design suitability. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL17P64M48SF2RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. KL17P64M48SF21 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. xN87M2 Package drawing Package dimensions are provided in package drawings. XFBGA 36-pin: 98ASA00708D LQFP 64-pin: 98ASS23234W QFN 32-pin: 98ASA00615D QFN 48-pin: 98ASA00616D MAPBGA 64-pin: 98ASA00420D 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x” replaced by the revision of the device you are using. 2 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Table of Contents 1 Ordering information............................................................. 4 2 Overview............................................................................... 4 2.1 System features............................................................. 5 2.1.1 ARM Cortex-M0+ core.....................................5 2.1.2 NVIC................................................................ 6 2.1.3 AWIC............................................................... 6 2.1.4 Memory............................................................7 2.1.5 Reset and boot................................................ 7 2.1.6 Clock options................................................... 9 2.1.7 Security............................................................12 2.1.8 Power management........................................ 12 2.1.9 LLWU...............................................................14 2.1.10 Debug controller.............................................. 15 2.1.11 COP................................................................. 15 2.2 Peripheral features........................................................ 16 2.2.1 BME................................................................. 16 2.2.2 DMA and DMAMUX.........................................16 2.2.3 TPM................................................................. 17 2.2.4 ADC................................................................. 17 2.2.5 VREF............................................................... 18 2.2.6 CMP.................................................................19 2.2.7 RTC................................................................. 19 2.2.8 PIT................................................................... 20 2.2.9 LPTMR............................................................ 20 2.2.10 CRC................................................................. 21 2.2.11 UART............................................................... 21 2.2.12 LPUART.......................................................... 22 2.2.13 SPI................................................................... 22 2.2.14 I2C................................................................... 23 2.2.15 FlexIO.............................................................. 23 2.2.16 Port control and GPIO..................................... 24 3 Memory map......................................................................... 26 4 Pinouts.................................................................................. 27 4.1 KL17 Signal Multiplexing and Pin Assignments.............27 4.2 Pin properties.................................................................30 4.3 Module Signal Description Tables................................. 33 4.3.1 Core modules.................................................. 33 4.3.2 System modules.............................................. 33 4.3.3 Clock modules................................................. 34 4.3.4 Analog............................................................. 34 4.3.5 Timer Modules................................................. 35 4.3.6 Communication interfaces............................... 36 Kinetis KL17 Microcontroller, Rev. 5, 04/2015 4.3.7 Human-machine interfaces (HMI)....................38 4.4 KL17 Family Pinouts...................................................... 38 4.5 Package dimensions......................................................43 5 Electrical characteristics........................................................51 5.1 Ratings...........................................................................51 5.1.1 Thermal handling ratings................................. 51 5.1.2 Moisture handling ratings................................ 52 5.1.3 ESD handling ratings....................................... 52 5.1.4 Voltage and current absolute operating ratings.............................................................. 52 5.2 General.......................................................................... 53 5.2.1 AC electrical characteristics............................ 53 5.2.2 Nonswitching electrical specifications............. 53 5.2.3 Switching specifications...................................68 5.2.4 Thermal specifications..................................... 69 5.3 Peripheral operating requirements and behaviors......... 70 5.3.1 Core modules.................................................. 70 5.3.2 System modules.............................................. 72 5.3.3 Clock modules................................................. 72 5.3.4 Memories and memory interfaces................... 75 5.3.5 Security and integrity modules........................ 77 5.3.6 Analog............................................................. 77 5.4 Timers............................................................................ 85 5.5 Communication interfaces............................................. 85 5.5.1 SPI switching specifications............................ 85 5.5.2 Inter-Integrated Circuit Interface (I2C) timing.. 89 5.5.3 UART............................................................... 91 6 Design considerations...........................................................91 6.1 Hardware design considerations................................... 91 6.1.1 Printed circuit board recommendations........... 92 6.1.2 Power delivery system.....................................92 6.1.3 Analog design.................................................. 93 6.1.4 Digital design................................................... 93 6.1.5 Crystal oscillator.............................................. 96 6.2 Software considerations................................................ 98 7 Part identification...................................................................99 7.1 Description..................................................................... 99 7.2 Format........................................................................... 99 7.3 Fields............................................................................. 99 7.4 Example......................................................................... 100 8 Revision history.....................................................................100 3 Freescale Semiconductor, Inc. Ordering information 1 Ordering information The following chips are available for ordering. Table 1. Ordering information Product Part number Memory Marking (Line1/Line2) Package IO and ADC channel Flash (KB) SRAM (KB) Pin count Package GPIOs GPIOs (INT/HD)1 ADC channels (SE/DP) MKL17Z64VLH4 MKL17Z64 / VLH4 64 16 64 LQFP 54 54/6 20/4 MKL17Z32VLH4 MKL17Z32 / VLH4 32 8 64 LQFP 54 54/6 20/4 MKL17Z64VDA4 M17M6 64 16 36 XFBGA 32 32/6 15/4 MKL17Z32VDA4 M17M5 32 8 36 XFBGA 32 32/6 15/4 MKL17Z64VFM4 M17M6V 64 16 32 QFN 28 28/6 11/2 MKL17Z32VFM4 M17M5V 32 8 32 QFN 28 28/6 11/2 MKL17Z64VMP4 TBD 64 16 64 MAPBGA 54 54/6 20/4 MKL17Z32VMP4 TBD 32 8 64 MAPBGA 54 54/6 20/4 MKL17Z64VFT4 TBD 64 16 48 QFN 40 40/6 18/3 MKL17Z32VFT4 TBD 32 8 48 QFN 40 40/6 18/3 1. INT: interrupt pin numbers; HD: high drive pin numbers NOTE The 48 QFN and 64 MAPBGA packages supporting MKLx7ZxxVFT4 and MKLx7ZxxVMP4 part numbers for this product are not yet available. However, these packages are included in Package Your Way program for Kinetis MCUs. Visit Freescale.com/KPYW for more details. 2 Overview The following figure shows the system diagram of this device 4 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview GPIOA GPIOB Slave Master GPIOC Cortex M0+ GPIOD GPIOE IOPORT CM0+ Core M0 NVIC DMA MUX 64 KB Flash CMP 1.2 V Voltage reference TPM0(6 channel) S0 16 KB ROM S1 16 KB RAM S2 BME TPM1(2 channel) Peripheral Bridge(Bus Clock - Max 24MHZ) 4-ch DMA M2 Crossabar Switch(Platform Clock - Max 48MHZ) Debug (SWD) ADC(16 bit 16ch) FMC TPM2(2 channel) Low Power Timer PIT RTC LPUART0 LPUART1 UART2 SPI0 SPI1 I2C0 I2C1 FlexIO Watchdog(COP) Register File(32 Bytes) MCG - Lite CRC HIRC48M LLWU LIRC2M/8M SMC RCM OSC PMC Figure 1. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. 2.1 System features The following sections describe the high-level system features. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 5 Freescale Semiconductor, Inc. Overview 2.1.1 ARM Cortex-M0+ core The enhanced ARM Cortex M0+ is the member of the Cortex-M series of processors targeting microcontroller cores focused on very cost sensitive, low power applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality including support for simple program trace capability. The processor supports the ARMv6-M instruction set (Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It is upward compatible with other Cortex-M profile processors. 2.1.2 NVIC The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It also differs in number of interrupt sources and supports 32 interrupt vectors. The Cortex-M family uses a number of methods to improve interrupt latency to up to 15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and VLPW modes. 2.1.3 AWIC The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous wake-up events in Stop mode and signal to clock control logic to resume system clocking. After clock restarts, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. The AWIC can be used to wake MCU core from Stop and VLPS modes. Wake-up sources are listed as below: Table 2. AWIC stop wake-up sources Wake-up source Description Available system resets RESET pin with filter mode disabled or enabled when LPO is its clock source, COP when its clock source is enabled. COP can also work when its clock source is enabled during Stop mode. Low-voltage detect Power management controller—functional in Stop mode Low-voltage warning Power management controller—functional in Stop mode Pin interrupts Port control module—any enabled pin interrupt is capable of waking the system ADC The ADC is functional when using internal clock source or external crystal clock CMP0 Interrupt in normal or trigger mode Table continues on the next page... 6 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview Table 2. AWIC stop wake-up sources (continued) Wake-up source Description I2Cx Address match wakeup LPUART0 , LPUART1 Any enabled interrupt can be a source as long as the module remains clocked UART2 Active edge on RXD RTC Alarm or seconds interrupt NMI NMI pin TPMx Any enabled interrupt can be a source as long as the module remains clocked LPTMR Any enabled interrupt can be a source as long as the module remains clocked SPIx Slave mode interrupt FlexIO Any enabled interrupt can be a source as long as the module remains clocked 2.1.4 Memory This device has the following features: • 8/16 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states. • The non-volatile memory is divided into two arrays • 32/64 KB of embedded program memory • 16 KB ROM (built-in bootloader to support UART, I2C, and SPI interfaces) The program flash memory contains a 16-byte flash configuration field that stores default protection settings and security information. The page size of program flash is 1 KB. The protection setting can protect 32 regions of the program flash memory from unintended erase or program operations. The security circuitry prevents unauthorized access to RAM or flash contents from debug port. • System register file This device contains a 32-byte register file that is powered in all power modes. Also, it retains contents during low power modes and is reset only during a power-on reset. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 7 Freescale Semiconductor, Inc. Overview 2.1.5 Reset and boot The following table lists all the reset sources supported by this device. NOTE In the following table, Y means the specific module, except for the registers, bits or conditions mentioned in the footnote, is reset by the corresponding Reset source. N means the specific module is not reset by the corresponding Reset source. Table 3. Reset source Reset sources Descriptions POR reset Power-on reset (POR) PMC SIM SMC RCM LLWU Reset pin is negated RTC Y Y Y Y Y Y Y Y Y Y1 Y Y Y Y Y N Y Y Low leakage wakeup (LLWU) reset N Y2 N Y N Y3 N N Y External pin reset (RESET) Y1 Y2 Y4 Y Y Y N N Y Computer operating properly (COP) watchdog reset Y1 Y2 Y4 Y5 Y Y N N Y Stop mode acknowledge error (SACKERR) Y1 Y2 Y4 Y5 Y Y N N Y Software reset (SW) Y1 Y2 Y4 Y5 Y Y N N Y Lockup reset (LOCKUP) Y1 Y2 Y4 Y5 Y Y N N Y MDM DAP system reset Y1 Y2 Y4 Y5 Y Y N N Y Debug reset Y1 Y2 Y4 Y5 Y Y N N Y System resets Low-voltage detect (LVD) Debug reset 1. 2. 3. 4. 5. Modules LPTMR Others Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV] Except SIM_SOPT1 Only if RESET is used to wake from VLLS mode. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT Except RCM_RPFC, RCM_RPFW, RCM_FM The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR) to relocate the exception vector table after reset. This device supports booting from: • internal flash • boot ROM 8 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows the user to customize the operation of the MCU at boot time. The register contains read-only bits that are loaded from the NVM's option byte in the flash configuration field. Below is boot flow chart for this device. POR or Reset N RCM[FORCEROM] =00 Y FOPT[BOOTPIN_OPT]=0 N Y BOOTCFG0 pin=0 Y N N FOPT[BOOTSRC _SEL]=10/11 Y Boot from ROM Boot from Flash Figure 2. Boot flow chart The blank chip is default to boot from ROM and remaps the vector table to ROM base address, otherwise, it remaps to flash address. 2.1.6 Clock options This chip provides a wide range of sources to generate the internal clocks. These sources include internal resistor capacitor (IRC) oscillators, external oscillators, external clock sources, and ceramic resonators. These sources can be configured to provide the required performance and optimize the power consumption. The IRC oscillators include the high-speed internal resister capacitor (HIRC) oscillator, the low-speed internal resister capacitor (LIRC) oscillator, and the low power oscillator (LPO). The HIRC oscillator generates a 48 MHz clock. The LIRC oscillator generates an 8 MHz or 2 MHz clock, and default to 8 MHz system clock on reset. The LIRC oscillator cannot be used in any VLLS modes. The LPO generates a 1 kHz clock and cannot be used in VLLS0 mode. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 9 Freescale Semiconductor, Inc. Overview The system oscillator supports low frequency crystals (32 kHz to 40 kHz), high frequency crystals (1 MHz to 32 MHz), and ceramic resonators (1 MHz to 32 MHz). An external clock source, DC to 48 MHz, can be used as the system clock through the EXTAL0 pin. The external oscillator also supports a low speed external clock (32.768 kHz) on the RTC_CLKIN pin for use with the RTC. For more details on the clock operations and configurations, see Reference Manual. The following figure is a high level block diagram of the clock generation. Multipurpose Clock Generator Lite IRC_TRIMs System Integration MCGPCLK HIRC48M LIRC_DIV2 CG MCGIRCLK LIRC 8MHz/ 8MHz 2MHz IRC 2MHz FCRDIV IRCS MCGOUTCLK CG Core/Platform/System clock OUTDIV4 CG Bus/Flash clock CLKS System oscillator EREFS0 EXTAL0 OUTDIV1 OSCCLK XTAL_CLK XTAL0 OSC logic OSC32KCLK OSCERCLK CG ERCLK32K RTC_CKLIN OS32KSEL RTC Counter logic RTCCLKOUTSEL PMC PMC logic LPO RTC_CLKOUT 1Hz CG — Clock gate Figure 3. Clock block diagram In order to provide flexibility, many peripherals can select from multiple clock sources for operation. This enables the peripheral to select a clock that will always be available during operation in various operational modes. The following table summarizes the clocks associated with each module. 10 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview Table 4. Module clocks Module Bus interface clock Internal clocks I/O interface clocks — Core modules ARM Cortex-M0+ core Platform clock Core clock NVIC Platform clock — — DAP Platform clock — SWD_CLK System modules DMA System clock — — DMA Mux Bus clock — — Port control Bus clock — — Crossbar Switch Platform clock — — Peripheral bridges System clock Bus clock — LLWU, PMC, SIM, RCM Bus clock LPO — Mode controller Bus clock — — MCM Platform clock — — COP watchdog Bus clock LPO, Bus Clock, MCGIRCLK, OSCERCLK — CRC Bus clock — — Clocks MCG_Lite Bus clock MCGOUTCLK, MCGPCLK, MCGIRCLK, OSCERCLK, ERCLK32K — OSC Bus clock OSCERCLK — Memory and memory interfaces Flash Controller Platform clock Flash memory Flash clock Flash clock — — — Analog ADC Bus clock OSCERCLK — CMP Bus clock — — Internal Voltage Reference (VREF) Bus clock — — Timers TPM Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1 PIT Bus clock — — LPTMR Bus clock LPO, OSCERCLK, MCGPCLK, ERCLK32K — RTC Bus clock ERCLK32K RTC_CLKOUT, RTC_CLKIN Communication interfaces SPI0 Bus clock — SPI0_SCK SPI1 System clock — SPI1_SCK I2C0 System Clock — I2C0_SCL Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 11 Freescale Semiconductor, Inc. Overview Table 4. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks I2C1 System Clock — I2C1_SCL LPUART0, LPUART1 Bus clock LPUART0 clock — LPUART1 clock UART2 Bus clock — — FlexIO Bus clock FlexIO clock — GPIO Platform clock Human-machine interfaces — — 2.1.7 Security Security state can be enabled via programming flash configuration field (0x40e). After enabling device security, the SWD port cannot access the memory resources of the MCU, and ROM boot loader is also limited to access flash and not allowed to read out flash information via ROM boot loader commands. Access interface Secure state Unsecure operation SWD port Cannot access memory source by SWD The debugger can write to the Flash interface Mass Erase in Progress field of the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command ROM boot loader Interface (UART/I2C/ SPI) Limit access to the flash, cannot read out flash content Send “FlashEraseAllUnsecureh" command or attempt to unlock flash security using the backdoor key This device features 80-bit unique identification number, which is programmed in factory and loaded to SIM register after power-on reset. 2.1.8 Power management The Power Management Controller (PMC) expands upon ARM’s operational modes of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can be used to optimize current consumption for a wide range of applications. The WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current configuration. For more information on ARM’s operational modes, See the ARM® Cortex User Guide. 12 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview The PMC provides Run (Run), and Very Low Power Run (VLPR) configurations in ARM’s Run operation mode. In these modes, the MCU core is active and can access all peripherals. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The configuration that matches the power versus performance requirements of the application can be selected. The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive, all of the peripherals can be enabled and operate as programmed. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop (LLS), and Very Low Leakage Stop (VLLS) configurations in ARM’s Deep Sleep operational mode. In these modes, the MCU core and most of the peripherals are disabled. Depending on the requirements of the application, different portions of the analog, logic, and memory can be retained or disabled to conserve power. The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are used to wake up the MCU from low power states. The NVIC is used to wake up the MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU core from STOP and VLPS modes. The LLWU is used to wake up the MCU core from LLS and VLLSx modes. For additional information regarding operational modes, power management, the NVIC, AWIC, or the LLWU, please refer to the Reference Manual. The following table provides information about the state of the peripherals in the various operational modes and the modules that can wake MCU from low power modes. Table 6. Peripherals states in different operational modes Core mode Run mode Sleep mode Device mode Descriptions Run In Run mode, all device modules are operational. Very Low Power Run In VLPR mode, all device modules are operational at a reduced frequency except the Low Voltage Detect (LVD) monitor, which is disabled. Wait In Wait mode, all peripheral modules are operational. The MCU core is placed into Sleep mode. Very Low Power Wait In VLPW mode, all peripheral modules are operational at a reduced frequency except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU core is placed into Sleep mode. Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 13 Freescale Semiconductor, Inc. Overview Table 6. Peripherals states in different operational modes (continued) Core mode Deep sleep Device mode Descriptions Stop In Stop mode, most peripheral clocks are disabled and placed in a static state. Stop mode retains all registers and SRAMs while maintaining Low Voltage Detection protection. In Stop mode, the ADC, CMP, LPTimer, RTC, and pin interrupts are operational. The NVIC is disabled, but the AWIC can be used to wake up from an interrupt. Very Low Power Stop In VLPS mode, the contents of the SRAM are retained. The CMP (low speed), ADC, OSC, RTC, LPTMR, TPM, FlexIO, LPUART, and DMA are operational, LVD and NVIC are disabled, AWIC is used to wake up from interrupt. Low Leakage Stop In LLS mode, the contents of the SRAM and the 32-byte system register file are retained. The CMP (low speed), LLWU, LPTMR, and RTC are operational. The ADC, CRC, DMA, FlexIO, I2C, LPUART, MCG-Lite, NVIC, PIT, SPI, TPM, UART, and COP are static, but retain their programming. The GPIO, and VREF are static, retain their programming, and continue to drive their previous values. Very Low Leakage Stop In VLLS modes, most peripherals are powered off and will resume operation from their reset state when the device wakes up. The LLWU, LPTMR, and RTC are operational in all VLLS modes. In VLLS3, the contents of the SRAM and the 32-byte system register file are retained. The CMP (low speed), and PMC are operational. The GPIO, and VREF are not operational but continue driving. In VLLS1, the contents of the 32-byte system register file are retained. The CMP (low speed), and PMC are operational. The GPIO, and VREF are not operational but continue driving. In VLLS0, the contents of the 32-byte system register file are retained. The PMC is operational. The GPIO is not operational but continues driving. The POR detection circuit can be enabled or disabled. 2.1.9 LLWU The LLWU module is used to wake MCU from low leakage power mode (LLS and VLLSx) and functional only on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU continues to detect wake-up events until the user has acknowledged the wake-up event. This device uses 8 external wakeup pin inputs and 4 internal modules as wakeup sources to the LLWU module. The following is internal peripheral and external pin inputs as wakeup sources to the LLWU module. 14 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview Table 7. Wakeup source LLWU pin Module source or pin name LLWU_P5 PTB0 LLWU_P6 PTC1 LLWU_P7 PTC3 LLWU_P8 PTC4 LLWU_P9 PTC5 LLWU_P10 PTC6 LLWU_P14 PTD4 LLWU_P15 PTD6 LLWU_M0IF LPTMR0 LLWU_M1IF CMP0 LLWU_M2IF Reserved LLWU_M3IF Reserved LLWU_M4IF Reserved LLWU_M5IF RTC alarm LLWU_M6IF Reserved LLWU_M7IF RTC seconds 2.1.10 Debug controller This device supports standard ARM 2-pin SWD debug port. It provides register and memory accessibility from the external debugger interface, basic run/halt control plus 2 breakpoints and 2 watchpoints. It also supports trace function with the Micro Trace Buffer (MTB), which provides a simple execution trace capability for the Cortex-M0+ processor. 2.1.11 COP The COP monitors internal system operation and forces a reset in case of failure. It can run from bus clock, LPO, 8/2 MHz internal oscillator or external crystal oscillator. Optional window mode can detect deviations in program flow or system frequency. The COP has the following features: • Support multiple clock input, 1 kHz clock(LPO), bus clock, 8/2 MHz internal reference clock, external crystal oscillator • Can work in Stop/VLPS and Debug mode Kinetis KL17 Microcontroller, Rev. 5, 04/2015 15 Freescale Semiconductor, Inc. Overview • Configurable for short and long timeout values, the longest timeout is up to 262 seconds • Support window mode 2.2 Peripheral features The following sections describe the features of each peripherals of the chip. 2.2.1 BME The Bit Manipulation Engine (BME) provides hardware support for atomic readmodify-write memory operations to the peripheral address space in Cortex-M0+ based microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for bit-oriented operations to peripheral registers. The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit, bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized data type. 2.2.2 DMA and DMAMUX The DMA controller module enables fast transfers of data, which provides an efficient way to move blocks of data with minimal processor interaction. The DMA controller in this device implements four channels which can be routed from up to 63 DMA request sources through DMA MUX module. Some of the peripheral request sources have asynchronous DMA capability which can be used to wake MCU from Stop mode. The peripherals which have such capability include LPUART0, LPUART1, FlexIO, TPM0TPM2, ADC0, CMP0, PORTA-PORTE. The DMA channel 0 and 1 can be periodically triggered by PIT via DMA MUX. Main features are listed below: • Dual-address transfers via 32-bit master connection to the system bus and data transfers in 8-, 16-, or 32-bit blocks • Supports programmable source and destination address and transfer size, optional modulo addressing from 16 bytes to 256 KB • Automatic updates of source and destination addresses 16 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview • Auto-alignment feature for source or destination accesses allows block transfers to occur at the optimal size based on the address, byte count,and programmed size, which significantly improves the speed of block transfer • Automatic single or double channel linking allows the current DMA channel to automatically trigger a DMA request to the linked channels without CPU intervention For more information on asynchronous DMA, see AN4631. 2.2.3 TPM This device contains three low power TPM modules (TPM). All TPM modules are functional in Stop/VLPS mode if the clock source is enabled. The TPM features include: • TPM clock mode is selectable from external clock input or internal clock source, HIRC48M clock, external crystal input clock or LIRC2M/8M clock. • Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 • TPM includes a 16-bit counter • Includes 6 channels that can be configured for input capture, output compare, edge-aligned PWM mode, or center-aligned PWM mode • Support the generation of an interrupt and/or DMA request per channel or counter overflow • Support selectable trigger input to optionally reset or cause the counter to start or stop incrementing • Support the generation of hardware triggers when the counter overflows and per channel 2.2.4 ADC this device contains one ADC module. This ADC module supports hardware triggers from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features: • Linear successive approximation algorithm with up to 16-bit resolution • Up to four pairs of differential and 17 single-ended external analog inputs • Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16bit, 12-bit, 10-bit, and 8-bit single-ended output modes Kinetis KL17 Microcontroller, Rev. 5, 04/2015 17 Freescale Semiconductor, Inc. Overview • • • • • • • • • • • Single or continuous conversion Configurable sample time and conversion speed/power Selectable clock source up to four Operation in low-power modes for lower noise Asynchronous clock source for lower noise operation with option to output the clock Selectable hardware conversion trigger Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value Temperature sensor Hardware average function up to 32x Selectable voltage reference: external or alternate Self-Calibration mode 2.2.4.1 Temperature sensor This device contains one temperature sensor internally connected to the input channel of AD26, see Table 55 for details of the linearity factor. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031. We recommend to use internal reference voltage as ADC reference with long sample time. 2.2.5 VREF The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically) trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC or CMP. The VREF supports the following programmable buffer modes: • Bandgap on only, used for stabilization and startup • High power buffer mode • Low-power buffer mode • Buffer disabled The VREF voltage output signal, bonded on VREFH for 48 QFN, 64 LQFP and 64 MAPBGA packages and on PTE30 for 32 QFN and 36 XFBGA packages, can be used by both internal and external peripherals in low and high power buffer mode. A 100 nF capacitor must always be connected between this pin and VSSA if the VREF is used. This capacitor must be as close to VREFO pin as possible. 18 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview 2.2.6 CMP The device contains one high-speed comparator and two 8-input multiplexers for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. The CMP includes one 6-bit DAC, which provides a selectable voltage reference for various user application cases. Besides, the CMP also has several module-to-module interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces. The CMP has the following features: • Inputs may range from rail to rail • Programmable hysteresis control • Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output • Selectable inversion on comparator output • Capability to produce a wide range of outputs such as sampled, digitally filtered • External hysteresis can be used at the same time that the output filter is used for internal functions • Two software selectable performance levels: shorter propagation delay at the expense of higher power and Low power with longer propagation delay • DMA transfer support • Functional in all modes of operation except in VLLS0 mode • The filter functions are not available in Stop, VLPS, LLS, or VLLSx modes • Integrated 6-bit DAC with selectable supply reference source and can be power down to conserve power • Two 8-to-1 channel mux 2.2.7 RTC The RTC is an always powered-on block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator or clock directly from RTC_CLKIN pin. RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers. The RTC module has the following features • 32-bit seconds counter with roll-over protection and 32-bit alarm Kinetis KL17 Microcontroller, Rev. 5, 04/2015 19 Freescale Semiconductor, Inc. Overview • 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm • Register write protection with register lock mechanism • 1 Hz square wave or second pulse output with optional interrupt 2.2.8 PIT The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It has two independent channels and each channel has a 32-bit counter. Both channels can be chained together to form a 64-bit counter. Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be used to periodically trigger DMA channel 1. Either channel can be programmed as an ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger DAC. The PIT module has the following features: • Each 32-bit timers is able to generate DMA trigger • Each 32-bit timers is able to generate timeout interrupts • Two timers can be cascaded to form a 64-bit timer • Each timer can be programmed as ADC/TPM trigger source • Timer 0 is able to trigger DAC 2.2.9 LPTMR The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features: • 16-bit time counter or pulse counter with compare • Optional interrupt can generate asynchronous wakeup from any low-power mode • Hardware trigger output • Counter supports free-running mode or reset on compare • Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter 20 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview 2.2.10 CRC This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The CRC module has the following features: • Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register • Programmable initial seed value and polynomial • Option to transpose input data or output data (the CRC result) bitwise or bytewise. • Option for inversion of final CRC result • 32-bit CPU register programming interface 2.2.11 UART This device contains a basic universal asynchronous receiver/transmitter (UART) module with DMA function supported. Generally, this module is used in RS-232, RS-485, and other communications and supports LIN slave operation and ISO7816. The UART module has the following features: • Full-duplex operation • 13-bit baud rate selection with /32 fractional divide, based on the module clock frequency • Programmable 8-bit or 9-bit data format • Programmable transmitter output polarity • Programmable receive input polarity • Up to 14-bit break character transmission. • 11-bit break character detection option • Two receiver wakeup methods with idle line or address mark wakeup • Address match feature in the receiver to reduce address mark wakeup ISR overhead • Ability to select MSB or LSB to be first bit on wire • Support for ISO 7816 protocol to interface with SIM cards and smart cards • Receiver framing error detection • Hardware parity generation and checking Kinetis KL17 Microcontroller, Rev. 5, 04/2015 21 Freescale Semiconductor, Inc. Overview • 1/16 bit-time noise detection • DMA interface 2.2.12 LPUART This product contains two Low-Power UART modules, both of their clock sources are selectable from IRC48M, IRC8M/2M or external crystal clock, and can work in Stop and VLPS modes. They also support 4× to 32× data oversampling rate to meet different applications. The LPUART module has the following features: • Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4× to 32× • Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode • Interrupt, DMA or polled operation • Hardware parity generation and checking • Programmable 8-bit, 9-bit or 10-bit character length • Programmable 1-bit or 2-bit stop bits • Three receiver wakeup methods • Idle line wakeup • Address mark wakeup • Receive data match • Automatic address matching to reduce ISR overhead: • Address mark matching • Idle line address matching • Address match start, address match end • Optional 13-bit break character generation / 11-bit break character detection • Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters • Selectable transmitter output and receiver input polarity 2.2.13 SPI This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes. FIFO function is available only on SPI1 module. The SPI modules have the following features: 22 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview • • • • • • • • • • • • Full-duplex or single-wire bidirectional mode Programmable transmit bit rate Double-buffered transmit and receive data register Serial clock phase and polarity options Slave select output Mode fault error flag with CPU interrupt capability Control of SPI operation during wait mode Selectable MSB-first or LSB-first shifting Programmable 8- or 16-bit data transmission length Receive data buffer hardware match feature 64-bit FIFO mode for high speed/large amounts of data transfers Support DMA 2.2.14 I2C This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer features, and address match to wake MCU from the low power mode. I2C modules support DMA transfer, and the interrupt condition can trigger DMA request when DMA function is enabled. The I2C modules have the following features: • Support for system management bus (SMBus) Specification, version 2 • Software programmable for one of 64 different serial clock frequencies • Software-selectable acknowledge bit • Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation and detection • Repeated START signal generation and detection • Acknowledge bit generation and detection • Bus busy detection • General call recognition • 10-bit address extension • Programmable input glitch filter • Low power mode wakeup on slave address match • Range slave address support • DMA support • Double buffering support to achieve higher baud rate Kinetis KL17 Microcontroller, Rev. 5, 04/2015 23 Freescale Semiconductor, Inc. Overview 2.2.15 FlexIO The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to UART, I2C, SPI, I2S, Camera IF, LCD RGB, PWM/ Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. The FlexIO module has the following features: • Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using remains enabled • Four 32-bit double buffered shift registers with transmit, receive, and data match modes, and continuous data transfer • The timing of the shifter’ shift, load and store events are controlled by the highly flexible 16-bit timer assigned to the shifter • Two or more shifter can be concatenated to support large data transfer sizes • Each 16-bit timers operates independently, supports for reset, enable and disable on a variety of internal or external trigger conditions with programmable trigger polarity • Flexible pin configuration supporting output disabled, open drain, bidirectional output data and output mode • Supports interrupt, DMA or polled transmit/receive operation 2.2.16 Port control and GPIO The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. The following figure shows the basic I/O pad structure. This diagram applies to all I/O pins except PTA20/RESET_b and those configured as pseudo open-drain outputs. PTA20/RESET_b is a true open-drain pin without p-channel output driver or diode to the ESD bus. Pseudo open-drain pins have the p-channel output driver disabled when configured for open-drain operation. None of the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above VDD. 24 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Overview Digital input IBE=1 whenever MUX≠000 PFE MUX IBE LPF ESD Bus VDD RPULL PE PS Analog input Digital output DSE SRE Figure 4. I/O simplified block diagram The PORT module has the following features: • all PIN support interrupt enable . • Configurable edge(rising,falling,both) or level sensitive interrupt type • Support DMA request • Asynchronous wake-up in low-power modes • Configurable pullup, pulldown, and pull-disable on select pins • Configurable high and low drive strength on selected pins • Configurable fast and slow slew rates on selected pins • Configurable passive filter on selected pins • Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions • Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features: • Port Data Input register visible in all digital pin-multiplexing modes • Port Data Output register with corresponding set/clear/toggle registers Kinetis KL17 Microcontroller, Rev. 5, 04/2015 25 Freescale Semiconductor, Inc. Memory map • Port Data Direction register • GPIO support single-cycle access via fast GPIO. 3 Memory map This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. The following figure shows the system memory and peripheral locations 0x4000_0000 0x4000_8000 0x4000_E000 0x4000_F000 0x0000_0000 Flash 0x0000_0000 0x07FF_FFFF 0x1C00_0000 Reserved Boot ROM 0x1C00_4000 0x1FFF_F000 0x4002_1000 0x07FF_FFFF Code space 0x4002_0000 0x4003_2000 0x1C00_0000 0x1C00_0000 ROM 0x1C00_3FFF 0x1C00_3FFF Reserved 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_D000 0x1FFF_F000 SRAM _L Data Space 0x2000_0000 0x2000_3000 0x4000_0000 Reserved Public peripheral 0x400F_F000 0x4400_0000 0x6000_0000 0xE000_0000 SRAM _U 0x2000_2FFF 0x4000_0000 Reserved 0x4007_FFFF 0x400F_E000 BM E 0x400F_E1FF 0x400F_F000 Reserved 0x400F_FFFF Private peripherals 0xE010_0000 0xE010_0000 0xF000_0000 0xF000_1000 0xF000_2000 Others 0xF000_3000 AIPS peripherals Reserved GPIO Reserved M TB M TBDWT ROM Table M CM 0xF000_4000 0xFFFF_FFFF 0xF800_0000 Reserved IOPORT 0xFFFF_FFFF 0x4004_0000 0x4004_1000 0x4004_7000 0x4004_8000 0x4004_9000 0x0000_A000 0x4004_B000 0x4004_C000 0x4004_D000 0x4005_4000 0x4005_5000 0x4005_F000 0x4006_4000 0x4006_5000 0x4006_6000 0x4006_7000 0x4006_C000 0x4007_2000 0x4007_3000 0x4007_4000 0x4007_6000 0x4007_7000 0x4007_C000 0x4007_D000 0x4007_E000 0x4007_F000 Reserved DM A controller Reserved Reserved GPIO controller(alias to 0x400F_F000) Reserved Flash m em ory DM A Channel M ultiplexer Reserved CRC32 Reserved PIT LPTPM 0 LPTPM 1 LPTPM 2 ADC0 Reserved RTC Reserved LPTM R System register file Reserved SIM low power logic SIM PORT A PORT B PORT C PORT D PORT E Reserved LPUART0 LPUART1 Reserved FlexIO Reserved M CG Lite OSC I2C0 I2C1 Reserved UART2 Reserved Reserved CM P VREF Reserved SPI0 SPI1 Figure 5. Memory map 26 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts 4 Pinouts 4.1 KL17 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE The 48 QFN and 64 MAPBGA packages for this product are not yet available. However, these packages are included in Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details. 64 36 LQFP XFB GA 32 QFN 48 QFN 64 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 — F2 9 — — VREF0 VREF0_B VREF0_B — — — — C5 NC NC NC 1 A1 1 — A1 PTE0 DISABLED PTE0/ SPI1_MISO LPUART1_ CLKOUT32 TX K 2 B1 2 — B1 PTE1 DISABLED PTE1 3 — — 1 — VDD VDD VDD 4 C4 — 2 C4 VSS VSS VSS 5 C2 3 3 E1 PTE16 ADC0_DP1/ ADC0_DP1/ PTE16 ADC0_SE1 ADC0_SE1 SPI0_PCS0 UART2_TX 6 C1 4 4 D1 PTE17 ADC0_ DM1/ ADC0_ SE5a SPI0_SCK 7 D1 5 5 E2 PTE18 ADC0_DP2/ ADC0_DP2/ PTE18 ADC0_SE2 ADC0_SE2 SPI0_MOSI I2C0_SDA SPI0_MISO FXIO0_D2 8 D2 6 6 D2 PTE19 ADC0_ DM2/ ADC0_ SE6a SPI0_MISO I2C0_SCL SPI0_MOSI FXIO0_D3 9 E3 — 7 G1 PTE20 ADC0_DP0/ ADC0_DP0/ PTE20 ADC0_SE0 ADC0_SE0 TPM1_CH0 LPUART0_ TX FXIO0_D4 10 E2 — 8 F1 PTE21 ADC0_ DM0/ TPM1_CH1 LPUART0_ RX FXIO0_D5 Kinetis KL17 Microcontroller, Rev. 5, 04/2015 ADC0_ DM1/ ADC0_ SE5a ADC0_ DM2/ ADC0_ SE6a ADC0_ DM0/ PTE17 PTE19 PTE21 RTC_ CLKOUT ALT7 CMP0_OUT I2C1_SDA SPI1_MOSI LPUART1_ RX SPI1_MISO I2C1_SCL TPM_ CLKIN0 FXIO0_D0 UART2_RX TPM_ CLKIN1 LPTMR0_ ALT3 FXIO0_D1 27 Freescale Semiconductor, Inc. Pinouts 64 36 LQFP XFB GA 32 QFN 48 QFN 64 MAP BGA Pin Name Default ADC0_ SE4a ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ADC0_ SE4a 11 E1 — — G2 PTE22 ADC0_DP3/ ADC0_DP3/ PTE22 ADC0_SE3 ADC0_SE3 TPM2_CH0 UART2_TX FXIO0_D6 12 F1 — — F2 PTE23 ADC0_ DM3/ ADC0_ SE7a ADC0_ DM3/ ADC0_ SE7a TPM2_CH1 UART2_RX FXIO0_D7 13 D3 7 9 F4 VDDA VDDA VDDA 14 D3 7 10 G4 VREFH VREFH VREFH 14 — — 10 G4 VREFO VREFO_A VREFO_A 15 D4 8 11 G3 VREFL VREFL VREFL 16 D4 8 12 F3 VSSA VSSA VSSA 17 — — 13 H1 PTE29 CMP0_IN5/ CMP0_IN5/ PTE29 ADC0_ ADC0_ SE4b SE4b TPM0_CH2 TPM_ CLKIN0 18 F2 9 14 H2 PTE30 ADC0_ SE23/ CMP0_IN4 PTE30 TPM0_CH3 TPM_ CLKIN1 19 — — — H3 PTE31 DISABLED PTE31 TPM0_CH4 20 — — 15 H4 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 21 — — 16 H5 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 22 F3 10 17 D3 PTA0 SWD_CLK PTA0 TPM0_CH5 23 F4 11 18 D4 PTA1 DISABLED PTA1 LPUART0_ RX TPM2_CH0 24 E4 12 19 E5 PTA2 DISABLED PTA2 LPUART0_ TX TPM2_CH1 25 E5 13 20 D5 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 26 F5 14 21 G5 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b 27 — — — F5 PTA5 DISABLED PTA5 TPM0_CH2 28 — — — H6 PTA12 DISABLED PTA12 TPM1_CH0 29 — — — G6 PTA13 DISABLED PTA13 TPM1_CH1 30 C3 15 22 G7 VDD VDD VDD 31 C4 16 23 H7 VSS VSS VSS 32 F6 17 24 H8 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_ RX TPM_ CLKIN0 33 E6 18 25 G8 PTA19 XTAL0 XTAL0 PTA19 LPUART1_ TX TPM_ CLKIN1 34 D5 19 26 F8 PTA20 RESET_b 35 D6 20 27 F7 PTB0/ LLWU_P5 ADC0_SE8 ADC0_SE8 PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 SPI1_MOSI SPI1_MISO 36 C6 21 28 F6 PTB1 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1 SPI1_MISO SPI1_MOSI 28 Freescale Semiconductor, Inc. ADC0_ SE23/ CMP0_IN4 PTE23 LPUART1_ TX LPTMR0_ ALT1 SWD_CLK PTA20 LPTMR0_ ALT1 RESET_b Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts 64 36 LQFP XFB GA 32 QFN 48 QFN 64 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 37 — — 29 E7 PTB2 ADC0_ SE12 ADC0_ SE12 PTB2 I2C0_SCL TPM2_CH0 38 — — 30 E8 PTB3 ADC0_ SE13 ADC0_ SE13 PTB3 I2C0_SDA TPM2_CH1 39 — — 31 E6 PTB16 DISABLED PTB16 SPI1_MOSI LPUART0_ RX TPM_ CLKIN0 SPI1_MISO 40 — — 32 D7 PTB17 DISABLED PTB17 SPI1_MISO LPUART0_ TX TPM_ CLKIN1 SPI1_MOSI 41 — — — D6 PTB18 DISABLED PTB18 TPM2_CH0 42 — — — C7 PTB19 DISABLED PTB19 TPM2_CH1 43 — — 33 D8 PTC0 ADC0_ SE14 ADC0_ SE14 PTC0 EXTRG_IN 44 C5 22 34 C6 PTC1/ ADC0_ LLWU_P6/ SE15 RTC_CLKIN ADC0_ SE15 PTC1/ I2C1_SCL LLWU_P6/ RTC_CLKIN TPM0_CH0 45 B6 23 35 B7 PTC2 ADC0_ SE11 ADC0_ SE11 PTC2 I2C1_SDA TPM0_CH1 46 B5 24 36 C8 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 SPI1_SCK 47 — — — E3 VSS VSS VSS 48 — — — E4 VDD VDD VDD 49 A6 25 37 B8 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 LPUART1_ TX 50 A5 26 38 A8 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK 51 B4 27 39 A7 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_MOSI EXTRG_IN SPI0_MISO 52 A4 28 40 B6 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO SPI0_MOSI 53 — — — A6 PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2C0_SCL TPM0_CH4 54 — — — B5 PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2C0_SDA TPM0_CH5 55 — — — B4 PTC10 DISABLED PTC10 I2C1_SCL 56 — — — A5 PTC11 DISABLED PTC11 I2C1_SDA 57 — — 41 C3 PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 FXIO0_D0 58 — — 42 A4 PTD1 ADC0_ SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 59 — — 43 C2 PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2 60 — — 44 B3 PTD3 DISABLED PTD3 SPI0_MISO UART2_TX 61 A3 29 45 A3 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_PCS0 UART2_RX TPM0_CH4 FXIO0_D4 62 B3 30 46 C1 PTD5 ADC0_ SE6b ADC0_ SE6b PTD5 SPI1_SCK FXIO0_D5 63 B2 31 47 B2 PTD6/ LLWU_P15 ADC0_ SE7b ADC0_ SE7b PTD6/ LLWU_P15 SPI1_MOSI LPUART0_ RX Kinetis KL17 Microcontroller, Rev. 5, 04/2015 ADC0_ SE5b LPUART1_ RX CMP0_OUT TPM0_CH2 CLKOUT TPM0_CH3 SPI1_PCS0 LPTMR0_ ALT2 UART2_TX ALT7 CMP0_OUT TPM0_CH3 SPI0_MOSI FXIO0_D3 TPM0_CH5 I2C1_SDA SPI1_MISO FXIO0_D6 29 Freescale Semiconductor, Inc. Pinouts 64 36 LQFP XFB GA 64 A2 32 QFN 48 QFN 64 MAP BGA 32 48 A2 Pin Name PTD7 Default ALT0 DISABLED ALT1 ALT2 PTD7 ALT3 ALT4 SPI1_MISO LPUART0_ TX ALT5 I2C1_SCL ALT6 ALT7 SPI1_MOSI FXIO0_D7 4.2 Pin properties Pin interrupt Open drain Passive pin filter after POR Slew rate after POR Pullup/ pulldown setting after POR Default status after POR Driver strength Pin name 64 MAPBGA 48 QFN 32 QFN 36 XFBGA 64 LQFP The following table lists the pin properties. — F2 9 — — VREF0 — — — — — — — — — — — C5 NC — — — — — — — 1 A1 1 — A1 PTE0 ND Hi-Z — FS N N Y 2 B1 2 — B1 PTE1 ND Hi-Z — FS N N Y 3 — — 1 — VDD — — — — — — — 4 C4 — 2 C4 VSS — — — — — — — 5 C2 3 3 E1 PTE16 ND Hi-Z — FS N N Y 6 C1 4 4 D1 PTE17 ND HI-Z — FS N N Y 7 D1 5 5 E2 PTE18 ND Hi-Z — FS N N Y 8 D2 6 6 D2 PTE19 ND HI-Z — FS N N Y 9 E3 — 7 G1 PTE20 ND Hi-Z — SS N N Y 10 E2 — 8 F1 PTE21 ND Hi-Z — SS N N Y 11 E1 — — G2 PTE22 ND Hi-Z — SS N N Y 12 F1 — — F2 PTE23 ND Hi-Z — SS N N Y 13 D3 7 9 F4 VDDA — — — — — — — 14 D3 7 10 G4 VREFH — — — — — — — 14 — — 10 G4 VREFO — — — — — — — 15 D4 8 11 G3 VREFL — — — — — — — 16 D4 8 12 F3 VSSA — — — — — — — 17 — — 13 H1 PTE29 ND Hi-Z — SS N N Y Table continues on the next page... 30 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pin interrupt Open drain Passive pin filter after POR Slew rate after POR Pullup/ pulldown setting after POR Default status after POR Driver strength Pin name 64 MAPBGA 48 QFN 32 QFN 36 XFBGA 64 LQFP Pinouts 18 F2 9 14 H2 PTE30 ND Hi-Z — SS N N Y 19 — — — H3 PTE31 ND Hi-Z — SS N N Y 20 — — 15 H4 PTE24 ND Hi-Z — SS N N Y 21 — — 16 H5 PTE25 ND Hi-Z — SS N N Y 22 F3 10 17 D3 PTA0 ND L PD SS N N Y 23 F4 11 18 D4 PTA1 ND Hi-Z — SS N N Y 24 E4 12 19 E5 PTA2 ND Hi-Z — SS N N Y 25 E5 13 20 D5 PTA3 ND H PU FS N N Y 26 F5 14 21 G5 PTA4 ND H PU SS Y N Y 27 — — — F5 PTA5 ND Hi-Z — SS N N Y 28 — — — H6 PTA12 ND Hi-Z — SS N N Y 29 — — — G6 PTA13 ND Hi-Z — SS N N Y 30 C3 15 22 G7 VDD ND — — — — — — 31 C4 16 23 H7 VSS ND — — — — — — 32 F6 17 24 H8 PTA18 ND Hi-Z — SS N N Y 33 E6 18 25 G8 PTA19 ND Hi-Z — SS N N Y 34 D5 19 26 F8 PTA20 ND H PU SS N Y Y 35 D6 20 27 F7 PTB0/LLWU_P5 HD Hi-Z — FS N N Y 36 C6 21 28 F6 PTB1 HD Hi-Z — FS N N Y 37 — — 29 E7 PTB2 ND Hi-Z — SS N N Y 38 — — 30 E8 PTB3 ND Hi-Z — SS N N Y 39 — — 31 E6 PTB16 ND Hi-Z — FS N N Y 40 — — 32 D7 PTB17 ND Hi-Z — FS N N Y 41 — — — D6 PTB18 ND Hi-Z — SS N N Y 42 — — — C7 PTB19 ND Hi-Z — SS N N Y 43 — — 33 D8 PTC0 ND Hi-Z — SS N N Y 44 C5 22 34 C6 PTC1/ LLWU_P6/ RTC_CLKIN ND Hi-Z — SS N N Y 45 B6 23 35 B7 PTC2 ND Hi-Z — SS N N Y Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 31 Freescale Semiconductor, Inc. Pin interrupt Open drain Passive pin filter after POR Slew rate after POR Pullup/ pulldown setting after POR Default status after POR Driver strength Pin name 64 MAPBGA 48 QFN 32 QFN 36 XFBGA 64 LQFP Pinouts 46 B5 24 36 C8 PTC3/ LLWU_P7 HD Hi-Z — FS N N Y 47 — — — E3 VSS — — — — — — — 48 — — — E4 VDD — — — — — — — 49 A6 25 37 B8 PTC4/ LLWU_P8 HD Hi-Z — FS N N Y 50 A5 26 38 A8 PTC5/ LLWU_P9 ND Hi-Z — FS N N Y 51 B4 27 39 A7 PTC6/ LLWU_P10 ND Hi-Z — FS N N Y 52 A4 28 40 B6 PTC7 ND Hi-Z — FS N N Y 53 — — — A6 PTC8 ND Hi-Z — SS N N Y 54 — — — B5 PTC9 ND Hi-Z — SS N N Y 55 — — — B4 PTC10 ND Hi-Z — SS N N Y 56 — — — A5 PTC11 ND Hi-Z — SS N N Y 57 — — 41 C3 PTD0 ND Hi-Z — FS N N Y 58 — — 42 A4 PTD1 ND Hi-Z — FS N N Y 59 — — 43 C2 PTD2 ND Hi-Z — FS N N Y 60 — — 44 B3 PTD3 ND Hi-Z — FS N N Y 61 A3 29 45 A3 PTD4/ LLWU_P14 ND Hi-Z — FS N N Y 62 B3 30 46 C1 PTD5 ND Hi-Z — FS N N Y 63 B2 31 47 B2 PTD6/ LLWU_P15 HD Hi-Z — FS N N Y 64 A2 32 48 A2 PTD7 HD Hi-Z — FS N N Y Properties Driver strength Default status after POR Abbreviation Descriptions ND Normal drive HD High drive Hi-Z High impendence Table continues on the next page... 32 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts Properties Pullup/ pulldown setting after POR Slew rate after POR Abbreviation Descriptions H High level L Low level PD Pullup PU Pulldown FS Fast slew rate SS Slow slew rate Passive Pin Filter after POR N Disabled Y Enabled Open drain N Disabled1 Y Enabled2 Y Yes Pin interrupt 1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain configurable. 2. PTA20 is a true open drain pin that must never be pulled above VDD. 4.3 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. 4.3.1 Core modules Table 9. SWD signal descriptions Chip signal name Module signal name SWD_DIO SWD_DIO Description I/O Serial Wire Debug Data Input/Output The SWD_DIO pin is used by an external debug tool for communication and device control. This pin is pulled up internally. SWD_CLK SWD_CLK Serial Wire Clock Input / Output Input This pin is the clock for debug logic when in the Serial Wire Debug mode. This pin is pulled down internally. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 33 Freescale Semiconductor, Inc. Pinouts 4.3.2 System modules Table 10. System signal descriptions Chip signal name Module signal name NMI — Description I/O Non-maskable interrupt I NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin. RESET — Reset bidirectional signal I/O VDD — MCU power I VSS — MCU ground I Table 11. LLWU signal descriptions Chip signal name Module signal name LLWU_Pn LLWU_Pn Description I/O Wakeup inputs (n = 5, 6, 7, 8, 9, 10, 14, 15) I 4.3.3 Clock modules Table 12. OSC signal descriptions Chip signal name Module signal name EXTAL0 EXTAL XTAL0 XTAL Description I/O External clock/Oscillator input I Oscillator output O 4.3.4 Analog This table presents the signal descriptions of the ADC0 module. Table 13. ADC0 signal descriptions Chip signal name Module signal name Description I/O ADC0_DPn DADP3–DADP0 Differential Analog Channel Inputs I ADC0_DMn DADM3–DADM0 Differential Analog Channel Inputs I ADC0_SEn ADn Single-Ended Analog Channel Inputs I VREFH VREFSH Voltage Reference Select High I Table continues on the next page... 34 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts Table 13. ADC0 signal descriptions (continued) Chip signal name Module signal name VREFL VREFSL VDDA VSSA EXTRG_IN ADHWT Description I/O Voltage Reference Select Low I VDDA Analog Power Supply I VSSA Analog Ground I Hardware trigger I This table presents the signal descriptions of the CMP0 module. Table 14. CMP0 signal descriptions Chip signal name Module signal name Description I/O CMP0_IN[5:0] IN[5:0] Analog voltage inputs I CMP0_OUT CMPO Comparator output O Table 15. VREF signal descriptions Chip signal name Module signal name Description I/O VREF_OUT VREF_OUT Internally-generated voltage reference output O 4.3.5 Timer Modules Table 16. TPM0 signal descriptions Chip signal name Module signal name Description TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. I TPM0_CH[5:0] TPM_CHn TPM channel (n = 5 to 0). A TPM channel pin is configured as output when configured in an output compare or PWM mode and the TPM counter is enabled, otherwise the TPM channel pin is an input. I/O Kinetis KL17 Microcontroller, Rev. 5, 04/2015 I/O 35 Freescale Semiconductor, Inc. Pinouts Table 17. TPM1 signal descriptions Chip signal name Module signal name Description I/O TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. I TPM1_CH[1:0] TPM_CHn TPM channel (n = 1 to 0). A TPM channel pin is configured as output when configured in an output compare or PWM mode and the TPM counter is enabled, otherwise the TPM channel pin is an input. I/O Table 18. TPM2 signal descriptions Chip signal name Module signal name Description I/O TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. I TPM2_CH[1:0] TPM_CHn TPM channel (n = 1 to 0). A TPM channel pin is configured as output when configured in an output compare or PWM mode and the TPM counter is enabled, otherwise the TPM channel pin is an input. I/O Table 19. LPTMR0 signal descriptions Chip signal name Module signal name Description LPTMR0_ALT[3:1] LPTMR0_ALTn Pulse Counter Input pin I/O I Table 20. RTC signal descriptions Chip signal name Module signal name Description I/O RTC_CLKOUT1 RTC_CLKOUT 1 Hz square-wave output or OSCERCLK O 1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL] 4.3.6 Communication interfaces Table 21. SPI0 signal descriptions Chip signal name Module signal name SPI0_MISO MISO Description I/O Master Data In, Slave Data Out I/O Table continues on the next page... 36 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts Table 21. SPI0 signal descriptions (continued) Chip signal name Module signal name SPI0_MOSI MOSI SPI0_SCLK SPSCK SPI0_PCS0 SS Description I/O Master Data Out, Slave Data In I/O SPI Serial Clock I/O Slave Select I/O Table 22. SPI1 signal descriptions Chip signal name Module signal name Description I/O SPI1_MISO MISO Master Data In, Slave Data Out I/O SPI1_MOSI MOSI Master Data Out, Slave Data In I/O SPI1_SCLK SPSCK SPI Serial Clock I/O SPI1_PCS0 SS Slave Select I/O Table 23. I2C0 signal descriptions Chip signal name Module signal name I2C0_SCL SCL I2C0_SDA Description I/O Bidirectional serial clock line of the I2C system. SDA Bidirectional serial data line of the I2C system. I/O I/O Table 24. I2C1 signal descriptions Chip signal name Module signal name I2C1_SCL SCL I2C1_SDA SDA Description I/O Bidirectional serial clock line of the I2C system. Bidirectional serial data line of the I2C system. I/O I/O Table 25. LPUART0 signal descriptions Chip signal name Module signal name Description I/O LPUART0_TX TxD Transmit data I/O LPUART0_RX RxD Receive data I Kinetis KL17 Microcontroller, Rev. 5, 04/2015 37 Freescale Semiconductor, Inc. Pinouts Table 26. LPUART1 signal descriptions Chip signal name Module signal name Description I/O LPUART1_TX TxD Transmit data I/O LPUART1_RX RxD Receive data I Table 27. UART2 signal descriptions Chip signal name Module signal name Description I/O UART2_TX TxD Transmit data O UART2_RX RxD Receive data I Table 28. FlexIO signal descriptions Chip signal name Module signal name FXIO0_Dx FXIO_Dn (n=0...7) Description Bidirectional FlexIO Shifter and Timer pin inputs/outputs I/O I/O 4.3.7 Human-machine interfaces (HMI) Table 29. GPIO Signal Descriptions Chip signal name Module signal name Description I/O PTA[31:0] PORTA31–PORTA0 General-purpose input/output I/O PTB[31:0] PORTB31–PORTB0 General-purpose input/output I/O PTC[11:0] PORTC11–PORTC0 General-purpose input/output I/O PTD[7:0] PORTD7–PORTD0 General-purpose input/output I/O PTE[31:0] PORTE31–PORTE0 General-purpose input/output I/O 4.4 KL17 Family Pinouts The figure below shows the 32 QFN pinouts. 38 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 32 31 30 29 28 27 26 25 Pinouts 4 21 PTB1 PTE18 5 20 PTB0/LLWU_P5 PTE19 6 19 PTA20 VDDA VREFH 7 18 PTA19 VREFL VSSA 8 17 PTA18 10 PTA0 VREF0 PTE30 16 PTE17 VSS PTC1/LLWU_P6/RTC_CLKIN 15 22 VDD 3 14 PTE16 PTA4 PTC2 13 23 PTA3 2 12 PTE1 PTA2 PTC3/LLWU_P7 11 24 PTA1 1 9 PTE0 Figure 6. 32 QFN Pinout diagram (transparent top view) The figure below shows the 48 QFN pinouts. NOTE The 48 QFN package for this product is not yet available. However, it is included in Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 39 Freescale Semiconductor, Inc. PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 48 47 46 45 44 43 42 41 40 39 38 37 Pinouts PTB16 PTE20 7 30 PTB3 PTE21 8 29 PTB2 VDDA 9 28 PTB1 VREFH VREFO 10 27 PTB0/LLWU_P5 VREFL 11 26 PTA20 VSSA 12 25 PTA19 PTA18 24 31 23 6 VSS PTE19 22 PTB17 VDD 32 21 5 PTA4 PTE18 20 PTC0 PTA3 33 19 4 PTA2 PTE17 18 PTC1/LLWU_P6/RTC_CLKIN PTA1 34 17 3 PTA0 PTE16 16 PTC2 PTE25 35 15 2 PTE24 VSS 14 PTC3/LLWU_P7 PTE30 36 13 1 PTE29 VDD Figure 7. 48 QFN Pinout diagram (transparent top view) The figure below shows the 64 MAPBGA pinouts. NOTE The 64 MAPBGA package for this product is not yet available. However, it is included in Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details. 40 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts 1 2 3 4 5 6 A PTE0 PTD7 PTD4/ LLWU_P14 PTD1 PTC11 PTC8 B PTE1 PTD6/ LLWU_P15 PTD3 PTC10 PTC9 PTC7 C PTD5 PTD2 PTD0 VSS NC D PTE17 PTE19 PTA0 PTA1 E PTE16 PTE18 VSS F PTE21 PTE23 G PTE20 H 7 8 PTC6/ PTC5/ LLWU_P10 LLWU_P9 A PTC2 PTC4/ LLWU_P8 B PTC1/ LLWU_P6/ RTC_CLKIN PTB19 PTC3/ LLWU_P7 C PTA3 PTB18 PTB17 PTC0 D VDD PTA2 PTB16 PTB2 PTB3 E VSSA VDDA PTA5 PTB1 PTB0/ LLWU_P5 PTA20 F PTE22 VREFL VREFH VREFO PTA4 PTA13 VDD PTA19 G PTE29 PTE30 PTE31 PTE24 PTE25 PTA12 VSS PTA18 H 1 2 3 4 5 6 7 8 Figure 8. 64 MAPBGA Pinout diagram (transparent top view) The figure below shows the 64 LQFP pinouts: Kinetis KL17 Microcontroller, Rev. 5, 04/2015 41 Freescale Semiconductor, Inc. PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinouts PTE20 9 40 PTB17 PTE21 10 39 PTB16 PTE22 11 38 PTB3 PTE23 12 37 PTB2 VDDA 13 36 PTB1 VREFH VREFO 14 35 PTB0/LLWU_P5 VREFL 15 34 PTA20 VSSA 16 33 PTA19 32 PTB18 PTA18 41 31 8 VSS PTE19 30 PTB19 VDD 42 29 7 PTA13 PTE18 28 PTC0 PTA12 43 27 6 PTA5 PTE17 26 PTC1/LLWU_P6/RTC_CLKIN PTA4 44 25 5 PTA3 PTE16 24 PTC2 PTA2 45 23 4 PTA1 VSS 22 PTC3/LLWU_P7 PTA0 46 21 3 PTE25 VDD 20 VSS PTE24 47 19 2 PTE31 PTE1 18 VDD PTE30 48 17 1 PTE29 PTE0 Figure 9. 64 LQFP Pinout diagram (top view) The figure below shows the 36 XFBGA pinouts: 42 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts 1 2 3 4 5 6 A PTE0 PTD7 PTD4/ LLWU_P14 PTC7 PTC5/ LLWU_P9 PTC4/ LLWU_P8 A B PTE1 PTD6/ LLWU_P15 PTD5 PTC2 B C PTE17 PTE16 VDD VSS PTC1/ LLWU_P6/ RTC_CLKIN PTB1 C D PTE18 PTE19 VDDA/ VREFH VREFL/ VSSA PTA20 PTB0/ LLWU_P5 D E PTE22 PTE21 PTE20 PTA2 PTA3 PTA19 E F PTE23 VREF0/ PTE30 PTA0 PTA1 PTA4 PTA18 F 1 2 3 4 5 6 PTC6/ PTC3/ LLWU_P10 LLWU_P7 Figure 10. 36 XFBGA Pinout diagram (transparent top view) 4.5 Package dimensions The following figures show the dimensions of the package options for the devices supported by this document. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 43 Freescale Semiconductor, Inc. Pinouts Figure 11. 64-pin LQFP package dimensions 1 44 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts Figure 12. 64-pin LQFP package dimensions 2 Kinetis KL17 Microcontroller, Rev. 5, 04/2015 45 Freescale Semiconductor, Inc. Pinouts Figure 13. 64-pin MAPBGA package dimension 46 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts Figure 14. 48-pin QFN package dimension 1 Kinetis KL17 Microcontroller, Rev. 5, 04/2015 47 Freescale Semiconductor, Inc. Pinouts Figure 15. 48-pin QFN package dimension 2 48 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Pinouts Figure 16. 36-pin XFBGA package dimension Kinetis KL17 Microcontroller, Rev. 5, 04/2015 49 Freescale Semiconductor, Inc. Pinouts Figure 17. 32-pin QFN package dimension 1 50 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Figure 18. 32-pin QFN package dimension 2 5 Electrical characteristics 5.1 Ratings Kinetis KL17 Microcontroller, Rev. 5, 04/2015 51 Freescale Semiconductor, Inc. Electrical characteristics 5.1.1 Thermal handling ratings Table 30. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.1.2 Moisture handling ratings Table 31. Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.1.3 ESD handling ratings Table 32. ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model –500 +500 V 2 Latch-up current at ambient temperature of 105 °C –100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 5.1.4 Voltage and current absolute operating ratings Table 33. Voltage and current absolute operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA Table continues on the next page... 52 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Table 33. Voltage and current absolute operating ratings (continued) Symbol VIO ID VDDA Description Min. Max. Unit IO pin input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDD – 0.3 VDD + 0.3 V Analog supply voltage 5.2 General 5.2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Input Signal High Low VIH 80% 50% 20% Midpoint1 VIL Fall Time Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 19. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume that the output pins have the following characteristics. • CL=30 pF loads • Slew rate disabled • Normal drive strength 5.2.2 Nonswitching electrical specifications Kinetis KL17 Microcontroller, Rev. 5, 04/2015 53 Freescale Semiconductor, Inc. Electrical characteristics 5.2.2.1 Voltage and current operating requirements Table 34. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V 0.06 × VDD — V -3 — mA -25 — mA VIH VIL Input high voltage Input low voltage VHYS Input hysteresis IICIO IO pin negative DC injection current — single pin 1 • VIN < VSS-0.3V IICcont Notes Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins • Negative current injection VODPU Open drain pullup voltage level VDD VDD V VRAM VDD voltage required to retain RAM 1.2 — V 2 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD. 5.2.2.2 Symbol LVD and POR operating requirements Table 35. VDD supply LVD and POR operating requirements Description Min. Typ. Max. Unit Notes VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V — VLVDH Falling low-voltage detect threshold — high range (LVDV = 01) 2.48 2.56 2.64 V — Low-voltage warning thresholds — high range VLVW1H • Level 1 falling (LVWV = 00) VLVW2H • Level 2 falling (LVWV = 01) VLVW3H 1 2.62 2.70 2.78 V 2.72 2.80 2.88 V 2.82 2.90 2.98 V Table continues on the next page... 54 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Table 35. VDD supply LVD and POR operating requirements (continued) Symbol VLVW4H Description • Level 3 falling (LVWV = 10) Min. Typ. Max. Unit 2.92 3.00 3.08 V Notes — ±60 — mV — 1.54 1.60 1.66 V — • Level 4 falling (LVWV = 11) VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) Low-voltage warning thresholds — low range VLVW1L • Level 1 falling (LVWV = 00) VLVW2L • Level 2 falling (LVWV = 01) VLVW3L • Level 3 falling (LVWV = 10) VLVW4L • Level 4 falling (LVWV = 11) VHYSL Low-voltage inhibit reset/recover hysteresis — low range 1 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.16 V — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage 5.2.2.3 Symbol VOH VOH Voltage and current operating behaviors Table 36. Voltage and current operating behaviors Description Min. VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA VDD – 0.5 — V Output high voltage — high drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA VDD – 0.5 — V — 100 mA VOL Output low voltage — normal drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — 0.5 V Output low voltage — high drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — 0.5 V — 100 mA Output low current total for all ports Notes 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA Output high current total for all ports IOLT Unit Output high voltage — normal drive pad IOHT VOL Max. Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 55 Freescale Semiconductor, Inc. Electrical characteristics Table 36. Voltage and current operating behaviors (continued) Symbol Description Min. Max. Unit Notes IIN Input leakage current (per pin) for full temperature range — 1 μA 2 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 2 IIN Input leakage current (total all pins) for full temperature range — 64 μA 2 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 3 1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD = 3.6 V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS 5.2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx → RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • HIRC clock mode Table 37. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit — — 300 μs — 152 166 μs — 152 166 μs — 93 104 μs — 7.5 8 μs — 7.5 8 μs — 7.5 8 μs Notes • VLLS0 → RUN • VLLS1 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN 56 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics 5.2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent the characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). NOTE The while(1) test is executed with flash cache enabled. Table 38. Power consumption operating behaviors Symbol IDDA Description Analog supply current IDD_RUNCO Running CoreMark in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V • at 25 °C Min. Typ. Max. Unit Notes — — See note mA 1 2 — • at 105 °C IDD_RUNCO Running While(1) loop in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V • at 25 °C — • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C IDD_RUN 4.79 4.98 4.94 5.14 2.73 2.87 2.9 3.05 mA mA 2 — 5.45 5.67 — 5.6 5.82 mA Run mode current—48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V 2 • at 25 °C • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 12 MHz core/6 MHz flash, VDD = 3.0 V • at 25 °C — 3.41 3.55 mA — 3.56 3.70 mA 2 — • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C • at 105 °C 2.37 2.49 2.52 2.65 mA 2 — 7.05 7.33 7.2 7.49 mA Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 57 Freescale Semiconductor, Inc. Electrical characteristics Table 38. Power consumption operating behaviors (continued) Symbol Description IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in flash all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C Min. Typ. Max. Unit — 3.39 3.53 mA 3.57 3.71 2.36 2.48 2.53 2.66 1.84 1.93 2 2.10 4.98 5.18 5.16 5.37 Notes • at 105 °C IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V • at 25 °C — mA • at 105 °C IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V • at 25 °C — • at 105 °C IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V • at 25 °C — mA mA • at 105 °C IDD_VLPRCO Very-low-power run core mark in flash in compute operation mode— 8 MHz LIRC mode, 4 MHz core/1 MHz flash, VDD = 3.0 V • at 25 °C — 710 752.6 μA IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in compute operation mode— 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C — 251 376.5 μA IDD_VLPRCO Very-low-power run While(1) loop in SRAM in compute operation mode:—2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C — 115 143.75 μA — 91 136.5 μA — 34 51 μA IDD_VLPR IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V • at 25 °C Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V • at 25 °C Table continues on the next page... 58 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Table 38. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C — 212 318 μA — 302 392.6 μA — 1.81 2.12 mA — 1.27 1.46 mA IDD_VLPW Very-low-power wait mode current, core disabled, 4 MHz system/ 1 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V • at 25 °C — 156 193.2 μA IDD_VLPW Very-low-power wait mode current, core disabled, 2 MHz system/ 0.5 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V • at 25 °C — 63 100.8 μA IDD_VLPW Very-low-power wait mode current, core disabled, 125 kHz system/ 31.25 kHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V • at 25 °C — 32 48 μA — 1.68 2.05 mA — 1.05 1.26 mA — 158.1 175.81 — 171 180.24 — 203.8 228.64 — 251.7 300.06 IDD_VLPR IDD_WAIT IDD_WAIT Very-low-power run mode current—8 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V • at 25 °C Wait mode current—core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V • at 25 °C Wait mode current—core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V • at 25 °C Notes IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12 MHz bus and flash, VDD = 3.0 V • at 25 °C IDD_PSTOP2 Partial Stop 2, core and system clock disabled, flash doze enabled, 12 MHz bus, VDD = 3.0 V • at 25 °C IDD_STOP Stop mode current at 3.0 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C μA Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 59 Freescale Semiconductor, Inc. Electrical characteristics Table 38. Power consumption operating behaviors (continued) Symbol Description IDD_VLPS Very-low-power stop mode current at 3.0 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C IDD_VLPS Very-low-power stop mode current at 1.8 V • at 25 °C and below • at 50 °C • at 85 °C • at 105 °C IDD_LLS Low-leakage stop mode current, all peripheral disable, at 3.0 V • at 25 °C and below • at 50 °C • at 70 °C • at 85 °C • at 105 °C IDD_LLS Low-leakage stop mode current with RTC current, at 3.0 V • at 25 °C and below • at 50 °C • at 70 °C • at 85 °C • at 105 °C IDD_LLS Low-leakage stop mode current with RTC current, at 1.8 V • at 25 °C and below • at 50 °C • at 70 °C • at 85 °C • at 105 °C IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V • at 25 °C and below • at 50 °C • at 70 °C Min. Typ. Max. — 2.34 3.80 — 5.04 8.03 — 20.48 31.97 — 42.34 65.78 — 2.33 3.80 — 4.95 7.94 — 20.18 31.57 — 41.93 65.17 — 1.71 1.96 — 2.59 3.30 — 4.46 7.06 — 7.55 10.15 — 17.03 22.67 Unit Notes μA μA μA 3 — 2.27 2.52 — 3.1 3.81 — 4.99 7.59 — 8.1 10.70 — 17.32 22.96 μA 3 — 2.1 2.35 — 2.89 3.60 — 4.65 7.25 — 7.61 10.21 — 16.38 22.02 — 1.43 1.58 — 2.06 2.52 — 3.51 5.20 — 5.91 7.60 — 13.36 17.08 μA μA Table continues on the next page... 60 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Table 38. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes • at 85 °C • at 105 °C IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V • at 25 °C and below • at 50 °C • at 70 °C • at 85 °C • at 105 °C IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 1.8 V • at 25 °C and below • at 50 °C • at 70 °C • at 85 °C • at 105 °C IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V • at 25 °C and below • at 50°C • at 70°C • at 85°C • at 105 °C IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V • at 25 °C and below • at 50°C • at 70°C • at 85°C • at 105 °C IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V • at 25 °C and below • at 50°C • at 70°C • at 85°C • at 105 °C 3 — 1.83 1.98 — 2.47 2.93 — 3.96 5.65 — 6.44 8.13 — 13.84 17.56 μA 3 — 1.68 1.83 — 2.27 2.73 — 3.66 5.35 — 5.97 7.66 — 12.92 16.64 — 0.84 1.06 — 1.19 1.33 — 2.03 2.62 — 3.54 4.13 — 8.53 9.98 μA μA 3 — 1.26 1.48 — 1.61 1.75 — 2.5 3.09 — 4.07 4.66 — 9 10.45 μA 3 — 1.08 1.30 — 1.42 1.56 — 2.21 2.80 — 3.59 4.18 — 8.02 9.47 μA Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 61 Freescale Semiconductor, Inc. Electrical characteristics Table 38. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. — 262 360 — 593 725 • at 50 °C — 1430 2014 • at 70 °C — 2930 3514 7930 9895 IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V • at 25 °C and below • at 85 °C Unit Notes nA • at 105 °C IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 1) at 3 V • at 25 °C and below 4 — 87 185 — 417 549 • at 50 °C — 1230 1230 • at 70 °C — 2720 3304 7780 9745 • at 85 °C nA • at 105 °C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high, optimized for balanced. 3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption. 4. No brownout Table 39. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 IIRC8MHz 8 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 8 MHz IRC enabled, MCG_SC[FCRDIV]=000b, MCG_MC[LIRC_DIV2]=000b. 77 77 77 77 77 77 µA IIRC2MHz 2 MHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 2 MHz IRC enabled, MCG_SC[FCRDIV]=000b, MCG_MC[LIRC_DIV2]=000b. 25 25 25 25 25 25 µA IEREFSTEN4MHz [C: ] External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 224 230 238 245 253 µA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by 440 490 540 560 570 580 Table continues on the next page... 62 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Table 39. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) entering all modes with the crystal enabled. • VLLS1 • VLLS3 • LLS • VLPS • STOP ILPTMR Unit -40 25 50 70 85 105 440 490 540 560 570 580 490 490 540 560 570 680 510 560 560 560 610 680 510 560 560 560 610 680 30 30 30 85 100 200 nA LPTMR peripheral adder measured by placing the device in VLLS1 mode with LPTMR enabled using LPO. nA ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 16 16 16 16 16 16 µA IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 430 500 500 530 530 760 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. • IRC8M (8 MHz internal reference clock) • IRC2M (2 MHz internal reference clock) 96 96 96 96 96 96 µA 31 31 31 31 31 31 ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. • IRC8M (8 MHz internal reference clock) • IRC2M (2 MHz internal reference clock) µA 130 130 130 130 130 130 Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 63 Freescale Semiconductor, Inc. Electrical characteristics Table 39. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 40 40 40 40 40 40 IBG Bandgap adder when BGEN bit is set and device is placed in VLPx or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 320 320 320 320 320 320 µA 5.2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • • • • MCG-Lite in HIRC for run mode, and LIRC for VLPR mode No GPIOs toggled Code execution from flash For the ALLOFF curve, all peripheral clocks are disabled except FTFA 64 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Figure 20. Run mode supply current vs. core frequency Kinetis KL17 Microcontroller, Rev. 5, 04/2015 65 Freescale Semiconductor, Inc. Electrical characteristics 66 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Figure 21. VLPR mode current vs. core frequency 5.2.2.6 EMC performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components, and MCU software operation play a significant role in the EMC performance. The system designer can consult the following Freescale applications notes, available on freescale.com for advice and guidance specifically targeted at optimizing EMC performance. • AN2321: Designing for Board Level Electromagnetic Compatibility • AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers • AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers • AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications Kinetis KL17 Microcontroller, Rev. 5, 04/2015 67 Freescale Semiconductor, Inc. Electrical characteristics • AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems • KL-QRUG (Kinetis L-series Quick Reference). 5.2.2.7 Symbol CIN Capacitance attributes Table 40. Capacitance attributes Description Input capacitance Min. Max. Unit — 7 pF Min. Max. Unit 5.2.3 Switching specifications 5.2.3.1 Symbol Device clock specifications Table 41. Device clock specifications Description Normal run mode fSYS System and core clock — 48 MHz fBUS Bus clock — 24 MHz fFLASH Flash clock — 24 MHz fLPTMR LPTMR clock — 24 MHz VLPR and VLPS modes1 fSYS System and core clock — 4 MHz fBUS Bus clock — 1 MHz fFLASH Flash clock — 1 MHz fLPTMR LPTMR clock2 — 24 MHz fERCLK External reference clock — 16 MHz — 16 MHz Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) — 16 MHz TPM asynchronous clock — 8 MHz UART0 asynchronous clock — 8 MHz fLPTMR_ERCLK LPTMR external reference clock fosc_hi_2 fTPM fUART0 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 68 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics 5.2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 42. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1 External RESET and NMI pin interrupt pulse width — Asynchronous path 100 — ns 2 GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2 Port rise and fall time — 36 ns 3 1. The synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 5.2.4 Thermal specifications 5.2.4.1 Symbol Thermal operating requirements Table 43. Thermal operating requirements Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + RθJA × chip power dissipation. 5.2.4.2 Thermal attributes NOTE The 48 QFN and 64 MAPBGA packages for this product are not yet available. However, it is included in Package Your Way program for Kinetis MCUs. Visit freescale.com/ KPYW for more details. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 69 Freescale Semiconductor, Inc. Electrical characteristics Table 44. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 32 QFN 36 XFBGA 64 LQFP Unit Notes Thermal resistance, junction to ambient (natural convection) 101 81.5 71 °C/W 1, 2, 3 RθJA Thermal resistance, junction to ambient (natural convection) 33 54.7 53 °C/W 1, 2, 3,4 Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 84 71.3 60 °C/W 1, 4, 5 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 28 50.0 47 °C/W 1, 4, 5 — RθJB Thermal resistance, junction to board 13 58.0 35 °C/W 6 — RθJC Thermal resistance, junction to case 1.7 45.3 21 °C/W 7 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 3 1.2 5 °C/W 8 — ΨJB Thermal characterization parameter, junction to package bottom (natural convection) - 44.5 - °C/W 9 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. 4. Per JEDEC JESD51-6 with the board horizontal. 5. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. 6. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 7. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 8. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 9. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. 5.3 Peripheral operating requirements and behaviors 5.3.1 Core modules 70 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics 5.3.1.1 Symbol J1 SWD electricals Table 45. SWD full voltage range electricals Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 25 MHz 1/J1 — ns 20 — ns SWD_CLK frequency of operation • Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width • Serial wire debug J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 22. Serial wire clock input timing Kinetis KL17 Microcontroller, Rev. 5, 04/2015 71 Freescale Semiconductor, Inc. Electrical characteristics SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 23. Serial wire data timing 5.3.2 System modules There are no specifications necessary for the device's system modules. 5.3.3 Clock modules 5.3.3.1 MCG-Lite specifications Table 46. IRC48M specifications Symbol Description Min. Typ. Max. Unit IDD48M Supply current — 400 500 μA firc48m Internal reference frequency — 48 — MHz — ± 0.5 ± 1.5 %firc48m Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at low voltage (VDD=1.71V-1.89V) over temperature Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over temperature Jcyc_irc48m tirc48mst 1 — ± 0.5 ± 1.0 %firc48m Period Jitter (RMS) — 35 150 ps Startup time — 2 3 μs 72 Freescale Semiconductor, Inc. Notes 2 Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics 1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard deviation (mean±3 sigma). 2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings: • MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10, or • SIM_SOPT2[PLLFLLSEL]=11 Table 47. IRC8M/2M specification Symbol Description Min. Typ. Max. Unit Notes IDD_2M Supply current in 2 MHz mode — 14 17 µA — IDD_8M Supply current in 8 MHz mode — 30 35 µA — fIRC_2M Output frequency — 2 — MHz — fIRC_8M Output frequency — 8 — MHz — fIRC_T_2M Output frequency range (trimmed) — — ±3 %fIRC — fIRC_T_8M Output frequency range (trimmed) — — ±3 %fIRC — Tsu_2M Startup time — — 12.5 µs — Tsu_8M Startup time — — 12.5 µs — 5.3.3.2 5.3.3.2.1 Oscillator electrical specifications Oscillator DC electrical specifications Table 48. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Supply current — high gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 73 Freescale Semiconductor, Inc. Electrical characteristics Table 48. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, lowpower mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V RS 2, 4 Series resistor — high-frequency, high-gain mode (HGO=1) 5 Vpp 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 74 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics 5.3.3.2.2 Symbol Oscillator frequency specifications Table 49. Oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — high-frequency mode (low range) (MCG_C2[RANGE]=01) 3 — 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz fec_extal Input clock frequency (external clock mode) — — 48 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 750 — ms Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — 250 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms fosc_lo tcst Description Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 5.3.4 Memories and memory interfaces 5.3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 5.3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 75 Freescale Semiconductor, Inc. Electrical characteristics Table 50. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes thvpgm4 Longword Program high-voltage time — 7.5 18 μs — thversscr Sector Erase high-voltage time — 13 113 ms 1 thversall Erase All high-voltage time — 52 452 ms 1 1. Maximum time based on expectations at cycling end-of-life. 5.3.4.1.2 Flash timing specifications — commands Table 51. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersscr Erase Flash Sector execution time — 14 114 ms 2 trd1all Read 1s All Blocks execution time — — 0.9 ms 1 trdonce Read Once execution time — — 25 μs 1 Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 70 575 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 70 575 ms 2 tpgmonce 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 5.3.4.1.3 Flash high voltage current behaviors Table 52. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 5.3.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 2.5 6.0 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 53. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash Table continues on the next page... 76 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics Table 53. NVM reliability specifications (continued) Min. Typ.1 Max. Unit Notes tnvmretp10k Data retention after up to 10 K cycles 5 50 — years — tnvmretp1k Data retention after up to 1 K cycles 20 100 — years — nnvmcycp Cycling endurance 10 K 50 K — cycles 2 Symbol Description 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C. 5.3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 5.3.6 Analog 5.3.6.1 ADC electrical specifications Using differential inputs can achieve better system accuracy than using single-end inputs. 5.3.6.1.1 16-bit ADC operating conditions Table 54. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 — 3.6 V — ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VADIN Input voltage • 16-bit differential mode VREFL — 31/32 × VREFH V — • All other modes VREFL — • 16-bit mode — 8 10 pF — • 8-bit / 10-bit / 12-bit modes — 4 5 — 2 5 kΩ — CADIN RADIN RAS Input capacitance Input series resistance Analog source resistance (external) VREFH 13-bit / 12-bit modes fADCK < 4 MHz 3 — — 5 kΩ Table continues on the next page... Kinetis KL17 Microcontroller, Rev. 5, 04/2015 77 Freescale Semiconductor, Inc. Electrical characteristics Table 54. 16-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes fADCK ADC conversion ≤ 13-bit mode clock frequency 1.0 — 18.0 MHz 4 fADCK ADC conversion 16-bit mode clock frequency 2.0 — 12.0 MHz 4 Crate ADC conversion ≤ 13-bit modes rate No ADC hardware averaging 5 20.000 — 818.330 ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion 16-bit mode rate No ADC hardware averaging 5 37.037 — 461.467 ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE VADIN CAS VAS RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 24. ADC input impedance equivalency diagram 78 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev. 5, 04/2015 Electrical characteristics 5.3.6.1.2 16-bit ADC electrical characteristics Table 55. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA5 IDDA_ADC Supply current fADACK ADC asynchronous clock source Sample Time TUE DNL See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±2 ±6.8 •