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MKL25Z32VFM4

MKL25Z32VFM4

  • 厂商:

    NXP(恩智浦)

  • 封装:

    VFQFN32_EP

  • 描述:

    IC MCU 32BIT 32KB FLASH 32QFN

  • 数据手册
  • 价格&库存
MKL25Z32VFM4 数据手册
Freescale Semiconductor, Inc. Data Sheet: Technical Data Document Number: KL25P80M48SF0 Rev 5 08/2014 Kinetis KL25 Sub-Family MKL25ZxxVFM4 MKL25ZxxVFT4 MKL25ZxxVLH4 MKL25ZxxVLK4 48 MHz Cortex-M0+ Based Microcontroller with USB Designed with efficiency in mind. Compatible with all other Kinetis L families as well as Kinetis K2x family. General purpose MCU with USB 2.0, featuring market leading ultra low-power to provide developers an appropriate entry-level 32-bit solution. This product offers: • Run power consumption down to 47 μA/MHz in very low power run mode • Static power consumption down to 2 μA with full state retention and 4 μs wakeup • Ultra-efficient Cortex-M0+ processor running up to 48 MHz with industry leading throughput • Memory option is up to 128 KB flash and 16 KB RAM • Energy-saving architecture is optimized for low power with 90 nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller Performance • 48 MHz ARM® Cortex®-M0+ core Memories and memory interfaces • Up to 128 KB program flash memory • Up to 16 KB SRAM 32-pin QFN (FM) 48-pin QFN (FT) 5 x 5 x 1 Pitch 0.5 mm 7 x 7 x 1 Pitch 0.5 mm 64-pin LQFP (LH) 80-pin LQFP (LK) 10 x 10 x 1.4 Pitch 0.5 12 x 12 x 1.4 Pitch 0.5 mm mm Human-machine interface • Low-power hardware touch sensor interface (TSI) • Up to 66 general-purpose input/output (GPIO) Communication interfaces • USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator • Two 8-bit SPI modules • One low power UART module • Two UART modules • Two I2C module System peripherals • Nine low-power modes to provide power optimization based on application requirements • COP Software watchdog • 4-channel DMA controller, supporting up to 63 request Analog Modules sources • Low-leakage wakeup unit • 16-bit SAR ADC • SWD debug interface and Micro Trace Buffer • 12-bit DAC • Bit Manipulation Engine • Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Clocks • 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator Timers • Multi-purpose clock source • Six channel Timer/PWM (TPM) • 1 kHz LPO clock • Two 2-channel Timer/PWM modules • Periodic interrupt timers Operating Characteristics • 16-bit low-power timer (LPTMR) • Voltage range: 1.71 to 3.6 V • Real time clock Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2014 Freescale Semiconductor, Inc. All rights reserved. Security and integrity modules • 80-bit unique identification number per chip • Flash write voltage range: 1.71 to 3.6 V • Temperature range (ambient): -40 to 105°C Ordering Information 1 Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL25Z32VFM4 32 4 23 MKL25Z64VFM4 64 8 23 MKL25Z128VFM4 128 16 23 MKL25Z32VFT4 32 4 36 MKL25Z64VFT4 64 8 36 MKL25Z128VFT4 128 16 36 MKL25Z32VLH4 32 4 50 MKL25Z64VLH4 64 8 50 MKL25Z128VLH4 128 16 50 MKL25Z32VLK4 32 4 66 MKL25Z64VLK4 64 8 66 MKL25Z128VLK4 128 16 66 1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number search. Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to KL2 Family Product Brief1 enable quick evaluation of a device for design suitability. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL25P80M48SF0RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. KL25P80M48SF01 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KINETIS_L_xN97F2 Package drawing Package dimensions are provided in package drawings. QFN 32-pin: 98ASA00473D1 QFN 48-pin: 98ASA00466D1 LQFP 64-pin: 98ASS23234W1 LQFP 80-pin: 98ASS23174W1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x” replaced by the revision of the device you are using. Figure 1 shows the functional modules in the chip. 2 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. Kinetis KL25 Family ARM ® Cortex™-M0+ Core System Internal watchdog Debug interfaces Memories and Memory Interfaces Program flash Phaselocked loop Frequencylocked loop DMA Interrupt controller Clocks RAM Low/high frequency oscillator BME MTB Internal reference clocks Security Analog Timers Internal watchdog 16-bit ADC x1 Timers 1x6ch+2x2ch Analog comparator x1 Low power timer x1 and Integrity 6-bit DAC 12-bit DAC Periodic interrupt timers Communication Interfaces Human-Machine Interface (HMI) GPIOs with interrupt 2 I C x2 Low power UART x1 TSI SPI x2 RTC UART x2 USB LS/FS x1 Migration difference from KL15 family LEGEND Figure 1. Functional block diagram Kinetis KL25 Sub-Family, Rev5 08/2014. 3 Freescale Semiconductor, Inc. Table of Contents 1 Ratings.................................................................................... 5 1.1 Thermal handling ratings................................................. 5 1.2 Moisture handling ratings................................................ 5 1.3 ESD handling ratings....................................................... 5 1.4 Voltage and current operating ratings............................. 5 2 General................................................................................... 6 2.1 AC electrical characteristics.............................................6 2.2 Nonswitching electrical specifications..............................7 2.2.1 Voltage and current operating requirements....... 7 2.2.2 LVD and POR operating requirements................7 2.2.3 Voltage and current operating behaviors.............8 2.2.4 Power mode transition operating behaviors........ 9 2.2.5 Power consumption operating behaviors............ 10 2.2.6 EMC radiated emissions operating behaviors..... 16 2.2.7 Designing with radiated emissions in mind..........17 2.2.8 Capacitance attributes.........................................17 2.3 Switching specifications...................................................17 2.3.1 Device clock specifications..................................17 2.3.2 General switching specifications......................... 18 2.4 Thermal specifications..................................................... 18 2.4.1 Thermal operating requirements......................... 18 2.4.2 Thermal attributes................................................19 3 Peripheral operating requirements and behaviors.................. 19 3.1 Core modules.................................................................. 19 3.1.1 SWD electricals .................................................. 19 3.2 System modules.............................................................. 21 3.3 Clock modules................................................................. 21 3.3.1 MCG specifications..............................................21 3.3.2 Oscillator electrical specifications........................23 3.4 Memories and memory interfaces................................... 25 3.4.1 Flash electrical specifications.............................. 25 3.5 Security and integrity modules........................................ 27 3.6 Analog............................................................................. 27 3.6.1 3.6.2 ADC electrical specifications............................... 27 CMP and 6-bit DAC electrical specifications....... 32 4 Freescale Semiconductor, Inc. 4 5 6 7 8 3.6.3 12-bit DAC electrical characteristics....................33 3.7 Timers..............................................................................36 3.8 Communication interfaces............................................... 36 3.8.1 USB electrical specifications............................... 36 3.8.2 USB VREG electrical specifications.................... 37 3.8.3 SPI switching specifications................................ 37 3.8.4 Inter-Integrated Circuit Interface (I2C) timing...... 42 3.8.5 UART...................................................................43 3.9 Human-machine interfaces (HMI)....................................43 3.9.1 TSI electrical specifications................................. 43 Dimensions............................................................................. 44 4.1 Obtaining package dimensions....................................... 44 Pinout...................................................................................... 44 5.1 KL25 Signal Multiplexing and Pin Assignments...............44 5.2 KL25 pinouts....................................................................47 Ordering parts......................................................................... 51 6.1 Determining valid orderable parts....................................51 Part identification.....................................................................51 7.1 Description.......................................................................52 7.2 Format............................................................................. 52 7.3 Fields............................................................................... 52 7.4 Example...........................................................................52 Terminology and guidelines.................................................... 53 8.1 Definition: Operating requirement....................................53 8.2 Definition: Operating behavior......................................... 53 8.3 Definition: Attribute.......................................................... 54 8.4 Definition: Rating............................................................. 54 8.5 Result of exceeding a rating............................................ 54 8.6 Relationship between ratings and operating requirements....................................................................55 8.7 Guidelines for ratings and operating requirements..........55 8.8 Definition: Typical value...................................................56 8.9 Typical value conditions.................................................. 57 9 Revision history.......................................................................57 Kinetis KL25 Sub-Family, Rev5 08/2014. Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2. Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 3. ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model –500 +500 V 2 Latch-up current at ambient temperature of 105 °C –100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. Kinetis KL25 Sub-Family, Rev5 08/2014. 5 Freescale Semiconductor, Inc. General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA VIO IO pin input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA ID VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage –0.3 3.63 V VUSB_DM USB_DM input voltage –0.3 3.63 V USB regulator input –0.3 6.0 V VREGIN 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal Low High 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. • CL=30 pF loads • Slew rate disabled • Normal drive strength 6 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. General 2.2 Nonswitching electrical specifications 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V — VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V — VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V — VIH VIL Input high voltage — • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V Input low voltage — • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V 0.06 × VDD — V –3 — mA VHYS Input hysteresis IICIO IO pin negative DC injection current—single pin — 1 • VIN < VSS–0.3V IICcont Notes Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins • Negative current injection — –25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V — 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 6. VDD supply LVD and POR operating requirements Symbol VPOR Description Min. Typ. Max. Unit Notes Falling VDD POR detect voltage 0.8 1.1 1.5 V — Table continues on the next page... Kinetis KL25 Sub-Family, Rev5 08/2014. 7 Freescale Semiconductor, Inc. General Table 6. VDD supply LVD and POR operating requirements (continued) Symbol VLVDH Description Min. Typ. Max. Unit Notes Falling low-voltage detect threshold — high range (LVDV = 01) 2.48 2.56 2.64 V — Low-voltage warning thresholds — high range VLVW1H • Level 1 falling (LVWV = 00) VLVW2H • Level 2 falling (LVWV = 01) VLVW3H • Level 3 falling (LVWV = 10) VLVW4H • Level 4 falling (LVWV = 11) VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1 2.62 2.70 2.78 V 2.72 2.80 2.88 V 2.82 2.90 2.98 V 2.92 3.00 3.08 V — ±60 — mV — 1.54 1.60 1.66 V — Low-voltage warning thresholds — low range VLVW1L • Level 1 falling (LVWV = 00) VLVW2L • Level 2 falling (LVWV = 01) VLVW3L • Level 3 falling (LVWV = 10) VLVW4L • Level 4 falling (LVWV = 11) VHYSL Low-voltage inhibit reset/recover hysteresis — low range 1 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.16 V — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 7. Voltage and current operating behaviors Symbol VOH Description Min. • 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA Output high current total for all ports Notes 1, 2 VDD – 0.5 — V VDD – 0.5 — V Output high voltage — High drive pad (except RESET) • 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA IOHT Unit Output high voltage — Normal drive pad (except RESET) • 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA VOH Max. 1, 2 VDD – 0.5 — V VDD – 0.5 — V — 100 mA — Table continues on the next page... 8 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. General Table 7. Voltage and current operating behaviors (continued) Symbol VOL VOL Description Min. Max. Unit Notes Output low voltage — Normal drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — 0.5 V Output low voltage — High drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA — 0.5 V Output low current total for all ports — 100 mA — IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 65 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA — RPU Internal pullup resistors 20 50 kΩ 4 RPD Internal pulldown resistors 20 50 kΩ 5 IOLT 1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 5. Measured at VDD supply voltage = VDD min and Vinput = VDD 2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz. Table 8. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first Min. Typ. Max. Unit — — 300 μs 1 Table continues on the next page... Kinetis KL25 Sub-Family, Rev5 08/2014. 9 Freescale Semiconductor, Inc. General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit — 95 115 μs — 93 115 μs — 42 53 μs — 4 4.6 μs — 4 4.4 μs — 4 4.4 μs instruction across the operating temperature range of the chip. • VLLS0 → RUN • VLLS1 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors Symbol IDDA Description Temp. Typ. Max Unit Note Analog supply current — — See note mA 1 IDD_RUNCO_ CM Run mode current in compute operation - 48 MHz core / 24 MHz flash/ bus disabled, LPTMR running using 4 MHz internal reference clock, CoreMark® benchmark code executing from flash, at 3.0 V — 6.4 — mA 2 IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash, at 3.0 V — 3.9 4.8 mA 3 IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V — 5 5.9 mA 3 Table continues on the next page... 10 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. General Table 9. Power consumption operating behaviors (continued) Symbol Description IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 V Temp. Typ. Max Unit Note at 25 °C 6.2 6.5 mA 3, 4 at 125 °C 6.8 7.1 mA IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V — 3.1 3.8 mA 3 IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V — 2.4 3.2 mA 3 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus, at 3.0 V — 1.6 2 mA 3 Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, LPTMR running with 4 MHz internal reference clock, CoreMark benchmark code executing from flash, at 3.0 V — 777 — µA 5 IDD_VLPRCO Very low power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code executing from flash, at 3.0 V — 171 420 µA 6 IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V — 204 449 µA 6 IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 V — 262 509 µA 4, 6 IDD_VLPW Very low power wait mode current core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V — 123 366 µA 6 IDD_STOP Stop mode current at 3.0 V at 25 °C 319 343 µA — at 50 °C 333 365 µA at 70 °C 353 400 µA at 85 °C 380 450 µA at 105 °C 444 572 µA at 25 °C 3.75 8.46 µA at 50 °C 6.66 13.41 µA at 70 °C 12.9 25.71 µA IDD_PSTOP2 IDD_VLPRCO _CM IDD_VLPS Very-low-power stop mode current at 3.0 V — Table continues on the next page... Kinetis KL25 Sub-Family, Rev5 08/2014. 11 Freescale Semiconductor, Inc. General Table 9. Power consumption operating behaviors (continued) Symbol IDD_LLS IDD_VLLS3 IDD_VLLS1 IDD_VLLS0 IDD_VLLS0 Description Low leakage stop mode current at 3.0 V Very low-leakage stop mode 3 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) at 3.0 V Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) at 3.0 V Temp. Typ. Max Unit at 85 °C 22.7 44.06 µA at 105 °C 48.4 90.1 µA at 25 °C 1.68 2.09 µA at 50 °C 3.05 4.04 µA at 70 °C 5.71 7.75 µA at 85 °C 10 13.54 µA at 105 °C 22.4 30.41 µA at 25 °C 1.22 1.6 µA at 50 °C 2.25 2.31 µA at 70 °C 4.21 5.44 µA at 85 °C 7.37 9.44 µA at 105 °C 16.6 21.76 µA at 25 °C 0.58 0.94 µA at 50 °C 1.26 1.31 µA at 70 °C 2.53 3.33 µA at 85 °C 4.74 6.1 µA at 105 °C 11.4 15.27 µA at 25 °C 0.31 0.65 µA at 50 °C 0.99 1.43 µA at 70 °C 2.25 3.01 µA at 85 °C 4.46 5.83 µA at 105 °C 11.13 14.99 µA at 25 °C 0.12 0.47 µA at 50 °C 0.8 1.24 µA at 70 °C 2.06 2.81 µA at 85 °C 4.27 5.62 µA at 105 °C 10.93 14.78 µA Note — — — — 7 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for time. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for balanced. 6. MCG configured for BLPI mode. 7. No brownout. 12 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. General Table 10. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 µA IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 µA IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 µA IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. VLLS1 440 490 540 560 570 580 nA VLLS3 440 490 540 560 570 580 LLS 490 490 540 560 570 680 VLPS 510 560 560 560 610 680 STOP 510 560 560 560 610 680 ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 µA IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 432 357 388 475 532 810 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. MCGIRCLK (4 MHz internal reference clock) 66 66 66 66 66 66 µA OSCERCLK (4 MHz external crystal) 214 237 246 254 260 268 MCGIRCLK (4 MHz internal reference clock) 86 86 86 86 86 86 OSCERCLK (4 MHz external crystal) 235 256 265 274 280 287 ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. µA Table continues on the next page... Kinetis KL25 Sub-Family, Rev5 08/2014. 13 Freescale Semiconductor, Inc. General Table 10. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 µA 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • • • • • MCG in FBE for run mode, and BLPE for VLPR mode USB regulator disabled No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFA 14 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. General Run Mode Current Vs Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 8.00E-03 7.00E-03 Current Consumption on VDD(A) 6.00E-03 5.00E-03 All Peripheral CLK Gates 4.00E-03 All Off All On 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 1 '1-1 2 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 3 4 6 12 24 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. Run mode supply current vs. core frequency Kinetis KL25 Sub-Family, Rev5 08/2014. 15 Freescale Semiconductor, Inc. General VLPR Mode Current Vs Core Frequency Temperature = 25, V DD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 400.00E-06 Current Consumption on VDD (A) 350.00E-06 300.00E-06 250.00E-06 All Peripheral CLK Gates 200.00E-06 All Off All On 150.00E-06 100.00E-06 50.00E-06 000.00E+00 '1-1 '1-2 1 '1-2 '1-4 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 4. VLPR mode current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP package Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15–50 13 dBμV VRE2 Radiated emissions voltage, band 2 50–150 15 dBμV VRE3 Radiated emissions voltage, band 3 150–500 12 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 7 dBμV IEC level 0.15–1000 M — VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and 16 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. General Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 48 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 2.2.8 Capacitance attributes Table 12. Capacitance attributes Symbol CIN Description Input capacitance Min. Max. Unit — 7 pF Min. Max. Unit 2.3 Switching specifications 2.3.1 Device clock specifications Table 13. Device clock specifications Symbol Description Normal run mode fSYS System and core clock — 48 MHz fBUS Bus clock — 24 MHz Flash clock — 24 MHz System and core clock when Full Speed USB in operation 20 — MHz LPTMR clock — 24 MHz fFLASH fSYS_USB fLPTMR VLPR and VLPS modes1 fSYS System and core clock — 4 MHz fBUS Bus clock — 1 MHz Flash clock — 1 MHz — 24 MHz fFLASH fLPTMR LPTMR clock2 Table continues on the next page... Kinetis KL25 Sub-Family, Rev5 08/2014. 17 Freescale Semiconductor, Inc. General Table 13. Device clock specifications (continued) Symbol fERCLK Description Min. Max. Unit — 16 MHz — 16 MHz Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) — 16 MHz TPM asynchronous clock — 8 MHz UART0 asynchronous clock — 8 MHz External reference clock fLPTMR_ERCLK LPTMR external reference clock fosc_hi_2 fTPM fUART0 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 14. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1 External RESET and NMI pin interrupt pulse width — Asynchronous path 100 — ns 2 GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2 Port rise and fall time — 36 ns 3 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 15. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C 18 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. Peripheral operating requirements and behaviors 2.4.2 Thermal attributes Table 16. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 80 LQFP 64 LQFP 48 QFN 32 QFN Unit Notes Thermal resistance, junction to ambient (natural convection) 70 71 84 92 °C/W 1 RθJA Thermal resistance, junction to ambient (natural convection) 53 52 28 33 °C/W Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) — 59 69 75 °C/W Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) — 46 22 27 °C/W — RθJB Thermal resistance, junction to board 34 34 10 12 °C/W 2 — RθJC Thermal resistance, junction to case 15 20 2.0 1.8 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 0.6 5 5.0 8 °C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules Kinetis KL25 Sub-Family, Rev5 08/2014. 19 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.1.1 SWD electricals Table 17. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 25 MHz 1/J1 — ns 20 — ns SWD_CLK frequency of operation • Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width • Serial wire debug J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 5. Serial wire clock input timing 20 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. Peripheral operating requirements and behaviors SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 6. Serial wire data timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 18. MCG specifications Symbol Description Min. Typ. Max. Unit fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C — 32.768 — kHz fints_t Internal reference frequency (slow clock) — user trimmed 31.25 — 39.0625 kHz — ± 0.3 ± 0.6 %fdco Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using C3[SCTRIM] and C4[SCFTRIM] Notes 1 Table continues on the next page... Kinetis KL25 Sub-Family, Rev5 08/2014. 21 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Δfdco_t Δfdco_t fintf_ft Δfintf_ft fintf_t Min. Typ. Max. Unit Notes Total deviation of trimmed average DCO output frequency over voltage and temperature — +0.5/-0.7 ±3 %fdco 1, 2 Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70 °C — ± 0.4 ± 1.5 %fdco 1, 2 Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25 °C — 4 — MHz Frequency deviation of internal reference clock (fast clock) over temperature and voltage — factory trimmed at nominal VDD and 25 °C — +1/-2 ±3 %fintf_ft Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C 3 — 5 MHz 2 floc_low Loss of external clock minimum frequency — RANGE = 00 (3/5) x fints_t — — kHz floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 (16/5) x fints_t — — kHz 31.25 — 39.0625 kHz 20 20.97 25 MHz 40 41.94 48 MHz — 23.99 — MHz — 47.97 — MHz — 180 — ps 7 — — 1 ms 8 48.0 — 100 MHz — 1060 — µA — 600 — µA 2.0 — 4.0 MHz FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 3, 4 640 × ffll_ref Mid range (DRS = 01) 1280 × ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS = 00) 5, 6 732 × ffll_ref Mid range (DRS = 01) 1464 × ffll_ref Jcyc_fll FLL period jitter • fVCO = 48 MHz tfll_acquire FLL target frequency acquisition time PLL fvco VCO operating frequency Ipll PLL operating current • PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) Ipll PLL operating current • PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) fpll_ref PLL reference frequency range Jcyc_pll PLL period jitter (RMS) 9 9 10 • fvco = 48 MHz — 120 — ps • fvco = 100 MHz — 50 — ps Table continues on the next page... 22 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Jacc_pll PLL accumulated jitter over 1µs (RMS) Typ. Max. Unit 10 • fvco = 48 MHz — 1350 — ps • fvco = 100 MHz — 600 — ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time Notes — — 10-6 150 × + 1075(1/ fpll_ref) s 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 19. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA — 1.2 — mA Table continues on the next page... Kinetis KL25 Sub-Family, Rev5 08/2014. 23 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol Description • 24 MHz Min. Typ. Max. Unit — 1.5 — mA Notes • 32 MHz IDDOSC Supply current — high gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA Cx EXTAL load capacitance — — — Cy XTAL load capacitance — — — RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, lowpower mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V RS 2, 3 2, 3 2, 4 Series resistor — high-frequency, high-gain mode (HGO=1) 5 Vpp 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 24 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. Peripheral operating requirements and behaviors 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Symbol Oscillator frequency specifications Table 20. Oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — high-frequency mode (low range) (MCG_C2[RANGE]=01) 3 — 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz fec_extal Input clock frequency (external clock mode) — — 48 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 750 — ms Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — 250 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms fosc_lo tcst Description Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. Kinetis KL25 Sub-Family, Rev5 08/2014. 25 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 21. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes thvpgm4 Longword Program high-voltage time — 7.5 18 μs — thversscr Sector Erase high-voltage time — 13 113 ms 1 thversall Erase All high-voltage time — 52 452 ms 1 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications — commands Table 22. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec1k tpgmchk Read 1s Section execution time (flash sector) — — 60 μs 1 Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersscr Erase Flash Sector execution time — 14 114 ms 2 trd1all Read 1s All Blocks execution time — — 1.8 ms — trdonce Read Once execution time — — 25 μs 1 Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 88 650 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tpgmonce 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 23. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit IDD_PGM Average current adder during high voltage flash programming operation — 2.5 6.0 mA IDD_ERS Average current adder during high voltage flash erase operation — 1.5 4.0 mA 26 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. Peripheral operating requirements and behaviors 3.4.1.4 Symbol Reliability specifications Table 24. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years — tnvmretp1k Data retention after up to 1 K cycles 20 100 — years — nnvmcycp Cycling endurance 10 K 50 K — cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C. 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.6.1.1 16-bit ADC operating conditions Table 25. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 — 3.6 V — ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V 3 VREFL ADC reference voltage low VSSA VSSA VSSA V 3 Table continues on the next page... Kinetis KL25 Sub-Family, Rev5 08/2014. 27 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 25. 16-bit ADC operating conditions (continued) Symbol Description VADIN Input voltage CADIN RADIN RAS Input capacitance Min. Typ.1 Max. Unit Notes • 16-bit differential mode VREFL — 31/32 * VREFH V — • All other modes VREFL — • 16-bit mode — 8 10 pF — • 8-bit / 10-bit / 12-bit modes — 4 5 — 2 5 kΩ — Conditions Input series resistance Analog source resistance (external) VREFH 13-bit / 12-bit modes 4 fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion ≤ 13-bit mode clock frequency 1.0 — 18.0 MHz 5 fADCK ADC conversion 16-bit mode clock frequency 2.0 — 12.0 MHz 5 Crate ADC conversion ≤ 13-bit modes rate No ADC hardware averaging 6 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion 16-bit mode rate No ADC hardware averaging 6 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. 28 Freescale Semiconductor, Inc. Kinetis KL25 Sub-Family, Rev5 08/2014. Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 7. ADC input impedance equivalency diagram 3.6.1.2 16-bit ADC electrical characteristics Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current ADC asynchronous clock source fADACK Conditions1 • ADLPC = 1, ADHSC = 0 • ADLPC = 1, ADHSC = 1 • ADLPC = 0, ADHSC = 0 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 1.2 2.4 3.9 MHz 2.4 4.0 6.1 MHz tADACK = 1/fADACK 3.0 5.2 7.3 MHz 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 • ADLPC = 0, ADHSC = 1 Sample Time TUE DNL See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 •
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