Freescale Semiconductor, Inc.
Data Sheet: Technical Data
KL33P80M48SF3
Rev. 2, 03/2015
Kinetis KL33 Microcontroller
MKL33Z32Vxx4
MKL33Z64Vxx4
48 MHz ARM® Cortex®-M0+ and 64 KB Flash
The KL33 series is optimized for cost-sensitive and batterypowered applications requiring low-power segment LCD. The
product offers:
• Low power segment LCD up to 40x8/42x6/44x4
• Embedded ROM with boot loader for flexible program
upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
• Hardware CRC module
• Down to 60uA/MHz in very low power run mode and
1.83uA in deep sleep mode (RAM + RTC retained)
Core Processor
• ARM® Cortex®-M0+ core up to 48 MHz
Memories
• 32/64 KB program flash memory
• 4/8 KB SRAM
• 8 KB ROM with build-in bootloader
• 32-byte backup register
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin Serial Wire Debug (SWD) programming and
debug interface
• Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller
Clocks
• 48 MHz high accuracy (up to 0.5%) internal reference
clock
• 8MHz/2MHz high accuracy (up to 3%) internal
reference clock
• 1KHz reference clock active under all low-power
modes (except VLLS0)
• 32–40KHz and 3–32MHz crystal oscillator
64 LQFP
10x10 mm P 0.5 mm
80 LQFP
12x12 mm P 0.5 mm
48 QFN
7x7 mm P 0.5 mm
64 BGA
5x5 mm P 0.5 mm
Peripherals
• Segment LCD supporting up to 40x8/42x6/44x4
segments
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1
Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of
additional UART, IrDA, SPI, I2C, PWM and other
serial modules, etc.
• One 16-bit 818 ksps ADC module with high
accuracy internal voltage reference (Vref) and up to
20 channels
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
• One 12-bit DAC
• 1.2 V internal voltage reference
Timers
•
•
•
•
•
One 6-channel Timer/PWM module
Two 2-channel Timer/PWM modules
One low-power timer
Periodic interrupt timer
Real time clock
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2014–2015 Freescale
Semiconductor, Inc. All rights reserved.
Operating Characteristics
Security and Integrity
• 80-bit unique identification number per chip
• Advanced flash security
• Hardware CRC module
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
Packages
• 80 LQFP 12mm x 12mm, 0.5mm pitch, 1.6mm
thickness
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm
thickness
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm
thickness (Package Your Way)
• 48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness
(Package Your Way)
I/O
• Up to 70 general-purpose input/output pins (GPIO)
and 4 high-drive pad
Low Power
• Down to 60uA/MHz in very low power run mode
• Down to 1.83uA in VLLS3 mode (RAM + RTC
retained)
• Six flexible static modes
Ordering Information
Product
Memory
Package
IO and ADC channel
Part number
Marking (Line1/
Line2)
Flash
(KB)
SRAM
(KB)
Pin
count
Package
GPIOs
GPIOs
(INT/HD)1
ADC
channels
(SE/DP)
MKL33Z32VFT4
TBD
32
4
48
QFN
40
40/4
17/3
MKL33Z64VFT4
TBD
64
8
48
QFN
40
40/4
17/3
MKL33Z32VLH4
MKL33Z32/VLH4
32
4
64
LQFP
54
54/4
20/4
MKL33Z64VLH4
MKL33Z64/VLH4
64
8
64
LQFP
54
54/4
20/4
MKL33Z32VMP4
TBD
32
4
64
MAPBGA
54
54/4
20/4
MKL33Z64VMP4
TBD
64
8
64
MAPBGA
54
54/4
20/4
MKL33Z32VLK4
MKL33Z32VLK4
32
4
80
LQFP
70
70/4
20/4
MKL33Z64VLK4
MKL33Z64VLK4
64
8
80
LQFP
70
70/4
20/4
1. INT: interrupt pin numbers; HD: high drive pin numbers
NOTE
The 48 QFN and 64 MAPBGA packages supporting MKLx3ZxxVFT4 and
MKLx3ZxxVMP4 part numbers for this product are not yet available. However, these
packages are included in Package Your Way program for Kinetis MCUs. Visit
freescale.com/KPYW for more details.
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KL3xPB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KL33P80M48SF3RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
Related Resources (continued)
Type
Description
Resource
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_L_0N01P1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
• 64-LQFP: 98ASS23234W1
• 64 MAPBGA:
98ASA00420D1
• 48 QFN: 98ASA00616D1
• 80 LQFP: 98ASS23174W1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
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Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................. 5
1.1 Thermal handling ratings............................................. 5
1.2 Moisture handling ratings............................................ 5
1.3 ESD handling ratings...................................................5
1.4 Voltage and current operating ratings......................... 5
2 General................................................................................. 6
2.1 AC electrical characteristics........................................ 6
2.2 Nonswitching electrical specifications......................... 6
2.2.1 Voltage and current operating requirements... 7
2.2.2 LVD and POR operating requirements............7
2.2.3 Voltage and current operating behaviors.........8
2.2.4 Power mode transition operating behaviors.... 9
5.1
5.2
6
SPI switching specifications........................................ 40
I2C............................................................................... 45
5.2.1 Inter-Integrated Circuit Interface (I2C) timing.. 45
5.3 UART...........................................................................47
Design considerations...........................................................47
6.1 Hardware design considerations................................. 47
6.1.1 Printed circuit board recommendations........... 47
6.1.2 Power delivery system.....................................47
6.1.3 Analog design..................................................48
6.1.4 Digital design................................................... 49
6.1.5 Crystal oscillator.............................................. 52
6.2 Software considerations.............................................. 53
Human-machine interfaces (HMI)......................................... 54
7.1 LCD electrical characteristics...................................... 54
Dimensions........................................................................... 56
8.1 Obtaining package dimensions................................... 56
Pinouts and Packaging......................................................... 56
9.1 KL33 Signal Multiplexing and Pin Assignments.......... 56
9.2 KL33 Family Pinouts....................................................60
Ordering parts....................................................................... 64
10.1 Determining valid orderable parts................................64
Part identification...................................................................64
11.1 Description...................................................................65
11.2 Format......................................................................... 65
11.3 Fields........................................................................... 65
11.4 Example.......................................................................65
Terminology and guidelines.................................................. 66
12.1 Definition: Operating requirement................................66
12.2 Definition: Operating behavior..................................... 66
12.3 Definition: Attribute...................................................... 67
12.4 Definition: Rating......................................................... 67
12.5 Result of exceeding a rating........................................ 67
12.6 Relationship between ratings and operating
2.2.5 Power consumption operating behaviors........ 10
2.2.6 EMC performance........................................... 20
2.2.7 Capacitance attributes.....................................21
2.3 Switching specifications...............................................21
2.3.1 Device clock specifications..............................21
2.3.2 General switching specifications..................... 21
2.4 Thermal specifications.................................................22
2.4.1 Thermal operating requirements..................... 22
2.4.2 Thermal attributes............................................22
3 Peripheral operating requirements and behaviors................ 23
3.1 Core modules.............................................................. 23
3.1.1 SWD electricals .............................................. 23
3.2 System modules.......................................................... 25
3.3 Clock modules............................................................. 25
3.3.1 MCG-Lite specifications...................................25
3.3.2 Oscillator electrical specifications....................25
3.4 Memories and memory interfaces............................... 28
3.4.1 Flash electrical specifications.......................... 28
3.5 Security and integrity modules.................................... 29
3.6 Analog......................................................................... 29
3.6.1 ADC electrical specifications........................... 29
7
3.6.2 Voltage reference electrical specifications...... 34
3.6.3 CMP and 6-bit DAC electrical specifications... 35
3.6.4 12-bit DAC electrical characteristics................37
4 Timers................................................................................... 40
5 Communication interfaces.....................................................40
requirements................................................................68
12.7 Guidelines for ratings and operating requirements......68
12.8 Definition: Typical value...............................................69
12.9 Typical value conditions.............................................. 70
13 Revision History.................................................................... 70
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Kinetis KL33 Microcontroller, Rev.2, 03/2015.
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
–2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
–500
+500
V
2
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
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General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
mA
VIO
IO pin input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
ID
VDDA
Analog supply voltage
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
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Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
General
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-3
—
mA
-25
—
mA
VIH
VIL
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
IO pin negative DC injection current — single pin
1
• VIN < VSS-0.3V
IICcont
Notes
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
• Negative current injection
VODPU
Open drain pullup voltage level
VDD
VDD
V
VSRAM
VDD voltage required to retain SRAM
1.2
—
V
2
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
—
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
1
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Kinetis KL33 Microcontroller, Rev.2, 03/2015.
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General
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol
Min.
Typ.
Max.
Unit
VLVW1H
Description
• Level 1 falling (LVWV = 00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV = 01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV = 10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV = 11)
2.92
3.00
3.08
V
—
±60
—
mV
—
1.54
1.60
1.66
V
—
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
VLVW1L
• Level 1 falling (LVWV = 00)
VLVW2L
• Level 2 falling (LVWV = 01)
VLVW3L
• Level 3 falling (LVWV = 10)
VLVW4L
• Level 4 falling (LVWV = 11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
1
1.74
1.80
1.86
V
1.84
1.90
1.96
V
1.94
2.00
2.06
V
2.04
2.10
2.16
V
—
±40
—
mV
—
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
—
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
—
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol
VOH
VOH
Description
Min.
Unit
Output high voltage — normal drive pad
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
—
V
Output high voltage — high drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
—
V
—
100
mA
Output high current total for all ports
VOL
Output low voltage — normal drive pad
Notes
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
IOHT
VOL
Max.
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
0.5
V
Output low voltage — high drive pad
1
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Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
General
Table 7. Voltage and current operating behaviors (continued)
Symbol
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
2
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
2
IIN
Input leakage current (total all pins) for full
temperature range
—
80
μA
2
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
IOLT
Description
Notes
3
1. PTB0, PTB1, PTC3, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PORTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 8. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
—
152
166
μs
—
152
166
μs
—
93
104
μs
—
7.5
8
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
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General
Table 8. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
7.5
8
μs
—
7.5
8
μs
Notes
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_FOPT[LPBOOT]=11)
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while (1) test is executed with flash cache enabled.
Table 9. Power consumption operating behaviors
Symbol
IDDA
Description
Analog supply current
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
2
—
4.74
4.93
—
4.9
5.10
—
3.27
3.43
—
3.42
3.59
mA
mA
2
—
5.63
5.86
—
5.79
6.02
mA
2,
—
3.47
3.61
—
3.63
3.78
mA
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Kinetis KL33 Microcontroller, Rev.2, 03/2015.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
Typ.
Max.
Unit
2
—
2.37
2.56
—
2.53
2.73
mA
2
—
6.91
7.19
—
7.07
7.35
—
4.14
4.31
—
4.3
4.47
—
2.7
2.92
—
2.86
3.09
—
1.99
2.15
—
2.14
2.31
—
5.39
5.61
—
5.56
5.78
IDD_VLPRCO Very Low Power Run Core Mark in Flash in
Compute Operation mode: Core@4MHz, Flash
@1MHz, VDD = 3.0 V
• at 25 °C
—
739
827.68
μA
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode,
4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
339
406.8
μA
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode,
2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
152
197.6
μA
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_VLPR
Notes
mA
mA
mA
mA
mA
Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
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General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
• at 25 °C
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_WAIT
IDD_WAIT
IDD_VLPW
Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in flash all peripheral
clock enable, 4 MHz core / 1 MHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM in all
peripheral clock disable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
• at 25 °C
Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
• at 25 °C
Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
• at 25 °C
Very-low-power wait mode current, core
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C
Min.
Typ.
Max.
Unit
—
119
178.5
μA
—
41
89.39
μA
—
277
360.1
μA
—
343
425.32
μA
—
375
450
μA
—
441
529.2
μA
—
45
103.5
μA
—
2.14
2.50
mA
—
1.41
1.62
mA
—
193
239.023
μA
Notes
Table continues on the next page...
12
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
IDD_VLPW
IDD_VLPW
Min.
Typ.
Max.
Unit
Very-low-power wait mode current, core
disabled, 2 MHz system/ 0.5 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C
—
78
124.8
μA
Very-low-power wait mode current, core
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C
—
39
78
μA
—
1.72
2.06
mA
—
1.1
1.32
mA
—
161
178.2
—
171.9
181.17
—
206.8
229.72
—
255.9
302.01
—
2.20
3.80
—
4.57
8.03
—
18.02
31.98
—
39.60
65.80
—
2.13
3.80
—
4.42
7.94
—
17.53
31.58
—
38.55
65.18
Notes
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
• at 25 °C
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
• at 25 °C
IDD_STOP
Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at 1.8 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_LLS
Low-leakage stop mode current, all peripheral
disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_LLS
Low-leakage stop mode current with RTC
current, at 3.0 V
• at 25 °C and below
μA
μA
μA
μA
—
1.63
2.25
—
2.42
3.55
—
4.22
7.08
—
7.16
10.22
—
15.34
22.69
—
2.3
2.99
μA
Table continues on the next page...
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
13
Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
IDD_LLS
Description
Min.
Typ.
Max.
• at 50 °C
—
3.12
4.50
• at 70 °C
—
4.96
7.71
• at 85 °C
—
7.93
10.75
• at 105 °C
—
16.02
22.99
Low-leakage stop mode current with RTC
current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
Unit
Notes
3
—
2.03
2.55
—
2.81
3.95
—
4.53
7.30
—
7.31
10.25
—
14.93
22.72
—
1.16
1.65
—
1.72
2.65
—
3.04
5.70
—
5.21
7.79
—
11.33
17.63
μA
μA
3
—
1.83
2.35
—
2.43
3.39
—
3.78
5.95
—
5.98
8.14
—
12.02
17.89
μA
3
—
1.58
1.98
—
2.13
3.17
—
3.37
5.80
—
5.4
7.83
—
10.99
16.86
—
0.62
1.06
—
0.99
1.43
—
1.88
2.65
—
3.41
4.53
μA
μA
Table continues on the next page...
14
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
• at 85°C
Min.
Typ.
Max.
—
7.89
9.99
Unit
Notes
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
• at 25 °C and below
3
—
1.31
1.52
—
1.7
2.04
—
2.6
3.20
—
4.14
4.69
—
8.51
10.46
3
—
1.06
1.35
—
1.39
1.73
—
2.18
2.83
—
3.54
4.60
—
7.43
9.97
—
278
385
• at 50 °C
—
578
1013
• at 70 °C
—
1530
2015
• at 85 °C
—
3070
3617
• at 105 °C
—
7550
9900
—
95
218
• at 50 °C
—
412
653
• at 70 °C
—
1350
1683
• at 85 °C
—
2900
3428
• at 105 °C
—
7380
9785
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
• at 25 °C and below
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
• at 25 °C and below
μA
μA
nA
nA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.20 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
15
Freescale Semiconductor, Inc.
General
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIRC8MHz
8 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
85
87
88
88
89
90
µA
IIRC2MHz
2 MHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
28
28
28
28
28
28
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
224
230
238
245
253
µA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of setting the
OSC0_CR[EREFSTEN and
EREFSTEN] bits to 1 and
SIM_SOPT1[OSC32KSEL] to 01.
Measured by entering all modes with
the crystal enabled.
• VLLS1
• VLLS3
• LLS
• VLPS
• STOP
440
490
540
560
570
580
440
490
540
560
570
580
490
490
540
560
570
680
510
560
560
560
610
680
510
560
560
560
610
680
30
30
30
85
100
200
ILPTMR
nA
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
nA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
16
16
16
16
16
16
µA
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
582
627
638
662
682
760
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Table continues on the next page...
16
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Includes selected clock source power
consumption.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the clock
signal. Includes selected clock source
and I/O switching currents.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
Temperature (°C)
Unit
-40
25
50
70
85
105
105
110
110
111
112
114
34
34
34
34
34
34
130
130
130
130
130
130
40
40
40
40
40
40
µA
µA
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx or VLLSx
mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
320
320
320
320
320
320
µA
ILCD
LCD peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the OSC0_CR[EREFSTEN,
EREFSTEN] bits. VIREG disabled,
resistor bias network enabled, 1/8 duty
cycle, 8 x 36 configuration for driving
288 Segments, 32 Hz frame rate, no
LCD glass connected. Includes
ERCLK32K (32 kHz external crystal)
power consumption.
4.9
4.9
4.9
4.9
4.9
4.9
µA
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
No GPIOs toggled
Code execution from flash
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
17
Freescale Semiconductor, Inc.
General
Figure 2. Run mode supply current vs. core frequency
18
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
General
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
19
Freescale Semiconductor, Inc.
General
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following Freescale applications notes, available on freescale.com for
advice and guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications
20
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
General
• AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems
• KL-QRUG (Kinetis L-series Quick Reference).
2.2.7 Capacitance attributes
Table 11. Capacitance attributes
Symbol
CIN
Description
Input capacitance
Min.
Max.
Unit
—
7
pF
Min.
Max.
Unit
2.3 Switching specifications
2.3.1 Device clock specifications
Table 12. Device clock specifications
Symbol
Description
Normal run mode
fSYS
System and core clock
—
48
MHz
fBUS
Bus clock
—
24
MHz
fFLASH
Flash clock
—
24
MHz
fLPTMR
LPTMR clock
—
24
MHz
VLPR and VLPS
modes1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
Flash clock
—
1
MHz
—
24
MHz
fFLASH
fLPTMR
LPTMR
clock2
fLPTMR_ERCLK LPTMR external reference clock
fosc_hi_2
fTPM
fLPUART0/1
—
16
MHz
Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
—
16
MHz
TPM asynchronous clock
—
8
MHz
LPUART0/1 asynchronous clock
—
8
MHz
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
21
Freescale Semiconductor, Inc.
General
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 13. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
—
36
ns
3
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 14. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Notes
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + θJA × chip power dissipation.
2.4.2 Thermal attributes
NOTE
The 48 QFN and 64 MAPBGA packages for this product are
not yet available. However, these packages are included in
Package Your Way program for Kinetis MCUs. Visit
freescale.com/KPYW for more details.
22
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
Peripheral operating requirements and behaviors
Table 15. Thermal attributes
Board type
Symbol
Single-layer (1S)
RθJA
Four-layer (2s2p)
Description
64 LQFP
80 LQFP
Unit
Notes
Thermal resistance, junction to
ambient (natural convection)
71
58
°C/W
1, 2
RθJA
Thermal resistance, junction to
ambient (natural convection)
53
43
°C/W
1, 2
Single-layer (1S)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
60
47
°C/W
1, 3
Four-layer (2s2p)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
46
37
°C/W
1, 3,
—
RθJB
Thermal resistance, junction to
board
35
26
°C/W
4
—
RθJC
Thermal resistance, junction to
case
21
15
°C/W
5
—
ΨJT
Thermal characterization
parameter, junction to package top
outside center (natural convection)
5
3
°C/W
6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 16. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
SWD_CLK frequency of operation
Table continues on the next page...
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 16. SWD full voltage range electricals (continued)
Symbol
Description
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
Min.
Max.
Unit
0
25
MHz
1/J1
—
ns
20
—
ns
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 4. Serial wire clock input timing
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 5. Serial wire data timing
24
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
Peripheral operating requirements and behaviors
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications
Table 17. IRC48M specifications
Symbol
Description
Min.
Typ.
Max.
Unit
IDD48M
Supply current
—
400
500
μA
firc48m
Internal reference frequency
—
48
—
MHz
—
± 0.5
± 1.5
%firc48m
—
± 0.5
± 1.0
%firc48m
Period Jitter (RMS)
—
35
150
ps
Startup time
—
2
3
μs
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over temperature
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over temperature
Jcyc_irc48m
tirc48mst
Notes
Table 18. IRC8M/2M specification
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_2M
Supply current in 2 MHz mode
—
14
17
µA
—
IDD_8M
Supply current in 8 MHz mode
—
30
35
µA
—
fIRC_2M
Output frequency
—
2
—
MHz
—
fIRC_8M
Output frequency
—
8
—
MHz
—
fIRC_T_2M
Output frequency range (trimmed)
—
—
±3
%fIRC
—
fIRC_T_8M
Output frequency range (trimmed)
—
—
±3
%fIRC
—
Tsu_2M
Startup time
—
—
12.5
µs
—
Tsu_8M
Startup time
—
—
12.5
µs
—
3.3.2 Oscillator electrical specifications
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
25
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.3.2.1
Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
—
0.6
—
V
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Vpp5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
Table continues on the next page...
26
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2
Symbol
Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Min.
Typ.
Max.
Unit
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency —
high-frequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
fosc_lo
tcst
Description
Notes
1, 2
1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
27
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 21. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
52
452
ms
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Flash timing specifications — commands
Table 22. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
0.9
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
70
575
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tersallu
Erase All Blocks Unsecure execution time
—
70
575
ms
2
tpgmonce
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
28
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
Peripheral operating requirements and behaviors
3.4.1.3
Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 24. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
Using differential inputs can achieve better system accuracy than using single-end
inputs.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
29
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.1.1
16-bit ADC operating conditions
Table 25. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
—
• All other modes
VREFL
—
• 16-bit mode
—
8
10
pF
—
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
kΩ
—
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
VREFH
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
5
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
30
Freescale Semiconductor, Inc.
Kinetis KL33 Microcontroller, Rev.2, 03/2015.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 6. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK =
1/fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
IDDA_ADC Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
See Reference Manual chapter for sample times
Total
unadjusted
error
• 12-bit modes
—
±2.5
±6.8
•
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