Freescale Semiconductor, Inc.
Data Sheet: Technical Data
KL43P64M48SF6
Rev. 5, 08/2015
Kinetis KL43 Microcontroller
MKL43Z256Vxx4(R)
MKL43Z128Vxx4(R)
48 MHz ARM® Cortex®-M0+ and 128/256 KB Flash
The KL43 series is optimized for cost-sensitive and batterypowered applications requiring low-power USB connectivity and
segment LCD. The product offers:
• Low power segment LCD up to 24x8 or 28x4
• USB FS 2.0 device without requiring an external crystal
• Embedded ROM with boot loader for flexible program
upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
• Down to 54uA/MHz in very low power run mode and
1.96uA in deep sleep mode (RAM + RTC retained)
Core Processor
• ARM® Cortex®-M0+ core up to 48 MHz
Memories
• 128/256 KB program flash memory
• 16/32 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin Serial Wire Debug (SWD) programming and
debug interface
• Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller
Clocks
• 48MHz high accuracy (up to 0.5%) internal reference
clock
• 8MHz/2MHz high accuracy (up to 3%) internal
reference clock
• 1KHz reference clock active under all low-power
modes (except VLLS0)
• 32–40KHz and 3–32MHz crystal oscillator
64 LQFP
10x10 mm P 0.5 mm
64 BGA
5x5 mm P 0.5 mm
Peripherals
• Segment LCD supporting up to 24x8 or 28x4
segments
• USB full-speed 2.0 device controller supporting
crystal-less operation
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1
Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of
additional UART, SPI, I2C, I2S, PWM and other
serial modules, etc.
• One serial audio interface I2S
• One 16-bit 818 ksps ADC module with high
accuracy internal voltage reference (Vref) and up to
16 channels
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
• One 12-bit DAC
• 1.2 V internal voltage reference
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2015 Freescale
Semiconductor, Inc. All rights reserved.
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
Packages
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm
thickness
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm
thickness
Security and Integrity
• 80-bit unique identification number per chip
• Advanced flash security
Low Power
I/O
• Down to 54uA/MHz in very low power run mode
• Up to 50 general-purpose input/output pins (GPIO)
• Down to 1.96uA in VLLS3 mode (RAM + RTC retained)
and 6 high-drive pad
• Six flexible static modes
Ordering Information
Product
Memory
Package
IO and ADC channel
Part number
Marking (Line1/
Line2)
Flash
(KB)
SRAM
(KB)
Pin
count
Package
GPIOs
GPIOs
(INT/HD)1
ADC
channels
(SE/DP)
MKL43Z128VLH4
MKL43Z128V//LH4
128
16
64
LQFP
50
31/6
16/2
MKL43Z256VLH4
MKL43Z256V//LH4
256
32
64
LQFP
50
31/6
16/2
MKL43Z128VMP4
M43P7V
128
16
64
MAPBGA
50
31/6
16/2
MKL43Z256VMP4
M43P8V
256
32
64
MAPBGA
50
31/6
16/2
1. INT: interrupt pin numbers; HD: high drive pin numbers
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KLX3PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KL43P64M48SF6RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_L_1N71K1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
64-LQFP: 98ASS23234W1 64
MAPBGA: 98ASA00420D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Table of Contents
1 Ratings.................................................................................. 4
1.1 Thermal handling ratings............................................... 4
1.2 Moisture handling ratings...............................................4
1.3 ESD handling ratings..................................................... 4
1.4 Voltage and current operating ratings............................4
2 General................................................................................. 5
2.1 AC electrical characteristics...........................................5
2.2 Nonswitching electrical specifications............................6
2.2.1 Voltage and current operating requirements......6
2.2.2 LVD and POR operating requirements.............. 6
2.2.3 Voltage and current operating behaviors........... 7
2.2.4 Power mode transition operating behaviors.......8
2.2.5 Power consumption operating behaviors...........9
2.2.6 EMC radiated emissions operating behaviors... 19
2.2.7 Designing with radiated emissions in mind........ 20
2.2.8 Capacitance attributes....................................... 20
2.3 Switching specifications................................................. 20
2.3.1 Device clock specifications................................ 20
2.3.2 General switching specifications........................21
2.4 Thermal specifications................................................... 21
2.4.1 Thermal operating requirements........................21
2.4.2 Thermal attributes.............................................. 22
3 Peripheral operating requirements and behaviors................ 22
3.1 Core modules................................................................ 22
3.1.1 SWD electricals .................................................23
3.2 System modules............................................................ 24
3.3 Clock modules............................................................... 24
3.3.1 MCG-Lite specifications..................................... 24
3.3.2 Oscillator electrical specifications...................... 26
3.4 Memories and memory interfaces................................. 28
3.4.1 Flash electrical specifications............................ 28
3.5 Security and integrity modules.......................................30
3.6 Analog............................................................................30
3.6.1 ADC electrical specifications..............................30
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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5
6
7
8
9
3.6.2 Voltage reference electrical specifications.........35
3.6.3 CMP and 6-bit DAC electrical specifications......36
3.6.4 12-bit DAC electrical characteristics.................. 38
3.7 Timers............................................................................ 41
3.8 Communication interfaces............................................. 41
3.8.1 USB electrical specifications..............................41
3.8.2 USB VREG electrical specifications...................42
3.8.3 SPI switching specifications...............................42
3.8.4 I2C..................................................................... 47
3.8.5 UART................................................................. 49
3.8.6 I2S/SAI switching specifications........................ 49
3.9 Human-machine interfaces (HMI).................................. 53
3.9.1 LCD electrical characteristics.............................53
Dimensions........................................................................... 55
4.1 Obtaining package dimensions......................................55
Pinouts and Packaging......................................................... 55
5.1 KL43 Signal Multiplexing and Pin Assignments.............55
5.2 KL43 Family Pinouts...................................................... 58
Ordering parts....................................................................... 60
6.1 Determining valid orderable parts.................................. 60
Part identification...................................................................60
7.1 Description..................................................................... 60
7.2 Format........................................................................... 61
7.3 Fields............................................................................. 61
7.4 Example......................................................................... 61
Terminology and guidelines.................................................. 62
8.1 Definitions...................................................................... 62
8.2 Examples....................................................................... 62
8.3 Typical-value conditions................................................ 63
8.4 Relationship between ratings and operating
requirements.................................................................. 63
8.5 Guidelines for ratings and operating requirements........ 64
Revision History.................................................................... 64
3
Freescale Semiconductor, Inc.
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
–2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
–500
+500
V
2
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
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Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
mA
VIO
IO pin input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
ID
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
VUSB_DP
USB_DP input voltage
–0.3
3.63
V
VUSB_DM
USB_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
VREGIN
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Low
VIH
Input Signal
High
80%
50%
20%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
5
Freescale Semiconductor, Inc.
General
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-3
—
mA
-25
—
mA
VIH
VIL
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
IO pin negative DC injection current — single pin
1
• VIN < VSS-0.3V
IICcont
Notes
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
• Negative current injection
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
2
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol
VPOR
Description
Min.
Typ.
Max.
Unit
Notes
Falling VDD POR detect voltage
0.8
1.1
1.5
V
—
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
General
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol
VLVDH
Description
Min.
Typ.
Max.
Unit
Notes
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
VLVW1H
• Level 1 falling (LVWV = 00)
VLVW2H
• Level 2 falling (LVWV = 01)
VLVW3H
• Level 3 falling (LVWV = 10)
VLVW4H
• Level 4 falling (LVWV = 11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
1
2.62
2.70
2.78
V
2.72
2.80
2.88
V
2.82
2.90
2.98
V
2.92
3.00
3.08
V
—
±60
—
mV
—
1.54
1.60
1.66
V
—
Low-voltage warning thresholds — low range
VLVW1L
• Level 1 falling (LVWV = 00)
VLVW2L
• Level 2 falling (LVWV = 01)
VLVW3L
• Level 3 falling (LVWV = 10)
VLVW4L
• Level 4 falling (LVWV = 11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
1
1.74
1.80
1.86
V
1.84
1.90
1.96
V
1.94
2.00
2.06
V
2.04
2.10
2.16
V
—
±40
—
mV
—
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
—
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
—
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol
VOH
VOH
Description
Min.
Max.
Unit
Output high voltage — normal drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
—
V
Output high voltage — high drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
—
V
—
100
mA
—
0.5
V
IOHT
Output high current total for all ports
VOL
Output low voltage — normal drive pad
Notes
1
Table continues on the next page...
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
General
Table 7. Voltage and current operating behaviors (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
VOL
IOLT
Min.
Max.
Unit
—
0.5
V
Notes
Output low voltage — high drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
2
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
2
IIN
Input leakage current (total all pins) for full
temperature range
—
64
μA
2
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
3
1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the
associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 8. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
—
152
166
μs
—
152
166
μs
—
93
104
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
General
Table 8. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
7.5
8
μs
—
7.5
8
μs
—
7.5
8
μs
Notes
• LLS → RUN
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_FOPT[LPBOOT]=11)
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while (1) test is executed with flash cache enabled.
Table 9. Power consumption operating behaviors
Symbol
IDDA
Description
Analog supply current
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable, 24
MHz core/12 MHz flash, VDD = 3.0 V
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
2
—
5.76
6.40
—
6.04
6.68
—
3.21
3.85
—
3.49
4.13
mA
mA
2
—
6.45
7.09
—
6.75
7.39
mA
2
—
3.95
4.59
—
4.23
4.87
mA
Table continues on the next page...
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 12
MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock disable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C
IDD_RUN
Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
2
—
2.68
3.32
—
2.96
3.60
mA
2
—
8.08
8.72
—
8.39
9.03
—
3.90
4.54
—
4.21
4.85
—
2.66
3.30
—
2.94
3.58
—
2.03
2.67
—
2.31
2.95
—
5.52
6.16
—
5.83
6.47
—
5.29
5.93
—
5.56
6.20
—
6.91
7.55
—
7.19
7.91
mA
mA
mA
mA
mA
mA
mA
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_VLPRC Very Low Power Run Core Mark in Flash in
Compute Operation mode: Core@4MHz, Flash
O
@1MHz, VDD = 3.0 V
• at 25 °C
—
826
907
μA
IDD_VLPRC Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode, 4
O
MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
405
486
μA
IDD_VLPRC Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode, 2
O
MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
154
235
μA
—
108
189
μA
—
39
120
μA
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
249
330
μA
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
337
418
μA
—
416
497
μA
—
494
575
μA
—
166
247
μA
Notes
• at 25 °C
• at 105 °C
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD =
3.0 V
• at 25 °C
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
Table continues on the next page...
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
50
131
μA
Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
208
289
μA
Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.81
1.89
mA
Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
—
1.22
1.39
mA
IDD_VLPW Very-low-power wait mode current, core
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
—
172
182
μA
IDD_VLPW Very-low-power wait mode current, core
disabled, 2 MHz system/ 0.5 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
—
69
76
μA
IDD_VLPW Very-low-power wait mode current, core
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0 V
—
36
40
μA
—
1.81
2.06
mA
—
1.00
1.25
mA
—
161.93
171.82
—
181.45
191.96
—
236.29
271.17
—
390.33
465.58
—
3.31
5.14
—
10.43
17.68
—
34.14
61.06
—
104.38
164.44
—
3.21
5.22
disable, 125 kHz core / 31.25 kHz flash, VDD =
3.0 V
• at 25 °C
IDD_VLPR
IDD_WAIT
IDD_WAIT
Notes
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at 1.8 V
• at 25 °C and below
μA
μA
Table continues on the next page...
12
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
IDD_LLS
Description
Min.
Typ.
Max.
• at 50 °C
—
10.26
17.62
• at 85 °C
—
33.49
60.19
• at 105 °C
—
102.92
162.20
—
2.06
3.33
—
4.72
6.85
—
8.13
13.30
—
13.34
24.70
—
41.08
52.43
—
2.46
3.73
—
5.12
7.25
—
8.53
11.78
—
13.74
18.91
—
41.48
52.83
Low-leakage stop mode current, all peripheral
disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_LLS
Low-leakage stop mode current with RTC
current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_LLS
Low-leakage stop mode current with RTC
current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
Unit
Notes
μA
μA
μA
3
—
2.35
2.70
—
4.91
6.75
—
8.32
11.78
—
13.44
18.21
—
40.47
51.85
—
1.45
1.85
—
3.37
4.39
—
5.76
8.48
—
9.72
14.30
—
30.41
37.50
μA
μA
3
—
2.05
2.45
—
3.97
4.99
—
6.36
9.08
—
10.32
14.73
—
31.01
38.10
μA
Table continues on the next page...
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Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
• at 25 °C and below
Min.
Typ.
Max.
—
1.96
2.36
—
3.86
5.67
—
6.23
8.53
—
10.21
13.37
—
30.25
37.02
—
0.66
0.80
—
1.78
3.87
—
2.55
4.26
—
4.83
6.64
—
16.42
20.49
—
1.26
1.40
—
2.38
4.47
—
3.15
4.86
—
5.43
7.24
—
17.02
21.09
—
1.96
2.28
—
2.78
3.37
—
4.85
6.88
—
15.78
18.81
—
0.35
0.47
• at 50 °C
—
1.25
1.44
• at 70 °C
—
2.53
3.24
• at 85 °C
—
4.40
5.24
• at 105 °C
—
16.09
19.29
• at 105 °C
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
• at 25 °C and below
μA
μA
3
1.30
• at 85°C
μA
3
1.16
• at 70°C
Notes
3
—
• at 50°C
Unit
μA
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
14
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
General
Table 9. Power consumption operating behaviors
Symbol
Description
Min.
Typ.
Max.
• at 25 °C and below
—
0.18
0.28
• at 50 °C
—
1.09
1.31
• at 70 °C
—
2.25
2.94
• at 85 °C
—
4.25
5.10
• at 105 °C
—
15.95
19.10
Unit
Notes
μA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIRC8MHz
8 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
93
93
93
93
93
93
µA
IIRC2MHz
2 MHz internal reference clock (IRC)
adder. Measured by entering STOP mode
with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
29
29
29
29
29
29
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
224
230
238
245
253
µA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering
all modes with the crystal enabled.
• VLLS1
440
490
540
560
570
580
440
490
540
560
570
580
490
490
540
560
570
680
510
560
560
560
610
680
510
560
560
560
610
680
30
30
30
85
100
200
• VLLS3
• LLS
• VLPS
• STOP
ILPTMR
nA
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
Table continues on the next page...
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Freescale Semiconductor, Inc.
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
-40
25
50
70
Unit
85
105
nA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate. Includes
selected clock source power
consumption.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare generating
100 Hz clock signal. No load is placed on
the I/O generating the clock signal.
Includes selected clock source and I/O
switching currents.
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
22
22
22
22
22
22
µA
114
114
114
114
114
114
µA
34
34
34
34
34
34
147
147
147
147
147
147
42
42
42
42
42
42
µA
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx or VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
330
330
330
330
330
330
µA
ILCD
LCD peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by means
of the OSC0_CR[EREFSTEN,
EREFSTEN] bits. VIREG disabled,
resistor bias network enabled, 1/8 duty
cycle, 8 x 36 configuration for driving 288
Segments, 32 Hz frame rate, no LCD
glass connected. Includes ERCLK32K (32
kHz external crystal) power consumption.
4.5
4.5
4.5
4.5
4.5
4.5
µA
16
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
General
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
•
MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
USB regulator disabled
No GPIOs toggled
Code execution from flash
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 2. Run mode supply current vs. core frequency
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
General
18
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Current
ionon
onVDD
VDD
(A)
CurrentC
Consumpt
onsumption
(A)
General
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP
package
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
11
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
12
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
10
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
6
dBμV
IEC level
0.15–1000
N
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
General
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = IRC48M, fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol
CIN
Description
Input capacitance
Min.
Max.
Unit
—
7
pF
Min.
Max.
Unit
—
48
MHz
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Normal run mode
fSYS
fBUS
fFLASH
fSYS_USB
fLPTMR
System and core
Bus
clock1
clock1
—
24
MHz
Flash clock1
—
24
MHz
System and core clock when Full Speed USB in operation
20
—
MHz
LPTMR clock
—
24
MHz
VLPR and VLPS
modes2
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
Flash clock
—
1
MHz
—
24
MHz
fFLASH
fLPTMR
LPTMR
clock3
Table continues on the next page...
20
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
General
Table 13. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
—
16
MHz
Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
—
16
MHz
TPM asynchronous clock
—
8
MHz
LPUART0/1 asynchronous clock
—
8
MHz
fLPTMR_ERCLK LPTMR external reference clock
fosc_hi_2
fTPM
fLPUART0/1
1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher
than the specified maximum frequency when IRC 48MHz is used as the clock source.
2. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
3. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
—
36
ns
3
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Notes
1
21
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
2.4.2 Thermal attributes
Table 16. Thermal attributes
Board type
Symbol
Single-layer (1S)
RθJA
Four-layer (2s2p)
Description
64 LQFP
64
MAPBGA
Unit
Notes
Thermal resistance, junction to
ambient (natural convection)
70
50.3
°C/W
1
RθJA
Thermal resistance, junction to
ambient (natural convection)
51
42.9
°C/W
Single-layer (1S)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
58
41.4
°C/W
Four-layer (2s2p)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
45
38.0
°C/W
—
RθJB
Thermal resistance, junction to
board
33
39.6
°C/W
2
—
RθJC
Thermal resistance, junction to
case
20
27.3
°C/W
3
—
ΨJT
Thermal characterization
parameter, junction to package top
outside center (natural convection)
4
0.4
°C/W
4
—
ΨJB
Thermal characterization
parameter, junction to package
bottom (natural convection)
-
12.6
°C/W
5
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
5. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
3 Peripheral operating requirements and behaviors
3.1 Core modules
22
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 4. Serial wire clock input timing
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 5. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications
Table 18. IRC48M specification
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD
Supply current
—
400
500
µA
—
fIRC
Output frequency
—
48
—
MHz
—
Δfirc48m_ol_lv
Open loop total deviation of IRC48M
frequency at low voltage
(VDD=1.71V-1.89V) over temperature
—
± 0.5
± 1.5
%firc48m
Δfirc48m_ol_hv
Open loop total deviation of IRC48M
frequency at high voltage
(VDD=1.89V-3.6V) over temperature
—
± 0.5
± 1.0
%firc48m
1
1
Table continues on the next page...
24
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
Table 18. IRC48M specification (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Tj
Period jitter (RMS)
—
35
150
ps
—
Tsu
Startup time
—
2
3
µs
—
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean +/-3sigma).
Table 19. IRC8M/2M specification
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_2M
Supply current in 2 MHz mode
—
14
17
µA
—
IDD_8M
Supply current in 8 MHz mode
—
30
35
µA
—
fIRC_2M
Output frequency
—
2
—
MHz
—
fIRC_8M
Output frequency
—
8
—
MHz
—
fIRC_T_2M
Output frequency range (trimmed)
—
—
±3
%fIRC
—
fIRC_T_8M
Output frequency range (trimmed)
—
—
±3
%fIRC
—
Tsu_2M
Startup time
—
—
12.5
µs
—
Tsu_8M
Startup time
—
—
12.5
µs
—
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
25
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 6. IRC8M Frequency Drift vs Temperature curve
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 20. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
—
1.2
—
mA
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
Table 20. Oscillator DC electrical specifications (continued)
Symbol
Description
• 24 MHz
Min.
Typ.
Max.
Unit
—
1.5
—
mA
Notes
• 32 MHz
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
Cy
XTAL load capacitance
—
—
—
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
RS
2, 3
2, 3
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2
Symbol
Oscillator frequency specifications
Table 21. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
28
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
—
52
452
ms
1
Unit
Notes
thversblk128k Erase Block high-voltage time for 128 KB
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Symbol
Flash timing specifications — commands
Table 23. Flash command timing specifications
Description
Min.
Typ.
Max.
Read 1s Block execution time
trd1blk128k
• 128 KB program flash
1
—
—
1.7
ms
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
Erase Flash Block execution time
tersblk128k
• 128 KB program flash
2
—
88
600
ms
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
175
1300
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tersallu
Erase All Blocks Unsecure execution time
—
175
1300
ms
2
tpgmonce
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4.1.3
Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 25. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
Using differential inputs can achieve better system accuracy than using single-end
inputs.
30
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
3.6.1.1
16-bit ADC operating conditions
Table 26. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
3
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
3
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 ×
VREFH
V
—
• All other modes
VREFL
—
• 16-bit mode
—
8
10
pF
—
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
kΩ
—
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
Analog source
resistance
(external)
VREFH
13-bit / 12-bit modes
4
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion ≤ 13-bit mode
clock frequency
1.0
—
24
MHz
5
fADCK
ADC conversion 16-bit mode
clock frequency
2.0
—
12.0
MHz
5
Crate
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
6
20.000
—
1200
ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
rate
No ADC hardware averaging
6
37.037
—
461.467
ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH can act as VREF_OUT when VREFV1 module is enabled.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 7. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Conditions1
Description
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK =
1/fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
IDDA_ADC Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
INL
See Reference Manual chapter for sample times
Total
unadjusted error
• 12-bit modes
—
±4
±6.8
• 3.6 V
3
3.3
3.6
V
2.1
2.8
3.6
V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
• Run mode
• Standby mode
VReg33out
Notes
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
42
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
3.8.3 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 36. SPI master mode timing on slew rate disabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Description
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
1
2 x tperiph
2048 x
tperiph
ns
2
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tperiph - 30
1024 x
tperiph
ns
—
Data setup time (inputs)
18
—
ns
—
tHI
Data hold time (inputs)
0
—
ns
—
8
tv
Data valid (after SPSCK edge)
—
15
ns
—
9
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 37. SPI master mode timing on slew rate enabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
tHI
Description
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
1
2 x tperiph
2048 x
tperiph
ns
2
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tperiph - 30
1024 x
tperiph
ns
—
Data setup time (inputs)
96
—
ns
—
Data hold time (inputs)
0
—
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
Table continues on the next page...
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 37. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol
8
tv
9
Description
Min.
Max.
Unit
Note
Data valid (after SPSCK edge)
—
52
ns
—
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
Rise time output
—
36
ns
—
tFO
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
SS1
(OUTPUT)
3
2
SPSCK
(CPOL=0)
(OUTPUT)
11
10
11
6
7
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
4
5
SPSCK
(CPOL=1)
(OUTPUT)
MISO
(INPUT)
10
5
MSB OUT2
BIT 6 . . . 1
9
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA = 0)
44
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
SS1
(OUTPUT)
2
3
SPSCK
(CPOL=0)
(OUTPUT)
5
SPSCK
(CPOL=1)
(OUTPUT)
5
6
MISO
(INPUT)
11
10
11
4
7
MSB IN2
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
10
PORT DATA MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI master mode timing (CPHA = 1)
Table 38. SPI slave mode timing on slew rate disabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Min.
Max.
Unit
Note
0
fperiph/4
Hz
1
4 x tperiph
—
ns
2
Enable lead time
1
—
tperiph
—
Enable lag time
1
—
tperiph
—
tperiph - 30
—
ns
—
Data setup time (inputs)
2.5
—
ns
—
tHI
Data hold time (inputs)
3.5
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tv
Data valid (after SPSCK edge)
—
31
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
13
1.
2.
3.
4.
38
Description
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 39. SPI slave mode timing on slew rate enabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
Enable lead time
4
tLag
Enable lag time
5
tWSPSCK
6
tSU
7
Frequency of operation
SPSCK period
Min.
Max.
Unit
Note
0
fperiph/4
Hz
1
4 x tperiph
—
ns
2
1
—
tperiph
—
1
—
tperiph
—
tperiph - 30
—
ns
—
Data setup time (inputs)
2
—
ns
—
tHI
Data hold time (inputs)
7
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tv
Data valid (after SPSCK edge)
—
122
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
36
ns
—
tFO
Fall time output
13
1.
2.
3.
4.
Description
Clock (SPSCK) high or low time
For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
SS
(INPUT)
2
12
13
12
13
4
SPSCK
(CPOL=0)
(INPUT)
5
3
SPSCK
(CPOL=1)
(INPUT)
5
9
8
MISO
(OUTPUT)
see
note
SLAVE MSB
6
MOSI
(INPUT)
10
11
11
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined
Figure 16. SPI slave mode timing (CPHA = 0)
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Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
SS
(INPUT)
4
2
3
SPSCK
(CPOL=0)
(INPUT)
5
SPSCK
(CPOL=1)
(INPUT)
5
see
note
SLAVE
8
MSB OUT
6
MOSI
(INPUT)
13
12
13
11
10
MISO
(OUTPUT)
12
9
BIT 6 . . . 1
SLAVE LSB OUT
BIT 6 . . . 1
LSB IN
7
MSB IN
NOTE: Not defined
Figure 17. SPI slave mode timing (CPHA = 1)
3.8.4 I2C
3.8.4.1
Inter-Integrated Circuit Interface (I2C) timing
Table 40. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
Unit
SCL Clock Frequency
fSCL
0
100
0
4001
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
µs
LOW period of the SCL clock
tLOW
4.7
—
1.25
—
µs
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
µs
Data hold time for I2C bus devices
tHD; DAT
02
3.453
04
0.92
µs
tSU; DAT
2505
—
1003, 6
Data set-up time
Rise time of SDA and SCL signals
tr
—
1000
—
ns
7
300
ns
6
20 +0.1Cb
Fall time of SDA and SCL signals
tf
—
300
20 +0.1Cb
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
47
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high
drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
2
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
To achieve 1MHz I2C clock rates, consider the following recommendations:
• To counter the effects of clock stretching, the I2C baud Rate select bits can be
configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the
SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
Table 41. I 2C 1Mbit/s timing
Characteristic
Symbol
Minimum
Maximum
Unit
MHz
SCL Clock Frequency
fSCL
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
µs
LOW period of the SCL clock
tLOW
0.5
—
µs
HIGH period of the SCL clock
tHIGH
0.26
—
µs
Set-up time for a repeated START condition
tSU; STA
0.26
—
µs
Data hold time for I2C bus devices
tHD; DAT
0
—
µs
Data set-up time
tSU; DAT
50
—
ns
Rise time of SDA and SCL signals
tr
20 +0.1Cb
120
ns
Fall time of SDA and SCL signals
tf
20 +0.1Cb
2
120
ns
Set-up time for STOP condition
tSU; STO
0.26
—
µs
Bus free time between STOP and START condition
tBUF
0.5
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
48
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
SDA
tf
tSU; DAT
tr
tLOW
tf
tHD; STA
tr
tSP
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
tSU; STO
SR
P
S
Figure 18. Timing definition for devices on the I2C bus
3.8.5 UART
See General switching specifications.
3.8.6 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks
are driven) and slave mode (clocks are input). All timing is given for noninverted
serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame
sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame
sync have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
3.8.6.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 42. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15.5
ns
Table continues on the next page...
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
49
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 42. I2S/SAI master mode timing (continued)
Num.
Characteristic
Min.
Max.
Unit
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
19
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
26
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 19. I2S/SAI timing — master modes
Table 43. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
33
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
—
ns
10
Table continues on the next page...
50
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
Table 43. I2S/SAI slave mode timing (continued)
Num.
S18
Characteristic
Min.
I2S_RXD hold after I2S_RX_BCLK
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
Max.
Unit
2
—
ns
—
28
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 20. I2S/SAI timing — slave modes
3.8.6.2
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 44. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
Table continues on the next page...
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
51
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 44. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
S1
0
S2
Max.
Unit
—
ns
—
ns
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 21. I2S/SAI timing — master modes
Table 45. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
87
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
52
Freescale Semiconductor, Inc.
valid1
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Peripheral operating requirements and behaviors
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S14
S15
S19
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 22. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 LCD electrical characteristics
Table 46. LCD electricals
Symbol
fFrame
Description
Min.
Typ.
Max.
Unit
• GCR[FFR]=0
23.3
—
73.1
Hz
• GCR[FFR]=1
46.6
—
146.2
Hz
Notes
LCD frame frequency
CLCD
LCD charge pump capacitance — nominal
value
—
100
—
nF
CBYLCD
LCD bypass capacitance — nominal value
—
100
—
nF
1
CGlass
LCD glass capacitance
—
2000
8000
pF
2
VIREG
VIREG
V
3
• RVTRIM=0000
—
0.91
—
• RVTRIM=1000
—
0.92
—
• RVTRIM=0100
—
0.93
—
• RVTRIM=1100
—
0.94
—
• RVTRIM=0010
—
0.96
—
• RVTRIM=1010
—
0.97
—
• RVTRIM=0110
—
0.98
—
Table continues on the next page...
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
53
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 46. LCD electricals (continued)
Symbol
Description
Min.
Typ.
Max.
• RVTRIM=1110
—
0.99
—
• RVTRIM=0001
—
1.01
—
• RVTRIM=1001
—
1.02
—
• RVTRIM=0101
—
1.03
—
• RVTRIM=1101
—
1.05
—
• RVTRIM=0011
—
1.06
—
• RVTRIM=1011
—
1.07
—
• RVTRIM=0111
—
1.08
—
• RVTRIM=1111
—
1.09
—
Unit
ΔRTRIM
VIREG TRIM resolution
—
—
3.0
% VIREG
IVIREG
VIREG current adder — RVEN = 1
—
1
—
µA
IRBIAS
RBIAS current adder
—
10
—
µA
—
1
—
µA
—
0.28
—
MΩ
—
2.98
—
MΩ
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
RRBIAS
Notes
RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
VLL1
VLL1 voltage
—
—
VIREG
V
4
VLL2
VLL2 voltage
—
—
2 x VIREG
V
4
VLL3
VLL3 voltage
—
—
3 x VIREG
V
4
VLL1
VLL1 voltage
—
—
VDDA / 3
V
5
VLL2
VLL2 voltage
—
—
VDDA / 1.5
V
5
VLL3
VLL3 voltage
—
—
VDDA
V
5
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. VLL1, VLL2 and VLL3 are a function of VIREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump
is enabled (GCR[CPSEL]=1).
5. VLL1, VLL2 and VLL3 are a function of VDDA only under either of the following conditions:
• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = VDDA
through the internal power switch (GCR[VSUPPLY]=0).
• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is
connected to VDDA externally (GCR[VSUPPLY]=1).
54
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Dimensions
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
64-pin LQFP
98ASS23234W
64-pin MAPBGA
98ASA00420D
5 Pinouts and Packaging
5.1 KL43 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
VREFH can act as VREF_OUT when VREFV1 module is
enabled.
64
64
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
A1
1
PTE0
DISABLED
LCD_P48
PTE0/
CLKOUT32K
SPI1_MISO
LPUART1_TX RTC_CLKOUT CMP0_OUT
I2C1_SDA
LCD_P48
B1
2
PTE1
DISABLED
LCD_P49
PTE1
SPI1_MOSI
LPUART1_RX
I2C1_SCL
LCD_P49
—
3
VDD
VDD
VDD
C4
4
VSS
VSS
VSS
E1
5
USB0_DP
USB0_DP
USB0_DP
D1
6
USB0_DM
USB0_DM
USB0_DM
E2
7
VOUT33
VOUT33
VOUT33
D2
8
VREGIN
VREGIN
VREGIN
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
SPI1_MISO
55
Freescale Semiconductor, Inc.
Pinouts and Packaging
64
64
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
G1
9
PTE20
ADC0_DP0/
ADC0_SE0
LCD_P59/
ADC0_DP0/
ADC0_SE0
PTE20
TPM1_CH0
LPUART0_TX
FXI00_D4
LCD_P59
F1
10
PTE21
ADC0_DM0/
ADC0_SE4a
LCD_P60/
ADC0_DM0/
ADC0_SE4a
PTE21
TPM1_CH1
LPUART0_RX
FXIO0_D5
LCD_P60
G2
11
PTE22
ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
PTE22
TPM2_CH0
UART2_TX
FXIO0_D6
F2
12
PTE23
ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
PTE23
TPM2_CH1
UART2_RX
FXIO0_D7
F4
13
VDDA
VDDA
VDDA
G4
14
VREFH
VREFH
VREFH
G3
15
VREFL
VREFL
VREFL
F3
16
VSSA
VSSA
VSSA
H1
17
PTE29
CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29
TPM0_CH2
TPM_CLKIN0
H2
18
PTE30
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
PTE30
TPM0_CH3
TPM_CLKIN1
H3
19
PTE31
DISABLED
PTE31
TPM0_CH4
H4
20
PTE24
DISABLED
PTE24
TPM0_CH0
I2C0_SCL
H5
21
PTE25
DISABLED
PTE25
TPM0_CH1
I2C0_SDA
D3
22
PTA0
SWD_CLK
PTA0
TPM0_CH5
D4
23
PTA1
DISABLED
PTA1
LPUART0_RX TPM2_CH0
E5
24
PTA2
DISABLED
PTA2
LPUART0_TX TPM2_CH1
D5
25
PTA3
SWD_DIO
PTA3
I2C1_SCL
TPM0_CH0
SWD_DIO
G5
26
PTA4
NMI_b
PTA4
I2C1_SDA
TPM0_CH1
NMI_b
F5
27
PTA5
DISABLED
PTA5
USB_CLKIN
TPM0_CH2
I2S0_TX_
BCLK
LPUART1_TX LPTMR0_
ALT1
SWD_CLK
H6
28
PTA12
DISABLED
PTA12
TPM1_CH0
I2S0_TXD0
G6
29
PTA13
DISABLED
PTA13
TPM1_CH1
I2S0_TX_FS
G7
30
VDD
VDD
VDD
H7
31
VSS
VSS
VSS
H8
32
PTA18
EXTAL0
EXTAL0
PTA18
LPUART1_RX TPM_CLKIN0
G8
33
PTA19
XTAL0
XTAL0
PTA19
LPUART1_TX TPM_CLKIN1
F8
34
PTA20
RESET_b
F7
35
PTB0/
LLWU_P5
LCD_P0/
ADC0_SE8
LCD_P0/
ADC0_SE8
PTB0/
LLWU_P5
I2C0_SCL
TPM1_CH0
LCD_P0
F6
36
PTB1
LCD_P1/
ADC0_SE9
LCD_P1/
ADC0_SE9
PTB1
I2C0_SDA
TPM1_CH1
LCD_P1
E7
37
PTB2
LCD_P2/
ADC0_SE12
LCD_P2/
ADC0_SE12
PTB2
I2C0_SCL
TPM2_CH0
LCD_P2
56
Freescale Semiconductor, Inc.
PTA20
LPTMR0_
ALT1
RESET_b
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Pinouts and Packaging
64
64
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
E8
38
PTB3
LCD_P3/
ADC0_SE13
LCD_P3/
ADC0_SE13
PTB3
I2C0_SDA
TPM2_CH1
E6
39
PTB16
LCD_P12
LCD_P12
PTB16
SPI1_MOSI
LPUART0_RX TPM_CLKIN0
SPI1_MISO
LCD_P12
D7
40
PTB17
LCD_P13
LCD_P13
PTB17
SPI1_MISO
LPUART0_TX TPM_CLKIN1
SPI1_MOSI
LCD_P13
D6
41
PTB18
LCD_P14
LCD_P14
PTB18
TPM2_CH0
I2S0_TX_
BCLK
LCD_P14
C7
42
PTB19
LCD_P15
LCD_P15
PTB19
TPM2_CH1
I2S0_TX_FS
LCD_P15
D8
43
PTC0
LCD_P20/
ADC0_SE14
LCD_P20/
ADC0_SE14
PTC0
EXTRG_IN
audioUSB_
SOF_OUT
C6
44
PTC1/
LLWU_P6/
RTC_CLKIN
LCD_P21/
ADC0_SE15
LCD_P21/
ADC0_SE15
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
B7
45
PTC2
LCD_P22/
ADC0_SE11
LCD_P22/
ADC0_SE11
PTC2
C8
46
PTC3/
LLWU_P7
LCD_P23
LCD_P23
PTC3/
LLWU_P7
E3
47
VSS
VSS
VSS
E4
—
VDD
VDD
VDD
C5
48
VLL3
VLL3
VLL3
A6
49
VLL2
VLL2
VLL2/
LCD_P4
PTC20
LCD_P4
B5
50
VLL1
VLL1
VLL1/
LCD_P5
PTC21
LCD_P5
B4
51
VCAP2
VCAP2
VCAP2/
LCD_P6
PTC22
LCD_P6
A5
52
VCAP1
VCAP1
VCAP1/
LCD_P39
PTC23
LCD_P39
B8
53
PTC4/
LLWU_P8
LCD_P24
LCD_P24
PTC4/
LLWU_P8
SPI0_SS
LPUART1_TX TPM0_CH3
A8
54
PTC5/
LLWU_P9
LCD_P25
LCD_P25
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
I2S0_RXD0
A7
55
PTC6/
LLWU_P10
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
PTC6/
LLWU_P10
SPI0_MOSI
EXTRG_IN
I2S0_RX_
BCLK
SPI0_MISO
B6
56
PTC7
LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7
SPI0_MISO
audioUSB_
SOF_OUT
I2S0_RX_FS
SPI0_MOSI
C3
57
PTD0
LCD_P40
LCD_P40
PTD0
SPI0_SS
TPM0_CH0
FXI00_D0
LCD_P40
A4
58
PTD1
LCD_P41/
ADC0_SE5b
LCD_P41/
ADC0_SE5b
PTD1
SPI0_SCK
TPM0_CH1
FXIO0_D1
LCD_P41
C2
59
PTD2
LCD_P42
LCD_P42
PTD2
SPI0_MOSI
UART2_RX
TPM0_CH2
SPI0_MISO
FXIO0_D2
LCD_P42
B3
60
PTD3
LCD_P43
LCD_P43
PTD3
SPI0_MISO
UART2_TX
TPM0_CH3
SPI0_MOSI
FXIO0_D3
LCD_P43
A3
61
PTD4/
LLWU_P14
LCD_P44
LCD_P44
PTD4/
LLWU_P14
SPI1_SS
UART2_RX
TPM0_CH4
FXI00_D4
LCD_P44
C1
62
PTD5
LCD_P45/
ADC0_SE6b
LCD_P45/
ADC0_SE6b
PTD5
SPI1_SCK
UART2_TX
TPM0_CH5
FXIO0_D5
LCD_P45
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
LCD_P3
CMP0_OUT
I2S0_TXD0
LCD_P20
TPM0_CH0
I2S0_TXD0
LCD_P21
I2C1_SDA
TPM0_CH1
I2S0_TX_FS
LCD_P22
SPI1_SCK
LPUART1_RX TPM0_CH2
I2S0_TX_
BCLK
LCD_P23
CLKOUT
I2S0_MCLK
LCD_P24
CMP0_OUT
LCD_P25
I2S0_MCLK
LCD_P26
LCD_P27
57
Freescale Semiconductor, Inc.
Pinouts and Packaging
64
64
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
B2
63
PTD6/
LLWU_P15
LCD_P46/
ADC0_SE7b
LCD_P46/
ADC0_SE7b
PTD6/
LLWU_P15
SPI1_MOSI
LPUART0_RX
SPI1_MISO
FXIO0_D6
LCD_P46
A2
64
PTD7
LCD_P47
LCD_P47
PTD7
SPI1_MISO
LPUART0_TX
SPI1_MOSI
FXIO0_D7
LCD_P47
5.2 KL43 Family Pinouts
Figure below shows the 64 LQFP pinouts
58
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VCAP1
VCAP2
VLL1
VLL2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pinouts and Packaging
PTB18
PTE20
9
40
PTB17
PTE21
10
39
PTB16
PTE22
11
38
PTB3
PTE23
12
37
PTB2
VDDA
13
36
PTB1
VREFH
14
35
PTB0/LLWU_P5
VREFL
15
34
PTA20
VSSA
16
33
PTA19
PTA18
32
41
31
8
VSS
VREGIN
30
PTB19
VDD
42
29
7
PTA13
VOUT33
28
PTC0
PTA12
43
27
6
PTA5
USB0_DM
26
PTC1/LLWU_P6/RTC_CLKIN
PTA4
44
25
5
PTA3
USB0_DP
24
PTC2
PTA2
45
23
4
PTA1
VSS
22
PTC3/LLWU_P7
PTA0
46
21
3
PTE25
VDD
20
VSS
PTE24
47
19
2
PTE31
PTE1
18
VLL3
PTE30
48
17
1
PTE29
PTE0
Figure 23. 64 LQFP Pinout diagram
Figure below shows the 64 MAPBGA pinouts
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
59
Freescale Semiconductor, Inc.
Ordering parts
1
2
3
4
5
6
A
PTE0
PTD7
PTD4/
LLWU_P14
PTD1
VCAP1
VLL2
B
PTE1
PTD6/
LLWU_P15
PTD3
VCAP2
VLL1
PTC7
C
PTD5
PTD2
PTD0
VSS
VLL3
D
USB0_DM
VREGIN
PTA0
PTA1
E
USB0_DP
VOUT33
VSS
F
PTE21
PTE23
G
PTE20
H
7
8
PTC6/
PTC5/
LLWU_P10 LLWU_P9
A
PTC2
PTC4/
LLWU_P8
B
PTC1/
LLWU_P6/
RTC_CLKIN
PTB19
PTC3/
LLWU_P7
C
PTA3
PTB18
PTB17
PTC0
D
VDD
PTA2
PTB16
PTB2
PTB3
E
VSSA
VDDA
PTA5
PTB1
PTB0/
LLWU_P5
PTA20
F
PTE22
VREFL
VREFH
PTA4
PTA13
VDD
PTA19
G
PTE29
PTE30
PTE31
PTE24
PTE25
PTA12
VSS
PTA18
H
1
2
3
4
5
6
7
8
Figure 24. 64 MAPBGA Pinout diagram
6 Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the Web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers:
7 Part identification
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Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 47. Part number fields descriptions
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
Kinetis family
• KL43
A
Key attribute
• Z = Cortex-M0+
FFF
Program flash memory size
• 128 = 128 KB
• 256 = 256 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
CC
Maximum CPU frequency (MHz)
• 4 = 48 MHz
N
Packaging type
• R = Tape and reel
7.4 Example
This is an example part number:
MKL43Z256VLH4
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
Terminology and guidelines
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
Term
Rating
Definition
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
62
Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Terminology and guidelines
8.2 Examples
EX
AM
PL
E
Operating rating:
EX
AM
PL
E
Operating requirement:
EX
A
M
PL
E
Operating behavior that includes a typical value:
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
Revision History
8.4 Relationship between ratings and operating requirements
nt
me
n.)
mi
g(
n
ati
gr
tin
era
ng
i
rat
e
Op
Op
)
in.
(m
e
uir
req
(m
nt
me
t
era
Op
ing
.)
ax
e
uir
req
ing
rat
ing
t
a
er
.)
ax
(m
Op
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
)
in.
(m
ng
ati
gr
n
i
l
d
lin
nd
Ha
ng
ati
gr
.)
ax
(m
n
Ha
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
9 Revision History
The following table provides a revision history for this document.
Table 48. Revision History
Rev. No.
Date
3
09 August
2014
4
03 March
2015
Substantial Changes
Initial Public release
• Updated Table 9 - Power consumption operating behaviors.
• Updated the features and completed the ordering information.
• Removed thickness dimension from package diagrams.
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
Revision History
Table 48. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Updated Related Resources table to include Chip Errata resource name and Package
Drawing part numbers in the respective rows.
• Updated Table 7. Voltage and current operating behaviors.
• Specified correct max. value for IIN.
• Updated Table - 9 Power consumption operating behaviors.
• Rows added for IDD for reset pin hold low (IDD_RESET_LOW) at 1.7V and 3V.
• Measurement unit updated for IDD_VLLS1 from nA to μA.
• Footnote 1 was moved in the beginning of the table as text.
• Added Table - 11 EMC radiated emissions operating behaviors for 64-pin LQFP
package under section 2.2.6.
• Updated Table - 18 (IRC48M specification) and Table - 19 (IRC8M/2M specification)
under section 3.3.1 - 'MCG-Lite specifications'.
• Removed supply voltage (VDD), temperature range (T), untrimmed (fIRC_UT), trim
function (ΔfIRC_C, ΔfIRC_F) data from Table - 18 (IRC48M specification).
• Removed supply voltage (VDD), temperature range (T) data from Table - 19
(IRC8M/2M specification).
• Added Figure 6. IRC8M Frequency Drift vs Temperature curve after Table - 19
(IRC8M/2M specification).
• Updated Table 29. VREF full-range operating behaviors.
• Removed Ac(Aging coefficient) row.
• Added Tchop_osc_stup parameter.
• Updated typical value of the Vout parameter.
• Added tables: "I2C timing" and "I2C 1Mbit/s timing" under section - I2C.
• Added VREF specifications (VREFH and VREFL) to Table 26. 16-bit ADC operating
conditions.
• Removed note: “This device does not have the USB_CLKIN signal available.”
5
12 August
2015
• In Table 9. Power consumption operating behaviors:
• Updated Max. values of IDD_WAIT, IDD_VLPW, IDD_STOP, IDD_VLPS, IDD_LLS,
IDD_VLLS3, IDD_VLLS1, IDD_VLLS0.
• Modified unit of IDD_VLLS0 from nA to μA.
• Removed IDD_RESET_LOW information.
• In Table 13. Device clock specifications, added a footnote for normal run mode.
• In Table 15. Thermal operating requirements, modified the footnote for Ambient
temperature.
• In Table 18. IRC48M specification, removed fIRC_T data and added Δfirc48m_of_lv and
Δfirc48m_of_hv specifications.
• In Table 26. 16-bit ADC operating conditions, updated Max. value of fADCK and Crate.
Kinetis KL43 Microcontroller, Rev.5, 08/2015.
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Freescale Semiconductor, Inc.
How to Reach Us:
Home Page:
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Web Support:
freescale.com/support
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, the Freescale logo, Energy Efficient Solutions logo, and
Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat.
& Tm. Off. All other product or service names are the property of their
respective owners. ARM and Cortex are registered trademarks of ARM
Limited (or its subsidiaries) in the EU and/or elsewhere. All rights
reserved.
©2014-2015 Freescale Semiconductor, Inc.
Document Number KL43P64M48SF6
Revision 5, 08/2015
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