NXP Semiconductors
Data Sheet: Technical Data
KV11P64M75
Rev. 6, 10/2020
Kinetis V Series KV10 and KV11,
128/64 KB Flash
75 MHz Cortex-M0+ Based Microcontroller
The Kinetis V Series KV11x MCU family is built on Arm®
Cortex®-M0+ core and enabled by innovative 90nm thin film
storage (TFS) flash process technology. The KV11x is an
extension of the existing KV10x family providing increased
memory, higher pin count, additional FTMs and a FlexCAN serial
interface.
• Dual 16-bit ADCs sampling at up to 1.2 MS/s in 12-bit
mode
• Highly accurate and flexible motor control timers
• Ideal for industrial motor control applications, inverters, and
low-end power conversion applications
MKV11Z128VXX7
MKV11Z64VXX7
MKV10Z64VXX7
MKV10Z128VXX7
32 QFN
64 LQFP
5 x 5 x 1.23 mm Pitch 10 x 10 x 1.4 mm Pitch
0.5 mm
0.5 mm
32 LQFP
7 x 7 x 1.4 mm Pitch
0.8 mm
Performance
• Up to 75 MHz Arm Cortex-M0+ based core
Memories and memory interfaces
• Up to 128 KB of program flash memory
• Up to 16 KB of RAM
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• 8-channel DMA controller
• SWD interface and Micro Trace buffer
• Bit Manipulation Engine (BME)
• External watchdog timer
• Advanced independent clocked watchdog
• Memory Mapped Divide and Square Root (MMDVSQ)
module
Clocks
• 32-40 kHz or 4-32 MHz external crystal oscillator
• Multipurpose clock generator (MCG) with frequencylocked loop referencing either internal or external
reference clock
Security and integrity modules
• 80-bit unique identification (ID) number per chip
• Hardware CRC module
48 LQFP
7 x 7 x 1.4 mm Pitch
0.5 mm
Communication interfaces
• One 16-bit SPI module
• One I2C module
• Two UART modules
• One FlexCAN module1
Timers
• Programmable delay block
• Two 6-channel FlexTimers (FTM) for motor control/
general purpose applications
• Four 2-channel FlexTimers (FTM) with quadrature
decoder functionality
• 16-bit low-power timer (LPTMR)
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Analog modules
• Two 16-bit SAR ADCs
• 12-bit DAC
• Two analog comparators (ACMP) containing a 6-bit
DAC and programmable reference input
Human-machine interface
• General-purpose I/O
1. Available only on KV11 parts
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Part Number 1
Memory
FlexCAN
Maximum number of
I\O's
Flash (KB)
SRAM (KB)
128
16
Yes
46
128
16
Yes
35
128
16
Yes
26
MKV11Z128VFM7
128
16
Yes
26
MKV11Z64VLH7
64
16
Yes
46
64
16
Yes
35
64
16
Yes
26
MKV11Z64VFM7
64
16
Yes
26
MKV10Z64VLH7
64
16
No
46
64
16
No
35
64
16
No
26
MKV10Z64VFM7
128
16
No
26
MKV10Z128VLH7
128
16
No
46
128
16
No
35
128
16
No
26
128
16
No
26
MKV11Z128VLH7
MKV11Z128VLF7
MKV11Z128VLC7
2
MKV11Z64VLF7
MKV11Z64VLC7
2
MKV10Z64VLF7
MKV10Z64VLC7
2
MKV10Z128VLF7
MKV10Z128VLC7
2
MKV10Z128VFM7
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
2. The 32-pin LQFP package supporting this part number is not yet available, however it is included in a Package Your
Way program for Kinetis MCUs. Please visit http://www.nxp.com/KPYW for more details.
Related Resources
Type
Description
Resource
Product
Selector
The Product Selector is a web-based tool to assist in selecting the MCU
product for your application.
Product Selector
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KV10PB 1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KV10P48M75RM 1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document
Chip Errata
The chip mask set Errata provides additional or corrective information for
a particular device mask set.
• KV10Z_1N81H1
• KINETIS_V_0N63P1
Package
drawing
Package dimensions are provided in package drawings.
• QFN 32-pin:
98ASA00473D1
• LQFP 32-pin:
98ASH70029A1
• LQFP 48-pin:
98ASH00962A1
• LQFP 64-pin:
98ASS23234W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
LEGEND
Not available on all parts. See ordering information table.
Figure 1. KV11 block diagram
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................8
2.2.3 Voltage and current operating behaviors.............9
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 KV11x Power consumption operating behaviors.10
2.2.6 EMC radiated emissions operating behaviors..... 16
2.2.7 Designing with radiated emissions in mind..........17
2.2.8 Capacitance attributes.........................................17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications..................................17
2.3.2 General switching specifications......................... 18
2.4 Thermal specifications..................................................... 19
2.4.1 Thermal operating requirements......................... 19
2.4.2 Thermal attributes................................................19
3 Peripheral operating requirements and behaviors.................. 20
3.1 Core modules.................................................................. 20
3.1.1 SWD Electricals ..................................................20
3.2 System modules.............................................................. 21
3.3 Clock modules................................................................. 21
3.3.1 MCG specifications..............................................21
3.3.2 Oscillator electrical specifications........................23
3.4 Memories and memory interfaces................................... 25
3.4.1 Flash electrical specifications.............................. 25
3.5 Security and integrity modules........................................ 27
3.6 Analog............................................................................. 27
3.6.1
ADC electrical specifications............................... 27
4
NXP Semiconductors
4
5
6
7
8
3.6.2 CMP and 6-bit DAC electrical specifications....... 31
3.6.3 12-bit DAC electrical characteristics....................33
3.7 Timers..............................................................................36
3.8 Communication interfaces............................................... 36
3.8.1 DSPI switching specifications (limited voltage
range).................................................................. 36
3.8.2 DSPI switching specifications (full voltage
range).................................................................. 39
3.8.3 I2C....................................................................... 43
3.8.4 UART...................................................................43
Dimensions............................................................................. 43
4.1 Obtaining package dimensions....................................... 43
Pinout...................................................................................... 44
5.1 KV11 Signal Multiplexing and Pin Assignments.............. 44
5.2 KV11 Pinouts................................................................... 47
Ordering parts......................................................................... 50
6.1 Determining valid orderable parts....................................50
Part identification.....................................................................50
7.1 Description.......................................................................51
7.2 Format............................................................................. 51
7.3 Fields............................................................................... 51
7.4 Example...........................................................................51
Terminology and guidelines.................................................... 52
8.1 Definition: Operating requirement....................................52
8.2 Definition: Operating behavior......................................... 52
8.3 Definition: Attribute.......................................................... 52
8.4 Definition: Rating............................................................. 53
8.5 Result of exceeding a rating............................................ 53
8.6 Relationship between ratings and operating
requirements....................................................................54
8.7 Guidelines for ratings and operating requirements..........54
8.8 Definition: Typical value...................................................55
8.9 Typical Value Conditions................................................. 56
9 Revision history.......................................................................56
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human-body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105 °C
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
1.4 Voltage and current operating ratings
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
5
NXP Semiconductors
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
VIO
ID
VDDA
0.31
mA
Digital pin input voltage (except open drain pins)
–0.3
VDD +
Open drain pins (PTC6 and PTC7)
–0.3
5.5
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
Analog supply voltage
V
1. Maximum value of VIO (except open drain pins) must be 3.8 V.
2 General
Electromagnetic compatibility (EMC) performance depends on the environment in
which the MCU resides. Board design and layout, circuit topology choices, location,
characteristics of external components, and MCU software operation play a significant
role in EMC performance.
See the following applications notes available on nxp.com for guidelines on optimizing
EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
6
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
General
Input Signal
High
Low
VIH
80%
50%
20%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.71 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.71 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VIH
VIL
Notes
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
Pin negative DC injection current—single pin
• VIN < VSS–0.3V
1
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
7
NXP Semiconductors
General
Table 1. Voltage and current operating requirements (continued)
Symbol
IICcont
Description
Contiguous pin DC injection current—regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
VRAM
VDD voltage required to retain RAM
Min.
Max.
Unit
–25
—
mA
1.2
—
V
Notes
1. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed, then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/IICIO.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
±60
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
±40
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
8
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
General
2.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
Min.
Max.
Unit
VDD – 0.5
—
V
VDD – 0.5
—
V
VDD – 0.5
—
V
VDD – 0.5
—
V
—
100
mA
—
0.5
V
—
0.5
V
—
0.5
V
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
1
IIN
Input leakage current (total all pins) for full
temperature range
—
41
μA
1
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
VOH
Description
Notes
Output high voltage — Normal drive pad
All port pins, except PTC6 and PTC7
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VOH
Output high voltage — High drive pad
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6,
PTD7 pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
IOHT
Output high current total for all ports
VOL
Output low voltage — Normal drive pad
All port pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
VOL
Output low voltage — High drive pad
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6,
PTD7 pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
IOLT
2
1. Measured at VDD = 3.6 V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
9
NXP Semiconductors
General
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 75 MHz
• Bus and flash clock = 25 MHz
• FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
—
123
132
μs
—
123
132
μs
—
67
72
μs
—
4
5
μs
—
4
5
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
1. Normal boot FTFA_FOPT[LPBOOT]=11
2.2.5 KV11x Power consumption operating behaviors
Table 5. KV11x power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
—
—
5
mA
Run mode current — all peripheral clocks
disabled, code executing from flash
• at 1.8 V 50 MHz (25 MHz Bus)
• at 3.0 V 50 MHz (25 MHz Bus)
• at 1.8 V 75 MHz (25 MHz Bus)
• at 3.0 V 75 MHz (25 MHz Bus)
IDD_RUN
Min.
Notes
1
Target IDD
—
5.3
6.2
mA
—
5.4
6.3
mA
—
7.2
8.3
mA
—
7.3
8.3
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
Target IDD
Table continues on the next page...
10
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
General
Table 5. KV11x power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• at 1.8 V 50 MHz
—
8.5
9.7
mA
• at 3.0 V 50 MHz
—
8.5
9.8
mA
• at 1.8 V 75 MHz
—
11.6
13.0
mA
• at 3.0 V 75 MHz
—
11.7
13.2
mA
Notes
IDD_WAIT
Wait mode high frequency 75 MHz current at
3.0 V — all peripheral clocks disabled
—
4
—
mA
—
IDD_WAIT
Wait mode reduced frequency 50 MHz current
at 3.0 V — all peripheral clocks disabled
—
3.4
—
mA
—
IDD_VLPR
Very-Low-Power Run mode current 4 MHz at
3.0 V — all peripheral clocks disabled
—
268
—
μA
4 MHz CPU
speed, 1 MHz
bus speed.
IDD_VLPR
Very-Low-Power Run mode current 4 MHz at
3.0 V — all peripheral clocks enabled
—
437
—
μA
4 MHz CPU
speed, 1 MHz
bus speed.
IDD_VLPW Very-Low-Power Wait mode current at 3.0 V —
all peripheral clocks enabled
—
348.9
—
μA
4 MHz CPU
speed, 1 MHz
bus speed.
IDD_VLPW Very-Low-Power Wait mode current at 3.0 V —
all peripheral clocks disabled
—
173.4
—
μA
4 MHz CPU
speed, 1 MHz
bus speed.
IDD_STOP
Stop mode current at 3.0 V
• -40 °C to 25 °C
—
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-Low-Power Stop mode current at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-Low-Leakage Stop mode 3 current at 3.0
V
• -40 °C to 25 °C
—
247.2
286
—
260.7
300
—
286
312
—
324
353
—
422.7
494
μA
—
—
2.9
3
—
6.8
5.9
—
15.4
13
—
29.1
39
—
66.4
86
μA
μA
—
1.3
1.6
• at 50 °C
—
2
2.3
• at 70 °C
—
3.7
4.3
• at 85 °C
—
6.7
7.5
• at 105 °C
—
15.1
16
IDD_VLLS1 Very-Low-Leakage Stop mode 1 current at 3.0
V
μA
—
—
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
11
NXP Semiconductors
General
Table 5. KV11x power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
• -40°C to 25°C
—
0.8
1.2
• at 50°C
—
1.2
1.4
• at 70°C
—
2.2
2.7
• at 85°C
—
4.0
5.1
• at 105°C
—
9.4
11.8
IDD_VLLS0 Very-Low-Leakage Stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
0.279
0.386
—
0.638
0.854
—
1.63
2.2
—
3.4
4.5
—
8.9
11.2
IDD_VLLS0 Very-Low-Leakage Stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
0.098
0.452
—
0.448
0.674
—
1.4
1.9
—
3.19
4.3
—
8.47
10.6
Unit
Notes
μA
—
μA
2
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. No brownout
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
Table continues on the next page...
12
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
entering all modes with the crystal
enabled.
VLLS1
VLLS3
Unit
-40
25
50
70
85
105
440
490
540
560
570
580
440
490
540
560
570
580
510
560
560
560
610
680
510
560
560
560
610
680
22
22
22
22
22
22
µA
66
66
66
66
66
66
µA
214
237
246
254
260
268
66
66
66
66
66
66
214
237
246
254
260
268
66
66
66
66
66
66
214
237
246
254
260
268
nA
VLPS
STOP
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
ISPI
SPI peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
II2C
I2C peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
IFTM
µA
µA
FTM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100Hz clock signal. No load
is placed on the I/O generating the
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
13
NXP Semiconductors
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
-40
clock signal. Includes selected clock
source and I/O switching currents.
25
50
70
Unit
85
105
µA
150
150
150
150
150
150
300
300
300
320
340
350
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
366
366
366
366
366
366
µA
IWDOG
WDOG peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
66
66
66
66
66
66
µA
214
237
246
254
260
268
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode (except for 75 MHz which is in FEE mode), and BLPE
for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
14
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
General
Figure 3. Run mode supply current vs. core frequency
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
15
NXP Semiconductors
General
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
15
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
17
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
12
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
4
dBμV
IEC level
0.15–1000
M
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
16
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
General
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 75 MHz, fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
48
MHz
fBUS
Bus clock
—
24
MHz
fFLASH
Flash clock
—
24
MHz
fLPTMR
LPTMR clock
—
24
MHz
High Speed run mode
fSYS
System and core clock
—
75
MHz
fBUS
Bus clock
—
25
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
17
NXP Semiconductors
General
Table 9. Device clock specifications (continued)
Symbol
fFTM
Description
FTM clock
Min.
Max.
Unit
—
75
MHz
Notes
VLPR mode
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
fFLASH
Flash clock
—
1
MHz
fLPTMR
LPTMR clock
—
25
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
—
16
MHz
—
16
MHz
fLPTMR_pin
fLPTMR_ERCL LPTMR external reference clock
K
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
3
Fast slew rate
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
—
8
ns
—
7
ns
—
15
ns
—
25
ns
Port rise and fall time
Slow slew rate
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. For high drive pins with high drive enabled, load is 75pF; other pins load (low drive) is 25pF.
18
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
General
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
TA
Description
Die junction temperature
Ambient temperature
1
Min.
Max.
Unit
–40
125
°C
–40
105
°C
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 12. Thermal attributes
Board type
Symb
ol
Single-layer
(1S)
RθJA
Four-layer
(2s2p)
RθJA
Description
64 LQFP
48
LQFP
32
LQFP
32
QFN
Unit
Notes
Thermal resistance,
junction to ambient
(natural convection)
64
81
85
98
°C/W
1
Thermal resistance,
junction to ambient
(natural convection)
46
57
57
34
°C/W
Single-layer
(1S)
RθJMA Thermal resistance,
junction to ambient (200
ft./min. air speed)
52
68
72
82
°C/W
Four-layer
(2s2p)
RθJMA Thermal resistance,
junction to ambient (200
ft./min. air speed)
39
51
50
28
°C/W
—
RθJB
Thermal resistance,
junction to board
28
35
33
14
°C/W
2
—
RθJC
Thermal resistance,
junction to case
15
25
25
2.5
°C/W
3
—
ΨJT
Thermal characterization
parameter, junction to
package top outside
center (natural
convection)
2
7
7
8
°C/W
4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
19
NXP Semiconductors
Peripheral operating requirements and behaviors
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD Electricals
Table 13. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 5. Serial wire clock input timing
20
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
Peripheral operating requirements and behaviors
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 6. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 14. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
—
± 0.3
± 0.6
%fdco
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
Notes
1
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
21
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
Δfdco_t
Δfdco_t
fintf_ft
Δfintf_ft
fintf_t
Min.
Typ.
Max.
Unit
Notes
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0 - 70 °C
—
± 0.4
± 1.5
%fdco
1, 2
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
4
—
MHz
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
—
+1/-2
±3
%fintf_ft
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
48
MHz
60
62.915
75
MHz
—
23.99
—
MHz
2
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS = 00,
DMX32 = 0)
3, 4
640 × ffll_ref
Mid range (DRS = 01,
DMX32 = 0)
1280 × ffll_ref
Mid range (DRS = 10,
DMX32 = 0)
1920 x ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS = 00,
DMX32 = 1)
5
6
732 × ffll_ref
Mid range (DRS = 01,
DMX32 = 1)
—
47.97
—
MHz
–
71.991
–
MHz
—
180
—
ps
7
—
—
1
ms
8
1464 × ffll_ref
Mid range (DRS = 10,
DMX32 = 1)
2197 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 75 MHz
tfll_acquire
FLL target frequency acquisition time
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
22
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
Peripheral operating requirements and behaviors
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or there is a change from FLL disabled (BLPE, BLPI) to FLL enabled
(FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 4 MHz
—
500
—
μA
• 8 MHz
—
600
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, lowpower mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
2, 4
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
23
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol
RS
Description
Min.
Typ.
Max.
Unit
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2
Symbol
Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Notes
1, 2
Table continues on the next page...
24
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
Peripheral operating requirements and behaviors
Table 16. Oscillator frequency specifications (continued)
Symbol
tcst
Description
Min.
Typ.
Max.
Unit
Notes
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
1000
—
ms
3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 17. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
104
904
ms
1
1. Maximum time based on expectations at cycling end-of-life.
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
25
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.1.2
Flash timing specifications — commands
Table 18. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec2k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
0.9
ms
1
trdonce
Read Once execution time
—
—
30
μs
1
tpgmonce
Program Once execution time
—
100
—
μs
—
tersall
Erase All Blocks execution time
—
140
1150
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3
Flash high voltage current behaviors
Table 19. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
12.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
8.0
mA
Reliability specifications
Table 20. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
26
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
ADC electrical specifications
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
3.6.1.1
16-bit ADC operating conditions
Table 21. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
• All other modes
VREFL
—
• 16-bit mode
—
8
10
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
CADIN
RADIN
RAS
Input
capacitance
Input resistance
Analog source
resistance
Notes
VREFH
pF
kΩ
13-bit / 12-bit modes
3
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion ≤ 13-bit mode
clock frequency
1.0
—
24.0
MHz
4
fADCK
ADC conversion 16-bit mode
clock frequency
2.0
—
12.0
MHz
4
Crate
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
5
20.000
—
1200
Ksps
Continuous conversions
enabled, subsequent
conversion time
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
27
NXP Semiconductors
ADC electrical specifications
Table 21. 16-bit ADC operating conditions (continued)
Symbol
Crate
Description
Conditions
Min.
ADC conversion 16-bit mode
rate
No ADC hardware averaging
Typ.1
Max.
Unit
Notes
5
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
ADC SAR
ENGINE
R ADIN
V ADIN
C AS
V AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 7. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
Conditions1.
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
Table continues on the next page...
28
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 6, 10/2020
ADC electrical specifications
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Description
ADC
asynchronous
clock source
fADACK
Conditions1.
• ADLPC = 1, ADHSC =
0
• ADLPC = 1, ADHSC =
1
• ADLPC = 0, ADHSC =
0
Min.
Typ.2
Max.
1.2
2.4
3.9
2.4
4.0
6.1
3.0
5.2
7.3
4.4
6.2
9.5
TUE
DNL
INL
EFS
EQ
ENOB
• 12-bit modes
—
±4
±6.8
•
工商网监
湘ICP备2023018690号
