NXP Semiconductors
Data Sheet: Technical Data
KV4XP100M168
Rev. 4, 09/2019
KV4x Data Sheet
MKV46FxxxVLy16
MKV44FxxxVLy16
MKV42FxxxVLy16
MKV46FxxxVLy16z
MKV42FxxxVLy16z
168 MHz Arm Cortex-M4 core based Microcontroller with
FPU
The Kinetis KV4x MCU family is a member of the Kinetis V
series and provides a high-performance solution for motor
control and Digital Power Conversion. Built upon the Arm®
Cortex®-M4 core operating at up to 168 MHz with DSP and
floating point unit, features include; dual 12-bit analog-to-digital
converters with 240ns conversion time, up to 30 PWM channels
for support of multi-motor systems, eFlexPWM module with 312
ps resolution for digital power conversion applications,
programmable delay block, memory protection unit, dual
FlexCAN modules and 64 to 256 KB of flash memory. KV4x
MCUs are offered in 48LQFP, 64LQFP, and 100LQFP
packages. All Kinetis V series MCUs are supported by a
comprehensive enablement suite from NXP and third-party
resources including reference designs, software libraries and
motor configuration tools.
Core
• Arm® Cortex®-M4 core up to 168 MHz with single
precision Floating Point Unit (FPU)
Memories
• Up to 256 KB of program flash memory
• Up to 32 KB of RAM
System peripherals
• 16-channel DMA controller
• Low-leakage wakeup unit
• SWD interface
• Advanced independent clocked watchdog
Clocks
• 32 to 40 kHz or 3 to 32 MHz crystal oscillator
• Multipurpose clock generator (MCG) with frequencylocked loop and phase-locked loop referencing either
internal or external reference clock
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
Human-machine interface
• General-purpose input/output
100 LQFP
64 LQFP
14 x 14 x 1.4 Pitch 0.5 10 x 10 x 1.4 Pitch 0.5
mm
mm
48 LQFP
7 x 7 x 1.4 Pitch 0.5 mm
Communication interfaces
• Two Universal Asynchronous Receiver/Transmitter
(UART) / FlexSCI modules with programmable 8- or
9-bit data format
• One 16-bit SPI module
• One I2C module
• Two FlexCAN modules
Analog Modules
• Two 12-bit cyclic ADCs
• Four analog comparator (CMP) containing a 6-bit
DAC and programmable reference input
• One 12-bit DAC
Timers
• One eFlexPWM with 4 sub-modules, providing 12
PWM outputs
• Two 8-channel FlexTimers (FTM0 and FTM3)
• One 2-channel FlexTimers (FTM1)
• Four Periodic interrupt timers (PIT)
• Two Programmable Delay Blocks (PDB)
• Quadrature Encoder/Decoder (ENC)
• Ratio of timer input clock frequency vs. core
frequency is 1:2 when core frequency is 168 Mhz,
and 1:1 when core frequency is less than or equal to
100 Mhz
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Security and integrity modules
• Hardware CRC module to support fast cyclic
redundancy checks
• External Watchdog Monitor (EWM)
Orderable part numbers summary1
NXP part
number
CPU
Pin
Total SRA
coun flash
M
freq
t
memo (KB)
uenc
ry
y
(KB)
(MHz
)
ADC
ADC
A
ADC
B
eFlexPWM
PW
MB
PW
M
Nan
oEdg
e
PW
MA
PW
MX
Flex Timers
FTM
0
FTM
3
FTM
1
DA
C
FlexCAN
CA
N0
CA
N1
MKV46F256VLL
16
168
100
256
32
18ch
20ch 1x8ch 1x4ch
Yes
1x8ch 1x8ch 1x2ch
1
1
1
MKV46F256VLH
16
168
64
256
32
13ch
16ch 1x8ch
Yes
1x8ch 1x8ch 1x2ch
1
1
1
MKV46F128VLL
16
168
100
128
24
18ch
20ch 1x8ch 1x4ch
Yes
1x8ch 1x8ch 1x2ch
1
1
1
MKV46F128VLH
16
168
64
128
24
13ch
16ch 1x8ch
Yes
1x8ch 1x8ch 1x2ch
1
1
1
MKV44F256VLL
16
168
100
256
32
18ch
20ch 1x8ch 1x4ch
Yes
—
—
—
1
1
1
MKV44F256VLH
16
168
64
256
32
13ch
16ch 1x8ch
Yes
—
—
—
1
1
1
MKV44F128VLL
16
168
100
128
24
18ch
20ch 1x8ch 1x4ch
Yes
—
—
—
1
1
1
MKV44F128VLH
16
168
64
128
24
13ch
16ch 1x8ch
—
Yes
—
—
—
1
1
1
MKV44F128VLF
16
168
48
128
24
11ch
10ch 1x8ch
—
Yes
—
—
—
1
1
—
MKV44F64VLH1
6
168
64
64
16
13ch
16ch 1x8ch
—
Yes
—
—
—
1
1
1
MKV44F64VLF1
6
168
48
64
16
11ch
10ch 1x8ch
—
Yes
—
—
—
1
1
—
MKV42F256VLL
16
168
100
256
32
18ch
20ch
—
—
—
1x8ch 1x8ch 1x2ch
—
1
1
MKV42F256VLH
16
168
64
256
32
13ch
16ch
—
—
—
1x8ch 1x8ch 1x2ch
—
1
1
MKV42F128VLL
16
168
100
128
24
18ch
20ch
—
—
—
1x8ch 1x8ch 1x2ch
—
1
1
MKV42F128VLH
16
168
64
128
24
13ch
16ch
—
—
—
1x8ch 1x8ch 1x2ch
—
1
1
MKV42F128VLF
16
168
48
128
24
11ch
10ch
—
—
—
1x8ch 1x8ch 1x2ch
—
1
—
MKV42F64VLH1
6
168
64
64
16
13ch
16ch
—
—
—
1x8ch 1x8ch 1x2ch
—
1
1
—
—
—
Table continues on the next page...
2
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Orderable part numbers summary1 (continued)
NXP part
number
CPU
Pin
Total SRA
coun flash
M
freq
t
memo (KB)
uenc
ry
y
(KB)
(MHz
)
MKV42F64VLF1
6
168
48
64
16
ADC
ADC
A
eFlexPWM
ADC
B
PW
MA
PW
MX
PW
MB
11ch
10ch
—
—
PW
M
Nan
oEdg
e
—
Flex Timers
FTM
0
FTM
3
FTM
1
1x8ch 1x8ch 1x2ch
DA
C
FlexCAN
CA
N0
CA
N1
1
—
—
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number
search.
Device Revision Number
Device Mask Set Number
SIM_SDID[REVID]
JTAG ID Register[PRN]
1N72K
0001
0001
Related Resources
Type
Description
Resource
Selector
Guide
The Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KV4XP100M168RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KV4XP100M1681
Chip Errata
The chip mask set Errata provides additional or corrective information
for a particular device mask set.
Kinetis_V_1N72K1
Package
drawing
Package dimensions are provided in package drawings.
• LQFP 100-pin:
98ASS23308W1
• LQFP 64-pin:
98ASS23234W1
• LQFP 48-pin:
98ASH00962A1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
KV4x Data Sheet, Rev. 4, 09/2019
3
NXP Semiconductors
MCG
Arm Cortex M4
32 kHz
RC
JTAG/SWD
3 2 -b it C P U
168 MHz
16 -ch
DMA
SPFPU
8 MHz
RC
PLL
100-240 MHz
Osc
Low range: 32 kHz
High range: 4-20 MHz
MCM
Crossbar switch (AXBS-Lite)
FMC
GPIO
Up to 70
32
RCM
SIM
PMC
128
Peripheral bridge
P-Flash
Up to 256 KB
SRAM
Up to 32 KB
eFlexPWM
8ch + 4ch
12 bit ADC
(4.1 MSPS)
nano-edge
1x 12 bit
DAC
FlexSCI
FlexSCI
12 bit ADC
(4.1 MSPS)
4 x HSCMP
with 6bit DAC
LPTMR
SPI
FlexTimer
8ch + 8ch +2ch
ENC
I2C
SMBUS
EWM
FlexCAN
x2
2 x PDB
WDOG
CRC
4 - ch PIT
IRQ
XBARA
XBARB
AOI
Figure 1. KV4x block diagram
4
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Table of Contents
1 Ratings.................................................................................. 6
1.1 Thermal handling ratings............................................... 6
1.2 Moisture handling ratings...............................................6
1.3 ESD handling ratings..................................................... 6
1.4 Voltage and current operating ratings............................6
1.5 Absolute Maximum Ratings........................................... 7
2 General................................................................................. 8
2.1 AC electrical characteristics...........................................8
2.2 Nonswitching electrical specifications............................9
2.2.1 Recommended Operating Conditions................9
2.2.2 LVD and POR operating requirements.............. 10
2.2.3 Voltage and current operating behaviors........... 10
2.2.4 Power mode transition operating behaviors.......11
2.2.5 Power consumption operating behaviors...........12
2.2.6 EMC radiated emissions operating behaviors... 17
2.2.7 Designing with radiated emissions in mind........ 18
2.2.8 Capacitance attributes....................................... 18
2.3 Switching specifications................................................. 18
2.3.1 Typical device clock specifications.................... 18
2.3.2 General switching specifications........................19
2.4 Thermal specifications................................................... 20
2.4.1 Thermal operating requirements........................20
2.4.2 Thermal attributes.............................................. 20
3 Peripheral operating requirements and behaviors................ 21
3.1 Core modules................................................................ 21
3.1.1 SWD Electricals ................................................ 21
3.1.2 JTAG electricals.................................................22
3.2 System modules............................................................ 25
3.3 Clock modules............................................................... 25
3.3.1 MCG specifications............................................ 25
3.3.2 Oscillator electrical specifications...................... 28
3.4 Memories and memory interfaces................................. 30
3.4.1 Flash electrical specifications............................ 30
3.5 Security and integrity modules.......................................31
3.6 Analog............................................................................31
3.6.1 12-bit cyclic Analog-to-Digital Converter (ADC)
parameters.........................................................31
KV4x Data Sheet, Rev. 4, 09/2019
4
5
6
7
8
3.6.2 CMP and 6-bit DAC electrical specifications......34
3.6.3 12-bit DAC electrical characteristics.................. 35
3.7 Timers............................................................................ 38
3.8 Enhanced NanoEdge PWM characteristics................... 38
3.9 Communication interfaces............................................. 39
3.9.1 SPI (DSPI) switching specifications (limited
voltage range).................................................... 39
3.9.2 SPI (DSPI) switching specifications (full voltage
range).................................................................43
3.9.3 I2C..................................................................... 46
3.9.4 UART................................................................. 46
Dimensions........................................................................... 46
4.1 Obtaining package dimensions......................................47
Pinout.................................................................................... 47
5.1 KV4x Signal Multiplexing and Pin Assignments............ 47
5.2 Pinout diagrams............................................................. 51
Ordering parts....................................................................... 54
6.1 Determining valid orderable parts.................................. 54
Part identification...................................................................55
7.1 Description..................................................................... 55
7.2 Format........................................................................... 55
7.3 Fields............................................................................. 55
7.4 Example......................................................................... 56
Terminology and guidelines.................................................. 56
8.1 Definition: Operating requirement.................................. 56
8.2 Definition: Operating behavior....................................... 56
8.3 Definition: Attribute........................................................ 57
8.4 Definition: Rating........................................................... 57
8.5 Result of exceeding a rating.......................................... 58
8.6 Relationship between ratings and operating
requirements.................................................................. 58
8.7 Guidelines for ratings and operating requirements........ 58
8.8 Definition: Typical value................................................. 59
8.9 Typical Value Conditions............................................... 60
9 Revision history.....................................................................60
5
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human-body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105 °C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-up Test.
1.4 Voltage and current operating ratings
6
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
VIO
ID
VDDA
mA
0.31
Digital pin input voltage (except open drain pins)
–0.3
VDD +
Open drain pins (PTC6 and PTC7)
–0.3
5.5
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
Analog supply voltage
V
1. Maximum value of VIO (except open drain pins) must be 3.8 V.
1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in Table 1 may affect
device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
Table 1. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V)
Symbol
Description
VDD
Notes1
Min
Max
Unit
Supply Voltage Range
-0.3
4.0
V
VDDA
Analog Supply Voltage Range
-0.3
4.0
V
VREFHx
ADC High Voltage Reference
-0.3
4.0
V
VREFLx
ADC Low Voltage Reference
-0.3
0.3
V
ΔVDD
Voltage difference VDD to VDDA
-0.3
0.3
V
ΔVSS
Voltage difference VSS to VSSA
-0.3
0.3
V
VIN
Digital Input Voltage Range
Pin Groups 1, 2
-0.3
4.0
V
VOSC
Oscillator Input Voltage Range
Pin Group 4
-0.4
4.0
V
VINA
Analog Input Voltage Range
Pin Group 3
-0.3
4.0
V
IIC
Input clamp current, per pin (VIN < 0)
—
-20.0
mA
—
-20.0
mA
IOC
Output clamp current, per pin (VO <
0)2
VOUT
Output Voltage Range (Normal Push-Pull mode)
Pin Group 1
-0.3
4.0
V
VOUTOD
Output Voltage Range (Open Drain mode)
Pin Group 2
-0.3
5.5
V
VOUT_DAC
DAC Output Voltage Range
Pin Group 5
-0.3
4.0
V
TA
Ambient Temperature Industrial
-40
105
°C
TSTG
Storage Temperature Range (Extended Industrial)
-55
150
°C
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET, PORTC6, and PORTC7
• Pin Group 3: ADC and Comparator Analog Inputs
KV4x Data Sheet, Rev. 4, 09/2019
7
NXP Semiconductors
General
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. Continuous clamp current per pin is -2.0 mA
2 General
Electromagnetic compatibility (EMC) performance depends on the environment in
which the MCU resides. Board design and layout, circuit topology choices, location,
characteristics of external components, and MCU software operation play a significant
role in EMC performance.
See the following applications notes available on nxp.com for guidelines on optimizing
EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
Low
High
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
8
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
General
All digital I/O switching characteristics, unless otherwise specified, assume:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2.2 Nonswitching electrical specifications
2.2.1 Recommended Operating Conditions
This section includes information about recommended operating conditions.
NOTE
Recommended VDD ramp rate is between 1 ms and 200 ms.
Table 2. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V)
Description
Notes1
Min
VDD
Supply Voltage Digital
2, 3
1.71
VDDA
Supply voltage (analog)
2, 3
2.7
Symbol
Typ
3.0
Max
Unit
3.6
V
3.6
V
VDDA
V
VREFHx
ADC (Cyclic) Reference Voltage High
2.7
ΔVDD
Voltage difference VDD to VDDA
-0.1
0
0.1
V
ΔVSS
Voltage difference VSS to VSSA
-0.1
0
0.1
V
0.04
168
MHz
0
168
0.7 x VDD
3.6
V
0.35 x VDD
V
–
V
F_MCGO
UT
•
•
Device Clock Frequency
using internal RC oscillator
using external clock source
VIH
Input Voltage High (digital inputs)
Pin Groups 1, 2
VIL
Input Voltage Low (digital inputs)
Pin Groups 1, 2
VHYS
VIHOSC
Input hystersis
Oscillator Input Voltage High
0.06 x VDD
–
Pin Group 4
2.0
VDD + 0.3
V
Oscillator Input Voltage Low
Pin Group 4
-0.3
0.8
V
DAC Output Current Drive Strength
Pin Group 5
1
mA
105
°C
XTAL driven by an external clock source
VILOSC
Cout
TA
Ambient Operating Temperature
-40
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
KV4x Data Sheet, Rev. 4, 09/2019
9
NXP Semiconductors
General
• Pin Group 6: PTB0, PTB1, PTD4, PTD5, PTD6, PTD7, PTC3, and PTC4. have high output current capability
• Pin Group 7: PTC6 and PTC7 are true open drain pins and have no P-chanl transistor. A external pull-up
resistor is required when these pins are outputs.
2. If the ADC is enabled, minimum VDD is 2.7 V and minimum VDDA is 2.7 V. ADCA and ADCB are not guaranteed to
operate below 2.7 V. All other analog modules besides the ADC and Nano-edge will operate down to 1.71 V.
3. If the Nano-edge is enabled, minimum VDD is 3.0 V and minimum VDDA is 3.0 V. Nano-edge is not guaranteed to operate
below 3.0 V. All other analog modules besides the ADC and Nano-edge will operate down to 1.71 V.
2.2.2 LVD and POR operating requirements
Table 3. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
±80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
±60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Typ.
Max.
Unit
Notes
Output high voltage — normal drive pad
Table continues on the next page...
10
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
VDD – 0.5
—
—
V
• 1.71 V ≤VDD ≤ 2.7 V, IOH = -5mA
VDD – 0.5
—
—
V
Output high voltage — High drive pad
Notes
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20mA
VDD – 0.5
—
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10mA
VDD – 0.5
—
—
V
—
—
100
mA
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
Output low current total for all ports
—
—
100
mA
Input leakage current, analog and digital
pins
• VSS ≤ VIN ≤ VDD
—
0.002
0.5
µA
3
RPU
Internal pullup resistors(except
RTC_WAKEUP pins)
20
—
50
kΩ
4
RPD
Internal pulldown resistors
20
—
50
kΩ
5
IOHT
Output high current total for all ports
VOL
Output low voltage — open drain pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = 3 mA
2
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = 1 mA
VOL
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
Output low voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
1
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
IOLT
IIN
1.
2.
3.
4.
5.
High drive pads are PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6 and PTD7.
Open drain pads are PTC6 and PTC7.
Measured at VDD=3.6V
Measured at VDD supply voltage = VDD min and Vinput = VSS
Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus and flash clock = 25 MHz
• FEI clock mode
KV4x Data Sheet, Rev. 4, 09/2019
11
NXP Semiconductors
General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Typ.
Max.
Unit
—
—
300
μs
—
—
173
μs
—
—
172
μs
—
—
96
μs
—
—
96
μs
—
—
5.4
μs
—
—
5.4
μs
After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating temperature
range of the chip.
Notes
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard deviation
(mean+3σ)
Table 6. Power consumption operating behaviors (All IDDs are Target values)
Symbol
Description
Min.
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash, excludes
IDDA
• @ 1.8V
• @ 3.0V
IDD_RUN
Typ.
Max.
Unit
Notes
1
—
6.8
17.2
mA
—
6.9
17.4
mA
Run mode current — all peripheral clocks
disabled, code executing from flash, excludes
IDDA
2
• @ 1.8V
• @ 3.0V
—
9.9
19.7
mA
Table continues on the next page...
12
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
General
Table 6. Power consumption operating behaviors (All IDDs are Target values) (continued)
Symbol
IDD_RUN
Description
Min.
Typ.
Max.
Unit
—
10.0
19.8
mA
Run mode current — all peripheral clocks
disabled, code executing from flash, excludes
IDDA
Notes
3
• @ 1.8V
—
17.0
25.9
mA
• @ 3.0V
—
17.2
26.1
mA
IDD_HSRUN Run mode current — all peripheral clocks
disabled, code executing from flash, excludes
IDDA
4
• @ 1.8V
—
26.3
45.3
mA
• @ 3.0V
—
26.5
45.5
mA
IDD_HSRUN Run mode current — all peripheral clocks
enabled, code executing from flash,excludes
IDDA
5
• @ 3.0V
• @ 25°C
—
34.0
45.5
mA
• @ 105°C
—
39.0
53.2
mA
IDD_WAIT
Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
—
8.9
14.93
mA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
—
0.58
1.88
mA
7
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
—
0.83
2.11
mA
8
—
0.34
1.59
mA
9
• @ –40 to 25°C
—
0.43
2.03
• @ 70°C
—
1.16
4.27
• @ 105°C
—
3.05
10.13
• @ –40 to 25°C
—
58
218
μA
• @ 70°C
—
280
1340
μA
• @ 105°C
—
924
2870
μA
• @ –40 to 25°C
—
2.8
5.3
μA
• @ 70°C
—
9.6
35.1
μA
• @ 105°C
—
37.4
134.8
μA
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
IDD_VLPS
mA
mA
mA
Very-low-power stop mode current at 3.0 V
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
Table continues on the next page...
KV4x Data Sheet, Rev. 4, 09/2019
13
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (All IDDs are Target values) (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• @ –40 to 25°C
—
2.7
3.3
μA
• @ 70°C
—
6.6
12.2
μA
• @ 105°C
—
25.9
50.5
μA
• @ –40 to 25°C
—
740
1200
nA
• @ 70°C
—
2.5
10.6
μA
• @ 105°C
—
11.1
26.5
μA
—
420
832
nA
—
1.9
9.4
μA
—
10.8
26.3
μA
—
200
599
nA
—
1.8
10.5
μA
—
10.8
26.3
μA
Notes
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0B Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS0A Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
1.
2.
3.
4.
5.
6.
Core frequency of 25 MHz.
Core frequency of 50 MHz.
Core frequency of 100 MHz.
Core frequency of 168 MHz.
Core frequency of 168 MHz. Nanoedge module at 84 MHz.
100 MHz core and system clock, 100 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks disabled. CACHE is Enabled and Clock Gate (CG) = ALLOFF
7. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
8. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
9. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
Table 7. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52
52
52
52
52
52
µA
Table continues on the next page...
14
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
General
Table 7. Low power mode peripheral adders — typical value (continued)
Symbol
Description
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS mode
with the crystal enabled.
Temperature (°C)
Unit
-40
25
50
70
85
105
206
228
237
245
251
258
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
uA
nA
VLLS1
VLLS3
440
490
540
560
570
580
VLPS
440
490
540
560
570
580
STOP
510
560
560
560
610
680
510
560
560
560
610
680
22
22
22
22
22
22
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
IUART
UART peripheral adder measured by placing
the device in STOP or VLPS mode with
selected clock source waiting for RX data at
115200 baud rate. Includes selected clock
source power consumption.
MCGIRCLK (4 MHz internal reference clock)
OSCERCLK (4 MHz external crystal)
IBG
2.2.5.1
Bandgap adder when BGEN bit is set and
device is placed in VLPx or VLLSx mode.
µA
µA
66
66
66
66
66
66
214
234
246
254
260
268
45
45
45
45
45
45
µA
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
MCG in FBE for run mode, and BLPE for VLPR mode
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
KV4x Data Sheet, Rev. 4, 09/2019
15
NXP Semiconductors
General
Figure 3. Run mode supply current vs. core frequency
16
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
General
Very Low Power Run (VLPR) Current vs Core Frequency
Temp (C)=25,VDD=3.6V,CACHE=ENABLE,Code Residence=Flash
1.00E-03
900.00E-06
800.00E-06
Current Consumption on VDD (A)
700.00E-06
600.00E-06
All Peripheral Clk Gates
500.00E-06
ALLOFF
ALLON
400.00E-06
300.00E-06
200.00E-06
100.00E-06
000.00E+00
'1-1-2
'1-1-1
'1-2-4
1
'1-1-4
'1-1-2
'1-2-4
2
'1-1-4
4
Clk Ratio
Core-Bus-Flash
Core Freq (Mhz)
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
NOTE
EMC measurements to IC-level IEC standards are available
from NXP on request.
Table 8. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
20
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
18
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
14
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
8
dBμV
IEC level
0.15–1000
L
—
VRE_IEC
KV4x Data Sheet, Rev. 4, 09/2019
2, 3
17
NXP Semiconductors
General
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 75 MHz, fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Typical device clock specifications
Table 10. Typical device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed RUN mode
fSYS
System and core clock
—
168
MHz
fBUS
Bus and Flash clock
—
24
MHz
fFPCK
Fast peripheral clock
—
84
MHz
fNANO
Nano-edge clock
—
168
MHz
Normal run mode
fSYS
System and core clock
—
100
MHz
fBUS
Bus and Flash clock
—
25
MHz
Table continues on the next page...
18
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
General
Table 10. Typical device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
fFPCK
Fast peripheral clock
—
100
MHz
fNANO
Nano-edge clock
—
200
MHz
Notes
Low Speed RUN mode
fSYS
System and core clock
—
50
MHz
fBUS
Bus and Flash clock
—
25
MHz
fFPCK
Fast peripheral clock
—
100
MHz
fNANO
Nano-edge clock
—
200
MHz
NOTE
When NaneEdge circuit is enabled, the following clock set
must be followed:
1. NanoEdge clock source must be from the PLL output
2. NanoEdge clock must be 2x the fast peripheral clock
3. NanoEdge clock must in the range of 164 Mhz ~232
Mhz
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and I2C signals.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
3
Fast slew rate
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
—
8
ns
—
7
ns
—
25
ns
—
15
ns
Port rise and fall time
Slow slew rate
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
KV4x Data Sheet, Rev. 4, 09/2019
19
NXP Semiconductors
General
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. For high drive pins with high drive enabled, load is 75pF; other pins load (low drive) is 25pF.
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
2.4.2 Thermal attributes
Table 13. Thermal attributes
Board type
Symbol
Description
100
LQFP
64 LQFP 48 LQFP
Unit
Notes
Single-layer (1S)
RθJA
Thermal resistance, junction to
ambient (natural convection)
62
64
71
°C/W
1
Four-layer (2s2p)
RθJA
Thermal resistance, junction to
ambient (natural convection)
49
46
47
°C/W
Single-layer (1S)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
52
52
58
°C/W
Four-layer (2s2p)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
43
39
41
°C/W
—
RθJB
Thermal resistance, junction to
board
35
28
24
°C/W
2
—
RθJC
Thermal resistance, junction to
case
17
15
18
°C/W
3
—
ΨJT
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
3
2
2
°C/W
4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
20
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD Electricals
Table 14. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
—
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 5. Serial wire clock input timing
KV4x Data Sheet, Rev. 4, 09/2019
21
NXP Semiconductors
Peripheral operating requirements and behaviors
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 6. Serial wire data timing
3.1.2 JTAG electricals
Table 15. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Operating voltage
2.7
3.6
TCLK frequency of operation
Unit
V
MHz
• Boundary Scan
—
10
• JTAG and CJTAG
—
25
• Serial Wire Debug
—
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.0
—
ns
J7
TCLK low to boundary scan output data valid
—
28
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
22
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
Table 15. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
19
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Table 16. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
—
3
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.0
—
ns
J7
TCLK low to boundary scan output data valid
—
30.6
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.0
—
ns
J11
TCLK low to TDO data valid
—
19.0
ns
J12
TCLK low to TDO high-Z
—
17.0
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
KV4x Data Sheet, Rev. 4, 09/2019
23
NXP Semiconductors
Peripheral operating requirements and behaviors
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
24
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
KV4x Data Sheet, Rev. 4, 09/2019
25
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 17. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Δfints_t
Total deviation of internal reference frequency
(slow clock) over voltage and temperature
—
+0.5/-0.7
±2
%
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
± 0.5
±2
%fdco
1
±1
%fdco
1
fints_t
Internal reference frequency (slow clock) —
user trimmed
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
Δfintf_ft
Frequency deviation of internal reference
frequency (fast clock) over voltage and
temperature — factory trimmed at nominal VDD
and 25 °C
—
+1/-2
±5
% fintf_ft
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
fintf_ft
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
2, 3
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
4, 5
732 × ffll_ref
Table continues on the next page...
26
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
Mid range (DRS=01)
Min.
Typ.
Max.
Unit
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
8
—
16
MHz
Notes
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
6
PLL
fpll_ref
PLL reference frequency range
fvcoclk_2x
VCO output frequency
220
—
480
MHz
fvcoclk
PLL output frequency
110
—
240
MHz
PLL quadrature output frequency
110
—
240
MHz
—
2.8
—
mA
—
4.7
—
mA
fvcoclk_90
Ipll
PLL operating current
• VCO @ 176 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 22)
Ipll
PLL operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 45)
Jcyc_pll
Jacc_pll
PLL period jitter (RMS)
7
7
8
• fvco = 48 MHz
—
120
—
ps
• fvco = 120 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
8
• fvco = 48 MHz
—
1350
—
ps
• fvco = 120 MHz
—
600
—
ps
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
150 × 10-6
+ 1075(1/
fpll_ref)
s
9
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
KV4x Data Sheet, Rev. 4, 09/2019
27
NXP Semiconductors
Peripheral operating requirements and behaviors
8. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 4 MHz
—
400
—
μA
• 8 MHz
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
RS
2, 4
Table continues on the next page...
28
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Series resistor — high-frequency, low-power
mode (HGO=0)
Notes
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2
Symbol
Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Min.
Typ.
Max.
Unit
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
1000
—
ms
fosc_lo
tcst
Description
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
KV4x Data Sheet, Rev. 4, 09/2019
29
NXP Semiconductors
Peripheral operating requirements and behaviors
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
208
1808
ms
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec4k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
0.9
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
280
2100
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
30
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
3.4.1.3
Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 23. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 12-bit cyclic Analog-to-Digital Converter (ADC) parameters
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard
deviation (mean+3σ).
KV4x Data Sheet, Rev. 4, 09/2019
31
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 24. 12-bit ADC electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
VDDA
2.7
3.3
3.6
V
Recommended Operating Conditions
Supply Voltage1
Vrefh Supply
Voltage, 2
ADC Conversion Clock3
Conversion Range
Input Voltage Range
Vrefhx
2.7
VDDA
V
fADCCLK
0.6
25
MHz
RAD
VREFL
VREFH
V
VADIN
V
External Reference
VREFL
VREFH
Internal Reference
VSSA
VDDA
Timing and Power
Conversion Time
tADC
6
ADC Clock Cycles
ADC Power-Up Time (from adc_pdn)
tADPU
13
ADC Clock Cycles
ADC RUN Current (per ADC block)
IADRUN
mA
• at 666.7 kHz ADC Clock, LP mode
1.1
1.36
• ≤ 8.33 MHz ADC Clock, 00 mode
6.9
8.09
• ≤ 12.5 MHz ADC Clock, 01 mode
11.9
14.05
• ≤ 16.67 MHz ADC Clock, 10 mode
20.4
23.86
• ≤ 20 MHz ADC Clock, 11 mode
25.9
31.03
• ≤ 25 MHz ADC Clock, 11 mode
26.3
31.40
ADC Powerdown Current (adc_pdn enabled)
IADPWRDWN
0.02
µA
IVREFH
0.001
µA
Integral non-Linearity4
INL
+/- 3
+/- 5
LSB5
Differential non-Linearity4
DNL
+/- 0.6
+/- 0.9
LSB5
VREFH Current
Accuracy (DC or Absolute)
Monotonicity
Offset6
LSB4
VOFFSET
+/- 25
• 1x gain mode
+/- 20
• 2x gain mode
+50, -10
• 4x gain mode
Gain Error
EGAIN
0.0002
%
AC Specifications7
Signal to Noise Ratio
SNR
59
dB
Total Harmonic Distortion
THD
64
dB
Spurious Free Dynamic Range
SFDR
65
dB
Signal to Noise plus Distortion
SINAD
59
dB
Effective Number of Bits
ENOB
9.1
bits
IIN
0
ADC Inputs
Input Leakage Current
+/-2
µA
Table continues on the next page...
32
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
Table 24. 12-bit ADC electrical specifications (continued)
Characteristic
Symbol
Input Injection Current
8
Min
Typ
IINJ
Input Capacitance
CADI
Max
Unit
+/-3
mA
pF
4.8
Sampling Capacitor
1. If the ADC’s reference is from VDDA: When VDDA is below 2.7 V, then the ADC functions, but the ADC specifications
are not guaranteed.
2. When the input is at the Vrefl level, then the resulting output will be all zeros (hex 000), plus any error contribution due
to offset and gain error. When the input is at the Vrefh level, then the output will be all ones (hex FFF), minus any error
contribution due to offset and gain error.
3. ADC clock duty cycle min/max is 45/55% .
4. DNL and INL conversion accuracy is not guaranteed from VREFL to VREFL + 0025 and VREFH to VREFH-0025.
5. LSB = Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 Gain Setting
6. Offset over the conversion range of 0025 to 4070, with internal/external reference.
7. Measured when converting a 1 kHz input Full Scale sine wave.
8. The current that can be injected into or sourced from an unselected ADC input, without affecting the performance of
the ADC.
3.6.1.1
Equivalent circuit for ADC inputs
The following figure shows the ADC input circuit during sample and hold. S1 and S2
are always opened/closed at non-overlapping phases,and both S1 and S2 operate at
the ADC clock frequency. The following equation gives equivalent input impedance
when the input is selected.
1
-12
(ADC ClockRate) x
1.4x10
+ 100ohm + 125ohm
C1: Single Ended Mode
2XC1: Differential Mode
Analog Input
1
125 ESD
Resistor
Channel Mux
equivalent resistance
100Ohms
S1
C1
S1
S/H
S1
2
C1
S2
S2
S1
(VREFHx - VREFLx ) / 2
C1: Single Ended Mode
2XC1: Differential Mode
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling
= 1.8pF
KV4x Data Sheet, Rev. 4, 09/2019
33
NXP Semiconductors
Peripheral operating requirements and behaviors
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. Sampling capacitor at the sample and hold circuit. Capacitor C1 (4.8pF) is normally
disconnected from the input, and is only connected to the input at sampling time.
4. S1 and S2 switch phases are non-overlapping and operate at the ADC clock
frequency
S1
S2
Figure 11. Equivalent circuit for A/D loading
3.6.2 CMP and 6-bit DAC electrical specifications
Table 25. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, high-speed mode (EN = 1, PMODE =
1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN = 1, PMODE =
0)
—
—
20
μA
VAIN
Analog input voltage
VSS
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator
hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN = 1,
PMODE = 1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN = 1, PMODE
= 0)
80
250
600
ns
Analog comparator initialization delay2
—
—
40
μs
6-bit DAC current adder (enabled)
—
7
—
μA
IDAC6b
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
34
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
3. 1 LSB = Vreference/64
CMP Hysteresis vs Vinn
90.00E-03
80.00E-03
CMP Hysteresis (V)
70.00E-03
60.00E-03
HYSTCTR
Setting
50.00E-03
0
1
2
3
40.00E-03
30.00E-03
20.00E-03
10.00E-03
000.00E+00
0.1
0.4
0.7
1
1.3
1.6
1.9
Vinn (V)
2.2
2.5
2.8
3.1
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
CMP Hysteresis vs Vinn
180.00E-03
160.00E-03
CMP Hysteresis (V)
140.00E-03
120.00E-03
HYSTCTR
Setting
100.00E-03
0
1
2
3
80.00E-03
60.00E-03
40.00E-03
20.00E-03
000.00E+00
-20.00E-03
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
KV4x Data Sheet, Rev. 4, 09/2019
35
NXP Semiconductors
Peripheral operating requirements and behaviors
3.6.3.1
Symbol
12-bit DAC operating requirements
Table 26. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
Notes
1.13
3.6
V
1
CL
Output load capacitance
—
100
pF
2
IL
Output load current
—
1
mA
1. The DAC reference can be selected to be VDDA or VREF_OUT.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
3.6.3.2
Symbol
12-bit DAC operating behaviors
Table 27. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
330
μA
—
—
1200
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08)
• High-speed mode
• Low speed mode
—
1
5
Vdacoutl
DAC output voltage range low — highspeed mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
VOFFSET Offset error
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance (load = 3 kΩ)
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
EG
PSRR
6
V/μs
Table continues on the next page...
36
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
Table 27. 12-bit DAC operating behaviors (continued)
Symbol
Description
BW
1.
2.
3.
4.
5.
6.
Min.
Typ.
Max.
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
3dB bandwidth
Unit
Notes
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 14. Typical INL error vs. digital code
KV4x Data Sheet, Rev. 4, 09/2019
37
NXP Semiconductors
Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
25
-40
85
105
125
Temperature °C
Figure 15. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Enhanced NanoEdge PWM characteristics
Table 28. NanoEdge PWM timing parameters - 100 Mhz operating frequency
Characteristic
Symbol
Min.
PWM clock frequency
NanoEdge Placement (NEP) Step
Size1, 2
pwmp
Delay for fault input activating to PWM output deactivated
1
Typ.
Max.
Unit
100
MHz
312
ps
ns
Table continues on the next page...
38
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
Table 28. NanoEdge PWM timing parameters - 100 Mhz operating frequency (continued)
Characteristic
Power-up
Symbol
Time3
Min.
tpu
Typ.
Max.
Unit
25
μs
1. Reference 100 MHz in NanoEdge Placement mode.
2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.
Table 29. NanoEdge PWM timing parameters - 84 Mhz operating frequency
Characteristic
Symbol
Min.
PWM clock frequency
NanoEdge Placement (NEP) Step
Size1, 2
pwmp
Delay for fault input activating to PWM output
deactivated
Typ.
tpu
Unit
84
MHz
372
ps
1
Power-up Time3
Max.
ns
30
μs
1. Reference 84 MHz in NanoEdge Placement mode.
2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.
3.9 Communication interfaces
3.9.1 SPI (DSPI) switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Fast pads:
• SIN: PTE19
• SOUT: PTE18
• SCK: PTE17
• PCS: PTE16
NOTE
Open drain pads:
KV4x Data Sheet, Rev. 4, 09/2019
39
NXP Semiconductors
Peripheral operating requirements and behaviors
• SIN: PTC7
• SOUT: PTC6
Table 30. Master mode DSPI timing for normal pads (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn output hold
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
17
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Table 31. Master mode DSPI timing for fast pads (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
37.5
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn output hold
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
13
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Table 32. Master mode DSPI timing for open drain pads (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
Notes
Table continues on the next page...
40
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
Table 32. Master mode DSPI timing for open drain pads (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
—
25
MHz
2 x tBUS
—
ns
Frequency of operation
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn output hold
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
15.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−3
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
17
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
SPI_PCSn
DS3
SPI_SCK
(CPOL=0)
DS7
SPI_SIN
DS1
DS2
DS4
DS8
First data
SPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 16. DSPI classic SPI timing — master mode
Table 33. Slave mode DSPI timing for normal pads (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
21
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
15
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
15
ns
KV4x Data Sheet, Rev. 4, 09/2019
41
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 34. Slave mode DSPI timing for fast pads (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
25
MHz
4 x tBUS
—
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
17
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
11
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
11
ns
Table 35. Slave mode DSPI timing for open drain pads (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
28
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
22
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
22
ns
SPI_SS
DS10
DS9
SPI_SCK
(POL=0)
DS15
SPI_SOUT
First data
DS13
SPI_SIN
DS12
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 17. DSPI classic SPI timing — slave mode
42
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
3.9.2 SPI (DSPI) switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Fast pads:
• SIN: PTE19
• SOUT: PTE18
• SCK: PTE17
• PCS: PTE16
NOTE
Open drain pads:
• SIN: PTC7
• SOUT: PTC6
Table 36. Master mode DSPI timing for normal pads (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
18.75
MHz
4 x tBUS
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-7.8
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
24
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
KV4x Data Sheet, Rev. 4, 09/2019
43
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 37. Master mode DSPI timing fast pads (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
25
MHz
4 x tBUS
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-7.8
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
17
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Table 38. Master mode DSPI timing open drain pads (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
18.75
MHz
4 x tBUS
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
26
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-7.8
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
24
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
44
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Peripheral operating requirements and behaviors
SPI_PCSn
DS3
SPI_SCK
DS7
(CPOL=0)
SPI_SIN
DS1
DS2
DS4
DS8
First data
SPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 18. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing for normal pads (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
12.5
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
27.5
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2.5
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
22
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
22
ns
Table 40. Slave mode DSPI timing for fast pads (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
18.75
MHz
8 x tBUS
—
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
20.5
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2.5
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
15
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
15
ns
KV4x Data Sheet, Rev. 4, 09/2019
45
NXP Semiconductors
Dimensions
Table 41. Slave mode DSPI timing for open drain pads (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
9.375
MHz
8 x tBUS
—
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
43.5
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2.5
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
38
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
38
ns
SPI_SS
DS10
DS9
SPI_SCK
DS15
(POL=0)
SPI_SOUT
DS12
First data
DS13
SPI_SIN
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 19. DSPI classic SPI timing — slave mode
3.9.3 I2C
See General switching specifications.
3.9.4 UART
See General switching specifications.
4 Dimensions
46
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Pinout
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
48-pin LQFP
98ASH00962A
64-pin LQFP
98ASS23234W
100-pin LQFP
98ASS23308W
5 Pinout
5.1 KV4x Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
100
64
48
LQFP LQFP LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
1
1
—
PTE0
ADCB_CH6f
ADCB_CH6f
PTE0
UART1_TX
XBAR0_
OUT10
XBAR0_IN11
2
2
—
PTE1/
LLWU_P0
ADCB_CH7f
ADCB_CH7f
PTE1/
LLWU_P0
UART1_RX
XBAR0_
OUT11
XBAR0_IN7
3
—
—
PTE2/
LLWU_P1
ADCB_CH6g ADCB_CH6g PTE2/
LLWU_P1
UART1_
CTS_b
4
—
—
PTE3
ADCB_CH7g ADCB_CH7g PTE3
UART1_
RTS_b
5
—
—
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
6
—
—
PTE5
DISABLED
PTE5
FTM3_CH0
7
—
—
PTE6/
LLWU_P16
DISABLED
PTE6/
LLWU_P16
FTM3_CH1
8
3
1
VDD
VDD
VDD
9
4
2
VSS
VSS
VSS
10
5
3
PTE16
ADCA_CH0
ADCA_CH0
KV4x Data Sheet, Rev. 4, 09/2019
PTE16
SPI0_PCS0
UART1_TX
FTM_CLKIN0
ALT7
FTM0_FLT3
47
NXP Semiconductors
Pinout
100
64
48
LQFP LQFP LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
11
6
4
PTE17/
LLWU_P19
ADCA_CH1
ADCA_CH1
PTE17/
LLWU_P19
SPI0_SCK
UART1_RX
FTM_CLKIN1
12
7
5
PTE18/
LLWU_P20
ADCB_CH0
ADCB_CH0
PTE18/
LLWU_P20
SPI0_SOUT
UART1_
CTS_b
I2C0_SDA
13
8
6
PTE19
ADCB_CH1
ADCB_CH1
PTE19
SPI0_SIN
UART1_
RTS_b
I2C0_SCL
14
—
—
ADCA_CH6a ADCA_CH6a ADCA_CH6a
15
—
—
ADCA_CH7a ADCA_CH7a ADCA_CH7a
16
—
7
PTE20
ADCA_CH6b ADCA_CH6b PTE20
FTM1_CH0
UART0_TX
17
—
8
PTE21
ADCA_CH7b ADCA_CH7b PTE21
FTM1_CH1
UART0_RX
18
9
—
ADCA_CH2
ADCA_CH2
ADCA_CH2
19
10
—
ADCA_CH3
ADCA_CH3
ADCA_CH3
20
11
—
ADCA_CH6c
ADCA_CH6c
ADCA_CH6c
21
12
—
ADCA_CH7c
ADCA_CH7c
ADCA_CH7c
22
13
9
VDDA
VDDA
VDDA
23
14
10
VREFH
VREFH
VREFH
24
15
11
VREFL
VREFL
VREFL
25
16
12
VSSA
VSSA
VSSA
26
17
13
PTE29
ADCA_CH4/
CMP1_IN5/
CMP0_IN5
ADCA_CH4/
CMP1_IN5/
CMP0_IN5
PTE29
FTM0_CH2
FTM_CLKIN0
27
18
14
PTE30
DAC0_OUT/
CMP1_IN3/
ADCA_CH5
DAC0_OUT/
CMP1_IN3/
ADCA_CH5
PTE30
FTM0_CH3
FTM_CLKIN1
28
19
—
ADCA_CH6d/ ADCA_CH6d/ ADCA_CH6d/
CMP0_IN4/ CMP0_IN4/ CMP0_IN4/
CMP2_IN3
CMP2_IN3
CMP2_IN3
29
—
—
VSS
VSS
VSS
30
—
—
VDD
VDD
VDD
31
20
15
PTE24
ADCB_CH4
ADCB_CH4
PTE24
CAN1_TX
FTM0_CH0
XBAR0_IN2
I2C0_SCL
EWM_OUT_b XBAR0_
OUT4
32
21
16
PTE25/
LLWU_P21
ADCB_CH5
ADCB_CH5
PTE25/
LLWU_P21
CAN1_RX
FTM0_CH1
XBAR0_IN3
I2C0_SDA
EWM_IN
33
—
—
PTE26
DISABLED
PTE26
34
22
17
PTA0
JTAG_TCLK/
SWD_CLK
PTA0
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
XBAR0_IN4
EWM_IN
35
23
18
PTA1
JTAG_TDI
PTA1
UART0_RX
FTM0_CH6
CMP0_OUT
FTM1_CH1
JTAG_TDI
36
24
19
PTA2
JTAG_TDO/
TRACE_
SWO
PTA2
UART0_TX
FTM0_CH7
CMP1_OUT
FTM1_CH0
JTAG_TDO/
TRACE_
SWO
37
25
20
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
XBAR0_IN9
EWM_OUT_b FLEXPWMA_ JTAG_TMS/
A0
SWD_DIO
48
NXP Semiconductors
LPTMR0_
ALT3
CMP3_OUT
XBAR0_
OUT5
JTAG_TCLK/
SWD_CLK
KV4x Data Sheet, Rev. 4, 09/2019
Pinout
100
64
48
LQFP LQFP LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
38
26
21
PTA4/
LLWU_P3
NMI_b
PTA4/
LLWU_P3
FTM0_CH1
XBAR0_IN10 FTM0_FLT3
39
27
—
PTA5
DISABLED
PTA5
FTM0_CH2
CMP2_OUT
40
—
22
VDD
VDD
VDD
41
—
23
VSS
VSS
VSS
42
28
—
PTA12
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
FTM1_CH0
FTM1_QD_
PHA
43
29
—
PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
FTM1_QD_
PHB
44
—
—
PTA14
CMP3_IN0
CMP3_IN0
PTA14
SPI0_PCS0
UART0_TX
45
—
—
PTA15
CMP3_IN1
CMP3_IN1
PTA15
SPI0_SCK
UART0_RX
46
—
—
PTA16
CMP3_IN2
CMP3_IN2
PTA16
SPI0_SOUT
UART0_
CTS_b/
UART0_
COL_b
47
—
—
PTA17
ADCA_CH7e ADCA_CH7e PTA17
SPI0_SIN
UART0_
RTS_b
48
30
—
VDD
VDD
VDD
49
31
—
VSS
VSS
VSS
50
32
24
PTA18
EXTAL0
EXTAL0
PTA18
XBAR0_IN7
FTM0_FLT2
FTM_CLKIN0 XBAR0_
OUT8
FTM3_CH2
51
33
25
PTA19
XTAL0
XTAL0
PTA19
XBAR0_IN8
FTM1_FLT0
FTM_CLKIN1 XBAR0_
OUT9
LPTMR0_
ALT1
52
34
26
RESET_b
RESET_b
RESET_b
53
35
27
PTB0/
LLWU_P5
ADCB_CH2
ADCB_CH2
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
54
36
28
PTB1
ADCB_CH3
ADCB_CH3
PTB1
I2C0_SDA
FTM1_CH1
FTM0_FLT2
55
37
29
PTB2
ADCA_CH6e/ ADCA_CH6e/ PTB2
CMP2_IN2
CMP2_IN2
I2C0_SCL
UART0_
RTS_b
FTM0_FLT1
56
38
30
PTB3
ADCB_CH7e/ ADCB_CH7e/ PTB3
CMP3_IN5
CMP3_IN5
I2C0_SDA
UART0_
CTS_b/
UART0_
COL_b
57
—
—
PTB9
DISABLED
58
—
—
PTB10
ADCB_CH6a ADCB_CH6a PTB10
FTM0_FLT1
59
—
—
PTB11
ADCB_CH7a ADCB_CH7a PTB11
FTM0_FLT2
60
—
—
VSS
VSS
VSS
61
—
—
VDD
VDD
VDD
62
39
31
PTB16
DISABLED
PTB16
63
40
32
PTB17
DISABLED
PTB17
64
41
—
PTB18
DISABLED
PTB18
CAN0_TX
FTM3_CH2
65
42
—
PTB19
DISABLED
PTB19
CAN0_RX
FTM3_CH3
KV4x Data Sheet, Rev. 4, 09/2019
EWM_IN
FLEXPWMA_ NMI_b
B0
JTAG_TRST_
b
FTM1_QD_
PHA
UART0_RX
FTM1_QD_
PHB
UART0_TX
FTM0_FLT3
FTM0_FLT0
PTB9
UART0_RX
FTM_CLKIN2 CAN0_TX
EWM_IN
UART0_TX
FTM_CLKIN1 CAN0_RX
EWM_OUT_b
XBAR0_IN5
49
NXP Semiconductors
Pinout
100
64
48
LQFP LQFP LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
66
—
—
PTB20
DISABLED
PTB20
FLEXPWMA_ CMP0_OUT
X0
67
—
—
PTB21
DISABLED
PTB21
FLEXPWMA_ CMP1_OUT
X1
68
—
—
PTB22
DISABLED
PTB22
FLEXPWMA_ CMP2_OUT
X2
69
—
—
PTB23
DISABLED
PTB23
70
43
33
PTC0
ADCB_CH6b ADCB_CH6b PTC0
SPI0_PCS4
PDB0_
EXTRG
71
44
34
PTC1/
LLWU_P6
ADCB_CH7b ADCB_CH7b PTC1/
LLWU_P6
SPI0_PCS3
UART1_
RTS_b
FTM0_CH0
FLEXPWMA_ XBAR0_IN11
A3
72
45
35
PTC2
ADCB_CH6c/ ADCB_CH6c/ PTC2
CMP1_IN0
CMP1_IN0
SPI0_PCS2
UART1_
CTS_b
FTM0_CH1
FLEXPWMA_ XBAR0_IN6
B3
73
46
36
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
74
47
—
VSS
VSS
VSS
75
48
—
VDD
VDD
VDD
76
49
37
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
CMP1_OUT
77
50
38
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
XBAR0_IN2
CMP0_OUT
FTM0_CH2
78
51
39
PTC6/
LLWU_P10
CMP2_IN4/
CMP0_IN0
CMP2_IN4/
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_
EXTRG
XBAR0_IN3
UART0_RX
XBAR0_
OUT6
I2C0_SCL
79
52
40
PTC7
CMP3_IN4/
CMP0_IN1
CMP3_IN4/
CMP0_IN1
PTC7
SPI0_SIN
XBAR0_IN4
UART0_TX
XBAR0_
OUT7
I2C0_SDA
80
53
—
PTC8
ADCB_CH7c/ ADCB_CH7c/ PTC8
CMP0_IN2
CMP0_IN2
FTM3_CH4
81
54
—
PTC9
ADCB_CH6d/ ADCB_CH6d/ PTC9
CMP0_IN3
CMP0_IN3
FTM3_CH5
82
55
—
PTC10
ADCB_CH7d ADCB_CH7d PTC10
FTM3_CH6
83
56
—
PTC11/
LLWU_P11
ADCB_CH6e ADCB_CH6e PTC11/
LLWU_P11
FTM3_CH7
84
—
—
PTC12
DISABLED
PTC12
85
—
—
PTC13
DISABLED
PTC13
86
—
—
PTC14
DISABLED
PTC14
I2C0_SCL
87
—
—
PTC15
DISABLED
PTC15
I2C0_SDA
88
—
—
VSS
VSS
VSS
89
—
—
VDD
VDD
VDD
90
—
—
PTC16
DISABLED
PTC16
CAN1_RX
91
—
—
PTC17
DISABLED
PTC17
CAN1_TX
92
—
—
PTC18
DISABLED
PTC18
93
57
41
PTD0/
LLWU_P12
DISABLED
PTD0/
LLWU_P12
50
NXP Semiconductors
SPI0_PCS5
FLEXPWMA_ CMP3_OUT
X3
FTM0_FLT1
FTM_CLKIN0
SPI0_PCS0
FTM3_FLT0
FTM3_FLT0
FTM_CLKIN1
SPI0_PCS0
FTM3_CH0
FTM0_CH0
FLEXPWMA_
A0
KV4x Data Sheet, Rev. 4, 09/2019
Pinout
100
64
48
LQFP LQFP LQFP
Pin Name
Default
ALT0
ADCA_CH7f
94
58
42
PTD1
ADCA_CH7f
95
59
43
PTD2/
LLWU_P13
96
60
44
97
61
98
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
PTD1
SPI0_SCK
FTM3_CH1
FTM0_CH1
FLEXPWMA_
B0
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
FTM3_CH2
FTM0_CH2
FLEXPWMA_ I2C0_SCL
A1
PTD3
DISABLED
PTD3
SPI0_SIN
FTM3_CH3
FTM0_CH3
FLEXPWMA_ I2C0_SDA
B1
45
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
FTM0_CH4
FLEXPWMA_ EWM_IN
A2
62
46
PTD5
ADCA_CH6g ADCA_CH6g PTD5
SPI0_PCS2
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
FLEXPWMA_ EWM_OUT_b SPI0_SCK
B2
99
63
47
PTD6/
LLWU_P15
ADCA_CH7g ADCA_CH7g PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM1_CH0
FTM0_FLT0
SPI0_SOUT
100
64
48
PTD7
DISABLED
UART0_TX
FTM0_CH7
FTM1_CH1
FTM0_FLT1
SPI0_SIN
PTD7
SPI0_PCS0
5.2 Pinout diagrams
The following diagrams show pinouts for the packages. For each pin, the diagrams
show the default function. However, many signals may be multiplexed onto a single
pin.
KV4x Data Sheet, Rev. 4, 09/2019
51
NXP Semiconductors
PTC17
PTC16
VDD
VSS
PTC15
PTC14
PTC13
PTC12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
90
89
88
87
86
85
84
83
82
81
80
PTC4/LLWU_P8
PTC18
92
91
PTC5/LLWU_P9
PTD0/LLWU_P12
76
PTD1
94
93
77
PTD2/LLWU_P13
PTC7
PTD3
96
95
PTC6/LLWU_P10
PTD4/LLWU_P14
97
79
PTD5
98
78
PTD6/LLWU_P15
99
100
PTD7
Pinout
PTE0
1
75
VDD
PTE1/LLWU_P0
2
74
VSS
PTE2/LLWU_P1
3
73
PTC3/LLWU_P7
PTE3
4
72
PTC2
PTE4/LLWU_P2
5
71
PTC1/LLWU_P6
PTE5
6
70
PTC0
PTE6/LLWU_P16
7
69
PTB23
VDD
8
68
PTB22
9
67
PTB21
10
66
PTB20
VSS
PTE16
PTE17/LLWU_P19
11
65
PTB19
PTE18/LLWU_P20
12
64
PTB18
PTE19
13
63
PTB17
ADCA_CH6a
14
62
PTB16
ADCA_CH7a
15
61
VDD
PTE20
16
60
VSS
PTE21
17
59
PTB11
ADCA_CH2
18
58
PTB10
ADCA_CH3
19
57
PTB9
ADCA_CH6c
20
56
PTB3
ADCA_CH7c
21
55
PTB2
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PTA1
PTA2
PTA3
PTA4/LLWU_P3
PTA5
VDD
VSS
PTA12
PTA13/LLWU_P4
PTA14
PTA15
PTA16
PTA17
VDD
49
34
PTA0
50
33
PTE26
VSS
32
PTE25/LLWU_P21
PTA18
31
PTE29
30
PTA19
VDD
RESET_b
51
PTE24
52
25
VSS
24
VSSA
29
VREFL
28
PTB0/LLWU_P5
27
PTB1
53
PTE30
54
ADCA_CH6d/CMP0_IN4/CMP2_IN3
22
23
26
VDDA
VREFH
Figure 20. 100-pin LQFP
52
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pinout
ADCA_CH2
9
40
PTB17
ADCA_CH3
10
39
PTB16
ADCA_CH6c
11
38
PTB3
ADCA_CH7c
12
37
PTB2
VDDA
13
36
PTB1
VREFH
14
35
PTB0/LLWU_P5
VREFL
15
34
RESET_b
VSSA
16
33
PTA19
32
PTB18
PTA18
41
31
8
VSS
PTE19
30
PTB19
VDD
42
29
7
PTA13/LLWU_P4
PTE18/LLWU_P20
28
PTC0
PTA12
43
27
6
PTA5
PTE17/LLWU_P19
26
PTC1/LLWU_P6
PTA4/LLWU_P3
44
25
5
PTA3
PTE16
24
PTC2
PTA2
45
23
4
PTA1
VSS
22
PTC3/LLWU_P7
PTA0
46
21
3
PTE25/LLWU_P21
VDD
20
VSS
PTE24
47
19
2
ADCA_CH6d/CMP0_IN4/CMP2_IN3
PTE1/LLWU_P0
18
VDD
PTE30
48
17
1
PTE29
PTE0
Figure 21. 64-pin LQFP
KV4x Data Sheet, Rev. 4, 09/2019
53
NXP Semiconductors
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
48
47
46
45
44
43
42
41
40
39
38
37
Ordering parts
PTE20
7
30
PTB3
PTE21
8
29
PTB2
VDDA
9
28
PTB1
VREFH
10
27
PTB0/LLWU_P5
VREFL
11
26
RESET_b
VSSA
12
25
PTA19
24
PTB16
PTA18
31
23
6
VSS
PTE19
22
PTB17
VDD
32
21
5
PTA4/LLWU_P3
PTE18/LLWU_P20
20
PTC0
PTA3
33
19
4
PTA2
PTE17/LLWU_P19
18
PTC1/LLWU_P6
PTA1
34
17
3
PTA0
PTE16
16
PTC2
PTE25/LLWU_P21
35
15
2
PTE24
VSS
14
PTC3/LLWU_P7
PTE30
36
13
1
PTE29
VDD
Figure 22. 48-pin LQFP
6 Ordering parts
54
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to www.nxp.com and perform a part number search
for the MKV4x device numbers.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KV## A FFF T PP CC S N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KV##
Kinetis family
• KV42
• KV44
• KV46
A
Key attribute
• F = Cortex-M4 w/ DSP and FPU
FFF
Program flash memory size
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LL = 100 LQFP (14 mm x 14 mm)
CC
Maximum CPU frequency (MHz)
• 16 = 168 MHz
Table continues on the next page...
KV4x Data Sheet, Rev. 4, 09/2019
55
NXP Semiconductors
Terminology and guidelines
Field
Description
Values
S
Software type
• (Blank) = Not software enabled
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MKV46F256VLL16
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
56
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Terminology and guidelines
8.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
KV4x Data Sheet, Rev. 4, 09/2019
Min.
–0.3
Max.
1.2
Unit
V
57
NXP Semiconductors
Terminology and guidelines
8.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
8.6 Relationship between ratings and operating requirements
ng
ati
r
ing
rat
e
Op
(
)
in.
(m
nt
me
n.)
mi
t
era
Op
ing
e
uir
req
g
tin
era
Op
nt
me
ire
u
req
ax
(m
.)
t
era
Op
ng
ati
ax
(m
.)
r
ing
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
dli
n
Ha
ng
ng
ati
)
in.
(m
r
li
nd
Ha
ng
ati
x.)
a
(m
r
ng
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
58
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Terminology and guidelines
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
KV4x Data Sheet, Rev. 4, 09/2019
59
NXP Semiconductors
Revision history
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.05
1.00
1.10
VDD (V)
8.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
9 Revision history
The following table provides a revision history for this document.
Table 42. Revision history
Rev. No.
Date
0
7/2014
1
2/2015
Substantial Changes
Initial NDA release.
• Added information about 48 LQFP package in the following
sections:
• Ordering information
• Fields
Table continues on the next page...
60
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
Revision history
Table 42. Revision history (continued)
Rev. No.
Date
Substantial Changes
• Obtaining package dimensions
• Pinout
• In table "Power consumption operating behaviors", removed the
text "Maximum core fequency of 150 Mhz" from note for IDDA.
• In table "Typical device clock specifications", removed information
about High Speed run mode.
2
8/2015
• Updated instances of operating frequency from 150 MHz to 168
Mhz
• Changed document number from "KV4XP100M150" to
"KV4XP100M168" due to the change in operating frequency
• Part numbers ending with "15" changed to ending with "16"
• Removed instances of MKV45, MKV43, and MKV40 part numbers
• Updated MKV41 part numbers to MKV42
• Added part numbers MKV44F256VLL16 and MKV44F256VLH16
• Updated table "Orderable part numbers summary"
• In table Recommended Operating Conditions :
• Updated minimum digital supply voltage to 1.71 V
• Added footnote numbers 2 and 3
• Removed rows for IOH, IOL, NF, TR, and tFLRET
• Updated table Voltage and current operating behaviors
• Updated table Power mode transition operating behaviors
• Updated table Power consumption operating behaviors
• Updated table EMC radiated emissions operating behaviors
• Updated table Typical device clock specifications
• Updated table Thermal attributes
• Updated the PLL section of table MCG specifications
• Updated tersall value in table Flash timing specifications —
commands
• Added note to section 12-bit cyclic Analog-to-Digital Converter
(ADC) parameters
• Updated IDDA_DACL P and IDDA_DACH P values in table 12-bit DAC
operating behaviors
• Updated the pinouts
• Added section Enhanced NanoEdge PWM characteristics
3
06/2016
•
•
•
•
•
4
09/2019
• In Introduction, added this table table
• Updated ARM to Arm as per branding guidelines
• Removed Package Your Way Note for 48 LQFP package all over
the document
• Removed KMS content all over document
• Removed Debug trace timing specifications
• Added VHYS in Recommended Operating Conditions table
• Added ∆fints_t and ∆fintf_ft in MCG specifications table
• Updated minimum value of J1 parameter in SWD full voltage range
electricals and JTAG limited voltage range electricals
KV4x Data Sheet, Rev. 4, 09/2019
Changed occurences of Freescale to NXP
In the features list, added a section for "Kinetis Motor Suite"
Added KMS orderable part numbers
Added section Kinetis Motor Suite (KMS)
In table 12-bit ADC electrical specifications, changed typical value
of ENOB from 9.5 to 9.1
61
NXP Semiconductors
Revision history
Table 42. Revision history
Rev. No.
Date
Substantial Changes
• Updated the values of GAIN error parameter in 12-bit ADC
electrical specifications
• ADded maximum values of IADRUN in 12-bit ADC electrical
specifications
• ADded the maximum values and footnotes to IDDs in Power
Consumption operating behaviors table
• Updated the footnote from VREFH to VREF_OUT in 12-bit DAC
operating requirements
62
NXP Semiconductors
KV4x Data Sheet, Rev. 4, 09/2019
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Revision 4, 09/2019