Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document Number: MKW01Z128
Rev. 6, 04/2016
MKW01Z128
MKW01Z128
MKW01Z128
Highly-integrated, cost-effective
single-package solution for
sub-1 GHz applications
1
Introduction
The MKW01 device is highly-integrated, cost-effective,
smart radio, sub-1 GHz wireless node solution composed
of a transceiver supporting FSK, GFSK, MSK, or OOK
modulations with a low-power ARM® Cortex M0+
CPU. The highly integrated RF transceiver operates over
a wide frequency range including 315 MHz, 433 MHz,
470 MHz, 868 MHz, 915 MHz, 928 MHz, and 955 MHz
in the license-free Industrial, Scientific and Medical
(ISM) frequency bands. This configuration allows users
to minimize the use of external components.
The MKW01 is targeted for the following low-power
wireless applications:
• Automated Meter Reading
• Wireless Sensor Networks
• Home and Building Automation
• Wireless Alarm and Security Systems
• Industrial Monitoring and Control
Freescale supplements the MKW01 with tools and
software that include hardware evaluation and
© 2013-2016 Freescale Semiconductor, Inc. All rights reserved.
Package Information
Ordering Information
Device
Device Marking
MKW01Z128CHN MKW01Z128CHN
Package
60 LGA
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Software Solutions . . . . . . . . . . . . . . . . . . . . . 5
4 Smart Radio Sub-1 GHz Wireless Node . . . . 5
5 MKW01 Pin Assignments and Connections 9
6 System and Power Management . . . . . . . . 15
7 Development Environment . . . . . . . . . . . . . 20
8 System Electrical Specification . . . . . . . . . 20
9 Typical Applications Circuit . . . . . . . . . . . . 25
10Mechanical Drawings . . . . . . . . . . . . . . . . . . 28
Appendix AMKW01 MCU Section Data Sheet 30
development boards, software development IDE and applications, drivers, custom PHY usable with
Freescale’s IEEE 802.15.4 compatible MAC and SMAC.
2
Features
This section provides a simplified block diagram and highlights MKW01 features.
2.1
Block Diagram
Figure 1 shows a simplified block diagram of the MKW01.
Kinetis MKW01 Wireless MCU
Core
System
Memory
ARM Cortex-M0+
48 MHz
DMA
128 KB Flash
Low-Leakage
Wake-Up Unit
16 KB RAM
Debug
Interfaces
Interrupt
Controller
Sub-1 GHz Transceiver
RF Transmitter and
Receiver
32 MHz
Oscillator
PLL
Synthesizer
Packet Engine
(AES)
66 Byte
FIFO
Timers
Interfaces
Clocks
12-bit DAC
Six-Channel
Timer/PWM (TPM)
2x I2C
Phase-Locked
Loop
Periodic
Interrupt
Timers
3x UART
16-bit ADC
Analog
Analog
Comparator
FrequencyLocked Loop
1x SPI
Low-Power
Timer
GPIOs
Real-Time Clock
32-bit Timer
Touch Sensing
Reference
Oscillators
Internal Reference
Clocks
Figure 1. MKW01 Simplified Block Diagram
2.2
•
Features Summary
RF Transceiver Features
— Operating Voltage from 1.8V to 3.6V.
— Programmable bit rate up to 600kbps (FSK)
— High Sensitivity: down to -120 dBm at 1.2 kbps
— High Selectivity: 16-tap FIR Channel Filter
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•
— Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, 80 dB Blocking Immunity, no Image
Frequency response
— Low current: Rx = 16mA, 100nA register retention
— Programmable Pout : -18 to +17 dBm in 1 dB steps
— Constant RF performance over voltage range of chip
— Fully integrated synthesizer with a resolution of 61 Hz
— FSK, GFSK, MSK, GMSK and OOK modulations
— Built-in Bit Synchronizer performing Clock recovery
— Incoming Sync Word Recognition
— Automatic RF Sense with ultra-fast AFC
— Packet engine with CRC, AES-128 encryption and 66-byte FIFO
— Built-in temperature sensor and Low battery indicator
— 32 MHz crystal oscillator clock source
— Dedicated I/O’s for connection with an external 32 kHz crystal
— Can be configured to be compliant with the relevant sections of numerous world-wide
standards, including but not limited to: ARIB-T108 and T67, FCC 15.231, 15.247, and 15.249,
EN54-25, and ETSI 300 220.
MCU Features
System:
— 48 MHz Max. Central Processor Unit (CPU) frequency
— 24 MHz Max. Bus frequency
— Vectored Interrupt Controller (NVIC) with 32 core-vectored interrupts with 4 programmable
interrupt priority levels
— Asynchronous Wake-up Interrupt Controller (AWIC)
— 4 channel Direct Memory Access (DMA)
— DMA request multiplex
— Non Maskable Interrupt (NMI)
— COP Watchdog
— Low leakage Wake-up Unit (LLWU)
— Debug and Trace
– 2-pin Serial Wire Debug (SWD)
— 80-bit wide ID number
Memory:
— 128 KB P-Flash with 64 byte flash cache
— 16 KB RAM
Clocks:
— External crystal oscillator or resonator:
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—
—
—
—
– 32 - 40 kHz low range, low power or full swing
– 3 MHz - 32 MHz high range, low power or full swing
DC - 48 MHz external square wave input clock
Internal clock references:
– 31.25 kHz to 39.063 kHz oscillator with +/– 1.5% max. deviation from 0 to +70C
– 4 MHz oscillator with +/– 3% max. deviation across temperature
– 1 kHz oscillator
Phase Locked Loop (PLL) with up to 100 MHz VCO
Frequency Locked Loop (FLL):
– Low range: 20 - 25 MHz
– Mid range: 40 - 48 MHz
Analog:
— Power Management Controller (PMC) with low voltage warning (LVW) and detect with
selectable trip points.
— 16-bit analog to digital converter
– 11 single ended channels available
– 2 status, control and results registers
– DMA support
— 1 High Speed Comparator (HSCMP) with internal 6-bit digital to analog converters (DAC)
— One 12-bit DAC with DMA support and 2 word data buffer
Timers:
— Six channel Timer/PWM (TPM)
— Periodic interrupt timers
— 16-bit low-power timer (LPTMR) can be configured to operate as a time counter or as a pulse
counter, across all power modes, including the low-leakage modes
— Real-time clock 32-bit timer
Wired Communication Interface:
— One Serial Peripheral Interface (SPI) available externally
— Two Inter-Integrated Circuits (I2C) with DMA support
— Three Universal Asynchronous Receiver / Transmitter (UART) with DMA Support
– UART0 supports standard features plus:
• TxD pin can be configured as pseudo open drain for 1-wire half-duplex
• x4 to x32 oversampling
• Functional in VLPS mode
• LIN slave operation
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– UART1 and UART2 support standard features
Human Machine Interface (HMI)
— General Purpose Input/Output (GPIO) supporting:
– Default to disabled (no leakage)
– 4 pins with 18 mA high current drive capability
– Hysteresis and configurable pull up device on all input pins
– Slew rate and drive strength fixed on all output pins
– Single cycle GPIO control via IOPORT
— Touch Sensor Inputs (TSI)
– 9-channel
– Selectable single channel wakeup source available in all modes
– DMA support
— Pin Interrupt
1.8 V to 3.6 V operating voltage with on-chip voltage regulators
Temperature range of –40C to 85C
60-pin LGA (8x8 mm) package
3
Software Solutions
Freescale will support the MKW01x128 platform with several software solutions:
• A radio utility GUI will be available that allows testing of various features and setting registers. A
connectivity test firmware will allow a limited set of testing controlled with a terminal emulator on
any computer.
• SMAC (Simple Media Access Controller) — This codebase provides simple communication and
test apps based on drivers/PHY utilities available as source code. This environment is useful for
hardware and RF debug, hardware standards certification, and developing proprietary applications.
• Additional software will be available through 3rd party providers.
4
Smart Radio Sub-1 GHz Wireless Node
The MKW01 brings together a transceiver chip and an MCU chip on a single substrate to provide a small
footprint, cost-effective sub-1 GHz wireless node. The transceiver is controlled by the MCU through a
dedicated SPI interface. The SPI bus interface and some status signals are connected in-package the
substrate to eliminate the need for external connections. The SPI supports bit order swapping providing
hardware support for bit endianess reducing processing overhead.
4.1
RF Transceiver
The transceiver (see Figure 2) is a single-chip integrated circuit ideally suited for today's high performance
ISM band RF applications. Its advanced features set, including state of the art packet engine, greatly
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simplifies system design while the high level of integration reduces the external RF component bill of
material (BOM) to a handful of passive de-coupling and matching components. It is intended for use as a
high-performance, low-cost FSK, GFSK, MSK, GMSK, and OOK RF transceiver for robust, frequency
agile, half-duplex bi-directional RF links.
The MKW01 is intended for applications over a wide frequency range, including the 433 MHz, the
868 MHz European, and the 902-928 MHz North American ISM bands. Coupled with a link budget in
excess of 135 dB, the transceiver advanced system features include a 66 byte TX/RX FIFO, configurable
automatic packet handler, listen mode, temperature sensor and configurable DIO’s which greatly enhance
system flexibility while at the same time significantly reducing MCU requirements. The transceiver
complies with both ETSI and FCC regulatory requirements.
Figure 2. MKW01 Transceiver Block Diagram
The major RF communication parameters of the MKW01 transceiver are programmable and most can be
dynamically set. This feature offers the unique advantage of programmable narrow-band and wide-band
communication modes without the need to modify external components. The transceiver is also optimized
for low power consumption while offering high RF output power and channelized operation.
4.2
ARM ® 32-bit Cortex M0+ CPU
The in-package MCU integrated circuit features an ARM ® Cortex M0+ CPU, up to 16 KB RAM, 128
KB Flash memory, and a rich set of peripherals (see Section 2.2, “Features Summary”). The RF transceiver
is controlled through the MCU SPI port which is dedicated to the RF device interface. Two of the
transceiver status IO lines are also directly connected to the MCU GPIO to monitor the transceiver
operation. In addition, the transceiver reset and additional status can be connected to the MCU through
external connections.
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Operational modes of the MKW01 are determined by the software running on the MCU. The MCU itself
has a run mode as well as an array of low power modes that are coordinated by the PMC. The MCU in turn
set the operational modes of the transceiver which include sleep, standby, and radio operational modes.
Two common application scenarios are:
• Low power, battery-operated standalone wireless node - a common example of this configuration
would be a remote sensor monitor. The wireless node programmed for standalone operation,
typically has a low active-mode duty cycle, and is designed for long battery life, i.e., lowest power.
• Communication channel to a higher level controller - in this example, the wireless node
implements the lower levels of a communications stack and is subordinate to the primary
controller. Typically the MKW01 is connected to the controller through a command channel
implemented via a UART/SCI port or other serial communication port.
4.3
System Clock Configuration
The MKW01 device allows for various system clock configurations:
• Pins 46 & 47 are provided to input a 32 or 30 MHz crystal for the transceiver reference clock source
(required) as shown in Figure 3.
• The transceiver can be programmed to provide a programmable frequency clock output (DIO5
which alternates as CLKOUT, pin 54) that can be used as an external source to the CPU (see
Figure 3 and Figure 4). As a result, a single crystal system clock solution is possible where the
transceiver reference clock source. Routing CLKOUT to the MCU without dividing it is
recommended, but it can be divided by 2, 4, 8, 16 and 32.
• The MCU provides a trimmable internal reference clock and also supports an external clock
source. An optional on-chip frequency locked loop (FLL) can be used with either clock source to
support a CPU clock as high as 48 MHz at 3.6 V.
• Pins 16 and 15 are available to provide an external 32.768 kHz external clock source for the MCU.
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Figure 3. MKW01 Single Crystal System Clock Connection
Figure 4. MKW01 Two Crystal System Clock Connection
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MKW01 Pin Assignments and Connections
Figure 5 shows the MKW01 pinout.
Figure 5. MKW01 Pinout (Top View)
MKW01Z128 Datasheet, Rev. 6, 04/2016
Freescale Semiconductor, Inc.
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5.1
Pin Definitions
Table 1 details the MKW01 pinout and functionality.
Table 1. Pin Function Description (Sheet 1 of 5)
Pin Name1
Pin
Type
Description
Functionality
1
VREFH
Input
MCU high reference voltage for ADC
2
VREFL
Input
MCU low reference voltage for ADC
3
VSSA
Power Input
MCU ADC Ground
Connect to ground
4
VSS
Power Input
MCU Ground
Connect to ground
5
PTE16/ADC0_DP1/ADCO_S Digital Input / MCU Port E Bit 16 / ADC0 Single Ended
E1/SPI0_PCS0/TPM/UART2_ Output
analog channel input DP1/ ADC0 Single
TX
Ended analog channel input SE1 / SPI
module 0 PCS0 / TPM module Clock In 0 /
UART2_TX
6
PTE17/ADC0_DM1/ADCO_S
E5a/SPI0_SCK/
TPM_CLKIN1/UART2_RX/
LPTMR0_ALT3
7
PTE18/ADC0_DP2/ADC0_SE Digital Input / MCU Port E Bit 18 / ADC0 Single Ended
2/SPI0_MOSI/IIC0_SDA/SPI0 Output
analog channel input DP2/ ADC0 Single
_MISO
Ended analog channel input 2 / SPI module
0 MOSI / IIC0 Bus Data / SPI module 0
MISO
8
PTE19/ADC0_DM2/
ADC0_SE6a/SPI0_MISO
/IIC0_SCL/ SPI0_MOSI
9
PTE30/DAC0_OUT/
Digit-l Input /
ADCO_SE23/
Output
CMP0_IN4/TPM0_CH3/TPM_
CLKIN1
10
PTA0/SWD_CLK/TSI0_CH1/T Digital Input / MCU Port A Bit 0 / Serial Wire Data Clock
PM0_CH5
Output
/ Touch Screen Interface Channel 1/ TPM
module 0 Channel 5
11
PTA3/SWD_DIO/TSI0_CH4/
IIC1_SCL/TPM0_CH0
Digital Input / MCU Port A Bit 3 / Serial Wire Data DIO /
Output
Touch Screen Interface Channel 4 / IIC1
Bus Clock / TPM module 0 Channel 0
12
PTA4/NMI_b/TSI0_CH5/
IIC1_SDA/TPM0_CH1
Digital Input / MCU Port A Bit 4/ / Non Maskable
Output
Interrupt_ b/Touch Screen Interface
Channel 5 /IIC1 Bus Data / TPM module 0
Channel 1
Digital Input / MCU Port E Bit 17 / ADC0 Single Ended
Output
analog channel input DM1/ ADC0 Single
Ended analog channel input 5a / SPI
module 0 SCK / TPM module Clock In 1 /
UART2_RX / Low Power Timer Module 0
ALT3
Digital Input / MCU Port E Bit 19 / ADC0 Single Ended
Output
analog channel input DM2/ ADC0 Single
Ended analog channel input 6a / SPI
module 0 MISO / IIC0 Bus Clock / SPI
module 0 MOSI
MCU Port E Bit 30 / DAC0 Output/ ADC0
Single Ended analog channel input 23 /
Comparator 0 Analog Voltage Input 4/ TPM
Timer module 0 Channel 3 / TPM module
Clock In 1
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Table 1. Pin Function Description (Sheet 2 of 5)
Pin Name1
Pin
Type
Description
Functionality
13
PTA2/TSI0_CH3/UART0_TX/ Digital Input / MCU Port A Bit 2/Touch Screen Interface
TPM2_CH1
Output
Channel 3/UART module 0 Transmit / TPM
module 2 Channel 1
14
PTA1/TSI0_CH2/UART0_RX/
TPM2_CH0
Digital Input / MCU Port A Bit 1/Touch Screen Interface
Output
Channel 2/UART module 0 Receive / TPM
module Channel 0
15
PTA18/EXTAL0/UART1_RX/
TPM_CLKIN0
Digital Input / MCU Port A Bit 18 / EXTAL0/ UART
Output
module 1 Receive / TPM module Clock In 0
16
PTA19/XTAL0/UART1_TX/TP
M_CLKIN1/LPTMR0_ALT1
Digital Input / MCU Port A Bit 19 / XTAL0/ UART module
Output
1 Transmit / TPM module Clock In 1
/Low Power Timer module 0 ALT1
17
PTB0/ADC0_SE8/TSI0_CH0/
LLWU_P5/IIC0_SCL/
TPM1_CH0
Digital Input / MCU Port B Bit 0 / ADC0 Single Ended
Output
analog channel input SE8 / Touch Screen
Interface Channel 0/ Low Leakage Wake
Up Port 5 / IIC0 Bus Clock / TPM module 1
Channel 0
18
PTB1/ADCO_SE9/TSI0_CH6/ Digital Input / MCU Port B Bit 1 / ADC0 Single Ended
IIC0_SDA/ TPM1_CH1
Output
analog channel input SE9 / Touch Screen
Interface Channel 6 / IIC0 Bus Data / TPM
module 1 Channel 1
19
VDD
Power Input
MCU VDD supply input
Connect to system VDD
supply
20
VSS
Power Input
MCU Ground
Connect to ground
21
PTB2/ADC0_SE12/TSI0_CH7 Digital
/IIC0_SCL/TPM2_CH0
Input/Output
MCU Port B Bit 2 / ADC0 Single Ended
analog channel input SE12 / Touch Screen
Interface Channel 7 / IIC0 Bus Clock / TPM
Timer module 2 Channel 0
22
PTB17/TSI0_CH10/SPI1_MIS Digital
O/UART0_TX/TPM_CLKIN1/ Input/Output
SPI1_MOSI
MCU Port B Bit 17 / Touch Screen Interface
Channel 10/SPI1 MOSI or MISO/UART0
TX / TPM timer clock
23
PTC4/LLWU_P8/SPI0_PCS0/ Digital Input / MCU Port C bit 4 / Low leakage Wake Up
UART1_TX/TPM0_CH3
Output
port 8 / SPI0 Chip Select / UART1 TX /
TPM Timer module 0 channel 3
24
PTC1/ADC0_SE15/TSI0_CH1 Digital Input MCU Port C Bit 1 /ADC0 Single Ended
4/LLWU_P6/RTC_CLKIN/
Output /
analog channel input SE15/ Touch Screen
IIC1_SCL/TPM0_CH0
Analog Input Interface Channel 14/ Low Leakage Wake
Up Port 6 / Real Time Counter Clock Input/
IC1 Bus Clock/ TPM module 0 Channel 0
25
PTC2/ADC0_SE11/TSI0_CH1 Digital Input / MCU Port C Bit 2 / ADC0 Single Ended
5/IIC1_SDA/TPM0_CH1
Output /
analog channel input SE11/ / Touch Screen
Analog Input Interface Channel 15 / IIC1 Bus Data / TPM
module 0 Channel 1
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Table 1. Pin Function Description (Sheet 3 of 5)
Pin
Pin Name1
26
PTC3/LLWU_P7/UART1_RX/
TPM0_CH2/CLKOUTa
27
PTD4/LLWU_P14/SPI1_PCS0 Digital Input / MCU Port D Bit 4 / Low Leak Wake Up Port
/UART2_RX/TPM0_CH4
Output
14/ SPI module 1 PCS0 / UART2 Receiver
input / TPM module 0 Channel 4
28
PTD5/ADC0_SE6b/SPI1_SC
K/UART2_TX/TPM0_CH5
29
PTD6/ADC0_SE7b/LLWU_P1 Digital Input / MCU Port D bit 6 / ADC0 Single Ended
5/SPI1_MOSI/UART0_RX/SPI Output /
analog channel input SE7b / Low leakage
1_MISO
Analog Input Wake Up port 15 / SPI1 MOSI / UART0 RX
/ SPI module 1 MISO
30
NC
No Connect
31
PTD7/SPI0_MISO/UART0_TX Digital
/SPI1_MOSI
Input/Output
MCU Port D Bit 7 / SPI module 0 MISO /
UART module 0 Transmit / SPI module 1
MOSI
32
PTE0/SPI1_MISO/UART1_TX Digital
/RTC_CLKOUT/CMP0_OUT/ Input/Output
IIC1_SDA
MCU Port E Bit 0 / SPI module 1 MISO /
UART module 1 Transmit / Real Time
Counter Clock Output / Comparator 0
Analog voltage Output / IIC1 Bus Data
33
PTA20/RESETB
Digital
Input/Output
MCU Port A Bit 20/MCU RESET
34
PTE1 / SPI1_MOSI /
UART1_RX /SPI1_MISO /
IIC1_SCL
Digital
Input/Output
MCU Port E Bit 1 / SPI module 1 MOSI /
UART module 1 RX / SPI1_MISO /
IIC1_SCL
35
VBAT2 (RF)
Power Input
Transceiver VDD
Connect to system VDD
supply
36
GND/SCAN (RF)
Power Input
Transceiver Ground
Connect to ground
37
RXTX (RF)
Digital
Output
Transceiver Rx / Tx RF Switch Control
Output; high when in TX
38
GND_PA2 (RF)
Power Input
Transceiver RF Ground
39
RFIO (RF)
RF Input /
Output
Transceiver RF Input / Output
40
GND_PA1 (RF)
Power Input
Transceiver RF Ground
41
PA_BOOST (RF)
RF Output
Transceiver Optional High-Power PA
Output
42
VR_PA (RF)
Power
Output
Transceiver regulated output voltage for
VR_PA use.
De-coupling cap
suggested.
43
VBAT1 (RF)
Power Input
Transceiver VDD for RF circuitry
Connect to system VDD
supply
Type
Description
Functionality
Digital Input / MCU Port C Bit 3 / Low Leakage Wake Up
Output
Port 7 / UART module 1 Receive / TPM
module 0 Channel 2/ Clock OutA
Digital Input / MCU Port D bit 5 / ADC0 Single Ended
Output /
analog channel input SE6b / SPI1 clock /
Analog Input UART2 TX / TPM module 0 Channel 5
Connect to ground
Connect to ground
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Table 1. Pin Function Description (Sheet 4 of 5)
Pin Name1
Pin
Type
Description
Functionality
44
VR_ANA (RF)
Power
Output
Transceiver regulated output voltage for
analog circuitry.
Decouple to ground with
100 nF capacitor
45
VR_DIG (RF)
Power
Output
Transceiver regulated output voltage for
digital circuitry.
Decouple to ground with
100 nF capacitor
46
XTA (RF)
Xtal Osc
Transceiver crystal reference oscillator
Connect to 32 MHz
crystal and load capacitor
47
XTB (RF)
Xtal Osc
Transceiver crystal reference oscillator
Connect to 32 MHz
crystal and load capacitor
48
RESET (RF)
Digital Input
Transceiver hardware reset input
Typically driven from
MCU GPIO
49
DIO0/PTE2/SPI1_SCK
Digital
Input/Output
Internally connected to Transceiver GPIO
bit 0 and MCU Port E bit 2 / SPI1 clock
MCU IO and Transceiver
IO connected in-package
50
DIO1/PTE3/SPI1_MISO/SPI1
_MOSI
Digital
Input/Output
Internally connected to Transceiver GPIO
bit 1 and MCU Port E bit 3 /SPI1 in or out
MCU IO and Transceiver
IO connected in-package
51
DIO2
Digital
Input/Output
Transceiver GPIO Bit 2
52
DIO3
Digital
Input/Output
Transceiver GPIO Bit 3
53
DIO4
Digital
Input/Output
Transceiver GPIO Bit 4
54
DIO5/CLKOUT
Digital
Input/Output
Transceiver GPIO Bit 5 / ClkOut
Commonly programmed
as ClkOut to supply MCU
clock; connect to Pin 15
55
VDD
Power Input
MCU VDD supply
Connect to VDD supply
56
VDDAD
Power Input
MCU Analog supply
Connect to Analog
supply
57
MISO/PTC7/SPI0_MISO/SPI0 Digital
_MOSI
Input/Output
Internal SPI data connection from
Transceiver MISO bit 1 to MCU SPI0 (Port
C bit 7 )
• MCU IO and
Transceiver IO
connected in-package
• MCU IO must be
configured for this
connection
58
NSS/PTD0/SPI0_PCS0
Digital
Input/Output
Internal SPI select connection between
Transceiver NSS and MCU SPI0 (Port D bit
0)
• MCU IO and
Transceiver IO
connected in-package
• MCU IO must be
configured for this
connection
59
SCK/PTC5/SPI0_SCK
Digital
Input/Output
Internal SPI clock connection between
Transceiver SCK and MCU SPI0 (port C bit
5)
• MCU IO and
Transceiver IO
connected in-package
• MCU IO must be
configured for this
connection
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Table 1. Pin Function Description (Sheet 5 of 5)
Pin Name1
Pin
60
MOSI/PTC6/SPI0_MOSI/
SPI0_MISO
FLAG VSS
1
Type
Description
Functionality
Digital
Input/Output
Internal SPI data connection to Transceiver
MOSI bit 1 to MCU SPI0 (Port C bit 6 )
• MCU IO and
Transceiver IO
connected in-package
• MCU IO must be
configured for this
connection
Power input
External package flag. Common VSS
Connect to ground.
Refer to ADD Table 1-3 for additional pin-out information on default and alternate setting selections.
5.2
Internal Functional Interconnects
The MCU provides control to the transceiver through the SPI Port and receives status from the transceiver
from the DIOx pins. Certain interconnects between the devices are routed on chip. In addition, the signals
are brought out to external pads.
Table 2. MKW01 Internal Functional Interconnects
Pin
MCU Signal
Transceiver
Signal
Description
49
DIO0/PTE2/SPI1_
SCK
DIO0
Transceiver DIO0 can be programmed to provide status to the MCU
50
DIO1/PTE3/SPI1_
MISO/SPI1_MOSI
DIO1
Transceiver DIO1 can be programmed to provide status to the MCU
57
MISO/PTC7/SPI0_
MISO/SPI0_MOSI
MISO
SPI data from transceiver to MCU
58
NSS/PTD0/SPI0_
PCS0
NSS
SPI chip select
59
SCK/PTC5/SPI0_
SCK
SCK
SPI Clock
60
MOSI/PTC6/SPI0_
MOSI/SPI0_MISO
MOSI
SPI data from MCU to transceiver
•
•
•
5.3
NOTE
As shown in Table 2, the MCU SPI Port pin selection must be
configured by software.
The transceiver DIO pins must be programmed to provide desired status.
Enhanced performance can be achieved by additionally routing some
DIO pins externally to other GPIO pins.
External Functional Interconnects
In addition to the in-package device interconnection, other external connections between the MCU and the
transceiver are common:
MKW01Z128 Datasheet, Rev. 6, 04/2016
14
Freescale Semiconductor, Inc.
1. Freescale recommends driving/controlling the transceiver reset from an MCU GPIO - This allows
overriding control of the transceiver from the system application.
2. The other DIO2-DIO4 status and RXTX signals can prove useful for monitoring the transceiver
operation - the DIO2-DIO4 signals must be programmed to provide operational status. All signals
must be connected externally to appropriate MCU GPIO for this function.
6
System and Power Management
The MKW01 consists of an independent transceiver and MCU. The MCU controls the transceiver through
programming of the SPI Port, and sets its operational mode through this control channel. Total current
draw for the MKW01 is dependent on the operation mode of both devices where different modes allow for
different levels of power-down. Some additional features supported are:
• Transceiver Sleep with MCU set at the lowest power state.
• The transceiver mode selection being independent of the MCU’s mode selection.
• The transceiver uses/powers-up the transmitter or receiver only as required.
• MCU peripheral control clock gating being disabled on a module-by-module basis to provide
lowest power.
• RTC can be used as wake-up timer.
• LLWU (Low Leakage Wake-up Unit) available.
6.1
MCU Power Modes
The MCU has 9 different modes of operation to allow the user to optimize power consumption for the level
of functionality needed. Depending on the STOP requirements of the user application, a variety of STOP
modes are available that provide state retention, partial power down or full power down of certain logic
and/or memory. I/O states are held in all modes of operation. Table 3 outlines the various available power
modes of MCU operation.
For each RUN mode there is a corresponding WAIT and STOP mode. WAIT modes are similiar to ARM
sleep modes. STOP modes (VLPS, STOP) are similiar to ARM sleep deep mode. The very low power run
(VLPR) operating mode can greatly reduce runtime power when the maximum bus frequency is not
required to handle application needs. The 3 primary modes of operation are RUN, WAIT and STOP. The
WFI instruction invokes both WAIT and STOP modes for the MCU. The primary modes are augmented
in a number of ways to provide lower power based on application needs.
MKW01Z128 Datasheet, Rev. 6, 04/2016
Freescale Semiconductor, Inc.
15
Table 3. MCU power modes
Description
Core Mode
Normal
Recovery
Method
Allows maximum performance of chip. Default mode out of reset;
onchip voltage regulator is on.
Run
—
Normal Wait - via Allows peripherals to function while the core is in sleep mode,
WFI
reducing power. NVIC remains sensitive to interrupts;
peripherals continue to be clocked.
Sleep
Interrupt
Normal Stop - via Places chip in static state. Lowest power mode that retains all
WFI
registers while maintaining LVD protection. NVIC is disabled;
AWIC is used to wake up from interrupt; peripheral clocks are
stopped.
Sleep Deep
Interrupt
VLPR (Very Low On-chip voltage regulator is in a low power mode that supplies
Power Run)
only enough power to run the chip at a reduced frequency.
Reduced frequency Flash access mode (1 MHz); LVD off; in
BLPI clock mode, the fast internal reference oscillator is
available to provide a low power nominal 4 MHz source for the
core with the nominal bus and flash clock required to be
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