NXP Semiconductors
Data Sheet: Technical Data
MKW2xDxxx
Rev. 2, 05/2016
MKW2xD Data Sheet
Supports MKW24D512V, MKW22D512V, MKW21D512V, and
MKW21D256V Products
MKW2xDxxxVHA5
The MKW2xD is a low power, compact integrated device
consisting of:
• A high-performance 2.4 GHz IEEE 802.15.4 compliant
radio transceiver
• A powerful ARM Cortex-M4 MCU system with connectivity
• Precision mixed signal analog peripherals
The MKW2xD family of devices are used to easily enable
connectivity based on the IEEE 802.15.4 Standard.
Core Processor and Memories
• 50 MHz Cortex-M4 CPU with DSP capabilities
• Up to 512 KB of flash memory
• Up to 64 KB of SRAM
Typical Applications
• Smart Energy 1.x
• ZigBee Home Automation
• ZigBee Healthcare
• ZigBee RF4CE
• ZigBee Light Link
• Thread
• Home Area Networks consisting of
• Meters
• Gateways
• In-home displays
• Connected appliances
• Networked Building Control and Home Automations
with
• Lighting Control
• HVAC
• Security
64 LQFP
8.0x8.0x0.91 mm P 0.5 mm
Peripherals
• USB
• Cryptographic Acceleration
• 16-bit ADC
• 12-bit DAC
• Flexible timers
Radio transceiver performance
• Up to –102 dBm receiver sensitivity
• +8 dBm maximum transmit output power
• Up to 58 dBm channel rejection
• Current consumption is minimized with peak
transmit current of 17 mA at 0 dBm output power,
and peak receive current of 15 mA in Low Power
Preamble Search mode.
Package and Operating Characteristics
• Packaged in an 8 x 8 mm LGA with 56 contacts
• Voltage range: 1.8 V to 3.6 V
• Ambient temperature range: –40°C to 105°C
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products. © 2013–2016 NXP B.V.
Ordering Information
Operatin
g Temp
Range
(TA)
Device
Memory
Options
Package
Description
MKW21D256VHA5(R)
-40 to
105°C
8x8 LGA (R: tape
and reel)
32 KB
SRAM,
256 KB
flash
Additional FlexMemory with up to 64 KB FlexNVM and
up to 4 KB FlexRAM. No USB.
MKW21D512VHA5(R)
-40 to
105°C
8x8 LGA (R: tape
and reel)
64 KB
SRAM,
512 KB
flash
Supports higher memory option and additional GPIO.
No USB. No FlexNVM or FlexRAM.
MKW22D512VHA5(R)
-40 to
105°C
8x8 LGA (R: tape
and reel)
64 KB
SRAM,
512 KB
flash
Supports full speed USB 2.0. No FlexNVM or
FlexRAM.
MKW24D512VHA5(R)
-40 to
105°C
8x8 LGA (R: tape
and reel)
64 KB
SRAM,
512 KB
flash
Supports Smart Energy 2.0 and full-speed USB 2.0.
No FlexNVM or FlexRAM.
Related Resources
Type
Description
Resource
Selector
Guide
The Kinetis MCUs Product Selector is a web-based tool that features
interactive application wizards and a dynamic product selector.
Product Selector
Fact Sheet
The Fact Sheet gives overview of the product key features and its uses.
KW2X Fact Sheet
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
MKW2xDRM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Package
drawing
Package dimensions are provided in package drawings.
98ASA00393D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
Table of Contents
1 Features.............................................................................. 4
1.1 Block diagram............................................................ 4
1.2 Radio features............................................................4
1.3 Microcontroller features............................................. 5
2 Transceiver description....................................................... 8
2.1 Key specifications...................................................... 8
2.2 RF interface and usage..............................................9
2.2.1 Clock output feature.......................................9
2.3 Transceiver functions.................................................10
2.3.1 Receive.......................................................... 10
2.3.2 Transmit......................................................... 10
2.3.3 Clear channel assessment (CCA), energy
3
4
5
6
detection (ED), and link quality indicator
(LQI)...............................................................11
2.3.4 Packet processor........................................... 12
2.3.5 Packet buffering............................................. 13
2.4 Dual PAN ID...............................................................14
System and power management.........................................15
3.1 Modes of operation.................................................... 15
3.2 Power management...................................................15
Radio Peripherals................................................................16
4.1 Clock output (CLK_OUT)........................................... 16
4.2 General-purpose input output (GPIO)........................16
4.3 Serial peripheral interface (SPI).................................18
4.3.1 Features.........................................................18
4.4 Antenna diversity....................................................... 19
4.5 RF Output Power Distribution.................................... 19
MKW2xD operating modes................................................. 20
5.1 Transceiver Transmit Current Distribution................. 21
MKW2xD electrical characteristics...................................... 22
6.1 Radio recommended operating conditions................ 22
6.2 Ratings.......................................................................23
6.2.1 Thermal handling ratings............................... 23
6.2.2 Moisture handling ratings...............................23
6.2.3 ESD handling ratings..................................... 23
6.2.4 Voltage and current operating ratings............24
7 MCU Electrical characteristics.............................................24
7.1 Maximum ratings........................................................24
7.2 AC electrical characteristics.......................................25
7.3 Nonswitching electrical specifications........................26
MKW2xD Data Sheet, Rev. 2, 05/2016
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
Voltage and current operating requirements..26
LVD and POR operating requirements.......... 27
Voltage and current operating behaviors....... 28
Power mode transition operating behaviors...28
Power consumption operating behaviors.......29
EMC radiated emissions operating
behaviors....................................................... 33
7.3.7 Designing with radiated emissions in mind.... 34
7.3.8 Capacitance attributes................................... 34
7.4 Switching specifications............................................. 34
7.4.1 Device clock specifications............................ 34
7.4.2 General switching specifications....................35
7.5 Thermal specifications............................................... 36
7.5.1 Thermal operating requirements....................36
7.5.2 Thermal attributes.......................................... 36
7.6 Peripheral operating requirements and behaviors..... 37
7.6.1 Core modules.................................................37
7.6.2 System modules............................................ 40
7.6.3 Clock modules............................................... 40
7.6.4 Memories and memory interfaces..................45
7.6.5 Security and integrity modules.......................49
7.6.6 Analog............................................................50
7.6.7 Timers............................................................ 57
7.6.8 Communication interfaces............................. 57
8 Transceiver Electrical Characteristics................................. 66
8.1 DC electrical characteristics.......................................66
8.2 AC electrical characteristics.......................................67
8.3 SPI timing: R_SSEL_B to R_SCLK........................... 68
8.4 SPI timing: R_SCLK to R_MOSI and R_MISO.......... 69
9 Crystal oscillator reference frequency................................. 69
9.1 Crystal oscillator design considerations.....................69
9.2 Crystal requirements..................................................69
10 Pin diagrams and pin assignments..................................... 71
10.1 MKW21D256/MKW21D512 Pin Assignment............. 71
10.2 MKW22/24D512V Pin Assignment............................ 72
10.3 Pin assignments.........................................................72
11 Dimensions..........................................................................76
11.1 Obtaining package dimensions..................................76
12 Revision History.................................................................. 77
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NXP Semiconductors
Features
1 Features
This section provides a simplified block diagram and highlights the device features.
1.1 Block diagram
Core
ARM® CortexTM –M4
50 MHz
Debug
Interfaces
DSP
Interrupt Controller
Security
and Integrity
Cyclic
Redundancy
Check (CRC)
16‐bit
ADC
Tamper Detect
High‐Speed
Comparator
with 6‐bit
DAC
Cryptography
Authentication
Unit
Internal and
External
Watchdogs
Program Flash
(up to 512 KB)
DMA
FlexNVM
64 KB
4 KB FlexRAM
MKW21D256 only
Timers
SRAM
(up to 64 KB)
IEEE 802.15.4 2006
2.4 GHz
Antenna Diversity
32 MHz
OSC
Communication Interfaces
FlexTimer
USB On‐the‐Go
(HS)
Programmable
Delay Block
I2C
Periodic Interrupt
Timers
UART
(ISO 7816)
USB Device
Charger Detect
(DCD)
SPI
USB Voltage
Regulator
Low‐Power
Timer
Independent
Real‐Time
Clock (RTC)
Random Number
Generator
Standard Feature
Memories
Low‐Leakage
Wake‐up Unit
Analog
RF Transceiver
System
Dual
PAN ID
SPI
Clocks
Phase‐Locked
Loop
Frequency
Locked Loop
Low/High
Frequency
Oscillators
Internal
Reference
Clocks
Optional
Figure 1. MKW2xD simplified block diagram
1.2 Radio features
• Fully compliant 802.15.4 Standard transceiver supports 250 kbps data rate with OQPSK modulation in 5.0 MHz channels with direct sequence spread-spectrum
(DSSS) encode and decode
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MKW2xD Data Sheet, Rev. 2, 05/2016
Features
• Operates on one of 16 selectable channels in the 2.4 GHz frequency ISM band
• Programmable output power
• Supports 2.36 to 2.4 GHz Medical Band (MBAN) frequencies with same
modulation as IEEE 802.15.4
• Hardware acceleration for IEEE® 802.15.4 2006 packet processing
• Random number generator
• Support for dual PAN mode
• 32 MHz crystal reference oscillator with on board trim capability to supplement
external load capacitors
• Programmable frequency clock output (CLK_OUT)
• Control port for Antenna Diversity mode
• Clocks
• 32 MHz crystal oscillator
• Internal 1 kHz low power oscillator
• DC to 32 MHz external square wave input clock
• Small RF footprint
• Differential input/output port used with external balun
• Integrated transmit/receive switch
• Supports single ended and antenna diversity options
• Low external components count
• Supports external PA and LNA
1.3 Microcontroller features
• Core:
• ARM Cortex-M4 Core at 50 MHz (1.25 MIPS/MHz)
• Supports DSP instructions
MKW2xD Data Sheet, Rev. 2, 05/2016
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Features
• Nested vectored interrupt controller (NVIC)
• Asynchronous wake-up interrupt controller (AWIC)
• Debug and trace capability
• 2-pin serial wire debug (SWD)
• IEEE 1149.1 Joint Test Action Group (JTAG)
• IEEE 1149.7 compact JTAG (cJTAG)
• Trace port interface unit (TPIU)
• Flash patch and breakpoint (FPB)
• Data watchpoint and trace (DWT)
• Instrumentation trace macrocell (ITM)
• Enhanced trace macrocell (ETM)
• System and power management:
• Software and hardware watchdog with external monitor pin
• DMA controller with 16 channels
• Low-leakage wake-up unit (LLWU)
• Power management controller with 10 different power modes
• Non-maskable interrupt (NMI)
• 128-bit unique identification (ID) number per chip
• Memories and memory interfaces:
• Up to 512 KB Program Flash
• Up to 64 KB of SRAM
• In MKW21D256, FlexMemory with up to 64 KB FlexNVM and up to 4 KB
FlexRAM can be partitioned.
• EEPROM has endurance of 10 million cycles over full voltage and temperature
range and read-while-write capability
• Flash security and protection features
• Serial flash programming interface (EzPort)
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MKW2xD Data Sheet, Rev. 2, 05/2016
Features
• Clocks
• Multi-purpose clock generator
• PLL and FLL operation
• Internal reference clocks (32 kHz or 2 MHz)
• Three separate crystal oscillators
• 3 MHz to 32 MHz crystal oscillator for MCU
• 32 kHz to 40 kHz crystal oscillator for MCU or RTC
• 32 MHz crystal oscillator for Radio
• Internal 1 kHz low power oscillator
• DC to 50 MHz external square wave input clock
• Security and integrity
• Hardware CRC module to support fast cyclic redundancy checks
• Tamper detect and secure storage
• Hardware random-number generator
• Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and
SHA-256 algorithms
• 128-bit unique identification (ID) number per chip
• Analog
• 16-bit SAR ADC
• High-speed Analog comparator (CMP) with 6-bit DAC
• Timers
• Up to 12 channels; 7 channels support external connections; 5 channels are
internal only
• Carrier modulator timer (CMT)
• Programmable delay block (PDB)
• 1x4ch programmable interrupt timer (PIT)
MKW2xD Data Sheet, Rev. 2, 05/2016
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Transceiver description
• Low-power timer (LPT)
• FlexTimers that support general-purpose PWM for motor control functions
• Communications
• One SPI
• Two I2C with SMBUS support
• Three UARTs (w/ ISO7816, IrDA, and hardware flow control)
• One USB On-The-Go Full Speed
• Human-machine interface
• GPIO with pin interrupt support, DMA request capability, digital glitch filter,
and other pin control options
• Operating characteristics
• Voltage range 1.8 V - 3.6 V
• Flash memory programming down to 1.8 V
• Temperature range (TA) -40 to 105°C
2 Transceiver description
2.1 Key specifications
MKW2xD meets or exceeds all IEEE 802.15.4 performance specifications applicable to
2.4 GHz ISM and MBAN (Medical Band Area Network) bands. Key specifications for
MKW2xD are:
• ISM band:
• RF operating frequency: 2405 MHz to 2480 MHz (center frequency range)
• 5 MHz channel spacing
• MBAN band:
• RF operating frequency: 2360 MHz to 2400 MHz (center frequency range)
• MBAN channel page 9 is (2360 MHz-2390 MHz band)
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MKW2xD Data Sheet, Rev. 2, 05/2016
Transceiver description
• Fc = 2363.0 + 1.0 * k in MHz for k = 0, 1, 2, ...26
• MBAN channel page 10 is (2390 MHz-2400 MHz band)
• Fc = 2390.0 + 1.0 * k in MHz for k = 0, 1, 2, ...8
• IEEE 802.15.4 Standard 2.4 GHz modulation scheme
• Chip rate: 2000 kbps
• Data rate: 250 kbps
• Symbol rate: 62.5 kbps
• Modulation: OQPSK
• Receiver sensitivity: -102 dBm, typical (@1% PER for 20 byte payload packet)
• Differential bidirectional RF input/output port with integrated transmit/receive
switch
• Programmable output power from -35 dBm to +8 dBm.
2.2 RF interface and usage
The MKW2xD RF output ports are bidirectional (diplexed between receive/transmit
modes) and differential enabling interfaces with numerous off-chip devices such as a
balun. When using a balun, this device provides an interface to directly connect
between a single-ended antenna and the MKW2xD RF ports. In addition, MKW2xD
provides four output driver ports that can have both drive strength and slew rate
configured to control external peripheral devices. These signals designated as
ANT_A, ANT_B, RX_SWITCH, and TX_SWITCH when enabled are switched via
an internal hardware state machine. These ports provide control features for peripheral
devices such as:
• Antenna diversity modules
• External PAs
• External LNAs
• T/R switches
MKW2xD Data Sheet, Rev. 2, 05/2016
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Transceiver functions
2.2.1 Clock output feature
The CLK_OUT digital output can be enabled to drive the system clock to the MCU.
This provides a highly accurate clock source based on the transceiver reference
oscillator. The clock is programmable over a wide range of frequencies divided down
from the reference 32 MHz (see Table 2). The CLK_OUT pin will be enabled upon
POR. The frequency CLK_OUT default to 4 MHz (32 MHz/8).
2.3 Transceiver functions
2.3.1 Receive
The receiver has the functionality to operate in either normal run state or low power run
state that can be considered as a partial power down mode. Low power run state can
save a considerable amount of current by duty-cycling some sections of the receiver
lineup during preamble search and is referred to as Low Power Preamble Search mode
(LPPS).
The radio receiver path is based upon a near zero IF (NZIF) architecture incorporating
front end amplification, one mixed signal down conversion to IF that is programmably
filtered, demodulated and digitally processed. The RF front end (FE) input port is
differential that shares the same off chip matching network with the transmit path.
2.3.2 Transmit
MKW2xD transmits OQPSK modulation having power and channel selection
adjustment per user application. After the channel of operation is determined, coarse
and fine tuning is executed within the Frac-N PLL to engage signal lock. After signal
lock is established, the modulated buffered signal is then routed to a multi-stage
amplifier for transmission. The differential signals at the output of the PA (RFOUTP,
RFOUTN) are converted as single ended (SE) signals with off chip components as
required.
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MKW2xD Data Sheet, Rev. 2, 05/2016
Transceiver functions
2.3.3 Clear channel assessment (CCA), energy detection (ED), and
link quality indicator (LQI)
The MKW2xD supports three clear channel assessment (CCA) modes of operation
including energy detection (ED) and link quality indicator (LQI). Functionality for
each of these modes is as follows.
2.3.3.1
CCA mode 1
CCA mode 1 has two functions:
• To estimate the energy in the received baseband signal. This energy is estimated
based on receiver signal strength indicator (RSSI).
• To determine whether the energy is greater than a set threshold.
The estimate of the energy can also be used as the Link Quality metric. In CCA Mode
1, the MKW2xD must warm up from Idle to Receive mode where RSSI averaging
takes place.
2.3.3.2
CCA mode 2
CCA mode 2 detects whether there is any 802.15.4 signal transmitting in the
frequency band that an 802.15.4 transmitter intends to transmit. From the definition of
CCA mode 2 in the 802.15.4 standard, the requirement is to detect an 802.15.4
complied signal. Whether the detected energy is strong or not is not important for
CCA mode 2.
2.3.3.3
CCA mode 3
CCA mode 3 as defined by 802.15.4 standard is implemented using a logical
combination of CCA mode 1 and CCA mode 2. Specifically, CCA mode 3 operates in
one of two operating modes:
• CCA mode 3 is asserted if both CCA mode 1 and CCA mode 2 are asserted.
• CCA mode 3 is asserted if either CCA mode 1 or CCA mode 2 is asserted.
This mode setting is available through a programmable register.
MKW2xD Data Sheet, Rev. 2, 05/2016
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NXP Semiconductors
Transceiver functions
2.3.3.4
Energy detection (ED)
Energy detection (ED) is based on receiver signal strength indicator (RSSI) and
correlator output for the 802.15.4 standard. ED is an average value of signal strength.
The magnitude from this measurement is calculated from the digital RSSI value that is
averaged over a 128 μs duration.
2.3.3.5
Link quality indicator (LQI)
Link quality indicator (LQI) is based on receiver signal strength indicator (RSSI) or
correlator output for the 802.15.4 standard. In this mode, the RSSI measurement is done
during normal packet reception. LQI computations for the MKW2xD are based on
either digital RSSI or correlator peak values. This setting is executed through a register
bit where the final LQI value is available 64 μs after preamble is detected. If a
continuous update of LQI based on RSSI throughout the packet is desired, it can be read
in a separate 8-bit register by enabling continuous update in a register bit.
2.3.4 Packet processor
The MKW2xD packet processor performs sophisticated hardware filtering of the
incoming received packet to determine if the packet is both PHY- and MAC-compliant,
is addressed to this device, if the device is a PAN coordinator and whether a message is
pending for the sending device. The packet processor greatly reduces the packet
filtering burden on software allowing it to tend to higher-layer tasks with a lower
latency and smaller software footprint.
2.3.4.1 Features
• Aggressive packet filtering to enable long, uninterrupted MCU sleep periods
• Fully compliant with both 2003 and 2006 versions of the 802.15.4 wireless
standard
• Supports all frame types, including reserved types
• Supports all valid 802.15.4 frame lengths
• Enables auto-Tx acknowledge frames (no MCU intervention) by parsing of frame
control field and sequence number
• Supports all source and destination address modes, and also PAN ID compression
• Supports broadcast address for PAN ID and short address mode
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MKW2xD Data Sheet, Rev. 2, 05/2016
Transceiver functions
• Supports “promiscuous” mode, to receive all packets regardless of address- and
rules-checking
• Allows frame type-specific filtering (e.g., reject all but beacon frames)
• Supports SLOTTED and non-SLOTTED modes
• Includes special filtering rules for PAN coordinator devices
• Enables minimum-turnaround Tx-acknowledge frames for data-polling requests
by automatically determining message-pending status
• Assists MCU in locating pending messages in its indirect queue for data-polling
end devices
• Makes available to MCU detailed status of frames that fail address- or ruleschecking.
• Supports Dual PAN mode, allowing the device to exist on 2 PAN's
simultaneously
• Supports 2 IEEE addresses for the device
• Supports active promiscuous mode
2.3.5 Packet buffering
The packet buffer is a 128-byte random access memory (RAM) dedicated to the
storage of 802.15.4 packet contents for both TX and RX sequences. For TX
sequences, software stores the contents of the packet buffer starting with the frame
length byte at packet buffer address 0 followed by the packet contents at the
subsequent packet buffer addresses. For RX sequences the incoming packet's frame
length is stored in a register external to the packet buffer. Software will read this
register to determine the number of bytes of packet buffer to read. This facilitates
DMA transfer through the SPI. For receive packets, an LQI byte is stored at the byte
immediately following the last byte of the packet (frame length +1). Usage of the
packet buffer for RX and TX sequences is on a time-shared basis; receive packet data
will overwrite the contents of the packet buffer. Software can inhibit receive-packet
overwriting of the packet buffer contents by setting the PB_PROTECT bit. This will
block RX packet overwriting, but will not inhibit TX content loading of the packet
buffer via the SPI.
MKW2xD Data Sheet, Rev. 2, 05/2016
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Transceiver functions
2.3.5.1 Features
• 128 byte buffer stores maximum length 802.15.4 packets
• Same buffer serves both TX and RX sequences
• The entire Packet Buffer can be uploaded or downloaded in a single SPI burst.
• Automatic address auto-incrementing for burst accesses
• Single-byte access mode supported.
• Entire packet buffer can be accessed in hibernate mode
• Under-run error interrupt supported
2.4 Dual PAN ID
In the past, radio transceivers designed for IEEE 802.15.4 applications allowed a device
to associate to one and only one PAN (Personal Area Network) at any given time. The
MKW2xD represents a high-performance SiP that includes hardware support for a
device to reside in two networks simultaneously. In optional Dual PAN mode, the
device alternates between the two (2) PANs under hardware or software control.
Hardware support for Dual PAN operation consists of two (2) sets of PAN and IEEE
addresses for the device, two (2) different channels (one for each PAN) and a
programmable timer to automatically switch PANs (including on-the-fly channel
changing) without software intervention. There are control bits to configure and enable
Dual PAN mode, and read only bits to monitor status in Dual PAN mode. A device can
be configured to be a PAN coordinator on either network, both networks or neither.
For the purpose of defining PAN in the context of Dual PAN mode, two (2) sets of
network parameters are maintained; PAN0 and PAN1. PAN0 and PAN1 will be used to
refer to the two (2) PANs where each parameter set uniquely identifies a PAN for Dual
PAN mode. These parameters are described in Table 1.
Table 1. PAN0 and PAN1 descriptions
PAN0
PAN1
Channel0 (PHY_INT0, PHY_FRAC0)
Channel1 (PHY_INT1, PHY_FRAC1)
MacPANID0 (16-bit register)
MacPANID1 (16-bit register)
MacShortAddrs0 (16-bit register)
MacShortAddrs1 (16-bit register)
MacLongAddrs0 (64-bit registers)
MacLongAddrs1 (64-bit registers)
PANCORDNTR0 (1-bit register)
PANCORDNTR1 (1-bit register)
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MKW2xD Data Sheet, Rev. 2, 05/2016
System and power management
During device initialization if Dual PAN mode is used, software will program both
parameter sets to configure the hardware for operation on two (2) networks.
3 System and power management
The MKW2xD is a low power device that also supports extensive system control and
power management modes to maximize battery life and provide system protection.
3.1 Modes of operation
The transceiver modes of operation include:
• Idle mode
• Doze mode
• Low power (LP) / hibernate mode
• Reset / powerdown mode
• Run mode
3.2 Power management
The MKW2xD power management is controlled through programming the modes of
operation. Different modes allow for different levels of power-down and RUN
operation. For the receiver, programmable power modes available are:
• Preamble search
• Preamble search sniff
• Low Power Preamble Search (LPPS)
• Fast Antenna Diversity (FAD) Preamble search
• Packet decoding
MKW2xD Data Sheet, Rev. 2, 05/2016
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Radio Peripherals
4 Radio Peripherals
The MKW2xD provides a set of I/O pins useful for suppling a system clock to the
MCU, controlling external RF modules/circuitry, and GPIO.
4.1 Clock output (CLK_OUT)
MKW2xD integrates a programmable clock to source numerous frequencies for
connection with various MCUs. Package pin 39 can be used to provide this clock source
as required allowing the user to make adjustments per their application requirement.
The transceiver CLK_OUT pin is internally connected to the MCU EXTAL pin so that
no external connection is needed to drive the MCU clock.
Care must be taken that the clock output signal does not interfere with the reference
oscillator or the radio. Additional functionality this feature supports is:
• XTAL domain can be completely gated off (hibernate mode)
• SPI communication allowed in hibernate
Table 2. CLK_OUT
CLK_OUT_DIV [2:0]
CLK_OUT frequency
0
32 MHz1
1
16 MHz
2
8 MHz
3
4 MHz
4
2 MHz
5
1 MHz
6
62.5 kHz
7
32.786 kHz
1
1
1. May require high drive strength for proper signal integrity.
There is an enable/disable bit for CLK_OUT. When disabling, the clock output will
optionally continue to run for 128 clock cycles after disablement. There is also be one
(1) bit available to adjust the CLK_OUT I/O pad drive strength.
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MKW2xD Data Sheet, Rev. 2, 05/2016
Radio Peripherals
4.2 General-purpose input output (GPIO)
In addition to the MCU supported GPIOs, the radio supports 2 GPIO pins. All I/O
pins will have the same supply voltage and depending on the supply, can vary from
1.8 V up to 3.6 V. When the pin is configured as a general-purpose output or for
peripheral use, there will be specific settings required per use case. Pin configuration
will be executed by software to adjust input/output direction and drive strength,
capability. When the pin is configured as a general-purpose input or for peripheral
use, software (see Table 3) can enable a pull-up or pull-down device. Immediately
after reset, all pins are configured as high-impedance general-purpose inputs with
internal pull-up devices enabled.
Features for these pins include:
• Programmable output drive strength
• Programmable output slew rate
• Hi-Z mode
• Programmable as outputs or inputs (default)
Table 3. Pin configuration summary
Pin function configuration
Details
I/O buffer full drive mode1
I/O buffer partial drive mode1
I/O buffer high
impedance2
Units
Min.
Typ.
Max.
Source or sink
—
±10
—
mA
Source or sink
—
±2
—
mA
Off state
—
—
10
nA
time3
2
4
6
ns
No slew, partial drive
Rise and fall time
2
4
6
ns
Slew, full drive
Rise and fall time
6
12
24
ns
Slew, partial drive
Rise and fall time
6
12
24
ns
No slew, full drive
Propagation
1.
2.
3.
4.
5.
6.
Tolerance
delay4,
no slew
Rise and fall
Full
drive5
—
—
11
ns
Propagation delay, no slew
Partial drive6
—
—
11
ns
Propagation delay, slew
Full drive
—
—
50
ns
Propagation delay, slew
Partial drive
—
—
50
ns
For this drive condition, the output voltage will not deviate more than 0.5 V from the rail reference VOH or VOL.
Leakage current applies for the full range of possible input voltage conditions.
Rise and fall time values in reference to 20% and 80%
Propagation Delay measured from/to 50% voltage point.
Full drive values provided are in reference to a 75 pF load.
Partial drive values provided are in reference to a 15 pF load.
MKW2xD Data Sheet, Rev. 2, 05/2016
17
NXP Semiconductors
Radio Peripherals
4.3 Serial peripheral interface (SPI)
The MKW2xD SiP uses a SPI interface allowing the MCU to communicate with the
radio's register set and packet buffer. The SPI is a slave-only interface; the MCU must
drive R_SSEL_B, R_SCLK and R_MOSI. Write and read access to both direct and
indirect registers is supported, and transfer length can be single-byte or bursts of
unlimited length. Write and read access to the Packet buffer can also be single-byte or a
burst mode of unlimited length.
The SPI interface is asynchronous to the rest of the IC. No relationship between
R_SCLK and MKW2xD's internal oscillator is assumed. And no relationship between
R_SCLK and the CLK_OUT pin is assumed. All synchronization of the SPI interface to
the IC takes place inside the SPI module. SPI synchronization takes place in both
directions; register writes and register reads. The SPI is capable of operation in all
power modes, except Reset. Operation in hibernate mode allows most transceiver
registers and the complete packet buffer to be accessed in the lowest-power operating
state enabling minimal power consumption, especially during the register-initialization
phase of the radio.
The SPI design features a compact, single-byte control word, reducing SPI access
latency to a minimum. Most SPI access types require only a single-byte control word,
with the address embedded in the control word. During control word transfer (the first
byte of any SPI access), the contents of the IRQSTS1 register (MKW2xD radio's
highest-priority status register) are always shifted out so that the MCU gets access to
IRQSTS1, with the minimum possible latency, on every SPI access.
4.3.1 Features
• 4-wire industry standard interface, supported by all MCUs
• SPI R_SCLK maximum frequency 16 MHz (for SPI write accesses)
• SPI R_SCLK maximum frequency 9 MHz (for SPI read accesses)
• Write and read access to all radio registers (direct and indirect)
• Write and read access to packet buffer
• SPI accesses can be single-byte or burst
• Automatic address auto-incrementing for burst accesses
18
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
Radio Peripherals
• The entire packet buffer can be uploaded or downloaded in a single SPI burst
• Entire packet buffer and most registers can be accessed in hibernate mode
• Built-in synchronization inside the SPI module to/from the rest of the radio
4.4 Antenna diversity
To improve the reliability of RF connectivity to long range applications, the antenna
diversity feature is supported without using the MCU through use of four dedicated
control pins (package pins 44, 45, 46, and 47).
Fast antenna diversity (FAD) mode supports this radio feature and, when enabled, will
allow the choice of selection between two antennas during the preamble phase. By
continually monitoring the received signal, the FAD block will select the first antenna
of which the received signal has a correlation factor above a predefined progammable
threshold. The FAD accomplishes the antenna selection by sequentially switching
between the two antennas testing for the presence of suitably strong s0 symbol where
the first antenna to reach this condition is then selected for the reception of the packet.
The antenna's are monitored for a period of 28 μs each. The antenna switching is
continued until 1.5 valid s0 symbols are detected. The demodulator then continues
with normal preamble search before declaring “Preamble Detect”.
4.5 RF Output Power Distribution
The following figure shows the linear region of the output and the typical power
distribution of the radio as a function of PA_PWR [4:0] range. The PA_PWR [4:0] is
the lower 5 bits of the PA_PWR 0x23 direct register and has a usable range of 3 to 31
decimal.
MKW2xD Data Sheet, Rev. 2, 05/2016
19
NXP Semiconductors
MKW2xD operating modes
Figure 2. MKW2xD transmit power vs. PA_PWR step
5 MKW2xD operating modes
For the discussion of this topic, the primary radio and MCU operating modes are
combined so that overall power consumption can then be derived. Depending on the
stop requirements of the user application, a variety of stop modes are available that
provide state retention, partial power down or full power down of certain logic and/or
memory. I/O states are held in all modes of operation. Both the radio and MCU's power
modes are described as follows.
The radio has 6 primary operating modes:
• Reset / power down
• Low power (LP) / hibernate
• Doze (low power with reference oscillator active)
20
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
MKW2xD operating modes
• Idle
• Receive
• Transmit
Table 4 lists and describes the transceivers power modes and consumption.
Table 4. Transceiver Power Modes
Mode
Definition
Reset / All IC functions off, leakage only. RST asserted.
powerdow
n
Low
Crystal reference oscillator off. (SPI is functional.)
power /
hibernate
Doze2
Crystal reference oscillator on but CLK_OUT output available only if selected.
Current
consumption1
< 100 nA
< 1 μA
500 μA3
(no CLK_OUT)
Idle
Crystal reference oscillator on with CLK_OUT output available only if selected.
3
700 μA
(no CLK_OUT)
Receive
Crystal reference oscillator on. Receiver on.
< 19.5 mA 4
15 mA, LPPS
mode
Transmit
1.
2.
3.
4.
5.
Crystal reference oscillator on. Transmitter on.
< 18 mA 5
Conditions: VBAT and VBAT_2 = 2.7 V, nominal process @ 25°C
While in Doze mode, 4 MHz max frequency can be selected for CLK_OUT.
Typical
Signal sensitivity = -102 dBm
RF output = 0 dBm
The MCU has a variety of operating modes. For each run mode there is a
corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop
modes (VLPS, STOP) are similar to ARM sleep deep mode. The very low power run
(VLPR) operating mode can drastically reduce runtime power when the maximum bus
frequency is not required to handle the application needs.
The three primary modes of operation are run, wait and stop. The WFI instruction
invokes both wait and stop modes for the chip. The primary modes are augmented in a
number of ways to provide lower power based on application needs.
MKW2xD Data Sheet, Rev. 2, 05/2016
21
NXP Semiconductors
MKW2xD electrical characteristics
5.1 Transceiver Transmit Current Distribution
The following figure shows the relation between the transmit power generated by the
radio and its current consumption.
Figure 3. MKW2xD transmit power vs transmit current (Radio Only)
6 MKW2xD electrical characteristics
6.1 Radio recommended operating conditions
Table 5. Recommended operating conditions
Characteristic
Symbol
Min
Typ
Max
Unit
VBAT, VDDINT
1.8
2.7
3.6
Vdc
Input Frequency
fin
2.360
—
2.480
GHz
Ambient Temperature Range
TA
-40
25
105
°C
Power Supply Voltage (VBAT = VDDINT)
Table continues on the next page...
22
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
Ratings
Table 5. Recommended operating conditions (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Logic Input Voltage Low
VIL
0
—
30%
VDDINT
V
Logic Input Voltage High
VIH
70%
VDDINT
—
VDDINT
V
SPI Clock Rate
fSPI
—
—
16.0
MHz
RF Input Power
Pmax
—
—
10
dBm
Crystal Reference Oscillator Frequency (±40 ppm over
operating conditions to meet the 802.15.4 Standard.)
fref
32 MHz only
6.2 Ratings
6.2.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
6.2.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
6.2.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
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MKW2xD Data Sheet, Rev. 2, 05/2016
23
NXP Semiconductors
MCU Electrical characteristics
Symbol
ILAT
Description
Min.
Max.
Unit
Notes
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
6.2.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.6
V
IDD
Digital supply current
—
155
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VDD + 0.3
V
VAIO
Analog1,
RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Maximum current single pin limit (applies to all digital pins)
–25
25
mA
ID
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
VDDA
Analog supply voltage
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
7 MCU Electrical characteristics
7.1 Maximum ratings
Table 6. Maximum ratings
Requirement
Note:
Description
Symbol
Rating level
Unit
Power Supply Voltage
VBAT, VBAT2
-0.3 to 3.6
Vdc
Digital Input Voltage
Vin
-0.3 to (VDDINT + 0.3)
Vdc
RF Input Power
Pmax
+10
dBm
Maximum ratings are those values beyond which damage to the device may occur. Functional operation should be
restricted to the limits in the electrical characteristics or recommended operating conditions tables.
ESD1
Human Body
Model
HBM
±2000
Vdc
Machine Model
MM
±200
Vdc
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24
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
Table 6. Maximum ratings (continued)
Requirement
Description
Symbol
Rating level
Unit
Charged Device
Model
CDM
±750
Vdc
Power ElectroStatic
Discharge /
Direct Contact
Power ElectroStatic
Discharge /
Indirect Contact
EMC2
Langer IC / EFT /
P201
Langer IC / EFT /
P201
No damage / latch up to ±4000
No soft failure / reset to ±1000
PESD
No damage / latch up to ±6000
No soft failure / reset to ±1000
No damage / latch up to ±5
EFT (Electro
Magnetic Fast
Transient)
Vdc
No soft failure / reset to ±5
No damage / latch up to ±300
No soft failure / reset to ±150
Vdc
Vdc
Vdc
Junction Temperature
TJ
+125
°C
Storage Temperature Range
Tstg
-65 to +165
°C
1. Electrostatic discharge on all device pads meet this requirement
2. Electromagnetic compatibility for this product is low stress rating level
Note
Maximum ratings are those values beyond which damage to
the device may occur. Functional operation should be
restricted to the limits in the electrical characteristics or
recommended operating conditions tables.
7.2 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
MKW2xD Data Sheet, Rev. 2, 05/2016
25
NXP Semiconductors
MCU Electrical characteristics
Input Signal
High
Low
VIH
80%
50%
20%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 4. Input signal measurement reference
7.3 Nonswitching electrical specifications
7.3.1 Voltage and current operating requirements
Table 7. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.8
3.6
V
VDDA
Analog supply voltage
1.8
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.8
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
VBAT
VIH
VIL
RTC battery supply voltage
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICIO
I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
IICcont
Notes
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
1
mA
-3
—
—
+3
-25
—
—
+25
mA
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26
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
Table 7. Voltage and current operating requirements (continued)
Symbol
VRAM
VRFVBAT
Description
Min.
Max.
Unit
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VBAT voltage required to retain the VBAT register file
Notes
1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VINVAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative
injection currents.
7.3.2 LVD and POR operating requirements
Table 8. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
MKW2xD Data Sheet, Rev. 2, 05/2016
Notes
27
NXP Semiconductors
MCU Electrical characteristics
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 9. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
7.3.3 Voltage and current operating behaviors
Table 10. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
0.5
V
—
100
mA
• @ full temperature range
—
1.0
μA
• @ 25 °C
—
0.1
μA
—
1
μA
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
IOZ
Hi-Z (off-state) leakage current (per pin)
1
IOZ
Total Hi-Z (off-state) leakage current (all input pins)
—
4
μA
RPU
Internal pullup resistors
22
50
kΩ
2
RPD
Internal pulldown resistors
22
50
kΩ
3
1. Tested by ganged leakage method
2. Measured at Vinput = VSS
3. Measured at Vinput = VDD
28
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
7.3.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
CPU and system clocks = 50 MHz
Bus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
Table 11. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
After a POR event, amount of time from the point
VDD reaches 1.71 V to execution of the first
instruction across the operating temperature range
of the chip.
• 1.71 V/(VDD slew rate) ≤ 300 μs
Max.
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
Notes
μs
1
—
300
—
1.7 V / (VDD
slew rate)
—
150
μs
—
79
μs
—
79
μs
—
6
μs
—
5.2
μs
—
5.2
μs
• 1.71 V/(VDD slew rate) > 300 μs
• VLLS1 → RUN
Unit
1. Normal boot (FTFL_OPT[LPBOOT]=1)
7.3.5 Power consumption operating behaviors
Table 12. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8 V
• @ 3.0 V
2
—
12.98
14
mA
—
12.93
13.8
mA
Table continues on the next page...
MKW2xD Data Sheet, Rev. 2, 05/2016
29
NXP Semiconductors
MCU Electrical characteristics
Table 12. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8 V
Typ.
Max.
Unit
Notes
3, 4
—
17.04
19.3
mA
—
17.01
18.9
mA
—
19.8
21.3
mA
• @ 3.0 V
• @ 25°C
• @ 125°C
IDD_WAIT
Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
—
7.95
9.5
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
5.88
7.4
mA
5
IDD_STOP
Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
320
436
360
489
410
620
610
1100
μA
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
—
754
—
μA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
—
1.1
—
mA
7
IDD_VLPW Very-low-power wait mode current at 3.0 V
—
437
—
μA
8
IDD_VLPS
—
7.33
24.2
14
32
28
48
110
280
3.14
4.8
6.48
28.3
13.85
44.6
55.53
71.3
2.19
3.4
4.35
4.35
8.92
24.6
35.33
45.3
1.77
3.1
2.81
13.8
5.20
22.3
19.88
34.2
1.03
1.8
IDD_LLS
Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
•
•
•
•
—
—
@ –40 to 25°C
@ 50°C
@ 70°C
@ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
—
—
μA
μA
μA
μA
μA
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30
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
Table 12. Power consumption operating behaviors (continued)
Symbol
Description
Min.
• @ 50°C
• @ 70°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
—
IDD_VBAT
—
Average current when CPU is not accessing
RTC registers at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
Typ.
Max.
1.92
7.5
4.03
15.9
17.43
28.7
0.543
1.1
1.36
7.58
3.39
14.3
16.52
24.1
0.359
0.95
1.03
6.8
2.87
15.4
15.20
25.3
0.91
1.1
1.1
1.35
1.5
1.85
4.3
5.7
Unit
Notes
μA
μA
μA
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks disabled.
3. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, and peripherals are in active operation.
4. Max values are measured with CPU executing DSP instructions
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
7. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
9. Includes 32 kHz oscillator current and RTC operation.
7.3.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
MCG in FBE mode
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFL
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MCU Electrical characteristics
Figure 5. Run mode supply current vs. core frequency
32
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MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
Figure 6. VLPR mode supply current vs. core frequency
7.3.6 EMC radiated emissions operating behaviors
Table 13. EMC radiated emissions operating behaviors 1
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
19
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
21
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
19
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
11
dBμV
IEC level
0.15–1000
L
—
VRE_IEC
3, 4
1. This data was collected on a MK20DN128VLH5 64pin LQFP device.
2. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
MKW2xD Data Sheet, Rev. 2, 05/2016
33
NXP Semiconductors
MCU Electrical characteristics
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
3. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 48 MHz, fBUS = 48MHz
4. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
7.3.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to www.nxp.com.
• Perform a keyword search for “EMC design.”
7.3.8 Capacitance attributes
Table 14. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
7.4 Switching specifications
7.4.1 Device clock specifications
Table 15. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
50
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
Notes
Normal run mode
fSYS
fBUS
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
Table continues on the next page...
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MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
Table 15. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
fLPTMR_pin
fLPTMR_ERCLK LPTMR external reference clock
—
16
MHz
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
7.4.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 16. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous
path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous
path
50
—
ns
3
External reset pulse width (digital glitch filter
disabled)
100
—
ns
3
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
13
ns
• 2.7 ≤ VDD ≤ 3.6V
—
7
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Port rise and fall time (low drive strength)
5
• Slew disabled
MKW2xD Data Sheet, Rev. 2, 05/2016
—
12
ns
—
6
ns
35
NXP Semiconductors
MCU Electrical characteristics
Table 16. General switching specifications
Symbol
Description
Min.
Max.
Unit
—
36
ns
—
24
ns
Notes
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can
be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
7.5 Thermal specifications
7.5.1 Thermal operating requirements
Table 17. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature1
–40
105
°C
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
7.5.2 Thermal attributes
Board type
Symbol
Description
80 LQFP
Unit
Notes
Single-layer (1s)
RθJA
Thermal
50
resistance,
junction to ambient
(natural
convection)
°C/W
1, 2
Four-layer (2s2p)
RθJA
Thermal
35
resistance,
junction to ambient
°C/W
1, 3
Table continues on the next page...
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MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
Board type
Symbol
Description
80 LQFP
Unit
Notes
(natural
convection)
Single-layer (1s)
RθJMA
Thermal
39
resistance,
junction to ambient
(200 ft./min. air
speed)
°C/W
1,3
Four-layer (2s2p)
RθJMA
Thermal
29
resistance,
junction to ambient
(200 ft./min. air
speed)
°C/W
1,3
—
RθJB
Thermal
resistance,
junction to board
19
°C/W
4
—
RθJC
Thermal
resistance,
junction to case
8
°C/W
5
—
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
2
°C/W
6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
7.6 Peripheral operating requirements and behaviors
7.6.1 Core modules
MKW2xD Data Sheet, Rev. 2, 05/2016
37
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MCU Electrical characteristics
7.6.1.1
Symbol
J1
JTAG electricals
Table 18. JTAG limited voltage range electricals
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
17
ns
100
—
ns
8
—
ns
Table 19. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.8
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
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MCU Electrical characteristics
Table 19. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
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MCU Electrical characteristics
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
7.6.2 System modules
There are no specifications necessary for the device's system modules.
7.6.3 Clock modules
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MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
7.6.3.1
Symbol
MCG specifications
Table 20. MCG specifications
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
1, 2
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5,6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
Table continues on the next page...
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MCU Electrical characteristics
Table 20. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
180
—
—
150
—
—
—
1
ms
48.0
—
100
MHz
—
1200
—
µA
—
700
—
µA
2.0
—
4.0
MHz
Notes
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
• fvco = 48 MHz
—
120
—
ps
• fvco = 100 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
9
• fvco = 48 MHz
—
1350
—
ps
• fvco = 100 MHz
—
600
—
ps
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
Lock detector detection time
8
9
Dlock
tpll_lock
8
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V 3.6 V
3
3.3
3.6
V
2.1
2.8
3.6
V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
• Run mode
• Standby mode
VReg33out
Notes
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
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7.6.8.4
DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 35. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS4
DS8
First data
DSPI_SOUT
DS1
DS2
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 17. DSPI classic SPI timing — master mode
Table 36. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
Table continues on the next page...
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MCU Electrical characteristics
Table 36. Slave mode DSPI timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 18. DSPI classic SPI timing — slave mode
7.6.8.5
DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 37. Master mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
1.8
3.6
V
1
Frequency of operation
—
12.5
MHz
4 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
Table continues on the next page...
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MCU Electrical characteristics
Table 37. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
20.5
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS1
DS2
DS4
DS8
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 19. DSPI classic SPI timing — master mode
Table 38. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
1.8
3.6
V
Frequency of operation
—
6.25
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
19
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
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MCU Electrical characteristics
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 20. DSPI classic SPI timing — slave mode
7.6.8.6
I2C
See General switching specifications.
7.6.8.7
UART
See General switching specifications.
7.6.8.8
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Due to a limited set of pin availability in the SiP, the I2S/SAI block is usable only for
receive mode and must be configured as a slave.
Table 39. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.8
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
Table continues on the next page...
62
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
Table 39. I2S/SAI master mode timing (continued)
Num.
Characteristic
Min.
Max.
Unit
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 21. I2S/SAI timing — master modes
Table 40. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.8
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
29
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
21
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
MKW2xD Data Sheet, Rev. 2, 05/2016
valid1
63
NXP Semiconductors
MCU Electrical characteristics
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 22. I2S/SAI timing — slave modes
7.6.8.9
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Due to a limited set of pin availability in the SiP, the I2S/SAI block is usable only for
receive mode and must be configured as a slave.
Table 41. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.8
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
75
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
64
NXP Semiconductors
MKW2xD Data Sheet, Rev. 2, 05/2016
MCU Electrical characteristics
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 23. I2S/SAI timing — master modes
Table 42. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.8
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
87
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1 —
72
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
MKW2xD Data Sheet, Rev. 2, 05/2016
65
NXP Semiconductors
Transceiver Electrical Characteristics
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 24. I2S/SAI timing — slave modes
8 Transceiver Electrical Characteristics
8.1 DC electrical characteristics
Table 43. DC electrical characteristics (VBAT, VBAT2 = 2.7 V, TA=25 °C, unless otherwise
noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Power Supply Current (VBAT + VBAT2)
Reset / power down1
Ileakage
—
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