MM908E621ACDWBR2

Freescale Semiconductor Technical Data Document Number: MM908E621 Rev. 6.0, 4/2012 Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror 908E621 QUAD HALF-BRIDGE AND TRIPLE HIGH SIDE SWITCH WITH EMBEDDED MCU AND LIN The 908E621 is an integrated single package solution that includes a high performance HC08 microcontroller with a SMARTMOS analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), a 10 bit analog-to-digital converter (ADC), internal serial peripheral interface (SPI), and an internal clock generator module (ICG). The analog control die provides four half-bridge and three high side outputs with diagnostic functions, a Hall effect sensor input, analog inputs, voltage regulator, window watchdog, and local interconnect network (LIN) physical layer. The single package solution, together with LIN, provides optimal application performance adjustments and space saving PCB design. It is well-suited for the control of automotive high end mirrors. EK (Pb-Free) 98ASA10712D 54-PIN SOICW-EP Features • • • • • • • • • • • High performance M68HC908EY16 core 16 KB of on-chip flash memory, 512 B of RAM Two 16-bit, two-channel timers LIN physical layer interface Autonomous MCU watchdog / MCU supervision One analog input with switchable current source Four low RDS(ON) half-bridge outputs Three low RDS(ON) high side outputs Wake-up and 2 or 3-pin Hall effect sensor input 12 microcontroller I/Os Pb-free packaging designated by suffix codes EK ORDERING INFORMATION VSP1:8] LIN VDDA/VREFH EVDD 4.7 μF VDD 100 nF VSSA/VREFL EVSS VSS RST A RST IRQ A IRQ PTA/KBD0 PTA1/KBD1 μC PortA PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTB3/AD3 μC PortB PTB4/AD4 PTB5/AD5 PTC2/MCLK μC PortC PTC3/OSC2 PTC4/OSC1 Internally Connected PTD0/TACH0 μC PortD PTD1/TACH1 μC PortE Internally Connected PTE1/RXD Device (Add an R2 suffix for Tape and reel orders) Temperature Range (TA) Package MM908E621ACPEK -40 to 85°C 54 SOICW-EP >22 μF Wake-up Input L0 HB1 HB2 908E621 HB3 HB4 HS1 M M 4 x Half-brideOutputs M High Side Output 1 HS2 High Side Output 2 HS3 High Side Output 3 HVDD A0 A0CST H0 TESTMODE Switched 5.0 V Output Analog Input with Curet Source Analog Input Current Source Trim Two 3-pin Hall Sensor Input Pull to GND for User Mode EP GND[1:4] Figure 1. 908E621 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007-2012. All rights reserved. 100 nF 2 PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB0/AD0 PTB0/AD0 Security Module Power-ON Reset Module DDRA PORT A PTB0/AD0 ADOUT SPSCK MOSI PTC1/MOSI PTA5/SPSCK MISO SS PWM PTC0/MISO PTA6/SS PTD0/TACH0 TXD PTE0/TXD IRQ_A Analog Multiplexer SPI & CONTROL Autonomous Watchdog Reset Control LIN Physical Layer Figure 2. 908E621 Simplified Internal Block Diagram PTE0/TXD PTE1/RXD PTD0/TACH0 PTD1/TACH1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO BEMF Module Prescaler Module Arbiter Module Periodic Wake-up Timebase Module Configuration Register Module Serial Peripheral Interface Module Computer Operating Properly Module Enhanced Serial Communication Interface Module 2-channel Timer Interface Module B PORT C DDRC FLSVPP PTD1/TACH1 Single External IRQ Module 24 Integral System Integration Module VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS IRQ RST OSC2 Internal Clock OSC1 Generator Module RST PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 PTA4/KBD4 VDDA/VREFH User Flash Vector Space, 36 Bytes IRQ PTA3/KBD3 EVDD 2-channel Timer Interface Module A PTD0/TACH0 RXD PTE1/RXD PTE1/RXD RST_A PTA2/KBD2 EVSS 5-Bit Keyboard Interrupt Module LIN PTA1/KBD1 PTA0/KBD0 VSSA/VREFL VSS A0 A0CST H0 HALLPORT HB4 HB3 HB2 HB1 Analog Port with Current Source Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic HS3 HS2 High Side Driver & Diagnostic High Side Driver & Diagnostic HS1[a:b] L0 HVDD VDD High Side Driver & Diagnostic Wakeup Port Switched VDD Driver & Diagnostic Voltage Regulator VSUP[1:8] Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes Flash programming (Burn-in), ROM 1024 Bytes Single Breakpoint Break Module GND[1:4] M68HC08 CPU CPU ALU Registers INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM TESTMODE PORT D PORT E DDRD DDRE Internal Bus DDRB PORT B 908E621 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS Transparent Top View of Package PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 1 54 2 53 3 52 4 51 5 50 6 49 IRQ RST 7 48 8 47 (PTD0/TACH0/BEMF -> PWM) PTD1/TACH1 9 46 10 45 RST_A IRQ_A 11 44 12 43 LIN A0CST A0 GND1 HB4 VSUP1 GND2 HB3 VSUP2 NC NC TESTMODE GND3 HB2 VSUP3 13 14 15 42 Exposed Pad 41 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VDDA/VREFH EVDD EVSS VSSA/VREFL (PTE1/RXD PWM) PWM signal This pin is an asynchronous external interrupt input pin. This pin is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin is the PWM signal test pin. It internally connects the MCU PTD0/TACH0 pin with the Analog die PWM input. Note: Do not connect in the application. MCU 10 PTD1/TACH1 Port D I/Os This pin is a special function, bidirectional I/O port pin that is shared with other functional modules in the MCU. MCU / Analog 44 (PTE1/RXD 20 V VDDRUN2 4.75 5.0 5.25 IOUTRUN – 120 150 mA VLR – – 100 mV STOP Mode Output Voltage(13) VDDSTOP 4.75 5.0 5.25 V STOP Mode Total Output Current IOUTSTOP 150 500 1100 μA SYSTEM RESETS AND INTERRUPTS Low Voltage Reset (LVR) Threshold Hysteresis Low Voltage Interrupt (LVI) V V High Voltage Interrupt (HVI) °C High Temperature Interrupt (HTI)(11) Threshold TJ Hysteresis °C High Temperature Reset (HTR)(11) Threshold TJ Hysteresis VOLTAGE REGULATOR(12) V Normal Mode Output Voltage(13) Normal Mode Total Output Current Load Regulation - IOUT = 60 mA, VSUP = 9.0 V, TJ = 125 °C Notes 11. This parameter is guaranteed by process monitoring but is not production tested. 12. Specification with external low ESR ceramic capacitor 1.0 μF< C < 4.7 μF and 200 mΩ ≤ ESR ≤ 10 Ω. Its not recommended to use capacitor values above 4.7 μF 13. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification. 908E621 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Recessive State, TXD HIGH, IOUT = 1.0 μA V LIN_REC VSUP -1 — — Dominant State, TXD LOW, 500 Ω External Pull-up Resistor V LIN_DOM — — 1.4 Normal Mode Pull-up Resistor to VSUP R PU 20 30 47 kΩ Stop, Sleep Mode Pull-up Current Source IPU — 20 — μA Output Current Shutdown Threshold IBLIM 100 230 280 mA Output Current Shutdown Timing IBLS 5.0 – 40 µs µA LIN PHYSICAL LAYER LIN Transceiver Output Voltage V Leakage Current to GND IBUS – 1.0 10 IBUS-PAS-REC 0.0 3.0 20 µA IBUS-NOGND -1.0 – 1.0 mA Receiver Threshold Dominant VBUS_DOM – – 0.4 Receiver Threshold Recessive VBUS_REC 0.6 – – Receiver Threshold Center VBUS_CNT 0.475 0.5 0.525 Receiver Threshold Hysteresis VBUS_HYS – – 0.175 RDS(ON)-HS1 – 185 225 IHSOC1 6.0 – 9.0 A tOCB – 4-8 – µs CRRATIOHS1 0.84 1.2 1.56 V/A fPWMHS – – 25 kHz VHSF – 0.9 – V ILeakHS – P0 = 0. The parity bit is only evaluated during a write operations and ignored for read operations. Bit X Not used Master Data Byte This byte includes data to be written, or no valid data, during a read operation. Master Address Byte Slave Status Byte A4 - A0 This byte always includes the contents of the system status register ($0C), independent if it is a write or read operation, or which register was selected. Includes the address of the desired register. R/W Includes the information, if it is a read or a write operation. • If R/W = 1 (read operation), the second byte of master contains no valid information, and the slave just transmits back register data. • If R/W = 0 (write operation), the master sends data to be written in the second byte, the slave sends concurrently contents of selected register prior to write operation, Slave Data Byte This byte includes the contents of selected register, during a write operation, it includes the register content prior to the write operation. SPI REGISTER OVERVIEW Table 12 summarizes the SPI Register addresses and the bit names of each register. 908E621 44 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 12. SPI Register Overview Addr Register Name R/W System Control (SYSCTL) R $00 $01 Half-bridge Output (HBOUT) $02 High Side Output (HSOUT) $03 Half-bridge Status and Control (HBSCTL) $04 High Side Status and Control (HSSCTL) $05 Reserved $06 Reserved $07 H0/L0 Status and Control (HLSCTL) $08 A0 and Multiplexer Control (A0MUCTL) $09 Interrupt Mask (IMR) $0A Interrupt Flag (IFR) $0B Watchdog Control (WDCTL) $0C System Status (SYSSTAT) $0D Reset Status (RSR) $0E System Test (SYSTEST) $0F System Trim 1 (SYSTRIM1) $10 System Trim 2 (SYSTRIM2) $11 System Trim 3 (SYSTRIM3) Bit 7 PSON W R HB4_H W R W HVDDON R CRM W R W HVDDOCF 6 5 4 3 2 1 0 0 0 STOP SLEEP HTIS1 HTIS0 VIS SRS1 SRS0 HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L HS3PWM HS2PWM HS1PWM HS3ON HS2ON HS1ON 0 0 0 HB4OCF HB3OCF HB2OCF HB1OCF 0 0 0 HS3OCF HS2OCF HS1OCF H0EN H0PD H0MS 0 R 0 reserved W R reserved W R L0F 0 0 H0F H0OCF W R W R W CSON CSSEL1 CSSEL0 CSA SS3 SS2 SS1 SS0 L0IE H0IE LINIE HTRD HTIE LVIE HVIE PSFIE L0IF H0IF LINIF 0 HTIF LVIF HVIF WDRE WDP1 WDP0 0 0 0 0 LINCL HTIF VF H0F HVDDF HSF HBF 0 POR PINR WDR HTR LVR LINWF L0WF R W R W R PSFIF 0 WDRST W R W R reserved W R W HVDDT1 HVDDT0 reserved reserved itrim3 itrim2 itrim1 itrim0 0 0 0 0 0 0 0 0 CRHB5 CRHB4 CRHB3 CRHB2 CRHB1 CRHB0 0 0 0 0 0 0 CRHS5 CRHS4 CRHS3 CRHS2 CRHS1 CRHS0 R W CRHBHC1 CRHBHC0 R W 0 0 0 CRHBHC3 CRHBHC2 908E621 Analog Integrated Circuit Device Data Freescale Semiconductor 45 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E621, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” ($FF) state: Watchdog Period Range Value (AWD Trim) Trim Values The window watchdog supervises device recovery (e.g. from code runaways). The application software has to clear the watchdog within the open window. Due to the high variation of the watchdog period, and therefore the reduced width of the watchdog window, a value is stored at address $FDCF. This value classifies the watchdog period into 3 ranges (Range 0, 1, 2). This allows the application software to select one of three time intervals to clear the watchdog, based on the stored value. The classification is done, so that the application software can have up to ±19% variations of the optimal clear interval (e.g. caused by ICG variation). The usage of the trim values located in the flash memory are explained through the following: Effective Open Window • $FD80:$FDDF Trim and Calibration Values • $FFFE:$FFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate these dependencies, an ICG trim value is located at address $FDC2. After trimming, the ICG has a typ. range of ±2% (±3% max.), at nominal conditions (filtered (100nF), stabilized (4.7 μF) VDD = 5.0 V, TAMBIENT~25 °C), and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG, this value has to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important: The value must be copied after every reset. Having a variation in the watchdog period in conjunction with a 50% open window, results in an effective open window, which can be calculated by: latest window open time: t_open = t_wd max / 2 earliest window closed time: t_closed = t_wd min Optimal Clear Interval The optimal clear interval, meaning the clear interval with the biggest possible variation to latest window open time, and to the earliest window closed time, can be calculated with the following formula: t_opt = t_open + (t_open+t_closed) / 2 See Table 13 to select the optimal clear interval for the watchdog based on the Window No. and chosen period. Table 13. Window Clear Interval Window Range Period Select bits $FDCF 0 1 2 Watchdog Period t_wd WDP1:0 min. max. 00 68 92 01 34 46 10 17 23 11 8.5 00 Unit Effective Open Window t_open t_closed 46 68 23 34 11.5 17 11.5 5.75 8.5 7.125 92 124 62 92 77 01 46 62 31 46 10 23 31 15.5 23 11 11.5 15.5 7.75 11.5 9.625 00 52 68 34 52 43 01 26 34 17 26 10 13 17 8.5 13 11 6.5 8.5 4.25 6.5 ms ms ms Unit Optimal Clear Interval t_opt Unit max. variation ms ±19.3% ms ±19.5% ms ±20.9% 57 ms ms ms 28.5 14.25 38.5 19.25 21.5 10.75 5.375 908E621 46 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Analog Die System Trim Values ITRIM3:0 - IRef Trim Bits For improved application performance, and to ensure the outlined datasheet values, the analog die needs to be trimmed. For this purpose, 3 trim values are stored in the Flash memory at addresses $FDC4 - $FDC6. These values have to be copied into the analog die SPI registers: • copy $FDC4 into SYSTRIM1 register $0F • copy $FDC5 into SYSTRIM2 register $10 • copy $FDC6 into SYSTRIM3 register $11 Note: These values must be copied to the respective SPI register after a reset, to ensure proper trimming of the device. These write only bits are for trimming the internal current references IRef (also A0, A0CST). The provided trim values have to be copied into these bits after every reset. Reset clears the ITRIM3:0 bits. System Test Register (SYSTEST) Register Name and Address: SYSTEST - $0E Bit7 6 5 4 3 2 1 Bit0 reserved reserved reserved reserved reserved reserved reserved reserved 0 0 0 0 0 0 0 0 Read Write Reset Note: do not write to the reserved bits Table 15. IRef Trim Bits itrim3 itrim2 itrim2 itrim0 Adjustment 0 0 0 0 0 0 0 0 1 2% 0 0 1 0 4% 0 0 1 1 8% 0 1 0 0 12% 0 1 0 1 -2% 0 1 1 0 -4% 0 1 1 1 -8% 1 0 0 0 -12% System Trim Register 2 (SYSTRIM2) The System Test Register is reserved for production testing and is not allowed to be written to. Register Name and Address: IFBHBTRIM - $10 Bit7 System Trim Register 1 (SYSTRIM1) Register Name and Address: IBIAS - $0F Bit7 6 HVDDT1 HVDDT0 0 0 Read Write Reset 5 4 3 2 1 Bit0 0 0 reserved reserved ITRIM3 ITRIM2 ITRIM1 ITRIM0 0 0 0 0 0 0 6 5 4 3 2 1 Bit0 0 0 Read 0 0 0 0 0 0 Write CRHBHC1 CRHBHC0 CRHB5 CRHB4 CRHB3 CRHB2 Reset 0 0 0 0 0 0 CRHB1 CRHB0 0 0 CRHBHC1:0 - Current Recopy HB1:2 Trim Bits Note: do not change (set) the reserved bits These write only bits are for trimming the current recopy of the half-bridge HB1 and HB2 (CSA=0). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHBHC1:0 bits. Table 16. Current Recopy Trim for HB1:2 (CSA=0) HVDDT1:0 - HVDD Over-current Shutdown Delay Bits These read/write bits allow changes to the filter time (for capacitive load) for HVDD over-current detection. Reset clears the HVDDT1:0 bits and sets the delay to the maximum value. Table 14. HVDD Over-current Shutdown Selection Bits HVDDT1 HVDDT0 Typical Delay 0 0 950 μs 0 1 536 μs 1 0 234 μs 1 1 78 μs CRHBHC1 CRHBHC0 Adjustment 0 0 0 0 1 -10% 1 0 5% 1 1 10% CRHB5:3 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB3 and HB4 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB5:3 bits. 908E621 Analog Integrated Circuit Device Data Freescale Semiconductor 47 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Current Recopy Trim for HB3:4 (CSA=0) Table 17. Current Recopy Trim for HB3:4 (CSA=1) CRHB5 CRHB4 CRHB3 Adjustment 0 0 0 0 0 0 1 -5% 0 1 0 -10% 0 1 1 -15% 1 0 0 reserved 1 0 1 5% 1 1 0 10% 1 1 1 15% CRHBHC3 CRHBHC2 Adjustment 0 0 0 0 1 -10% 1 0 5% 1 1 10% CRHS5:3 - Current Recopy HS2:3 Trim Bits These write only bits are for trimming the current recopy of the high side HS2 and HS3. The provided trim values have to be copied into these bits after every reset. Reset clears the CRHS5:3 bits. CRHB2:0 - Current Recopy HB1:2 Trim Bits Table 19. Current Recopy Trim for HS2:3 These write only bits are for trimming the current recopy of the half-bridge HB1 and HB2 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB2:0 bits. Table 18. Current Recopy Trim for HB1:2 (CSA=1) CRHB2 CRHB1 CRHB0 Adjustment 0 0 0 0 0 0 1 -5% 0 1 0 -10% 0 1 1 -15% 1 0 0 reserved 1 0 1 5% 1 1 0 10% 1 1 1 15% CRHS5 CRHS4 CRHS3 Adjustment 0 0 0 0 0 0 1 -5% 0 1 0 -10% 0 1 1 -15% 1 0 0 reserved 1 0 1 5% 1 1 0 10% 1 1 1 15% CRHS2:0 - Current Recopy HS1 Trim Bits These write only bits are for trimming the current recopy of the high side HS1. The provided Trim values have to be copied into these bits after every reset. Reset clears the CRHS2:0 bits. Current Recopy Trim for HS1 System Trim Register 3 (SYSTRIM3) Register Name and Address: IFBHSTRIM - $11 Bit7 6 5 4 3 2 1 Bit0 Read 0 0 0 0 0 0 0 0 Write CRHBH C3 CRHBH C2 CRHS5 CRHS4 CRHS3 CRHS2 CRHS1 CRHS0 Reset 0 0 0 0 0 0 0 0 CRHBHC3:2 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB3 and HB4 (CSA=0). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHBHC3:2 bits. CRHS2 CRHS1 CRHS0 Adjustment 0 0 0 0 0 0 1 -5% 0 1 0 -10% 0 1 1 -15% 1 0 0 reserved 1 0 1 5% 1 1 0 10% 1 1 1 15% 908E621 48 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E621 has the MC68HC908EY16 MCU embedded, typically all the development tools available for the MCU also apply for this device. However, due to the additional analog die circuitry and the nominal +12 V supply voltage, some additional items have to be considered: • nominal 12 V rather than the 5.0 or 3.0 V supply • high voltage VTST might be applied not only to IRQ pin, but IRQ_A pin • MCU monitoring (Normal request timeout) has to be disabled For a detailed information on the MCU related development support, see the MC68HC908EY16 datasheet section development support. The programming is principally possible at two stages in the manufacturing process, first on chip level, before the IC is soldered onto a pcb board, and second after the IC is soldered onto the pcb board. Chip level programming At the Chip level, the easiest way is to only power the MCU with +5.0 V (see Figure 30), and not to provide the analog chip with VSUP. In this setup, all the analog pins should be left open (e.g. VSUP[1:8]), and interconnections between the MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 datasheet, section development support. VSUP[1:8] VDD GND[1:4] VSS +5V VDDA/VREFH RST EVDD RST_A +5V 1 1µF + + 3 4 1µF GND C1C2+ V+ + 5 RS232 DB-9 VCC C1+ 100nF VTST 16 C2- MAX232 V- IRQ_A 1µF 15 7 T2OUT 3 8 R2IN EVSS +5V 9.8304MHz CLOCK +5V + TESTMODE CLK PTB4/AD4 T2IN 10 6 10k 5 4 3 2 10k PTC4/OSC1 1µF 74HC125 5 MM908E621 1µF 6 R2OUT 9 4.7µF VSSA/VREFL + 2 74HC125 2 IRQ 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 1 Figure 30. Normal Monitor Mode Circuit (MCU only) Of course it is also possible to supply the whole system PCB level programming with VSUP instead (12 V) as described in Figure 31, page 50. If the IC is soldered onto the pcb board, it is typically not possible to separately power the MCU with +5.0 V. The whole system has to be powered up providing VSUP (see Figure 31). 908E621 Analog Integrated Circuit Device Data Freescale Semiconductor 49 TYPICAL APPLICATIONS . VDD VSUP 47µF + 100nF VSUP[1:8] VDD GND[1:4] VSS VDDA/VREFH RST EVDD RST_A 100nF VDD 1 1µF 16 + + 3 4 1µF VCC C1+ VTST C1- GND C2+ V+ + 5 RS232 DB-9 C2- MAX232 V- 7 T2OUT 3 8 R2IN EVSS VDD 1µF + 2 10k 9.8304MHz CLOCK 6 VDD TESTMODE CLK 10k PTC4/OSC1 1µF + PTB4/AD4 T2IN 10 6 74HC125 R2OUT 9 MM908E621 IRQ_A 15 4.7µF VSSA/VREFL 1µF 10k 74HC125 2 IRQ 10k 5 DATA PTA1/KBD1 PTA0/KBD0 10k 4 PTB3/AD3 3 2 1 5 Figure 31. Normal Monitor Mode Circuit Table 20 summarizes the possible configurations and the necessary setups. Table 20. Monitor Mode Signal Requirements and Options Mode IRQ RST TESTMODE Normal Monitor Forced Monitor VTST VDD 1 X 1 $FFFF (blank) VDD VDD Reset Vector Serial Communication Mode Selection PTA0 PTA1 PTB3 PTB4 1 0 0 1 1 0 X VDD VDD 0 not $FFFF (not blank) X X X COP OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 ON disabled disabled — Nominal 1.6 MHz Nominal 6300 ON enabled enabled — Nominal 1.6 MHz Nominal 6300 X GND User Communication Speed Normal Request Baud Bus Time-out External Clock Frequency Rate ICG X Notes 36. PTA0 must have a pullup resistor to VDD in monitor mode 37. 38. 39. 40. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don’t care VTST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V EMC/EMI RECOMMENDATIONS VSUP Pins (VSUP[1:8]) This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be found on the Freescale web site www.freescale.com. It is recommended to place a high quality ceramic decoupling capacitor close to the VSUP pins to improve EMC/EMI behavior. 908E621 50 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS LIN Pin For DPI (Direct Power Injection) and ESD (Electrostatic Discharge), it is recommended to place a high quality ceramic decoupling capacitor near the LIN pin. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. Voltage Regulator Output Pins (VDD and VSS) Use a high quality ceramic decoupling capacitor to stabilize the regulated voltage. MCU Digital Supply Pins (EVDD and EVSS) Fast signal transitions on MCU pins place high, short duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. MCU Analog Supply Pins (VREFH/VDDA and VREFL/ VSSA) To avoid noise on the analog supply pins, it is important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces, and connected to the voltage regulator output. Figure 32 and Figure 33 show the recommendations on schematics and layout level, and Table 21 indicates recommended external components and layout considerations. D1 VSUP[1:8] VSUP C1 + VDD C2 VSS VDDA/VREFH L1 LIN LIN EVDD V1 C5 C3 MM908E621 C4 EVSS GND[1:4] VSSA/VREFL Figure 32. EMC/EMI recommendations 908E621 Analog Integrated Circuit Device Data Freescale Semiconductor 51 TYPICAL APPLICATIONS 1 54 2 53 3 52 4 51 5 50 49 48 8 EVDD 47 9 EVSS 46 10 VSSA/VREFL 45 11 44 12 43 VDD 42 908E621 15 16 39 17 38 18 VSUP1 19 GND2 VSUP8 37 36 VSUP7 20 21 41 40 GND1 VSUP2 35 34 22 VSUP6 32 24 VSUP5 31 GND3 GND4 30 VSUP3 VSUP4 25 26 29 D1 28 VBAT V1 27 GND 33 23 C1 14 LIN VSS C2 C5 13 C4 7 VDDA/VREFH C3 6 LIN L1 Figure 33. PCB Layout Recommendations . Table 21. Component Value Recommendation Component Recommended Value(41) D1 Comments / Signal routing reverse battery protection C1 Bulk Capacitor C2 100nF, SMD Ceramic, Low ESR Close to VSUP pins with good ground return C3 100nF, SMD Ceramic, Low ESR Close (