MM908E624ACPEW

Freescale Semiconductor Technical Data Document Number: MM908E624 Rev. 11.0, 4/2012 Integrated Triple High Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers 908E624 HIGH SIDE SWITCH The 908E624 is an integrated single-package solution that includes a high performance HC08 microcontroller with a SMARTMOS analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analogto-digital converter (ADC), internal serial peripheral interface (SPI), and an internal clock generator module. The analog control die provides three high side outputs with diagnostic functions, voltage regulator, watchdog, current sense operational amplifier, and local interconnect network (LIN) physical layer. The single package solution, together with LIN, provides optimal application performance adjustments and space saving PCB design. It is well-suited for the control of automotive high current motors applications using relays (e.g., window lifts, fans, and sun roofs). Features • High performance M68HC908EY16 core • 16 KB of on-chip flash memory, 512 B of RAM • Internal clock generator module • Two 16-bit, two-channel timers • 10-bit ADC • LIN physical layer interface • Low dropout voltage regulator • Three high side outputs • Two wake-up inputs • 16 microcontroller I / Os EW (Pb-FREE) SUFFIX 98ASA99294D 54-pin SOICW ORDERING INFORMATION Device (Add an R2 suffix for Tape and reel orders) Temperature Range (TA) MM908E624ACPEW - 40°C to 85°C MM908E624AYPEW - 40°C to 125°C 908E624 VBAT LIN Interface 5.0 V Microcontroller Ports LIN VREFH VDDA EVDD VCC VDD VREFL VSSA EVSS AGND GND VSP1 VSP RXD PTE1/RXD RST RST_A IRQ IRQ_A PTD0/TACH0 PW/MIN PTA0-4 PTB1;3-7 PTC2-4 PTD1/TACH1 HS3 L1 L2 HS1 M HS2 +E WDCONF To Microcontroller A/D Channel OUT -E Figure 1. 908E624 Simplified Application Diagram *This document contains certain information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2012. All rights reserved. Package 54 SOICW Monitor ROM, 310 Bytes VSS VDD VSSA VREFL VDDA VREFH IRQ RST OSC1 OSC2 PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6/TBCH0 PTB7/AD7/TBCH1 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTA5/SPSCK PTA6/SS Security Module Power-On Reset Module POWER 10 Bit Analog-to-Digital Converter Module Single External IRQ Module 24 Internal System Integration Module Internal Clock Generator Module User Flash Vector Space, 36 Bytes FLASH programming (burn in) ROM, 1024 Bytes PTE1/RXD MCU Die PTA5/SPSCK PTC1/MOSI PTC0/MISO PTA6/SS PTE0/TXD SPSCK MOSI MISO SS TXD Analog Die RXD SPI & Mode Control Reset Control Module Window Watchdog LIN Physical Layer VSUP1 Figure 2. 908E624 Simplified Internal Block Diagram PTE0/TxD PTE1/RxD PTD0/TACH0 PTD1/TACH1 PTC0/MISO PTC1/MOSI PTC2/MCLK PTC3/OSC2 PTC4/OSC1 BEMF Module Prescaler Module Arbiter Module Periodic Wakeup Timebase Module Configuration Register Module Serial Pheripheral Interface Module Computer Operating Properly Module Enhanced Serial Communication Interface Module 2-channel Timer Interface Module B 2-channel Timer Interface Module A 5-Bit Keyboard Interrupt Module Single Breakpoint Break Module PWMIN PWMIN Amplifier Wake Up Input 2 Wake Up Input 1 High Side Driver & Diagnostic High Side Driver & Diagnostic High Side Driver & Diagnostic Voltage Regulator VSUP2 FLSVPP PTD1/TACH1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 User RAM, 512 Bytes User Flash, 15,872 Bytes Control and Status Register, 64 Bytes ALU PORT A 2 CPU Registers VDDA PTA1/KBD1 EVDD PORT B PTA0/KBD0 EVSS Internal Bus VSSA DDRC VREFL DDRA RST DDRB PTD0/TACH0 PORT C LIN DDRD PWMIN PORT D VSUP1 DDRE VSUP2 VSUP2 VSUP2 GND PORT E WDCONF M68HC08 CPU OUT -E +E VCC L2 L1 HS3 HS2 HS1 VDD INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM AGND RST_A IRQ_A IRQ VREFH 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2 Figure 3. Pin Connections Table 1. Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 16. Die Pin Pin Name Formal Name Definition MCU 1 2 6 7 8 11 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 Port B I/Os These pins are special function, bidirectional I/O port pins, that are shared with other functional modules in the MCU. MCU 3 4 5 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK Port C I/Os These pins are special function, bidirectional I/O port pins, that are shared with other functional modules in the MCU. MCU 9 IRQ External Interrupt Input MCU 10 RST External Reset MCU 12 13 PTD0/TACH0 PTD1/TACH1 Port D I /Os These pins are special function, bidirectional I /O port pins, that are shared with other functional modules in the MCU. — 14, 15, 16, 20, 21, 22, 32, 41 NC No Connect Not connected. MCU 42 PTE1/ RXD Port E I /O This pin is an asynchronous external interrupt input pin. This pin is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin is a special function, bidirectional I/O port pin, that can is shared with other functional modules in the MCU. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 16. Die Pin Pin Name Formal Name Definition MCU 43 48 VREFL VREFH ADC References These pins are the reference voltage pins for the analog-to-digital converter (ADC). MCU 44 47 VSSA VDDA ADC Supply Pins These pins are the power supply pins for the analog-to-digital converter. MCU 45 46 EVSS EVDD MCU Power Supply Pins MCU 49 50 52 53 54 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 Port A I /Os MCU 51 FLSVPP Test Pin Analog 17 PWMIN Direct High Side Control Input Analog 18 RST_A Internal Reset Output Analog 19 IRQ_A Internal Interrupt Output This pin is the interrupt output pin of the analog die indicating errors or wake-up events. Analog 23 24 L1 L2 Wake-Up Inputs These pins are the wake-up inputs of the analog chip. Analog 25 26 27 HS3 HS2 HS1 High Side Output These output pins are low RDS(ON) high side switches. Analog 31 28 VSUP1 VSUP2 Power Supply Pins Analog 29 LIN LIN Bus Analog 30 34 GND AGND Power Ground Pins Analog 33 VDD Voltage Regulator Output Analog 35 VCC Amplifier Power Supply This pin is the single +5.0 V power supply for the current sense operational amplifier. Analog 36 OUT Amplifier Output This pin is the output of the current sense operational amplifier. Analog 37 38 -E +E Amplifier Inputs These pins are the current sense operational amplifier inverted and non-inverted inputs. Analog 39 WDCONF Window Watchdog Configuration Pin Analog 40 RXD LIN Transceiver Output These pins are the ground and power supply pins, respectively. The MCU operates from a single power supply. These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. For test purposes only. Do not connect in the application. This pin allows the enabling and PWM control of the high side HS1 and HS2 pins. This pin is the reset output pin of the analog die. These pins are device power supply pins. This pin represents the single-wire bus transmitter and receiver. These pins are device power ground connections. The + 5.0 V voltage regulator output pin is intended to supply the embedded microcontroller. This input pin is for configuration of the watchdog period and allows the disabling of the watchdog. This pin is the output of LIN transceiver. 908E624 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to the device. Rating Symbol Value Unit Analog Chip Supply Voltage under Normal Operation (Steady-state) VSUP(SS) - 0.3 to 27 Analog Chip Supply Voltage under Transient Conditions VSUP(PK) - 0.3 to 40 VDD - 0.3 to 5.5 VIN (ANALOG) - 0.3 to VDD +0.3 VIN (MCU) VSS - 0.3 to VDD +0.3 All Pins except VDD, VSS, PTA0:PTA6 , PTC0:PTC1 IPIN(1) ±15 PTA0:PTA6, PTC0:PTC1 Pins IPIN(2) ± 25 Maximum Microcontroller VSS Output Current IMVSS 100 mA Maximum Microcontroller VDD Input Current IMVDD 100 mA Maximum Input Voltage, +E, -E Pins V + E-E - 0.3 to 7.0 V Maximum Input Current, +E, -E Pins I + E-E ± 20 mA VOUT - 0.3 to VCC + 0.3 V IOUT ± 20 mA Normal Operation (Steady-state) VBUS(SS) -18 to 40 Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 13) VBUS(PK) -150 to 100 Normal Operation with a 33 kΩ resistor (Steady-state) VWAKE(SS) -18 to 40 Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 13) VWAKE(PK) -100 to 100 VESD1 ± 2000 ELECTRICAL RATINGS Supply Voltage V MCU Chip Supply Voltage Input Pin Voltage V Analog Chip Microcontroller Chip Maximum Microcontroller Current per Pin mA Current Sense Operational Amplifier Maximum Output Voltage, OUT Pin Maximum Output Current, OUT Pin LIN Supply Voltage V L1 and L2 Pin Voltage V ESD Voltage Human Body Model V (1) Machine Model (1) Charge Device Model (1) VESD2 ±100 VESD3 ± 500 Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model, Robotic (CZAP = 4.0 pF). 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to the device. Rating Symbol Value Unit THERMAL RATINGS Package Operating Ambient Temperature (4) Operating Junction Temperature (2)(4) °C TA MM908E624ACPEW MM908E624AYPEW - 40 to 85 - 40 to 125 TJ MM908E624ACPEW MM908E624AYPEW °C - 40 to 125 - 40 to 125 Storage Temperature TSTG - 40 to 150 °C Peak Package Reflow Temperature During Reflow(3)(5) TPPRT Note 5 °C Notes 2. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation of the analog die. The analog die junction temperature must not exceed 150°C under these conditions. 3. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 4. Independent of TA, device parametrics are only guaranteed for - 40 < TJ < 125 °C. Please see note 2. TJ is a factor of power dissipation, package thermal resistance, and available heat sinking. 5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 908E624 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP 5.5 — 18 V VSUPOP — — 27 V IRUN — 20 — mA VSUP = 13.5 V, LIN in recessive state ISTOP — 60 75 μA VSUP = 13.5 V, LIN in recessive state ISLEEP — 35 45 μA VOL — — 0.4 V SUPPLY VOLTAGE RANGE Nominal Operating Voltage Functional Operating Voltage (6) SUPPLY CURRENT RANGE Normal Mode (7) VSUP = 13.5 V, Analog Chip in Normal Mode, MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled Stop Mode (7), (8) Sleep Mode (7), (8) DIGITAL INTERFACE RATINGS (ANALOG DIE) Output Pin RST_A Low-state Output Voltage (IOUT = - 1.5 mA) IOH — 250 — μA IOL_MAX -1.5 — -8.0 mA Low-state Output Voltage (IOUT = - 1.5 mA) VOL — — 0.4 High-state Output Voltage (IOUT = 250 μA) VOH 3.85 — — Low-state Output Voltage (IOUT = - 1.5 mA) VOL — — 0.4 High-state Output Voltage (IOUT = 250 μA) VOH 3.85 — — V CIN — 4.0 — pF Input Logic Low Voltage VIL — — 1.5 V Input Logic High Voltage VIH 3.5 — — V IIN -10 — 10 μA CIN — 4.0 — pF IPU — 40 — μA High-state Output Current (VOUT > 3.5 V) Pull-down Current Limitation Output Pin IRQ_A V Output Pin RXD Capacitance (9) V Input Pin PWMIN Input Current Capacitance (9) Pin TXD, SS – Pull-up Current Notes 6. Device is fully functional. All functions are operating. Over-temperature may occur. 7. Total current (IVSUP1 + IVSUP2) measured at GND pin. 8. Stop and Sleep mode current will increase if VSUP exceeds 15 V. 9. This parameter is guaranteed by process monitoring but is not production tested. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max 3.6 4.0 4.4 Unit SYSTEM RESETS AND INTERRUPTS Low-voltage Reset (LVR) V V LVRON Threshold Low-voltage Interrupt (LVI) V Threshold V LVI 5.7 6.0 6.6 Hysteresis V LVI_HYS — 1.0 — Threshold V HVI 18 19.25 20.5 V Hysteresis V HVI_HYS — 220 — mV High-voltage Interrupt (HVI) VOLTAGE REGULATOR (10) Normal Mode Output Voltage Normal Mode Output Current Limitation V V DDRUN 2.0 mA < IDD < 50 mA, 5.5 V < VSUP < 27 V (11) IDDRUN Dropout Voltage 4.75 5.0 5.25 50 110 200 — 0.1 0.2 V V DDDROP VSUP = 4.9 V, IDD = 50 mA mA Stop Mode Output Voltage (12) V DDSTOP 4.75 5.0 5.25 V Stop Mode Regulator Current Limitation IDDSTOP 4.0 8.0 14 mA Normal Mode, 5.5 V < VSUP < 27 V, IDD = 10 mA VLRRUN — 20 150 Stop Mode, 5.5 V < VSUP < 27 V, IDD = 2.0 mA VLR STOP — 10 100 Line Regulation mV Load Regulation mV Normal Mode, 1.0 mA < IDD < 50 mA, VSUP = 18 V VLRRUN — 40 150 Stop Mode, 1.0 mA < IDD < 5.0 mA, VSUP = 18 V VLDSTOP — 40 150 T PRE 120 135 160 °C T SD 155 170 — °C 20 30 45 Over-temperature Prewarning (Junction) (13) Thermal Shutdown Temperature (Junction) Temperature Threshold Difference TSD - TPRE (13) ΔT SD-T PRE °C Notes 10. Specification with external capacitor 2.0 μF< C < 10 μF and 200 mΩ ≤ ESR ≤ 10 Ω. Capacitor value up to 47 μF can be used. 11. Total VDD regulator current. A 5.0 mA current for current sense operational amplifier is included. Digital output supplied from VDD. 12. 13. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification. This parameter is guaranteed by process monitoring but not production tested 908E624 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit REXT 10 — 100 kΩ -15 — 15 WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy) (14) WDCACC % LIN PHYSICAL LAYER LIN Transceiver Output Voltage V Recessive State, TXD HIGH, IOUT = 1.0 μA V LIN_REC VSUP -1 — — Dominant State, TXD LOW, 500 Ω External Pull-up Resistor V LIN_DOM — — 1.4 Normal Mode Pullup Resistor to VSUP R PU 20 30 60 kΩ Stop, Sleep Mode Pull-up Current Source IPU — 2.0 — μA IOV-CUR 50 75 150 mA — 1.0 10 0.0 3.0 20 -1.0 — 1.0 Output Current Shutdown Threshold Leakage Current to GND μA IBUS VSUP Disconnected, VBUS at 18 V Recessive State, 8.0 V ≤ VSUP ≤ 18 V, 8.0 V≤ VBUS ≤ 18 V, VBUS ≥ VSUP GND Disconnected, VGND = VSUP, VBUS at -18 V LIN Receiver VSUP Receiver Threshold Dominant V BUS_DOM — — Receiver Threshold Recessive V BUS_REC 0.6 — — V BUS_CNT 0.475 0.5 0.525 V BUS_HYS — — 0.175 Receiver Threshold Center Receiver Threshold Hysteresis 0.4 HIGH SIDE OUTPUTS HS1 AND HS2 Switch On Resistance TJ = 25 °C, ILOAD = 150 mA, VSUP > 9.0 V Ω RDS(ON) — 2.0 2.5 TJ = 125 °C, ILOAD = 150 mA, VSUP > 9.0 V — — 4.5 TJ = 125 °C, ILOAD = 120 mA, 5.5 V < VSUP > 9.0 V — 3.0 — ILIM 300 — 600 mA THSSD 155 — 190 °C ILEAK — — 10 μA Output Current Limit Over-temperature Shutdown (15), (16) Leakage Current Output Clamp Voltage V VCL IOUT = -100 mA - 6.0 — — Notes 14. Watchdog timing period calculation formula: PWD = 0.991 * REXT + 0.648 (REXT in kΩ and PWD in ms). 15. 16. This parameter is guaranteed by process monitoring but it is not production tested When over-temperature occurs, switch is turned off and latched off. Flag is set in SPI. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit — — 7.0 TJ = 125 °C, ILOAD = 50 mA, VSUP > 9.0 V — — 10 TJ = 125 °C, ILOAD = 30 mA, 5.5 V < VSUP > 9.0 V — — 14 ILIM 60 100 200 mA THSSD 155 — 190 °C ILEAK — — 10 μA VIMC - 0.1 — VCC + 0.1 V Output Current ± 1.0 mA VOUT1 0.1 — VCC - 0.1 Output Current ± 5.0 mA VOUT2 0.3 — VCC - 0.3 Input Bias Current IB — — 250 nA Input Offset Current IO -100 — 100 nA Input Offset Voltage VIO - 25 — 25 mV 5.5 V < VSUP < 6.0 V 2.0 2.5 3.0 6.0 V < VSUP < 18 V 2.5 3.0 3.5 18 V < VSUP < 27 V 2.7 3.2 3.7 5.5 V < VSUP < 6.0 V 2.7 3.3 3.8 6.0 V < VSUP < 18 V 3.0 4.0 4.5 18 V < VSUP < 27 V 3.5 4.2 4.7 0.5 — 1.3 -10 — 10 HIGH SIDE OUTPUT HS3 Switch On Resistance TJ = 25 °C, ILOAD = 50 m A, VSUP > 9.0 V Output Current Limitation Over-temperature Shutdown (17), (18) Leakage Current Ω RDS(ON) CURRENT SENSE OPERATIONAL AMPLIFIER Rail-to-Rail Input Voltage Output Voltage Range V L1 AND L2 INPUTS Low Detection Threshold High Detection Threshold Hysteresis VTHL VTHH V V VHYS 5.5 V < VSUP < 27 V Input Current V μA IIN - 0.2 V < VIN < 40 V Notes 17. This parameter is guaranteed by process monitoring but it is not production tested 18. When over-temperature occurs, switch is turned off and latched off. Flag is set in SPI. 908E624 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Dominant Propagation Delay TXD to LIN t DOM-MIN — — 50 μs Dominant Propagation Delay TXD to LIN t DOM-MAX — — 50 μs Recessive Propagation Delay TXD to LIN t REC-MIN — — 50 μs Recessive Propagation Delay TXD to LIN t REC-MAX — — 50 μs Propagation Delay Symmetry: t DOM-MIN - t REC-MAX DT1 -10.44 — — μs Propagation Delay Symmetry: t DOM-MAX - t REC-MIN DT2 — — 11 μs Dominant Propagation Delay TXD to LIN t DOM-MIN — — 100 μs Dominant Propagation Delay TXD to LIN t DOM-MAX — — 100 μs Recessive Propagation Delay TXD to LIN t REC-MIN — — 100 μs Recessive Propagation Delay TXD to LIN t REC-MAX — — 100 μs Propagation Delay Symmetry: t DOM-MIN - t REC-MAX DT1S - 22 — — μs Propagation Delay Symmetry: t DOM-MAX - t REC-MIN DT2S — — 23 μs SRFAST — 15 — V / μs Receiver Dominant Propagation Delay (22) t RL — 3.5 6.0 μs Receiver Recessive Propagation Delay (22) t RH — 3.5 6.0 μs t R-SYM - 2.0 — 2.0 μs t PROPWL 35 — 150 μs t WAKE — 20 — μs LIN PHYSICAL LAYER Driver Characteristics for Normal Slew Rate (19), (20) Driver Characteristics for Slow Slew Rate (19), (21) Driver Characteristics for Fast Slew Rate LIN High Slew Rate (Programming Mode) Receiver Characteristics and Wake-Up Timings Receiver Propagation Delay Symmetry Bus Wake-up Deglitcher Bus Wake-up Event Reported (23) Notes 19. VSUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. 20. See Figure 6, page 14. 21. See Figure 7, page 14. 22. Measured between LIN signal threshold VIL or VIH and 50% of RXD signal. 23. t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 15. In Sleep mode the VDD rise time is strongly dependent upon the decoupling capacitor at VDD pin. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit tOV-DELAY — 10 — μs f SPIOP 0.25 — 4.0 MHz t WUF 8.0 20 38 μs LIN PHYSICAL LAYER (CONTINUED) Output Current Shutdown Delay SPI INTERFACE TIMING SPI Operating Recommended Frequency L1 AND L2 INPUTS Wake-up Filter Time (24) WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) Watchdog Period t PWD ms External Resistor REXT = 10 kΩ (1%) — 10.558 External Resistor REXT = 100 kΩ (1%) — 99.748 — Without External Resistor REXT (WDCONF Pin Open) 97 150 205 — STATE MACHINE TIMING Reset Low Level Duration after VDD High (28) t RST 0.65 1.0 1.35 ms Interrupt Low Level Duration t INT 7.0 10 13 μs t NR TOUT 97 150 205 ms t S-HSON — 3.0 10 μs t S-HSOFF — 3.0 10 μs t S-NR2N 6.0 35 70 μs 15 40 80 90 — N/A t S-1STSPI 30 — N/A μs t 2SS 15 — — μs Normal Request Mode Timeout (28) Delay Between SPI Command and HS1 / HS2 / HS3 Turn On (25) , (26) Delay Between SPI Command and HS1 / HS2 / HS3 Turn Off (25) , (26) Delay Between Normal Request and Normal Mode After W/ D Trigger Command (27) Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode (VDD On and Reset High) t W-SS Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI Command t W-SPI Delay Between Interrupt Pulse and First SPI Command Accepted Minimum Time Between Two Rising Edges on SS Notes 24. 25. 26. 27. 28. μs μs This parameter is guaranteed by process monitoring but is not production tested. Delay between turn-on or turn-off command and high side on or high side off, excluding rise or fall time due to external load. Delay between the end of the SPI command (rising edge of the SS) and start of device activation / deactivation. This parameter is guaranteed by process monitoring but it is not production tested. Also see Figure 10 on page 15 908E624 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MICROCONTROLLER PARAMETRICS Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Supply Voltage Rejection Ratio (29) SVR 60 — — dB (29) CMR 70 — — dB GBP 1.0 — — MHz SR 0.5 — — V/ μs PHMO 40 — — ° OLG — 85 — dB CURRENT SENSE OPERATIONAL AMPLIFIER Common Mode Rejection Ratio Gain Bandwidth (29) Slew Rate Phase Margin (for Gain = 1, Load 100 pF / 5.0 kΩ (29) Open Loop Gain Notes 29. This parameter is guaranteed by process monitoring but it is not production tested. MICROCONTROLLER PARAMETRICS Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet. Module Description Core High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Timer Two 16-Bit Timers with 2 Channels (TIM A and TIM B) Flash 16 K Bytes RAM 512 Bytes ADC 10-Bit Analog-to-Digital Converter SPI SPI Module ESCI Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment ICG Internal Clock Generation Module TIMING DIAGRAMS Transient Pulse Generator LIN, L1, and L2 10 kΩ 10k 1.0 nF 1nF Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b. Figure 4. Test Circuit for Transient Test Pulses 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VSUP VSUP R0 TXD LIN RXD C0 R0R0 and C0C0 Combinations: and combinations: ‚Ä¢ 1.0 kΩ and 1.0 - 1k Ohm and 1nF ‚Ä¢- 600 Ω and 6.86.8nF 660 Ohm and ‚Ä¢- 500 Ω and 1010nF 500 Ohm and Figure 5. Test Circuit for LIN Timing Measurements TXD tREC-MAX LIN tDOM-MIN 58.1% VSUP VLIN_REC 74.4% VSUP 40% VSUP 60% VSUP 28.4% VSUP 42.2% VSUP tDOM-MAX tREC-MIN RXD tRL tRH Figure 6. LIN Timing Measurements for Normal Slew Rate TXD tREC-MAX LIN t DOM-MIN VLIN_REC 61.6% VSUP 77.8% VSUP 40% Vsup 60% VSUP 25.1% VSUP 38.9% VSUP t DOM-MAX tREC-MIN RXD t RL t RH Figure 7. LIN Timing Measurements for Slow Slew Rate 908E624 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS LIN VLIN_REC 0.4VSUP 0.4 VSUP Dominant level Dominant Level VDD t PROPWL TpropWL t WAKE Twake Figure 8. Wake-up Sleep Mode Timing LIN VLIN_REC 0.4VSUP 0.4 VSUP Dominant level Dominant Level IRQ_A tTwake WAKE t PROPWL TpropWL Figure 9. Wake-up Stop Mode Timing VSUP VDD RST_A tRST tNRTOUT Figure 10. Power On Reset and Normal Request Timeout Timing 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E624 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E624 is well suited to perform relay control in applications like window lift, sunroof, etc., via a three-wire LIN bus. The device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as high side outputs. Other ports are also provided, which include a current sense operational amplifier port and two wake-up pins. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL PIN DESCRIPTION See Figure 1, 908E624 Simplified Application Diagram, page 1, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on page 3 for a depiction of the pin locations on the package. PORT A I /O PINS (PTA0:4) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt pins KBD0 : KBD4. The PTA5/SPSCK pin is not accessible in this device and is internally connected to the SPI clock pin of the analog die. The PTA6/ SS pin is likewise not accessible. For details, refer to the 68HC908EY16 data sheet. PORT B I/O PINS (PTB1:7) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. All pins are shared with the ADC module. The PTB6 : PTB7 pins are also shared with the Timer B module. The PTB0/AD0 and PTB2/AD2 pins are not accessible in this device. For details, refer to the 68HC908EY16 data sheet. PORT C I/O PINS (PTC2:4) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI pins of the analog die. For details, refer to the 68HC908EY16 data sheet. PORT D I /O PINS (PTD:0:1) PTD1/ TACH1 and PTD0/ TACH0/BEMF are special function, bidirectional I /O port pins that can also be programmed to be timer pins. For details, refer to the 68HC908EY16 data sheet. PORT E I /O PIN (PTE1) PTE1/ RXD and PTE0/ TXD are special function, bidirectional I/O port pins that can also be programmed to be enhanced serial communication. PTE0/ TXD is internally connected to the TXD pin of the analog die. The connection for the receiver must be done externally. For details, refer to the 68HC908EY16 data sheet. EXTERNAL INTERRUPT PIN (IRQ) The IRQ pin is an asynchronous external interrupt pin. This pin contains an internal pull-up resistor that is always activated, even when the IRQ pin is pulled LOW. For details, refer to the 68HC908EY16 data sheet. EXTERNAL RESET PIN (RST) A logic [0] on the RST pin forces the MCU to a known startup state. It is driven LOW when any internal reset source is asserted. This pin contains an internal pull-up resistor that is always activated, even when the reset pin is pulled LOW. Important To ensure proper operation, do not add any external pull-up resistor. For details, refer to the 68HC908EY16 data sheet. MCU POWER SUPPLY PINS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground pins, respectively. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details, refer to the 68HC908EY16 data sheet. 908E624 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION ADC SUPPLY PINS (VDDA AND VSSA) VDDA and VSSA are the power supply pins for the analogto-digital converter (ADC). It is recommended that a highquality ceramic decoupling capacitor be placed between these pins. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground pin for the ADC and should be tied to the same potential as EVSS via separate traces. For details, refer to the 68HC908EY16 data sheet. the watchdog period. If the pin is open, the watchdog period is fixed to its default value. The watchdog can be disabled (e.g., for flash programming or software debugging) by connecting this pin to GND. POWER SUPPLY PINS (VSUP1 AND VSUP2) This VSUP1 power supply pin supplies the voltage regulator, the internal logic, and LIN transceiver. This VSUP2 power supply pin is the positive supply for the high side switches. ADC REFERENCE PINS (VREFL AND VREFH) VREFL and VREFH are the reference voltage pins for the ADC. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSSA via separate traces. For details, refer to the 68HC908EY16 data sheet. POWER GROUND PIN (GND) This pin is the device ground connection. HIGH SIDE OUTPUT PINS (HS1 AND HS2) These pins are high side switch outputs to drive loads such as relays or lamps. Each switch is protected with overtemperature and current limit (over-current). The output has an internal clamp circuitry for inductive load. The HS1 and HS2 outputs are controlled by the SPI and have a direct enabled input (PWMIN) for PWM capability. TEST PIN (FLSVPP) This pin is for test purposes only. Do not connect in the application or connect to GND. PWMIN PIN (PWMIN) This pin is the direct PWM input for high side outputs 1 and 2 (HS1 and HS2). If no PWM control is required, PWMIN must be connected to VDD to enable the HS1 and HS2 outputs. LIN TRANSCEIVER OUTPUT PIN (RXD) This pin is the output of LIN transceiver. The pin must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD pin). RESET PIN (RST_A) RST_A is the reset output pin of the analog die and must be connected to the RST pin of the MCU. Important To ensure proper operation, do not add any external pull-up resistor. INTERRUPT PIN (IRQ_A) IRQ_A is the interrupt output pin of the analog die indicating errors or wake-up events. This pin must be connected to the IRQ pin of the MCU. WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) This pin is the configuration pin for the internal watchdog. A resistor is connected to this pin. The resistor value defines HIGH SIDE OUTPUT PIN (HS3) This high side switch can be used to drive small lamps, Hall-effect sensors, or switch pull-up resistors. The switch is protected with over-temperature and current limit (overcurrent). The output is controlled only by the SPI. LIN BUS PIN (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. WAKE-UP PINS (L1 AND L2) These pins are high-voltage capable inputs used to sense external switches and to wake-up the device from Sleep or Stop mode. During Normal mode the state of these pins can be read through the SPI. Important If unused, these pins should be connected to VSUP or GND to avoid parasitic transitions. In Low Power Mode, this could lead to random wake-up events. CURRENT SENSE OPERATIONAL AMPLIFIER PINS (E+, E-, OUT, VCC) These are the pins of the single supply current sense operational amplifier. • The E+ and E- input pins are the non-inverting and inverting inputs of the current sense operational amplifier, respectively. • The OUT pin is the output pin of the current sense operational amplifier. • The VCC pin is the + 5.0 V single supply connection. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Note If the operational amplifier is not used, it is possible to connect all pins (E+, E-, OUT and VCC) to GND. In this case, all of the four pins must be grounded. + 5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD) The VDD pin is needed to place an external capacitor to stabilize the regulated output voltage. The VDD pin is intended to supply the embedded microcontroller. The pin is protected against shorts to GND with an integrated current limit (temperature shutdown could occur). Important The VDD, EVDD, VDDA, and VREFH pins must be connected together. VOLTAGE REGULATOR AND CURRENT SENSE AMPLIFIER GROUND PIN (AGND) The AGND pin is the ground pin of the voltage regulator and the current sense operational amplifier. Important GND, AGND, VSS, EVSS, VSSA, and VREFL pins must be connected together. NO CONNECT PINS (NC) The NC pins are not connected internally. Note Each of the NC pins can be left open or connected to ground (recommended). 908E624 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES 908E624 ANALOG DIE MODES OF OPERATION Wake-up from Stop mode is initiated by a wake-up interrupt. Wake-up from Sleep mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MODE1:2 bits in the SPI Control register. Figure 11 describes how transitions are done between the different operating modes and Table 6, page 20, gives an overview of the operating mode. The 908E624 offers three operating modes: Normal (Run), Stop, and Sleep. In Normal mode the device is active and is operating under normal application conditions. The Stop and Sleep modes are low-power modes with wake-up capabilities. In Stop mode, the voltage regulator still supplies the MCU with VDD (limited current capability), and in Sleep mode the voltage regulator is turned off (VDD = 0 V). Normal Request Timeout Expired (t NRTOUT ) Normal Request timeout expired (NR TOUT) VVDD Low DD Low VDD High and Normal Request VVDDLow Low DD VVDD LOW (>t NRTOUT ) expired) Expired DD Low (>NRTOUT and and VSUVLVF =0 =0 Wake-up Wake-Up (Reset) (Reset) Sleep Command SLEEP Command Sleep Stop STOPCommand Command Normal WD Failed WD failed Wake-up Interrupt Wake-Up Interrupt Reset Reset Delay (t Delay VDD High and Reset RST) expired RST) (tExpired WD Disabled WD disabled Power Up WDtrigger Trigger WD Power Down Stop VDD VDD Low Low Legend WD: Watchdog Notes: WD Disabled: Watchdog disabled (WDCONF pin connected to GND) WD - meansisWatchdog WD Trigger: Watchdog triggered by SPI command WD means or Watchdog disabled (WDCONF terminal connected to GND) WD Failed: No disabled watchdog- trigger trigger occurs in closed window WD trigger – means Watchdog is triggered by SPI command Stop Command: Stop command sent via SPI WD failed – means no Watchdog trigger or trigger occurs in closed window Sleep Command: Sleep command sent via SPI STOP Command - means STOP command sent via SPI Wake-up: L1 or L2 state change or LIN bus wake-up or SS rising edge SLEEP Command - means SLEEP command send via SPI Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge Figure 11. Operating Modes and Transitions 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 6. Operating Modes Overview Device Mode Voltage Regulator Wake-up Capabilities Output Watchdog Function HS1, HS2, and HS3 LIN Interface Sense Amplifier Reset VDD ON N/A LOW Disabled Disabled Recessive only Not active Normal Request VDD ON N/A HIGH 150 ms time out if WD enabled Enabled Transmit and receive Not active Normal (Run) VDD ON N/A HIGH Window WD if enabled Enabled Transmit and receive Active Stop VDD ON with limited current capability LIN wake-up, L1, L2 state change, SS rising edge HIGH Disabled Disabled Recessive state with wake-up capability Not active Sleep VDD OFF LIN wake-up L1, L2 state change LOW Disabled Disabled Recessive state with wake-up capability Not active RST_A INTERRUPTS Wake-up Interrupts In Normal (Run) mode the 908E624 has four different interrupt sources. An interrupt pulse on the IRQ_A pin is generated to report a fault to the MCU. All interrupts are not maskable and cannot be disabled. After an Interrupt the INTSRC bit in the SPI Status register is set, indicating the source of the event. This interrupt source information is only transferred once, and the INTSRC bit is cleared automatically. In Stop mode the IRQ_A pin reports wake-up events on the L1, L2, or the LIN bus to the MCU. All wake-up interrupts are not maskable and cannot be disabled. After a wake-up interrupt, the INTSRC bit in the Serial Peripheral Interface (SPI) Status register is set, indicating the source of the event. This wake-up source information is only transferred once, and the INTSRC bit is cleared automatically. Figure 12, page 21, describes the Stop / Wake-up procedure. Low-Voltage Interrupt Low-voltage interrupt (LVI) is related to external supply voltage VSUP1. If this voltage falls below the LVI threshold, it will set the LVF bit in the SPI Status register and an interrupt will be initiated. The LVF bit remains set as long as the Lowvoltage condition is present. During Sleep and Stop mode the low-voltage interrupt circuitry is disabled. High-voltage Interrupt High-voltage interrupt (HVI) is related to external supply voltage VSUP1. If this voltage rises above the HVI threshold, it will set the HVF bit in the SPI Status register and an interrupt will be initiated. The HVF bit remains set as long as the high-voltage condition is present. During Sleep and Stop mode the high-voltage interrupt circuitry is disabled. Voltage Regulator Temperature Prewarning (VDDT) Voltage regulator temperature prewarning (VDDT) is generated if the voltage regulator temperature is above the TPRE threshold. It will set the VDDT bit in the SPI Status register and an interrupt will be initiated. The VDDT bit remains set as long as the error condition is present. During Sleep and Stop mode the voltage regulator temperature prewarning circuitry is disabled. High Side Switch Thermal Shutdown (HSST) The high side switch thermal shutdown HSST is generated if one of the high side switches HS1 : HS3 is above the HSST threshold, it will shutdown all high side switches, set the HSST flag in the SPI Status register and an interrupt will be initiated. The HSST bit remains set as long as the error condition is present. During Sleep and Stop mode the high side switch thermal shutdown circuitry is disabled. 908E624 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MCU Power Die From Reset initialize operate SPI: 2x STOP Command Switch to VREG low current mode STOP Wake-up on LIN or L1, L2? IRQ interrupt ? Assert IRQ SPI: reason for interrupt Switch to VREG high current mode operate Figure 12. Stop Mode / Wake-up Procedure ANALOG DIE INPUTS / OUTPUTS High Side Output Pins HS1 and HS2 These are two high side switches used to drive loads such as relays or lamps. They are protected with over-temperature and current limit (over-current) and include an active internal clamp circuitry for inductive load drive. Control is done using the SPI Control register. PWM capability is offered through the PWMIN input pin. The high side switch is turned on if both the HSxON bit in the SPI Control register is set and the PWMIN input is HIGH (refer to Figure 13, page 22). In order to have HS1 on, the PWMIN must be HIGH and bit HS1ON must be set. The same applies to the HS2 output. If no PWM control is required, PWMIN must be connected to the VDD pin. Current Limit (Over-current) Protection These high side switches feature current limit to protect them against over-current and short circuit conditions. Over-temperature Protection If an over-temperature condition occurs on any of the three high side switches, all high side switches (HS1, HS2, and HS3) are turned off and latched off. The failure is reported by the HSST bit in the SPI Control register. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Sleep and Stop Mode Current Limit (Over-current) Protection In Sleep and Stop modes the high sides are disabled. This high side feature switch feature current limit to protect it against over-current and short-circuit conditions. High Side Output HS3 This high side switch can be used to drive small lamps, Hall-effect sensors, or switch pull-up resistors. Control is done using the SPI Control register. No direct PWM control is possible on this pin (refer to Figure 14, page 22). Over-temperature Protection If an over-temperature condition occurs on any of the three high side switches, all high side switches (HS1, HS2, and HS3) are turned off and latched off. The failure is reported by the HSST bit in the SPI Control register. Sleep and Stop Mode In Sleep and Stop mode the high side is disabled. . PWMIN VSUP2 MODE1:2 HSxON Control On/Off High Side Driver Status Charge Pump, Current Limit Protection, Over-temperature Protection HSx Figure 13. High Side HS1 and HS2 Circuitry . MODE1:2 VSUP2 HS3ON Control On/Off High Side Driver Status Charge Pump, Current Limit Protection, Over-temperature Protection HS3 Figure 14. High Side HS3 Circuitry LIN PHYSICAL LAYER The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low side MOSFET with over-current protection and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The slew rate can be selected for optimized operation at 10 and 20 kBit/s as well as a fast baud rate for test and programming. The slew rate can be adapted with the bits LINSL2:1 in the SPI Control Register. The initial slew rate is optimized for 20 kBit/s. 908E624 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES The LIN pin offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. the transmitter and set the LINFAIL flag in the SPI Status Register. For improved performance and safe behavior in case of LIN bus short to Ground or LIN bus leakage during low power mode the internal pull-up resistor on the LIN pin can be disconnected, with the LIN-PU bit in the SPI Control Register, and a small current source keeps the LIN bus at recessive level. In case of a LIN bus short to GND, this feature will reduce the current consumption in STOP and SLEEP modes. The LIN transmitter circuitry is enabled in Normal and Normal Request mode. An over-current condition (e.g. LIN bus short to VBAT) or a over-temperature in the output low side FET will shutdown MODE2:1 LINSL2:1 LIN-PU VSUP1 LINWU LINFAIL Control 2µA 30k LIN bus TXD Slope Control Wake-up Filter Receiver GND RXD Figure 15. LIN Interface TXD Pin STOP Mode and Wake-up Feature The TXD pin is the MCU interface to control the state of the LIN transmitter (see Figure 2, page 2). When TXD is LOW, the LIN pin is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off (recessive state). The TXD pin has an internal pull-up current source in order to set the LIN bus to recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. During STOP mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Stop mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in recessive state. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by an rising edge will generate a wake-up interrupt and set the LINWF flag in the SPI Status Register. Also see Figure 9, page 15. RXD Pin The RXD transceiver pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. SLEEP Mode and Wake-up Feature During SLEEP mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Sleep mode sequence the internal pull-up resistor is 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES disconnected from VSUP and a small current source keeps the LIN pin in recessive state. The receiver is still active to be able to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by an rising edge will generate a system wake-up (reset) and set the LINWF flag in the SPI Status Register. Also see Figure 8, page 15). WINDOW WATCHDOG The window watchdog is configurable using an external resistor at the WDCONF pin. The watchdog is cleared through by the MODE1:2 bits in the SPI Control register (refer to Table 8, page 26). A watchdog clear is only allowed in the open window. If the watchdog is cleared in the closed window or has not been cleared at the end of the open window, the watchdog will generate a reset on the RST_A pin and reset the whole device. Note The watchdog clear in Normal request mode (150 ms) (first watchdog clear) has no window. Window closed no watchdog clear allowed Window open for watchdog clear WD timing x 50% WD timing x 50% WD period (t (PPWD WD) ) WD timing selected by resistor on WDCONF terminal. Figure 16. Window Watchdog Operation Current Limit (Over-current) Protection The voltage regulator has current limit to protect the device against over-current and short-circuit conditions. Over-temperature Protection The voltage regulator also features an over-temperature protection having an over-temperature warning (Interrupt VDDT) and an over-temperature shutdown. Stop Mode During Stop mode, the Stop mode regulator supplies a regulated output voltage. The Stop mode regulator has a limited output current capability. Sleep Mode In Sleep mode the voltage regulator external VDD is turned off. FACTORY TRIMMING AND CALIBRATION To enhance the ease of use of the 908E624, various parameters (e.g., ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” (0xFF) state: • 0xFD80 :0xFDDF Trim and Calibration Values • 0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values The usage of the trim values, located in the flash memory, is explained in the following. Watchdog Configuration Internal Clock Generator (ICG) Trim Value If the WDCONF pin is left open, the default watchdog period is selected (typ. 150 ms). If no watchdog function is required, the WDCONF pin must be connected to GND. The watchdog period is calculated using the following formula: The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low frequency base clock (IBASE), will vary as much as ±25%, due to process, temperature, and voltage dependencies. To compensate for these dependencies, an ICG trim value is located at the address $FDC2. After trimming the ICG, a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100 nF) and stabilized (4.7 μF) VDD = 5.0 V, TAmbient~23 °C) and will vary over-temperature and voltage (VDD) as indicated in the 68HC908EY16 data sheet. To trim the ICG, these values must be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to be copied after every reset. t PWD [ms] = 0.991 * REXT [kΩ] + 0.648 VOLTAGE REGULATOR The 908E624 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD pin to provide the 5.0 V to the microcontroller. OPERATING MODES OF THE MCU For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 data sheet. 908E624 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS 908E624 SPI INTERFACE AND CONFIGURATION • MOSI — Master-Out Slave-In • MISO — Master-In Slave-Out • SPSCK — Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 8 bits of control information and the slave replies with 8 bits of status data. The serial peripheral interface creates the communication link between the microcontroller and the analog die of the 908E624. The interface consists of four pins (see Figure 17): • SS — Slave Select SS Register write data MOSI D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Register read data MISO D7 D6 D5 D4 D3 SPSCK Read data latch Rising edge of SPSCK Change MISO/MOSI Output Write data latch Falling edge of SPSCK Sample MISO/MOSI Input Figure 17. SPI Protocol The data transfer is only valid if exactly 8 sample clock During the inactive phase of the SS (HIGH), the new data edges are present in the active (low) phase of SS. transfer is prepared. The rising edge of the slave select SS indicates the end of The falling edge of the SS indicates the start of a new data transfer and puts the MISO in the low-impedance state and the transfer and latches the write data (MOSI) into the latches the analog status data (Register read data). register The SS high forces MISO to the high-impedance state. With the rising edge of the SPI clock, SPSCK the data is moved to MISO/MOSI pins. With the falling edge of the SPI SPI REGISTER OVERVIEW clock SPSCK the data is sampled by the Receiver. Table 7 summarizes the SPI Register bit meaning, reset value, and bit reset condition. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS . Table 7. SPI Register Overview Bit Read / Write Information D7 Write LINSL2 INTSRC (30) Read D6 D5 D4 D3 D2 D1 D0 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 LINWU or LINFAIL HVF LVF or BATFAIL (31) VDDT HSST L2 L1 Write Reset Value 0 0 0 0 0 0 — — Write Reset Condition POR, RESET POR, RESET POR POR, RESET POR, RESET POR, RESET — — Notes 30. D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source. 31. The first SPI read after reset returns the BATFAIL flag state on bit D4. reduce the power consumption, e.g. in combination with STOP/SLEEP mode. SPI Control Register (Write) Table 8 shows the SPI Control register bits by name. HS3ON : HS1ON — High Side H3 : HS1 Enable Bits Table 8. Control Bits Function (Write Operation) D7 D6 D5 D4 D3 D2 D1 D0 LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 LINSL2 : 1 — LIN Baud Rate and Low-power Mode Selection Bits These bits enable the HSx. Reset clears the HSxON bit. • 1 = HSx switched on (refer to Note below). • 0 = HSx switched off. Note If no PWM on HS1 and HS2 is required, the PWMIN pin must be connected to the VDD pin. These bits select the LIN slew rate and requested lowpower mode in accordance with Table 9. Reset clears the LINSL2 : 1 bits. MODE2 : 1 — Mode Section Bits Table 9. LIN Baud Rate and Low-power Mode Selection Bits Table 10. Mode Selection Bits MODE2 MODE1 Description 0 0 Sleep Mode (32) Baud Rate up to 20 kbps (normal) 0 1 Stop Mode (32) 1 Baud Rate up to 10 kbps (slow) 1 0 Watchdog Clear (33) 0 Fast Program Download Baud Rate up to 100 kbps 1 1 Run (Normal) Mode LINSL2 LINSL1 Description 0 0 0 1 1 The MODE2 : 1 bits control the operating modes and the watchdog in accordance with Table 10. 1 Low-power Mode (Sleep or Stop) Request LIN-PU — LIN Pull-up Enable Bit This bit controls the LIN pull-up resistor during Sleep and Stop modes. • 1 = Pull-up disconnected in Sleep and Stop modes. • 0 = Pull-up connected in Sleep and Stop modes. If the Pull-up is disconnected, a small current source is used to pull the LIN pin in recessive state. In case of an erroneous short of the LIN bus to ground, this will significantly Notes 32. To enter Sleep and Stop mode, a special sequence of SPI commands is implemented. 33. The device stays in Run (Normal) mode. To safely enter Sleep or Stop mode and to ensure that these modes are not affected by noise issue during SPI transmission, the Sleep / Stop commands require two SPI transmissions. Sleep Mode Sequence The Sleep command, as shown in Table 11, must be sent twice. Table 11. Sleep Command Bits LINSL2 LINSL1 LIN-PU HS3ON HS2ON 1 1 0/1 0 0 HS1ON MODE2 MODE1 0 0 0 908E624 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION Stop Mode Sequence The Stop command, as shown in Table 12, must be sent twice. Table 12. Stop Command Bits LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 1 1 0/1 0 0 0 0 1 SPI Status Register (Read) Table 13 shows the SPI Status register bits by name. Table 13. Control Bits Function (Read Operation) D7 D6 D5 D4 D3 D2 D1 D0 INTSRC LINWU or LINFAIL HVF LVF or BATFAIL VDDT HSST L2 L1 INTSCR — Register Content Flags or Interrupt Source This bit indicates if the register contents reflect the flags or an interrupt / wake-up interrupt source. • 1 = D6 : D0 reflects the interrupt or wake-up source. • 0 = No interrupt occurred. Other SPI bits report real time status. LINWU / LINFAIL — LIN Status Flag Bit This bit indicates a LIN wake-up condition. • 1 = LIN bus wake-up occurred or LIN over-current/overtemperature occurred. • 0 = No LIN bus wake-up occurred. In case of a LIN over-current/over-temperature condition the LIN transmitter is disabled. To reenable the LIN transmitter, the error condition must be GONE and the LINWU/LINFAIL flag must be cleared. The flag is cleared by reading the flag when it is set (SPI command). HVF — High-voltage Flag Bit This flag is set on an over-voltage (VSUP1) condition. • 1 = High-voltage condition has occurred. • 0 = no High-voltage condition. LVF / BATFAIL — Low-voltage Flag Bit This flag is set on an under-voltage (VSUP1) condition. • 1 = Low-voltage condition has occurred. • 0 = No low-voltage condition. VDDT — Voltage Regulator Status Flag Bit This flag is set as prewarning in case of an overtemperature condition on the voltage regulator. • 1 = Voltage regulator over-temperature condition, prewarning. • 0 = No over-temperature detected. HSST — High Side Status Flag Bit This flag is set on over-temperature conditions on one of the high side outputs. • 1 = HSx off due to over-temperature. • 0 = No over-temperature. In case one of the high sides has an over-temperature condition all high side switches are disabled. To reenable the high side switches, the flags have to be cleared, by reading the flag when it is set and by writing a one to high side HSxON bit (two SPI commands are necessary). L2:L1— Wake-up Inputs L1, L2 Status Flag Bit These flags reflect the status of the L2 and L1 input pins and indicate the wake-up source. • 1 = L2 : L1 input high or wake-up by L2 : L1 (first register read after wake-up indicated with INTSRC = 1). • 0 = L2 : L1 input low. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 27 TYPICAL APPLICATIONS TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E624 has the MC68HC908EY16 MCU embedded typically all the development tools available for the MCU also apply for this device, however due to the fact of the additional analog die circuitry and the nominal +12 V supply voltage some additional items have to be considered: • nominal 12 V rather than 5.0 or 3.0 V supply • high voltage VTST might be applied not only to IRQ pin, but IRQ_A pin • MCU monitoring (Normal request timeout) has to be disabled For a detailed information on the MCU related development support see the MC68HC908EY16 data sheet section development support. The programming is principally possible at two stages in the manufacturing process — first on chip level, before the IC is soldered onto a PCB board and second after the IC is soldered onto the PCB board. Chip Level Programming On Chip level the easiest way is to only power the MCU with +5.0 V (see Figure 18) and not to provide the analog chip with VSUP, in this setup all the analog pin should be left open (e.g. VSUP[1:2]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 data sheet - section development support. VSUP[1:2] VDD GND AGND +5V VREFH RST VDDA RST_A EVDD VDD 100nF 1 1µF C1- GND C2+ V+ + 5 2 16 C2- MAX232 V- 15 1µF VDD 5 8 R2IN R2OUT 9 10k 9.8304MHz CLOCK 1µF PTB4/AD4 CLK T2IN 10 6 10k 10k 5 +5V PTC4/OSC1 PTA1/KBD1 DATA 10k PTA0/KBD0 4 PTB3/AD3 WDCONF 3 2 VSSA EVSS 6 + 4.7µF VREFL IRQ_A + 2 74HC125 3 MM908E624 1µF 74HC125 7 T2OUT IRQ VTST + 4 RS232 DB-9 VCC + 3 1µF C1+ 1 Figure 18. Normal Monitor Mode Circuit (MCU only) Of course it is also possible to supply the whole system with VSUP (12 V) instead as described in Figure 19, page 29. 908E624 28 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS system has to be powered up providing VSUP (see Figure 19). PCB Level Programming If the IC is soldered onto the PCB board, it is typically not possible to separately power the MCU with +5.0 V, the whole VDD VSUP[1:2] VSUP 47µF + VDD GND 100nF AGND VREFH RST VDDA RST_A EVDD VDD 100nF 1 1µF VTST + 4 C1- GND C2+ V+ + 5 RS232 DB-9 16 + 3 1µF VCC C1+ C2- MAX232 V- 1µF + IRQ_A VDD R2OUT 9 PTB4/AD4 CLK T2IN 10 8 R2IN 10k 9.8304MHz CLOCK 1µF 6 74HC125 3 VSSA EVSS 6 + 7 T2OUT MM908E624 1µF 2 VDD PTC4/OSC1 10k 10k PTA1/KBD1 5 DATA 10k PTA0/KBD0 4 PTB3/AD3 WDCONF 3 2 4.7µF VREFL 2.2k 15 74HC125 2 IRQ 1 5 Figure 19. Normal Monitor Mode Circuit Table 14 summarizes the possible configurations and the necessary setups. Table 14. Monitor Mode Signal Requirements and Options Mode IRQ RST WDCONF Normal Monitor Forced Monitor VTST VDD GND X GND $FFFF (blank) VDD VDD Reset Vector Serial Communication Mode Selection PTA0 PTA1 PTB3 PTB4 1 0 0 1 1 0 X VDD VDD REXT not $FFFF (not blank) X X X ICG COP OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 ON disabled disabled — Nominal 1.6 MHz Nominal 6300 ON enabled enabled — Nominal 1.6 MHz Nominal 6300 X GND User Communication Speed Normal Request Bus Timeout External Frequenc Baud Rate Clock y X Notes 34. PTA0 must have a pull-up resistor to VDD in monitor mode. 35. 36. 37. 38. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256. X = don’t care. VTST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 29 TYPICAL APPLICATIONS EMC/EMI RECOMMENDATIONS MCU Digital Supply Pins (EVDD and EVSS) This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be found on the Freescale website: www.freescale.com. Fast signal transitions on MCU pins place high, short duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. VSUP Pins (VSUP1 and VSUP2) Its recommended to place a high quality ceramic decoupling capacitor close to the VSUP pins to improve EMC/EMI behavior. LIN Pin For DPI (Direct Power Injection) and ESD (Electro Static Discharge) it is recommended to place a high quality ceramic decoupling capacitor near the LIN pin. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. MCU Analog Supply Pins (VREFH, VDDA, VREFL, and VSSA) To avoid noise on the analog supply pins it is important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. Figure 20 and Figure 21 show the recommendations on schematics and layout level and Table 15 indicates recommended external components and layout considerations. Voltage Regulator Output Pins (VDD and AGND) Use a high quality ceramic decoupling capacitor to stabilize the regulated voltage. D1 VSUP C1 + C2 VSUP1 VDD VSUP2 AGND VREFH VDDA L1 LIN LIN EVDD V1 C5 C3 MM908E624 C4 VREFL VSSA GND EVSS Figure 20. EMC/EMI Recommendations 908E624 30 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS 1 54 2 53 3 52 4 51 50 6 49 7 VREFH 48 8 VDDA 47 9 EVDD 46 10 EVSS 45 11 VSSA 44 12 VREFL 43 13 42 908E624 41 15 40 16 39 17 38 18 37 19 36 20 35 21 AGND 34 22 VDD 33 23 NC 24 VSUP1 31 25 GND 30 Comment: Terminal 32 NC - used for signal routing C4 26 LIN 29 27 VSUP2 28 C1 32 C2 14 C3 5 D1 LIN L1 V1 C5 VBAT Figure 21. PCB Layout Recommendations . Table 15. Component Value Recommendation Component Recommended Value(39) D1 Comments / Signal routing Reverse battery protection C1 Bulk Capacitor C2 100 nF, SMD Ceramic Close (