MM912F634CV2AER2

Freescale Semiconductor Document Number: MM912F634 Rev. 9.0, 6/2015 Technical Data Integrated S12 Based Relay Driver with LIN MM912F634 The MM912F634 is an integrated single package solution integrating an HCS12 microcontroller with a SMARTMOS analog control IC. The Die to Die Interface (D2D) controlled analog die combines system base chip and application specific functions, including a LIN transceiver. 48-PIN LQFP 98ASH00962A 7.0 mm x 7.0 mm AP SUFFIX: Non-exposed Pad Features • • • • • • • • • • • 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM Background debug (BDM) & debug module (DBG) Die to die bus interface for transparent memory mapping On-chip oscillator & two independent watchdogs LIN 2.1 physical layer interface with integrated SCI Six digital MCU GPIOs shared with SPI (PA5…0) 10-Bit, 15 channel - analog to digital converter (ADC) 16-Bit, four channel - timer module (TIM16B4C) 8-Bit, two channel - pulse width modulation module (PWM) Six high-voltage / wake-up inputs (L5.0) Three low-voltage GPIOs (PB2.0) • • • • • • • • 48-PIN LQFP-EP 98ASA00173D 7.0 mm x 7.0 mm AE SUFFIX: Exposed Pad Low-power modes with cyclic sense & forced wake-up Current sense module with selectable gain Reverse battery protected voltage sense module Two protected low-side outputs to drive inductive loads Two protected high-side outputs Chip temperature sensor Hall sensor supply Integrated voltage regulator(s) MM912F634 Battery Sense Power Supply VSENSE1 LS1 VS1 PGND M Low-Side Drivers VS2 LIN interface LS2 LIN ISENSEH1 LGND Current Sense Module ISENSEL1 ADC2p5 ADC Supply HSUP AGND 2.5V Supply Hall Sensor supply VDD EVDD 5V Supply VDDX EVDDX Digital Ground DGND EVSS EVSSX Hall Sensor PTB0/AD0/RX/TIM0CH0 PTB1/AD1/TX/TIM0CH1 PTB2/AD2/PWM/TIM0CH2 HS1 Reset 5V digital I/O Debug and external Oscillator MCU Test RESET RESET_A PA0/MISO PA1/MOSI PA2/SCK PA3/SS PA4 PA5 BKGD/MODC EXTAL XTAL TEST 1) HS21 L0 L1 L21 L31 L41 L51 TCLK TEST_A Feature not available in all Analog Options Figure 1. Simplified Application Diagram © Freescale Semiconductor, Inc., 2010-2015. All rights reserved. Hall Sensor 5V GPI/O with optional pull-up (shared with ADC, PWM, Timer, SCI) 12V Light/LED and switch supply Analog/Digital Inputs (High Voltage- and Wake Up capable) Analog Test ORDERING INFORMATION 1 Ordering Information ‘ Table 1. Ordering Information Temperature Range (TA) Device (2) MM912F634DV1AE MM912F634DV2AE -40 to 105 °C MM912F634DV2AP Package Max. Bus Frequency (MHz) (fBUSMAX) Flash (kB) 98ASA00173D, 48-PIN LQFP-EP 20 32 98ASH00962A, 48-PIN LQFP 16 32 Analog Option (1) RAM (kB) 1 2 2 Note: 1. See Table 2. 2. For Tape and Reel orders add R2 to the part suffix Table 2. Analog Options(3) Feature Option 1 Option 2 Current Sense Module YES NO Wake-up Inputs (Lx) L0…L5 L0…L3 Note: 3. This table only highlights the analog die differences between the derivatives. See Section 4.2.3, “Analog Die Options" for detailed information. The device part number follows the standard scheme below: MM 9 Product Category Memory Type MM – Qualified Standard 9 – FLASH, OTP SM – Custom Device Blank - ROM PM – Prototype Device 12 f xxx r MCU Core 08 – HC08 12 – HC12 Memory Size A – 1k B – 2k C – 4k D – 8k E – 16k F – 32k G – 48k H – 64k I – 96k J – 128k Analog Core/ Target Revision (default A) t TA Temperature Range I = 0°C to 85°C C = -40°C to 85°C V = -40°C to 105°C M = -40°C to 125°C a PP RR Analog Die Option (default 1) Package Designator AE – LQFP48-EP AP – LQFP48 Tape & Reel Indicator Figure 2. Part Number Scheme MM912F634 2 Analog Integrated Circuit Device Data Freescale Semiconductor ORDERING INFORMATION Table of Contents 1 2 3 4 5 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 MM912F634 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 MCU Die Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Thermal Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.8 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.9 Additional Test Information ISO7637-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 MM912F634 - Analog Die Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.5 Die to Die Interface - Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.8 Wake-up / Cyclic Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.9 Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.10 Hall Sensor Supply Output - HSUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.11 High-side Drivers - HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.12 Low-side Drivers - LSx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.13 PWM Control Module (PWM8B2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.14 LIN Physical Layer Interface - LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.15 Serial Communication Interface (S08SCIV4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.16 High Voltage Inputs - Lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.17 General Purpose I/O - PTB[0…2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.18 Basic Timer Module - TIM (TIM16B4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.19 Analog Digital Converter - ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.20 Current Sense Module - ISENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.21 Temperature Sensor - TSENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.22 Supply Voltage Sense - VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.23 Internal Supply Voltage Sense - VS1SENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.24 Internal Bandgap Reference Voltage Sense - BANDGAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.25 MM912F634 - Analog Die Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.26 MM912F634 - MCU Die Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.27 Port Integration Module (9S12I32PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.28 Memory Mapping Control (S12SMMCV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.29 Interrupt Module (S12SINTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.30 Background Debug Module (S12SBDMV1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 4.31 S12S Debug (S12SDBGV1) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.32 S12S Clocks and Reset Generator (S12SCRGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.33 External Oscillator (S12SOSCFPV1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 4.34 Real Time Interrupt (S12SRTIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 4.35 Computer Operating Properly (S12SCOPV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 4.36 32 kbyte Flash Module (S12SFTSR32KV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 4.37 Die-to-Die Initiator (D2DIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 4.38 Serial Peripheral Interface (S12SPIV4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 5.1 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ORDERING INFORMATION L L T 5 4 3 2 1 RAM 2k Byte ALU SPI Control and Status Register CPU Register M68HCS12 CPU Internal Reference Clock OSC Clock Monitor Full Swing Pierce Oscillator Reset Generation and Test Entry RESET Flash 32k Bytes SS SCK MOSI Single-Wire Background Debug Module COP Watchdog Interrupt Module Real Time Interrupt Debug Module include 64 byte Trace Buffer RAM D2DI MCU Die D2DCLK D2DDAT0 D2DDAT1 D2DDAT2 D2DDAT3 D2DINT Test Interface Reset Control Module Window Watchdog Module OSC (trimmable) Interrupt Control Module Die To Die Interface Analog Multiplexer Chip Temp Sense Module Wake Up Module 2 Channel PWM Module Current Sense Module ISENSEL 4 Channel Timer Module LS1 Low Side Control Module PGND GPIO ADC 10bit Lx Input Module SCI L5 L4 L3 L2 L1 L0 AGND ADC2p5 PTB2/AD2/PWM/TIMC PTB1/AD1/TX/TIMCH1 PTB0/AD0/RX/TIMCH0 LGND Analog Integrated Circuit Device Data Freescale Semiconductor 4 LIN Physical Layer LIN Internal Bus VS2 LS2 18V clamped Output Module HSUP MISO EVDD ISENSEH High Side Control Module HS2 Cascaded Voltage Regulators VDD = 2.5V VDDX = 5V VS1 0 EVSS TCLK VBAT Sense Module HS1 RESET_A Analog Die VSENSE X X VDDX BKGD/MODC PTA DDRA Internal Bus VDD DGND TEST_A Figure 3. Device Block Diagram MM912F634 PIN ASSIGNMENT 2 Pin Assignment NC BKGD RESET RESET_A TCLK TEST_A NC ISENSEH ISENSEL LS2 PGND LS1 48 47 46 45 44 43 42 41 40 39 38 37 NC 1 36 L5 EXTAL 2 35 L4 XTAL 3 34 L3 TEST 4 33 L2 PA5 5 32 L1 PA4 6 31 L0 PA3 7 30 AGND PA2 8 29 ADC2p5 PA1 9 28 PTB2 PA0 10 27 PTB1 EVSSX 11 26 PTB0 EVDDX 12 25 LGND 22 HS1 HS2 LIN 21 VS2 24 20 VS1 HSUP 19 VSENSE 23 18 DGND VDD 17 15 EVDD VDDX 14 EVSS 16 13 Figure 4. MM912F634 Pin Out NOTE The device exposed pad (package option AE only) is recommended to be connected to GND. Not all pins are available for analog die option 2. See Section 4.2.3, “Analog Die Options" for details. 2.1 MM912F634 Pin Description The following table gives a brief description of all available pins on the MM912F634 package. Refer to the highlighted chapter for detailed information. Table 3. MM912F634 Pin Description Pin # Pin Name Formal Name Description 1 NC Not connected Pin This pin is reserved for alternative function and should be left floating or connected to GND. 2 EXTAL MCU Oscillator Pin EXTAL is one of the optional crystal/resonator driver and external clock pins. On reset, all the device clocks are derived from the Internal Reference Clock. See Section 4.33, “External Oscillator (S12SOSCFPV1)". MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 5 PIN ASSIGNMENT Table 3. MM912F634 Pin Description (continued) Pin # Pin Name Formal Name Description 3 XTAL MCU Oscillator Pin XTAL is one of the optional crystal/resonator driver and external clock pins. On reset, all the device clocks are derived from the Internal Reference Clock. See Section 4.33, “External Oscillator (S12SOSCFPV1)". 4 TEST MCU Test Pin This input only pin is reserved for test. This pin has a pull-down device. The TEST pin must be tied to EVSS in user mode. 5 PA5 MCU PA5 Pin General purpose port A input or output pin 5. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". 6 PA4 MCU PA4 Pin General purpose port A input or output pin 4. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". 7 PA3 MCU PA3 / SS Pin General purpose port A input or output pin 3, shared with the SS signal of the integrated SPI Interface. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". 8 PA2 MCU PA2 / SCK Pin General purpose port A input or output pin 2, shared with the SCLK signal of the integrated SPI Interface. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". 9 PA1 MCU PA1 / MOSI Pin General purpose port A input or output pin 1, shared with the MOSI signal of the integrated SPI Interface. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". 10 PA0 MCU PA0 / MISO Pin General-purpose port A input or output pin 0, shared with the MISO signal of the integrated SPI Interface. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". 11 EVSSX MCU 5.0 V Ground Pin Ground for the MCU 5.0 V power supply. 12 EVDDX MCU 5.0 V Supply Pin MCU 5.0 V - I/O buffer supply. See Section 4.26, “MM912F634 - MCU Die Overview". 13 EVSS MCU 2.5 V Ground Pin Ground for the MCU 2.5 V power supply. 14 EVDD MCU 2.5 V Supply Pin MCU 2.5 V - MCU Core- and Flash power supply. See Section 4.26, “MM912F634 - MCU Die Overview". 15 VDD Voltage Regulator Output 2.5 V +2.5 V main voltage regulator output pin. External capacitor (CVDD) needed. See Section 4.4, “Power Supply". 16 VDDX Voltage Regulator Output 5.0 V +5.0 V main voltage regulator output pin. External capacitor (CVDDX) needed. See Section 4.4, “Power Supply". 17 DGND Digital Ground Pin This pin is the device digital ground connection for the 5.0 V and 2.5 V logic. DGND, LGND, and AGND are internally connected to PGND via a back to back diode. 18 VSENSE Voltage Sense Pin Battery voltage sense input. This pin can be connected directly to the battery line for voltage measurements. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC via the analog multiplexer.The pin is self-protected against reverse battery connections. An external resistor (RVSENSE) is needed for protection(4). See Section 4.22, “Supply Voltage Sense - VSENSE". 19 VS1 Power Supply Pin 1 This pin is the device power supply pin 1. VS1 is primarily supplying the VDDX Voltage regulator and the Hall Sensor Supply Regulator (HSUP). VS1 can be sensed via a voltage divider through the AD converter. Reverse battery protection diode is required. See Section 4.4, “Power Supply" 20 VS2 Power Supply Pin 2 This pin is the device power supply pin 2. VS2 supplies the High-side Drivers (HSx). Reverse battery protection diode required. See Section 4.4, “Power Supply" 21 HS1 High-side Output 1 This pin is the first High-side output. It is supplied through the VS2 pin. It is designed to drive small resistive loads with optional PWM. In cyclic sense mode, this output activates periodically during low power mode. See Section 4.11, “High-side Drivers - HS". 22 HS2 High-side Output 2 This pin is the second High-side output. It is supplied through the VS2 pin. It is designed to drive small resistive loads with optional PWM. In cyclic sense mode, this output activates periodically during low power mode. See Section 4.11, “High-side Drivers - HS". 23 HSUP 24 LIN 25 LGND This pin is designed as an 18 V Regulator to drive Hall Sensor Elements. It is supplied through Hall Sensor Supply Output the VS1 pin. An external capacitor (CHSUP) is needed. See Section 4.10, “Hall Sensor Supply Output - HSUP". LIN Bus I/O This pin represents the single-wire bus transmitter and receiver. See Section 4.14, “LIN Physical Layer Interface - LIN". LIN Ground Pin This pin is the device LIN Ground connection. DGND, LGND, and AGND are internally connected to PGND via a back to back diode. MM912F634 6 Analog Integrated Circuit Device Data Freescale Semiconductor PIN ASSIGNMENT Table 3. MM912F634 Pin Description (continued) Pin # 26 27 Pin Name PTB0 PTB1 Formal Name Description General Purpose I/O 0 This is the General Purpose I/O pin 0 based on VDDX with the following shared functions: • PTB0 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD0 - Analog Input Channel 0, 0…2.5 V (ADC2p5) analog input • TIM0CH0 - Timer Channel 0 Input/Output • Rx - Selectable connection to LIN / SCI See Section 4.17, “General Purpose I/O - PTB[0…2]". General Purpose I/O 1 This is the General Purpose I/O pin 1 based on VDDX with the following shared functions: • PTB1 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD1 - Analog Input Channel 1, 0…2.5 V (ADC2p5) analog input • TIM0CH1 - Timer Channel 1 Input/Output • Tx - Selectable connection to LIN / SCI See Section 4.17, “General Purpose I/O - PTB[0…2]". 28 PTB2 General Purpose I/O 2 This is the General Purpose I/O pin 2 based on VDDX with the following shared functions: • PTB2 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD2 - Analog Input Channel 2, 0…2.5 V (ADC2p5) analog input • TIM0CH2 - Timer Channel 2 Input/Output • PWM - Selectable connection to PWM Channel 0 or 1 See Section 4.17, “General Purpose I/O - PTB[0…2]". 29 ADC2p5 ADC Reference Voltage This pin represents the ADC reference voltage and has to be connected to a filter capacitor. See Section 4.19, “Analog Digital Converter - ADC" 30 AGND Analog Ground Pin This pin is the device Analog to Digital Converter ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode. High Voltage Input 0 This pins is the High Voltage Input 0 with the following shared functions: • L0 - Digital High Voltage Input 0. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(5) • AD3 - Analog Input 3 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU0 - Selectable Wake-up input 0 for wake up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx" High Voltage Input 1 This pins is the High Voltage Input 1 with the following shared functions: • L1 - Digital High Voltage Input 1. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(5) • AD4 - Analog Input 4 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU1 - Selectable Wake-up input 1 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". High Voltage Input 2 This pins is the High Voltage Input 2 with the following shared functions: • L2 - Digital High Voltage Input 2. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(5) • AD5 - Analog Input 5 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU2 - Selectable Wake-up input 2 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". High Voltage Input 3 This pins is the High Voltage Input 3 with the following shared functions: • L3 - Digital High Voltage Input 3. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(5) • AD6 - Analog Input 6 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU3 - Selectable Wake-up input 3 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". High Voltage Input 4 This pins is the High Voltage Input 4 with the following shared functions: • L4 - Digital High Voltage Input 4. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(5) • AD7 - Analog Input 7 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU4 - Selectable Wake-up input 4 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". Note: This pin function is not available on all device configurations. 31 32 33 34 35 L0 L1 L2 L3 L4 MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 7 PIN ASSIGNMENT Table 3. MM912F634 Pin Description (continued) Pin # Pin Name Formal Name Description High Voltage Input 5 This pins is the High Voltage Input 5 with the following shared functions: • L5 - Digital High Voltage Input 5. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(5) • AD8 - Analog Input 8 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU5 - Selectable Wake-up input 5 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". Note: This pin function is not available on all device configurations. LS1 Low-side Output 1 Low-side output 1 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.12, “Low-side Drivers - LSx". 38 PGND Power Ground Pin This pin is the device Low-side Ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode. 39 LS2 Low-side Output 2 Low-side output 2 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.12, “Low-side Drivers - LSx". 40 ISENSEL Current Sense Pins L Current Sense differential input “Low”. This pin is used in combination with ISENSEH to measure the voltage drop across a shunt resistor. See Section 4.20, “Current Sense Module - ISENSE". Note: This pin function is not available on all device configurations. 41 ISENSEH Current Sense Pins H Current Sense differential input “High”. This pin is used in combination with ISENSEL to measure the voltage drop across a shunt resistor. Section 4.20, “Current Sense Module ISENSE". Note: This pin function is not available on all device configurations. 42 NC Not connected Pin This pin is reserved for alternative function and should be left floating. 43 TEST_A Test Mode Pin Analog die Test Mode pin for Test Mode only. This pin must be grounded in user mode. 44 TCLK Test Clock Input Test Mode Clock Input pin for Test Mode only. The pin can be used to disable the internal watchdog for development purpose in user mode. See Section 4.9, “Window Watchdog". The pin is recommended to be grounded in user mode. 45 RESET_A Reset I/O Bidirectional Reset I/O pin of the analog die. Active low signal. Internal pull-up. VDDX based. See Section 4.7, “Resets". To be externally connected to the RESET pin. 46 RESET MCU Reset Pin The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device to EVDDX. 47 BKGD MCU Background Debug and Mode Pin The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pull-up device. 48 NC Not connected Pin This pin is reserved for alternative function and should be left floating or connected to GND. 36 L5 37 Note: 4. An optional filter capacitor CVSENSE is recommended to be placed between the board connector and RVSENSE to GND for increased ESD performance. 5. An optional filter capacitor CLx is recommended to be placed between the board connector and RLx to GND for increased ESD performance. 2.2 MCU Die Signal Properties This section describes the external MCU signals. It includes a table of signal properties. Table 4. Signal Properties Summary Pin Name Function 1 Pin Name Function 2 Power Supply EXTAL — XTAL RESET Internal Pull Resistor CTRL Reset State VDD NA NA — VDD NA NA — VDDX Pull-up Description Oscillator pins External reset MM912F634 8 Analog Integrated Circuit Device Data Freescale Semiconductor PIN ASSIGNMENT Table 4. Signal Properties Summary (continued) Pin Name Function 1 Pin Name Function 2 Power Supply TEST — BKGD Internal Pull Resistor Description CTRL Reset State N.A. RESET pin Down MODC VDDX Always on UP Background debug PA5 — VDDX NA NA Port A I/O PA4 — VDDX NA NA Port A I/O PA3 SS VDDX NA NA Port A I/O, SPI PA2 SCK VDDX NA NA Port A I/O, SPI PA1 MOSI VDDX NA NA Port A I/O, SPI PA0 MISO VDDX NA NA Port A I/O, SPI Test input MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS 3 Electrical Characteristics 3.1 General This supplement contains electrical information for the embedded MC9S12I32 microcontroller die, as well as the MM912F634 analog die. 3.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. All voltages are with respect to ground unless otherwise noted. Table 5. Absolute Maximum Electrical Ratings - Analog Die Ratings Symbol Value Supply Voltage at VS1 and VS2 Normal Operation (DC) Transient Conditions (load dump) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) VSUP(SS) VSUP(PK) VSUP(TR) -0.3 to 27 -0.3 to 40 see Section 3.9, “Additional Test Information ISO7637-2" L0…L5 - Pin Voltage Normal Operation with a series RLX resistor (DC) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) VLxDC VLxTR -27 to 40 see Section 3.9, “Additional Test Information ISO7637-2" LIN Pin Voltage Normal Operation (DC) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) VBUSDC VBUSTR -33 to 40 see Section 3.9, “Additional Test Information ISO7637-2" Supply Voltage at VDDX VDDX -0.3 to 5.5 V Supply Voltage at VDD (6) VDD -0.3 to 2.75 V VDD output current IVDD Internally Limited A VDDX output current IVDDX Internally Limited A TCLK Pin Voltage VTCLK -0.3 to 10 V RESET_A Pin Voltage VIN -0.3 to VDDx+0.3 V Input / Output Pins PTB[0:2] Voltage VIN -0.3 to VDDx+0.3 V HS1 and HS2 Pin Voltage (DC) VHS -0.3 to VS2+0.3 V LS1 and LS2 Pin Voltage (DC) VLS -0.3 to 45 V VISENSE -0.3 to 40 V VHSUP -0.3 to VS1+0.3 V VVSENSE -27 to 40 V ISENSEH and ISENSEL Pin Voltage (DC) HSUP Pin Voltage (DC) VSENSE Pin Voltage (DC) Unit V V V Note: 6. Caution: As this pin is adjacent to the VDDX pin, care should be taken to avoid a short between VDD and VDDX, for example, during the soldering process. A short-circuit between these pins might lead to permanent damage. MM912F634 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Table 6. Maximum Electrical Ratings - MCU Die Ratings Symbol Value Unit 5.0 V Supply Voltage VEDDX -0.3 to 6.0 V 2.5 V Supply Voltage VEDD -0.3 to 2.75 V Digital I/O input voltage (PA0...PA7, PE0, PE1) VIN -0.3 to 6.0 V EXTAL, XTAL VILV -0.3 to 2.16 V VTEST -0.3 to 10.0 V Instantaneous maximum current Single pin limit for all digital I/O pins ID -25 to 25 mA Instantaneous maximum current Single pin limit for EXTAL, XTAL I -25 to 25 mA Symbol Value Unit Storage Temperature TSTG -55 to 150 C Package Thermal Resistance - LQFP48-EP Four layer board (JEDEC 2s2p) Junction to Ambient Natural Convection (7) Junction to Board (9) Two layer board (JEDEC 1s) Junction to Ambient Natural Convection (7), (8) RJA RJB 39 16 C/W RJA 91 Package Thermal Resistance - LQFP48 Four layer board (JEDEC 2s2p) Junction to Ambient Natural Convection (7) Junction to Board (9) Two layer board (JEDEC 1s) Junction to Ambient Natural Convection (7), (8) RJA RJB 59 31 RJA 96 TPPRT 300 TEST input DL Table 7. Maximum Thermal Ratings Ratings Peak Package Reflow Temperature During Reflow (10),(11) C/W °C Notes 7. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 8. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 9. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 10. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 11. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC34xxxD enter 34xxx), and review parametrics. 3.3 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. Table 8. Operating Conditions Ratings Analog Die Nominal Operating Voltage Symbol Value Unit VSUP 5.5 to 18 V 5.5 to 27 V 4.5 to 5.5 V Analog Die Functional Operating Voltage - Device is fully functional. All features are operating. VSUPOP MCU I/O and supply voltage(12) VEDDX MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS Table 8. Operating Conditions (continued) Ratings Symbol Value Unit VEDD 2.25 to 2.75 V MCU External Oscillator fOSC 4.0 to 16 MHz MCU Bus frequency fBUS MCU Digital logic supply voltage(12) fBUSMAX (13) MHz TA -40 to 105 C Operating Junction Temperature - Analog Die TJ_A -40 to 150 C Operating Junction Temperature - MCU Die TJ_M -40 to 140 C Operating Ambient Temperature, MM912x634xVxxx Note: 12. During power up and power down sequence always VDD < VDDX 13. fBUSMAX frequency ratings differ by device and is specified in Table 1 3.4 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. 3.4.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted, the currents are measured in MCU special single chip mode and the CPU code is executed from RAM. Table 9. Supply Currents Ratings Symbol Normal Mode analog die only, excluding external loads, LIN Recessive State (5.5 V  VSUP  18 V, 2.25 V  EVDD  2.75 V, 4.5 V  EVDDX  5.5 V, -40 °C  TJ_A  150 °C). IRUN_A Normal Mode MCU die only (TJ_M = 140 °C; VDD = 2.75 V, VDDX = 5.5 V, fOSC = 4.0 MHz, fBUS = fBUSMAX(18))(15) IRUN_M Stop Mode internal analog die only, excluding external loads, LIN Recessive State, Lx enabled, measured at VS1+VS2 (5.5 V  VSUP  18 V, 2.25 V  EVDD  2.75 V, 4.5 V  EVDDX  5.5 V) -40 °C  TJ_A  125 °C 125 °C  TJ_A  140 °C ISTOP_A Stop Mode MCU die only (VDD = 2.75 V, VDDX = 5.5 V, fOSC = 4.0 MHz, fBUS = fBUSMAX(18); MCU in STOP; RTI and COP off)(16) TJ_M = 140 °C TJ_M = 105 °C TJ_M = 25 °C ISTOP_M Stop Mode MCU die only (VDD = 2.75 V, VDDX = 5.5 V, fOSC = 4.0 MHz, fBUS = fBUSMAX(18); MCU in STOP; RTI and COP on)(16) TJ_M = 140 °C TJ_M = 105 °C TJ_M = 25 °C ISTOP_M Wait Mode MCU die only (TJ_M = 140 °C; VDD = 2.75 V, VDDX = 5.5 V, fOSC = 4.0 MHz, fBUS = fBUSMAX(18); All modules except RTI disabled)(17) IWAIT_M Sleep Mode (VDD = VDDX = OFF; 5.5 V  VSUP  18 V; -40 °C  TJ_A  150 °C; 3.0 V  LX  1.0 V). ISLEEP Cyclic Sense Supply Current Adder (5.0 ms Cycle) Note: 14. 15. 16. 17. 18. Min Typ(14) Max Unit - 5.0 8.0 mA - 12.5 15 mA - 20 - 40 50 - 0.135 0.035 0.010 0.400 0.200 0.030 mA - 0.205 0.104 0.079 0.500 0.300 0.110 mA - 7.0 12 mA - 15 28 µA - 15 20 µA µA ICS Typical values noted reflect the approximate parameter mean at TA = 25 °C IRUN_M denotes the sum of the currents flowing into VDD and VDDX. ISTOP_M denotes the sum of the currents flowing into VDD and VDDX. IWAIT_M denotes the sum of the currents flowing into VDD and VDDX. fBUSMAX frequency ratings differ by device and is specified in Table 1. MM912F634 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS 3.5 Static Electrical Characteristics Static electrical characteristics noted under conditions 5.5V  VSUP  18 V, -40 °C  TA  105 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted. 3.5.1 Static Electrical Characteristics Analog Die Table 10. Static Electrical Characteristics - Power Supply Ratings Symbol Min Typ Max Unit Power-On Reset (POR) Threshold (measured on VS1) VPOR 1.5 - 3.5 V Low Voltage Warning (LVI) Threshold (measured on VS1, falling edge) Hysteresis (measured on VS1) VLVI VLVI_H 5.55 - 6.0 1.0 6.6 - V High Voltage Warning (HVI) Threshold (measured on VS2, rising edge) Hysteresis (measured on VS2) VHVI VHVI_H 18 - 19.25 1.0 20.5 - V Low Battery Warning (LBI) Threshold (measured on VSENSE, falling edge) Hysteresis (measured on VSENSE) VLBI VLBI_H 5.55 - 6.0 1.0 6.6 - V VJ2602UV 5.5 5.7 6.2 V Low VDDX Voltage (LVRX) Threshold VLVRX 2.7 3.0 3.3 V Low VDD Voltage Reset (LVR) Threshold Normal Mode VLVR 2.30 2.35 2.4 V VLVRS 1.6 1.85 2.1 V VDD Overvoltage Threshold (VROV) VVDDOV 2.575 2.7875 3.0 V VDDX Overvoltage Threshold (VROVX) VVDDXOV 5.25 5.675 6.1 V J2602 Undervoltage threshold Low VDD Voltage Reset (LVR) Threshold Stop Mode (19) Note: 19. See MM912F634ER, MM912F634, Silicon Analog Mask (M91W) / Digital Mask (M33G) Errata Table 11. Static Electrical Characteristics - Resets Ratings Symbol Min Typ Max Unit VOL - - 0.8 V RRPU 25 - 50 k Low-state Input Voltage VIL - - 0.3VDDX V High-state Input Voltage VIH 0.7VDDX - - V VRSTRV - 1.5 - V 5.0 7.5 10 mA Symbol Min Typ Max Unit Watchdog Disable Voltage (fixed voltage) VTST 7.0 - 10 V Watchdog Enable Voltage (fixed voltage) VTSTEN - - 5.5 V Low-state Output Voltage IOUT = 2.0 mA Pull-up Resistor Reset Release Voltage (VDDX) RESET_A pin Current Limitation Table 12. Static Electrical Characteristics - Window Watchdog Ratings MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS Table 13. Static Electrical Characteristics - Voltage Regulator 5V (VDDX) Ratings Min Typ Max 4.75 5.00 5.25 80 130 200 mA - 5.0 5.5 V IVDDXLIMSTOP - - 20 mA Line Regulation Normal Mode, IVDDX = 80 mA Stop Mode, IVDDX = 500 µA LRXRUN LRXSTOP - 20 - 25 200 mV Load Regulation Normal Mode, 1.0 mA < IVDDX < 80 mA Normal Mode, VSUP = 3.6 V, 1.0 mA < IVDDX < 40 mA Stop Mode, 100 µA < IVDDX < 500 µA LDXRUN LDXCRK LDXSTOP - 15 - 80 200 250 CVDDX 1.0 - 10 µF CVDDX_R - - 10  Min Typ Max Unit 2,425 2.5 2,575 - 80 80 120 143 mA 2.25 2.5 2.75 V IVDDLIMSTOP - - 10 mA Line Regulation Normal Mode, IVDD = 45 mA Stop Mode, IVDD = 1.0 mA LRRUN LRSTOP - 10 - 12.5 200 mV Load Regulation Normal Mode, 1.0 mA < IVDD < 45 mA Normal Mode, VSUP = 3.6 V, 1.0 mA < IVDD < 30 mA Stop Mode, 100 µA < IVDD < 500 µA LDRUN LDCRK LDSTOP - 7.5 - 40 40 200 CVDD 1.0 - 10 µF CVDD_R - - 10  Normal Mode Output Voltage 1.0 mA < IVDDX + IVDDXINTERNAL < 80 mA; 5.5 V < VSUP < 27 V (20) Normal Mode Output Current Limitation (IVDDX) Stop Mode Output Voltage (IVDDX + IVDDXINTERNAL < 500 µA for TJ 25 °C; IVDDX + IVDDXINTERNAL < 400 µA for TJ < 25 °C) (20) Stop Mode Output Current Limitation (IVDDX) Symbol VDDXRUN IVDDXLIMRUN Unit V VDDXSTOP External Capacitor External Capacitor ESR mV Note: 20. IVDDXINTERNAL includes internal consumption from both analog and MCU die. Table 14. Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD) Ratings Symbol VDDRUN Normal Mode Output Voltage 1.0 mA < IVDD + IVDDINTERNAL  45 mA; 5.5 V < VSUP < 27 V (21) Normal Mode Output Current Limitation (IVDD) TJ < 25 °C TJ  25 °C Stop Mode Output Voltage´ (IVDD + IVDDINTERNAL < 500 µA for TJ 25 °C; IVDD + IVDDINTERNAL < 400 µA for TJ < 25 °C) (21) Stop Mode Output Current Limitation (IVDD) V IVDDLIMRUN VDDSTOP External Capacitor External Capacitor ESR mV Note: 21. IVDDINTERNAL includes internal consumption from both analog and MCU die. MM912F634 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Table 15. Static Electrical Characteristics - Hall Sensor Supply Output - HSUP Ratings Symbol Min Typ Max Unit IHSUP 40 70 90 mA - - 10 13  VHSUPMAX 16 17.5 18 V Load Regulation (1.0 mA < IHSUP < 30 mA; VSUP > 18 V) LDHSUP - - 500 mV Hall Supply Capacitor Range CHSUP 0.22 - 10 µF CHSUP_R - - 10  Current Limitation (3.7 V  VSUP  18 V) Output Drain-to-Source On resistance TJ = 150 °C, ILOAD = 30 mA; 5.5 V  VSUP  16 V TJ = 150 °C, ILOAD = 30 mA; 3.7 V  VSUP < 5.5 V Output Voltage: (18 V  VSUP  27 V) External Capacitor ESR RDS(on) Table 16. Static Electrical Characteristics - High-side Drivers - HS Ratings Symbol Min Typ Max - - 7.0 10 14 Unit Output Drain-to-Source On resistance TJ = 25 °C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150 °C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150 °C, ILOAD = 30 mA; 5.5V < VSUP < 9.0 V RDS(ON) Output Current Limitation (0 V < VOUT < VSUP - 2.0 V) ILIMHSX 60 110 250 mA Open Load Current Detection IOLHSX - 5.0 7.5 mA Leakage Current (-0.2 V < VHSx < VS2 + 0.2 V) ILEAK - - 10 µA Current Limitation Flag Threshold (5.5 V < VSUP < 27 V) VTHSC VSUP -2 - - V Min Typ Max Unit – – – – – – 2.5 4.5 10  Table 17. Static Electrical Characteristics - Low-side Drivers - LS Ratings Symbol Output Drain-to-Source On resistance TJ = 25 °C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 150 °C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 150 °C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V RDS(ON) Output Current Limitation (2.0 V < VOUT < VSUP) ILIMLSX 180 275 380 mA Open Load Current Detection IOLLSX - 8.0 12 mA Leakage Current (-0.2 V < VOUT < VS1) ILEAK - - 10 µA VCLAMP 40 - 45 V Coil Series Resistance (IOUT = 150 mA) RCOIL 120 - Coil Inductance (IOUT = 150 mA) RCOIL - - 400 mH Current Limitation Flag Threshold (5.5 V < VSUP < 27 V) VTHSC 2.0 - - V Symbol Min Typ Max Unit IBUSLIM 40 120 200 mA Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE; Driver OFF; VBUS = 0 V; VBAT = 12 V IBUS_PAS_DOM -1.0 - - mA Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE; Driver OFF; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS  VBAT IBUS_PAS_REC - - 20 µA Active Output Energy Clamp (IOUT = 150 mA)   Table 18. Static Electrical Characteristics - LIN Physical Layer Interface - LIN Ratings Current Limitation for Driver dominant state. VBUS = 18 V MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS Table 18. Static Electrical Characteristics - LIN Physical Layer Interface - LIN (continued) Ratings Symbol Min Typ Max Unit Input Leakage Current; GND Disconnected; GNDDEVICE = VSUP; 0 < VBUS < 18 V; VBAT = 12 V IBUS_NO_GND -1.0 - 1.0 mA Input Leakage Current; VBAT disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V IBUS_NO_BAT - - 100 µA Receiver Input Voltage; Receiver Dominant State VBUSDOM - - 0.4 VSUP Receiver Input Voltage; Receiver Recessive State VBUSREC 0.6 - - VSUP Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VBUS_CNT 0.475 0.5 0.525 VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VBUS_HYS - - 0.175 VSUP Voltage Drop at the serial Diode DSER_INT 0.4 0.7 1.0 V RSLAVE 20 30 60 k VWUP 4.5 5.0 6.0 V VDOM - - 2.5 V LIN Pull-up Resistor Bus Wake-up Threshold from Stop or Sleep(22) Bus Dominant Voltage Note: 22. Considering drop from VBAT to LIN, at very low VBAT level, the internal logic detects a dominant as the threshold does not decrease with VSUP. Table 19. Static Electrical Characteristics - High Voltage Inputs - Lx Ratings Symbol Min Typ Max Unit Low Detection Threshold 7.0 V  VSUP  27 V 5.5 V  VSUP  7 V VTHL 2.2 1.5 2.5 2.5 3.4 4.0 V High Detection Threshold 7.0 V  VSUP  27 V 5.5 V  VSUP  7 V VTHH 2.6 2.0 3.0 3.0 3.7 4.5 V Hysteresis 5.5 V  VSUP  27 V VHYS 0.25 0.45 1.0 V IIN -10 - 10 µA RLxIN - - 1.2 M RLx 9.5 10 10.5 k CLx - 100 - nF Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0) LXDS (Lx Divider Select) = 0 LXDS (Lx Divider Select) = 1 RATIOLx - 2.0 7.2 - Analog Input Divider Ratio Accuracy RATIOLX -5.5 - 5.5 % Analog Inputs Channel Ratio - Mismatch LXDS (Lx Divider Select) = 0 LXDS (Lx Divider Select) = 1 LxMATCH - - 5.0 5.0 % Input Current Lx (-0.2 V < VIN < VS1) Analog Input Impedance Lx Lx Series Resistor Lx Capacitor (optional)(23) Note: 23. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" are guaranteed without the optional capacitor. Table 20. Static Electrical Characteristics - General Purpose I/O - PTB[0…2] Ratings Symbol Min Typ Max Unit Input high voltage VIH 0.7VDDX - VDDX+0.3 V Input low voltage VIL VSS-0.3 - 0.35VDDX V Input hysteresis VHYS - 140 - mV Input high voltage (VS1 = 3.7 V) VIH3.7 2.1 - VDDX+0.3 V MM912F634 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Table 20. Static Electrical Characteristics - General Purpose I/O - PTB[0…2] (continued) Ratings Symbol Min Typ Max Unit Input low voltage (VS1 = 3.7 V) VIL3.7 VSS-0.3 - 1.4 V Input hysteresis (VS1 = 3.7 V) VHYS3.7 100 200 300 mV -1.0 - 1.0 µA Input leakage current (pins in high-impedance input mode) (VIN = VDDX or VSSX) IIN Output high voltage (pins in output mode) Full drive IOH = –10 mA VOH VDDX-0.8 - - V Output low voltage (pins in output mode) Full drive IOL = +10 mA VOL - - 0.8 V Internal pull-up resistance (VIH min > Input voltage > VIL max) RPUL 26.25 37.5 48.75 k CIN - 6.0 - pF VCL_AIN VDD - - V Analog Input impedance = 10 k max, Capacitance = 12 pF RAIN - - 10 k Analog Input Capacitance = 12 pF CAIN - 12 - pF Maximum current all PTB combined (VDDX capability) IBMAX -15 - 15 mA Output Drive strength at 10 MHz COUT - - 100 pF Input capacitance Clamp Voltage when selected as analog input Table 21. Static Electrical Characteristics - Analog Digital Converter - ADC(24) Ratings Symbol Min Typ Max ADC2p5 Reference Voltage 5.5 V < VSUP < 27 V VADC2p5RUN 2,45 2.5 2,55 ADC2p5 Reference Stop Mode Output Voltage VADC2p5STOP - - 100 mV Line Regulation, Normal Mode LRRUNA - 10 12.5 mV External Capacitor CADC2p5 0.1 - 1.0 µF External Capacitor ESR CVDD_R - - 10 W Scale Factor Error ESCALE -1 - 1 LSB Differential Linearity Error EDNL -1.5 - 1.5 LSB Integral Linearity Error EINL -1.5 - 1.5 LSB Zero Offset Error EOFF -2.0 - 2.0 LSB Quantization Error EQ -0.5 - 0.5 LSB Total Error with offset compensation TE -5.0 - 5.0 LSB ADCH14 1.1 1.25 1.4 V Bandgap measurement Channel (CH14) Valid Result Range (including 7.0% bg1p25 sleep accuracy + high-impedance measurement error of 5.0% at fADC)(25) Unit V Note: 24. No external load allowed on the ADC2p5 pin. 25. Reduced ADC frequency lowers measurement error. MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS Table 22. Static Electrical Characteristics - Current Sense Module - ISENSE Ratings Symbol Gain CSGS (Current Sense Gain Select) = 000 CSGS (Current Sense Gain Select) = 001 CSGS (Current Sense Gain Select) = 010 CSGS (Current Sense Gain Select) = 011 CSGS (Current Sense Gain Select) = 100 CSGS (Current Sense Gain Select) = 101 CSGS (Current Sense Gain Select) = 110 CSGS (Current Sense Gain Select) = 111 Gain Accuracy Offset Resolution Min Typ Max Unit - 7.0 9.0 10 12 14 18 24 36 - -3.0 - 3.0 % G (26) ISENSEH, ISENSEL Input Common Mode Voltage Range Current Sense Module - Normal Mode Current Consumption Adder (CSE = 1) -1.5 - 1.5 % RES - 51 - mA/LSB VIN -0.2 - 3.0 V IISENSE - 600 - µA Symbol Min Typ Max Unit TSG - 9.17 - mV/k Note: 26. RES = 2.44 mV/(GAIN*RSHUNT) Table 23. Static Electrical Characteristics - Temperature Sensor - TSENSE Ratings Internal Chip Temperature Sense Gain (27) Internal Chip Temperature Sense Error at the end of conversion(27) Temperature represented by a ADCIN Voltage of 0.150 TSERR –5.0 - 5.0 °C V(27) T0.15V -55 -50 -45 °C (27) T1.984V 145 150 155 °C Temperature represented by a ADCIN Voltage of 1.984 V Note: 27. Guaranteed by design and characterization. Table 24. Static Electrical Characteristics - Supply Voltage Sense - VSENSE and VS1SENSE Ratings VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / ADCIN) 5.5 V < VSUP < 27 V VSENSE error - whole path (VSENSE pin to Digital value) VS1SENSE Input Divider Ratio (RATIOVS1SENSE = VVS1SENSE / ADCIN) 5.5 V < VSUP < 27 V VS1SENSE error - whole path (VS1 pin to Digital value) VSENSE Series Resistor (28) VSENSE Capacitor (optional) Symbol Min RATIOVSENSE ERVSENSE Typ Max Unit 5.0 % 10.8 - RATIOVS1SENSE 10.8 ERVS1SENSE - - 5.0 % RVSENSE 9.5 10 10.5 k CVSENSE - 100 - nF Note: 28. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" is guaranteed without the optional capacitor. MM912F634 18 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS 3.5.2 Static Electrical Characteristics MCU Die 3.5.2.1 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. Table 25. 5.0 V I/O Characteristics for PTA, RESET and BKGD Pins Ratings Symbol Min Typ Max Unit 0.65*VDD - - V Input high voltage V Input high voltage VIH - - VDD + 0.3 V Input low voltage VIL - - 0.35*VDD V Input low voltage VIL VSS - 0.3 - - V Input hysteresis VHYS - 250 - mV IIN -1.0 - 1.0 A OH VDD – 0.8 - - V OH VDD – 0.8 - - V Input leakage current (pins in high-impedance input mode) Vin = VDDX or VSSX IH Output high voltage (pins in output mode) Partial Drive IOH = -2.0 mA V Output high voltage (pins in output mode) Full Drive IOH = -10 mA V Output low voltage (pins in output mode) Partial drive IOL = +2.0 mA VOL - - 0.8 V Output low voltage (pins in output mode) Full Drive IOL = +10 mA VOL - - 0.8 V Internal pull-up resistance (VIHmin > input voltage > VILmax) RPUL 25 - 50 k Internal pull-down resistance (VIHmin > input voltage > VILmax) RPDH 25 - 50 k Cin - 6.0 - pF IICS IICP -2.5 -25 - 2.5 25 mA Input capacitance current(29) Injection Single pin limit Total device Limit, sum of all injected currents Note: 29. Refer to Section 3.8, “ESD Protection and Latch-up Immunity" for more details. 3.6 Dynamic Electrical Characteristics Dynamic electrical characteristics noted under conditions 5.5V  VSUP  18 V, -40 °C  TA  105 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted. 3.6.1 Dynamic Electrical Characteristics Analog Die Table 26. Dynamic Electrical Characteristics - Modes of Operation Ratings Symbol Min Typ Max Unit VDD Short Timeout tVTO 110 150 205 ms Analog Base Clock fBASE - 100 - kHz Reset Delay tRST 140 200 280 µs Table 27. Dynamic Electrical Characteristics - Power Supply Ratings Glitch Filter Low Battery Warning Symbol Min Typ Max Unit (LBI)(30) tLB - 2.0 - µs (30) tLV - 2.0 - µs Glitch Filter Low Voltage Warning (LVI) MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS Table 27. Dynamic Electrical Characteristics - Power Supply (continued) Ratings Symbol Min Typ Max Unit (30) tHV - 2.0 - µs Symbol Min Typ Max Glitch Filter High Voltage Warning (HVI) Note: 30. Guaranteed by design. Table 28. Dynamic Electrical Characteristics - Die to Die Interface - D2D Ratings Unit fD2D fADC(MIN) - Symbol Min Typ Max Unit Reset Deglitch Filter Time tRSTDF 1.2 2.0 3.0 µs Reset Low Level Duration tRSTLOW 140 200 280 µs Symbol Min Typ Max Unit Lx Wake-up Filter Time tWUF - 20 Cyclic Sense / Forced Wake-up Timing Accuracy - not trimmed CSAC -35 - 35 % trimmed(32) CSACT -5.0 - 5.0 % Operating Frequency (D2DCLK, D2D[0:3]) fBUSMAX (31) MHz Note: 31. fBUSMAX frequency ratings differ by device and is specified in Table 1 Table 29. Dynamic Electrical Characteristics - Resets Ratings Table 30. Dynamic Electrical Characteristics - Wake-up / Cyclic Sense Ratings Cyclic Sense / Forced Wake-up Timing Accuracy - Time between HSx on and Lx sense during cyclic sense tS s same as tHSON / tHSONT - tHSON 140 200 280 s tHSONT 180 200 220 s Symbol Min Typ Max Unit Initial Non-window Watchdog Timeout tIWDTO 110 150 190 ms Watchdog Timeout Accuracy - not trimmed WDAC -35 - 35 % Watchdog Timeout Accuracy - trimmed WDACT -5.0 - 5.0 % Symbol Min Typ Max Unit - - 50 kHz HSx ON duration during Cyclic Sense HSx ON duration during Cyclic Sense - trimmed(32) Note: 32. Trimming parameters are not available in Sleep mode. Table 31. Dynamic Electrical Characteristics - Window Watchdog Ratings Table 32. Dynamic Electrical Characteristics - High-side Drivers - HS Ratings High-side Operating Frequency(33), Load Condition: CLOAD2.2 nF; RLOAD500  fHS Note: 33. Guaranteed by design. MM912F634 20 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Table 33. Dynamic Electrical Characteristics - Low-side Drivers - LS Ratings (34), Low-side Operating Frequency RLOAD500  Symbol Min Typ Max Unit - - 50 kHz Symbol Min Typ Max Unit tPROPWL 60 80 100 µs BRFAST - - 100 kBit/s tREC_PD - - 6.0 µs tREC_SYM -2.0 - 2.0 µs fHS Load Condition: CLOAD2.2 nF; Note: 34. Guaranteed by design. Table 34. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN Ratings Bus Wake-up Deglitcher (Sleep and Stop Mode) Fast Bit Rate (Programming Mode) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF )(35) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR LIN Driver - 20.0 kBit/s; Bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 k / 6,8 nF;660  / 10 nF;500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 6. Duty Cycle 1: THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, 7.0 V VSUP18 V; tBit = 50 µs;, D1 = tBUS_REC(MIN)/(2 x tBit) D1 0.396 - - Duty Cycle 2: THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, 7.6 V VSUP18 V; tBIT = 50 µs, D2 = tBUS_REC(MAX)/(2 x tBIT) D2 - - 0.581 LIN Driver - 10.0 kBit/s; Bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 k / 6,8 nF;660  / 10 nF;500  Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 7. Duty Cycle 3: THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, 7.0 V VSUP18 V; tBIT = 96 µs, D3 = TBUS_REC(MIN)/(2 x tBIT) D3 0.417 - - Duty Cycle 4: THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, 7.6 V VSUP18 V; tBIT = 96 µs, D4 = tBUS_REC(MAX)/(2 x tBIT) D4 - - 0.590 tTRAN_SYM -7.25 0 7.25 Transmitter Symmetry tTRAN_SYM < MAX(tTRAN_SYM60%, tTRAN_SYM40%) tran_sym60% = ttran_pdf60% - ttran_pdr60% tran_sym40% = ttran_pdf40% - ttran_pdr40% µs Note: 35. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 8. 36. LIN Transmitter Timing, (VSUP from 7.0 to 18 V) - See Figure 9 VSU VSU RO TXD LIN RXD CO GND Note: Rn and Cn: 1.0k/1.0nF, 660/6.8 Figure 5. Test Circuit for Timing Measurements MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 21 ELECTRICAL CHARACTERISTICS Figure 6. LIN Timing Measurements for Normal Baud Rate Figure 7. LIN Timing Measurements for Slow Baud Rate MM912F634 22 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Figure 8. LIN Receiver Timing TX BUS 60% 40% ttran_pdf60% ttran_pdr40% ttran_pdf40% ttran_pdr60% Figure 9. LIN Transmitter Timing Table 35. Dynamic Electrical Characteristics - General Purpose I/O - PTB[0…2] Ratings GPIO Digital Frequency(37) Propagation Delay - Rising Rise Time - Rising Edge (37) Propagation Delay - Falling Rise Time - Falling Edge(37), (38) Edge(37) Edge(37) Symbol Min Typ Max Unit fPTB - - 10 MHz tPDR - - 20 ns tRISE - - 17.5 ns tPDF - - 20 ns tFALL - - 17.5 ns Note: 37. Guaranteed by design. 38. Load PTBx = 100 pF. MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 23 ELECTRICAL CHARACTERISTICS Table 36. Dynamic Electrical Characteristics - Analog Digital Converter - ADC Ratings ADC Operating Symbol Min Typ Max Unit fADC 1.6 2.0 2.4 MHz Frequency(39) Conversion Time (from ACCR write to CC Flag)(39) tCONV Sample Frequency Channel 14 (Bandgap) (39) fCH14 26 - - clk 2.5 kHz Note: 39. Guaranteed by design. 3.6.2 3.6.2.1 Dynamic Electrical Characteristics MCU Die NVM Timing The time base for all NVM program or erase operations is derived from the bus block. A minimum bus frequency fNVMBUS is required for performing program or erase operations. The NVM module do not has any means to monitor the frequency and does not prevent a program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency, a full program, or erase transition is not assured. The Flash program and erase operations are timed using a clock derived from the bus clock using the FCLKDIV and register. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table 37 are calculated for maximum fNVMOP and maximum fBUS. The maximum times are calculated for minimum fNVMOP and a fBUS of 2.0 MHz. 3.6.2.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP, and can be calculated according to the following formula. t 3.6.2.1.2 swpgm 1 1 = 9  ------------------------- + 25  ----------f f NVMOP bus Burst Programming This applies only to the Flash, where up to 64 words in a row can be programmed consecutively, using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: bwpgm 1 1 = 4  ------------------------- + 9  ----------f f NVMOP bus t = t t The time to program a whole row is: brpgm swpgm + 63  t bwpgm Burst programming is more than 2 times faster than single word programming. 3.6.2.1.3 Sector Erase NOTE The sector erase cycle is divided into 16 individual erase pulses to achieve faster system response during the erase flow. The given erase time (tERA) specifies the time considering consecutive pulses. MM912F634 24 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Erasing a 512-byte Flash sector takes: t era 1  4000  ------------------------f NVMOP The setup time can be ignored for this operation. 3.6.2.1.4 Mass Erase Erasing a NVM block takes: t mass 1  20000 Þ ------------------------f NVMOP The setup time can be ignored for this operation. 3.6.2.1.5 Blank Check The time it takes to perform a blank check on the Flash is dependant on the location of the first non-blank word, starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check ª location Þ t cyc + 10 Þ t cyc Table 37. NVM Timing Characteristics Rating Symbol Min Typ Max Unit Bus frequency for programming or erase operations fNVMBUS 1.0 - - MHz Operating frequency fNVMOP 150 - 200 kHz tSWPGM 46(40) - 74.5(40) s Single word programming time Flash burst programming consecutive word Flash burst programming time for 64 Sector erase words(43) time(41) Mass erase time Blank check time Flash per block tBWPGM 20.4 (40) tBRPGM 1331.2(40) tERA 20(42) tMASS tCHECK 100 (44) 11(43) - 31 (41) s - 2027.5(41) s - 26.7(41) ms - (41) ms - 133 65546(44) tCYC Note: 40. Minimum programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fBUS. 41. The sector erase cycle is divided into 16 individual erase pulses to achieve faster system response during the erase flow. The given erase time (tERA) specifies the time considering consecutive pulses. 42. Minimum erase times are achieved under maximum NVM operating frequency, fNVMOP. 43. Minimum time, if first word in the array is not blank. 44. Maximum time to complete check on an erased block. MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 25 ELECTRICAL CHARACTERISTICS 3.6.2.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress tests during qualification, constant process monitors, and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Table 38. NVM Reliability Characteristics Rating Symbol Data retention after 10,000 program/erase cycles for TJAVG 85 C Data retention with VLVRX the MM912F634 analog die enters in Normal mode. To avoid short-circuit conditions being present for a long time, a tVTO timeout is implemented. Once VDD < VLVR or VDDX < VLVRX with VS1 > (VLVRI+ VLVR _H) for more than tVTO, the MM912F634 analog die transitions directly to Sleep mode. The Reset Status Register (RSR) indicates the source of the reset by individual flags. • • • • • • POR - Power On Reset LVR - Low Voltage Reset VDD LVRX - Low Voltage Reset VDDX WDR - Watchdog Reset EXR - External Reset WUR - Wake-up Sleep Reset MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 51 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION See also Section 4.7, “Resets". 4.3.3 Normal Mode In Normal mode, all MM912F634 analog die user functions are active and can be controlled by the D2D Interface. Both regulators (VDD and VDDX) are active and operate with full current capability. Once entered in Normal mode, the Watchdog operates as a simple non-window watchdog with an initial timeout (tIWDTO) to be reset via the D2D Interface. After the initial reset, the watchdog operates in standard window mode. See Section 4.9, “Window Watchdog" for details. 4.3.4 Stop Mode NOTE To avoid any pending analog die interrupts prevent the MCU from entering MCU stop resulting in unexpected system behavior, the analog die IRQ sources should be disabled and the corresponding flags be cleared before entering stop. The Stop mode allows reduced current consumption with fast startup time. In this mode, both voltage regulators (VDD and VDDX) are active, with limited current drive capability. In this condition, the MCU is supposed to operate in Low Power mode (STOP or WAIT). The device can enter in Stop mode by configuring the Mode Control Register (MCR) via the D2D Interface. The MCU has to enter a Low Power mode immediately afterwards executing the STOP or WAIT instruction. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. While in Stop mode, the MM912F634 analog die wakes up on the following sources: • • • • Lx - Wake-up (maskable with selectable cyclic sense) Forced Wake-up (configurable timeout) LIN Wake-up D2D Wake-up (special command) After Wake-up from the sources listed above, the device transitions to Normal mode. Reset wakes up the device directly to Reset mode. See Section 4.8, “Wake-up / Cyclic Sense" for details. 4.3.5 Sleep Mode The Sleep mode allows very low current consumption. In this mode, both voltage regulators (VDD and VDDX) are inactive. The device can enter into Sleep mode by configuring the Mode Control Register (MCR) via the D2D- Interface. During Sleep mode, all unused internal blocks are deactivated to allow the lowest possible consumption. Power consumption decreases further if the Cyclic Sense or Forced Wake-up feature are disabled. While in Sleep mode, the MM912F634 analog die wakes up on the following sources: • Lx - Wake-up (maskable with selectable cyclic sense) • Forced Wake-up (configurable timeout) • LIN Wake-up After Wake-up from the sources listed above or a reset condition, the device transitions to Reset mode. See Section 4.8, “Wake-up / Cyclic Sense" for details. MM912F634 52 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.3.6 Analog Die Functionality by Operation Mode Table 71. Operation Mode Overview Function Reset Normal Stop Sleep VDD/VDDX full full stop OFF HSUP full OFF OFF LSx full OFF OFF Cyclic Sense(66) HSx full ADC full OFF OFF D2D full functional OFF full Wake-up(66) Wake-up(66) full OFF OFF Lx OFF PTBx Cyclic Sense(66) (66) Wake-up(66) LIN full Watchdog full(67) OFF OFF VSENSE full OFF OFF CSENSE full OFF OFF Cyclic Sense Wake-up not active Cyclic Sense(66) Cyclic Sense(66) Note: 66. If configured. 67. Special init through non window watchdog. 4.3.7 Register Definition 4.3.7.1 Mode Control Register (MCR) Table 72. Mode Control Register (MCR) Offset() 0x16 R Access: User read/write 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 1 MODE W Reset 0 0 0 Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 73. MCR - Register Field Descriptions Field 1-0 MODE Description Mode Select - These bits issue a transition from to the selected Operating mode. 00 - Normal mode. Only with effect in Stop Mode. Issues a wake-up and transition to Normal mode. 01 - Stop mode. Initiates a transition to Stop mode.(68) 10 - Sleep mode. Initiates transition to Sleep mode. 11 - Normal mode. Note: 68. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 53 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.4 Power Supply The MM912F634 analog die supplies VDD (2.5 V), VDDX (5.0 V), and HSUP, based on the supply voltage applied to the VS1 pin. VDD is cascaded of the VDDX regulator. To separate the High-side outputs from the main power supply, the VS2 pin does only power the High-side drivers. Both supply pins have to be externally protected against reverse battery conditions. To supply external Hall Effect Sensors, the HSUP pin supplies a switchable regulated supply. See Section 4.10, “Hall Sensor Supply Output - HSUP". A reverse battery protected input (VSENSE) is implemented to measure the Battery Voltage directly. A serial resistor (RVSENSE) is required on this pin. See Section 4.22, “Supply Voltage Sense - VSENSE". In addition, the VS1 supply can be routed to the ADC (VS1SENSE) to measure the VS1 pin voltage directly. See Section 4.23, “Internal Supply Voltage Sense - VS1SENSE". To have an independent ADC verification, the internal sleep mode bandgap voltage can be routed to the ADC (BANDGAP). As this node is independent from the ADC reference, any out of range result would indicate malfunctioning ADC or Bandgap reference. See Section 4.24, “Internal Bandgap Reference Voltage Sense - BANDGAP". To stabilize the internal ADC reference voltage for higher precision measurements, the current limited ADC2p5 pin needs to be connected to an external filter capacitor (CADC2p5). It is not recommended to connect additional loads to this pin. See Section 4.19, “Analog Digital Converter - ADC". The following safety features are implemented: VSENSE VS1 LBI - Low Battery Interrupt, internally measured at VSENSE LVI - Low Voltage Interrupt, internally measured at VS1 HVI - High Voltage Interrupt, internally measured at VS2 VROVI - Voltage Regulator Overvoltage Interrupt internally measured at VDD and VDDX LVR - Low Voltage Reset, internally measured at VDD LVRX - Low Voltage Reset, internally measured at VDDX HTI - High Temperature Interrupt measured between the VDD and VDDX regulators Overtemperature Shutdown measured between the VDD and VDDX regulators VS2 • • • • • • • • LBI HVI HS1 HS2 ÷ HS1 & HS2 LVI ADC bg1p25sleep HSUP HSUP (18V) Regulator VDDX (5V) Regulator CHSUP VDDXINTERNAL VDDX LVRX VROV CVDDX ADC2p5 ADC 2.5V Reference VDD (2.5V) Regulator CADC VDD VDDINTERNAL LVR CVDD Figure 17. MM912F634 Power Supply MM912F634 54 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.4.1 Voltage Regulators VDD (2.5 V) & VDDX (5.0 V) To supply the MCU die and minor additional loads two cascaded voltage regulators have been implemented, VDDX (5.0 V) and VDD (2.5 V). External capacitors (CVDD) and (CVDDX) are required for proper regulation. 4.4.2 Power Up Behavior / Power Down Behavior To guarantee safe power up and down behavior, special dependencies are implemented to prevent unwanted MCU execution. Figure 18 shows a standard power up and power down sequence. MCU_POR MCU_POR RESET_A Normal Operating Range (not to scale) VLBI / VLVI VROVX 5V VLVRX VROX VLVR 4 1 5 2 VPOR_A VPOR_MCU 3 VSUP 6 VDDX VDD Figure 18. Power-up / Down Sequence To avoid any abnormal device behavior, it is essential to have the MCU Power on Reset (POR) block complete its start-up sequence before the analog die reset signal (RESET A) is asserted. Since the RESET A circuitry is supplied by VDDX, the voltage on the 2.5 V supply (VDD) needs to remain below the POR threshold whenever VDDX is too low to guarantee RESET A can be properly asserted (3;6). This is achieved with the following implementation. Power-up: • The VDD regulator is enabled after VDDX has reached the VLVRX threshold (1). • Once VDD reaches VLVR, the RESET_A is released (2). Power-down: • Once VDDX has reached the VLVRX threshold (4), the VDD regulator is disabled and the regulator output is actively pulled down to discharge any VDD capacitance (5). RESET_A is activated as well. • The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 55 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.4.3 Register Definition 4.4.3.1 Voltage Control Register (VCR) Table 74. Voltage Control Register (VCR) Offset(69) Access: User read/write 0x04 R 7 6 5 0 0 0 0 0 0 W Reset 4 3 2 1 0 VROVIE HTIE HVIE LVIE LBIE 0 0 0 0 0 Note: 69. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 75. VCR - Register Field Descriptions Field 4 VROVIE Description Voltage Regulator Overvoltage Interrupt Enable — Enables the interrupt for the Regulator Overvoltage Condition. 0 - Voltage Regulator Overvoltage Interrupt is disabled 1 - Voltage Regulator Overvoltage Interrupt is enabled 3 HTIE High Temperature Interrupt Enable — Enables the interrupt for the Voltage Regulator (VDD/VDDX) Temperature Warning. 0 - High Temperature Interrupt is disabled 1 - High Temperature Interrupt is enabled 2 HVIE High Voltage Interrupt Enable — Enables the interrupt for the VS2 - High Voltage Warning. 0 - High Voltage Interrupt is disabled 1 - High Voltage Interrupt is enabled 1 LVIE Low Voltage Interrupt Enable — Enables the interrupt for the VS1 - Low Voltage Warning. 0 - Low Voltage Interrupt is disabled 1 - Low Voltage Interrupt is enabled 0 LBIE Low Battery Interrupt Enable — Enables the interrupt for the VSENSE - Low Battery Voltage Warning. 0 - Low Battery Interrupt is disabled 1 - Low Battery Interrupt is enabled 4.4.3.2 Voltage Status Register (VSR) Table 76. Voltage Status Register (VSR) Offset(70) 0x05 R Access: User read 7 6 5 4 3 2 1 0 0 0 0 VROVC HTC HVC LVC LBC 0 0 0 0 0 0 0 0 W Reset Note: 70. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912F634 56 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION Table 77. VSR - Register Field Descriptions Field Description 4 VROVC Voltage Regulator Overvoltage Condition - This status bit indicates an overvoltage warning is present for at least one of the main voltage regulators (VDD or VDDX). Reading the register clears the VROVI flag if present. See Section 4.6, “Interrupts" for details. Note: This feature requires the trimming of Section 4.25.2.3, “Trimming Register 2 (CTR2)" to be done to be effective. Untrimmed devices may issue the VROVC condition including the LS turn off at normal operation. 0 - No Voltage Regulator Overvoltage Condition present. 1 - Voltage Regulator Overvoltage Condition present. 3 HTC High Temperature Condition - This status bit indicates a high temperature warning is present for the Voltage regulators (VDD/VDDX). Reading the register clears the HTI flag if present. See Section 4.6, “Interrupts" for details. 0 - No High Temperature Condition present. 1 - High Temperature Condition present. 2 HVC High Voltage Condition - This status bit indicates a high voltage warning for VS2 is present. Reading the register clears the HVI flag if present. See Section 4.6, “Interrupts" for details. 0 - No High Voltage Condition present. 1 - High Voltage Condition present. 1 LVC Low Voltage Condition - This status bit indicates a low voltage warning for VS1 is present. Reading the register clears the LVI flag if present. See Section 4.6, “Interrupts" for details. 0 - No Low Voltage Condition present. 1 - Low Voltage Condition present. 0 LBC Low Battery Condition - This status bit indicates a low voltage warning for VSENSE is present. Reading the register clears the LBI flag if present. See Section 4.6, “Interrupts" for details. 0 - No Low Battery Condition present. 1 - Low Battery Condition present. 4.5 Die to Die Interface - Target The D2D Interface is the bus interface to the Microcontroller. Access to the MM912F634 analog die is controlled by the D2D Interface module. This section describes the functionality of the die-to-die target block (D2D). 4.5.1 Overview The D2D is the target for a data transfer from the target to the initiator (MCU). The initiator provides a set of configuration registers and two memory mapped 256 Byte address windows. When writing to a window, a transaction is initiated sending a write command, followed by an 8-bit address, and the data byte or word is received from the initiator. When reading from a window, a transaction is received with the read command, followed by an 8-bit address. The target then responds with the data. The basic idea is that a peripheral located on the MM912F634 analog die, can be addressed like an on-chip peripheral. Features: • • • • • • • software transparent register access to peripherals on the MM912F634 analog die 256 Byte address window supports blocking read or write, as well as non-blocking write transactions 4 bit physical bus width automatic synchronization of the target when initiator starts driving the interface clock generates transaction and error status as well as EOT acknowledge providing single interrupt interface to D2D Initiator MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 57 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.5.2 Low Power Mode Operation The D2D module is disabled in SLEEP mode. In Stop mode, the D2DINT signal is used to wake-up a powered down MCU. As the MCU could wake up without the MM912F634 analog die, a special command is recognized as a wake-up event during Stop mode. See Section 4.3, “Modes of Operation". 4.5.2.1 Normal Mode / Stop Mode NOTE The maximum allowed clock speed of the interface is limited to fD2D. While in Normal or Stop mode, D2DCLK acts as input only with pull present. D2D[3:0] operates as an input/output with pull-down always present. D2DINT acts as output only. 4.5.2.2 Sleep Mode While in Sleep mode, all Interface data pins are pulled down to DGND to reduce power consumption. 4.6 Interrupts Interrupts are used to signal a microcontroller that a peripheral needs to be serviced. While in Stop mode, the interrupt signal is used to signal Wake-up events. The interrupts are signaled by an active high level of the D2DINT pin, which remains high until the interrupt is acknowledged via the D2D-Interface. Interrupts are only asserted while in Normal mode. 4.6.1 Interrupt Source Identification Once an Interrupt is signalized, there are two options to identify the corresponding source(s). 4.6.1.1 Interrupt Source Mirror NOTE The VSI - Voltage Status Interrupt combines the five status flags for the Low Battery Interrupt, Low Voltage Interrupt, High Voltage Interrupt, Voltage Regulator Overvoltage Interrupt, and the Voltage Regulator High Temperature Interrupt. The specific source can be identified by reading the Voltage Status Register - VSR. All Interrupt sources in MM912F634 analog die are mirrored to a special Interrupt Source Register (ISR). This register is read only and indicates all currently pending Interrupts. Reading this register does not acknowledge any interrupt. An additional D2D access is necessary to serve the specific module. 4.6.1.1.1 Interrupt Source Register (ISR) Table 78. Interrupt Source Register (ISR) Offset(71) 0x00 (0x00 and 0x01 for 8Bit access) R Access: User read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 HOT LSOT HSOT LINOT SCI RX TX ERR TOV CH3 CH2 CH1 CH0 VSI W Note: 71. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912F634 58 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION Table 79. ISR - Register Field Descriptions Field Description 0 - VSI VSI - Voltage Status Interrupt combining the following sources: • Low Battery Interrupt • Low Voltage Interrupt • High Voltage Interrupt • Voltage Regulator Overvoltage Interrupt • Voltage Regulator High Temperature Interrupt 1 - CH0 CH0 - TIM Channel 0 Interrupt 2 - CH1 CH1 - TIM Channel 1 Interrupt 3 - CH2 CH2 - TIM Channel 2 Interrupt 4 - CH3 CH3 - TIM Channel 3 Interrupt 5 - TOV TOV - Timer Overflow Interrupt 6 - ERR ERR - SCI Error Interrupt 7 - TX TX - SCI Transmit Interrupt 8 - RX RX - SCI Receive Interrupt 9 - SCI SCI - ADC Sequence Complete Interrupt 10 - LINOT LINOT - LIN Driver Overtemperature Interrupt 11 - HSOT HSOT - High-side Overtemperature Interrupt 12 - LSOT LSOT - Low-side Overtemperature Interrupt 13 - HOT HOT - HSUP Overtemperature Interrupt 4.6.1.2 Interrupt Vector Emulation by Priority To allow a vector based interrupt handling by the MCU, the number of the highest prioritized interrupt pending is returned in the Interrupt Vector Register. To allow an offset based vector table, the result is pre-shifted (multiple of 2). Reading this register does not acknowledge an interrupt. An additional D2D access is necessary to serve the specific module. 4.6.1.2.1 Interrupt Vector Register (IVR) Table 80. Interrupt Vector Register (IVR) Offset(72) 0x02 R Access: User read 7 6 0 0 5 4 3 2 1 0 IRQ W Note: 72. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 81. IVR - Register Field Descriptions Field 5:0 IRQ Description Represents the highest prioritized interrupt pending. See Table 82 In case no interrupt is pending, the result is 0. The following table is listing all MM912F634 analog die interrupt sources with the corresponding priority. MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 59 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION Table 82. Interrupt Source Priority Interrupt Source IRQ Priority no interrupt pending or wake-up from Stop mode 0x00 1 (highest) LVI - Low Voltage Interrupt 0x02 2 HTI - Voltage Regulator High Temperature Interrupt 0x04 3 LBI - Low Battery Interrupt 0x06 4 CH0 - TIM Channel 0 Interrupt 0x08 5 CH1 - TIM Channel 1 Interrupt 0x0A 6 CH2 - TIM Channel 2 Interrupt 0x0C 7 CH3 - TIM Channel 3 Interrupt 0x0E 8 TOV - Timer Overflow Interrupt 0x10 9 ERR - SCI Error Interrupt 0x12 10 TX - SCI Transmit Interrupt 0x14 11 RX - SCI Receive Interrupt 0x16 12 SCI - ADC Sequence Complete Interrupt 0x18 13 LINOT - LIN Driver Overtemperature Interrupt 0x1A 14 HSOT - High-side Overtemperature Interrupt 0x1C 15 LSOT - Low-side Overtemperature Interrupt 0x1E 16 HOT - HSUP Overtemperature Interrupt 0x20 17 HVI - High Voltage Interrupt 0x22 18 VROVI - Voltage Regulator Overvoltage Interrupt 0x24 19 (lowest) 4.6.2 4.6.2.1 Interrupt Sources Voltage Status Interrupt (VSI) The Voltage Status Interrupt - VSI combines the five interrupt sources of the Voltage Status Register. It is only available in the Interrupt Source Register (ISR). Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.2 Low Voltage Interrupt (LVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.3 Voltage Regulator High Temperature Interrupt (HTI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.4 Low Battery Interrupt (LBI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.5 TIM Channel 0 Interrupt (CH0) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". MM912F634 60 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.6.2.6 TIM Channel 1 Interrupt (CH1) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". 4.6.2.7 TIM Channel 2 Interrupt (CH2) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". 4.6.2.8 TIM Channel 3 Interrupt (CH3) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". 4.6.2.9 TIM Timer Overflow Interrupt (TOV) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". 4.6.2.10 SCI Error Interrupt (ERR) See Section 4.15, “Serial Communication Interface (S08SCIV4)". 4.6.2.11 SCI Transmit Interrupt (TX) See Section 4.15, “Serial Communication Interface (S08SCIV4)". 4.6.2.12 SCI Receive Interrupt (RX) See Section 4.15, “Serial Communication Interface (S08SCIV4)". 4.6.2.13 LIN Driver Overtemperature Interrupt (LINOT) Acknowledge the interrupt by reading the LIN Register - LINR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.14, “LIN Physical Layer Interface - LIN" for details on the LIN Register including masking information. 4.6.2.14 High-side Overtemperature Interrupt (HSOT) Acknowledge the interrupt by reading the High-side Status Register - HSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.11, “High-side Drivers - HS" for details on the High-side Status Register including masking information. 4.6.2.15 Low-side Overtemperature Interrupt (LSOT) Acknowledge the interrupt by reading the Low-side Status Register - LSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.12, “Low-side Drivers - LSx" for details on the Low-side Status Register including masking information. 4.6.2.16 HSUP Overtemperature Interrupt (HOT) Acknowledge the interrupt by reading the Hall Supply Register - HSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.10, “Hall Sensor Supply Output - HSUP" for details on the Hall Supply Register including masking information. 4.6.2.17 High Voltage Interrupt (HVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.18 Voltage Regulator Overvoltage Interrupt (VROVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 61 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.7 Resets To protect the system during critical events, the MM912F634 analog die drives the RESET_A pin low during the presence of the reset condition. In addition, the RESET_A pin is monitored for external reset events. To match the MCU, the RESET_A pin is based on the VDDX voltage level. After an internal reset condition has gone, the RESET_A stays low for an additional time tRST before being released. Entering reset mode causes all MM912F634 analog die registers to be initialized to their RESET default. The only registers with valid information are the Reset Status Register (RSR) and the Wake-up Source Register (WUS). 4.7.1 Reset Sources In the MM912F634 six reset sources exist. 4.7.1.1 POR - Analog Die Power On Reset To indicate the device power supply (VS1) was below VPOR or the MM912F634 analog die was powered up, the POR condition is set. See Section 4.3, “Modes of Operation". 4.7.1.2 LVR - Low Voltage Reset - VDD With the VDD voltage regulator output voltage falling below VLVR, the Low Voltage Reset condition becomes present. As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. See Section 4.4, “Power Supply". 4.7.1.3 LVRX - Low Voltage Reset - VDDX With the VDDX voltage regulator output voltage falling below VLVRX, the Low Voltage Reset condition becomes present. See Section 4.4, “Power Supply". 4.7.1.4 WUR - Wake-up Reset While in Sleep mode, any active wake-up event causes a MM912F634 analog die transition from Sleep to Reset Mode. To determine the wake-up source, refer to Section 4.8, “Wake-up / Cyclic Sense". 4.7.1.5 EXR - External Reset Any low level voltage at the RESET_A pin with a duration > tRSTDF issues an External Reset event. This reset source is also active in Stop mode. 4.7.1.6 WDR - Watchdog Reset Any incorrect serving if the MM912F634 analog die Watchdog results in a Watchdog Reset. Refer to the Section 4.9, “Window Watchdog" for details. 4.7.2 Register Definition 4.7.2.1 Reset Status Register (RSR) Table 83. Reset Status Register (RSR) Offset(73) 0x15 R Access: User read 7 6 5 4 3 2 1 0 0 0 WDR EXR WUR LVRX LVR POR W Note: 73. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912F634 62 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION Table 84. RSR - Register Field Descriptions Field Description 5 - WDR Watchdog Reset - Reset caused by an incorrect serving of the watchdog. 4 - EXR External Reset - Reset caused by the RESET_A pin driven low externally for > tRSTDF 3 - WUR Wake-up Reset - Reset caused by a wake-up from Sleep mode. To determine the wake-up source, refer to Section 4.8, “Wake-up / Cyclic Sense". 2 - LVRX Low Voltage Reset VDDX - Reset caused by a low voltage condition monitored at the VDDX output. 1 - LVR Low Voltage Reset VDD - Reset caused by a low voltage condition monitored at the VDD output.(74) 0 - POR Power On Reset - Supply Voltage was below VPOR. Note: 74. As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. Reading the Reset Status register clears the information inside. Writing has no effect. LVR and LVRX are masked when POR or WUR are set. 4.8 Wake-up / Cyclic Sense To wake-up the MM912F634 analog die from Stop or Sleep mode, several wake-up sources are implemented. As described in Section 4.3, “Modes of Operation", a wake-up from Stop mode results in an interrupt (D2DINT) to the MCU combined with a transition to Normal mode. A wake-up from Sleep mode results in a transition to Reset mode. In any case, the source of the wake-up can be identified by reading the Wake-up Source Register (WSR). The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between the WSR read and MCR write. In general, there are the following seven main wake-up sources: • • • • • • • Wake-up by a state change of one of the Lx inputs Wake-up by a state change of one of the Lx inputs during a cyclic sense Wake-up due to a forced wake-up Wake-up by the LIN module Wake-up by D2D interface (Stop mode only) Wake-up due to internal / external Reset (Stop mode only) Wake-up due to loss of supply voltage (Sleep mode only) VSUP HS1 HS2 D2DINT Wake Up Module D2DCLK D2D3 D2D2 Forced Wake Up Cyclic Sense / Forced Wake Up Timer D2D Wake Up L0 L1 L2 D2D1 L3 D2D0 Cyclic Wake Up Lx – Wake Up LIN Wake Up L4 L5 LIN LIN Bus Figure 19. Wake-up Sources MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 63 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.8.1 4.8.1.1 Wake-up Sources Lx - Wake-up (Cyclic Sense Disabled) Any state digital change on a Wake-up Enabled Lx input issues a wake-up. In order to select and activate a Wake-up Input (Lx), the Wake-up Control Register (WCR) must be configured with appropriate LxWE inputs enabled or disabled before entering low power mode. The Lx - Wake-up may be combined with the Forced Wake-up. Note: Selecting a Lx Input for wake-up disables a selected analog input once entering low power mode. 4.8.1.2 Lx - Cyclic Sense Wake-up NOTE Once Cyclic Sense is configured (CSSEL!=0), the state change is only recognized from one cyclic sense event to the next. The additional accuracy of the cyclic sense cycle by the WD clock trimming is only active during STOP mode. There is no trimmed clock available during SLEEP mode. To reduce external power consumption during low power mode a cyclic wake-up has been implemented. Configuring the Timing Control Register (TCR) a specific cycle time can be selected to implement a periodic switching of the HS1 or HS2 output with the corresponding detection of an Lx state change. Any configuration of the HSx in the High-side Control Register (HSCR) is ignored when entering low power mode. The Lx - Cyclic Sense Wake-up may be combined with the Forced Wake-up. In case both (forced and Lx change) events are present at the same time, the Forced Wake-up is indicated as Wake-up source. 4.8.1.3 Forced Wake-up Configuring the Forced Wake-up Multiplier (FWM) in the Timing Control Register (TCR) enables the forced wake-up based on the selected Cyclic Sense Timing (CST). Forced Wake-up can be combined with all other wake-up sources considering the timing dependencies. 4.8.1.4 LIN - Wake-up While in Low-Power mode the MM912F634 analog die monitors the activity on the LIN bus. A dominant pulse longer than tPROPWL followed by a dominant to recessive transition causes a LIN Wake-up. This behavior protects the system from a short-to-ground bus condition. 4.8.1.5 D2D - Wake-up (Stop Mode Only) Receiving a Normal mode request via the D2D interface (MODE=0, Mode Control Register (MCR)) results in a wake-up from stop mode. As this condition is controlled by the MCU, no wake-up status bit does indicate this wake-up source. 4.8.1.6 Wake-up Due to Internal / External Reset (STOP Mode Only) While in Stop mode, a Reset due to a VDD low voltage condition or an external Reset applied on the RESET_A pin results in a Wake-up with immediate transition to Reset mode. In this case, the LVR or EXR bits in the Reset Status Register indicates the source of the event. 4.8.1.7 Wake-up Due to Loss of Supply Voltage (SLEEP Mode Only) While in Sleep mode, a supply voltage VS1 < VPOR results in a transition to Power On mode. MM912F634 64 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 4.8.2 Register Definition 4.8.2.1 Wake-up Control Register (WCR) Table 85. Wake-up Control Register (WCR) Offset(75) 0x12 Access: User read/write 7 R CSSEL W Reset 6 0 0 5 4 3 2 1 0 L5WE L4WE L3WE L2WE L1WE L0WE 1 1 1 1 1 1 Note: 75. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 86. WCR - Register Field Descriptions Field Description 7-6 CSSEL Cyclic Sense Select - Configures the HSx output for the cyclic sense event. Note, with no LxWE selected - only the selected HSx output is switched periodically, no Lx state change would be detected. For all configurations, the Forced Wake-up can be activated in parallel in Section 4.8.2.2, “Timing Control Register (TCR)" 00 - Cyclic Sense Off 01 - Cyclic Sense with periodic HS1on 10 - Cyclic Sense with periodic HS2 on 11 - Cyclic Sense with periodic HS1 and HS2 on. 5 - L5WE Wake-up Input 5 Enabled - L5 Wake-up Select Bit. 0 - L5 Wake-up Disabled 1 - L5 Wake-up Enabled 4 - L4WE Wake-up Input 4 Enabled - L4 Wake-up Select Bit. 0 - L4 Wake-up Disabled 1 - L4 Wake-up Enabled 3 - L3WE Wake-up Input 3 Enabled - L3 Wake-up Select Bit. 0 - L3Wake-up Disabled 1 - L3 Wake-up Enabled 2- L2WE Wake-up Input 2 Enabled - L2 Wake-up Select Bit. 0 - L2 Wake-up Disabled 1 - L2 Wake-up Enabled 1 - L1WE Wake-up Input 1 Enabled - L1 Wake-up Select Bit. 0 - L1 Wake-up Disabled 1 - L1 Wake-up Enabled 0 - L0WE Wake-up Input 0 Enabled - L0 Wake-up Select Bit. 0 - L0 Wake-up Disabled 1 - L0 Wake-up Enabled 4.8.2.2 Timing Control Register (TCR) Table 87. Timing Control Register (TCR) Offset(76) 0x13 Access: User read/write 7 6 R 4 3 2 FWM W Reset 5 0 0 1 0 0 0 CST 0 0 0 0 Note: 76. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912F634 Analog Integrated Circuit Device Data Freescale Semiconductor 65 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION Table 88. TCR - Register Field Descriptions Field Description 7-4 FWM Forced Wake-up Multiplicator - Configures the multiplicator for the forced wake-up. The selected multiplicator (FWM!=0) forces a wake-up every FWM x CST ms. With this implementation, Forced and Cyclic wake-up can be performed in parallel with the cyclic sense period