MMPF0100F1AEP

NXP Semiconductors Data sheet: Technical Data Document Number: MMPF0100 Rev. 20, 5/2022 14 channel configurable power management integrated circuit PF0100 The PF0100 SMARTMOS power management integrated circuit (PMIC) provides a highly programmable/ configurable architecture, with fully integrated power devices and minimal external components. With up to six buck converters, six linear regulators, RTC supply, and coin-cell charger, the PF0100 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip one time programmable (OTP) memory, the PF0100 is available in pre-programmed standard versions, or non-programmed to support custom programming. The PF0100 is defined to power an entire embedded MCU platform solution such as i.MX 6 based eReader, IPTV, medical monitoring, and home/factory automation. Features: • Four to six buck converters, depending on configuration • Single/Dual phase/ parallel options • DDR termination tracking mode option • Boost regulator to 5.0 V output • Six general purpose linear regulators • Programmable output voltage, sequence, and timing • OTP (one time programmable) memory for device configuration • Coin cell charger and RTC supply • DDR termination reference voltage • Power control logic with processor interface and event detection • I2C control • Individually programmable ON, OFF, and standby modes PF0100 POWER MANAGEMENT EP SUFFIX (E-TYPE) 98ASA00405D 56 QFN 8X8 Applications: • Tablets • IPTV • eReaders • Set top boxes • Industrial control • Medical monitoring • Home automation/ alarm/ energy management i.MX 6X VREFDDR SW4 1000 mA DDR MEMORY INTERFACE DDR Memory SW3A/B 2500 mA SW1A/B 2500 mA Processor Core Voltages SW1C 2000 mA SW2 2000 mA SWBST 600 mA SD-MMC/ NAND Mem. SATA HDD Parallel control/GPIOS I2 C Communication I2C Communication VGEN2 250 mA VGEN3 100 mA VGEN4 350 mA Camera COINCELL Sensors Camera USB Ethernet CAN Cluster/HUD Front USB POD Rear Seat Infotaiment Figure 1. Simplified application diagram © NXP B.V. 2022. Audio Codec HDMI LDVS Display VGEN6 200 mA Main Supply 2.8 – 4.5 V External AMP Microphones Speakers GPS MIPI uPCIe WAM GPS MIPI VGEN5 100 mA LICELL Charger SATA - FLASH NAND - NOR Interfaces Control Signals VGEN1 100 mA ES SUFFIX (WF-TYPE) 98ASA00589D 56 QFN 8X8 Rear USB POD Table of Contents 1 2 3 4 5 6 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3.1 General specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.2 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.1 Device start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.2 One time programmability (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.3 OTP prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.4 Reading OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.5 Programming OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.1 Clock adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3.1 Internal core voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3.2 VREFDDR voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4.2 State machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.3 Power tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.4 Buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.5 Boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.6 LDO regulators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.4.7 VSNVS LDO/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.5.1 I2C device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.5.2 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.5.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.5.4 Interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.5.5 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.5.6 Register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PF0100 2 NXP Semiconductors 7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 PF0100 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 General routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 Parallel routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.5 Switching regulator layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 118 118 119 123 123 123 123 123 124 125 125 125 126 126 134 134 135 PF0100 NXP Semiconductors 3 ORDERABLE PARTS 1 Orderable parts The PF0100 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device uses “NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 10. Table 1. Orderable Part Variations Part Number Temperature (TA) Package Programming Reference Designs MMPF0100NPAEP NP N/A MMPF0100F0AEP F0 MCIMX6Q-SDP MCIMX6Q-SDB MCIMX6DL-SDP F1 MCIMX6SLEVK F2 N/A F3 N/A MMPF0100F4AEP F4 N/A MMPF0100F6AEP F6 MCIMX6SX-SDB MMPF0100FCAEP FC N/A MMPF0100FDAEP FD MCIMX6SLLEVK MMPF0100NPANES NP N/A MMPF0100F0ANES F0 MCIMX6Q-SDP MCIMX6Q-SDB MCIMX6DL-SDP MMPF0100F3ANES F3 N/A F4 N/A F6 MCIMX6SX-SDB MMPF0100F9ANES F9 N/A MMPF0100FAANES FA N/A MMPF0100FBANES FB N/A MMPF0100FCANES FC N/A MMPF0100F1AEP MMPF0100F2AEP MMPF0100F3AEP MMPF0100F4ANES MMPF0100F6ANES -40 °C to 85 °C (for use in consumer applications) -40 °C to 105 °C (for use in extended industrial applications) 56 QFN 8x8 mm - 0.5 mm pitch E-Type QFN (full lead) 56 QFN 8x8 mm - 0.5 mm pitch WF-Type QFN (wettable flank) Notes (1), (2) (1), (2), (3) (1), (2) (1), (2) (1), (2), (4) (1), (2) (1), (2), (4) (1), (2) Notes 1. For tape and reel, add an R2 suffix to the part number. 2. For programming details see Table 10. The available OTP options are not restricted to the listed reference designs. They can be used in any application where the listed voltage and sequence details are acceptable. 3. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option instead of the F2 OTP option. 4. SW2 can support an output current rating of 2.5 A in NP, F9, and FA Industrial versions only (ANES suffix) when SW2ILIM=0 PF0100 4 NXP Semiconductors ORDERABLE PARTS 1.1 PF0100 version differences PF0100A is an improved version of the PF0100 power management IC. Table 2 summarizes the difference between the two versions and should be referred to when migrating from the PF0100 to the PF0100A. Note that programming options are the same for both versions of the device. Table 2. Differences between PF0100 and PF0100A Description PF0100 PF0100A Version identification Reading SILICON REV register at address 0x03 returns 0x11. DEVICEID register at address 0x00 reads 0x10 in PF0100 and PF0100A Reading SILICON REV register at address 0x03 returns 0x21. DEVICEID register at address 0x00 reads 0x10 in PF0100 and PF0100A VSNVS current limit VSNVS current limit increased in the PF0100A In the PF0100A, the XOR function is removed. It is In the PF0100, FUSE_POR1, FUSE_POR2, and required to set FUSE_POR1, FUSE_POR2, and FUSE_POR3 bits are XOR’ed into the FUSE_POR3 bits during OTP programming. OTP_FUSE_PORx register setting during OTP FUSE_POR_XOR bit. The FUSE_POR_XOR bit has to be 1 for fuses to be loaded during startup. programming This can be achieved by setting any one or all of the FUSE_PORx bits during OTP programming. Erratum ER19 Erratum ER19 applicable to PF0100. Applications Errata ER19 fixed in PF0100A. External expecting to operate in the conditions mentioned in workaround not required ER19 need to implement an external workaround to overcome the problem. Refer to the product errata for details Erratum ER20 Erratum ER20 applicable to PF0100 Errata ER20 fixed in PF0100A Erratum ER22 Erratum ER22 applicable to PF0100 Errata ER22 fixed in PF0100A. Workaround not required In addition to the version differences, Table 3 shows the differences on the test temperature rating for each version of PF0100 covered on this datasheet. Table 3. Ambient temperature range Device Qualification tier Ambient temperature range (TMIN to TMAX) MMPF0100 Consumer and Industrial TA = -40 °C to 85 °C MMPF0100A Consumer TA = -40 °C to 85 °C MMPF0100AN Extended Industrial TA = -40 °C to 105 °C PF0100 NXP Semiconductors 5 INTERNAL BLOCK DIAGRAM 2 Internal block diagram PF0100 VGEN1 100 mA VIN1 VGEN1 SW1FB SW1A/B Single/Dual 2500 mA Buck VGEN2 250 mA VGEN2 VIN2 VGEN3 VGEN3 100 mA VGEN4 VGEN4 350 mA SW1C 2000 mA Buck O/P Drive O/P Drive SW1BLX O/P Drive SW1CLX Initialization State Machine SW2 2000 mA Buck VGEN6 200 mA VGEN6 SW1CIN SW1VSSSNS VGEN5 100 mA VGEN5 SW1BIN SW1CFB Core Control logic VIN3 SW1AIN SW1ALX O/P Drive SW2LX SW2IN SW2IN SW2FB Supplies Control OTP SW3AFB VDDOTP CONTROL I2C Interface VDDIO SCL SDA SW3A/B Single/Dual DDR 2500 mA Buck O/P Drive O/P Drive DVS CONTROL SW3AIN SW3ALX SW3BLX SW3BIN SW3BFB DVS Control SW3VSSSNS SW4FB 2 Trim-In-Package I C Register map VCOREDIG VCOREREF O/P Drive SW4IN SW4LX GNDREF1 Reference Generation VCORE SW4 1000 mA Buck Clocks and resets SWBST 600 mA Boost O/P Drive SWBSTLX SWBSTIN GNDREF SWBSTFB VREFDDR VINREFDDR Clocks 32 kHz and 16 MHz VHALF VIN Li Cell Charger LICELL Best of Supply INTB SDWNB STANDBY RESETBMCU ICTEST PWRON VSNVS VSNVS Figure 2. Simplified internal block diagram PF0100 6 NXP Semiconductors PIN CONNECTIONS SDA VCOREREF VCOREDIG VIN VCORE GNDREF VDDOTP SWBSTLX SWBSTIN SWBSTFB VSNVS Pinout diagram SCL 3.1 VDDIO Pin connections PWRON 3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 INTB 1 42 LICELL SDWNB 2 41 VGEN6 RESETBMCU 3 40 VIN3 STANDBY 4 39 VGEN5 ICTEST 5 38 SW3AFB SW1FB 6 37 SW3AIN SW1AIN 7 36 SW3ALX SW1ALX 8 35 SW3BLX SW1BLX 9 34 SW3BIN SW1BIN 10 33 SW3BFB SW1CLX 11 32 SW3VSSSNS SW1CIN 12 31 VREFDDR SW1CFB 13 30 VINREFDDR SW1VSSSNS 14 29 VHALF 24 25 26 27 28 VGEN4 SW4FB 23 VIN2 VGEN2 22 VGEN3 VIN1 21 SW2FB VGEN1 20 SW2IN 19 SW2IN 18 SW2LX 17 SW4LX 16 SW4IN 15 GNDREF1 EP Figure 3. Pinout diagram PF0100 NXP Semiconductors 7 PIN CONNECTIONS 3.2 Pin definitions Table 4. PF0100 pin definitions Pin number Pin name Pin function Max rating Type 1 INTB O 3.6 V Digital Open drain interrupt signal to processor 2 SDWNB O 3.6 V Digital Open drain signal to indicate an imminent system shutdown 3 RESETBMCU O 3.6 V Digital Open drain reset output to processor. Alternatively can be used as a power good output. 4 STANDBY I 3.6 V Digital Standby input signal from processor 5 ICTEST I 7.5 V Digital/ Analog Reserved pin. Connect to GND in application. 6 SW1FB (6) I 3.6 V Analog Output voltage feedback for SW1A/B. Route this trace separately from the high current path and terminate at the output capacitance. 7 SW1AIN (6) I 4.8 V Analog Input to SW1A regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 8 SW1ALX (6) O 4.8 V Analog Regulator 1A switch node connection 9 SW1BLX (6) O 4.8 V Analog Regulator 1B switch node connection 10 SW1BIN (6) I 4.8 V Analog Input to SW1B regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 11 SW1CLX (6) O 4.8 V Analog Regulator 1C switch node connection 12 SW1CIN (6) I 4.8 V Analog Input to SW1C regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 13 SW1CFB (6) I 3.6V Analog Output voltage feedback for SW1C. Route this trace separately from the high current path and terminate at the output capacitance. 14 SW1VSSSNS GND - GND Ground reference for regulators SW1ABC. It is connected externally to GNDREF through a board ground plane. 15 GNDREF1 GND - GND Ground reference for regulators SW2 and SW4. It is connected externally to GNDREF, via board ground plane. 16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor. 17 VIN1 I 3.6 V Analog VGEN1, 2 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. 18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor. 19 SW4FB (6) I 3.6 V Analog Output voltage feedback for SW4. Route this trace separately from the high current path and terminate at the output capacitance. 20 SW4IN (6) I 4.8 V Analog Input to SW4 regulator. Bypass with at least a 4.7μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 21 SW4LX (6) O 4.8 V Analog Regulator 4 switch node connection 22 SW2LX (6) O 4.8 V Analog Regulator 2 switch node connection 23 SW2IN (6) I 4.8 V Analog 24 SW2IN (6) I 4.8 V Analog Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to these pins as possible. 25 SW2FB (6) I 3.6 V Analog Output voltage feedback for SW2. Route this trace separately from the high current path and terminate at the output capacitance. 26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 27 VIN2 I 3.6 V Analog VGEN3,4 input. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. 28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor. Definition PF0100 8 NXP Semiconductors PIN CONNECTIONS Table 4. PF0100 pin definitions (continued) Pin number Pin name Pin function Max rating Type 29 VHALF I 3.6 V Analog Half supply reference for VREFDDR 30 VINREFDDR I 3.6 V Analog VREFDDR regulator input. Bypass with at least 1.0 μF decoupling capacitor as close to the pin as possible. 31 VREFDDR O 3.6 V Analog VREFDDR regulator output 32 SW3VSSSNS GND - GND Ground reference for the SW3 regulator. Connect to GNDREF externally via the board ground plane. 33 SW3BFB (6) I 3.6 V Analog Output voltage feedback for SW3B. Route this trace separately from the high current path and terminate at the output capacitance. 34 SW3BIN (6) I 4.8 V Analog Input to SW3B regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 35 SW3BLX (6) O 4.8 V Analog Regulator 3B switch node connection 36 SW3ALX (6) O 4.8 V Analog Regulator 3A switch node connection 37 SW3AIN (6) I 4.8 V Analog Input to SW3A regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 38 SW3AFB (6) I 3.6 V Analog Output voltage feedback for SW3A. Route this trace separately from the high current path and terminate at the output capacitance. 39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 40 VIN3 I 4.8 V Analog VGEN5, 6 input. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. 41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor. 42 LICELL I/O 3.6 V Analog Coin cell supply input/output 43 VSNVS O 3.6 V Analog LDO or coin cell output to processor 44 SWBSTFB (6) I 5.5 V Analog Boost regulator feedback. Connect this pin to the output rail close to the load. Keep this trace away from other noisy traces and planes. 45 SWBSTIN (6) I 4.8 V Analog Input to SWBST regulator. Bypass with at least a 2.2 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 46 SWBSTLX (6) O 7.5 V Analog SWBST switch node connection 47 VDDOTP I 10 V(5) 48 GNDREF GND - GND 49 VCORE O 3.6 V Analog Analog Core supply 50 VIN I 4.8 V Analog Main chip supply 51 VCOREDIG O 1.5 V Analog Digital Core supply 52 VCOREREF O 1.5 V Analog Main band gap reference 53 SDA I/O 3.6 V Digital I2C data line (Open drain) 54 SCL I 3.6 V Digital I2C clock 55 VDDIO I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 μF ceramic capacitor 56 PWRON I 3.6 V Digital Power On/off from processor - EP GND - GND Expose pad. Functions as ground return for buck regulators. Tie this pad to the inner and external ground planes through vias to allow effective thermal dissipation. Definition Digital and Supply to program OTP fuses Analog Ground reference for the main band gap regulator. Notes 5. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise. 6. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be connected to VIN with a 0.1 μF bypass capacitor. PF0100 NXP Semiconductors 9 GENERAL PRODUCT CHARACTERISTICS 4 General product characteristics 4.1 Absolute maximum ratings Table 5. Absolute maximum ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section. Symbol Description Value Unit Main input supply voltage -0.3 to 4.8 V VDDOTP OTP programming input supply voltage -0.3 to 10 V VLICELL Coin cell voltage -0.3 to 3.6 V ±2000 ±500 V Notes Electrical ratings VIN VESD ESD ratings Human body model Charge device model (7) Notes 7. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM), robotic (CZAP = 4.0 pF). PF0100 10 NXP Semiconductors GENERAL PRODUCT CHARACTERISTICS 4.2 Thermal characteristics Table 6. Thermal ratings Symbol Description (rating) Min. Max. Unit Notes TA Ambient operating temperature range • PF0100 • PF0100A • PF0100AN -40 -40 -40 85 85 105 TJ Operating junction temperature range -40 125 °C Storage temperature range -65 150 °C – Note 10 °C (9)(10) Junction to ambient • Natural convection • Four layer board (2s2p) • Eight layer board (2s6p) – – 28 15 °C/W (11)(12)(13) Junction to ambient (@200 ft/min) • Four layer board (2s2p) – 22 °C/W (11)(13) Junction to board – 10 °C/W (14) RΘJCBOTTOM Junction to case bottom – 1.2 °C/W (15) ΨJT Junction to package top • Natural convection – 2.0 °C/W (16) Thermal ratings TST TPPRT Peak package reflow temperature °C (8) QFN56 thermal resistance and package dissipation ratings RθJA RθJMA RθJB Notes 8. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 7 for thermal protection features. 9. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 10. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics. 11. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 12. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5. 13. Per JEDEC JESD51-6 with the board horizontal. 14. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 15. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 16. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD512. When Greek letter (Ψ) are not available, the thermal characterization parameter is written as Psi-JT. 4.2.1 Power dissipation During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 6. To optimize the thermal management and to avoid overheating, the PF0100 provides thermal protection. An internal comparator monitors the die temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I are generated when the respective thresholds specified in Table 7 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register INTSENSE0. In the event of excessive power dissipation, thermal protection circuitry shuts down the PF0100. This thermal protection acts above the thermal protection threshold listed in Table 7. To avoid any unwanted power downs resulting from internal noise, the protection is debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured so protection is not tripped under normal conditions. PF0100 NXP Semiconductors 11 GENERAL PRODUCT CHARACTERISTICS Table 7. Thermal protection thresholds Parameter Min. Typ. Max. Units Thermal 110 °C Threshold (THERM110) 100 110 120 °C Thermal 120 °C Threshold (THERM120) 110 120 130 °C Thermal 125 °C Threshold (THERM125) 115 125 135 °C Thermal 130 °C Threshold (THERM130) 120 130 140 °C Thermal Warning Hysteresis 2.0 – 4.0 °C Thermal Protection Threshold 130 140 150 °C 4.3 Electrical characteristics 4.3.1 General specifications Table 8. General PMIC static characteristics. TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external component values and full load current range, unless otherwise noted. Pin name PWRON RESETBMCU SCL SDA INTB SDWNB STANDBY VDDOTP Parameter Load condition Min. Max. Unit VIL – 0.0 0.2 * VSNVS V VIH – 0.8 * VSNVS 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V VIL – 0.0 0.2 * VDDIO V VIH – 0.8 * VDDIO 3.6 V VIL – 0.0 0.2 * VDDIO V VIH – 0.8 * VDDIO 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7*VDDIO VDDIO V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V VIL – 0.0 0.2 * VSNVS V VIH – 0.8 * VSNVS 3.6 V VIL – 0.0 0.3 V VIH – 1.1 1.7 V PF0100 12 NXP Semiconductors GENERAL PRODUCT CHARACTERISTICS 4.3.2 Current consumption Table 9. Current consumption summary TMIN to TMAX (See Table 3), VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V, VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted. Mode PF0100 conditions System conditions Typical MAX Unit Notes Coin Cell VSNVS from LICELL All other blocks off VIN = 0.0 V VSNVSVOLT[2:0] = 110 No load on VSNVS 4.0 7.0 μA (17),(19), (23) Off MMPF0100 VSNVS from VIN or LICELL Wake-up from PWRON active 32 k RC on All other blocks off VIN ≥ UVDET No load on VSNVS, PMIC able to wake-up 16 21 μA (18),(19) Off MMPF0100A VSNVS from VIN or LICELL Wake-up from PWRON active 32 k RC on All other blocks off VIN ≥ UVDET No load on VSNVS, PMIC able to wake-up 17 25 μA (18),(19) No load on VSNVS. DDR memories in self refresh 122 220(22) Sleep VSNVS from VIN Wake-up from PWRON active Trimmed reference active SW3A/B PFM Trimmed 16 MHz RC off 32 k RC on VREFDDR disabled (19) 250(21) μA 122 Standby MMPF0100 VSNVS from either VIN or LICELL SW1A/B combined in PFM SW1C in PFM SW2 in PFM SW3A/B combined in PFM SW4 in PFM SWBST off Trimmed 16 MHz RC enabled Trimmed reference active VGEN1-6 enabled VREFDDR enabled No load on VSNVS. Processor enabled in low power mode. All rails powered on except boost (load = 0 mA) 297 450 (20) (19) 1000 (22) μA 297 Standby MMPF0100A VSNVS from either VIN or LICELL SW1A/B combined in PFM SW1C in PFM SW2 in PFM SW3A/B combined in PFM SW4 in PFM SWBST off Trimmed 16 MHz RC enabled Trimmed reference active VGEN1-6 enabled VREFDDR enabled No load on VSNVS. Processor enabled in low power mode. All rails powered on except boost (load = 0 mA) 297 450 (22) (19) 550(21) μA 297 Notes 17. Refer to Figure 4 for coin cell mode characteristics over temperature. 18. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically. 19. 20. 21. 22. 23. For PFM operation, headroom should be 300 mV or greater. From 0 °C to 85 °C From -40 °C to 105 °C, applicable only to extended industrial parts. From -40 °C to 85 °C, applicable to consumer, industrial and extended industrial part numbers. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN. The additional current is < 30 μA with a pull up resistor of 100 kΩ. The i.MX 6x processors have an internal pull up from the POR_B pin to the VDD_SNVS_IN pin. For i.MX 6x applications, if additional current in the coin cell mode is not desired, use an external switch to disconnect the RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull-up RESETBMCU to a rail off in the coin cell mode. PF0100 NXP Semiconductors 13 GENERAL PRODUCT CHARACTERISTICS Coin Cell mode current (uA) Coin cell mode 100 MMPF0100 10 MMPF0100A 1 -40 -20 0 20 40 60 80 Temperature (°C) Temperature (oC) Figure 4. Coin cell mode current vs temperature PF0100 14 NXP Semiconductors GENERAL DESCRIPTION 5 General description The PF0100 is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application processors. 5.1 Features This section summarizes the PF0100 features. • Input voltage range to PMIC: 2.8 V - 4.5 V • Buck regulators • Four to six channel configurable • SW1A/B/C, 4.5 A (single); 0.3 V to 1.875 V • SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 V to 1.875 V • SW2, 2.0 A; 0.4 V to 3.3 V (2.5 A; 1.2 V to 3.3 V (24)) • SW3A/B, 2.5 A (single/dual); 0.4 V to 3.3 V • SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 V to 3.3 V • SW4, 1.0 A; 0.4 V to 3.3 V • SW4, VTT mode provide DDR termination at 50% of SW3A • Dynamic voltage scaling • Modes: PWM, PFM, APS • Programmable output voltage • Programmable current limit • Programmable soft start • Programmable PWM switching frequency • Programmable OCP with fault interrupt • Boost regulator • SWBST, 5.0 V to 5.15 V, 0.6 A, OTG support • Modes: PFM and auto • OCP fault interrupt • LDOs • Six user programable LDO • VGEN1, 0.80 V to 1.55 V, 100 mA • VGEN2, 0.80 V to 1.55 V, 250 mA • VGEN3, 1.8 V to 3.3 V, 100 mA • VGEN4, 1.8 V to 3.3 V, 350 mA • VGEN5, 1.8 V to 3.3 V, 100 mA • VGEN6, 1.8 V to 3.3 V, 200 mA • Soft start • LDO/switch supply • VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400 μA • DDR memory reference voltage • VREFDDR, 0.6 V to 0.9 V, 10 mA • 16 MHz internal master clock • OTP(one time programmable) memory for device configuration • User programmable start-up sequence and timing • Battery backed memory including coin cell charger • I2C interface • User programmable standby, sleep, and off modes Notes 24. SW2 capable of 2.5 A in NP, F9, and FA Industrial versions only (ANES suffix) PF0100 NXP Semiconductors 15 GENERAL DESCRIPTION 5.2 Functional block diagram MMPF0100 functional internal block diagram Power generation OTP startup configuration OTP prototyping (Try before buy) Sequence and timing Voltage Switching regulators Phasing and frequency selection SW1A/B/C (0.3 V to 1.875 V) Configurable 4.5 A or 2.5 A+2.0 A Bias & references Internal core voltage reference SW2 (0.4 V to 3.3 V, 2.0 A) DDR voltage reference Logic and control Parallel MCU interface Regulator control Linear regulators VGEN1 (0.8 V to 1.55 V, 100 mA) VGEN2 (0.8 V to 1.55 V, 250 mA) VGEN3 (1.8 V to 3.3 V, 100 mA) SW3A/B (0.4 V to 3.3 V) Configurable 2.5 A or 1.25 A+1.25 A VGEN4 (1.8 V to 3.3 V, 350 mA) SW4 (0.4 V to 3.3 V, 1.0 A) VGEN6 (1.8 V to 3.3 V, 200 mA) Boost Regulator (5.0 V to 5.15 V, 600 mA) USB OTG Supply VSNVS (1.0 V to 3.0 V, 400 μA) RTC supply with coin cell charger VGEN5 (1.8 V to 3.3 V, 100 mA) 2 I C communication and registers Fault detection and protection Thermal Current limit Short-circuit Figure 5. Functional block diagram 5.3 Functional description 5.3.1 Power generation The PF0100 PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs, one switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices. The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with higher current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. Further, SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the buck regulators, SW4, can also operate as a tracking regulator when used for memory termination. The buck regulators provide the supply to processor cores and to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for the processor cores and/or other circuitry. Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be powered from VIN, or from a coin cell. 5.3.2 Control logic The PF0100 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-up section, or by configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration. The PF0100 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger for the coin cell is included as well. PF0100 16 NXP Semiconductors GENERAL DESCRIPTION 5.3.2.1 5.3.2.1.1 Interface signals PWRON PWRON is an input signal to the IC generating a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG bit. Refer to section 6.4.2.1 Turn on events, page 31 for more details. 5.3.2.1.2 STANDBY STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section 6.4.1.3 Standby mode, page 29 for more details. Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide VSNVS, or the PMIC does not reliably enter and exit the STANDBY mode. 5.3.2.1.3 RESETBMCU RESETBMCU is an open drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 ms to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event. When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100 is turned off if the fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described above is repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on Table 137 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses. 5.3.2.1.4 SDWNB SDWNB is an open drain, active low output notifying the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock cycle before powering down and is then de-asserted in the OFF state. 5.3.2.1.5 INTB INTB is an open drain, active low output. It is asserted when any fault occurs, provided the fault interrupt is unmasked. INTB is de-asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit. PF0100 NXP Semiconductors 17 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6 Functional block requirements and behaviors 6.1 Start-up The PF0100 can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in to the device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kΩ resistor. The OTP configuration is enabled by connecting VDDOTP to GND. For NP devices, selecting the OTP configuration causes the PF0100 to not start-up. However, the PF0100 can be controlled through the I2C port for prototyping and programming. Once programmed, the NP device starts up with the customer programmed configuration. 6.1.1 Device start-up configuration Table 10 shows the default configuration, which can be accessed on all devices as described previously, as well as the pre-programmed OTP configurations. Table 10. Start-up configuration Registers Default configuration Pre-programmed OTP configuration All devices F0 F1(25) F2(25) F3 F4 F6 F9 FA FB FC FD Default I C Address 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 VSNVS_VOLT 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V SW1AB_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.2 V SW1AB_SEQ 1 1 1 1 2 2 2 5 5 2 2 2 SW1C_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.2 V SW1C_SEQ 1 2 1 1 2 2 2 5 5 2 2 2 SW2_VOLT 3.0 V 3.3 V 3.15 V 3.15 V 3.15 V 3.15 V 3.3 V 1.375 V 1.375 V 3.3 V 3.3 V 3.15 V SW2_SEQ 2 5 2 2 1 1 4 5 5 6 5 1 SW3A_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V 1.2 V 1.35 V 1.2 V SW3A_SEQ 3 3 4 4 4 4 3 6 6 4 3 4 SW3B_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V 1.2 V 1.35 V 1.2 V SW3B_SEQ 3 3 4 4 4 4 3 6 6 4 3 4 SW4_VOLT 1.8 V 3.15 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.825 V 1.825 V 1.8 V 3.15 V 1.8 V SW4_SEQ 3 6 3 3 3 3 4 7 7 3 6 3 SWBST_VOLT - 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V SWBST_SEQ - 13 6 6 6 6 Off 10 10 Off 13 6 VREFDDR_SEQ 3 3 4 4 4 4 3 6 6 4 3 4 VGEN1_VOLT - 1.5 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.5 V 1.5 V 1.2 V VGEN1_SEQ - 9 4 4 4 4 5 - - 3 9 - VGEN2_VOLT 1.5 V 1.5 V - - - - 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V VGEN2_SEQ 2 10 - - - - Off 8 8 Off 10 7 VGEN3_VOLT - 2.5 V - - - - 2.8 V 1.8 V 1.8 V 2.5 V 2.5 V 1.8 V VGEN3_SEQ - 11 - - - - 5 8 8 Off 11 7 VGEN4_VOLT 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 3.0 V 3.0 V 1.8 V 1.8V 1.8 V VGEN4_SEQ 3 7 3 3 3 3 4 4 4 7 7 3 VGEN5_VOLT 2.5 V 2.8 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 2.5 V 2.5 V 2.8 V 2.8 V 2.5 V 2 PF0100 18 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 10. Start-up configuration (continued) Registers Default configuration Pre-programmed OTP configuration All devices F0 F1(25) F2(25) F3 F4 F6 F9 FA FB FC FD VGEN5_SEQ 3 12 5 5 5 5 5 8 8 1 1 5 VGEN6_VOLT 2.8 V 3.3 V - - - - 3.0 V 2.8 V 2.8 V 3.3 V 3.3 V 2.8 V VGEN6_SEQ 3 8 - - - - 1 7 7 8 8 7 1.0 ms 2.0 ms 1.0 ms 1.0 ms 1.0 ms 1.0 ms 0.5 ms 0.5 ms 0.5 ms 2.0 ms 2.0 ms 1.0 ms 6.25 mV/μs 1.5625 mV /μs 12.5 mV/ μs 12.5 mV/ μs 12.5 mV/ μs 12.5 mV/ μs 6.25 mV/ μs PU CONFIG, SEQ_CLK_SPEED PU CONFIG, SWDVS_CLK PU CONFIG, PWRON SW1AB CONFIG SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz 2.0 MHz SW2 CONFIG 2.0 MHz SW3A CONFIG SW3AB Single Phase, 2.0 MHz SW3B CONFIG 2.0 MHz PG EN 1.5625 mV/ 1.5625 mV/ 12.5 mV/μs μs μs SW1ABC Single Phase, 2.0 MHz SW1AB Single Phase, SW1C Independent mode, 2.0 MHz Level sensitive SW1C CONFIG SW4 CONFIG 6.25 mV/μs 6.25 mV/μs No VTT, 2.0 MHz RESETBMCU in default mode Notes 25. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option instead of the F2 OTP option. PF0100 NXP Semiconductors 19 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS LICELL UVDET VIN td1 tr1 1V VSNVS td2 tr2 td3 PWRON tr3 SW1A/B SW1C td4 tr3 SW2 VGEN2 td4 tr3 SW3A/B SW4 VREFDDR VGEN4 VGEN5 td5 VGEN6 tr4 RESETBMCU *VSNVS starts from 1.0 V if LICELL is valid before VIN. Figure 6. Default start-up sequence Table 11. Default start-up sequence timing Parameter Description Min. Typ. Max. Unit Notes (26) tD1 Turn-on delay of VSNVS – 5.0 – ms tR1 Rise time of VSNVS – 3.0 – ms tD2 User determined delay – 1.0 – ms – (27) – ms • SEQ_CLK_SPEED[1:0] = 00 – 2.0 – • SEQ_CLK_SPEED[1:0] = 01 – 2.5 – tR2 Rise time of PWRON Turn-on delay of first regulator tD3 tR3 • SEQ_CLK_SPEED[1:0] = 10 – 4.0 – • SEQ_CLK_SPEED[1:0] = 11 – 7.0 – – 0.2 – Rise time of regulators (28) ms ms (29) PF0100 20 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 11. Default start-up sequence timing (continued) Parameter Description Min. Typ. Max. • SEQ_CLK_SPEED[1:0] = 00 – 0.5 – • SEQ_CLK_SPEED[1:0] = 01 – 1.0 – • SEQ_CLK_SPEED[1:0] = 10 – 2.0 – • SEQ_CLK_SPEED[1:0] = 11 – 4.0 – Unit Notes Delay between regulators tD4 ms tR4 Rise time of RESETBMCU – 0.2 – ms tD5 Turn-on delay of RESETBMCU – 2.0 – ms Notes 26. Assumes LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may extend to a maximum of 24 ms. 27. Depends on the external signal driving PWRON. 28. Default configuration. 29. Rise time is a function of slew rate of regulators and nominal voltage selected. 6.1.2 One time programmability (OTP) OTP allows the programming of start-up configurations for a variety of applications. Before permanently programming the IC by programming fuses, a configuration may be prototyped by using the “Try Before Buy” (TBB) feature. Further, an error correction code(ECC) algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. The parameters which can be configured by OTP are listed below. • General: I2C slave address, PWRON pin configuration, start-up sequence and timing • Buck regulators: Output voltage, dual/single phase or independent mode configuration, switching frequency, and soft start ramp rate • Boost regulator and LDOs: Output voltage NOTE: When prototyping or programming fuses, the user must ensure register settings are consistent with the hardware configuration. This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single/ dual phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it is gated by the buck regulator in the start-up sequence. 6.1.2.1 Start-up sequence and timing Each regulator has 5-bit allocated to program its start-up time slot from a turn on event; therefore, each can be placed from position one to thirty-one in the start-up sequence. The all zeros code indicates a regulator is not part of the start-up sequence and remains off. See Table 12. The delay between each position is equal; however, four delay options are available. See Table 13. The start-up sequence terminates at the last programmed regulator. PF0100 NXP Semiconductors 21 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 12. Start-up sequence SWxx_SEQ[4:0]/ VGENx_SEQ[4:0]/ VREFDDR_SEQ[4:0] Sequence 00000 Off 00001 SEQ_CLK_SPEED[1:0] * 1 00010 SEQ_CLK_SPEED[1:0] * 2 * * * * * * * * 11111 SEQ_CLK_SPEED[1:0] * 31 Table 13. Start-up sequence clock speed SEQ_CLK_SPEED[1:0] Time (μs) 00 500 01 1000 10 2000 11 4000 6.1.2.2 PWRON pin configuration The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input (PWRON_CFG = 1). As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it into sleep mode. As an edge sensitive input, such as when connected to a mechanical switch, a falling edge turns on the part and if the switch is held low for greater than or equal to 4.0 seconds, the part turns off or enters sleep mode. Table 14. PWRON configuration PWRON_CFG Mode 0 PWRON pin HIGH = ON PWRON pin LOW = OFF or Sleep mode 1 PWRON pin pulled LOW momentarily = ON PWRON pin LOW for 4.0 seconds = OFF or Sleep mode I2C address configuration 6.1.2.3 The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts. Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to “1” while the lower three LSBs of the I2C address (I2C_SLV_ADDR[2:0]) are programmable as shown in Table 15. Table 15. I2C address configuration I2C_SLV_ADDR[3] hard coded I2C_SLV_ADDR[2:0] I2C device address (Hex) 1 000 0x08 1 001 0x09 1 010 0x0A 1 011 0x0B PF0100 22 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 15. I2C address configuration (continued) I2C_SLV_ADDR[3] hard coded I2C_SLV_ADDR[2:0] I2C device address (Hex) 1 100 0x0C 1 101 0x0D 1 110 0x0E 1 111 0x0F 6.1.2.4 Soft start ramp rate The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in 6.4.4.2.1 Dynamic voltage scaling, page 35. 6.1.3 OTP prototyping Before permanently programming fuses, it is possible to test the desired configuration by using the “Try Before Buy” feature. With this feature, the configuration is loaded from the OTP registers. These registers merely serve as temporary storage for the values to be written to the fuses, for the values read from the fuses, or for the values read from the default configuration. To avoid confusion, these registers are referred to as the TBBOTP registers. The portion of the register map concerned with OTP is shown in Table 137 and Table 138. The contents of the TBBOTP registers are initialized to zero when a valid VIN is first applied. The values loaded into the TBBOTP registers depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR_XOR bits. Refer to Table 16. • If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration. • If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 1, the values are loaded from the fuses. In the MMPF0100, FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In the MMPF0100A, the XOR function is removed. It is required to set all of the FUSE_PORx bits to be able to load the fuses. • If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 0, the TBBOTP registers remain initialized at zero. The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP registers maintained and not loaded from a different source. The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 V to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V, TBB_POR = 1 and there is a valid turn-on event. Refer to the application note AN4536 for an example of prototyping. 6.1.4 Reading OTP fuses As described in the previous section, the contents of the fuses are loaded to the TBBOTP registers when the following conditions are met; VIN is valid, VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 1. If ECC were enabled at the time the fuses were programmed, the error corrected values can be loaded into the TBBOTP registers if desired. Once the fuses are loaded and a turn-on event occurs, the PMIC powers on with the configuration programmed in the fuses. For more details on reading the OTP fuses, see application note AN4536. 6.1.5 Programming OTP fuses The parameters which can be programmed are shown in the TBBOTP registers in Table 137. Extended page 1, page 111 of the register map. The PF0100 offers ECC, the control registers for which functions are located in Extended Page 2 of the register map. There are ten banks of twenty-six fuses each which can be programmed. Programming the fuses requires an 8.25 V, 100 mA supply powering the VDDOTP pin, bypassed with 10 to 20 μF of capacitance. For more details on programming the OTP fuses, see application note AN4536. PF0100 NXP Semiconductors 23 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 16. Source of start-up sequence VDDOTP(V) TBB_POR FUSE_POR_XOR Start-up sequence 0 0 0 None 0 0 1 OTP fuses 0 1 x TBBOTP registers 1.5 x x Factory defined 6.2 16 MHz and 32 kHz clocks There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within -8.0/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions: • VIN < UVDET • All regulators are in sleep mode • All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions: • During start-up, VIN > UVDET • PWRON_CFG = 1, for power button debounce timing In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 27 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock. Table 17. 16 MHz clock specifications TMIN to TMAX (See Table 3), VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V and typical external component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted. Symbol Min. Typ. Max. Units Operating voltage from VIN 2.8 – 4.5 V f16MHZ 16 MHz clock frequency 14.7 16 17.2 MHz f2MHZ 2.0 MHz clock frequency 1.84 – 2.15 MHz VIN16MHz Parameters Notes (30) Notes 30. 2.0 MHz clock is derived from the 16 MHz clock. 6.2.1 Clock adjustment The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By changing the factory trim values of the 16 MHz clock, the user may add an offset as small as ±3.0% of the nominal frequency. Contact your NXP representative for detailed information on this feature. 6.3 Bias and references block description 6.3.1 Internal core voltage references All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the performance of the bandgap. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is kept powered as long as there is a valid supply and/or valid coin cell. Table 18 shows the main characteristics of the core circuitry. PF0100 24 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 18. Core voltages electrical specifications(32) TMIN to TMAX (See Table 3), VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V, and typical external component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted. Symbol Parameters Min. Typ. Max. Units Notes – – 1.5 1.3 – – V (31) – – 2.775 0.0 – – V Output voltage – 1.2 – V VCOREREFACC Absolute accuracy – 0.5 – % VCOREREFTACC Temperature drift – 0.25 – % VCOREDIG (digital core supply) Output voltage • ON mode • Coin cell mode and OFF VCOREDIG — VCORE (analog core supply) Output voltage • ON mode and charging • OFF and coin cell mode VCORE (31) — VCOREREF (bandgap / regulator reference) VCOREREF (31) Notes 31. 3.0 V < VIN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system malfunction. 32. For information only. 6.3.1.1 External components Table 19. External components for core voltages 6.3.2 Regulator Capacitor value (μF) VCOREDIG 1.0 VCORE 1.0 VCOREREF 0.22 VREFDDR voltage reference VREFDDR is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then utilizes a voltage follower to drive the load. VINREFDDR CHALF1 100 nf VINREFDDR VHALF CHALF2 100 nf _ + Discharge VREFDDR VREFDDR CREFDDR 1.0 uf Figure 7. VREFDDR block diagram PF0100 NXP Semiconductors 25 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.3.2.1 VREFDDR control register The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 20. Table 20. Register VREFDDCRTL - ADDR 0x6A Name UNUSED Bit # R/W Default 3:0 – 0x00 UNUSED 4 R/W 0x00 Enable or disables VREFDDR output voltage • 0 = VREFDDR Disabled • 1 = VREFDDR Enabled 7:5 – 0x00 UNUSED VREFDDREN UNUSED 6.3.2.1.1 Description External components Table 21. VREFDDR external components(33) Capacitor Capacitance (μF) VINREFDDR(34) to VHALF 0.1 VHALF to GND 0.1 VREFDDR 1.0 Notes 33. Use X5R or X7R capacitors. 34. VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output. 6.3.2.1.2 VREFDDR specifications Table 22. VREFDDR electrical characteristics TMIN to TMAX (See Table 3), VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes VREFDDR VINREFDDR Operating input voltage range 1.2 – 1.8 V IREFDDR Operating load current range 0.0 – 10 mA Current limit • IREFDDR when VREFDDR is forced to VINREFDDR/4 10.5 15 25 mA – 8.0 – μA – VINREFDDR/2 – V IREFDDRLIM IREFDDRQ Quiescent Current (35) Active mode – DC VREFDDR Output voltage • 1.2 V < VINREFDDR < 1.8 V • 0.0 mA < IREFDDR < 10 mA VREFDDRTOL Output voltage tolerance (TA = -40 °C to 85 °C) • 1.2 V < VINREFDDR < 1.8 V • 0.6 mA ≤ IREFDDR ≤ 10 mA –1.0 – 1.0 % VREFDDRTOL Output voltage tolerance (TA = -40 °C to 105 °C), applicable only to the extended industrial version • 1.2 V < VINREFDDR < 1.8 V • 0.6 mA ≤ IREFDDR ≤ 10 mA –1.2 – 1.2 % VREFDDRLOR Load regulation • 1.0 mA < IREFDDR < 10 mA • 1.2 V < VINREFDDR < 1.8 V – 0.40 – mV/mA PF0100 26 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 22. VREFDDR electrical characteristics (continued) TMIN to TMAX (See Table 3), VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit tONREFDDR Turn-on time • Enable to 90% of end value • VINREFDDR = 1.2 V, 1.8 V • IREFDDR = 0.0 mA – – 100 μs tOFFREFDDR Turn-off time • Disable to 10% of initial value • VINREFDDR = 1.2 V, 1.8 V • IREFDDR = 0.0 mA – – 10 ms VREFDDROSH Start-up overshoot • VINREFDDR = 1.2 V, 1.8 V • IREFDDR = 0.0 mA – 1.0 6.0 % VREFDDRTLR Transient load response • VINREFDDR = 1.2 V, 1.8 V – 5.0 – mV Notes Active mode – AC Notes 35. When VREFDDR is off there is a quiescent current of 1.5 μA typical. PF0100 NXP Semiconductors 27 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4 Power generation 6.4.1 Modes of operation The operation of the PF0100 can be reduced to five states, or modes: on, off, sleep, standby, and coin cell. Figure 8 shows the state diagram of the PF0100, along with the conditions to enter and exit from each state. Coin Cell VIN < UVDET VIN < UVDET VIN > UVDET PWRON = 0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) VIN < UVDET Sleep VIN < UVDET PWRON = 0 Any SWxOMODE bits=1 (PWRON_CFG=0) Or PWRON=0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) Thermal shutdown PWRON = 0 Any SWxOMODE bits=1 (PWRON_CFG=0) Or PWRON=0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) PWRON=1 & VIN > UVDET (PWRON_CFG =0) Or PWRON= 0 < 4.0 sec & VIN > UVDET (PWRON_CFG=1) PWRON=1 & VIN > UVDET (PWRON_CFG = 0) Or PWRON= 0 < 4.0 sec & VIN > UVDET (PWRON_CFG=1) OFF PWRON = 0 All SWxOMODE bits= 0 (PWRON_CFG = 0) Or PWRON = 0 held >= 4.0 sec All SWxOMODE bits= 0 & PWRONRSTEN = 1 (PWRON_CFG = 1) ON Thermal shudown STANDBY asserted STANDBY de-asserted Standby PWRON = 0 All SWxOMODE bits= 0 (PWRON_CFG = 0) Or PWRON = 0 held >= 4.0 sec All SWxOMODE bits= 0 & PWRONRSTEN = 1 (PWRON_CFG = 1) Thermal shutdown Figure 8. State diagram To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must exceed the rising UVDET threshold to allow a power up. Refer to Table 29 for the UVDET thresholds. Additionally, I2C control is not possible in the coin cell mode and the interrupt signal, INTB, is only active in sleep, standby, and on states. 6.4.1.1 ON mode The PF0100 enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation. 6.4.1.2 OFF mode The PF0100 enters the off mode after a turn-off event. A thermal shutdown event also forces the PF0100 into the off mode. Only VCOREDIG and VSNVS are powered in the mode of operation. To exit the off mode, a valid turn-on event is required. RESETBMCU is asserted, low, in this mode. PF0100 28 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.1.3 Standby mode • Depending on STANDBY pin configuration, standby is entered when the STANDBY pin is asserted. This is typically used for lowpower mode of operation. • When STANDBY is de-asserted, standby mode is exited. A product may be designed to go into a low-power mode after periods of inactivity. The STANDBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the regulators or disabling some regulators. The configuration of the regulators in standby is pre-programmed through the I2C interface. Note that the STANDBY pin is programmable for active high or active low polarity, and decoding of a standby event takes into account the programmed input polarity as shown in Table 23. When the PF0100 is powered up first, regulator settings for the standby mode are mirrored from the regulator settings for the on mode. To change the STANDBY pin polarity to Active Low, set the STANDBYINV bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STANDBY generally is referred to as active high throughout this document. Table 23. Standby pin and polarity control STANDBY (pin)(37) STANDBYINV (I2C bit)(38) STANDBY control (36) 0 0 0 0 1 1 1 0 1 1 1 0 Notes 36. STANDBY = 0: System is not in standby, STANDBY = 1: System is in standby 37. The state of the STANDBY pin only has influence in on mode. 38. Bit 6 in power control register (ADDR - 0x1B) Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a standby event. This allows the processor and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 24, STBYDLY delays the standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the standby event. Table 24. STANDBY delay - initiated response STBYDLY[1:0](39) Function 00 No delay 01 One 32 k period (default) 10 Two 32 k periods 11 Three 32 k periods Notes 39. Bits [5:4] in power control register (ADDR - 0x1B) 6.4.1.4 Sleep mode • Depending on PWRON pin configuration, sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set. • To exit sleep mode, assert the PWRON pin. In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/ B, and SW4. The activated regulators maintains settings for this mode and voltage until the next turn-on event. Table 25 shows the control bits in sleep mode. During sleep mode, interrupts are active and the INTB pin reports any unmasked fault event. PF0100 NXP Semiconductors 29 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 25. Regulator mode control SWxOMODE Off operational mode (Sleep) (40) 0 Off 1 PFM Notes 40. For sleep mode, an activated switching regulator, should use the off mode set point as programmed by SW1xOFF[5:0] for SW1A/B/C and SWxOFF[6:0] for SW2, SW3A/B, and SW4. 6.4.1.5 Coin cell mode In the coin cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the PMIC. No turn-on event is accepted in the coin cell state. Transition to the off state requires VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. If the coin cell is depleted, a complete system reset occurs. At the next application of power and the detection of a turn-on event, the system is re-initialized with all I2C bits including those reset on COINPORB, which are restored to their default states. 6.4.2 State machine flow summary Table 26 provides a summary matrix of the PF0100 flow diagram to show the conditions needed to transition from one state to another. Table 26. State machine flow summary STATE Next state OFF Coin cell Sleep Standby ON OFF X VIN < UVDET X X PWRON_CFG = 0 PWRON = 1 & VIN > UVDET or PWRON_CFG = 1 PWRON = 0 < 4.0 s & VIN > UNDET Coin cell VIN > UVDET X X X X Thermal shutdown Initial state Sleep PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 VIN < UVDET X X PWRON_CFG = 0 PWRON = 1 & VIN > UVDET or PWRON_CFG = 1 PWRON = 0 < 4.0 s & VIN > UNDET VIN < UVDET PWRON_CFG = 0 PWRON = 0 Any SWxOMODE = 1 or PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 X Standby de-asserted VIN < UVDET PWRON_CFG = 0 PWRON = 0 Any SWxOMODE = 1 or PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 Standby asserted X Thermal shutdown Standby PWRON_CFG = 0 PWRON = 0 All SWxOMODE = 0 or PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s All SWxOMODE = 0 & PWRONRSTEN = 1 Thermal shutdown ON PWRON_CFG = 0 PWRON = 0 All SWxOMODE = 0 or PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s All SWxOMODE = 0 & PWRONRSTEN = 1 PF0100 30 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.2.1 Turn on events From off and sleep modes, the PMIC is powered on by a turn-on event. The type of turn-on event depends on the configuration of PWRON. PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1. VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON is high (pulled up to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a Turn-on event. See the state diagram, Figure 8, and the Table 26 for more details. Any regulator enabled in the sleep mode remains enabled when transitioning from sleep to on, i.e., the regulator does not turn off and then on again to match the start-up sequence. The following is a more detailed description of the PWRON configurations: • If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC turns on; the interrupt and sense bits, PWRONI and PWRONS respectively, is set. • If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC turns on; the interrupt and sense bits, PWRONI and PWRONS respectively, sets. The sense bit shows the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press. The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in Table 27. The interrupt is cleared by software, or when cycling through the OFF mode. Table 27. PWRON hardware debounce bit settings Bits PWRONDBNC[1:0] State Turn on debounce (ms) Falling edge INT debounce (ms) Rising edge INT debounce (ms) 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 Notes 41. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin. 6.4.2.2 6.4.2.2.1 Turn off events PWRON pin The PWRON pin is used to power off the PF0100. The PWRON pin can be configured with OTP to power off the PMIC under the following two conditions: 1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low. 2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit. 6.4.2.2.2 Thermal protection If the die temperature surpasses a given threshold, the thermal protection circuit powers off the PMIC to avoid damage. A turn-on event does not power on the PMIC while it is in thermal protection. The part remains in off mode until the die temperature decreases below a given threshold. There are no specific interrupts related to this other than the warning interrupt. See 4.2.1 Power dissipation, page 11 section for more detailed information. 6.4.2.2.3 Undervoltage detection When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin cell mode. PF0100 NXP Semiconductors 31 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.3 Power tree The PF0100 PMIC features six buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination, and a DDR voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as well as the boost regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they are powered on or off. The six general use LDO regulators are directly supplied from the main input supply or from the switching regulators depending on the application requirements. Since VREFDDR is intended to provide DDR memory reference voltage, it should be supplied by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR. VSNVS is supplied by either the main input supply or the coin cell. Refer to Table 28 for a summary of all power supplies provided by the PF0100. Table 28. Power tree summary Supply Output voltage (V) Step size (mV) Maximum load current (mA) SW1A/B 0.3 - 1.875 25 2500 SW1C 0.3 - 1.875 25 2000 SW2 0.4 - 3.3 25/50 2000 (43) SW3A/B 0.4 - 3.3 25/50 1250 (42) SW4 0.5*SW3A_OUT, 0.4 - 3.3 25/50 1000 SWBST 5.00/5.05/5.10/5.15 50 600 VGEN1 0.80 – 1.55 50 100 VGEN2 0.80 – 1.55 50 250 VGEN3 1.8 – 3.3 100 100 VGEN4 1.8 – 3.3 100 350 VGEN5 1.8 – 3.3 100 100 VGEN6 1.8 – 3.3 100 200 VSNVS 1.0 - 3.0 NA 0.4 VREFDDR 0.5*SW3A_OUT NA 10 Notes 42. Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up to 2500 mA. 43. SW2 capable of 2500 mA in NP, F9, and FA Industrial versions only (ANES suffix) Figure 9 shows a simplified power map with various recommended options to supply the different block within the PF0100, as well as the typical application voltage domain on the i.MX 6X processor. Note that each application power tree is dependent upon the system’s voltage and current requirements, therefore a proper input voltage should be selected for the regulators. The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges. Table 29 summarizes the UVDET thresholds. Table 29. UVDET threshold UVDET threshold VIN Rising 3.1 V Falling 2.65 V PF0100 32 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS SW1A CORE (0.3 to 1.875 V), 1.25 A i.MX6X MCU VDDARM_IN SW1B CORE (0.3 to 1.875 V), 1.25 A VIN 2.8 - 4.5 V SW1C SOC (0.3 to 1.875 V), 2.0 A VDDSOC_IN SW2 VDDHIGH (0.4 to 3.3 V), 2.0 A VDDHIGH_IN SW3A DDR CORE (0.4 to 3.3 V), 1.25 A SW3B DDR IO (0.4 to 3.3 V), 1.25 A VDD_DDR_IO SW4 System/VTT (0.4 to 3.3 V) (0.5*VDDR) 1.0 A SWBST 5.0 V, 0.6 A VREFDDR 0.5*VDDR, 10 mA SW3A/B VIN MUX / COIN CHRG Coincell VINMAX = 3.4 V SW4 VINMAX = 3.6 V SW4 SW4 VSNVS_IN USB_OTG DDR3 Peripherals VGEN4 (1.8 to 3.3 V), 350 mA VGEN5 (1.8 to 3.3 V), 100 mA VIN SW2 VGEN2 (0.80 to 1.55 V), 250 mA VGEN3 (1.8 to 3.3 V), 100 mA VIN SW2 VSNVS 1.0 to 3.0 V, 400 uA VGEN1 (0.80 to 1.55 V), 100 mA VIN SW2 LDO_3p0 VINMAX = 4.5 V VGEN6 (1.8 to 3.3 V), 200 mA Figure 9. PF0100 typical power map PF0100 NXP Semiconductors 33 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4 Buck regulators Each buck regulator is capable of operating in PFM, APS, and PWM switching modes. 6.4.4.1 Current limit Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit condition persists for more than 8.0 ms, a fault interrupt is generated. 6.4.4.2 General control To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur by any of the following means: I2C programming, exiting/entering the Standby mode, exiting/entering Sleep mode, and load current variation. Available switching modes for buck regulators are presented in Table 30. Table 30. Switching mode description Mode Description OFF The regulator is switched off and the output voltage is discharged. PFM In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions. During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Table 31 summarizes the buck regulator programmability for normal and standby modes. Table 31. Regulator mode control SWxMODE[3:0] Normal mode Standby mode 0000 Off Off 0001 PWM Off 0010 Reserved Reserved 0011 PFM Off 0100 APS Off 0101 PWM PWM 0110 PWM APS 0111 Reserved Reserved 1000 APS APS 1001 Reserved Reserved 1010 Reserved Reserved 1011 Reserved Reserved 1100 APS PFM 1101 PWM PFM 1110 Reserved Reserved 1111 Reserved Reserved PF0100 34 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Transitioning between normal and standby modes can affect a change in switching modes as well as output voltage. The rate of the output voltage change is controlled by the dynamic voltage scaling (DVS), explained in 6.4.4.2.1 Dynamic voltage scaling, page 35. For each regulator, the output voltage options are the same for normal and standby modes. When in standby mode, the regulator outputs the voltage programmed in its standby voltage register and operates in the mode selected by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator returns to its normal switching mode and its output voltage programmed in its voltage register. Any regulators whose SWxOMODE bit is set to “1” enters Sleep mode if a PWRON turn-off event occurs, and any regulator whose SWxOMODE bit is set to “0” turns off. In sleep mode, the regulator outputs the voltage programmed in its off (sleep) voltage register and operates in the PFM mode. The regulator exits the sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit is set to “1” remains on and change to its normal configuration settings when exiting the sleep state to the on state. Any regulator whose SWxOMODE bit is set to “0” is powered up with the same delay in the start-up sequence as when powering on from off. At this point, the regulator returns to its default on state output voltage and switch mode settings. Table 25 shows the control bits in sleep mode. When sleep mode is activated by the SWxOMODE bit, the regulator uses the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4. 6.4.4.2.1 Dynamic voltage scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. 1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B, and SW4. A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 34 and Table 35. 2. Standby mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SW1xSTBY[5:0] for SW1A/B/C and by bits SWxSTBY[6:0] for SW2, SW3A/B, and SW4. Voltage transitions initiated by a Standby event are governed by the SW1xDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 34 and Table 35, respectively. 3. Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SW1xOFF[5:0] for SW1A/B/C and by bits SWxOFF[6:0] for SW2, SW3A/B, and SW4. Voltage transitions initiated by a turn-off event are governed by the SW1xDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 34 and Table 35, respectively. Table 32, Table 33, Table 34, and Table 35 summarize the set point control and DVS time stepping applied to all regulators. Table 32. DVS control logic for SW1A/B/C STANDBY Set point selected by 0 SW1x[5:0] 1 SW1xSTBY[5:0] Table 33. DVS control logic for SW2, SW3A/B, and SW4 STANDBY Set Point Selected by 0 SWx[6:0] 1 SWxSTBY[6:0] Table 34. DVS speed selection for SW1A/B/C SW1xDVSSPEED[1:0] Function 00 25 mV step each 2.0 μs 01 (default) 25 mV step each 4.0 μs 10 25 mV step each 8.0 μs 11 25 mV step each 16 μs PF0100 NXP Semiconductors 35 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 35. DVS speed selection for SW2, SW3A/B, and SW4 SWxDVSSPEED[1:0] Function SWx[6] = 0 or SWxSTBY[6] = 0 Function SWx[6] = 1 or SWxSTBY[6] = 1 00 25 mV step each 2.0 μs 50 mV step each 4.0 μs 01 (default) 25 mV step each 4.0 μs 50 mV step each 8.0 μs 10 25 mV step each 8.0 μs 50 mV step each 16 μs 11 25 mV step each 16 μs 50 mV step each 32 μs The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the DVS period the overcurrent condition on the regulator should be masked. Requested Set Point Internally Controlled Steps Example Actual Output Voltage Output Voltage Initial Set Point Actual Output Voltage Internally Controlled Steps Voltage Change Request Output Voltage with light Load Request for Higher Voltage Possible Output Voltage Window Request for Lower Voltage Initiated by I2C Programming, Standby Control Figure 10. Voltage stepping with DVS 6.4.4.2.2 Regulator phase clock The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 36. By default, each regulator is initialized at 90 ° out of phase with respect to each other. For example, SW1x is set to 0 °, SW2 is set to 90 °, SW3A/B is set to 180 °, and SW4 is set to 270 ° by default at power up. Table 36. Regulator phase clock selection SWxPHASE[1:0] Phase of clock sent to regulator (degrees) 00 0 01 90 10 180 11 270 The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 38 shows the selectable options for SWxFREQ[1:0]. For each frequency, all phases are available, allowing regulators operating at different frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and 4.0 MHz, 180 ° are the same in terms of phasing. Table 37 shows the optimum phasing when using more than one switching frequency. PF0100 36 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 37. Optimum phasing Frequencies Optimum Phasing 1.0 MHz 2.0 MHz 0° 180 ° 1.0 MHz 4.0 MHz 0° 180 ° 2.0 MHz 4.0 MHz 0° 180 ° 1.0 MHz 2.0 MHz 4.0 MHz 0° 90 ° 90 ° Table 38. Regulator frequency configuration SWxFREQ[1:0] Frequency 00 1.0 MHz 01 2.0 MHz 10 4.0 MHz 11 Reserved 6.4.4.2.3 Programmable maximum current The maximum current, ISWxMAX, of each buck regulator is programmable. This allows the use of smaller inductors where lower currents are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. The SWx_PWRSTG[2:0] bits in Table 138. Extended Page 2, page 115 of the register map control the number of power stages. See Table 39 for the programmable options. Bit[0] must always be enabled to ensure the stage with the current sensor is chosen. The default setting, SWx_PWRSTG[2:0] = 111, represents the highest maximum current. The current limit for each option is also scaled by the percentage of power stages enabled. Table 39. Programmable current configuration Regulators Control bits % of power stages enabled SW1AB_PWRSTG[2:0] SW1AB ISW1ABMAX 0 0 1 40% 1.0 0 1 1 80% 2.0 1 0 1 60% 1.5 1 1 1 100% 2.5 SW1C_PWRSTG[2:0] SW1C ISW1CMAX 0 0 1 43% 0.9 0 1 1 58% 1.2 1 0 1 86% 1.7 1 1 100% 1 SW2_PWRSTG[2:0] SW2 Rated current (A) 2.0 ISW2MAX 0 0 1 38% 0.75 0 1 1 75% 1.5 1 0 1 63% 1.25 1 1 1 100% 2.0 PF0100 NXP Semiconductors 37 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 39. Programmable current configuration (continued) Regulators Control bits % of power stages enabled SW3A_PWRSTG[2:0] SW3A ISW3AMAX 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 SW3B_PWRSTG[2:0] SW3B ISW3BMAX 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 SW4_PWRSTG[2:0] SW4 6.4.4.3 Rated current (A) ISW4MAX 0 0 1 50% 0.5 0 1 1 75% 0.75 1 0 1 75% 0.75 1 1 1 100% 1.0 SW1A/B/C SW1/A/B/C are 2.5 A to 4.5 A buck regulators which can be configured in various phasing schemes, depending on the desired cost/ performance trade-offs. The following configurations are available: • SW1A/B/C single phase with one inductor • SW1A/B as a single phase with one inductor and SW1C in independent mode with one inductor • SW1A/B as a dual phase with two inductors and SW1C in independent mode with one inductor The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Table 137. Extended page 1, page 111, as shown in Table 40. . Table 40. SW1 configuration SW1_CONFIG[1:0] Description 00 A/B/C single phase 01 A/B single phase, C independent mode 10 A/B dual phase, C independent mode 11 Reserved 6.4.4.3.1 SW1A/B/C single phase In this configuration, all phases A, B, and C, are connected together to a single inductor, thus, providing up to 4.50 A current capability for high current applications. The feedback and all other controls are accomplished by use of pin SW1CFB and SW1C control registers, respectively. Figure 11 shows the connection for SW1A/B/C in single phase mode. During single phase mode operation, all three phases use the same configuration for frequency, phase, and DVS speed set in SW1CCONF register. However, the same configuration settings for frequency, phase, and DVS speed setting on SW1AB registers should be used. The SW1FB pin should be left floating in this configuration. PF0100 38 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS VIN SW1AIN SW1AMODE ISENSE CINSW1A SW1A/B/C SW1ALX LSW1 Controller Driver COSW1A SW1AFAULT Internal Compensation SW1FB I2C Z2 Z1 EA DAC VREF VIN SW1BIN SW1BMODE ISENSE CINSW1B SW1BLX Controller I2C Interface Driver SW1BFAULT VIN SW1CIN SW1CMODE ISENSE CINSW1C SW1CLX Controller Driver SW1CFAULT EP Internal Compensation SW1CFB I2C Z2 Z1 EA VREF DAC Figure 11. SW1A/B/C single phase block diagram 6.4.4.3.2 SW1A/B single phase - SW1C independent mode In this configuration, SW1A/B is connected as a single phase with a single inductor, while SW1C is used as an independent output, using its own inductor and configurations parameters. This configuration allows reduced component count by using only one inductor for SW1A/ B. As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different voltage set point for normal, standby, and sleep modes, as well as switching mode selection and on/off control. Figure 12 shows the physical connection for SW1A/B in single phase and SW1C as an independent output. PF0100 NXP Semiconductors 39 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS VIN SW1AIN SW1AMODE ISENSE CINSW1A SW1A/B SW1ALX LSW1A Controller Driver COSW1A SW1AFAULT Internal Compensation SW1FB I2C Z2 Z1 EA DAC VREF VIN SW1BIN SW1BMODE ISENSE CINSW1B SW1BLX Controller I2C Interface Driver SW1BFAULT VIN SW1CIN SW1C SW1CLX LSW1C COSW1C SW1CMODE ISENSE CINSW1C Controller Driver SW1CFAULT EP Internal Compensation SW1CFB I2C Z2 Z1 EA VREF DAC Figure 12. SW1A/B single phase, SW1C independent mode block diagram Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register, while SW1CLX node operates independently, using the configuration in the SW1CCONF register. 6.4.4.3.3 SW1A/B dual phase - SW1C independent mode In this mode, SW1A/B is connected in dual phase mode using one inductor per switching node, while SW1C is used as an independent output using its own inductor and configuration parameters. This mode provides a smaller output voltage ripple on the SW1A/B output. As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different voltage set point for normal, standby, and sleep modes, as well as switching mode selection and on/off control. Figure 13 shows the physical connection for SW1A/B in dual phase and SW1C as an independent output. PF0100 40 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS VIN SW1AIN SW1AMODE ISENSE CINSW1A SW1AB SW1ALX LSW1A Controller Driver COSW1A SW1AFAULT Internal Compensation SW1FB I2C Z2 Z1 EA DAC VREF VIN SW1BIN SW1BMODE ISENSE CINSW1B SW1BLX LSW1B I2C Interface Controller Driver COSW1B SW1BFAULT VIN SW1CIN SW1C SW1CLX LSW1C COSW1C SW1CMODE ISENSE CINSW1C Controller Driver SW1CFAULT EP Internal Compensation SW1CFB I2C Z2 Z1 EA VREF DAC Figure 13. SW1A/B dual phase, SW1C independent mode block diagram In this mode of operation, SW1ALX and SW1BLX nodes operate automatically at 180 ° phase shift from each other and use the same frequency and DVS configured by SW1ABCONF register, while SW1CLX node operate independently using the configuration in the SW1CCONF register. 6.4.4.3.4 SW1A/B/C setup and control registers SW1A/B and SW1C output voltages are programmable from 0.300 V to 1.875 V in steps of 25 mV. The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW1x[5:0], SW1xSTBY[5:0], and SW1xOFF[5:0] bits respectively. Table 41 shows the output voltage coding for SW1A/B or SW1C. Note: Voltage set points of 0.6 V and below are not supported. PF0100 NXP Semiconductors 41 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 41. SW1A/B/C output voltage configuration Set point SW1x[5:0] SW1xSTBY[5:0] SW1xOFF[5:0] SW1x output (V) Set point SW1x[5:0] SW1xSTBY[5:0] SW1xOFF[5:0] SW1x output (V) 0 000000 0.3000 32 100000 1.1000 1 000001 0.3250 33 100001 1.1250 2 000010 0.3500 34 100010 1.1500 3 000011 0.3750 35 100011 1.1750 4 000100 0.4000 36 100100 1.2000 5 000101 0.4250 37 100101 1.2250 6 000110 0.4500 38 100110 1.2500 7 000111 0.4750 39 100111 1.2750 8 001000 0.5000 40 101000 1.3000 9 001001 0.5250 41 101001 1.3250 10 001010 0.5500 42 101010 1.3500 11 001011 0.5750 43 101011 1.3750 12 001100 0.6000 44 101100 1.4000 13 001101 0.6250 45 101101 1.4250 14 001110 0.6500 46 101110 1.4500 15 001111 0.6750 47 101111 1.4750 16 010000 0.7000 48 110000 1.5000 17 010001 0.7250 49 110001 1.5250 18 010010 0.7500 50 110010 1.5500 19 010011 0.7750 51 110011 1.5750 20 010100 0.8000 52 110100 1.6000 21 010101 0.8250 53 110101 1.6250 22 010110 0.8500 54 110110 1.6500 23 010111 0.8750 55 110111 1.6750 24 011000 0.9000 56 111000 1.7000 25 011001 0.9250 57 111001 1.7250 26 011010 0.9500 58 111010 1.7500 27 011011 0.9750 59 111011 1.7750 28 011100 1.0000 60 111100 1.8000 29 011101 1.0250 61 111101 1.8250 30 011110 1.0500 62 111110 1.8500 31 011111 1.0750 63 111111 1.8750 PF0100 42 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 42 provides a list of registers used to configure and operate SW1A/B/C and a detailed description on each one of these register is provided in Table 43 through Table 52. Table 42. SW1A/B/C register summary Register Address Output SW1ABVOLT 0x20 SW1AB output voltage set point in normal operation SW1ABSTBY 0x21 SW1AB output voltage set point on standby SW1ABOFF 0x22 SW1AB output voltage set point on sleep SW1ABMODE 0x23 SW1AB switching mode selector register SW1ABCONF 0x24 SW1AB DVS, phase, frequency and ILIM configuration SW1CVOLT 0x2E SW1C output voltage set point in normal operation SW1CSTBY 0x2F SW1C output voltage set point in standby SW1COFF 0x30 SW1C output voltage set point in sleep SW1CMODE 0x31 SW1C switching mode selector register SW1CCONF 0x32 SW1C DVS, phase, frequency and ILIM configuration Table 43. Register SW1ABVOLT - ADDR 0x20 Name Bit # R/W Default Description SW1AB 5:0 R/W 0x00 Sets the SW1AB output voltage during normal operation mode. See Table 41 for all possible configurations. UNUSED 7:6 – 0x00 unused Table 44. Register SW1ABSTBY - ADDR 0x21 Name Bit # R/W Default Description SW1ABSTBY 5:0 R/W 0x00 Sets the SW1AB output voltage during standby mode. See Table 41 for all possible configurations. UNUSED 7:6 – 0x00 unused Table 45. Register SW1ABOFF - ADDR 0x22 Name Bit # R/W Default Description SW1ABOFF 5:0 R/W 0x00 Sets the SW1AB output voltage during sleep mode. See Table 41 for all possible configurations. UNUSED 7:6 – 0x00 unused PF0100 NXP Semiconductors 43 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 46. Register SW1ABMODE - ADDR 0x23 Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW1AB switching operation mode. See Table 31 for all possible configurations. UNUSED 4 – 0x00 unused SW1ABOMODE 5 R/W 0x00 Set status of SW1AB when in sleep mode • 0 = OFF • 1 = PFM 7:6 – 0x00 unused SW1ABMODE UNUSED Description Table 47. Register SW1ABCONF - ADDR 0x24 Name Bit # R/W Default Description SW1ABILIM 0 R/W 0x00 SW1AB current limit level selection • 0 = High level current limit • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW1ABFREQ 3:2 R/W 0x00 SW1A/B switching frequency selector. See Table 38. SW1ABPHASE 5:4 R/W 0x00 SW1A/B phase clock selection. See Table 36. SW1ABDVSSPEED 7:6 R/W 0x00 SW1A/B DVS speed selection. See Table 34. Table 48. Register SW1CVOLT - ADDR 0x2E Name Bit # R/W Default Description SW1C 5:0 R/W 0x00 Sets the SW1C output voltage during normal operation mode. See Table 41 for all possible configurations. UNUSED 7:6 – 0x00 unused Table 49. Register SW1CSTBY - ADDR 0x2F Name Bit # R/W Default Description SW1CSTBY 5:0 R/W 0x00 Sets the SW1C output voltage during standby mode. See Table 41 for all possible configurations. UNUSED 7:6 – 0x00 unused Table 50. Register SW1COFF - ADDR 0x30 Name Bit # R/W Default Description SW1COFF 5:0 R/W 0x00 Sets the SW1C output voltage during sleep mode. See Table 41 for all possible configurations. UNUSED 7:6 – 0x00 unused PF0100 44 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 51. Register SW1CMODE - ADDR 0x31 Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW1C switching operation mode. See Table 30 for all possible configurations. UNUSED 4 – 0x00 unused SW1COMODE 5 R/W 0x00 Set status of SW1C when in sleep mode • 0 = OFF • 1 = PFM 7:6 – 0x00 unused SW1CMODE UNUSED Description Table 52. Register SW1CCONF - ADDR 0x32 Name Bit # R/W Default SW1CILIM 0 R/W 0x00 SW1C current limit level selection • 0 = High level current limit • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW1CFREQ 3:2 R/W 0x00 SW1C switching frequency selector. See Table 38. SW1CPHASE 5:4 R/W 0x00 SW1C phase clock selection.See Table 36. SW1CDVSSPEED 7:6 R/W 0x00 SW1C DVS speed selection. See Table 34. 6.4.4.3.5 Description SW1A/B/C external components Table 53. SW1A/B/C external component recommendations Mode Components CINSW1A(44) CIN1AHF A/B/C single phase A/B Single - C independent mode A/B Dual - C independent mode SW1A input capacitor 4.7 μF 4.7 μF 4.7 μF (44) SW1A decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF (44) SW1B input capacitor 4.7 μF 4.7 μF 4.7 μF (44) CINSW1B CIN1BHF Description SW1B decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF (44) SW1C input capacitor 4.7 μF 4.7 μF 4.7 μF (44) SW1C decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF 6 x 22 μF 2 x 22 μF 4 x 22 μF – 3 x 22 μF 3 x 22 μF CINSW1C CIN1CHF COSW1AB COSW1C (44) (44) SW1A/B output capacitor SW1C output capacitor LSW1A SW1A inductor 1.0 μH 1.0 μH 1.0 μH LSW1B SW1B inductor – – 1.0 μH LSW1C SW1C inductor – 1.0 μH 1.0 μH Notes 44. Use X5R or X7R capacitors. PF0100 NXP Semiconductors 45 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.3.6 SW1A/B/C specifications Table 54. SW1A/B/C electrical characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes SW1A/B/C (single phase) VINSW1A VINSW1B VINSW1C Operating input voltage 2.8 – 4.5 V VSW1ABC Nominal output voltage – Table 41 – V -25 -3.0% – – 25 3.0% -65 -45 -3.0% – – – 65 45 3.0% – – 4500 7.1 5.3 10.5 7.9 13.7 10.3 Start-up overshoot • ISW1ABC = 0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V – – 66 mV Turn-on time • Enable to 90% of end value • ISW1x = 0 mA • DVS clk = 25 mV/4.0 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V – – 500 µs – – – 1.0 2.0 4.0 – – – – – – – – – 77 82 86 84 80 68 – – – – – – Output ripple – 10 – mV VSW1ABCLIR Line regulation (APS, PWM) – – 20 mV VSW1ABCLOR DC load regulation (APS, PWM) – – 20 mV Output voltage accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 4.5 A VSW1ABCACC • 0.625 V ≤ VSW1ABC ≤ 1.450 V • 1.475 V ≤ VSW1ABC ≤ 1.875 V • PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 150 mA • 0.625 V < VSW1ABC < 0.675 V • 0.7 V < VSW1ABC < 0.85 V • 0.875 V < VSW1ABC < 1.875 V ISW1ABC ISW1ABCLIM VSW1ABCOSH tONSW1ABC fSW1ABC Rated output load current, • 2.8 V < VIN < 4.5 V, 0.625 V < VSW1ABC < 1.875 V Current limiter peak current detection • Current through inductor • SW1ABILIM = 0 • SW1ABILIM = 1 Switching frequency • SW1xFREQ[1:0] = 00 • SW1xFREQ[1:0] = 01 • SW1xFREQ[1:0] = 10 mV % mA A MHz Efficiency • VIN = 3.6 V, fSW1ABC = 2.0 MHz, LSW1ABC = 1.0 μH ηSW1ABC ΔVSW1ABC • PFM, 0.9 V, 1.0 mA • PFM, 1.2 V, 50 mA • APS, PWM, 1.2 V, 850 mA • APS, PWM, 1.2 V, 1275 mA • APS, PWM, 1.2 V, 2125 mA • APS, PWM, 1.2 V, 4500 mA % PF0100 46 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 54. SW1A/B/C electrical characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Transient load regulation • Transient load = 0 to 2.25 A, di/dt = 100 mA/μs • Overshoot • Undershoot – – – – 50 50 Quiescent current • PFM Mode • APS Mode – – 18 145 – – µA Discharge resistance – 600 – Ω Notes SW1A/B/C (single phase) (continued) VSW1ABCLOTR ISW1ABCQ RSW1ABCDIS mV SW1A/B (single/dual phase) VINSW1A VINSW1B Operating input voltage 2.8 – 4.5 V VSW1AB Nominal output voltage – Table 41 – V -25 -3.0% - 25 3.0% -65 -45 -3.0% – – – 65 45 3.0% – – 2500 4.5 3.3 6.5 4.9 8.5 6.4 2.2 1.6 3.2 2.4 4.3 3.2 Output voltage accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 2.5 A VSW1ABACC • 0.625 V ≤ VSW1AB ≤ 1.450 V • 1.475 V ≤ VSW1AB ≤ 1.875 V • PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 150 mA • 0.625 V < VSW1AB < 0.675 V • 0.7 V < VSW1AB < 0.85 V • 0.875 V < VSW1AB < 1.875 V ISW1AB ISW1ABLIM Rated output load current, • 2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V Current limiter peak current detection • SW1A/B single phase (current through inductor) • SW1ABILIM = 0 • SW1ABILIM = 1 • • SW1A/B dual phase (current through inductor per phase) • SW1ABILIM = 0 • SW1ABILIM = 1 mV % mA (46) A (46) VSW1ABOSH Start-up overshoot • ISW1AB = 0.0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V – – 66 mV tONSW1AB Turn-on time • Enable to 90% of end value • ISW1AB = 0.0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V – – 500 µs – – – 1.0 2.0 4.0 – – – fSW1AB Switching frequency • SW1ABFREQ[1:0] = 00 • SW1ABFREQ[1:0] = 01 • SW1ABFREQ[1:0] = 10 MHz PF0100 NXP Semiconductors 47 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 54. SW1A/B/C electrical characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit – – – – – – 82 84 86 87 82 71 – – – – – – Output ripple – 10 – mV VSW1ABLIR Line regulation (APS, PWM) – – 20 mV VSW1ABLOR DC load regulation (APS, PWM) – – 20 mV VSW1ABLOTR Transient load regulation • Transient load = 0 to 1.25 A, di/dt = 100 mA/μs • Overshoot • Undershoot – – – – 50 50 Quiescent current • PFM mode • APS mode – – 18 235 – – µA Notes SW1A/B (single/dual phase) (continued) Efficiency (single phase) • VIN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH ηSW1AB ΔVSW1AB ISW1ABQ • PFM, 0.9 V, 1.0 mA • PFM, 1.2 V, 50 mA • APS, PWM, 1.2 V, 500 mA • APS, PWM, 1.2 V, 750 mA • APS, PWM, 1.2 V, 1250 mA • APS, PWM, 1.2 V, 2500 mA % mV RONSW1AP SW1A P-MOSFET RDS(on) • VINSW1A = 3.3 V – 215 245 mΩ RONSW1AN SW1A N-MOSFET RDS(on) • VINSW1A = 3.3 V – 258 326 mΩ ISW1APQ SW1A P-MOSFET leakage current • VINSW1A = 4.5 V – – 7.5 µA ISW1ANQ SW1A N-MOSFET leakage current • VINSW1A = 4.5 V – – 2.5 µA RONSW1BP SW1B P-MOSFET RDS(on) • VINSW1B = 3.3 V – 215 245 mΩ RONSW1BN SW1B N-MOSFET RDS(on) • VINSW1B = 3.3 V – 258 326 mΩ ISW1BPQ SW1B P-MOSFET leakage current • VINSW1B = 4.5 V – – 7.5 µA ISW1BNQ SW1B N-MOSFET leakage current • VINSW1B = 4.5 V – – 2.5 µA Discharge resistance – 600 – Ω RSW1ABDIS PF0100 48 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 54. SW1A/B/C electrical characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes SW1C (independent) VINSW1C Operating input voltage 2.8 – 4.5 V VSW1C Nominal output voltage – Table 41 – V -25 -3.0% – – 25 3.0% Output voltage accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1C < 2.0 A VSW1CACC • 0.625 V ≤ VSW1C ≤ 1.450 V • 1.475 V ≤ VSW1C ≤ 1.875 V • PFM, steady state 2.8 V < VIN < 4.5 V, 0 < ISW1C < 50 mA • 0.625 V < VSW1C < 0.675 V • 0.7 V < VSW1C < 0.85 V • 0.875 V < VSW1C < 1.875 V ISW1C ISW1CLIM Rated output load current • 2.8 V < VIN < 4.5 V, 0.625 V < VSW1C < 1.875 V Current limiter peak current detection • Current through inductor • SW1CILIM = 0 • SW1CILIM = 1 mV -65 -45 -3.0% – – – 65 45 3.0% – – 2000 2.6 1.95 4.0 3.0 5.2 3.9 mA A — VSW1COSH Start-up overshoot • ISW1C = 0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V – – 66 mV tONSW1C Turn-on time • Enable to 90% of end value • ISW1C = 0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V – – 500 µs – – – 1.0 2.0 4.0 – – – – – – – – – 77 78 86 84 78 65 – – – – – – Output ripple – 10 – mV VSW1CLIR Line regulation (APS, PWM) – – 20 mV VSW1CLOR DC load regulation (APS, PWM) – – 20 mV VSW1CLOTR Transient load regulation • Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs • Overshoot • Undershoot – – – – 50 50 Quiescent current • PFM mode • APS mode – – 22 145 – – fSW1C Switching frequency • SW1CFREQ[1:0] = 00 • SW1CFREQ[1:0] = 01 • SW1CFREQ[1:0] = 10 (45) MHz Efficiency • VIN = 3.6 V, fSW1C = 2.0 MHz, LSW1C = 1.0 μH • PFM, 0.9 V, 1.0 mA • PFM, 1.2 V, 50 mA • APS, PWM, 1.2 V, 400 mA • APS, PWM, 1.2 V, 600 mA • APS, PWM, 1.2 V, 1000 mA • APS, PWM, 1.2 V, 2000 mA ηSW1C ΔVSW1C ISW1CQ % mV µA PF0100 NXP Semiconductors 49 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 54. SW1A/B/C electrical characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. 184 206 211 260 Unit Notes SW1C (independent) (continued) RONSW1CP SW1C P-MOSFET RDS(on) • at VINSW1C = 3.3 V – RONSW1CN SW1C N-MOSFET RDS(on) • at VINSW1C = 3.3 V – ISW1CPQ SW1C P-MOSFET leakage current • VINSW1C = 4.5 V – – 10.5 µA ISW1CNQ SW1C N-MOSFET leakage current • VINSW1C = 4.5 V – – 3.5 µA RSW1CDIS Discharge resistance – 600 – Ω mΩ mΩ Notes 45. Meets 1.89 A current rating for VDDSOC_IN domain on i.MX 6X processor. 46. Current rating of SW1AB supports the power virus mode of operation of the i.MX 6X processor. PFM 0.1 1 10 Load Current (mA) 100 1000 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 Efficiency (%) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 APS PWM 10 100 1000 10000 Load Current (mA) Figure 14. SW1AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; consumer version PF0100 50 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS PFM 0.1 1 10 100 1000 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 Efficiency (%) Efficiency (%) 100 90 80 ) (% 70 y 60 c n 50 e i 40 c if f 30 E 20 10 0 APS PWM 10 Load Current (mA) 100 1000 10000 Load Current (mA) Figure 15. SW1AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; extended industrial version PFM 0.1 1 10 100 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 Efficiency (%) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 APS PWM 10 1000 100 1000 10000 Load Current (mA) Load Current (mA) Figure 16. SW1C efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; consumer version 100 90 80 ) 70 (% y 60 c n 50 e i c fif 40 E 30 20 10 0 Efficiency (%) Efficiency (%) 100 90 80 ) 70 (% y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 Load Current (mA) 100 1000 APS PWM 10 100 1000 10000 Load Current (mA) Figure 17. SW1C efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; extended industrial version PF0100 NXP Semiconductors 51 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.4 SW2 SW2 is a single phase, 2.0 A rated buck regulator (2.5 A in NP, F9, and FA Industrial versions only (ANES suffix)). Table 30 describes the modes, and Table 31 show the options for the SWxMODE[3:0] bits. Figure 18 shows the block diagram and the external component connections for SW2 regulator. VIN SW2IN SW2MODE ISENSE CINSW2 SW2 Controller SW2LX Driver LSW2 COSW2 SW2FAULT EP Internal Compensation SW2FB I2C Interface I2C Z2 Z1 VREF EA DAC Figure 18. SW2 block diagram 6.4.4.4.1 SW2 setup and control registers SW2 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW2[6] is set to “0”, the output is limited to the lower output voltages from 0.400 V to 1.975 V with 25 mV increments, as determined by bits SW2[5:0]. Likewise, once bit SW2[6] is set to “1”, the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV increments, as determined by bits SW2[5:0]. In order to optimize the performance of the regulator, it is recommended only voltages from 2.000 V to 3.300 V be used in the high range, and the lower range be used for voltages from 0.400 V to 1.975 V. The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW2[5:0], SW2STBY[5:0] and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] are copied into bits SW2STBY[6], and SW2OFF[6] bits. Therefore, the output voltage range remains the same in all three operating modes. Table 55 shows the output voltage coding valid for SW2. Note: Voltage set points of 0.6 V and below are not supported. Table 55. SW2 output voltage configuration Low output voltage range(47) High output voltage range Set point SW2[6:0] SW2 output Set point SW2[6:0] SW2 output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 PF0100 52 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 55. SW2 output voltage configuration (continued) Low output voltage range(47) High output voltage range Set point SW2[6:0] SW2 output Set point SW2[6:0] SW2 output 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 PF0100 NXP Semiconductors 53 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 55. SW2 output voltage configuration (continued) Low output voltage range(47) High output voltage range Set point SW2[6:0] SW2 output Set point SW2[6:0] SW2 output 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 47. For voltages less than 2.0 V, only use set points 0 to 63. Setup and control of SW2 is done through I2C registers listed in Table 56, and a detailed description of each one of the registers is provided in Tables 57 to Table 61. Table 56. SW2 register summary Register Address Description SW2VOLT 0x35 Output voltage set point on normal operation SW2STBY 0x36 Output voltage set point on standby SW2OFF 0x37 Output voltage set point on sleep SW2MODE 0x38 Switching mode selector register SW2CONF 0x39 DVS, phase, frequency, and ILIM configuration Table 57. Register SW2VOLT - ADDR 0x35 Name Bit # R/W Default Description SW2 5:0 R/W 0x00 Sets the SW2 output voltage during normal operation mode. See Table 55 for all possible configurations. SW2 6 R 0x00 Sets the operating output voltage range for SW2. Set during OTP or TBB configuration only. See Table 55 for all possible configurations. UNUSED 7 – 0x00 unused PF0100 54 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 58. Register SW2STBY - ADDR 0x36 Name SW2STBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW2 output voltage during standby mode. See Table 55 for all possible configurations. SW2STBY 6 R 0x00 Sets the operating output voltage range for SW2 on standby mode. This bit inherits the value configured on bit SW2[6] during OTP or TBB configuration. See Table 55 for all possible configurations. UNUSED 7 – 0x00 unused Table 59. Register SW2OFF - ADDR 0x37 Name SW2OFF Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW2 output voltage during sleep mode. See Table 55 for all possible configurations. SW2OFF 6 R 0x00 Sets the operating output voltage range for SW2 on sleep mode. This bit inherits the value configured on bit SW2[6] during OTP or TBB configuration. See Table 55 for all possible configurations. UNUSED 7 – 0x00 unused Table 60. Register SW2MODE - ADDR 0x38 Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW2 switching operation mode. See Table 30 for all possible configurations. UNUSED 4 – 0x00 unused SW2OMODE 5 R/W 0x00 Set status of SW2 when in sleep mode • 0 = OFF • 1 = PFM 7:6 – 0x00 unused SW2MODE UNUSED Description Table 61. Register SW2CONF - ADDR 0x39 Name Bit # R/W Default Description SW2ILIM 0 R/W 0x00 SW2 current limit level selection (48) • 0 = High level current limit • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. See Table 38. SW2PHASE 5:4 R/W 0x00 SW2 phase clock selection. See Table 36. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection. See Table 35. Notes 48. SW2ILIM = 0 must be used in NP/F9/FA versions (Industrial only) if 2.5 A output load current is desired PF0100 NXP Semiconductors 55 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.4.2 SW2 external components Table 62. SW2 external component recommendations Components Description CINSW2(49) CIN2HF Values SW2 input capacitor 4.7 μF (49) SW2 decoupling input capacitor 0.1 μF (49) SW2 output capacitor COSW2 3 x 22 μF 1.0 μH SW2 inductor LSW2 Notes 49. Use X5R or X7R capacitors. 6.4.4.4.3 SW2 Specifications Table 63. SW2 electrical characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min Typ Max Unit Notes (50) Switch mode supply SW2 VINSW2 Operating input voltage 2.8 – 4.5 V VSW2 Nominal output voltage – Table 55 – V -25 -3.0% -6.0% – – – 25 3.0% 6.0% -65 -45 -3.0% -3.0% – – – – 65 45 3.0% 3.0% – – – – 2000 2500 2.8 2.1 4.0 3.0 5.2 3.9 Output voltage accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 2.0 A VSW2ACC • 0.625 V < VSW2 < 0.85 V • 0.875 V < VSW2 < 1.975 V • 2.0 V < VSW2 < 3.3 V • PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 ≤ 50 mA • 0.625 V < VSW2 < 0.675 V • 0.7 V < VSW2 < 0.85 V • 0.875 V < VSW2 < 1.975 V • 2.0 V < VSW2 < 3.3 V ISW2 ISW2LIM Rated output load current • 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V • 2.8 V < VIN < 4.5 V, 1.2 V < VSW2 < 3.3 V, SW2LIM = 0 Current limiter peak current detection • Current through inductor • SW2ILIM = 0 • SW2ILIM = 1 mV % mA Start-up overshoot • ISW2 = 0.0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V – – 66 mV tONSW2 Turn-on time • Enable to 90% of end value • ISW2 = 0.0 mA • DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V – – 550 µs – – – 1.0 2.0 4.0 – – – fSW2 (52) A VSW2OSH Switching frequency • SW2FREQ[1:0] = 00 • SW2FREQ[1:0] = 01 • SW2FREQ[1:0] = 10 (51) MHz PF0100 56 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 63. SW2 electrical characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min Typ Max Unit – – – – – – 94 95 96 94 92 86 – – – – – – Output ripple – 10 – mV VSW2LIR Line regulation (APS, PWM) – – 20 mV VSW2LOR DC load regulation (APS, PWM) – – 20 mV VSW2LOTR Transient load regulation • Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs • Overshoot • Undershoot – – – – 50 50 Quiescent current • PFM mode • APS mode (low output voltage settings) • APS mode (high output voltage settings) – – – 23 145 305 – – – Notes Switch mode supply SW2 (continued) Efficiency • VIN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH • PFM, 3.15 V, 1.0 mA • PFM, 3.15 V, 50 mA • APS, PWM, 3.15 V, 400 mA • APS, PWM, 3.15 V, 600 mA • APS, PWM, 3.15 V, 1000 mA • APS, PWM, 3.15 V, 2000 mA ηSW2 ΔVSW2 ISW2Q % mV µA RONSW2P SW2 P-MOSFET RDS(on) • at VIN = VINSW2 = 3.3 V – 190 209 mΩ RONSW2N SW2 N-MOSFET RDS(on) • at VIN = VINSW2 = 3.3 V – 212 255 mΩ ISW2PQ SW2 P-MOSFET leakage current • VIN = VINSW2 = 4.5 V – – 12 µA ISW2NQ SW2 N-MOSFET leakage current • VIN = VINSW2 = 4.5 V – – 4.0 µA RSW2DIS Discharge resistance – 600 – Ω Notes 50. When output is set to > 2.6 V the output follows the input down when VIN gets near 2.8 V. 51. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance). 52. Applies to NP, F9, and FA Industrial versions only (ANES suffix) PF0100 NXP Semiconductors 57 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS PFM 0.1 1 10 100 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 Efficiency (%) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 APS PWM 10 1000 Load Current (mA) 100 1000 10000 Load Current (mA) Figure 19. sw2 Efficiency Waveforms: VIN = 4.2 V; VOUT = 3.0 V; consumer version 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 Efficiency (%) Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 Load Current (mA) 100 1000 APS PWM 10 100 1000 10000 Load Current (mA) Figure 20. sw2 efficiency waveforms: vin = 4.2 v; vout = 3.0 v; Extended Industrial Version 6.4.4.4.4 SW3A/B SW3A/B are 1.25 to 2.5 A rated buck regulators, depending on the configuration. Table 30 describes the available switching modes and Table 31 show the actual configuration options for the SW3xMODE[3:0] bits. SW3A/B can be configured in various phasing schemes, depending on the desired cost/performance trade-offs. The following configurations are available: • A single phase • A dual phase • Independent regulators The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 64 shows the options for the SW3CFG[1:0] bits. PF0100 58 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 64. SW3 configuration SW3_CONFIG[1:0] Description 00 A/B single phase 01 A/B single phase 10 A/B dual phase 11 A/B independent 6.4.4.4.5 SW3A/B single phase In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 21. This configuration reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set. VIN SW3AIN SW3AMODE ISENSE CINSW3A SW3 SW3ALX LSW3A Controller Driver COSW3A SW3AFAULT Internal Compensation SW3AFB I2C Z2 Z1 VREF EA DAC I2C Interface VIN SW3BIN SW3BMODE ISENSE CINSW3B SW3BLX Controller Driver SW3BFAULT EP I2C Internal Compensation SW3BFB Z2 VREF Z1 EA DAC Figure 21. SW3A/B single phase block diagram PF0100 NXP Semiconductors 59 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.4.6 SW3A/B dual phase SW3A/B can be connected in dual phase configuration using one inductor per switching node, as shown in Figure 22. This mode allows a smaller output voltage ripple. Feedback is taken from pin SW3AFB and pin SW3BFB must be left open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set. In this configuration, the regulators switch 180 degrees apart. VIN SW3AIN SW3AMODE ISENSE CINSW3A SW3 SW3ALX LSW3A Controller Driver COSW3A SW3AFAULT Internal Compensation SW3AFB I2C Z2 Z1 VREF EA I2C Interface DAC VIN SW3BIN SW3BLX LSW3B COSW3B SW3BMODE ISENSE CINSW3B Controller Driver SW3BFAULT EP I2C Internal Compensation SW3BFB Z2 VREF Z1 EA DAC Figure 22. SW3A/B dual phase block diagram PF0100 60 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.4.7 SW3A - SW3B independent outputs SW3A and SW3B can be configured as independent outputs as shown in Figure 23, providing flexibility for applications requiring more voltage rails with less current capability. Each output is configured and controlled independently by its respective I2C registers as shown in Table 66. VIN SW3AIN SW3AMODE ISENSE CINSW3A SW3A SW3ALX LSW3A Controller Driver COSW3A SW3AFAULT Internal Compensation SW3AFB I2C Z2 Z1 VREF EA DAC VIN SW3BIN SW3BLX LSW3B COSW3B I2C Interface ISENSE CINSW3B SW3B SW3BMODE Controller Driver SW3BFAULT EP Internal Compensation SW3BFB I2C Z2 Z1 EA VREF DAC Figure 23. SW3A/B independent output block diagram 6.4.4.4.8 SW3A/B Setup and Control Registers SW3A/B output voltage is programmable from 0.400 V to 3.300 V; however, bit SW3x[6] in register SW3xVOLT is read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW3x[6] is set to “0”, the output is limited to the lower output voltages from 0.40 V to 1.975 V with 25 mV increments, as determined by bits SW3x[5:0]. Likewise, once bit SW3x[6] is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV increments, as determined by bits SW3x[5:0]. In order to optimize the performance of the regulator, it is recommended only voltages from 2.00 V to 3.300 V be used in the high range and the lower range be used for voltages from 0.400 V to 1.975 V. The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW3x[5:0], SW3xSTBY[5:0], and SW3xOFF[5:0] bits respectively; however, the initial state of the SW3x[6] bit is copied into the SW3xSTBY[6] and SW3xOFF[6] bits. Therefore, the output voltage range remains the same on all three operating modes. Table 65 shows the output voltage coding valid for SW3x. Note: Voltage set points of 0.6 V and below are not supported. PF0100 NXP Semiconductors 61 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 65. SW3A/B output voltage configuration Low output voltage range (53) High output voltage range Set point SW3x[6:0] SW3x output Set point SW3x[6:0] SW3x output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 PF0100 62 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 65. SW3A/B output voltage configuration Low output voltage range (53) High output voltage range Set point SW3x[6:0] SW3x output Set point SW3x[6:0] SW3x output 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 53. For voltages less than 2.0 V, only use set points 0 to 63. PF0100 NXP Semiconductors 63 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 66 provides a list of registers used to configure and operate SW3A/B. A detailed description on each of these register is provided on Tables 67 through Table 76. Table 66. SW3AB register summary Register Address Output SW3AVOLT 0x3C SW3A output voltage set point on normal operation SW3ASTBY 0x3D SW3A output voltage set point on standby SW3AOFF 0x3E SW3A output voltage set point on sleep SW3AMODE 0x3F SW3A switching mode selector register SW3ACONF 0x40 SW3A DVS, phase, frequency and ILIM configuration SW3BVOLT 0x43 SW3B output voltage set point on normal operation SW3BSTBY 0x44 SW3B output voltage set point on standby SW3BOFF 0x45 SW3B output voltage set point on sleep SW3BMODE 0x46 SW3B switching mode selector register SW3BCONF 0x47 SW3B DVS, phase, frequency and ILIM configuration Table 67. Register SW3AVOLT - ADDR 0x3C Name Bit # R/W Default Description SW3A 5:0 R/W 0x00 Sets the SW3A output voltage (independent) or SW3A/B output voltage (single/dual phase), during normal operation mode. See Table 65 for all possible configurations. SW3A 6 R 0x00 Sets the operating output voltage range for SW3A (independent) or SW3A/B (single/dual phase). Set during OTP or TBB configuration only. See Table 65 for all possible configurations. UNUSED 7 – 0x00 unused Table 68. Register SW3ASTBY - ADDR 0x3D Name SW3ASTBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3A output voltage (independent) or SW3A/B output voltage (single/dual phase), during standby mode. See Table 65 for all possible configurations. SW3ASTBY 6 R 0x00 Sets the operating output voltage range for SW3A (independent) or SW3A/B (single/dual phase) on standby mode. This bit inherits the value configured on bit SW3A[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 – 0x00 unused PF0100 64 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 69. Register SW3AOFF - ADDR 0x3E Name SW3AOFF Bit # 5:0 R/W R/W Default Description 0x00 Sets the SW3A output voltage (independent) or SW3A/B output voltage (Single/Dual phase), during Sleep mode. See Table 65 for all possible configurations. SW3AOFF 6 R 0x00 Sets the operating output voltage range for SW3A (independent) or SW3A/B (single/dual phase) on sleep mode. This bit inherits the value configured on bit SW3A[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 – 0x00 unused Table 70. Register SW3AMODE - ADDR 0x3F Name SW3AMODE UNUSED SW3AOMODE UNUSED Bit # R/W Default Description 3:0 R/W 0x08 Sets the SW3A (independent) or SW3A/B (single/ dual phase) switching operation mode. See Table 30 for all possible configurations. 4 – 0x00 unused 5 R/W 0x00 Set status of SW3A (independent) or SW3A/B (single/dual phase) when in sleep mode. • 0 = OFF • 1 = PFM 7:6 – 0x00 unused Table 71. Register SW3ACONF - ADDR 0x40 Name Bit # R/W Default Description SW3AILIM 0 R/W 0x00 SW3A current limit level selection • 0 = High level current limit • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW3AFREQ 3:2 R/W 0x00 SW3A switching frequency selector. See Table 38. SW3APHASE 5:4 R/W 0x00 SW3A phase clock selection. See Table 36. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 35. Table 72. Register SW3BVOLT - ADDR 0x43 Name Bit # R/W Default Description SW3B 5:0 R/W 0x00 Sets the SW3B output voltage (independent) during normal operation mode. See Table 65 for all possible configurations. SW3B 6 R 0x00 Sets the operating output voltage range for SW3B (independent). Set during OTP or TBB configuration only. See Table 65 for all possible configurations. UNUSED 7 – 0x00 unused PF0100 NXP Semiconductors 65 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 73. Register SW3BSTBY - ADDR 0x44 Name SW3BSTBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3B output voltage (independent) during standby mode. See Table 65 for all possible configurations. SW3BSTBY 6 R 0x00 Sets the operating output voltage range for SW3B (Independent) on standby mode. This bit inherits the value configured on bit SW3B[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 – 0x00 unused Table 74. Register SW3BOFF - ADDR 0x45 Name SW3BOFF Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3B output voltage (independent) during sleep mode. See Table 65 for all possible configurations. SW3BOFF 6 R 0x00 Sets the operating output voltage range for SW3B (independent) on sleep mode. This bit inherits the value configured on bit SW3B[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 – 0x00 unused Table 75. Register SW3BMODE - ADDR 0x46 Name SW3BMODE UNUSED SW3BOMODE UNUSED Bit # R/W Default Description 3:0 R/W 0x08 Sets the SW3B (independent) switching operation mode. See Table 30 for all possible configurations. 4 – 0x00 unused 5 R/W 0x00 Set status of SW3B (independent) when in sleep mode. • 0 = OFF • 1 = PFM 7:6 – 0x00 unused Table 76. Register SW3BCONF - ADDR 0x47 Name Bit # R/W Default Description SW3BILIM 0 R/W 0x00 SW3B current limit level selection • 0 = High level Current limit • 1 = Low level Current limit UNUSED 1 R/W 0x00 Unused SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 38. SW3BPHASE 5:4 R/W 0x00 SW3B phase clock selection. See Table 36. SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 35. PF0100 66 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.4.9 SW3A/B external components Table 77. SW3A/B external component requirements Mode Components Description SW3A/B single phase SW3A/B dual phase SW3A independent SW3B independent CINSW3A(54) SW3A input capacitor 4.7 μF 4.7 μF 4.7 μF CIN3AHF(54) SW3A decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF CINSW3B(54) SW3B input capacitor 4.7 μF 4.7 μF 4.7 μF CIN3BHF(54) SW3B decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF COSW3A(54) SW3A output capacitor 3 x 22 μF 2 x 22 μF 2 x 22 μF COSW3B(54) SW3B output capacitor – 2 x 22 μF 2 x 22 μF LSW3A SW3A inductor 1.0 μH 1.0 μH 1.0 μH LSW3B SW3B inductor – 1.0 μH 1.0 μH Notes 54. Use X5R or X7R capacitors. 6.4.4.4.10 SW3A/B specifications Table 78. SW3A/B electrical characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit Notes (55) Switch mode supply SW3a/B VINSW3x Operating input voltage 2.8 – 4.5 V VSW3x Nominal output voltage - Table 65 - V -25 -3.0% -6.0% – – – 25 3.0% 6.0% -65 -45 -3.0% -3.0% – – – – 65 45 3.0% 3.0% – – – – 2500 1250 Output voltage accuracy • PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3x < ISW3xMAX VSW3xACC • • 0.625 V < VSW3x < 0.85 V • 0.875 V < VSW3x < 1.975 V • 2.0 V < VSW3x < 3.3 V • PFM , steady state (2.8 V < VIN < 4.5 V, 0 < ISW3x < 50 mA) • 0.625 V < VSW3x < 0.675 V • 0.7 V < VSW3x < 0.85 V • 0.875 V < VSW3x < 1.975 V • 2.0 V < VSW3x < 3.3 V ISW3x Rated output load current • 2.8 V < VIN < 4.5 V, 0.625 V < VSW3x < 3.3 V • PWM, APS mode single/dual phase • PWM, APS mode independent (per phase) mV % mA (56) PF0100 NXP Semiconductors 67 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 78. SW3A/B electrical characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Parameter Symbol Min. Typ. Max. 3.5 2.7 5.0 3.8 6.5 4.9 Unit Notes Switch mode supply SW3a/B (continued) Current limiter peak current detection • Single phase (current through inductor) • SW3xILIM = 0 • SW3xILIM = 1 ISW3xLIM A • Independent mode or dual phase (current through inductor per phase) • SW3xILIM = 0 • SW3xILIM = 1 1.8 1.3 2.5 1.9 3.3 2.5 VSW3xOSH Start-up overshoot • ISW3x = 0.0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V – – 66 mV tONSW3x Turn-on time • Enable to 90% of end value • ISW3x = 0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V – – 500 µs – – – 1.0 2.0 4.0 – – – – – – – – – 84 85 85 84 80 74 – – – – – – – 10 – fSW3x Switching frequency • SW3xFREQ[1:0] = 00 • SW3xFREQ[1:0] = 01 • SW3xFREQ[1:0] = 10 MHz Efficiency (single phase) • fSW3 = 2.0 MHz, LSW3x 1.0 μH ηSW3AB ΔVSW3x • PFM, 1.5 V, 1.0 mA • PFM, 1.5 V, 50 mA • APS, PWM 1.5 V, 500 mA • APS, PWM 1.5 V, 750 mA • APS, PWM 1.5 V, 1250 mA • APS, PWM 1.5 V, 2500 mA Output ripple % mV VSW3xLIR Line regulation (APS, PWM) – – 20 mV VSW3xLOR DC load regulation (APS, PWM) – – 20 mV – – – – 50 50 – – – – – 22 300 50 250 150 – – – – – 215 245 258 326 VSW3xLOTR ISW3xQ Transient load regulation • Transient load = 0.0 mA to ISW3x/2, di/dt = 100 mA/μs • Overshoot • Undershoot Quiescent current • PFM mode (single/dual phase) • APS mode (single/dual phase) • PFM mode (independent mode) • APS mode (SW3A independent mode) • APS mode (SW3B independent mode) RONSW3AP SW3A P-MOSFET RDS(on) • at VIN = VINSW3A = 3.3 V – RONSW3AN SW3A N-MOSFET RDS(on) • at VIN = VINSW3A = 3.3 V – mV µA mΩ mΩ PF0100 68 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 78. SW3A/B electrical characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit Notes Switch Mode Supply SW3a/B (Continued) ISW3APQ SW3A P-MOSFET leakage current • VIN = VINSW3A = 4.5 V – – 7.5 µA ISW3ANQ SW3A N-MOSFET leakage current • VIN = VINSW3A = 4.5 V – – 2.5 µA RONSW3BP SW3B P-MOSFET RDS(on) • at VIN = VINSW3B = 3.3 V – 215 245 RONSW3BN SW3B N-MOSFET RDS(on) • at VIN = VINSW3B = 3.3 V – 258 326 ISW3BPQ SW3B P-MOSFET leakage current • VIN = VINSW3B = 4.5 V – – 7.5 µA ISW3BPQ SW3B N-MOSFET leakage current • VIN = VINSW3B = 4.5 V – – 2.5 µA RSW3xDIS Discharge resistance – 600 – Ω mΩ mΩ Notes 55. When output is set to > 2.6 V the output follows the input down when VIN gets near 2.8 V. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW3x - VSW3x) = ISW3x* (DCR of inductor +RONSW3xP + PCB trace resistance). Efficiency (%) 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 PFM 0.1 1 10 Load Current (mA) 100 1000 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 Efficiency (%) 56. APS PWM 10 100 1000 10000 Load Current (mA) Figure 24. SW3AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.5 V; consumer version PF0100 NXP Semiconductors 69 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 100 90 80 ) 70 % ( y 60 c n 50 e i c if 40 f E 30 20 10 0 Efficiency (%) Efficiency (%) 100 90 80 ) 70 (% y 60 c n 50 e i c fif 40 E 30 20 10 0 PFM 0.1 1 10 100 1000 APS PWM 10 100 Load Current (mA) 1000 10000 Load Current (mA) Figure 25. SW3AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.5 V; extended industrial version 6.4.4.5 SW4 SW4 is a 1.0 A rated single phase buck regulator capable of operating in two modes. In its default mode, it operates as a normal buck regulator with a programmable output between 0.400 V and 3.300 V. It is capable of operating in the three available switching modes: PFM, APS, and PWM, described on Table 30 and configured by the SW4MODE[3:0] bits, as shown in Table 31. If the system requires DDR memory termination, SW4 can be used in its VTT mode. In the VTT mode, its reference voltage tracks the output voltage of SW3A, scaled by 0.5. Furthermore, when in VTT mode, only the PWM switching mode is allowed. The VTT mode can be configured by use of VTT bit in the OTP_SW4_CONFIG register. Figure 26 shows the block diagram and the external component connections for the SW4 regulator. VIN SW4IN SW4 SW4LX LSW4 COSW4 SW4MODE ISENSE CINSW4 Controller Driver SW4FAULT EP Internal Compensation SW4FB I2C Interface I2C Z2 Z1 EA VREF DAC Figure 26. SW4 block diagram 6.4.4.5.1 SW4 setup and control registers To set the SW4 in regulator or VTT mode, bit VTT of the register OTP_SW4_CONF register in Table 137. Extended page 1, page 111, is programmed during OTP or TBB configuration; setting bit VTT to “1” enables SW4 to operate in VTT mode and “0” in regulator mode. See 6.1.2 One time programmability (OTP), page 21 for detailed information on OTP configuration. In regulator mode, the SW4 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW4[6] in the SW4VOLT register is read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Once SW4[6] is set to “0”, the output is limited to the lower output voltages, from 0.400 V to 1.975 V with 25 mV increments, as determined by the SW4[5:0] bits. Likewise, once the SW4[6] bit is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV increments, as determined by the SW4[5:0] bits. To optimize the performance of the regulator, it is recommended only voltages from 2.000 V to 3.300 V be used in the high range and the lower range be used for voltages from 0.400 V to 1.975 V. PF0100 70 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW4[5:0], SW4STBY[5:0], and SW4OFF[5:0] bits, respectively. However, the initial state of the SW4[6] bit is copied into bits SW4STBY[6], and SW4OFF[6] bits, so the output voltage range remains the same on all three operating modes. Table 79 shows the output voltage coding valid for SW4. Note: Voltage set points of 0.6 V and below are not supported, except in the VTT mode. Table 79. SW4 output voltage configuration Low output voltage range(57) High output voltage range Set point SW4[6:0] SW4 output Set point SW4[6:0] SW4 output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 PF0100 NXP Semiconductors 71 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 79. SW4 output voltage configuration (continued) Low output voltage range(57) High output voltage range Set point SW4[6:0] SW4 output Set point SW4[6:0] SW4 output 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 57. For voltages less than 2.0 V, only use set points 0 to 63. PF0100 72 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Full setup and control of SW4 is done through the I2C registers listed on Table 80, and a detailed description of each one of the registers is provided in Tables 81 to Table 85. Table 80. SW4 register summary Register Address Description SW4VOLT 0x4A Output voltage set point on normal operation SW4STBY 0x4B Output voltage set point on standby SW4OFF 0x4C Output voltage set point on sleep SW4MODE 0x4D Switching mode selector register SW4CONF 0x4E DVS, phase, frequency and ILIM configuration Table 81. Register SW4VOLT - ADDR 0x4A Name Bit # R/W Default Description SW4 5:0 R/W 0x00 Sets the SW4 output voltage during normal operation mode. See Table 79 for all possible configurations. SW4 6 R 0x00 Sets the operating output voltage range for SW4. Set during OTP or TBB configuration only. See Table 79 for all possible configurations. UNUSED 7 – 0x00 unused Table 82. Register SW4STBY - ADDR 0x4B Name SW4STBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW4 output voltage during standby mode. See Table 79 for all possible configurations. SW4STBY 6 R 0x00 Sets the operating output voltage range for SW4 on standby mode. This bit inherits the value configured on bit SW4[6] during OTP or TBB configuration. See Table 79 for all possible configurations. UNUSED 7 – 0x00 unused Table 83. Register SW4OFF - ADDR 0x4C Name SW4OFF Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW4 output voltage during sleep mode. See Table 79 for all possible configurations. SW4OFF 6 R 0x00 Sets the operating output voltage range for SW4 on sleep mode. This bit inherits the value configured on bit SW4[6] during OTP or TBB configuration. See Table 79 for all possible configurations. UNUSED 7 – 0x00 unused PF0100 NXP Semiconductors 73 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 84. Register SW4MODE - ADDR 0x4D Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW4 switching operation mode. See Table 30 for all possible configurations. UNUSED 4 – 0x00 unused SW4OMODE 5 R/W 0x00 Set status of SW4 when in sleep mode • 0 = OFF • 1 = PFM 7:6 – 0x00 unused SW4MODE UNUSED Description Table 85. Register SW4CONF - ADDR 0x4E Name Bit # R/W Default SW4ILIM 0 R/W 0x00 SW4 current limit level selection • 0 = High level current limit • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW4FREQ 3:2 R/W 0x00 SW4 switching frequency selector. See Table 38. SW4PHASE 5:4 R/W 0x00 SW4 phase clock selection. See Table 36. SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 35. 6.4.4.5.2 Description SW4 external components Table 86. SW4 external component requirements Components CINSW4(58) CIN4HF Description Values SW4 input capacitor 4.7 μF (58) SW4 decoupling input capacitor 0.1 μF (58) SW4 output capacitor COSW4 LSW4 SW4 inductor 3 x 22 μF 1.0 μH Notes 58. Use X5R or X7R capacitors PF0100 74 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.5.3 SW4 specifications Table 87. SW4 electrical characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes (59) Switch mode supply SW4 VINSW4 Operating input voltage 2.8 – 4.5 V VSW4 Nominal output voltage • Normal operation • VTT mode – – Table 79 VSW3AFB/2 – – V -25 -3.0 -6.0 – – – 25 3.0 6.0 mV % % -65 -45 -3.0 -3.0 -40 – – – – – 65 45 3.0 3.0 40 mV mV % % mV – – 1000 mA 1.4 1.0 2.0 1.5 3.0 2.4 Output voltage accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A • 0.625 V < VSW4 < 0.85 V • 0.875 V < VSW4 < 1.975 V • 2.0 V < VSW4 < 3.3 V VSW4ACC ISW4 ISW4LIM • PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 50 mA • • 0.625 V < VSW4 < 0.675 V • 0.7 V < VSW4 < 0.85 V • 0.875 V < VSW4 < 1.975 V • 2.0 V < VSW4 < 3.3 V VTT Mode , 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A Rated output load current • 2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 3.3 V Current limiter peak current detection Current through inductor • SW4ILIM = 0 • SW4ILIM = 1 A VSW4OSH Start-up overshoot • ISW4 = 0.0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V – – 66 mV tONSW4 Turn-on time • Enable to 90% of end value • ISW4 = 0.0 mA • DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V – – 500 µs – – – 1.0 2.0 4.0 – – – • PFM, 1.8 V, 1.0 mA • PFM, 1.8 V, 50 mA • APS, PWM 1.8 V, 200 mA • APS, PWM 1.8 V, 500 mA • APS, PWM 1.8 V, 1000 mA – – – – – 81 78 87 88 83 – – – – – • PWM 0.75 V, 200 mA • PWM 0.75 V, 500 mA • PWM 0.75 V, 1000 mA – – – 78 76 66 – – – – 10 – fSW4 Switching frequency • SW4FREQ[1:0] = 00 • SW4FREQ[1:0] = 01 • SW4FREQ[1:0] = 10 (60) MHz Efficiency • fSW4 = 2.0 MHz, LSW4 = 1.0 μH ηSW4 ΔVSW4 Output ripple % mV PF0100 NXP Semiconductors 75 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 87. SW4 electrical characteristics (continued) All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes Switch mode supply SW4 (continued) VSW4LIR Line regulation (APS, PWM) – – 20 mV VSW4LOR DC load regulation (APS, PWM) – – 20 mV VSW4LOTR Transient load regulation • Transient load = 0.0 mA to 500 mA, di/dt = 100 mA/μs • Overshoot • Undershoot – – – – 50 50 Quiescent current • PFM mode • APS mode – – 22 145 – – µA ISW4Q mV RONSW4P SW4 P-MOSFET RDS(on) • at VIN = VINSW4 = 3.3 V – 236 274 mΩ RONSW4N SW4 N-MOSFET RDS(on) • at VIN = VINSW4 = 3.3 V – 293 378 mΩ ISW4PQ SW4 P-MOSFET leakage current • VIN = VINSW4 = 4.5 V – – 6.0 µA ISW4NQ SW4 N-MOSFET leakage current • VIN = VINSW4 = 4.5 V – – 2.0 µA RSW4DIS Discharge resistance – 600 – Ω Notes 59. When output is set to > 2.6 V the output follows the input down when VIN gets near 2.8 V. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW4 - VSW4) = ISW4* (DCR of inductor +RONSW4P + PCB trace resistance). 90 80 Efficiency (%) 70 ) % ( 60 y 50 c n e i 40 ic ff 30 E 20 PFM 10 0 0.1 1 10 Load Current (mA) 100 1000 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 Efficiency (%) 60. APS PWM 10 100 1000 10000 Load Current (mA) Figure 27. SW4 efficiency waveforms: VIN = 4.2 V; VOUT = 1.8 V; consumer version PF0100 76 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 100 90 80 ) 70 % ( y 60 c n 50 e i ic ff 40 E 30 20 10 0 90 Efficiency (%) 70 ) % ( 60 y c 50 n e i 40 ic ff E 30 20 Efficiency (%) 80 PFM 10 0 0.1 1 10 100 APS PWM 10 1000 100 1000 10000 Load Current (mA) Load Current (mA) Figure 28. SW4 efficiency waveforms: VIN = 4.2 V; VOUT = 1.8 V; extended industrial version 6.4.5 Boost regulator SWBST is a boost regulator with a programmable output from 5.0 V to 5.15 V. SWBST can supply the VUSB regulator for the USB PHY in OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator causes the SWBSTOUT and SWBSTFB voltage to be a Schottky drop below the input voltage whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. Figure 29 shows the block diagram and component connection for the boost regulator. VIN CINBST VOBST LBST SWBSTIN DBST SWBSTMODE SWBSTLX Driver EP OC RSENSE VREFSC Controller SWBSTFAULT I2C Interface SC VREFUV UV SWBSTFB COSWBST Internal Compensation Z2 Z1 EA VREF Figure 29. Boost regulator architecture PF0100 NXP Semiconductors 77 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.5.1 SWBST setup and control Boost regulator control is done through a single register SWBSTCTL described in Table 88. SWBST is included in the power-up sequence if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros. Table 88. Register SWBSTCTL - ADDR 0x66 Name Bit # SWBST1VOLT 1:0 SWBST1MODE UNUSED SWBST1STBYMODE UNUSED R/W Default R/W Description 0x00 Set the output voltage for SWBST • 00 = 5.000 V • 01 = 5.050 V • 10 = 5.100 V • 11 = 5.150 V 3:2 R 0x02 Set the Switching mode on normal operation • 00 = OFF • 01 = PFM • 10 = Auto (Default)(61) • 11 = APS 4 – 0x00 unused 6:5 R/W 0x02 Set the switching mode on standby • 00 = OFF • 01 = PFM • 10 = Auto (Default)(61) • 11 = APS 7 – 0x00 unused Notes 61. In auto mode, the controller automatically switches between PFM and APS modes depending on the load current. The SWBST regulator starts up by default in the auto mode if SWBST is part of the startup sequence. 6.4.5.2 SWBST external components Table 89. SWBST external component requirements Components CINBST(62) CINBSTHF COBST (62) (62) Description Values SWBST input capacitor 10 μF SWBST decoupling input capacitor 0.1 μF SWBST output capacitor LSBST SWBST inductor DBST SWBST boost diode 2 x 22 μF 2.2 μH 1.0 A, 20 V Schottky Notes 62. Use X5R or X7R capacitors. PF0100 78 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.5.3 SWBST specifications Table 90. SWBST Electrical Specifications All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameters Min. Typ. Max. Units 2.8 – 4.5 V – Table 88 – V -4.0 – 3.0 % Output ripple • 2.8 V ≤ VIN ≤ 4.5 V • 0 < ISWBST < ISWBSTMAX, excluding reverse recovery of Schottky diode – – 120 mV Vp-p VSWBSTLOR DC load regulation • 0 < ISWBST < ISWBSTMAX – 0.5 – mV/mA VSWBSTLIR DC line regulation • 2.8 V ≤ VIN ≤ 4.5 V, ISWBST = ISWBSTMAX – 50 – mV – – – – 500 600 mA – 222 289 μA Notes Switch mode supply SWBST VINSWBST VSWBST VSWBSTACC ΔVSWBST ISWBST ISWBSTQ Input voltage range Nominal output voltage Output voltage accuracy • 2.8 V ≤ VIN ≤ 4.5 V • 0 < ISWBST < ISWBSTMAX Continuous load current • 2.8 V ≤ VIN ≤ 3.0 V • 3.0 V ≤ VIN ≤ 4.5 V Quiescent current • Auto RDSONBST MOSFET on resistance ISWBSTLIM Peak current limit – 206 306 mΩ 1400 2200 3200 mA Start-up overshoot • ISWBST = 0.0 mA – – 500 mV VSWBSTTR Transient load response • ISWBST from 1.0 mA to 100 mA in 1.0 µs • Maximum transient amplitude – – 300 mV VSWBSTTR Transient load response • ISWBST from 100 mA to 1.0 mA in 1.0 µs • Maximum transient amplitude – – 300 mV tSWBSTTR Transient load response • ISWBST from 1.0 mA to 100 mA in 1.0 µs • Time to settle 80% of transient – – 500 µs tSWBSTTR Transient load response • ISWBST from 100 mA to 1.0 mA in 1.0 µs • Time to settle 80% of transient – – 20 ms ISWBSTHSQ NMOS Off leakage • SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00 – 1.0 5.0 µA tONSWBST Turn-on time • Enable to 90% of VSWBST, ISWBST = 0.0 mA – – 2.0 ms fSWBST Switching frequency – 2.0 – MHz ηSWBST Efficiency • ISWBST = ISWBSTMAX – 86 – % VSWBSTOSH (63) Notes 63. Only in auto mode. PF0100 NXP Semiconductors 79 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.6 LDO regulators description This section describes the LDO regulators provided by the PF0100. All regulators use the main bandgap as reference. Refer to 6.3 Bias and references block description, page 24 for further information on the internal reference voltages. A low-power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest bias currents may be attained by forcing the part into its low-power mode by setting the VGENxLPWR bit. The use of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is disabled, the output is discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low. VINx VINx VREF _ VGENxEN + VGENxLPWR VGENx VGENx I2C Interface CGENx VGENx Discharge Figure 30. General LDO block diagram 6.4.6.1 Transient response waveforms Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 31. Note that the transient line and load response refers to the overshoot, or undershoot only, excluding the DC shift. IL = IMAX/10 IMAX ILOAD IL = IMAX Overshoot VOUT IMAX/10 1.0 us 1.0 us Undershoot Transient Load Stimulus VOUT Transient Load Response VINx_FINAL VINx_INITIAL VINx_INITIAL VINx Overshoot VOUT VINx_FINAL 10 us 10 us Undershoot Transient Line Stimulus VOUT Transient Line Response Figure 31. Transient waveforms PF0100 80 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.6.2 Short-circuit protection All general purpose LDOs have short-circuit protection capability. The short-circuit protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product damage. If a short-circuit condition is detected, the LDO is disabled by resetting its VGENxEN bit, while at the same time, an interrupt VGENxFAULTI is generated to flag the fault to the system processor. The VGENxFAULTI interrupt is maskable through the VGENxFAULTM mask bit. The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators do not automatically disable upon a shortcircuit detection. However, the current limiter continues to limit the output current of the regulator. By default, the REGSCPEN is not set; therefore, at start-up none of the regulators is disabled if an overloaded condition occurs. A fault interrupt, VGENxFAULTI, is generated in an overload condition regardless of the state of the REGSCPEN bit. See Table 91 for SCP behavior configuration. Table 91. Short-circuit behavior REGSCPEN[0] Short-circuit behavior 0 Current limit 1 Shutdown 6.4.6.3 LDO regulator control Each LDO is fully controlled through its respective VGENxCTL register. This register enables the user to set the LDO output voltage according to Table 92 for VGEN1 and VGEN2; and uses the voltage set point on Table 93 for VGEN3 through VGEN6. Table 92. VGEN1, VGEN2 output voltage configuration Set point VGENx[3:0] VGENx output (V) 0 0000 0.800 1 0001 0.850 2 0010 0.900 3 0011 0.950 4 0100 1.000 5 0101 1.050 6 0110 1.100 7 0111 1.150 8 1000 1.200 9 1001 1.250 10 1010 1.300 11 1011 1.350 12 1100 1.400 13 1101 1.450 14 1110 1.500 15 1111 1.550 Table 93. VGEN3/ 4/ 5/ 6 output voltage configuration Set point VGENx[3:0] VGENx output (V) 0 0000 1.80 1 0001 1.90 2 0010 2.00 PF0100 NXP Semiconductors 81 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 93. VGEN3/ 4/ 5/ 6 output voltage configuration (continued) Set point VGENx[3:0] VGENx output (V) 3 0011 2.10 4 0100 2.20 5 0101 2.30 6 0110 2.40 7 0111 2.50 8 1000 2.60 9 1001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 94 presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output. Table 94. LDO control VGENxEN VGENxLPWR VGENxSTBY STANDBY(64) VGENxOUT 0 X X X Off 1 0 0 X On 1 1 0 X Low power 1 X 1 0 On 1 0 1 1 Off 1 1 1 1 Low power Notes 64. STANDBY refers to a standby event as described earlier. For more detail information, Table 95 through Table 100 provide a description of all registers necessary to operate all six general purpose LDO regulators. Table 95. Register VGEN1CTL - ADDR 0x6C Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN1 output voltage. See Table 92 for all possible configurations. VGEN1EN 4 – 0x00 Enables or disables VGEN1 output • 0 = OFF • 1 = ON VGEN1STBY 5 R/W 0x00 Set VGEN1 output state when in standby. Refer to Table 94. VGEN1LPWR 6 R/W 0x00 Enable low-power mode for VGEN1. Refer to Table 94. UNUSED 7 – 0x00 unused VGEN1 Description PF0100 82 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 96. Register VGEN2CTL - ADDR 0x6D Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN2 output voltage. See Table 92 for all possible configurations. VGEN2EN 4 – 0x00 Enables or disables VGEN2 output • 0 = OFF • 1 = ON VGEN2STBY 5 R/W 0x00 Set VGEN2 output state when in standby. Refer to Table 94. VGEN2LPWR 6 R/W 0x00 Enable low-power mode for VGEN2. Refer to Table 94. UNUSED 7 – 0x00 unused VGEN2 Description Table 97. Register VGEN3CTL - ADDR 0x6E Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN3 output voltage. See Table 93 for all possible configurations. VGEN3EN 4 – 0x00 Enables or disables VGEN3 output • 0 = OFF • 1 = ON VGEN3STBY 5 R/W 0x00 Set VGEN3 output state when in standby. Refer to Table 94. VGEN3LPWR 6 R/W 0x00 Enable low-power mode for VGEN3. Refer to Table 94. UNUSED 7 – 0x00 unused VGEN3 Description Table 98. Register VGEN4CTL - ADDR 0x6F Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN4 output voltage. See Table 93 for all possible configurations. VGEN4EN 4 – 0x00 Enables or disables VGEN4 output • 0 = OFF • 1 = ON VGEN4STBY 5 R/W 0x00 Set VGEN4 output state when in standby. Refer to Table 94. VGEN4LPWR 6 R/W 0x00 Enable low-power mode for VGEN4. Refer to Table 94. UNUSED 7 – 0x00 unused VGEN4 Description PF0100 NXP Semiconductors 83 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 99. Register VGEN5CTL - ADDR 0x70 Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN5 output voltage. See Table 93 for all possible configurations. VGEN5EN 4 – 0x00 Enables or disables VGEN5 output • 0 = OFF • 1 = ON VGEN5STBY 5 R/W 0x00 Set VGEN5 output state when in standby. Refer to Table 94. VGEN5LPWR 6 R/W 0x00 Enable low-power mode for VGEN5. Refer to Table 94. UNUSED 7 – 0x00 unused VGEN5 Description Table 100. Register VGEN6CTL - ADDR 0x71 Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN6 output voltage. See Table 93 for all possible configurations. VGEN6EN 4 – 0x00 Enables or disables VGEN6 output • 0 = OFF • 1 = ON VGEN6STBY 5 R/W 0x00 Set VGEN6 output state when in standby. Refer to Table 94. VGEN6LPWR 6 R/W 0x00 Enable low-power mode for VGEN6. Refer to Table 94. UNUSED 7 – 0x00 unused VGEN6 6.4.6.4 Description External components Table 101 lists the typical component values for the general purpose LDO regulators. Table 101. LDO external components Regulator Output capacitor (μF)(65) VGEN1 2.2 VGEN2 4.7 VGEN3 2.2 VGEN4 4.7 VGEN5 2.2 VGEN6 2.2 Notes 65. Use X5R/X7R ceramic capacitors. PF0100 84 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.6.5 6.4.6.5.1 LDO specifications VGEN1 Table 102. VGEN1 electrical characteristics All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes VGEN1 VIN1 Operating input voltage 1.75 – 3.40 V VGEN1NOM Nominal output voltage – Table 92 – V IGEN1 Operating load current 0.0 – 100 mA VGEN1TOL Output voltage tolerance • 1.75 V < VIN1 < 3.4 V • 0.0 mA < IGEN1 < 100 mA • VGEN1[3:0] = 0000 to 1111 -3.0 – 3.0 % VGEN1LOR Load regulation • (VGEN1 at IGEN1 = 100 mA) - (VGEN1 at IGEN1 = 0.0 mA) • For any 1.75 V < VIN1 < 3.4 V – 0.15 – mV/mA VGEN1LIR Line regulation • (VGEN1 at VIN1 = 3.4 V) - (VGEN1 at VIN1 = 1.75 V) • For any 0.0 mA < IGEN1 < 100 mA – 0.30 – mV/mA IGEN1LIM Current limit • IGEN1 when VGEN1 is forced to VGEN1NOM/2 122 167 200 mA IGEN1OCP Overcurrent protection threshold • IGEN1 required to cause the SCP function to disable LDO when REGSCPEN = 1 115 – 200 mA – 14 – μA • VGEN1[3:0] = 0000 - 1101 • VGEN1[3:0] = 1110, 1111 50 37 60 45 – – Output noise density • VIN1 = 1.75 V, IGEN1 = 75 mA • 100 Hz –