MPC17511AEPR2

Freescale Semiconductor Technical Data Document Number: MPC17511A Rev. 5.0, 9/2008 17511A The 17511A is a monolithic H-Bridge designed to be used in portable electronic applications to control small DC motors or bipolar step motors. End applications include head positioners (CDROM or disk drive), camera focus motors, and camera shutter solenoids. The 17511A can operate efficiently with supply voltages as low as 2.0V to as high as 6.8V. Its low RDS(ON) H-Bridge output MOSFETs (0.46  typical) can provide continuos motor drive currents of 1.0A and handle peak currents up to 3.0A. It is easily interfaced to low-cost MCUs via parallel 3.0V- or 5.0V- compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. This device contains an integrated charge pump and level shifter (for gate drive voltages), integrated shoot-through current protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry. The 17511A has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Features • 2.0V to 6.8V Continuous Operation • Output Current 1.0 A(DC), 3.0A (Peak) • MOSFETs < 600 m RDS(ON) @ 25C Guaranteed • 3.0V/ 5.0V TTL- / CMOS-Compatible Inputs • PWM Frequencies up to 200 kHz • Undervoltage Shutdown • Cross-Conduction Suppression • Low Power Consumption • Pb-Free Packaging Designated by Suffix Codes EV and EP 5.0V H-BRIDGE MOTOR DRIVER IC EV SUFFIX (PB-FREE) 98ASA10614D 16-PIN VMFP ORDERING INFORMATION Device MPC17511AEV/EL MPC17511AEP MPC17511AEP/ R2 17511A VM C1L C1H C2L C2H CRES GOUT OUT1 Motor MCU EN GIN IN1 IN2 OUT2 GND Figure 1. 17511A Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008. All rights reserved. Temperature Range (TA) MPC17511AEV 5.0V VDD EP SUFFIX (PB-FREE) 98ARL10577D 24-PIN QFN Package 16 VMFP -20°C to 65°C 24 QFN ARCHIVE INFORMATION ARCHIVE INFORMATION 1.0 A 6.8 V H-Bridge Motor Driver IC INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM Charge Pump C2L C2H C1L CRES GOUT LowVoltage Shutdown VDD VM IN1 OUT1 Level Shifter Predriver IN2 VDD OUT2 Control Logic GIN VDD PGND LGND EN ARCHIVE INFORMATION ARCHIVE INFORMATION C1H Figure 2. 17511A Simplified Internal Block Diagram 17511A 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS C2L 1 16 C2H C1H 2 15 CRES C1L 3 14 GOUT VM 4 13 OUT2 VDD 5 12 PGND IN1 6 11 OUT1 IN2 7 10 GIN EN 8 9 LGND ARCHIVE INFORMATION ARCHIVE INFORMATION PIN CONNECTIONS Figure 3. VMFP Pin Connections Table 1. VMFP Pin Function Description Pin Number Pin Name Formal Name 1 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole). 2 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole). 3 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole). 4 VM Motor Drive Power Supply 5 VDD Logic Supply 6 IN1 Input Control 1 Control signal input 1 7 IN2 Input Control 2 Control signal input 2. 8 EN Enable Control Enable control signal input pin. 9 LGND Logic Ground 10 GIN Gate Driver Input LOW = True control signal for GOUT pin. 11 OUT1 H-Bridge Output 1 Driver output 1 (right half of H-Bridge). 12 PGND Power Ground 13 OUT2 H-Bridge Output 2 Driver output 2 (left half of H-Bridge). 14 GOUT Gate Driver Output Output gate driver signal to external MOSFET switch. 15 CRES Charge Pump Output Capacitor Connection 16 C2H Charge Pump 2H Definition Driver power supply voltage input pin. Control circuit power supply pin. Logic ground pin. Driver ground pin. Charge pump reservoir capacitor pin. Charge pump bucket capacitor 2 (positive pole). 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 3 2 17 OUT2 VM 3 16 PGND VM 4 15 PGND NC 5 14 OUT1 NC 6 13 NC GIN 9 10 11 12 LGND 8 EN 7 IN2 VM IN1 NC 1 Figure 4. QFN Pin Connections Table 2. QFN Pin Function Description Pin Number Pin Name Formal Name 1, 2, 3, 4 VM Motor Drive Power Supply 5, 6, 13, 18 NC No Connect This pin is not used. 7 VDD Logic Supply Control circuit power supply pin. 8 IN1 Logic Input Control 1 Control signal input 1. 9 IN2 Logic Input Control 2 Control signal input 2. 10 EN Enable Control 11 LGND Logic Ground 12 GIN Gate Driver Input 14 OUT1 Output 1 15, 16 PGND Power Ground 17 OUT2 Output 2 19 GOUT Gate Driver Output 20 CRES Pre-Driver Power Supply 21 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole). 22 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole). 23 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole). 24 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole). Definition Driver power supply voltage input pin. Enable control signal input pin. Logic ground pin. LOW = True control signal for GOUT pin. Driver output 1 (right half of H-Bridge). Driver ground pin. Driver output 2 (left half of H-Bridge). Output gate driver signal to external MOSFET switch. Pre-driver circuit power supply pin. ARCHIVE INFORMATION GOUT CRES C2H C2L C1H 24 23 22 21 20 19 18 VM VDD ARCHIVE INFORMATION C1L PIN CONNECTIONS 17511A 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings Rating Symbol Value Unit VM -0.5 to 8.0 V VCRES -0.5 to 14.0 V Logic Supply Voltage VDD -0.5 to 7.0 V Signal Input Voltage (EN, IN1, IN2, GIN) VIN -0.5 to VDD + 0.5 V IO 1.0 IOPK 3.0 Human Body Model VESD1 ±1800 Machine Model VESD2 ± 100 TSTG -65 to 150 C Operating Ambient Temperature TA -20 to 65 C Operating Junction Temperature TJ -20 to 150 C Motor Supply Voltage ARCHIVE INFORMATION Charge Pump Output Voltage Driver Output Current A Continuous Peak (1) ESD Voltage (2) V Storage Temperature Range Thermal Resistance ARCHIVE INFORMATION All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device. (3) C/W RJA 24 Pin QFN 50 16 Pin VMFP 150 Power Dissipation (4) PD 24 Pin QFN 16 Pin VMFP Soldering Temperature mW 2500 830 (5) Peak Package Reflow Temperature During Reflow (6), (7) TSOLDER 260 C TPPRT Note 7 °C Notes 1. TA = 25C, 10 ms pulse width at 200 ms intervals. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 3. QFN24: 45 x 30 x 1 [mm] glass EPOXY board mount. (See: recommended heat pattern) VMFP16: 37 x 50 x 1.6 [mm] glass EPOXY board mount. When the exposed pad is bonded, Rsj will not be performed. Maximum at TA = 25C. When the exposed pad is bonded, Rsj will not be performed. 4. 5. 6. 7. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions TA = 25C, VM VDD 5.0V, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Driver Circuit Power Supply Voltage VM 2.0 5.0 6.8 V Logic Supply Voltage VDD 2.7 5.0 5.7 V C1, C2, C3 0.01 0.1 1.0 F VMSTBY – – 1.0 A VDDSTBY – – 1.0 mA VDD IC – – 3.0 mA – – 0.7 mA Low VDD Detection Voltage (10) VDDDET 1.5 2.0 2.5 V Driver Output ON Resistance (11) RDS(ON) – 0.46 0.60  12 13 13.5 10 11.2 – ARCHIVE INFORMATION Capacitor for Charge Pump Standby Power Supply Current I Motor Supply Standby Current Logic Supply Standby Current (8) I Operating Power Supply Current Logic Supply Current (9) Charge Pump Circuit Supply Current I RES GATE DRIVE Gate Drive Voltage (12) VC V RES No Current Load Gate Drive Ability (Internally Supplied) I VC V RESLOAD CRES = -1.0 mA Gate Drive Output VC RES- 0.5 VC RES- 0.1 VC V IOUT = -50 A VGOUTHIGH lIN = 50 A VGOUTLOW LGND VIN 0 – VDD V High-Level Input Voltage VIH VDD x 0.7 – – V Low-Level Input Voltage VIL – – VDD x 0.3 V IIH – – 1.0 A IIL -1.0 – – A RPU 50 100 200 k RES LGND + 0.1 LGND + 0.5 CONTROL LOGIC Logic Input Voltage Logic Input Function (2.7V < VDD < 5.7V) High-Level Input Current Low-Level Input Current Pull-Up Resistance (EN, GIN) ARCHIVE INFORMATION POWER Notes 8. 9. I I VDDSTBY includes current to the predriver circuit. VDD includes current to the predriver circuit. 10. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the V V gate voltage CRES is applied from an external source, CRES = 7.5V. 11. IO = 1.0A source + sink. 12. Input logic signal not present. 17511A 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25C, VM VDD 5.0V, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit fIN – – 200 kHz Pulse Input Frequency Input Pulse Rise Time ARCHIVE INFORMATION Input Pulse Fall Time (13) tR (15) – – 1.0 (14) s 1.0 (14) s tF – – tPLH tPHL – 0.55 1.0 – 0.55 1.0 tSON tSOFF – 0.15 0.5 – 0.15 0.5 – 0.1 3.0 – – 10 ARCHIVE INFORMATION INPUT (EN, IN1, IN2, GIN) OUTPUT Propagation Delay Time s Turn-ON Time Turn-OFF Time GOUT Propagation Delay Time s Turn-ON Time Turn-OFF Time Charge Pump Circuit Rise Time (16) Low-Voltage Detection Time Notes 13. 14. 15. 16. 17. ms tVCRESON (17) t VDDDET ms Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. When C1 = C2 = C3 = 0.1 F. Time to charge CRES to 11V after application of VDD. 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS VDDDETON 50% tPLH (tSON) tPHL VDDDETOFF 50% t (tSOFF) t VDDDET VDDDET 90% OUT1, OUT2 (GOUT) ARCHIVE INFORMATION VDD 0.8 V/ 1.5 V 2.5 V/3.5 V 90% 0% ( VCRES /0.02  RG NC NC NC NC 0.01 F MCU C1L C1H C2L C2H CRES VDD VM GOUT ARCHIVE INFORMATION ARCHIVE INFORMATION V OUT1 Motor EN GIN IN1 IN2 Solenoid OUT2 GND NC = No Connect Figure 7. 17511A Typical Application Diagram CEMF SNUBBING TECHNIQUES Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients via placing a capacitor or zener at the supply pin (VM) (see Figure 8). 5.0 V 5.0 V 17511A VM VDD 5.0 V 5.0 V 17511A VM VDD C1L C1H OUT1 C2L C2H CRES C1L C1H OUT1 C2L C2H CRES GND GND OUT2 OUT2 Figure 8. CEMF Snubbing Techniques 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 11 PACKAGING SOLDERING PACKAGING SOLDERING THERMAL PERFORMANCE Obverse Reverse Figure 9. Recomended Heat Patterns for QFN24 EP ARCHIVE INFORMATION ARCHIVE INFORMATION Below are the recommended heat patterns for the QFN24 Exposed Pad thermal package. 17511A 12 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS ARCHIVE INFORMATION ARCHIVE INFORMATION For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EV (PB-FREE) SUFFIX 16-PIN VMFP PLASTIC PACKAGE 98ASA10614D ISSUE B 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 13 PACKAGING PACKAGE DIMENSIONS ARCHIVE INFORMATION ARCHIVE INFORMATION PACKAGE DIMENSIONS (CONTINUED) EP (PB-FREE) SUFFIX 24-PIN QFN NON-LEADED PACKAGE 98ARL10577D ISSUE B 17511A 14 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS ARCHIVE INFORMATION ARCHIVE INFORMATION PACKAGE DIMENSIONS (CONTINUED) 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 15 REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES • • • Implemented Revision History page Converted to Freescale format Added Peak Package Reflow Temperature During Reflow (solder reflow) parameter and Note with instructions from www.freescale.com to Maximum Ratings Table 3 3.0 11/2007 • Replaced 16 pin package drawing with 98ASA10614D, REV. B and replaced 24 pin package drawing with 98ARL10577D, REV. B. 4.0 2/2008 • Revised Siplified Application Diagram on page 1; Corrected typo - VM voltage from 15V to 5V. 5.0 8/2008 • Further Defined Thermal Resistance and Power Disapation in Table 2, Page 5 for both packages. ARCHIVE INFORMATION 4/2007 ARCHIVE INFORMATION 2.0 17511A 16 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MPC17511A Rev. 5.0 9/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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