NXP Semiconductors
Technical Data
Document Number: MPC17529
Rev. 4.0, 7/2016
0.7 A dual H-Bridge motor driver with
3.0 V/5.0 V compatible logic I/O
17529
The 17529 is a monolithic dual H-Bridge power IC ideal for portable electronic
applications containing bipolar step motors and/or brush DC-motors (e.g.,
cameras and disk drive head positioners).
The 17529 operates from 2.0 V to 6.8 V, with independent control of each HBridge via parallel MCU interface (3.0 V and 5.0 V compatible logic). The device
features an on-board charge pump, as well as built-in shoot-through current
protection and an undervoltage shutdown function.
The 17529 has four operating modes: forward, reverse, brake, and tri-stated
(high-impedance). The 17529 has a low total RDS(on) of 1.2 Ω (max at 25 °C).
The 17529’s low output resistance and high slew rate provides efficient drive for
many types of micromotors.
DUAL H-BRIDGE
EV SUFFIX (PB-FREE)
98ASA10616D
20-PIN VMFP
Features
• Low total RDS(on) 0.7 Ω (typ), 1.2 Ω (max) at 25 °C
• Output current 0.7 A (DC), 1.4 A (peak)
• Shoot-through current protection circuit
• 3.0 V/ 5.0 V CMOS-compatible inputs
• PWM control input frequency up to 200 kHz
• Built-in charge pump circuit
• Low power consumption
• Undervoltage detection and shutdown circuit
5.0 V
5.0 V
17529
VDD
VM 1/2
C1L
C1H
C2L
OUT1A
C2H
CRES
OUT1B
MCU
IN1A
IN1B
IN2A
IN2B
OE
OUT2A
GND
PGND1/2
OUT2B
N
S
Bipolar
Step
Motor
Figure 1. 17529 simplified application diagram
© 2016 NXP B.V.
EJ SUFFIX (PB-FREE)
98ASA00887D
20-PIN TSSOP
WITH EXPOSED PAD
ORDERABLE PARTS
Orderable parts
Table 1. Orderable part variations (1)
Part number
MPC17529EV/EL (2)
MPC17529EJ
Temperature (TA)
-20 °C to 65 °C
Package
20 VMFP
20 TSSOP (exposed pad)
Notes
1. To order parts in tape & reel, add the R2 suffix to the part number.
2. Not recommended for new designs.
17529
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NXP Semiconductors
INTERNAL BLOCK DIAGRAM
Internal block diagram
CRES
C2H
Charge
Pump
C1H
C1L
C2L
Low
Voltage
Shutdown
VDD
VM1
IN1A
OUT1A
H-Bridge
OUT1B
IN1B
VDD
PGND1
OE
Control
Logic
Level Shifter
Pre-driver
VM2
IN2A
OUT2A
H-Bridge
OUT2B
IN2B
PGND2
LGND
Figure 2. 17529 simplified internal block diagram
17529
NXP Semiconductors
3
PIN CONNECTIONS
Pin connections
Transparent
top view
VDD
IN1A
IN1B
OE
OUT2A
PGND1
OUT1A
VM1
CRES
C2H
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
LGND
IN2A
IN2B
VM2
OUT2B
PGND2
OUT1B
C2L
C1L
CIH
Figure 3. 17529 pin connections
Table 2. Pin function description
Pin
Pin name
Formal name
Definition
1
VDD
Control Circuit Power Supply
2
IN1A
Logic Input Control 1A
Logic input control of OUT1A (refer to Table 6, Truth table, page 8).
3
IN1B
Logic Input Control 1B
Logic input control of OUT1B (refer to Table 6, Truth table, page 8).
4
OE
Output Enable
5
OUT2A
H-Bridge Output 2A
6
PGND1
Power Ground 1
7
OUT1A
H-Bridge Output 1A
8
VM1
Motor Drive Power Supply 1
Positive power source connection for control circuit.
Logic output Enable control of H-Bridges (Low = True).
Output A of H-Bridge channel 2.
High-current power ground 1.
Output A of H-Bridge channel 1.
Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).
9
CRES
Pre-driver Power Supply
10
C2H
Charge Pump 2H
Internal triple charge pump output as pre-driver power supply.
Charge pump bucket capacitor 2 (positive pole).
11
C1H
Charge Pump 1H
Charge pump bucket capacitor 1 (positive pole).
12
C1L
Charge Pump 1L
Charge pump bucket capacitor 1 (negative pole).
Charge pump bucket capacitor 2 (negative pole).
13
C2L
Charge Pump 2L
14
OUT1B
H-Bridge Output 1B
15
PGND2
Power Ground 2
16
OUT2B
H-Bridge Output 2B
17
VM2
Motor Drive Power Supply 2
18
IN2B
Logic Input Control 2B
Logic input control of OUT2B (refer to Table 6, Truth table, page 8).
19
IN2A
Logic Input Control 2A
Logic input control of OUT2A (refer to Table 6, Truth table, page 8).
20
LGND
Logic Ground
Low-current logic signal ground.
-
-
-
Exposed pad on 20-Pin TSSOP
Output B of H-Bridge channel 1.
High-current power ground 2.
Output B of H-Bridge channel 2.
Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).
17529
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NXP Semiconductors
MAXIMUM RATINGS
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to
the device.
Symbol
Value
Unit
Motor Supply Voltage
-0.5 to 8.0
V
Charge Pump Output Voltage
-0.5 to 14
V
VDD
Logic Supply Voltage
-0.5 to 7.0
V
VIN
Signal Input Voltage
-0.5 to VDD + 0.5
V
0.7
1.4
A
±1500
± 200
V
VM
VCRES
IO
IOPK
VESD1
VESD2
Rating
Driver Output Current
• Continuous
• Peak
ESD Voltage
• Human Body Model
• Machine Model
Notes
(3)
(4)
(5)
TJ
Operating Junction Temperature
-20 to 150
°C
TA
Operating Ambient Temperature
-20 to 65
°C
TSTG
Storage Temperature Range
-65 to 150
°C
RθJA
Thermal Resistance
120
°C/W
Power Dissipation
1040
mW
(7)
°C
(8) (9)
PD
TPPRT
Peak Package Reflow Temperature During Reflow
Note 9
(6)
,
Notes
3. TA = 25 °C, 10 ms pulse at 200 ms interval.
4.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
5.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
6.
7.
Mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB).
TA = 25 °C.
8.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), Go to www. NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all
orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
9.
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STATIC ELECTRICAL CHARACTERISTICS
Static electrical characteristics
Table 4. Static electrical characteristics
Characteristics noted under conditions TA = 25 °C, VDD = VM = 5.0 V, GND = 0 V, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power (VM1, VM2, VDD)
VM
Motor Supply Voltage
2.0
5.0
6.8
V
VDD
Logic Supply Voltage
2.7
5.0
5.6
V
IQM
Driver Quiescent Supply Current (No Signal Input)
–
–
1.0
μA
–
–
1.0
mA
–
–
–
–
3.0
0.7
mA
1.5
2.0
2.5
V
–
0.7
1.2
Ohms
12
13
13.5
V
0.01
0.1
1.0
μF
0.0
–
VDD
V
VDD x 0.7
–
–
-1.0
–
–
–
–
–
50
–
VDD x 0.3
1.0
–
100
V
V
μA
μA
μA
IQVDD
Logic Quiescent Supply Current (No Signal Input)
IDVDD
ICRES
Operating Power Supply Current
• Logic Supply Current (11)
• Charge Pump Circuit Supply Current (12)
VDDDET
Low VDD Detection Voltage (13)
RDS(ON)
Driver Output ON Resistance (14)
(10)
Gate drive (C1L – C1H, C2L – C2H, CRES)
VCRES
CCP
Gate Drive Voltage
Recommended External Capacitance (C1L – C1H, C2L – C2H, CRES –
GND)
Control logic (OE, N1A, N1B, N2A, N2B)
VIN
Logic Input Voltage
VIH
VIL
IIH
IIL
Logic Inputs (2.7 V < VDD < 5.7 V)
• High-Level Input Voltage
• Low-Level Input Voltage
• High-Level Input Current
• Low-Level Input Current
• OE Pin Input Current Low
IOILOE
Notes
10.
IQVDD includes the current to pre-driver circuit.
11.
IVDD includes the current to pre-driver circuit at fIN = 100 kHz.
12.
At fIN = 20 kHz.
13.
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate voltage
VCRES is applied from an external source, VCRES = 7.5 V.
14.
Source + sink at IO = 0.7 A.
17529
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NXP Semiconductors
DYNAMIC ELECTRICAL CHARACTERISTICS
Dynamic electrical characteristics
Table 5. Dynamic electrical characteristics
Characteristics noted under conditions TA = 25 °C, VDD = VM = 5.0 V, GND = 0 V, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Input (IN1A, IN1B, OE, IN2A, IN2B)
f IN
Pulse Input Frequency
–
–
200
kHz
tR
Input Pulse Rise Time
–
–
1.0 (16)
μs
(15)
–
–
(16)
μs
(17)
Propagation Delay Time
• Turn-ON Time
• Turn-OFF Time
–
–
0.1
0.1
0.5
0.5
μs
(18)
t VGON
Charge Pump Wake-Up Time
–
1.0
3.0
ms
(19)
t VDDDET
Low-Voltage Detection Time
–
–
10
ms
tF
Input Pulse Fall Time
1.0
Output (OUT1A, OUT1B, OUT2A, OUT2B)
t PLH
t PHL
Notes
15.
16.
17.
18.
19.
Time is defined between 10% and 90%.
That is, the input waveform slope must be steeper than this.
Time is defined between 90% and 10%.
Load of Output is 8.0 Ω resistance.
CCP = 0.1 μF.
Timing diagrams
IN1,
IN2,
OE
50%
tPLH
tPHL
90%
OUTA,
OUTB
10%
Figure 4. tPLH, tPHL, and tPZH timing
VDDDETON
VDD
0.8 V/
1.5 V
2.5 V/3.5 V
VDDDETOFF
50%
tVDDDET
tVDDDET
90%
IM
0%
(> VDD (e.g., VM = 5.0 V, VDD = 3.0 V), in order to ensure full enhancement of the high-side
MOSFET channels.
5.0 V
17529
V
CRES < 14 V
RG > VCRES /0.02 Ω
RG
NC
NC
NC
NC
VDD VM
C1L
C1H
OUT1A
C2L
C2H
CRES
0.01 μF
OUT1B
OUT2A
IN1A
IN1B
IN2A
IN2B
MCU
OE
OUT2B
GND
NC = No Connect
Figure 7. 17529 Typical application diagram
Conducted electromotive force (CEMF) snubbing techniques
Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads.
Typical practice is to provide snubbing of voltage transients by placing a capacitor or zener at the supply pin (VM) (see Figure 8).
5.0 V
5.0 V
175XX
VDD
VM
5.0 V
5.0 V
175XX
VDD
VM
C1L
C1L
C1H
C1H
C2L
C2H
OUT
CRES
C2L
C2H
CRES
OUT
GND
OUT
OUT
GND
Figure 8. CEMF snubbing techniques
PCB layout
When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground pins to ensure proper
filtering from transients. For all high-current paths, use wide copper traces and shortest possible distances.
17529
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NXP Semiconductors
PACKAGE DIMENSIONS
Package dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number.
Package
Suffix
Package outline drawing number
20-PIN VMFP
EV
98ASA10616D
20-TSSOP
EJ
98ASA00887D
17529
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PACKAGE DIMENSIONS
17529
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PACKAGE DIMENSIONS
17529
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PACKAGE DIMENSIONS
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PACKAGE DIMENSIONS
17529
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PACKAGE DIMENSIONS
17529
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PACKAGE DIMENSIONS
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REVISION HISTORY
Revision history
Revision
Date
9/2005
•
•
Implemented Revision History page
Converted to Freescale format
12/2013
•
•
•
No technical changes
Revised back page
Updated document properties
7/2015
•
•
•
Added 98ASA00887D package information and updated tables where applicable
Added MPC17529EJ to the ordering information
Updated as per PCN # 16724
8/2015
•
Corrected the 98A package information for 20-pin TSSOP
10/2015
•
•
•
Added EP notation for TSSOP package.
Fixed notations for TSSOP in Orderable parts and Pin connections.
Updated Package dimensions 98A drawing for TSSOP
7/2016
•
Updated to NXP document form and style
2.0
3.0
4.0
Description of changes
17529
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NXP Semiconductors
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products herein.
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© 2016 NXP B.V.
Document Number: MPC17529
Rev. 4.0
7/2016
