MPC17533EVEL

Freescale Semiconductor Technical Data Document Number: MPC17533 Rev. 3.0, 12/2013 0.7 A 6.8 V Dual H-Bridge Motor Driver 17533 The 17533 is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar stepper motors and/or brush DC-motors (e.g., cameras and disk drive head positioners). The 17533 operates from 2.0 V to 6.8 V, with independent control of each H-Bridge via parallel MCU interface (3.0 V and 5.0 V compatible logic). The device features built-in shoot-through current protection and an undervoltage shutdown function. The 17533 has four operating modes: forward, reverse, brake, and tri-stated (high-impedance). The 17533 has a low total RDS(ON) of 1.2 Ω (max at 25 °C). The 17533’s low output resistance and high slew rate provides efficient drive for many types of micromotors. Features • Low total RDS(ON) 0.8 Ω (typ), 1.2 Ω (max) at 25 °C • Output current 0.7 A (DC), 1.4 A (peak) • Shoot-through current protection circuit • 3.0 V/ 5.0 V CMOS-compatible inputs • PWM control Input frequency up to 200 kHz • Built-in 2-channel H-Bridge driver • Low power consumption • Undervoltage detection and shutdown circuit EV SUFFIX (Pb-FREE) 98ASA10614D 16-PIN VMFP ORDERING INFORMATION Device (For Tape and Reel, add an R2 Suffix) Temperature Range (TA) Package MPC17533EV/EL -20 °C to 65 °C 16 VMFP 5.0 V 5.0 V 13 V H-BRIDGE MOTOR DRIVER 17533 VDD VG VM OUT1A OUT1B MCU IN1A IN1B IN2A IN2B OE OUT2A OUT2B N S Bipolar Step Motor GND Figure 1. 17533 Simplified Application Diagram © Freescale Semiconductor, Inc., 2012-2013. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VG Low Voltage Shutdown VDD VM1 IN1A OUT1A H-Bridge 1 OUT1B IN1B VDD PGND1 OE Control Logic Level Shifter Pre-driver VM2 IN2A OUT2A H-Bridge 2 OUT2B IN2B PGND2 LGND Figure 2. 17533 Simplified Internal Block Diagram 17533 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS OUT1A 1 16 PGND2 VM1 2 15 OUT2A IN1A 3 14 IN2A IN1B 4 13 IN2B VDD 5 12 VG OE 6 11 VM2 LGND 7 10 OUT2B OUT1B 8 9 PGND1 Figure 3. 17533 Pin Connections Table 1. PIN Function Description Pin Pin Name Formal Name Definition 1 OUT1A H-Bridge Output 1A 2 VM1 Motor Drive Power Supply 1 3 IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 5, Truth Table, page 7). 4 IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 5, Truth Table, page 7). 5 VDD Logic Supply 6 OE Output Enable Logic output Enable control of H-Bridges (Low = True). 7 LGND Logic Ground Low-current logic signal ground. 8 OUT1B H-Bridge Output 1B Output B of H-Bridge channel 1. 9 PGND1 Power Ground 1 10 OUT2B H-Bridge Output 2B 11 VM2 Motor Drive Power Supply 2 12 VG 13 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 5, Truth Table, page 7). 14 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 5, Truth Table, page 7). 15 OUT2A H-Bridge Output 2A 16 PGND2 Power Ground 2 Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). Control circuit power supply pin. High-current power ground 1. Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). Gate Driver Circuit Voltage Input Input pin for the gate drive voltage. Output A of H-Bridge channel 2. High-current power ground 2. 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit Motor Supply Voltage VM -0.5 to 8.0 V Gate Driver Circuit Power Supply Voltage VG -0.5 to 14 V Logic Supply Voltage VDD -0.5 to 7.0 V Signal Input Voltage VIN -0.5 to VDD + 0.5 V IO 0.7 IOPK 1.4 Human Body Model VESD1 ±1500 Machine Model VESD2 ± 200 Operating Junction Temperature TJ -55 to 150 °C Operating Ambient Temperature TA -20 to 65 °C TSTG -55 to 150 °C RθJA 150 °C/W PD 830 mW TPPRT Note 6 °C Driver Output Current A Continuous Peak (1) ESD Voltage (2) V Storage Temperature Range Thermal Resistance Power Dissipation (3) (4) Peak Package Reflow Temperature During Reflow (5), (6) Notes 1. TA = 25°C. 10 ms pulse at 200 ms intervals. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 3. 4. Mounted on 37 mm x 50 mm x 1.6 mm glass epoxy board mount. TA = 25 °C. 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 6. 17533 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25 °C, VDD = VM = 5.0 V, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Motor Supply Voltage VM 2.0 5.0 6.8 V Logic Supply Voltage VDD 2.7 5.0 5.7 V IQM – – 1.0 QVDD I QVG – – 20 – – 150 Logic Supply Current (8) IVDD – – 3.0 Gate Driver Circuit Power Supply Current (9) IVG – – 0.7 VDDDET 1.5 2.0 2.5 RDS(ON) – 0.8 1.2 RDS(ON)2 – – 1.5 VG 12 13 13.5 V VIN 0 – VDD V High-Level Input Voltage VIH VDD x 0.7 – – V Low-Level Input Voltage VIL – – VDD x 0.3 V High-Level Input Current IIH – – 1.0 μA IIL -1.0 – – μA IIL-OE – 50 100 μA POWER μA Quiescent Power Supply Current Driver Circuit Power Supply Current I Logic Supply Current (7) Gate Driver Circuit Power Supply Current Operating Power Supply Current Low VDD Detection Voltage (10) mA Ω Driver Output ON Resistance Source + Sink at IO = 0.7 A(11) VG = 9.5 V, VM = 5.0 V, TA = 25 °C(12) V GATE DRIVE Gate Drive Circuit Power Supply Voltage CONTROL LOGIC Logic Input Voltage Logic Inputs (2.7 V < VDD < 5.7 V) Low-Level Input Current OE Pin Input Current Low Notes 7. IQVDD includes the current to pre-driver circuit. 8. IV 9. At fIN = 20 kHz. DD includes the current to pre-driver circuit at fIN = 100 kHz. 10. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When gate voltage VG is applied from an external source, VG = 7.5 V. 11. 12. The total H-Bridge ON resistance when VG is 13 V. Increased RDS(ON) value as the result of a reduced VG value of 9.5 V. 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25 °C, VDD = VM = 5.0 V, GND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit f IN – – 200 kHz tR – – 1.0 μs tF – INPUT Pulse Input Frequency Input Pulse Rise Time (13) Input Pulse Fall Time (15) (14) – 1.0 μs (14) OUTPUT Propagation Delay Time (16) μs Turn-ON Time t PLH – 0.1 0.5 Turn-OFF Time t PHL – 0.1 0.5 tVDDDET – – 10 Low Voltage Detection Notes 13. 14. 15. 16. 17. Time(17) ms Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Load of Output is 8.0 Ω resistance. see Figure 4 See Figure 5 17533 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS VDDDETon IN1, IN2, OE 50% 2.5 V VDDDEToff VDD 50% 1.5 V tPLH tPHL tVDDDET 90% 90% OUTA, OUTB tVDDDET 0% (> VDD (e.g., VM = 5.0 V, VDD = 3.0 V), in order to ensure full enhancement of the high-side MOSFET channels. 5.0 V 17533 VDD VG < 14 V VM OUT1A RG > VG /0.02 Ω VG RG 0.01 μF OUT1B IN1A IN1B IN2A IN2B MCU OE OUT2A OUT2B GND Figure 6. 17533 Typical Application Diagram CEMF SNUBBING TECHNIQUES PCB LAYOUT Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commuting currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a zener or a capacitor at the supply pin (VM) (see Figure 7). When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground pins to ensure proper filtering from transients. For all highcurrent paths, use wide copper traces and shortest possible distances. 5.0 V 5.0 V 17533 VDD VM 5.0 V 5.0 V 17533 VDD VM OUT OUT OUT OUT OUT OUT OUT GND OUT GND Figure 7. CEMF Snubbing Techniques 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 9 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 6. Package 16-PIN VMFP Suffix EV Package Outline Drawing Number 98ASA10614D 17533 10 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EV (Pb-FREE) SUFFIX 16-LEAD VMFP 98ASA10614D ISSUE B 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 11 PACKAGING PACKAGE DIMENSIONS EV (Pb-FREE) SUFFIX 16-LEAD VMFP 98ASA10614D ISSUE B 17533 12 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 2.0 5/2006 • • Converted to Freescale format Added Revision History page 3.0 7/2006 • • • Updated to the prevailing form and style Corrected device isometric drawing on page 1 Added RoHS compliance 12/2013 • • • No technical changes Revised back page Updated document properties 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 13 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Home Page: freescale.com Freescale products. There are no express or implied copyright licenses granted hereunder to design or Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale fabricate any integrated circuits based on the information in this document. makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Document Number: MPC17533 Rev. 3.0 12/2013