Freescale Semiconductor, Inc.
Product Brief
MPC535PB/D
Rev. 0, 2/2003
Freescale Semiconductor, Inc...
MPC535/MPC536
Product Brief
This document provides an overview of the MPC535/MPC536 microcontrollers, including a
block diagram showing the major modular components, sections that list the major features,
and differences between the MPC535/MPC536 and the MPC555. The MPC535 and MPC536
devices are members of the Motorola MPC500 RISC Microcontroller family. The parts herein
will be referred to only as MPC535 unless specific parts need to be referenced.
Table 1. MPC535/MPC536 Features
1
Device
Flash
Code Compression
MPC535
1 Mbyte
Code compression not supported
MPC536
1 Mbyte
Code compression supported
Introduction
The MPC535 device offers the following features:
•
•
•
•
•
•
•
PowerPC™ core with a floating point unit (FPU) and a burst buffer controller (BBC)
Unified system integration unit (USIU), a flexible memory controller, and improved
interrupt controller
1 Mbyte of Flash memory (UC3F)
— Typical endurance of 100,000 write/erase cycles @ 25ºC
— Typical data retention of 100 years @ 25ºC
36 Kbytes of static RAM (two CALRAM modules)
— 8 Kbytes of normal access or overlay access (sixteen 512-byte regions)
— 4 Kbytes in CALRAM A, 4 Kbytes in CALRAM B
A 22-timer channel modular I/O system (MIOS14)
— Same as MIOS1 plus a real-time clock sub-module (MRTCSM), 4 counter
sub-modules (MCSM), and 4 PWM sub-modules (MPWMSM)
One TouCAN module (TouCAN_B)
One enhanced queued analog to digital converter (QADC64E A).
•
One queued serial multi-channel module (QSMCM A) which contains a queued
serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)
•
-40°C – 85°C ambient temperature
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Block Diagram
•
Debug features:
— A Nexus debug port (class 3) – IEEE-ISTO 5001-1999
— JTAG and background debug mode (BDM)
•
1.1
Packaging and Electrical
Block Diagram
Figure 1 is a block diagram of the MPC535.
JTAG
Freescale Semiconductor, Inc...
Burst
Buffer
Controller 2
512 Kbytes
Flash
512 Kbytes
Flash
U-Bus
DECRAM
(4Kbytes)
MPC500
Core
+
FP
E-Bus
USIU
4 Kbyte CALRAM B
READI
4 Kbyte Overlay
L2U
L-Bus
32 Kbyte CALRAM A
28 Kbytes SRAM
No Overlay
4 Kbyte Overlay
QADC64E
UIMB
I/F
QSMCM
IMB3
Tou
CAN
MIOS14
Figure 1. MPC535 Block Diagram
1.2
Detailed Feature List
The MPC535 key features are explained in the following sections.
1.2.1
•
•
2
High Performance CPU System
Fully static design
Four major power saving modes
— On, doze, sleep, deep-sleep and power-down
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
1.2.2
•
Freescale Semiconductor, Inc...
1.2.3
•
•
•
•
•
•
•
•
•
1.2.4
•
1.2.5
•
•
•
Detailed Feature List
RISC MCU Central Processing Unit (RCPU)
High-performance core
— PowerPC single issue integer core
— Precise exception model
— Floating point
— Code compression (MPC536 only)
– Compression reduces usage of internal or external Flash memory
– Compression optimized for automotive (non-cached) applications
– New compression scheme decreases code size to 40% –50% of source
MPC500 System Interface (USIU)
MPC500 system interface (USIU, BBC, L2U)
Periodic interrupt timer, bus monitor, clocks, decrementer and time base
Clock synthesizer, power management, reset controller
External bus tolerates 5-V inputs, provides 2.6-V outputs
Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40
internal interrupts
IEEE 1149.1 JTAG test access port
Bus supports multiple master designs
USIU supports dual-mapping of Flash to move part of internal Flash memory to external bus for
development
External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions
per memory cycle
Burst Buffer Controller (BBC) Module
Exception vector table relocation features allow exception table to be relocated to following
locations:
— 0x0000 0000 - 0x0000 1FFF (normal MPC500 exception table location)
— 0x0001 0000 - 0x0001 1FFF (0 + 64 Kbytes; second page of internal Flash)
— Second internal Flash module
— Internal SRAM
— 0x0FFF_0100 (external memory space; normal MPC500 exception table location)
Flexible Memory Protection Unit
Flexible memory protection units in BBC (IMPU) and L2U (DMPU)
Default attributes available in one global entry
Attribute support for speculative accesses
MOTOROLA
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
3
Detailed Feature List
1.2.6
Freescale Semiconductor, Inc...
•
•
•
•
•
•
•
•
•
1.2.7
•
Freescale Semiconductor, Inc.
Memory Controller
Flexible chip selects via memory controller
24-bit address and 32-bit data buses
4- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support
Four-beat transfer bursts, two-clock minimum bus transactions
Use with SRAM, EPROM, Flash and other peripherals
Byte selects or write enables
32-bit address decodes with bit masks
Four instruction regions
Four data regions
1 Mbyte of CDR3 Flash EEPROM Memory (UC3F)
•
•
•
•
•
1 Mbyte Flash
— Two UC3F modules, 512 Kbytes each
Page mode read
Block (64-Kbyte) erasable
External 4.75- to 5.25-V VPP program and erase power supply
Typical endurance of 100,000 write/erase cycles @ 25ºC
Typical data retention of 100 years @ 25ºC
1.2.8
36-Kbyte Static RAM (CALRAM)
•
36-Kbyte static calibration RAM
— Composed of 4-Kbyte and 32-Kbyte CALRAM modules
Fast access: one clock
Keep-alive power
Soft defect detection (SDD)
4 Kbyte calibration (overlay) RAM per module (8 Kbytes total)
Eight 512-byte overlay regions per module (16 regions total)
•
•
•
•
•
1.2.9
•
•
•
•
•
General Purpose I/O Support (GPIO)
General-purpose I/O support
Address (24) and data (32) pins can be used as GPIO in single-chip mode
16 GPIO in MIOS14
Many peripheral pins can be used as GPIO when not used as primary functions
5-V outputs with slew rate control
1.2.10 Debug Features
•
•
•
•
4
Extensive system debug support
On-chip watchpoints and breakpoints
Program flow tracking
Background debug mode (BDM)
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Detailed Feature List
1.2.10.1 Nexus Debug Port (Class 3)
•
•
Nexus/IEEE – ISTO 5001-1999 debug port (Class 3)
Nine- or 16-pin interface
1.2.11 Integrated I/O System
•
True 5-V I/O
1.2.11.1 22-Channel Modular I/O System (MIOS14)
Freescale Semiconductor, Inc...
•
•
•
•
•
22-channel MIOS timer (MIOS14)
Six modulus counter submodules (MCSM)
— Four additional MCSM submodules compared to MIOS1
10 double action submodules (DASM).
12 dedicated PWM submodules (PWMSM)
— Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins)
MIOS real-time clock submodule (MRTCSM) provides low power clock/counter
— Requires external 32-KHz crystal
— Uses four pins: two for 32-KHz crystal, two for power/ground.
1.2.12 One Enhanced Queued Analog-to-Digital Converter
Module (QADC64E)
•
•
•
•
•
One enhanced queued analog to digital converter (QADC64E A) with 16 total analog channels.
10 bit A/D converter with internal sample/hold
— Typical conversion time is 4 µs (250-Kbyte samples/sec)
— Two conversion command queues of variable length
Automated queue modes initiated by:
— External edge trigger/level gate
— Software command
— Periodic/interval timer, assignable to both queue 1 and 2
64 result registers
— Output data is right or left justified, signed or unsigned
Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference
voltage
1.2.13 One CAN 2.0B Controller (TouCAN) Module
•
•
•
•
•
•
One TouCAN module (TouCAN_B)
16 message buffers, programmable I/O mode
Maskable interrupts
Programmable loopback for self-test operation
Independent of the transmission medium (external transceiver is assumed)
Open network architecture, multimaster concept
MOTOROLA
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
5
Detailed Feature List
•
•
•
Freescale Semiconductor, Inc.
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode, with programmable wake up on bus activity
1.2.14 Queued Serial Multi-Channel Module (QSMCM)
•
Freescale Semiconductor, Inc...
•
•
One queued serial module with one queued-SPI and two SCI (QSMCM_A)
— QSMCM_A matches full MPC555 QSMCM functionality
Queued-SPI
— Provides full-duplex communication port for peripheral expansion or interprocessor
communication
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-select pins support up to 16 devices
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient
interfacing to serial analog-to-digital (A/D) converters
SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer on one SCI
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,
or a new address byte is received
1.2.15 Electrical Specifications and Packaging
•
•
40 MHz operation
-40°C – 85°C ambient temperature
•
2.6 V ± 0.1 V external bus
— External bus is compatible with external memory devices operating from 2.5 V to 3.4 V.
— Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes.
2.6 ± 0.1 V internal logic
5-V I/O (5.0 ± 0.25 V)
Plastic ball grid array (PBGA) packaging
– 388 ball PBGA
– 27 mm x 27 mm body size
1.0 mm ball pitch
•
•
•
•
6
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
MPC535 Optional Features
1.3
MPC535 Optional Features
The following features of the MPC535 are optional features and may not appear in certain configurations:
2
•
40-MHz operation
•
MPC536 supports code compression
Differences between the MPC535 and the MPC555
The MPC535 is an enhanced version of the MPC555. Most functional features of the MPC555 are
unchanged on the MPC535. Table 2 shows the high level differences.
Table 2. Differences Between Modules of the MPC555 and the MPC535
Freescale Semiconductor, Inc...
Module
MPC555
MPC535
CPU Core
No Change
BBC
BBC with improved code compression 1
BBC
L2U
No Change
SRAM
26-Kbytes
36-Kbyte CALRAM with overlay features
Flash
448-Kbyte CMF
1-Mbyte UC3F
(new programming, etc.)
USIU
USIU
USIU with enhanced interrupt controller
JTAG
No Change
READI
None
New Module
UIMB
QADC64
No Change
2 QADC64 (16 channels on each QADC
for 32 total channels)
QSMCM
1 QADC64E
( 16 channels accessible)
(1) No Change (1)
MIOS
MIOS1
TouCAN
MIOS14: MIOS1 with real-time clock
(MRTCSM), 4 more PWMSMs and 4 more
MCSMs
(2) No Change (1)
Power Supplies
—
1
40 MHz with two power supplies:
nominal 3.3-V to 5.0-V power supplies
40 MHz with two power supplies:
5.0-V I/O, 2.6-V internal logic
Available on some options.
MOTOROLA
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
7
Freescale Semiconductor, Inc.
Additional MPC535 Differences
2.1
Additional MPC535 Differences
The following are additional differences between the MPC555 and the MPC535.
•
•
Freescale Semiconductor, Inc...
•
•
•
•
•
•
•
•
•
•
•
8
SPI (MISO, MOSI, and SCK) pin drive.
— MPC535 provides 21-ns rise/fall with 200-pf load using CMOS (20%/70%) levels
GPIO on MODCK1 pin outputs only 2.6 V
— MODCK1 pin is in keep-alive power section with no 5-V rail available
— 5.0-V compatibility modes
– Input is 5-V friendly
– 2.6-V output has less slew rate control
– 2.6-V: VOH = 2.3 V
Power supplies for external bus pins
— QVDDL is quiet supply to hold non-switching outputs quiet even when noisy supply
(NVDDL) sags
— QVDDL supplies pre-drive and other pad logic
— NVDDL only supplies final PMOS driver stage
— QVDDL and NVDDL shorted on customer board after filtering
Pull-up and pull-down changes during PORESET and HRESET
— All 2.6-V/5-V pads (external bus: address/data/control) pull down at reset
— All 5-V pads pull up at reset
— Additional control granularity in the PDMCR register
No pull-ups on QSMCM SCI receive pads
A_RXD1_QGPI1, A_RXD2_QGPI2 pins do not have weak pull-up during reset or any other time
CLKOUT has 3 drive strength options
— Better matches drive to requirements to reduce EMI
— 25, 50, 100 pf instead of 45 and 90 pf
Change reset value of ENGCLK to maximum divide (crystal/128)
— For a 4-MHz crystal, this is 31.25 KHz
– ENGCLK is selectable between 2.6 V and 5 V
A daisy chain between UC3F modules allows either module to provide the reset configuration
word (RCW)
Censorship operation
— A RCW bit controls whether or not the entire UC3F can be erased while censorship is violated
BBC SPRs (PPC regs) access in two clocks instead of one clock
CALRAM internal protection block size is 8 Kbytes
— Instead of 4 Kbytes on MPC555 LRAM
CALRAM causes machine check exception instead of data storage interrupt (DSI) exception in
certain cases
— For non-overlay CPU core accesses, a DSI exception is taken
— For overlay accesses and any non-core access (slave mode), a machine check exception is
taken
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Additional MPC535 Differences
•
CALRAM causes DSI exception only if the data relocation (DR) bit in the core machine state
register, MSR[DR], is set.
— L2U on MPC555 already followed this protocol, but the LRAM did not. Now all L-bus
peripherals follow this protocol.
— The MSR[DR] bit is described in the reference manual for more information.
•
Four additional PRDS control bits were added to the USIU to allow more granularity of PRDS
control on a part
•
BBC includes a 4-Kbyte DECRAM that can be used if compression is not used or is not available.
Freescale Semiconductor, Inc...
3
SRAM Keep-Alive Power Behavior
The SRAM has three keep-alive power pins (VDDSRAM1, VDDSRAM2, and VDDSRAM3). These pins
provide keep-alive power to the SRAM arrays in the CALRAM modules.
The VDDSRAM1 pin powers the 32-Kbyte CALRAM A during keep-alive while power is off to the
MPC535 (except for the keep-alive power supplies). CALRAM A keeps all of its 32 Kbytes powered during
power down.
The VDDSRAM2 pin powers the 4-Kbyte CALRAM B module. The CALRAM modules only power their
arrays from the VDDSRAM pins during keep-alive. During normal operation, they are powered by the
normal internal VDD of the part.
The 4-Kbyte DECRAM in the BBC module power its arrays via the VDDSRAM3 pin during keep-alive and
are supplied by VDD during normal operation.
4
MPC535 Memory Map
The internal memory map is organized as a single 4-Mbyte block. This is shown in Figure 3. This block can
be moved to one of eight different locations. The internal memory space is divided into the following
sections:
•
Flash memory (1 Mbyte) — U-bus memory
•
Static RAM memory (36 Kbytes CALRAM) — L-bus memory
•
Control registers and IMB3 modules (64 Kbytes), partitioned as
— USIU and flash control registers
— UIMB interface and IMB3 modules
— CALRAM and READI control registers (L-bus control register space)
The internal memory block can reside in one of eight possible 4-Mbyte memory spaces. These eight
locations are the first eight 4-Mbyte memory blocks starting with address 0x0000 0000, as shown in
Figure 2. There is a user programmable register in the USIU to configure the internal memory map to one
of the eight possible locations. Programmability of internal memory map location allows multiple chip
system.
The IMB3 address space block in Figure 3 shows memory allocation for IMB3 modules. It does not show
the actual memory space required for individual modules. All modules are mapped to the low address,
numerically, of the memory allocated for that module in the IMB3 address space.
MOTOROLA
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
9
Freescale Semiconductor, Inc.
Additional MPC535 Differences
Internal 4-Mbyte Memory Block
(Resides in one of eight locations)
0x0000 0000
0x003F FFFF
0x0040 0000
0x007F FFFF
0x0080 0000
0x00BF FFFF
0x00C0 0000
Freescale Semiconductor, Inc...
0x00FF FFFF
0x0100 0000
0x013F FFFF
0x0140 0000
0x017F FFFF
0x0180 0000
0x01BF FFFF
0x01C0 0000
0x01FF FFFF
0xFFFF FFFF
Figure 2. Memory Map
10
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Additional MPC535 Differences
0x00 0000
0x07 FFFF
0x08 0000
0x0F FFFF
0x10 0000
Freescale Semiconductor, Inc...
0x2F 7FFF
Ox2F 8000
0x2F 8FFF
0x2F 9000
0x2F 9FFF
0x2F A000
UC3F_A Flash
512 Kbytes
UC3F_B Flash
512 Kbytes
0x37 FFFF
0x38 0000
0x2F C000
UC3F_A Control
(64 bytes)
0x2F C800
UC3F_B Control
(64 bytes)
0x2F C840
Reserved for Flash
(2,016 Kbytes)
DECRAM
4 Kbytes
Reserved for IMB
480 Kbytes
CALRAM/
Readi Control
256 bytes
0x38 00FF
0x38 0100 Reserved (L-bus Control)
~32 Kbytes
0x38 3FFF
0x38 4000
Reserved (L-bus Mem)
444 Kbytes
Reserved* (144 bytes)
0x30 0080
Reserved (3952 bytes)
0x3F 7FFF
0x3F 8000
All 4-Kbytes can be
Overlay Section
CALRAM_B (4 Kbyte)
CALRAM_A
0x3F FFFF
(32 Kbyte)
4-Kbyte Overlay Section
0x30 0090
0x30 1000
Reserved* (10 Kbytes)
0x30 2000
Reserved (2 Kbytes)
0x30 3800
0x30 4000
Reserved* (2 Kbytes)
0x30 4400
QADC64_A (1 Kbytes)
0x30 4800
Reserved* (1 Kbytes)
0x30 4C00
QSMCM_A (1 Kbytes)
0x30 5000
Reserved* (1 Kbytes)
0x30 5400
Reserved (1 Kbytes)
0x30 5800
Reserved* (1 Kbytes)
0x30 5C00
MIOS14 (4 Kbytes)
0x3F 6FFF
0x3F 7000
0x2F C87F
0x30 0000
Reserved
BBC Control Registers
8 Kbytes
0x2F BFFF
0x2F C000 USIU & Flash Control
0x2F FFFF
16 Kbytes
0x30 0000
UIMB I/F & IMB
Modules
32 Kbytes
0x30 7FFF
0x30 8000
USIU Control Registers
0x30 6000
Reserved* (1 Kbytes)
0x30 7000
TOUCAN_B (1 Kbytes)
0x30 7400
Reserved* (1 Kbytes)
0x30 7800
Reserved (896 bytes)
0x30 7900
UIMB Control Registers
(128 bytes)
0x30 7F80
0x30 7FFF
Note: Reserved, do not write to this space.
Figure 3. Internal Memory Block
MOTOROLA
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
11
12
VDDRTC
B
C
VSS
VDD
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
ADDR_
ADDR_
ADDR_ ADDR_
ADDR_
ADDR_
ADDR_
ADDR_
ADDR_
ADDR_
ADDR_
VSS
VDD
2
VSS
1
QVDDL
NC
AE QVDDL
SGPIOA29
AD ADDR_
SGPIOA28
AC ADDR_
Figure 4. MPC535 Pinout Diagram
MOTOROLA
DATA_
DATA_
3
4
SGPIOD0 SGPIOD2
DATA_
SGPIOD1
VDD
VSS
QVDDL
VDD
VSS
QVDDL
SGPIOA26 SGPIOA27 SGPIOA31
AB ADDR_
SGPIOA24 SGPIOA25 SGPIOA15 SGPIOA30
ADDR_
SGPIOA22 SGPIOA23 SGPIOA13 SGPIOA14
AA ADDR_
AF
ADDR_
SGPIOA20 SGPIOA21 SGPIOA11 SGPIOA12
ADDR_
Y ADDR_
W
ADDR_
NVDDL
SGPIOA18 SGPIOA19 SGPIOA9 SGPIOA10
V ADDR_
SGPIOA16 SGPIOA17 SGPIOA8
U ADDR_
ADDR_
DATA_
DATA_
5
6
DATA_
SGPIOD6
DATA_
DATA_
SGPIOD5
SGPIOD4
DATA_
SGPIOD3
NC
13
VSS
VSS
VSS
VSS
14
VSS
VSS
VSS
VSS
15
QVDDL
QVDDL
QVDDL
QVDDL
NVDDL
DATA_
DATA_
SGPIOD24 SGPIOD22 SGPIOD20
DATA_
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SGPIOC7_
NVDDL IRQOUT_ NVDDL
B_LWP0
VSS
VSS
VSS
VSS
VSS
VSS
7
SGPIOD8
DATA_
DATA_
SGPIOD7
8
SGPIOD10
DATA_
DATA_
SGPIOD9
9
SGPIOD12
DATA_
SGPIOD11
DATA_
DATA_
DATA_
DATA_
10
11
12
SGPIOD14 SGPIOD16 SGPIOD18
13
IRQ1_B_
RSV_B_
SGPIOC1
IRQ3_B_KR
DATA_
DATA_
DATA_
_B_RETRY_B
SGPIOD13 SGPIOD15 SGPIOD17 _SGPIOC3
16
VSS
VSS
17
VDDH
VSS
ETRIG1 B_CNRX0
ETRIG2
VSS
14
15
16
18
CS3_B
VSS
VSS
VSS
VSS
17
18
CS2_B
CS0_B
WE_B_ CS1_B
AT2
NVDDL
OE_B WE_B_
AT0
IRQ2_B_
CR_B_
SGPIOC2
WE_B_
AT1
VSS
VSS
VSS
VSS
VSS
VSS
BG_B_
BR_B_ IRQ0_B_ WE_B_
VF0_
LWP1 VF1_IWP2 SGPIOC0 AT3
BB_B_ RD_WR
VF2_
_B
IWP3
IRQ4_
DATA_
DATA_
DATA_
DATA_
DATA_
DATA_
DATA_
DATA_
B_AT2 TEA_B
SGPIOD31 SGPIOD30 SGPIOD28 SGPIOD26 SGPIOD25 SGPIOD23 SGPIOD21 SGPIOD19 _SGPIOC4
SGPIOD29 SGPIOD27
MDO_3
ADDR_
VSS
IWP0_ SGPIOC6_
FRZ_
VFLS0
PTR_B
MSEO
_B
T
VSS
IWP1_
VFLS1
MDO_2
TDO_
DSDO
VSS
R MDO_1
MDO_0
MCKO
JCOMP
P MDO_7_
MPIO32B7
MPIO32B10 MPIO32B8 MPIO32B9
VSS
N
L
VSS
VSS
VSS
VSS
12
NOTE: This is a top down view of the balls.
AN47_
AN59_A_
ANZ_A_ AN51_A_ AN55_A_ PQA7
PQB7
PQA3
PQB3
VSS
VSS
TMS MDO_4_ MDO_6_ MDO_5_
VDDH
AN82
AN54_A_
AN46_
ANY_A_ AN50_A_ MA2_ AN57_A_
PQB6
PQA5
PQB2
PQA2
11
VSS
VSS
VDD
VSS
VSS
VSS
VSS
10
VSSA
AN52_A_
AN49_A_ MA0_ AN56_A_ AN58_A_
PQB5
PQA4
PQA6
PQA0
9
VDDA
8
AN53_A_
MA1_
PQA1
M TDI_DSDI EVTI_B RSTI_B MSEI_B
MDI_1
VDDH
VSS
VSS
7
AN48_A_
PQB4
VSS
TCK_
DSCK
MDI_0
VSS
VSS
VSS
VSS
VSS
VDDSRAM3
NVDDL
VSS
VSS
VSS
VSS
VDD
AN45_
ANX
_A_PQB1
VSS
6
VSS
5
VSS
MCKI
VSS
VSS
VSS
VSS
J
VSS
VSS
VSS
VSS
VSSRTC
VSS
K
VDDSRAM2
VSS
XTAL32 B_CNTX0 VDDSRAM1
H
G
F
E
4
VRL
19
TSIZ1
BURST
_B
TSIZ0
BI_B_
STS_B
VSS
VSS
VSS
VSS
19
20
21
VDD
VSS
VSS
VSS
VSS
20
TA_B
TS_B
21
EPEE
BDIP_B
B0EPEE CLKOUT
VDDH
VSS
VSS
VSS
VSS
22
22
ENGCLK_
BUCLK
NC
VDD
VSS
NVDDL
VSS
VSS
VSS
23
25
MPWM17
VSS
VSS
MDA31
MDA27
MDA29
MPWM0 MPWM1
MDA28
VF2_
MPIO
32B2
VF1_
MPIO
32B1
VSS
Y
23
NC
VDD
VSS
QVDDL
24
VDD
VSS
XFC
25
VSS
26
QVDDL
QVDDL VDDSYN
IRQ5_B_
QVDDL SGPIOC5_
MODCK1
SRESET IRQ7_B_ VSSSYN
MODCK3
_B
AF
AE
AD
AC
AB
KAPWR
HRESET IRQ6_B_ RSTCONF_ EXTAL
MODCK2 B_TEXP
_B
VSSF
NC
W
V
U
T
R
P
AA
VSS
EXTCLK
VFLASH A_PCS1_ PULLSEL
QGPIO1
A_RXD2_
A_TXD2_
QPI2
QGPO2 (C3F_SUP2)
A_PCS3_
QGPIO3
(C3F_IOUT)
A_RXD1_
A_MOSI_
QPI1
QGPIO5
(C3F_SUP1)
VSS
VSS
VSS
VSS
VSS
A_SCK_
QGPIO6
(C3F_CLK)
A_MISO_
QGPIO4
VSS
VSS
VSS
N
M
MPWM4_ VFLS0_
MPIO
MPIO
32B3
32B5
VSS
L
VF0_
MPIO
32B0
MPWM19
K
MPIO
32B13
J
H
G
F
E
D
C
B
A
XTAL
PORESET_B
_TRST_B
VDDF
NVDDL
A_PCS0_SS
_B_QGPIO0
A_PCS2_
QGPIO2
A_TXD1_
QGPO1
VSS
VSS
VDDH
MPIO
32B15
MPIO
32B14
VFLS1_
MPIO
32B4
MDA14
MDA15
MPWM21_
MPIO
32B12
MPWM20_
MPIO
MPWM3 MPWM2 MPWM16
32B11
MDA30
MDA12
MDA13
VSS
VSS
VDD
VSS
26
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VSS
24
MPWM5_ MPWM18
MDA11
MPIO
32B6
VDD
VSS
VSS
VSS
VSS
5
D EXTAL32
VSS
A
3
VRH
AN44_
VDD ANW
ALTREF
_A_PQB0
2
VSS
1
VDD
Freescale Semiconductor, Inc...
Additional MPC535 Differences
Freescale Semiconductor, Inc.
MPC535 Pinout Diagram
Figure 4 shows the pinout for the MPC535.
Freescale Semiconductor, Inc.
Additional MPC535 Differences
Freescale Semiconductor, Inc...
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
13
Freescale Semiconductor, Inc.
Additional MPC535 Differences
Freescale Semiconductor, Inc...
THIS PAGE INTENTIONALLY LEFT BLANK
14
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Additional MPC535 Differences
Freescale Semiconductor, Inc...
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
MPC535/MPC536 Product Brief
For More Information On This Product,
Go to: www.freescale.com
15
Freescale Semiconductor, Inc.
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447
JAPAN:
Freescale Semiconductor, Inc...
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu Minato-ku
Tokyo 106-8573 Japan
81-3-3440-3569
Information in this document is provided solely to enable system and software implementers to use
ASIA/PACIFIC:
Motorola products. There are no express or implied copyright licenses granted hereunder to design
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre, 2 Dai King Street
Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
or fabricate any integrated circuits or integrated circuits based on the information in this document.
TECHNICAL INFORMATION CENTER:
use of any product or circuit, and specifically disclaims any and all liability, including without
1-800-521-6274
limitation consequential or incidental damages. “Typical” parameters which may be provided in
HOME PAGE:
http://www.motorola.com/semiconductors
Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does Motorola assume any liability arising out of the application or
Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated
for each customer application by customer’s technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any other application in which
the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.
digital dna is a trademark of Motorola, Inc. The described product contains a PowerPC processor
core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product
or service names are the property of their respective owners. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2003
MPC535PB/D
For More Information On This Product,
Go to: www.freescale.com
