MPC561/MPC563 Reference Manual
Additional Devices Supported:
MPC562
MPC564
MPC561RM
REV 1.2
08/2005
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MPC561RM
REV 1.2
08/2005
Contents
Paragraph
Number
Title
Page
Number
About This Book lxxvii
Audience ..................................................................................................................... lxxvii
Organization ................................................................................................................ lxxvii
Suggested Reading ........................................................................................................ lxxx
Conventions and Nomenclature .................................................................................... lxxx
Notational Conventions ............................................................................................... lxxxi
Acronyms and Abbreviations ..................................................................................... lxxxii
References .................................................................................................................. lxxxiii
Chapter 1
Overview
1.1
1.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.1.5
1.3.1.6
1.3.1.7
1.3.1.8
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.3.3.5
1.3.3.6
1.4
1.5
1.6
1.7
1.8
Introduction ..................................................................................................................... 1-1
Block Diagram ................................................................................................................ 1-2
Key Features ................................................................................................................... 1-3
High-Performance CPU System ................................................................................. 1-3
RISC MCU Central Processing Unit (RCPU) ........................................................ 1-4
Unified System Interface Unit (USIU) ................................................................... 1-4
Burst Buffer Controller (BBC) Module .................................................................. 1-4
Flexible Memory Protection Unit ........................................................................... 1-5
Memory Controller ................................................................................................. 1-5
512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) –
MPC563/MPC564 Only 1-5
32-Kbyte Static RAM (CALRAM) ........................................................................ 1-6
General Purpose I/O Support (GPIO) ..................................................................... 1-6
Nexus Debug Port (Class 3) ........................................................................................ 1-6
Integrated I/O System ................................................................................................. 1-6
Two Time Processor Units (TPU3) ........................................................................ 1-6
22-Channel Modular I/O System (MIOS14) .......................................................... 1-6
Two Enhanced Queued Analog-to-Digital Converter Modules (QADC64E) ........ 1-7
Three CAN 2.0B Controller (TouCAN) Modules .................................................. 1-7
Queued Serial Multi-Channel Module (QSMCM) ................................................. 1-8
Peripheral Pin Multiplexing (PPM) ........................................................................ 1-8
MPC561/MPC563 Optional Features ............................................................................. 1-9
Comparison of MPC561/MPC563 and MPC555 ........................................................... 1-9
Additional MPC561/MPC563 Differences ................................................................... 1-10
SRAM Keep-Alive Power Behavior ............................................................................. 1-11
MPC561/MPC563 Address Map .................................................................................. 1-11
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
1.9
Title
Page
Number
Supporting Documentation List .................................................................................... 1-14
Chapter 2
Signal Descriptions
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.4.1
2.6.4.2
2.6.4.3
2.6.4.4
2.6.5
Signal Groupings ............................................................................................................ 2-1
Signal Summary .............................................................................................................. 2-3
MPC561/MPC563 Signal Multiplexing ................................................................... 2-20
READI Port Signal Sharing ...................................................................................... 2-21
Pad Module Configuration Register (PDMCR) ............................................................ 2-22
Pad Module Configuration Register (PDMCR2) .......................................................... 2-23
MPC561/MPC563 Development Support Signal Sharing ............................................ 2-28
JTAG Mode Selection .............................................................................................. 2-29
BDM Mode Selection ............................................................................................... 2-30
Nexus Mode Selection .............................................................................................. 2-30
Reset State ..................................................................................................................... 2-31
Signal Functionality Configuration Out of Reset ..................................................... 2-31
Signal State During Reset ......................................................................................... 2-31
Power-On Reset and Hard Reset .............................................................................. 2-32
Pull-Up/Pull-Down ................................................................................................... 2-32
Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only Signals .. 2-32
Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals .................... 2-32
Special Pull Resistor Disable Control Functionality (SPRDS) ............................ 2-32
Pull Device Select (PULL_SEL) .......................................................................... 2-33
Signal Reset States .................................................................................................... 2-33
Chapter 3
Central Processing Unit
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.6
RCPU Block Diagram .................................................................................................... 3-1
RCPU Key Features ........................................................................................................ 3-3
Instruction Sequencer ..................................................................................................... 3-3
Independent Execution Units .......................................................................................... 3-4
Branch Processing Unit (BPU) ................................................................................... 3-5
Integer Unit (IU) ......................................................................................................... 3-5
Load/Store Unit (LSU) ............................................................................................... 3-6
Floating-Point Unit (FPU) .......................................................................................... 3-6
Levels of the PowerPC ISA Architecture ....................................................................... 3-6
RCPU Programming Model ............................................................................................ 3-7
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.4.1
3.7.4.2
3.7.4.3
3.7.5
3.7.6
3.7.7
3.8
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10
3.9.10.1
3.9.10.2
3.9.10.3
3.10
3.10.1
3.10.2
3.10.3
3.11
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.12
3.13
3.13.1
3.13.2
Title
Page
Number
User Instruction Set Architecture (UISA)
Register Set ............................................................................................................... 3-12
General-Purpose Registers (GPRs) ........................................................................... 3-12
Floating-Point Registers (FPRs) ............................................................................... 3-12
Floating-Point Status and Control Register (FPSCR) .............................................. 3-13
Condition Register (CR) ........................................................................................... 3-16
Condition Register CR0 Field Definition ............................................................. 3-17
Condition Register CR1 Field Definition ............................................................. 3-17
Condition Register CRn Field — Compare Instruction ....................................... 3-17
Integer Exception Register (XER) ............................................................................ 3-18
Link Register (LR) .................................................................................................... 3-19
Count Register (CTR) ............................................................................................... 3-19
VEA Register Set — Time Base (TB) .......................................................................... 3-20
OEA Register Set .......................................................................................................... 3-20
Machine State Register (MSR) ................................................................................. 3-20
DAE/Source Instruction Service Register (DSISR) ................................................. 3-22
Data Address Register (DAR) .................................................................................. 3-23
Time Base Facility (TB) — OEA ............................................................................. 3-23
Decrementer Register (DEC) .................................................................................... 3-23
Machine Status Save/Restore Register 0 (SRR0) ..................................................... 3-23
Machine Status Save/Restore Register 1 (SRR1) ..................................................... 3-23
General SPRs (SPRG0–SPRG3) .............................................................................. 3-24
Processor Version Register (PVR) ........................................................................... 3-25
Implementation-Specific SPRs ................................................................................. 3-25
EIE, EID, and NRI Special-Purpose Registers ..................................................... 3-25
Floating-Point Exception Cause Register (FPECR) ............................................. 3-26
Additional Implementation-Specific Registers ..................................................... 3-27
Instruction Set ............................................................................................................... 3-27
Instruction Set Summary .......................................................................................... 3-28
Recommended Simplified Mnemonics ..................................................................... 3-33
Calculating Effective Addresses ............................................................................... 3-34
Exception Model ........................................................................................................... 3-34
Exception Classes ..................................................................................................... 3-35
Ordered Exceptions ................................................................................................... 3-35
Unordered Exceptions ............................................................................................... 3-35
Precise Exceptions .................................................................................................... 3-36
Exception Vector Table ............................................................................................ 3-36
Instruction Timing ........................................................................................................ 3-37
User Instruction Set Architecture (UISA) .................................................................... 3-39
Computation Modes .................................................................................................. 3-39
Reserved Fields ......................................................................................................... 3-39
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
3.13.3
3.13.4
3.13.5
3.13.6
3.13.7
3.13.7.1
3.13.7.2
3.13.8
3.13.8.1
3.13.9
3.13.9.1
3.13.9.2
3.13.10
3.13.10.1
3.13.10.2
3.13.10.3
3.13.10.4
3.13.10.5
3.13.10.6
3.13.10.7
3.13.10.8
3.14
3.14.1
3.14.2
3.14.3
3.14.4
3.14.5
3.14.6
3.15
3.15.1
3.15.1.1
3.15.1.2
3.15.2
3.15.2.1
3.15.3
3.15.4
3.15.4.1
3.15.4.2
3.15.4.3
3.15.4.4
3.15.4.5
Title
Page
Number
Classes of Instructions .............................................................................................. 3-40
Exceptions ................................................................................................................. 3-40
Branch Processor ...................................................................................................... 3-40
Instruction Fetching .................................................................................................. 3-40
Branch Instructions ................................................................................................... 3-40
Invalid Branch Instruction Forms ......................................................................... 3-40
Branch Prediction ................................................................................................. 3-40
Fixed-Point Processor ............................................................................................... 3-41
Fixed-Point Instructions ........................................................................................ 3-41
Floating-Point Processor ........................................................................................... 3-41
General .................................................................................................................. 3-41
Optional Instructions ............................................................................................ 3-41
Load/Store Processor ................................................................................................ 3-42
Fixed-Point Load with Update and Store with Update Instructions ..................... 3-42
Fixed-Point Load and Store Multiple Instructions ............................................... 3-42
Fixed-Point Load String Instructions .................................................................... 3-42
Storage Synchronization Instructions ................................................................... 3-42
Floating-Point Load and Store With Update Instructions .................................... 3-42
Floating-Point Load Single Instructions ............................................................... 3-42
Floating-Point Store Single Instructions ............................................................... 3-42
Optional Instructions ............................................................................................ 3-43
Virtual Environment Architecture (VEA) .................................................................... 3-43
Atomic Update Primitives ........................................................................................ 3-43
Effect of Operand Placement on Performance ......................................................... 3-43
Storage Control Instructions ..................................................................................... 3-43
Instruction Synchronize (isync) Instruction .............................................................. 3-43
Enforce In-Order Execution of I/O (eieio) Instruction ............................................. 3-44
Time Base ................................................................................................................. 3-44
Operating Environment Architecture (OEA) ................................................................ 3-44
Branch Processor Registers ...................................................................................... 3-44
Machine State Register (MSR) ............................................................................. 3-44
Branch Processors Instructions ............................................................................. 3-44
Fixed-Point Processor ............................................................................................... 3-44
Special Purpose Registers ..................................................................................... 3-44
Storage Control Instructions ..................................................................................... 3-45
Exceptions ................................................................................................................. 3-45
System Reset Exception and NMI (0x0100) ........................................................ 3-45
Machine Check Exception (0x0200) .................................................................... 3-46
Data Storage Exception (0x0300) ......................................................................... 3-48
Instruction Storage Exception (0x0400) ............................................................... 3-48
External Interrupt (0x0500) .................................................................................. 3-48
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
vi
Contents
Paragraph
Number
3.15.4.6
3.15.4.7
3.15.4.8
3.15.4.9
3.15.4.10
3.15.4.11
3.15.4.12
3.15.4.13
3.15.4.14
3.15.4.15
3.15.4.16
3.15.5
3.15.6
3.15.7
Title
Page
Number
Alignment Exception (0x00600) .......................................................................... 3-49
Program Exception (0x0700) ................................................................................ 3-51
Floating-Point Unavailable Exception (0x0800) .................................................. 3-52
Decrementer Exception (0x0900) ......................................................................... 3-53
System Call Exception (0x0C00) ......................................................................... 3-54
Trace Exception (0x0D00) ................................................................................... 3-54
Floating-Point Assist Exception (0x0E00) ........................................................... 3-55
Implementation-Dependent Software Emulation Exception (0x1000) ................ 3-56
Implementation-Dependent Instruction Protection Exception (0x1300) .............. 3-57
Implementation-Specific Data Protection Error Exception (0x1400) .................. 3-58
Implementation-Dependent Debug Exceptions .................................................... 3-59
Partially Executed Instructions ................................................................................. 3-60
Timer Facilities ......................................................................................................... 3-61
Optional Facilities and Instructions .......................................................................... 3-61
Chapter 4
Burst Buffer Controller 2 Module
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.1.1
4.4.1.2
4.5
Key Features ................................................................................................................... 4-2
BIU Key Features ....................................................................................................... 4-2
IMPU Key Features .................................................................................................... 4-3
ICDU Key Features .................................................................................................... 4-3
DECRAM Key Features ............................................................................................. 4-4
Branch Target Buffer Key Features ............................................................................ 4-4
Operation Modes ............................................................................................................. 4-4
Instruction Fetch ......................................................................................................... 4-4
Decompression Off Mode ....................................................................................... 4-4
Decompression On Mode ....................................................................................... 4-5
Burst Operation of the BBC ........................................................................................ 4-5
Access Violation Detection ........................................................................................ 4-5
Slave Operation ........................................................................................................... 4-6
Reset Behavior ............................................................................................................ 4-6
Debug Operation Mode .............................................................................................. 4-7
Exception Table Relocation (ETR) ................................................................................. 4-7
ETR Operation ............................................................................................................ 4-8
Enhanced External Interrupt Relocation (EEIR) ...................................................... 4-10
Decompressor RAM (DECRAM) Functionality .......................................................... 4-12
General-Purpose Memory Operation ........................................................................ 4-13
Memory Protection Violations ............................................................................. 4-14
DECRAM Standby Operation Mode .................................................................... 4-14
Branch Target Buffer .................................................................................................... 4-14
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.6
4.6.1
4.6.1.1
4.6.1.2
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.2.5
4.6.3
Title
Page
Number
BTB Operation .......................................................................................................... 4-14
BTB Invalidation .................................................................................................. 4-16
BTB Enabling/Disabling ...................................................................................... 4-16
BTB Inhibit Regions ............................................................................................. 4-16
BBC Programming Model ............................................................................................ 4-17
Address Map ............................................................................................................. 4-17
BBC Special Purpose Registers (SPRs) ............................................................... 4-17
DECRAM and DCCR Block ................................................................................ 4-18
BBC Register Descriptions ....................................................................................... 4-19
BBC Module Configuration Register (BBCMCR) ............................................... 4-19
Region Base Address Registers (MI_RBA[0:3]) ................................................. 4-21
Region Attribute Registers (MI_RA[0:3]) ............................................................ 4-22
Global Region Attribute Register (MI_GRA) ...................................................... 4-23
External Interrupt Relocation Table Base Address Register (EIBADR) .............. 4-25
Decompressor Class Configuration Registers .......................................................... 4-25
Chapter 5
Unified System Interface Unit (USIU) Overview
5.1
5.1.1
Memory Map and Registers ............................................................................................ 5-2
USIU Special-Purpose Registers ................................................................................ 5-6
Chapter 6
System Configuration and Protection
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.4
6.1.4.1
6.1.4.2
6.1.4.3
6.1.4.4
6.1.4.4.1
6.1.4.4.2
System Configuration and Protection Features .............................................................. 6-3
System Configuration ................................................................................................. 6-3
USIU Pin Multiplexing ........................................................................................... 6-4
Arbitration Support ................................................................................................. 6-4
External Master Modes ............................................................................................... 6-4
Operation in External Master Modes ...................................................................... 6-5
Address Decoding for External Accesses ............................................................... 6-6
USIU General-Purpose I/O ......................................................................................... 6-6
Enhanced Interrupt Controller .................................................................................... 6-8
Key Features ........................................................................................................... 6-8
Interrupt Configuration ........................................................................................... 6-8
Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode) 6-10
Enhanced Interrupt Controller Operation ............................................................. 6-11
Lower Priority Request Masking ...................................................................... 6-14
Backward Compatibility with MPC555/MPC556 ............................................ 6-14
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
6.1.4.5
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.2
6.2.1
6.2.2
6.2.2.1
6.2.2.1.1
6.2.2.1.2
6.2.2.1.3
6.2.2.2
6.2.2.2.1
6.2.2.2.2
6.2.2.2.3
6.2.2.2.4
6.2.2.2.5
6.2.2.2.6
6.2.2.2.7
6.2.2.2.8
6.2.2.2.9
6.2.2.3
6.2.2.3.1
6.2.2.3.2
6.2.2.3.3
6.2.2.4
6.2.2.4.1
6.2.2.4.2
6.2.2.4.3
6.2.2.4.4
6.2.2.4.5
6.2.2.4.6
6.2.2.4.7
6.2.2.4.8
6.2.2.4.9
6.2.2.4.10
Title
Page
Number
Interrupt Overhead Estimation for Enhanced Interrupt Controller Mode ............ 6-16
Hardware Bus Monitor ............................................................................................. 6-17
Decrementer (DEC) .................................................................................................. 6-18
Time Base (TB) ........................................................................................................ 6-19
Real-Time Clock (RTC) ........................................................................................... 6-19
Periodic Interrupt Timer (PIT) .................................................................................. 6-20
Software Watchdog Timer (SWT) ............................................................................ 6-21
Freeze Operation ....................................................................................................... 6-23
Low Power Stop Operation ....................................................................................... 6-23
Memory Map and Register Definitions ........................................................................ 6-23
Memory Map ............................................................................................................ 6-23
System Configuration and Protection Registers ....................................................... 6-24
System Configuration Registers ........................................................................... 6-24
SIU Module Configuration Register (SIUMCR) .............................................. 6-25
Internal Memory Map Register (IMMR) .......................................................... 6-28
External Master Control Register (EMCR) ...................................................... 6-29
SIU Interrupt Controller Registers ........................................................................ 6-31
SIU Interrupt Pending Register (SIPEND) ....................................................... 6-32
SIU Interrupt Pending Register 2 (SIPEND2) .................................................. 6-32
SIU Interrupt Pending Register 3 (SIPEND3) .................................................. 6-33
SIU Interrupt Mask Register (SIMASK) .......................................................... 6-33
SIU Interrupt Mask Register 2 (SIMASK2) .................................................... 6-34
SIU Interrupt Mask Register 3 (SIMASK3) ..................................................... 6-35
SIU Interrupt Edge Level Register (SIEL) ....................................................... 6-35
SIU Interrupt Vector Register (SIVEC) ........................................................... 6-35
Interrupt In-Service Registers (SISR2 and SISR3) .......................................... 6-37
System Protection Registers ................................................................................. 6-37
System Protection Control Register (SYPCR) ................................................. 6-37
Software Service Register (SWSR) .................................................................. 6-38
Transfer Error Status Register (TESR) ............................................................. 6-39
System Timer Registers ........................................................................................ 6-40
Decrementer Register (DEC) ............................................................................ 6-40
Time Base SPRs (TB) ....................................................................................... 6-40
Time Base Reference Registers (TBREF0 and TBREF1) ................................ 6-41
Time Base Control and Status Register (TBSCR) ............................................ 6-42
Real-Time Clock Status and Control Register (RTCSC) ................................. 6-42
Real-Time Clock Register (RTC) ..................................................................... 6-43
Real-Time Clock Alarm Register (RTCAL) .................................................... 6-44
Periodic Interrupt Status and Control Register (PISCR) .................................. 6-44
Periodic Interrupt Timer Count Register (PITC) .............................................. 6-45
Periodic Interrupt Timer Register (PITR) ........................................................ 6-45
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
6.2.2.5
6.2.2.5.1
6.2.2.5.2
6.2.2.5.3
Title
Page
Number
General-Purpose I/O Registers ............................................................................. 6-46
SGPIO Data Register 1 (SGPIODT1) ............................................................. 6-46
SGPIO Data Register 2 (SGPIODT2) ............................................................. 6-47
SGPIO Control Register (SGPIOCR) .............................................................. 6-48
Chapter 7
Reset
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
Reset Operation ............................................................................................................... 7-1
Power-On Reset .......................................................................................................... 7-1
Hard Reset ................................................................................................................... 7-2
Soft Reset .................................................................................................................... 7-2
Loss of PLL Lock ....................................................................................................... 7-2
On-Chip Clock Switch ................................................................................................ 7-3
Software Watchdog Reset ........................................................................................... 7-3
Checkstop Reset .......................................................................................................... 7-3
Debug Port Hard Reset ............................................................................................... 7-3
Debug Port Soft Reset ................................................................................................. 7-3
JTAG Reset ................................................................................................................. 7-3
ILBC Illegal Bit Change ............................................................................................. 7-3
Reset Actions Summary .................................................................................................. 7-3
Data Coherency During Reset ........................................................................................ 7-4
Reset Status Register (RSR) ........................................................................................... 7-5
Reset Configuration ........................................................................................................ 7-7
Hard Reset Configuration ........................................................................................... 7-7
Hard Reset Configuration Word (RCW) .................................................................. 7-11
Soft Reset Configuration .......................................................................................... 7-13
Chapter 8
Clocks and Power Control
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.4
System Clock Sources .................................................................................................... 8-3
System PLL ..................................................................................................................... 8-3
Frequency Multiplication ............................................................................................ 8-4
Skew Elimination ........................................................................................................ 8-4
Pre-Divider .................................................................................................................. 8-4
PLL Block Diagram .................................................................................................... 8-4
PLL Pins ..................................................................................................................... 8-5
System Clock During PLL Loss of Lock ........................................................................ 8-6
Low-Power Divider ........................................................................................................ 8-6
MPC561/MPC563 Reference Manual, Rev. 1.2
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Paragraph
Number
8.5
8.5.1
8.5.2
8.5.3
8.6
8.7
8.7.1
8.7.2
8.7.3
8.7.3.1
8.7.3.2
8.7.3.3
8.7.3.4
8.7.3.5
8.8
8.8.1
8.8.2
8.8.2.1
8.8.2.2
8.8.2.3
8.8.2.4
8.8.2.5
8.8.2.6
8.8.2.7
8.8.2.8
8.8.2.9
8.8.2.10
8.8.2.11
8.8.3
8.8.3.1
8.8.3.2
8.9
8.10
8.11
8.11.1
8.11.2
8.11.3
8.11.4
Title
Page
Number
Internal Clock Signals ..................................................................................................... 8-7
General System Clocks ............................................................................................. 8-10
Clock Out (CLKOUT) .............................................................................................. 8-13
Engineering Clock (ENGCLK) ................................................................................ 8-14
Clock Source Switching ................................................................................................ 8-14
Low-Power Modes ........................................................................................................ 8-16
Entering a Low-Power Mode .................................................................................... 8-16
Power Mode Descriptions ......................................................................................... 8-17
Exiting from Low-Power Modes .............................................................................. 8-17
Exiting from Normal-Low Mode .......................................................................... 8-18
Exiting from Doze Mode ...................................................................................... 8-19
Exiting from Deep-Sleep Mode ............................................................................ 8-19
Exiting from Power-Down Mode ......................................................................... 8-19
Low-Power Modes Flow ...................................................................................... 8-19
Basic Power Structure ................................................................................................... 8-21
General Power Supply Definitions ........................................................................... 8-21
Chip Power Structure ................................................................................................ 8-22
NVDDL ................................................................................................................ 8-22
QVDDL ................................................................................................................ 8-22
VDD ...................................................................................................................... 8-22
VDDSYN, VSSSYN ............................................................................................ 8-22
KAPWR ................................................................................................................ 8-22
VDDA, VSSA ....................................................................................................... 8-22
VFLASH ............................................................................................................... 8-22
VDDF, VSSF ........................................................................................................ 8-22
VDDH ................................................................................................................... 8-23
IRAMSTBY .......................................................................................................... 8-23
VSS ....................................................................................................................... 8-23
Keep-Alive Power ..................................................................................................... 8-24
Keep-Alive Power Configuration ......................................................................... 8-24
Keep-Alive Power Registers Lock Mechanism .................................................... 8-25
IRAMSTBY Supply Failure Detection ......................................................................... 8-27
Power-Up/Down Sequencing ....................................................................................... 8-27
Clocks Unit Programming Model ................................................................................. 8-29
System Clock Control Register (SCCR) ................................................................... 8-29
PLL, Low-Power, and Reset-Control Register (PLPRCR) ...................................... 8-33
Change of Lock Interrupt Register (COLIR) ............................................................ 8-36
IRAMSTBY Control Register (VSRMCR) .............................................................. 8-37
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
Title
Page
Number
Chapter 9
External Bus Interface
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
9.5.3
9.5.3.1
9.5.3.2
9.5.4
9.5.5
9.5.6
9.5.7
9.5.7.1
9.5.7.2
9.5.7.3
9.5.7.4
9.5.8
9.5.8.1
9.5.8.2
9.5.8.3
9.5.8.4
9.5.8.5
9.5.8.6
9.5.8.7
9.5.9
9.5.9.1
9.5.9.2
9.5.9.3
9.5.9.4
9.5.10
9.5.11
9.5.11.1
9.5.11.2
Features ........................................................................................................................... 9-1
Bus Transfer Signals ....................................................................................................... 9-1
Bus Control Signals ........................................................................................................ 9-2
Bus Interface Signal Descriptions ................................................................................... 9-3
Bus Operations ................................................................................................................ 9-8
Basic Transfer Protocol .............................................................................................. 9-8
Single Beat Transfer ................................................................................................... 9-9
Single Beat Read Flow ........................................................................................... 9-9
Single Beat Write Flow ........................................................................................ 9-11
Single Beat Flow with Small Port Size ................................................................. 9-14
Data Bus Pre-Discharge Mode ................................................................................. 9-15
Operating Conditions ............................................................................................ 9-16
Initialization Sequence .......................................................................................... 9-16
Burst Transfer ........................................................................................................... 9-17
Burst Mechanism ...................................................................................................... 9-18
Alignment and Packaging of Transfers .................................................................... 9-29
Arbitration Phase ...................................................................................................... 9-32
Bus Request .......................................................................................................... 9-33
Bus Grant .............................................................................................................. 9-33
Bus Busy ............................................................................................................... 9-34
Internal Bus Arbiter .............................................................................................. 9-35
Address Transfer Phase Signals ................................................................................ 9-37
Transfer Start ........................................................................................................ 9-37
Address Bus .......................................................................................................... 9-37
Read/Write ............................................................................................................ 9-37
Burst Indicator ...................................................................................................... 9-37
Transfer Size ......................................................................................................... 9-38
Address Types ...................................................................................................... 9-38
Burst Data in Progress .......................................................................................... 9-40
Termination Signals .................................................................................................. 9-40
Transfer Acknowledge .......................................................................................... 9-40
Burst Inhibit .......................................................................................................... 9-40
Transfer Error Acknowledge ................................................................................ 9-40
Termination Signals Protocol ............................................................................... 9-40
Storage Reservation .................................................................................................. 9-42
Bus Exception Control Cycles .................................................................................. 9-45
Retrying a Bus Cycle ............................................................................................ 9-45
Termination Signals Protocol Summary ............................................................... 9-49
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
9.5.12
9.5.13
9.5.14
Title
Page
Number
Bus Operation in External Master Modes ................................................................. 9-49
Contention Resolution on External Bus .................................................................... 9-53
Show Cycle Transactions .......................................................................................... 9-55
Chapter 10
Memory Controller
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.6.1
10.2.6.2
10.2.6.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.4
10.5
10.6
10.7
10.8
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
Overview ....................................................................................................................... 10-1
Memory Controller Architecture .................................................................................. 10-3
Associated Registers ................................................................................................. 10-4
Port Size Configuration ............................................................................................ 10-4
Write-Protect Configuration ..................................................................................... 10-5
Address and Address Space Checking ...................................................................... 10-5
Burst Support ............................................................................................................ 10-5
Reduced Data Setup Time ........................................................................................ 10-6
Case 1: Normal Setup Time .................................................................................. 10-6
Case 2: Short Setup Time ..................................................................................... 10-7
Summary of Short Setup Time ............................................................................. 10-8
Chip-Select Timing ..................................................................................................... 10-10
Memory Devices Interface Example ...................................................................... 10-12
Peripheral Devices Interface Example .................................................................... 10-13
Relaxed Timing Examples ...................................................................................... 10-14
Extended Hold Time on Read Accesses ................................................................. 10-18
Summary of GPCM Timing Options ...................................................................... 10-22
Write and Byte Enable Signals ................................................................................... 10-24
Dual Mapping of the Internal Flash EEPROM Array ................................................ 10-24
Dual Mapping of an External Flash Region ............................................................... 10-26
Global (Boot) Chip-Select Operation ......................................................................... 10-27
Memory Controller External Master Support ............................................................. 10-28
Programming Model ................................................................................................... 10-31
General Memory Controller Programming Notes .................................................. 10-31
Memory Controller Status Registers (MSTAT) ..................................................... 10-32
Memory Controller Base Registers (BR0–BR3) .................................................... 10-32
Memory Controller Option Registers (OR0–OR3) ................................................ 10-34
Dual-Mapping Base Register (DMBR) .................................................................. 10-36
Dual-Mapping Option Register (DMOR) ............................................................... 10-37
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
Title
Page
Number
Chapter 11
L-Bus to U-Bus Interface (L2U)
11.1
11.2
11.3
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.6
11.6.1
11.6.2
11.6.3
11.7
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.7.6
11.8
11.8.1
11.8.2
11.8.3
11.8.4
11.8.5
11.8.6
General Features ........................................................................................................... 11-1
Data Memory Protection Unit Features ........................................................................ 11-1
L2U Block Diagram ...................................................................................................... 11-2
Modes Of Operation ..................................................................................................... 11-3
Normal Mode ............................................................................................................ 11-3
Reset Operation ......................................................................................................... 11-4
Peripheral Mode ........................................................................................................ 11-4
Factory Test Mode .................................................................................................... 11-4
Data Memory Protection ............................................................................................... 11-4
Functional Description .............................................................................................. 11-5
Associated Registers ................................................................................................. 11-6
L-Bus Memory Access Violations ............................................................................ 11-7
Reservation Support ...................................................................................................... 11-7
Reservation Protocol ................................................................................................. 11-8
L2U Reservation Support ......................................................................................... 11-8
Reserved Location (Bus) and Possible Actions ........................................................ 11-9
L-Bus Show Cycle Support .......................................................................................... 11-9
Programming Show Cycles .................................................................................... 11-10
Performance Impact ................................................................................................ 11-10
Show Cycle Protocol .............................................................................................. 11-10
L-Bus Write Show Cycle Flow ............................................................................... 11-10
L-Bus Read Show Cycle Flow ................................................................................ 11-11
Show Cycle Support Guidelines ............................................................................. 11-11
L2U Programming Model ........................................................................................... 11-12
U-Bus Access .......................................................................................................... 11-13
Transaction Size ...................................................................................................... 11-13
L2U Module Configuration Register (L2U_MCR) ................................................ 11-13
Region Base Address Registers (L2U_RBAx) ....................................................... 11-14
Region Attribute Registers (L2U_RAx) ................................................................. 11-15
Global Region Attribute Register (L2U_GRA) ...................................................... 11-16
Chapter 12
U-Bus to IMB3 Bus Interface (UIMB)
12.1
12.2
12.3
12.4
Features ......................................................................................................................... 12-1
UIMB Block Diagram .................................................................................................. 12-2
Clock Module ............................................................................................................... 12-2
Interrupt Operation ....................................................................................................... 12-3
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
12.4.1
12.4.2
12.4.3
12.4.4
12.5
12.5.1
12.5.2
12.5.3
Title
Page
Number
Interrupt Sources and Levels on IMB3 ..................................................................... 12-3
IMB3 Interrupt Multiplexing .................................................................................... 12-4
ILBS Sequencing ...................................................................................................... 12-4
Interrupt Synchronizer .............................................................................................. 12-5
Programming Model ..................................................................................................... 12-6
UIMB Module Configuration Register (UMCR) ..................................................... 12-7
Test Control Register (UTSTCREG) ........................................................................ 12-8
Pending Interrupt Request Register (UIPEND) ........................................................ 12-8
Chapter 13
QADC64E Legacy Mode Operation
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
13.3.1.4
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.4
13.4.1
13.4.1.1
13.4.1.2
13.4.2
13.4.3
13.4.4
QADC64E Block Diagram ........................................................................................... 13-1
Key Features and Quick Reference Diagrams .............................................................. 13-2
Features of the QADC64E Legacy Mode Operation ................................................ 13-2
Memory Map ............................................................................................................ 13-3
Legacy and Enhanced Modes of Operation .............................................................. 13-4
Using the Queue and Result Word Table ................................................................. 13-5
External Multiplexing ............................................................................................... 13-5
Programming the QADC64E Registers ........................................................................ 13-7
QADC64E Module Configuration Register (QADMCR) ........................................ 13-8
Low Power Stop Mode ......................................................................................... 13-9
Freeze Mode ......................................................................................................... 13-9
Switching Between Legacy and Enhanced Modes of Operation ........................ 13-10
Supervisor/Unrestricted Address Space ............................................................. 13-10
QADC64E Interrupt Register (QADCINT) ............................................................ 13-12
Port Data Register (PORTQA and PORTQB) ........................................................ 13-13
Port Data Direction Register (DDRQA) ................................................................. 13-14
Control Register 0 (QACR0) .................................................................................. 13-14
Control Register 1 (QACR1) .................................................................................. 13-15
Control Register 2 (QACR2) .................................................................................. 13-17
Status Registers (QASR0 and QASR1) .................................................................. 13-20
Conversion Command Word Table ........................................................................ 13-27
Result Word Table .................................................................................................. 13-32
Analog Subsystem ...................................................................................................... 13-34
Analog-to-Digital Converter Operation .................................................................. 13-34
Conversion Cycle Times ..................................................................................... 13-35
Amplifier Bypass Mode Conversion Timing ..................................................... 13-35
Channel Decode and Multiplexer ........................................................................... 13-36
Sample Buffer Amplifier ........................................................................................ 13-36
Digital-to-Analog Converter (DAC) Array ............................................................ 13-36
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
13.4.5
13.4.6
13.4.7
13.4.8
13.5
13.5.1
13.5.2
13.5.3
13.5.4
13.5.4.1
13.5.4.2
13.5.4.3
13.5.4.3.1
13.5.4.3.2
13.5.4.3.3
13.5.4.3.4
13.5.4.4
13.5.4.4.1
13.5.4.4.2
13.5.4.4.3
13.5.4.4.4
13.5.5
13.5.6
13.5.7
13.5.7.1
13.5.7.2
13.6
13.6.1
13.6.2
13.7
13.7.1
13.7.2
13.7.3
13.7.3.1
13.7.4
13.7.5
13.7.5.1
13.7.5.2
13.7.5.3
13.7.5.4
Title
Page
Number
Comparator ............................................................................................................. 13-37
Bias ......................................................................................................................... 13-37
Successive Approximation Register ...................................................................... 13-37
State Machine ......................................................................................................... 13-37
Digital Subsystem ....................................................................................................... 13-37
Queue Priority ......................................................................................................... 13-38
Paused Sub-Queues ................................................................................................. 13-38
Boundary Conditions .............................................................................................. 13-40
Scan Modes ............................................................................................................. 13-41
Disabled Mode .................................................................................................... 13-41
Reserved Mode ................................................................................................... 13-41
Single-Scan Modes ............................................................................................. 13-42
Software Initiated Single-Scan Mode ............................................................. 13-42
External Trigger Single-Scan Mode ............................................................... 13-43
External Gated Single-Scan Mode ................................................................. 13-43
Periodic/Interval Timer Single-Scan Mode .................................................... 13-44
Continuous-Scan Modes ..................................................................................... 13-44
Software Initiated Continuous-Scan Mode ..................................................... 13-45
External Trigger Continuous-Scan Mode ....................................................... 13-46
External Gated Continuous-Scan Mode ......................................................... 13-46
Periodic/Interval Timer Continuous-Scan Mode ............................................ 13-47
QADC64E Clock (QCLK) Generation ................................................................... 13-47
Periodic / Interval Timer ......................................................................................... 13-51
Configuration and Control Using the IMB3 Interface ............................................ 13-51
QADC64E Bus Interface Unit ............................................................................ 13-51
QADC64E Bus Accessing .................................................................................. 13-52
Trigger and Queue Interaction Examples ................................................................... 13-54
Queue Priority Schemes .......................................................................................... 13-54
Conversion Timing Schemes .................................................................................. 13-63
QADC64E Integration Requirements ......................................................................... 13-66
Port Digital Input/Output Signals ........................................................................... 13-66
External Trigger Input Signals ................................................................................ 13-67
Analog Power Signals ............................................................................................. 13-67
Analog Supply Filtering and Grounding ............................................................ 13-69
Analog Reference Signals ....................................................................................... 13-71
Analog Input Signals .............................................................................................. 13-71
Analog Input Considerations .............................................................................. 13-73
Settling Time for the External Circuit ................................................................ 13-75
Error Resulting from Leakage ............................................................................ 13-75
Accommodating Positive/Negative Stress Conditions ....................................... 13-76
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
Title
Page
Number
Chapter 14
QADC64E Enhanced Mode Operation
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.1.3
14.3.1.4
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
14.3.9
14.3.10
14.3.10.1
14.3.11
14.3.11.1
14.3.12
14.3.13
14.3.14
14.3.15
14.3.16
14.3.17
14.3.18
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.4.1
QADC64E Block Diagram ........................................................................................... 14-1
Key Features and Quick Reference Diagrams .............................................................. 14-2
Features of the QADC64E Enhanced Mode Operation ............................................ 14-2
Memory Map ............................................................................................................ 14-3
Legacy and Enhanced Modes of Operation .............................................................. 14-4
Using the Queue and Result Word Table ................................................................. 14-5
External Multiplexing ............................................................................................... 14-5
Programming the QADC64E Registers ........................................................................ 14-7
QADC64E Module Configuration Register ........................................................... 14-8
Low Power Stop Mode ......................................................................................... 14-8
Freeze Mode ......................................................................................................... 14-9
Switching Between Legacy and Enhanced Modes of Operation .......................... 14-9
Supervisor/Unrestricted Address Space ............................................................. 14-10
QADC64E Interrupt Register ................................................................................. 14-11
Port Data Register ................................................................................................... 14-12
Port Data Direction Register ................................................................................... 14-13
Control Register 0 ................................................................................................... 14-14
Control Register 1 ................................................................................................... 14-16
Control Register 2 ................................................................................................... 14-18
Status Registers (QASR0 and QASR1) .................................................................. 14-22
Conversion Command Word Table ........................................................................ 14-28
Result Word Table .................................................................................................. 14-34
Analog Subsystem .............................................................................................. 14-36
Analog-to-Digital Converter Operation .................................................................. 14-36
Conversion Cycle Times ..................................................................................... 14-36
Channel Decode and Multiplexer ........................................................................... 14-37
Sample Buffer Amplifier ........................................................................................ 14-37
Digital to Analog Converter (DAC) Array ............................................................. 14-37
Comparator ............................................................................................................. 14-38
Bias ......................................................................................................................... 14-38
Successive Approximation Register ...................................................................... 14-38
State Machine ......................................................................................................... 14-38
Digital Subsystem ....................................................................................................... 14-38
Queue Priority ......................................................................................................... 14-39
Sub-Queues That are Paused .................................................................................. 14-39
Boundary Conditions .............................................................................................. 14-41
Scan Modes ............................................................................................................. 14-42
Disabled Mode .................................................................................................... 14-42
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
14.4.4.2
14.4.4.3
14.4.4.3.1
14.4.4.3.2
14.4.4.3.3
14.4.4.3.4
14.4.4.4
14.4.4.4.1
14.4.4.4.2
14.4.4.4.3
14.4.4.4.4
14.4.5
14.4.6
14.4.7
14.4.7.1
14.4.7.2
14.5
14.5.1
14.5.2
14.6
14.6.1
14.6.2
14.6.3
14.6.3.1
14.6.4
14.6.5
14.6.5.1
14.6.5.2
14.6.5.3
14.6.5.4
Title
Page
Number
Reserved Mode ................................................................................................... 14-42
Single-Scan Modes ............................................................................................. 14-43
Software Initiated Single-Scan Mode ............................................................. 14-43
External Trigger Single-Scan Mode ............................................................... 14-44
External Gated Single-Scan Mode ................................................................. 14-44
Periodic/Interval Timer Single-Scan Mode .................................................... 14-45
Continuous-Scan Modes ..................................................................................... 14-45
Software Initiated Continuous-Scan Mode ..................................................... 14-46
External Trigger Continuous-Scan Mode ....................................................... 14-47
External Gated Continuous-Scan Mode ......................................................... 14-47
Periodic/Interval Timer Continuous-Scan Mode ............................................ 14-48
QADC64E Clock (QCLK) Generation ................................................................... 14-48
Periodic/Interval Timer ........................................................................................... 14-50
Configuration and Control Using the IMB3 Interface ............................................ 14-51
QADC64E Bus Interface Unit ............................................................................ 14-51
QADC64E Bus Accessing .................................................................................. 14-51
Trigger and Queue Interaction Examples ................................................................... 14-53
Queue Priority Schemes .......................................................................................... 14-53
Conversion Timing Schemes .................................................................................. 14-62
QADC64E Integration Requirements ......................................................................... 14-65
Port Digital Input/Output Signals ........................................................................... 14-65
External Trigger Input Signals ................................................................................ 14-66
Analog Power Signals ............................................................................................. 14-66
Analog Supply Filtering and Grounding ............................................................ 14-67
Analog Reference Signals ....................................................................................... 14-69
Analog Input Signals .............................................................................................. 14-70
Analog Input Considerations .............................................................................. 14-71
Settling Time for the External Circuit ................................................................ 14-73
Error Resulting from Leakage ............................................................................ 14-73
Accommodating Positive/Negative Stress Conditions ....................................... 14-74
Chapter 15
Queued Serial Multi-Channel Module
15.1
15.2
15.2.1
15.3
15.4
15.4.1
15.4.2
Block Diagram .............................................................................................................. 15-1
Key Features ................................................................................................................. 15-2
MPC561/MPC563 QSMCM Details ........................................................................ 15-3
Memory Maps ............................................................................................................... 15-4
QSMCM Global Registers ............................................................................................ 15-6
Low-Power Stop Operation ...................................................................................... 15-6
Freeze Operation ....................................................................................................... 15-6
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
15.4.3
15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
15.5
15.5.1
15.5.2
15.5.3
15.6
15.6.1
15.6.1.1
15.6.1.2
15.6.1.3
15.6.1.4
15.6.1.5
15.6.2
15.6.2.1
15.6.2.2
15.6.2.3
15.6.3
15.6.4
15.6.4.1
15.6.4.2
15.6.4.3
15.6.5
15.6.5.1
15.6.5.2
15.6.5.3
15.6.5.4
15.6.5.5
15.6.5.6
15.6.5.7
15.6.5.8
15.6.6
15.6.6.1
15.6.7
15.6.8
15.7
15.7.1
Title
Page
Number
Access Protection ...................................................................................................... 15-6
QSMCM Interrupts ................................................................................................... 15-7
QSPI Interrupt Generation ........................................................................................ 15-8
QSMCM Configuration Register (QSMCMMCR) .................................................. 15-8
QSMCM Test Register (QTEST) ............................................................................. 15-9
QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL) ..................................... 15-9
QSMCM Pin Control Registers .................................................................................. 15-10
Port QS Data Register (PORTQS) .......................................................................... 15-11
PORTQS Pin Assignment Register (PQSPAR) ..................................................... 15-12
PORTQS Data Direction Register (DDRQS) ......................................................... 15-13
Queued Serial Peripheral Interface ............................................................................. 15-14
QSPI Registers ....................................................................................................... 15-16
QSPI Control Register 0 (SPCR0) ...................................................................... 15-17
QSPI Control Register 1 (SPCR1) ...................................................................... 15-19
QSPI Control Register 2 (SPCR2) ...................................................................... 15-20
QSPI Control Register 3 (SPCR3) ...................................................................... 15-20
QSPI Status Register (SPSR) .............................................................................. 15-21
QSPI RAM .............................................................................................................. 15-22
Receive RAM ..................................................................................................... 15-23
Transmit RAM .................................................................................................... 15-23
Command RAM .................................................................................................. 15-23
QSPI Pins ................................................................................................................ 15-24
QSPI Operation ....................................................................................................... 15-25
Enabling, Disabling, and Halting the SPI ........................................................... 15-26
QSPI Interrupts ................................................................................................... 15-26
QSPI Flow .......................................................................................................... 15-27
Master Mode Operation .......................................................................................... 15-34
Clock Phase and Polarity .................................................................................... 15-35
Baud Rate Selection ............................................................................................ 15-35
Delay Before Transfer ........................................................................................ 15-36
Delay After Transfer ........................................................................................... 15-36
Transfer Length .................................................................................................. 15-37
Peripheral Chip Selects ....................................................................................... 15-37
Optional Enhanced Peripheral Chip Selects ....................................................... 15-37
Master Wraparound Mode .................................................................................. 15-38
Slave Mode ............................................................................................................. 15-39
Description of Slave Operation .......................................................................... 15-40
Slave Wraparound Mode ........................................................................................ 15-41
Mode Fault .............................................................................................................. 15-42
Serial Communication Interface ................................................................................. 15-42
SCI Registers .......................................................................................................... 15-45
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xix
Contents
Paragraph
Number
15.7.2
15.7.3
15.7.4
15.7.5
15.7.6
15.7.7
15.7.7.1
15.7.7.2
15.7.7.3
15.7.7.4
15.7.7.5
15.7.7.6
15.7.7.7
15.7.7.8
15.7.7.9
15.7.7.10
15.7.7.11
15.8
15.8.1
15.8.2
15.8.2.1
15.8.2.2
15.8.3
15.8.4
15.8.5
15.8.6
15.8.7
15.8.8
15.8.9
15.8.10
15.8.11
15.8.12
Title
Page
Number
SCI Control Register 0 (SCCxR0) .......................................................................... 15-46
SCI Control Register 1 (SCCxR1) .......................................................................... 15-47
SCI Status Register (SCxSR) .................................................................................. 15-48
SCI Data Register (SCxDR) ................................................................................... 15-50
SCI Pins .................................................................................................................. 15-51
SCI Operation ......................................................................................................... 15-51
Definition of Terms ............................................................................................ 15-51
Serial Formats ..................................................................................................... 15-52
Baud Clock ......................................................................................................... 15-52
Parity Checking .................................................................................................. 15-53
Transmitter Operation ......................................................................................... 15-54
Receiver Operation ............................................................................................. 15-55
Receiver Bit Processor ........................................................................................ 15-55
Receiver Functional Operation ........................................................................... 15-57
Idle-Line Detection ............................................................................................. 15-58
Receiver Wake-Up .............................................................................................. 15-58
Internal Loop Mode ............................................................................................ 15-59
SCI Queue Operation .................................................................................................. 15-59
Queue Operation of SCI1 for Transmit and Receive .............................................. 15-59
Queued SCI1 Status and Control Registers ............................................................ 15-59
QSCI1 Control Register (QSCI1CR) .................................................................. 15-60
QSCI1 Status Register (QSCI1SR) .................................................................... 15-61
QSCI1 Transmitter Block Diagram ........................................................................ 15-62
QSCI1 Additional Transmit Operation Features .................................................... 15-63
QSCI1 Transmit Flow Chart Implementing the Queue .......................................... 15-65
Example QSCI1 Transmit for 17 Data Bytes ......................................................... 15-67
Example SCI Transmit for 25 Data Bytes .............................................................. 15-68
QSCI1 Receiver Block Diagram ............................................................................. 15-70
QSCI1 Additional Receive Operation Features ...................................................... 15-70
QSCI1 Receive Flow Chart Implementing the Queue ............................................ 15-73
QSCI1 Receive Queue Software Flow Chart ......................................................... 15-74
Example QSCI1 Receive Operation of 17 Data Frames ......................................... 15-75
Chapter 16
CAN 2.0B Controller Module
16.1
16.2
16.2.1
16.3
16.3.1
Features ......................................................................................................................... 16-1
External Signals ............................................................................................................ 16-2
TouCAN Signal Sharing ........................................................................................... 16-3
TouCAN Architecture ................................................................................................... 16-3
Tx/Rx Message Buffer Structure .............................................................................. 16-4
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
16.3.1.1
16.3.1.2
16.3.1.3
16.3.1.4
16.3.1.5
16.3.1.6
16.3.2
16.3.3
16.3.3.1
16.3.4
16.3.5
16.4
16.4.1
16.4.2
16.4.3
16.4.3.1
16.4.3.2
16.4.4
16.4.4.1
16.4.4.2
16.4.5
16.4.6
16.5
16.5.1
16.5.2
16.5.3
16.6
16.7
16.7.1
16.7.2
16.7.3
16.7.4
16.7.5
16.7.6
16.7.7
16.7.8
16.7.9
16.7.10
16.7.11
16.7.12
16.7.13
Title
Page
Number
Common Fields for Extended and Standard Format Frames ................................ 16-4
Fields for Extended Format Frames ..................................................................... 16-6
Fields for Standard Format Frames ...................................................................... 16-6
Serial Message Buffers ......................................................................................... 16-6
Message Buffer Activation/Deactivation Mechanism .......................................... 16-7
Message Buffer Lock/Release/Busy Mechanism ................................................. 16-7
Receive Mask Registers ............................................................................................ 16-7
Bit Timing ................................................................................................................. 16-8
Configuring the TouCAN Bit Timing ................................................................ 16-10
Error Counters ......................................................................................................... 16-10
Time Stamp ............................................................................................................. 16-12
TouCAN Operation ..................................................................................................... 16-12
TouCAN Reset ........................................................................................................ 16-12
TouCAN Initialization ............................................................................................ 16-13
Transmit Process ..................................................................................................... 16-13
Transmit Message Buffer Deactivation .............................................................. 16-14
Reception of Transmitted Frames ....................................................................... 16-14
Receive Process ...................................................................................................... 16-14
Receive Message Buffer Deactivation ................................................................ 16-16
Locking and Releasing Message Buffers ........................................................... 16-16
Remote Frames ....................................................................................................... 16-17
Overload Frames ..................................................................................................... 16-17
Special Operating Modes ............................................................................................ 16-17
Debug Mode ........................................................................................................... 16-17
Low-Power Stop Mode ........................................................................................... 16-18
Auto Power Save Mode .......................................................................................... 16-19
Interrupts ..................................................................................................................... 16-20
Programming Model ................................................................................................... 16-21
TouCAN Module Configuration Register (CANMCR) ......................................... 16-25
TouCAN Test Configuration Register .................................................................... 16-27
TouCAN Interrupt Configuration Register (CANICR) .......................................... 16-27
Control Register 0 (CANCTRL0) ........................................................................... 16-27
Control Register 1 (CANCTRL1) ........................................................................... 16-28
Prescaler Divide Register (PRESDIV) ................................................................... 16-29
Control Register 2 (CANCTRL2) ........................................................................... 16-30
Free Running Timer (TIMER) ................................................................................ 16-31
Receive Global Mask Registers (RXGMSKHI, RXGMSKLO) ............................ 16-31
Receive Buffer 14 Mask Registers (RX14MSKHI, RX14MSKLO) ...................... 16-32
Receive Buffer 15 Mask Registers (RX15MSKHI, RX15MSKLO) ...................... 16-33
Error and Status Register (ESTAT) ........................................................................ 16-33
Interrupt Mask Register (IMASK) .......................................................................... 16-35
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
16.7.14
16.7.15
Title
Page
Number
Interrupt Flag Register (IFLAG) ............................................................................. 16-36
Error Counters (RXECTR, TXECTR) .................................................................... 16-36
Chapter 17
Modular Input/Output Subsystem (MIOS14)
17.1
17.2
17.2.1
17.2.2
17.3
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
17.4
17.4.1
17.4.2
17.5
17.6
17.6.1
17.6.1.1
17.6.1.2
17.6.1.3
17.6.1.4
17.7
17.7.1
17.7.1.1
17.7.1.2
17.7.2
17.7.3
17.7.3.1
17.7.3.2
17.8
17.8.1
17.8.1.1
17.8.2
17.8.3
17.8.4
17.8.5
Block Diagram .............................................................................................................. 17-1
MIOS14 Key Features .................................................................................................. 17-3
Submodule Numbering, Naming, and Addressing ................................................... 17-4
Signal Naming Convention ....................................................................................... 17-5
MIOS14 Configuration ................................................................................................. 17-6
MIOS14 Signals ........................................................................................................ 17-9
MIOS14 Bus System ................................................................................................ 17-9
Read/Write and Control Bus ................................................................................... 17-10
Request Bus ............................................................................................................ 17-10
Counter Bus Set ...................................................................................................... 17-10
MIOS14 Programming Model .................................................................................... 17-10
Bus Error Support ................................................................................................... 17-10
Wait States .............................................................................................................. 17-11
MIOS14 I/O Ports ....................................................................................................... 17-13
MIOS14 Bus Interface Submodule (MBISM) ............................................................ 17-13
MIOS14 Bus Interface (MBISM) Registers ........................................................... 17-13
MIOS14 Test and Signal Control Register (MIOS14TPCR) ............................. 17-13
MIOS14 Vector Register (MIOS14VECT) ........................................................ 17-14
MIOS14 Module and Version Number Register (MIOS14VNR) ...................... 17-14
MIOS14 Module Configuration Register (MIOS14MCR) ................................. 17-15
MIOS14 Counter Prescaler Submodule (MCPSM) .................................................... 17-16
MCPSM Features .................................................................................................... 17-16
MCPSM Signal Functions .................................................................................. 17-17
Modular I/O Bus (MIOB) Interface .................................................................... 17-17
Effect of RESET on MCPSM ................................................................................. 17-17
MCPSM Registers .................................................................................................. 17-17
MCPSM Registers Organization ........................................................................ 17-17
MCPSM Status/Control Register (MCPSMSCR) .............................................. 17-18
MIOS14 Modulus Counter Submodule (MMCSM) ................................................... 17-19
MMCSM Features .................................................................................................. 17-20
MMCSM Signal Functions ................................................................................. 17-21
MMCSM Prescaler ................................................................................................. 17-21
Modular I/O Bus (MIOB) Interface ........................................................................ 17-21
Effect of RESET on MMCSM ................................................................................ 17-22
MMCSM Registers ................................................................................................. 17-22
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
17.8.5.1
17.8.5.2
17.8.5.3
17.8.5.4
17.8.5.5
17.9
17.9.1
17.9.1.1
17.9.2
17.9.3
17.9.3.1
17.9.3.2
17.9.3.3
17.9.3.4
17.9.3.5
17.9.3.5.1
17.9.3.5.2
17.9.3.5.3
17.9.3.6
17.9.4
17.9.5
17.9.6
17.9.6.1
17.9.6.2
17.9.6.3
17.9.6.4
17.9.6.5
17.10
17.10.1
17.10.2
17.10.3
17.10.3.1
17.10.3.2
17.10.3.3
17.10.3.4
17.10.3.5
17.10.3.6
17.10.3.7
17.10.3.8
17.10.3.9
Title
Page
Number
MMCSM Register Organization ......................................................................... 17-22
MMCSM Up-Counter Register (MMCSMCNT) ............................................... 17-23
MMCSM Modulus Latch Register (MMCSMML) ............................................ 17-24
MMCSM Status/Control Register (MMCSMSCRD)
(Duplicated) .................................................................................................... 17-24
MMCSM Status/Control Register (MMCSMSCR) ............................................ 17-24
MIOS14 Double Action Submodule (MDASM) ........................................................ 17-26
MDASM Features ................................................................................................... 17-27
MDASM Signal Functions ................................................................................. 17-28
MDASM Description .............................................................................................. 17-28
MDASM Modes of Operation ................................................................................ 17-29
Disable (DIS) Mode ............................................................................................ 17-29
Input Pulse Width Measurement (IPWM) Mode ................................................ 17-30
Input Period Measurement (IPM) Mode ............................................................. 17-31
Input Capture (IC) Mode .................................................................................... 17-32
Output Compare (OCB and OCAB) Modes ....................................................... 17-33
Single Shot Output Pulse Operation ............................................................... 17-34
Single Output Compare Operation ................................................................. 17-35
Output Port Bit Operation ............................................................................... 17-36
Output Pulse Width Modulation (OPWM) Mode .............................................. 17-36
Modular I/O Bus (MIOB) Interface ........................................................................ 17-39
Effect of RESET on MDASM ................................................................................ 17-39
MDASM Registers ................................................................................................. 17-39
MDASM Registers Organization ....................................................................... 17-39
MDASM Data A (MDASMAR) Register .......................................................... 17-41
MDASM Data B (MDASMBR) Register ........................................................... 17-42
MDASM Status/Control Register (MDASMSCRD) (Duplicated) .................... 17-43
MDASM Status/Control Register (MDASMSCR) ............................................ 17-43
MIOS14 Pulse Width Modulation Submodule (MPWMSM) .................................... 17-46
MPWMSM Terminology ........................................................................................ 17-47
MPWMSM Features ............................................................................................... 17-47
MPWMSM Description .......................................................................................... 17-48
Clock Selection ................................................................................................... 17-49
Counter ............................................................................................................... 17-49
Period Register .................................................................................................... 17-49
Pulse Width Registers ......................................................................................... 17-50
Duty Cycles (0% and 100%) .............................................................................. 17-51
Pulse/Frequency Range Table ............................................................................ 17-52
MPWMSM Status and Control Register (SCR) ................................................. 17-53
MPWMSM Interrupt .......................................................................................... 17-53
MPWMSM Port Functions ................................................................................. 17-54
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
17.10.3.10
17.10.4
17.10.5
17.10.6
17.10.6.1
17.10.6.2
17.10.6.3
17.10.6.4
17.10.6.5
17.11
17.11.1
17.11.2
17.11.3
17.11.3.1
17.11.3.2
17.11.4
17.11.5
17.11.6
17.11.7
17.11.8
17.11.8.1
17.11.8.2
17.12
17.12.1
17.12.2
17.12.3
17.12.3.1
17.12.3.2
17.12.3.3
17.12.4
17.12.4.1
17.12.4.2
17.12.4.3
17.12.5
17.12.6
17.12.6.1
17.12.6.2
17.13
17.13.1
17.13.2
17.13.3
Title
Page
Number
MPWMSM Data Coherency ............................................................................... 17-54
Modular Input/Output Bus (MIOS14) Interface ..................................................... 17-54
Effect of RESET on MPWMSM ............................................................................ 17-54
MPWMSM Registers .............................................................................................. 17-55
MPWMSM Registers Organization .................................................................... 17-55
MPWMSM Period Register (MPWMPERR) ..................................................... 17-57
MPWMSM Pulse Width Register (MPWMPULR) ........................................... 17-57
MPWMSM Counter Register (MPWMCNTR) .................................................. 17-58
MPWMSM Status/Control Register (MPWMSCR) ........................................... 17-58
MIOS14 16-bit Parallel Port I/O Submodule (MPIOSM) .......................................... 17-60
MPIOSM Features .................................................................................................. 17-61
MPIOSM Signal Functions ..................................................................................... 17-61
MPIOSM Description ............................................................................................. 17-61
MPIOSM Port Function ...................................................................................... 17-61
Non-Bonded MPIOSM Pads .............................................................................. 17-61
Modular I/O Bus (MIOB) Interface ........................................................................ 17-62
Effect of RESET on MPIOSM ............................................................................... 17-62
MPIOSM Testing .................................................................................................... 17-62
MPIOSM Registers ................................................................................................. 17-62
MPIOSM Register Organization ............................................................................ 17-62
MPIOSM Data Register (MPIOSMDR) ............................................................. 17-62
MPIOSM Data Direction Register (MPIOSMDDR) .......................................... 17-63
MIOS14 Interrupts ...................................................................................................... 17-63
MIOS14 Interrupt Structure .................................................................................... 17-63
MIOS14 Interrupt Request Submodule (MIRSM) ................................................. 17-64
MIRSM0 Interrupt Registers .................................................................................. 17-65
Interrupt Status Register (MIOS14SR0) ............................................................. 17-65
Interrupt Enable Register (MIOS14ER0) ........................................................... 17-66
Interrupt Request Pending Register (MIOS14RPR0) ......................................... 17-66
MIRSM1 Interrupt Registers .................................................................................. 17-67
Interrupt Status Register (MIOS14SR1) ............................................................. 17-67
Interrupt Enable Register (MIOS14ER1) ........................................................... 17-68
Interrupt Request Pending Register (MIOS14RPR1) ......................................... 17-68
Interrupt Control Section (ICS) .............................................................................. 17-69
MBISM Interrupt Registers .................................................................................... 17-69
MIOS14 Interrupt Level Register 0 (MIOS14LVL0) ........................................ 17-69
MIOS14 Interrupt Level Register 1 (MIOS14LVL1) ........................................ 17-70
MIOS14 Function Examples ...................................................................................... 17-70
MIOS14 Input Double Edge Pulse Width Measurement ........................................ 17-70
MIOS14 Input Double Edge Period Measurement ................................................. 17-71
MIOS14 Double Edge Single Output Pulse Generation ......................................... 17-72
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxiv
Contents
Paragraph
Number
17.13.4
17.13.5
Title
Page
Number
MIOS14 Output Pulse Width Modulation with MDASM ...................................... 17-73
MIOS14 Input Pulse Accumulation ........................................................................ 17-74
Chapter 18
Peripheral Pin Multiplexing (PPM) Module
18.1
18.2
18.3
18.3.1
18.3.1.1
18.3.1.2
18.3.1.3
18.3.2
18.3.2.1
18.3.2.2
18.3.2.3
18.3.2.4
18.3.3
18.4
18.4.1
18.4.1.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
Key Features ................................................................................................................. 18-1
Programming Model ..................................................................................................... 18-2
Functional Description .................................................................................................. 18-3
PPM Parallel-to-Serial Communication Protocol ..................................................... 18-3
Internal Multiplexing ............................................................................................ 18-4
PPM Clocks .......................................................................................................... 18-5
PPM Control Settings ........................................................................................... 18-7
PPM Signal Short Functionality ............................................................................... 18-9
TouCAN Shorting ................................................................................................. 18-9
TPU Shorting ........................................................................................................ 18-9
ETRIG1 and ETRIG2 ........................................................................................... 18-9
T2CLK ................................................................................................................ 18-10
PPM Module Pad Configuration ............................................................................. 18-10
PPM Registers ............................................................................................................. 18-10
Module Configuration Register (PPMMCR) .......................................................... 18-10
Entering Stop Mode ............................................................................................ 18-11
PPM Control Register (PPMPCR) .......................................................................... 18-12
Transmit Configuration Registers (TX_CONFIG_1 and TX_CONFIG_2) ........... 18-15
Receive Configuration Registers (RX_CONFIG_1 and RX_CONFIG_2) ............ 18-16
Receive Data Register (RX_DATA) ...................................................................... 18-17
Receive Shift Register (RX_SHIFTER) ................................................................. 18-18
Transmit Data Register (TX_DATA) ..................................................................... 18-18
General-Purpose Data Out (GPDO) ....................................................................... 18-18
General-Purpose Data In (GPDI) ............................................................................ 18-19
Short Register (SHORT_REG) .............................................................................. 18-19
Short Channels Register (SHORT_CH_REG) ...................................................... 18-22
Scale Transmit Clock Register (SCALE_TCLK_REG) ........................................ 18-24
Chapter 19
Time Processor Unit 3
19.1
19.2
19.2.1
Overview ....................................................................................................................... 19-2
TPU3 Components ........................................................................................................ 19-2
Time Bases ................................................................................................................ 19-2
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
19.2.2
19.2.3
19.2.4
19.2.5
19.2.6
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
19.3.9
19.4
19.4.1
19.4.2
19.4.3
19.4.4
19.4.5
19.4.6
19.4.7
19.4.8
19.4.9
19.4.10
19.4.11
19.4.12
19.4.13
19.4.14
19.4.15
19.5
Title
Page
Number
Timer Channels ......................................................................................................... 19-2
Scheduler .................................................................................................................. 19-2
Microengine .............................................................................................................. 19-3
Host Interface ............................................................................................................ 19-3
Parameter RAM ........................................................................................................ 19-3
TPU Operation .............................................................................................................. 19-3
Event Timing ............................................................................................................ 19-3
Channel Orthogonality .............................................................................................. 19-4
Interchannel Communication .................................................................................... 19-4
Programmable Channel Service Priority .................................................................. 19-4
Coherency ................................................................................................................. 19-4
Emulation Support .................................................................................................... 19-4
TPU3 Interrupts ........................................................................................................ 19-5
Prescaler Control for TCR1 ...................................................................................... 19-5
Prescaler Control for TCR2 ...................................................................................... 19-7
Programming Model ..................................................................................................... 19-8
TPU Module Configuration Register (TPUMCR) ................................................. 19-11
Development Support Control Register (DSCR) .................................................... 19-12
Development Support Status Register (DSSR) ...................................................... 19-13
TPU3 Interrupt Configuration Register (TICR) ..................................................... 19-14
Channel Interrupt Enable Register (CIER) ............................................................. 19-15
Channel Function Select Registers (CFSRn) .......................................................... 19-15
Host Sequence Registers (HSQRn) ........................................................................ 19-16
Host Service Request Registers (HSRRn) ............................................................. 19-17
Channel Priority Registers (CPRx) ......................................................................... 19-18
Channel Interrupt Status Register (CISR) .............................................................. 19-19
TPU3 Module Configuration Register 2 (TPUMCR2) ........................................... 19-19
TPU Module Configuration Register 3 (TPUMCR3) ............................................. 19-21
SIU Test Register (SIUTST) ................................................................................... 19-22
Factory Test Registers ............................................................................................ 19-22
TPU3 Parameter RAM ............................................................................................ 19-23
Time Functions ........................................................................................................... 19-23
Chapter 20
Dual-Port TPU3 RAM (DPTRAM)
20.1
20.2
20.3
20.3.1
20.3.2
Features ......................................................................................................................... 20-1
DPTRAM Configuration Block Diagram ..................................................................... 20-2
Programming Model ..................................................................................................... 20-2
DPTRAM Module Configuration Register (DPTMCR) ......................................... 20-3
DPTRAM Test Register (DPTTCR) ......................................................................... 20-4
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxvi
Contents
Paragraph
Number
20.3.3
20.3.4
20.3.5
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.4.6
20.5
Title
Page
Number
RAM Base Address Register (RAMBAR) ............................................................... 20-4
MISR High (MISRH) and MISR Low Registers (MISRL) ...................................... 20-5
MISC Counter (MISCNT) ........................................................................................ 20-6
DPTRAM Operation ..................................................................................................... 20-6
Normal Operation ..................................................................................................... 20-6
Standby Operation .................................................................................................... 20-6
Reset Operation ......................................................................................................... 20-7
Stop Operation .......................................................................................................... 20-7
Freeze Operation ....................................................................................................... 20-7
TPU3 Emulation Mode Operation ............................................................................ 20-7
Multiple Input Signature Calculator (MISC) ................................................................ 20-8
Chapter 21
CDR3 Flash (UC3F) EEPROM
21.0.1
21.1
21.1.1
21.2
21.2.1
21.2.1.1
21.2.1.2
21.2.1.3
21.2.1.4
21.2.2
21.2.3
21.2.3.1
21.2.4
21.3
21.3.1
21.3.2
21.3.3
21.3.3.1
21.3.4
21.3.5
21.3.6
21.3.6.1
21.3.7
21.3.7.1
21.3.7.2
21.3.7.3
Features of the CDR3 Flash EEPROM (UC3F) ....................................................... 21-3
UC3F Interface ............................................................................................................. 21-4
External Interface ...................................................................................................... 21-4
Programming Model ..................................................................................................... 21-5
UC3F EEPROM Control Registers .......................................................................... 21-5
Register Addressing .............................................................................................. 21-5
UC3F EEPROM Configuration Register (UC3FMCR) ....................................... 21-5
UC3F EEPROM Extended Configuration Register (UC3FMCRE) ..................... 21-8
UC3F EEPROM High Voltage Control Register (UC3FCTL) .......................... 21-11
UC3F EEPROM Array Addressing ........................................................................ 21-15
UC3F EEPROM Shadow Row ............................................................................... 21-15
Reset Configuration Word (UC3FCFIG) ........................................................... 21-16
UC3F EEPROM 512-Kbyte Array Configuration .................................................. 21-19
UC3F Operation .......................................................................................................... 21-19
Reset ........................................................................................................................ 21-19
Register Read and Write Operation ........................................................................ 21-20
Array Read Operation ............................................................................................. 21-20
Array On-Page Read Operation .......................................................................... 21-21
Shadow Row Select Read Operation ...................................................................... 21-21
Array Program/Erase Interlock Write Operation .................................................... 21-21
High Voltage Operations ........................................................................................ 21-21
Overview of Program/Erase Operation .............................................................. 21-21
Programming .......................................................................................................... 21-21
Program Sequence .............................................................................................. 21-22
Program Shadow Information ............................................................................. 21-24
Program Suspend ................................................................................................ 21-25
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
21.3.8
21.3.8.1
21.3.8.2
21.3.8.3
21.3.9
21.3.10
21.3.11
21.3.11.1
21.3.11.2
21.3.11.3
21.3.11.4
21.3.12
Title
Page
Number
Erasing .................................................................................................................... 21-25
Erase Sequence ................................................................................................... 21-26
Erasing Shadow Information Words .................................................................. 21-28
Erase Suspend ..................................................................................................... 21-28
Stop Operation ........................................................................................................ 21-28
Disabled .................................................................................................................. 21-29
Censored Accesses and Non-Censored Accesses ................................................... 21-29
Setting and Clearing Censor ............................................................................... 21-31
Setting Censor ..................................................................................................... 21-32
Clearing Censor .................................................................................................. 21-32
Switching The UC3F EEPROM Censorship ...................................................... 21-33
Background Debug Mode or Freeze Operation ...................................................... 21-34
Chapter 22
CALRAM Operation
22.1
22.2
22.3
22.4
22.4.1
22.4.2
22.4.2.1
22.4.3
22.4.4
22.4.5
22.4.6
22.4.6.1
22.4.6.2
22.4.6.3
22.4.6.4
22.5
22.5.1
22.5.2
22.5.3
22.5.4
Features ......................................................................................................................... 22-1
CALRAM Block Diagram ............................................................................................ 22-2
CALRAM Memory Map .............................................................................................. 22-2
Modes of Operation ...................................................................................................... 22-4
Reset .......................................................................................................................... 22-5
One-Cycle Mode ....................................................................................................... 22-5
CALRAM Access/Privilege Violations ................................................................ 22-5
Two-Cycle Mode ...................................................................................................... 22-5
Standby Operation/Keep-Alive Power .................................................................... 22-5
Stop Operation .......................................................................................................... 22-6
Overlay Mode Operation ......................................................................................... 22-6
Overlay Mode Configuration ................................................................................ 22-6
Priority of Overlay Regions ................................................................................ 22-11
Normal (Non-Overlay) Access to Overlay Regions ........................................... 22-12
Calibration Write Cycle Flow ............................................................................. 22-12
Programming Model ................................................................................................... 22-12
CALRAM Module Configuration Register (CRAMMCR) .................................... 22-13
CALRAM Region Base Address Registers (CRAM_RBAx) ................................ 22-15
CALRAM Overlay Configuration Register (CRAM_OVLCR) ............................. 22-17
CALRAM Ownership Trace Register (CRAM_OTR) ........................................... 22-17
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
Title
Page
Number
Chapter 23
Development Support
23.1
23.1.1
23.1.1.1
23.1.1.2
23.1.1.3
23.1.2
23.1.3
23.1.4
23.1.4.1
23.1.4.2
23.1.4.3
23.1.4.4
23.1.4.5
23.1.5
23.2
23.2.1
23.2.1.1
23.2.1.2
23.2.1.3
23.2.1.4
23.2.1.5
23.2.1.6
23.2.2
23.2.2.1
23.2.3
23.2.3.1
23.3
23.3.1
23.3.1.1
23.3.1.2
23.3.1.3
23.3.1.4
23.3.1.5
23.3.1.6
23.4
23.4.1
23.4.2
23.4.3
Program Flow Tracking ................................................................................................ 23-1
Program Trace Cycle ................................................................................................ 23-2
Instruction Queue Status Pins — VF [0:2] ........................................................... 23-2
History Buffer Flushes Status Pins— VFLS [0:1] ............................................... 23-3
Queue Flush Information Special Case ................................................................ 23-4
Program Trace when in Debug Mode ....................................................................... 23-4
Sequential Instructions Marked as Indirect Branch .................................................. 23-4
External Hardware .................................................................................................... 23-4
Synchronizing the Trace Window to the CPU Internal Events ............................ 23-5
Detecting the Trace Window Start Address ......................................................... 23-6
Detecting the Assertion/Negation of VSYNC ...................................................... 23-6
Detecting the Trace Window End Address .......................................................... 23-6
Compress .............................................................................................................. 23-7
Instruction Fetch Show Cycle Control ...................................................................... 23-7
Watchpoints and Breakpoints Support ......................................................................... 23-7
Internal Watchpoints and Breakpoints ...................................................................... 23-9
Restrictions ......................................................................................................... 23-11
Byte and Half-Word Working Modes ................................................................ 23-11
Examples ............................................................................................................. 23-12
Context Dependent Filter .................................................................................... 23-13
Ignore First Match .............................................................................................. 23-14
Generating Six Compare Types .......................................................................... 23-14
Instruction Support ................................................................................................. 23-14
Load/Store Support ............................................................................................. 23-16
Watchpoint Counters .............................................................................................. 23-19
Trap Enable Programming .................................................................................. 23-19
Development System Interface ................................................................................... 23-19
Debug Mode Support .............................................................................................. 23-21
Debug Mode Enable vs. Debug Mode Disable .................................................. 23-23
Entering Debug Mode ......................................................................................... 23-24
Check Stop State and Debug Mode .................................................................... 23-26
Saving Machine State upon Entering Debug Mode ........................................... 23-27
Running in Debug Mode .................................................................................... 23-27
Exiting Debug Mode ........................................................................................... 23-28
Development Port ....................................................................................................... 23-28
Development Port Pins ........................................................................................... 23-28
Development Serial Clock ...................................................................................... 23-29
Development Serial Data In .................................................................................... 23-29
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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Contents
Paragraph
Number
23.4.4
23.4.5
23.4.5.1
23.4.5.2
23.4.5.3
23.4.6
23.4.6.1
23.4.6.2
23.4.6.3
23.4.6.4
23.4.6.5
23.4.6.6
23.4.6.7
23.4.6.8
23.4.6.9
23.4.6.10
23.4.6.11
23.5
23.5.1
23.6
23.6.1
23.6.2
23.6.3
23.6.4
23.6.5
23.6.6
23.6.7
23.6.8
23.6.9
23.6.10
23.6.11
23.6.12
23.6.13
Title
Page
Number
Development Serial Data Out ................................................................................. 23-29
Freeze Signal ........................................................................................................... 23-29
SGPIO6/FRZ/PTR Signal ................................................................................... 23-30
IWP[0:1]/VFLS[0:1] Signals .............................................................................. 23-30
VFLS[0:1]/MPIO32B[3:4] Signals ................................................................... 23-30
Development Port Registers ................................................................................... 23-30
Development Port Shift Register ........................................................................ 23-30
Trap Enable Control Register ............................................................................. 23-30
Development Port Registers Decode .................................................................. 23-31
Development Port Serial Communications — Clock Mode Selection ............... 23-31
Development Port Serial Communications — Trap Enable Mode .................... 23-33
Serial Data into Development Port — Trap Enable Mode ................................. 23-33
Serial Data Out of Development Port — Trap Enable Mode ............................. 23-34
Development Port Serial Communications — Debug Mode ............................. 23-35
Serial Data Into Development Port ..................................................................... 23-35
Serial Data Out of Development Port ................................................................. 23-36
Fast Download Procedure ................................................................................... 23-37
Software Monitor Debugger Support ......................................................................... 23-38
Freeze Indication ..................................................................................................... 23-38
Development Support Registers ................................................................................. 23-39
Register Protection .................................................................................................. 23-40
Comparator A–D Value Registers (CMPA–CMPD) .............................................. 23-41
Exception Cause Register (ECR) ............................................................................ 23-41
Debug Enable Register (DER) ................................................................................ 23-43
Breakpoint Counter A Value and Control Register ................................................ 23-45
Breakpoint Counter B Value and Control Register ................................................ 23-46
Comparator E–F Value Registers (CMPE–CMPF) ................................................ 23-46
Comparator G–H Value Registers (CMPG–CMPH) .............................................. 23-47
L-Bus Support Control Register 1 .......................................................................... 23-47
L-Bus Support Control Register 2 .......................................................................... 23-48
I-Bus Support Control Register (ICTRL) ............................................................... 23-51
Breakpoint Address Register (BAR) ...................................................................... 23-53
Development Port Data Register (DPDR) .............................................................. 23-53
Chapter 24
READI Module
24.1
24.1.1
24.2
24.2.1
Features Summary ........................................................................................................ 24-1
Functional Block Diagram ........................................................................................ 24-2
Modes of Operation ...................................................................................................... 24-3
Reset Configuration .................................................................................................. 24-3
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
24.2.2
24.2.3
24.2.4
24.3
24.4
24.5
24.6
24.6.1
24.6.1.1
24.6.1.2
24.6.1.3
24.6.1.4
24.6.1.5
24.6.1.6
24.6.1.7
24.6.1.8
24.6.1.9
24.6.2
24.6.3
24.6.4
24.6.5
24.6.5.1
24.6.5.2
24.7
24.7.1
24.7.1.1
24.7.2
24.7.3
24.7.4
24.7.5
24.7.5.1
24.7.5.2
24.7.5.3
24.7.5.3.1
24.7.5.3.2
24.7.5.4
24.7.6
24.7.7
24.7.7.1
24.7.7.2
Title
Page
Number
Security ..................................................................................................................... 24-4
Normal ...................................................................................................................... 24-4
Disabled .................................................................................................................... 24-4
Parametrics .................................................................................................................... 24-4
Messages ....................................................................................................................... 24-4
Terms and Definitions .................................................................................................. 24-6
Programming Model ..................................................................................................... 24-8
Register Map ............................................................................................................. 24-8
User-Mapped Register (OTR) .............................................................................. 24-8
Tool-Mapped Registers ........................................................................................ 24-9
Device ID Register (DID) ..................................................................................... 24-9
Development Control Register (DC) .................................................................. 24-10
Mode Control Register (MC) .............................................................................. 24-11
User Base Address Register (UBA) ................................................................... 24-12
Read/Write Access Register (RWA) .................................................................. 24-13
Upload/Download Information Register (UDI) .................................................. 24-15
Data Trace Attributes 1 and 2 Registers (DTA1 and DTA2) ............................. 24-17
Accessing Memory-Mapped Locations Via
the Auxiliary Port ............................................................................................... 24-18
Accessing READI Tool Mapped Registers Via the Auxiliary Port ........................ 24-19
Partial Register Updates .......................................................................................... 24-19
Programming Considerations ................................................................................. 24-20
Program Trace Guidelines .................................................................................. 24-20
Compressed Code Mode Guidelines .................................................................. 24-20
Signal Interface ........................................................................................................... 24-20
Functional Description ............................................................................................ 24-21
Signals Implemented .......................................................................................... 24-21
Functional Block Diagram ...................................................................................... 24-22
Message Priority ..................................................................................................... 24-22
Signal Protocol ........................................................................................................ 24-23
Messages ................................................................................................................. 24-24
Message Formats ................................................................................................ 24-28
Rules of Messages .............................................................................................. 24-31
Branch Trace Message Examples ....................................................................... 24-32
Example of Indirect Branch Message ............................................................. 24-32
Example of Direct Branch Message ............................................................... 24-33
Non-Temporal Ordering of Transmitted Messages ............................................ 24-33
READI Reset Configuration ................................................................................... 24-34
READI Signals ....................................................................................................... 24-36
Reset Configuration for Debug Mode ................................................................ 24-36
Reset Configuration for Non-Debug Mode ........................................................ 24-37
MPC561/MPC563 Reference Manual, Rev. 1.2
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Paragraph
Number
24.7.7.3
24.7.7.4
24.7.7.5
24.8
24.8.1
24.8.1.1
24.8.2
24.8.2.1
24.8.2.2
24.8.2.3
24.8.2.4
24.8.2.4.1
24.8.2.4.2
24.8.2.4.3
24.8.2.4.4
24.8.2.4.5
24.8.2.5
24.8.2.6
24.8.3
24.8.4
24.8.4.1
24.8.4.2
24.8.4.3
24.8.4.4
24.8.5
24.8.6
24.8.7
24.9
24.9.1
24.9.2
24.9.2.1
24.9.2.2
24.9.2.3
24.9.2.4
24.9.2.5
24.9.2.6
24.9.3
24.9.4
24.9.5
24.9.6
24.9.7
Title
Page
Number
Secure Mode ....................................................................................................... 24-37
Disabled Mode .................................................................................................... 24-37
Guidelines for Transmitting Input Messages ...................................................... 24-37
Program Trace ............................................................................................................ 24-38
Branch Trace Messaging ........................................................................................ 24-38
RCPU Instructions that Cause BTM Messages .................................................. 24-38
BTM Message Formats ........................................................................................... 24-38
Direct Branch Messages ..................................................................................... 24-38
Indirect Branch Messages ................................................................................... 24-39
Correction Messages ........................................................................................... 24-40
Synchronization Messages .................................................................................. 24-42
Direct Branch Synchronization Message ....................................................... 24-44
Indirect Branch Synchronization Message ..................................................... 24-44
Direct Branch Synchronization Message With Compressed Code ................ 24-44
Indirect Branch Synchronization Message with Compressed Code ............... 24-45
Resource Full Message ................................................................................... 24-45
Error Messages ................................................................................................... 24-46
Relative Addressing ............................................................................................ 24-46
Queue Overflow Program Trace Error Message .................................................... 24-47
Branch Trace Message Operation ........................................................................... 24-47
BTM Capture and Encoding Algorithm ............................................................. 24-47
Instruction Fetch Snooping ................................................................................. 24-48
Instruction Execution Tracking .......................................................................... 24-48
Instruction Flush Cases ....................................................................................... 24-48
Branch Trace Message Queueing ........................................................................... 24-48
BTM Timing Diagrams .......................................................................................... 24-49
Program Trace Guidelines ...................................................................................... 24-51
Data Trace .................................................................................................................. 24-52
Data Trace for the Load/Store Bus (L-Bus) ............................................................ 24-52
Data Trace Message Formats .................................................................................. 24-52
Data Write Message ............................................................................................ 24-52
Data Read Message ............................................................................................. 24-53
Data Trace Synchronization Messages ............................................................... 24-53
Data Write Synchronization Message ................................................................ 24-54
Data Read Synchronization Messaging .............................................................. 24-54
Relative Addressing ............................................................................................ 24-54
Queue Overflow Data Trace Error Message ........................................................... 24-54
Data Trace Operation .............................................................................................. 24-54
Data Trace Windowing ........................................................................................... 24-56
Special L-Bus Cases ............................................................................................... 24-56
Data Trace Queuing ................................................................................................ 24-56
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
24.9.8
24.9.8.1
24.9.8.2
24.9.9
24.10
24.10.1
24.10.2
24.10.2.1
24.10.2.2
24.10.3
24.10.3.1
24.10.3.2
24.10.4
24.10.4.1
24.10.4.2
24.10.5
24.10.5.1
24.10.5.2
24.10.5.3
24.10.6
24.10.7
24.10.8
24.10.8.1
24.10.8.2
24.10.8.3
24.10.9
24.10.10
24.10.10.1
24.11
24.12
24.12.1
24.12.1.1
24.12.2
24.12.3
24.12.4
24.13
24.13.1
24.13.2
24.13.2.1
24.13.2.2
24.13.3
Title
Page
Number
Throughput and Latency ......................................................................................... 24-57
Assumptions for Throughput Analysis ............................................................... 24-57
Throughput Calculations .................................................................................... 24-57
Data Timing Diagrams ............................................................................................ 24-57
Read/Write Access ...................................................................................................... 24-59
Functional Description ............................................................................................ 24-59
Write Operation to Memory-Mapped Locations and SPR Registers ..................... 24-61
Single Write Operation ....................................................................................... 24-61
Block Write Operation ........................................................................................ 24-62
Read Operation to Memory-Mapped Locations and SPR Registers ...................... 24-63
Single Read Operation ........................................................................................ 24-63
Block Read Operation ......................................................................................... 24-64
Read/Write Access to Internal READI Registers ................................................... 24-64
Write Operation .................................................................................................. 24-64
Read Operation ................................................................................................... 24-65
Error Handling ........................................................................................................ 24-65
Access Alignment ............................................................................................... 24-65
L-Bus Address Error ........................................................................................... 24-65
L-Bus Data Error ................................................................................................ 24-65
Exception Sequences .............................................................................................. 24-66
Secure Mode ........................................................................................................... 24-66
Error Messages ....................................................................................................... 24-66
Read/Write Access Error .................................................................................... 24-66
Invalid Message .................................................................................................. 24-67
Invalid Access Opcode ....................................................................................... 24-67
Faster Read/Write Accesses with Default Attributes ............................................. 24-67
Throughput and Latency ......................................................................................... 24-68
Assumptions for Throughput Analysis ............................................................... 24-68
Read/Write Timing Diagrams ..................................................................................... 24-69
Watchpoint Support ................................................................................................... 24-72
Watchpoint Messaging ........................................................................................... 24-72
Watchpoint Source Field .................................................................................... 24-73
Watchpoint Overrun Error Message ....................................................................... 24-73
Synchronization ...................................................................................................... 24-74
Watchpoint Timing Diagrams ................................................................................ 24-74
Ownership Trace ........................................................................................................ 24-74
Ownership Trace Messaging .................................................................................. 24-75
Queue Overflow Ownership Trace Error Message ................................................. 24-75
OTM Flow .......................................................................................................... 24-75
OTM Queueing ................................................................................................... 24-76
OTM Timing Diagrams .......................................................................................... 24-76
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
24.14
24.14.1
24.14.1.1
24.14.1.2
24.14.1.3
24.14.1.4
24.14.2
24.14.2.1
24.14.2.2
24.14.2.3
24.14.2.4
24.14.3
24.14.4
24.15
24.15.1
24.15.2
Title
Page
Number
RCPU Development Access ...................................................................................... 24-76
RCPU Development Access Messaging ................................................................. 24-77
DSDI Message .................................................................................................... 24-77
DSDO Message .................................................................................................. 24-78
BDM Status Message ......................................................................................... 24-78
Error Message (Invalid Message) ....................................................................... 24-79
RCPU Development Access Operation .................................................................. 24-79
Enabling RCPU Development Access Via READI Signals ............................... 24-80
Entering Background Debug Mode (BDM) Via READI Signals ...................... 24-80
Non-Debug Mode Access of RCPU Development Access ................................ 24-80
RCPU Development Access Flow Diagram ....................................................... 24-81
Throughput .............................................................................................................. 24-82
Development Access Timing Diagrams ................................................................. 24-82
Power Management ................................................................................................... 24-86
Functional Description ............................................................................................ 24-86
Low Power Modes .................................................................................................. 24-86
Chapter 25
IEEE 1149.1-Compliant Interface (JTAG)
25.1
25.1.1
25.1.2
25.1.2.1
25.1.2.2
25.1.3
25.1.3.1
25.1.3.2
25.1.3.3
25.1.3.4
25.1.4
25.2
25.2.1
25.2.2
IEEE 1149.1 Test Access Port ...................................................................................... 25-1
Overview ................................................................................................................... 25-2
Entering JTAG Mode ................................................................................................ 25-3
TAP Controller ..................................................................................................... 25-4
Boundary Scan Register ....................................................................................... 25-4
Instruction Register ................................................................................................. 25-30
EXTEST ............................................................................................................. 25-31
SAMPLE/PRELOAD ......................................................................................... 25-31
BYPASS ............................................................................................................. 25-31
CLAMP ............................................................................................................... 25-32
HI-Z ........................................................................................................................ 25-32
MPC561/MPC563 Restrictions .................................................................................. 25-32
Non-Scan Chain Operation ..................................................................................... 25-32
BSDL Description ................................................................................................... 25-33
Appendix A
MPC562/MPC564 Compression Features
A.1
A.2
ICDU Key Features ........................................................................................................ A-1
Class-Based Compression Model Main Principles......................................................... A-1
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
A.2.1
A.2.2
A.2.3
A.2.4
A.2.5
A.2.6
A.2.7
A.2.8
A.2.8.1
A.2.8.2
A.2.8.3
A.2.9
A.2.9.1
A.2.9.2
A.2.9.3
A.2.9.4
A.2.9.5
A.2.10
A.2.11
A.2.12
A.2.13
A.2.14
A.2.14.1
A.2.14.2
A.3
A.3.1
A.3.1.1
A.3.1.2
A.3.1.2.1
A.3.2
A.3.3
A.3.3.1
A.4
Title
Page
Number
Compression Model Features ..................................................................................... A-1
Model Limitations....................................................................................................... A-2
Instruction Class-Based Compression Algorithm....................................................... A-2
Compressed Address Generation with Direct Branches............................................. A-4
Compressed Address Generation—Indirect Branches ............................................... A-6
Compressed Address Generation—Exceptions .......................................................... A-6
Class Code Compression Algorithm Rules ................................................................ A-7
Bypass Field Compression Rules ............................................................................... A-7
Branch Right Segment Compression #1................................................................. A-7
Branch Right Segment Compression #2................................................................. A-8
Right Segment Zero Length Compression Bypass................................................. A-8
Instruction Class Structures and Programming .......................................................... A-8
Global Bypass......................................................................................................... A-8
Single Segment Full Compression – CLASS_1 ..................................................... A-9
Twin Segment Full Compression – CLASS_2 ....................................................... A-9
Left Segment Compression and Right Segment Bypass – CLASS_3................. A-10
Left Segment Bypass and Right Segment Compression—CLASS_4..................A-11
Instruction Layout Programming Summary ..............................................................A-11
Compression Process .................................................................................................A-11
Decompression.......................................................................................................... A-12
Compression Environment Initialization .................................................................. A-13
Compression/Non-Compression Mode Switch ........................................................ A-14
Compression Definition for Exception Handlers ................................................. A-14
Running Mixed Code............................................................................................ A-14
Operation Modes........................................................................................................... A-14
Instruction Fetch ....................................................................................................... A-14
Decompression Off Mode..................................................................................... A-15
Decompression On Mode ..................................................................................... A-15
Show Cycles in Decompression On Mode ....................................................... A-15
Vocabulary Table Storage Operation ........................................................................ A-16
READI Compression ................................................................................................ A-16
I-Bus Support Control Register (ICTRL) ............................................................. A-16
Decompressor Class Configuration Registers (DCCR0-15) ........................................ A-18
MPC561/MPC563 Reference Manual, Rev. 1.2
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Paragraph
Number
Title
Page
Number
Appendix B
Internal Memory Map
Appendix C
Clock and Board Guidelines
C.1
C.2
C.2.1
C.2.2
C.2.3
C.3
C.3.1
C.3.2
C.3.3
MPC56x Device Power Distribution ...............................................................................C-2
Crystal Oscillator External Components .........................................................................C-4
KAPWR Filtering ........................................................................................................C-5
PLL External Components...........................................................................................C-5
PLL Off-Chip Capacitor CXFC...................................................................................C-6
PLL and Clock Oscillator External Components Layout Requirements .........................C-7
Traces and Placement ..................................................................................................C-7
Grounding/Guarding....................................................................................................C-7
IRAMSTBY Regulator Circuit....................................................................................C-7
Appendix D
TPU3 ROM Functions
D.1
D.2
D.3
D.4
D.5
D.6
D.7
D.8
D.9
D.10
D.11
D.12
D.13
D.14
D.15
D.16
D.17
D.18
D.19
D.20
D.20.1
Overview......................................................................................................................... D-1
Programmable Time Accumulator (PTA) ....................................................................... D-3
Queued Output Match TPU3 Function (QOM) .............................................................. D-5
Table Stepper Motor (TSM)............................................................................................ D-7
Frequency Measurement (FQM) .................................................................................. D-10
Universal Asynchronous Receiver/Transmitter (UART).............................................. D-12
New Input Capture/Transition Counter (NITC)............................................................ D-15
Multiphase Motor Commutation (COMM) .................................................................. D-17
Hall Effect Decode (HALLD) ...................................................................................... D-20
Multichannel Pulse-Width Modulation (MCPWM) ..................................................... D-22
Multi TPU (MULTI) ..................................................................................................... D-30
Fast Quadrature Decode TPU3 Function (FQD) .......................................................... D-35
Period/Pulse-Width Accumulator (PPWA)................................................................... D-38
ID TPU3 Function (ID)................................................................................................. D-40
Output Compare (OC) .................................................................................................. D-42
Pulse-Width Modulation (PWM).................................................................................. D-44
Discrete Input/Output (DIO)......................................................................................... D-46
Synchronized Pulse-Width Modulation (SPWM)......................................................... D-48
Read/Write Timers and Pin TPU3 Function (RWTPIN) .............................................. D-51
Serial Input/Output Port (SIOP) ................................................................................... D-53
Parameters................................................................................................................. D-53
MPC561/MPC563 Reference Manual, Rev. 1.2
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Contents
Paragraph
Number
D.20.1.1
D.20.1.2
D.20.1.3
D.20.1.4
D.20.1.5
D.20.1.6
D.20.2
D.20.3
D.20.3.1
D.20.3.2
D.20.3.3
Title
Page
Number
CHAN_CONTROL .............................................................................................. D-56
BIT_D ................................................................................................................... D-56
HALF_PERIOD ................................................................................................... D-56
BIT_COUNT ........................................................................................................ D-56
XFER_SIZE.......................................................................................................... D-56
SIOP_DATA ......................................................................................................... D-57
Host RCPU Initialization of the SIOP Function....................................................... D-57
SIOP Function Performance ..................................................................................... D-57
XFER_SIZE Greater Than 16 .............................................................................. D-58
Data Positioning.................................................................................................... D-58
Data Timing .......................................................................................................... D-58
Appendix E
Memory Access Timing
Appendix F
Electrical Characteristics
F.1
F.2
F.2.1
F.2.2
F.2.3
F.3
F.3.1
F.4
F.5
F.6
F.7
F.8
F.8.1
F.8.2
F.9
F.9.1
F.9.2
F.10
F.10.1
F.11
F.12
F.13
Package ............................................................................................................................ F-2
EMI Characteristics ......................................................................................................... F-2
Reference Documents .................................................................................................. F-2
Definitions and Acronyms ........................................................................................... F-3
EMI Testing Specifications.......................................................................................... F-3
Thermal Characteristics ................................................................................................... F-3
Thermal References ..................................................................................................... F-5
ESD Protection ................................................................................................................ F-6
DC Electrical Characteristics........................................................................................... F-7
Oscillator and PLL Electrical Characteristics................................................................ F-11
Flash Electrical Characteristics...................................................................................... F-12
Power-Up/Down Sequencing......................................................................................... F-13
Power-Up/Down Option A ........................................................................................ F-13
Power-Up/Down Option B ........................................................................................ F-15
Issues Regarding Power Sequence ................................................................................ F-17
Application of PORESET or HRESET ..................................................................... F-17
Keep-Alive RAM....................................................................................................... F-18
AC Timing ..................................................................................................................... F-18
Debug Port Timing .................................................................................................... F-43
READI Electrical Characteristics .................................................................................. F-45
RESET Timing............................................................................................................... F-47
IEEE 1149.1 Electrical Characteristics.......................................................................... F-50
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxxvii
Contents
Paragraph
Number
F.14
F.15
F.16
F.17
F.18
F.19
F.20
F.20.1
F.20.2
F.20.3
F.21
F.22
F.22.1
F.22.1.1
Title
Page
Number
QADC64E Electrical Characteristics............................................................................. F-54
QSMCM Electrical Characteristics ............................................................................... F-56
GPIO Electrical Characteristics ..................................................................................... F-60
TPU3 Electrical Characteristics..................................................................................... F-61
TouCAN Electrical Characteristics................................................................................ F-62
PPM Timing Characteristics .......................................................................................... F-62
MIOS Timing Characteristics ........................................................................................ F-64
MPWMSM Timing Characteristics ........................................................................... F-64
MMCSM Timing Characteristics .............................................................................. F-67
MDASM Timing Characteristics............................................................................... F-69
MPIOSM Timing Characteristics .................................................................................. F-71
Pin Summary ................................................................................................................. F-73
Package Diagrams...................................................................................................... F-83
MPC561/MPC563 Ball Map ................................................................................. F-86
Appendix G
66-MHz Electrical Characteristics
G.1
G.2
G.3
G.3.1
G.3.2
G.3.3
G.4
G.4.1
G.5
G.6
G.7
G.8
G.9
G.9.1
G.9.2
G.10
G.10.1
G.10.2
G.11
G.11.1
G.12
G.13
G.14
66-MHz Feature Limitations .......................................................................................... G-1
Package ........................................................................................................................... G-3
EMI Characteristics ........................................................................................................ G-3
Reference Documents ................................................................................................. G-3
Definitions and Acronyms .......................................................................................... G-3
EMI Testing Specifications......................................................................................... G-3
Thermal Characteristics .................................................................................................. G-3
Thermal References .................................................................................................... G-6
ESD Protection ............................................................................................................... G-6
DC Electrical Characteristics.......................................................................................... G-7
Oscillator and PLL Electrical Characteristics............................................................... G-10
Flash Electrical Characteristics......................................................................................G-11
Power-Up/Down Sequencing........................................................................................ G-12
Power-Up/Down Option A ....................................................................................... G-13
Power-Up/Down Option B ....................................................................................... G-15
Issues Regarding Power Sequence ............................................................................... G-17
Application of PORESET or HRESET .................................................................... G-17
Keep-Alive RAM...................................................................................................... G-18
AC Timing .................................................................................................................... G-18
Debug Port Timing ................................................................................................... G-41
READI Electrical Characteristics ................................................................................. G-43
RESET Timing.............................................................................................................. G-44
IEEE 1149.1 Electrical Characteristics......................................................................... G-47
MPC561/MPC563 Reference Manual, Rev. 1.2
xxxviii
Freescale Semiconductor
Contents
Paragraph
Number
G.15
G.16
G.17
G.18
G.19
G.20
G.21
G.21.1
G.21.2
G.21.3
G.22
G.23
G.23.1
G.23.1.1
Title
Page
Number
QADC64E Electrical Characteristics............................................................................ G-50
QSMCM Electrical Characteristics .............................................................................. G-52
GPIO Electrical Characteristics .................................................................................... G-56
TPU3 Electrical Characteristics.................................................................................... G-57
TouCAN Electrical Characteristics............................................................................... G-58
PPM Timing Characteristics ......................................................................................... G-58
MIOS Timing Characteristics ....................................................................................... G-59
MPWMSM Timing Characteristics .......................................................................... G-60
MMCSM Timing Characteristics ............................................................................. G-62
MDASM Timing Characteristics.............................................................................. G-64
MPIOSM Timing Characteristics ................................................................................. G-67
Pin Summary ................................................................................................................ G-68
Package Diagrams..................................................................................................... G-78
MPC561/MPC563 Ball Map ................................................................................ G-81
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxxix
Contents
Paragraph
Number
Title
Page
Number
MPC561/MPC563 Reference Manual, Rev. 1.2
xl
Freescale Semiconductor
Figures
Figure
Number
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
Title
Page
Number
MPC561/MPC563 Block Diagram ........................................................................................... 1-3
Recommended Connection Diagram for IRAMSTBY........................................................... 1-11
MPC561/MPC563 Memory Map ........................................................................................... 1-12
MPC561/MPC563 Internal Memory Map .............................................................................. 1-14
MPC561/MPC563 Signal Groupings ....................................................................................... 2-2
Pads Module Configuration Register (PDMCR) .................................................................... 2-22
Pads Module Configuration Register 2 (PDMCR2) ............................................................... 2-23
Debug Mode Selection (JTAG) .............................................................................................. 2-30
Debug Mode Selection (BDM)............................................................................................... 2-30
Debug Mode Selection (Nexus).............................................................................................. 2-31
RCPU Block Diagram .............................................................................................................. 3-2
Sequencer Data Path ................................................................................................................. 3-4
RCPU Programming Model ..................................................................................................... 3-8
General-Purpose Registers (GPRs)......................................................................................... 3-12
Floating-Point Registers (FPRs) ............................................................................................. 3-13
Floating-Point Status and Control Register (FPSCR)............................................................. 3-14
Condition Register (CR) ......................................................................................................... 3-16
Integer Exception Register (XER) .......................................................................................... 3-18
Link Register (LR).................................................................................................................. 3-19
Count Register (CTR) ............................................................................................................. 3-19
Machine State Register (MSR) ............................................................................................... 3-20
DAE/Source Instruction Service Register (DSISR) ............................................................... 3-22
Data Address Register (DAR) ................................................................................................ 3-23
Machine Status Save/Restore Register 0 (SRR0) ................................................................... 3-23
Machine Status Save/Restore Register 1 (SRR1) ................................................................... 3-24
SPRG0–SPRG3 — General Special-Purpose Registers 0–3 .................................................. 3-24
Processor Version Register (PVR) ......................................................................................... 3-25
Floating-Point Exception Cause Register (FPECR) ............................................................... 3-26
Basic Instruction Pipeline ....................................................................................................... 3-38
BBC Module Block Diagram ................................................................................................... 4-2
Exception Table Entries Mapping ............................................................................................ 4-8
External Interrupt Vectors Splitting........................................................................................ 4-12
DECRAM Interfaces Block Diagram ..................................................................................... 4-13
BTB Block Diagram ............................................................................................................... 4-16
MPC561/MPC563 Memory Map ........................................................................................... 4-17
BBC Module Configuration Register (BBCMCR)................................................................. 4-19
Region Base Address Register (MI_RBA[0:3]) ..................................................................... 4-21
Region Attribute Register (MI_RA0[0:3]) ............................................................................. 4-22
Global Region Attribute Register (MI_GRA) ........................................................................ 4-23
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xli
Figures
Figure
Page
Title
Number
Number
4-11
External Interrupt Relocation Table Base Address Register (EIBADR)................................ 4-25
5-1
USIU Block Diagram................................................................................................................ 5-2
6-1
System Configuration and Protection Logic............................................................................. 6-3
6-2
Circuit Paths of Reading and Writing to SGPIO ...................................................................... 6-7
6-3
MPC561/MPC563 Interrupt Structure...................................................................................... 6-9
6-4
Lower Priority Request Masking—One Bit Diagram ............................................................ 6-14
6-5
MPC561/MPC563 Interrupt Controller Block Diagram ........................................................ 6-15
6-6
Typical Interrupt Handler Routine.......................................................................................... 6-17
6-7
RTC Block Diagram ............................................................................................................... 6-20
6-8
PIT Block Diagram ................................................................................................................. 6-21
6-9
SWT State Diagram ................................................................................................................ 6-22
6-10
SWT Block Diagram .............................................................................................................. 6-23
6-11
MPC561/MPC563 Memory Map ........................................................................................... 6-24
6-12
SIU Module Configuration Register (SIUMCR).................................................................... 6-25
6-13
Internal Memory Mapping Register (IMMR)......................................................................... 6-28
6-14
External Master Control Register (EMCR) ............................................................................ 6-30
6-15
SIU Interrupt Pending Register (SIPEND) ............................................................................. 6-32
6-16
SIU Interrupt Pending Register 2 (SIPEND2) ........................................................................ 6-32
6-17
SIU Interrupt Pending Register 3 (SIPEND3) ........................................................................ 6-33
6-18
SIU Interrupt Mask Register (SIMASK) ................................................................................ 6-34
6-19
SIU Interrupt Mask Register 2 (SIMASK2) ........................................................................... 6-34
6-20
SIU Interrupt Mask Register 3 (SIMASK3) ........................................................................... 6-35
6-21
SIU Interrupt Edge Level Register (SIEL) ............................................................................. 6-35
6-22
SIU Interrupt Vector Register (SIVEC).................................................................................. 6-36
6-23
Example of SIVEC Register Usage for Interrupt Table Handling ......................................... 6-36
6-24
Interrupt In-Service Register 2 (SISR2) ................................................................................. 6-37
6-25
Interrupt In-Service Register 3 (SISR3) ................................................................................. 6-37
6-26
System Protection Control Register (SYPCR) ....................................................................... 6-38
6-27
Software Service Register (SWSR) ........................................................................................ 6-39
6-28
Transfer Error Status Register (TESR) ................................................................................... 6-39
6-29
Decrementer Register (DEC).................................................................................................. 6-40
6-30
Time Base (Reading) (TB) ..................................................................................................... 6-41
6-31
Time Base (Writing) (TB) ...................................................................................................... 6-41
6-32
Time Base Reference Register 0 (TBREF0)........................................................................... 6-41
6-33
Time Base Reference Register 1 (TBREF1)........................................................................... 6-41
6-34
Time Base Control and Status Register (TBSCR).................................................................. 6-42
6-35
Real-Time Clock Status and Control Register (RTCSC) ....................................................... 6-43
6-36
Real-Time Clock Register (RTC) ........................................................................................... 6-43
6-37
Real-Time Clock Alarm Register (RTCAL) .......................................................................... 6-44
6-38
Periodic Interrupt Status and Control Register (PISCR) ........................................................ 6-44
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
6-39
Periodic Interrupt Timer Count (PITC) .................................................................................. 6-45
6-40
Periodic Interrupt Timer Register (PITR)............................................................................... 6-45
6-41
SGPIO Data Register 1 (SGPIODT1) .................................................................................... 6-46
6-42
SGPIO Data Register 2 (SGPIODT2) .................................................................................... 6-47
6-43
SGPIO Control Register (SGPIOCR)..................................................................................... 6-48
7-1
Reset Status Register (RSR) ..................................................................................................... 7-5
7-2
Reset Configuration Basic Scheme........................................................................................... 7-8
7-3
Reset Configuration Sampling Scheme for
“Short” PORESET Assertion, Limp Mode Disabled ............................................................... 7-9
7-4
Reset Configuration Timing for “Short” PORESET Assertion, Limp Mode Enabled............. 7-9
7-5
Reset Configuration Timing for “Long” PORESET Assertion, Limp Mode Disabled.......... 7-10
7-6
Reset Configuration Sampling Timing Requirements............................................................ 7-10
7-7
Reset Configuration Word (RCW) ......................................................................................... 7-11
8-1
Clock Unit Block Diagram ....................................................................................................... 8-2
8-2
Main System Oscillator Crystal Configuration ........................................................................ 8-3
8-3
System PLL Block Diagram ..................................................................................................... 8-5
8-4
MPC561/MPC563 Clocks ........................................................................................................ 8-8
8-5
General System Clocks Select ................................................................................................ 8-11
8-6
Divided System Clocks Timing Diagram ............................................................................... 8-12
8-7
Clocks Timing For DFNH = 1 (or DFNL = 0) ....................................................................... 8-13
8-8
Clock Source Switching Flow Chart ...................................................................................... 8-15
8-9
Low-Power Modes Flow Diagram ......................................................................................... 8-20
8-10
IRAMSTBY Regulator Circuit ............................................................................................... 8-23
8-11
Basic Power Supply Configuration......................................................................................... 8-24
8-12
External Power Supply Scheme.............................................................................................. 8-25
8-13
Keep-Alive Register Key State Diagram................................................................................ 8-27
8-14
No Standby, No KAPWR, All System Power-On/Off ........................................................... 8-28
8-15
Standby and KAPWR, Other Power-On/Off .......................................................................... 8-29
8-16
System Clock and Reset Control Register (SCCR) ................................................................ 8-30
8-17
PLL, Low-Power, and Reset-Control Register (PLPRCR) .................................................... 8-34
8-18
Change of Lock Interrupt Register (COLIR).......................................................................... 8-36
8-19
IRAMSTBY Control Register (VSRMCR) ............................................................................ 8-37
9-1
Input Sample Window .............................................................................................................. 9-2
9-2
MPC561/MPC563 Bus Signals ................................................................................................ 9-3
9-3
Basic Transfer Protocol ............................................................................................................ 9-8
9-4
Basic Flow Diagram of a Single Beat Read Cycle ................................................................... 9-9
9-5
Single Beat Read Cycle – Basic Timing – Zero Wait States.................................................. 9-10
9-6
Single Beat Read Cycle – Basic Timing – One Wait State .................................................... 9-11
9-7
Basic Flow Diagram of a Single Beat Write Cycle ................................................................ 9-12
9-8
Single Beat Basic Write Cycle Timing – Zero Wait States .................................................... 9-13
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xliii
Figures
Figure
Page
Title
Number
Number
9-9
Single Beat Basic Write Cycle Timing – One Wait State ...................................................... 9-14
9-10
Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size ......................................... 9-15
9-11
Read Followed by Write when Pre-Discharge Mode is Enabled, and EHTR is Set .............. 9-17
9-12
Basic Flow Diagram Of A Burst-Read Cycle......................................................................... 9-21
9-13
Burst-Read Cycle – 32-Bit Port Size – Zero Wait State......................................................... 9-21
9-14
Burst-Read Cycle – 32-Bit Port Size – One Wait State.......................................................... 9-22
9-15
Burst-Read Cycle – 32-Bit Port Size – Wait States Between Beats ....................................... 9-23
9-16
Burst-Read Cycle – 16-Bit Port Size ...................................................................................... 9-24
9-17
Basic Flow Diagram of a Burst-Write Cycle.......................................................................... 9-26
9-18
Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
(Only for External Master Memory Controller Service Support)........................................... 9-26
9-19
Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst)................................................ 9-27
9-20
Non-Wrap Burst with Three Beats ......................................................................................... 9-28
9-21
Non-Wrap Burst with One Data Beat ..................................................................................... 9-29
9-22
Internal Operand Representation ............................................................................................ 9-30
9-23
Interface To Different Port Size Devices................................................................................ 9-31
9-24
Bus Arbitration Flowchart ...................................................................................................... 9-33
9-25
Master Signals Basic Connection ........................................................................................... 9-34
9-26
Bus Arbitration Timing Diagram............................................................................................ 9-35
9-27
Internal Bus Arbitration State Machine .................................................................................. 9-36
9-28
Termination Signals Protocol Basic Connection .................................................................... 9-41
9-29
Termination Signals Protocol Timing Diagram...................................................................... 9-41
9-30
Reservation on Local Bus ....................................................................................................... 9-43
9-31
Reservation on Multi-level Bus Hierarchy ............................................................................. 9-44
9-32
Retry Transfer Timing – Internal Arbiter ............................................................................... 9-46
9-33
Retry Transfer Timing – External Arbiter .............................................................................. 9-47
9-34
Retry on Burst Cycle............................................................................................................... 9-48
9-35
Basic Flow of an External Master Read Access ..................................................................... 9-50
9-36
Basic Flow of an External Master Write Access .................................................................... 9-51
9-37
Peripheral Mode: External Master Reads from MPC561/MPC563 (Two Wait States) ......... 9-52
9-38
Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States)............ 9-53
9-39
Flow of Retry of External Master Read Access ..................................................................... 9-54
9-40
Retry of External Master Access (Internal Arbiter)................................................................ 9-55
9-41
Instruction Show Cycle Transaction....................................................................................... 9-57
9-42
Data Show Cycle Transaction................................................................................................. 9-58
10-1
Memory Controller Function within the USIU....................................................................... 10-1
10-2
Memory Controller Block Diagram........................................................................................ 10-2
10-3
MPC561/MPC563 Simple System Configuration .................................................................. 10-3
10-4
Bank Base Address and Match Structure ............................................................................... 10-4
10-5
A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts) ............................................. 10-9
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
10-6
4 Beat Burst Read with Short Setup Time (Zero Wait State) ............................................... 10-10
10-7
GPCM–Memory Devices Interface ...................................................................................... 10-12
10-8
Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)....................................... 10-13
10-9
Peripheral Devices Interface ................................................................................................. 10-13
10-10 Peripheral Devices Basic Timing (ACS = 11, TRLX = 0) ................................................... 10-14
10-11 Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1).................................... 10-15
10-12 Relaxed Timing — Write Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) ................ 10-16
10-13 Relaxed Timing — Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) ................ 10-17
10-14 Relaxed Timing — Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1.................. 10-18
10-15 Consecutive Accesses (Write After Read, EHTR = 0) ......................................................... 10-19
10-16 Consecutive Accesses (Write After Read, EHTR = 1) ......................................................... 10-20
10-17 Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1) .......................................................... 10-21
10-18 Consecutive Accesses (Read After Read from Same Bank, EHTR = 1).............................. 10-22
10-19 Aliasing Phenomenon Illustration ........................................................................................ 10-26
10-20 Synchronous External Master
Configuration for GPCM-Handled Memory Devices .......................................................... 10-29
10-21 Synchronous External Master Basic Access (GPCM Controlled)........................................ 10-30
10-22 Memory Controller Status Register (MSTAT) ..................................................................... 10-32
10-23 Memory Controller Base Registers 0–3 (BR0–BR3) ........................................................... 10-32
10-24 Memory Controller Option Registers 1–3 (OR0–OR3) ....................................................... 10-34
10-25 Dual-Mapping Base Register (DMBR) ................................................................................ 10-36
10-26 Dual-Mapping Option Register (DMOR)............................................................................. 10-37
11-1
L2U Bus Interface Block Diagram ......................................................................................... 11-3
11-2
DMPU Basic Functional Diagram .......................................................................................... 11-5
11-3
Region Base Address Example............................................................................................... 11-7
11-4
L2U Module Configuration Register (L2U_MCR) .............................................................. 11-14
11-5
L2U Region x Base Address Register (L2U_RBAx) ........................................................... 11-14
11-6
L2U Region X Attribute Register (L2U_RAx) .................................................................... 11-15
11-7
L2U Global Region Attribute Register (L2U_GRA) ........................................................... 11-16
12-1
UIMB Interface Module Block Diagram................................................................................ 12-2
12-2
IMB3 Clock – Full-Speed IMB3 Bus ..................................................................................... 12-3
12-3
IMB3 Clock – Half-Speed IMB3 Bus .................................................................................... 12-3
12-4
Interrupt Synchronizer Signal Flow........................................................................................ 12-4
12-5
Time-Multiplexing Protocol for IRQ Signals ......................................................................... 12-5
12-6
Interrupt Synchronizer Block Diagram................................................................................... 12-6
12-7
UIMB Module Configuration Register (UMCR) ................................................................... 12-7
12-8
Pending Interrupt Request Register (UIPEND)...................................................................... 12-9
13-1
QADC64E Block Diagram ..................................................................................................... 13-1
13-2
QADC64E Conversion Queue Operation............................................................................... 13-5
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xlv
Figures
Figure
Page
Title
Number
Number
13-3
Example of External Multiplexing ......................................................................................... 13-6
13-4
Module Configuration Register (QADCMCR) ...................................................................... 13-8
13-5
QADC Interrupt Register (QADCINT) ................................................................................ 13-12
13-6
Interrupt Levels on IRQ with ILBS ...................................................................................... 13-13
13-7
Port x Data Register (PORTQA and PORTQB).................................................................. 13-13
13-8
Port A Data Direction Register (DDRQA) .......................................................................... 13-14
13-9
Control Register 0 (QACR0) ................................................................................................ 13-15
13-10
Control Register 1 (QACR1) ............................................................................................... 13-16
13-11 Control Register 2 (QACR2) ................................................................................................ 13-18
13-12 Status Register 0 (QASR0) ................................................................................................... 13-21
13-13 QADC64E Queue Status Transition ..................................................................................... 13-26
13-14 Status Register 1 (QASR1) ................................................................................................... 13-27
13-15 QADC64E Conversion Queue Operation............................................................................. 13-28
13-16 Conversion Command Word Table (CCW) ......................................................................... 13-30
13-17 Right Justified, Unsigned Result Format (RJURR).............................................................. 13-33
13-18 Left Justified, Signed Result Format (LJSRR) ..................................................................... 13-33
13-19 Left Justified, Unsigned Result Register (LJURR) .............................................................. 13-33
13-20 QADC64E Analog Subsystem Block Diagram .................................................................... 13-34
13-21 Conversion Timing ............................................................................................................... 13-35
13-22 Bypass Mode Conversion Timing ........................................................................................ 13-36
13-23 QADC64E Queue Operation with Pause.............................................................................. 13-39
13-24 QADC64E Clock Subsystem Functions ............................................................................... 13-48
13-25 QADC64E Clock Programmability Examples ..................................................................... 13-50
13-26 Bus Cycle Accesses .............................................................................................................. 13-53
13-27 CCW Priority Situation 1...................................................................................................... 13-56
13-28 CCW Priority Situation 2...................................................................................................... 13-56
13-29 CCW Priority Situation 3...................................................................................................... 13-57
13-30 CCW Priority Situation 4...................................................................................................... 13-57
13-31 CCW Priority Situation 5...................................................................................................... 13-58
13-32 CCW Priority Situation 6...................................................................................................... 13-58
13-33 CCW Priority Situation 7...................................................................................................... 13-59
13-34 CCW Priority Situation 8...................................................................................................... 13-59
13-35 CCW Priority Situation 9...................................................................................................... 13-60
13-36 CCW Priority Situation 10.................................................................................................... 13-60
13-37 CCW Priority Situation 11.................................................................................................... 13-61
13-38 CCW Freeze Situation 12 ..................................................................................................... 13-61
13-39 CCW Freeze Situation 13 ..................................................................................................... 13-62
13-40 CCW Freeze Situation 14 ..................................................................................................... 13-62
13-41 CCW Freeze Situation 15 ..................................................................................................... 13-62
13-42 CCW Freeze Situation 16 ..................................................................................................... 13-62
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13-43 CCW Freeze Situation 17 ..................................................................................................... 13-63
13-44 CCW Freeze Situation 18 ..................................................................................................... 13-63
13-45 CCW Freeze Situation 19 ..................................................................................................... 13-63
13-46 External Trigger Mode (Positive Edge) Timing with Pause................................................. 13-64
13-47 Gated Mode, Single-Scan Timing ........................................................................................ 13-65
13-48 Gated Mode, Continuous Scan Timing................................................................................. 13-66
13-49 Equivalent Analog Input Circuitry ....................................................................................... 13-68
13-50 Errors Resulting from Clipping ............................................................................................ 13-69
13-51 Star-Ground at the Point of Power Supply Origin ................................................................ 13-71
13-52 Electrical Model of an A/D Input Signal .............................................................................. 13-72
13-53 External Multiplexing of Analog Signal Sources ................................................................. 13-74
13-54 Input Signal Subjected to Negative Stress ............................................................................ 13-76
13-55 Input Signal Subjected to Positive Stress ............................................................................. 13-77
14-1
QADC64E Block Diagram ..................................................................................................... 14-1
14-2
CCW Queue and Result Table Block Diagram ...................................................................... 14-5
14-3
Example of External Multiplexing ......................................................................................... 14-6
14-4
Module Configuration Register (QADCMCR) ...................................................................... 14-8
14-5
QADC Interrupt Register (QADCINT) ................................................................................ 14-12
14-6
Interrupt Levels on IRQ with ILBS ...................................................................................... 14-12
14-7
Port A Data Register (PORTQA), Port B Data Register (PORTQB)................................... 14-13
14-8
Portx Data Direction Register (DDRQA and DDRQB) ...................................................... 14-14
14-9
Control Register 0 (QACR0) ................................................................................................ 14-14
14-10
Control Register 1 (QACR1) ............................................................................................... 14-16
14-11 Control Register 2 (QACR2) ................................................................................................ 14-18
14-12 Status Register 0 (QASR0) ................................................................................................... 14-22
14-13 Queue Status Transition........................................................................................................ 14-27
14-14 Status Register 1 (QASR1) ................................................................................................... 14-28
14-15 QADC64E Conversion Queue Operation............................................................................. 14-29
14-16 Conversion Command Word Table (CCW) ......................................................................... 14-31
14-17 Right Justified, Unsigned Result Format (RJURR).............................................................. 14-35
14-18 Left Justified, Signed Result Format (LJSRR) ..................................................................... 14-35
14-19 Left Justified, Unsigned Result Register (LJURR) .............................................................. 14-35
14-20 QADC64E Analog Subsystem Block Diagram .................................................................... 14-36
14-21 Conversion Timing ............................................................................................................... 14-37
14-22 QADC64E Queue Operation With Pause ............................................................................. 14-40
14-23 QADC64E Clock Subsystem Functions ............................................................................... 14-49
14-24 Bus Cycle Accesses .............................................................................................................. 14-52
14-25 CCW Priority Situation 1...................................................................................................... 14-55
14-26 CCW Priority Situation 2...................................................................................................... 14-55
14-27 CCW Priority Situation 3...................................................................................................... 14-56
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14-28 CCW Priority Situation 4...................................................................................................... 14-56
14-29 CCW Priority Situation 5...................................................................................................... 14-57
14-30 CCW Priority Situation 6...................................................................................................... 14-57
14-31 CCW Priority Situation 7...................................................................................................... 14-58
14-32 CCW Priority Situation 8...................................................................................................... 14-58
14-33 CCW Priority Situation 9...................................................................................................... 14-59
14-34 CCW Priority Situation 10.................................................................................................... 14-59
14-35 CCW Priority Situation 11.................................................................................................... 14-60
14-36 CCW Freeze Situation 12 ..................................................................................................... 14-60
14-37 CCW Freeze Situation 13 ..................................................................................................... 14-61
14-38 CCW Freeze Situation 14 ..................................................................................................... 14-61
14-39 CCW Freeze Situation 15 ..................................................................................................... 14-61
14-40 CCW Freeze Situation 16 ..................................................................................................... 14-61
14-41 CCW Freeze Situation 17 ..................................................................................................... 14-62
14-42 CCW Freeze Situation 18 ..................................................................................................... 14-62
14-43 CCW Freeze Situation 19 ..................................................................................................... 14-62
14-44 External Trigger Mode (Positive Edge) Timing with Pause................................................. 14-63
14-45 Gated Mode, Single-Scan Timing ........................................................................................ 14-64
14-46 Gated Mode, Continuous Scan Timing................................................................................. 14-65
14-47 Equivalent Analog Input Circuitry ....................................................................................... 14-66
14-48 Errors Resulting from Clipping ............................................................................................ 14-67
14-49 Star-Ground at the Point of Power Supply Origin ................................................................ 14-69
14-50 Electrical Model of an A/D Input Signal .............................................................................. 14-71
14-51 External Multiplexing of Analog Signal Sources ................................................................. 14-72
14-52 Input Signal Subjected to Negative Stress ............................................................................ 14-74
14-53 Input Signal Subjected to Positive Stress ............................................................................. 14-75
15-1
QSMCM Block Diagram ........................................................................................................ 15-2
15-2
QSMCM Interrupt Levels ....................................................................................................... 15-7
15-3
Interrupt Hardware Block Diagram ........................................................................................ 15-8
15-4
QSMCM Configuration Register (QSMCMMCR) ................................................................ 15-8
15-5
QSM2 Dual SCI Interrupt Level Register (QDSCI_IL) ......................................................... 15-9
15-6
QSPI_IL — QSPI Interrupt Level Register .......................................................................... 15-10
15-7
PORTQS — Port QS Data Register ..................................................................................... 15-12
15-8
PORTQS Pin Assignment Register (PQSPAR).................................................................... 15-13
15-9
PORTQS Data Direction Register (DDRQS) ....................................................................... 15-14
15-10 QSPI Block Diagram ............................................................................................................ 15-15
15-11 QSPI Control Register 0 (SPCR0)........................................................................................ 15-17
15-12 SPCR1 — QSPI Control Register ........................................................................................ 15-19
15-13 SPCR2 — QSPI Control Register 2 ..................................................................................... 15-20
15-14 SPCR3 — QSPI Control Register 3 ..................................................................................... 15-21
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15-15 QSPI Status Register (SPSR)................................................................................................ 15-21
15-16 QSPI RAM............................................................................................................................ 15-23
15-17 CR[0:F] — Command RAM 0x30 51C0, 0x30 51DF.......................................................... 15-24
15-18 Flowchart of QSPI Initialization Operation.......................................................................... 15-28
15-19 Flowchart of QSPI Master Operation (Part 1) ...................................................................... 15-29
15-20 Flowchart of QSPI Master Operation (Part 2) ...................................................................... 15-30
15-21 Flowchart of QSPI Master Operation (Part 3) ...................................................................... 15-31
15-22 Flowchart of QSPI Slave Operation (Part 1) ........................................................................ 15-32
15-23 Flowchart of QSPI Slave Operation (Part 2) ........................................................................ 15-33
15-24 SCI Transmitter Block Diagram ........................................................................................... 15-43
15-25 SCI Receiver Block Diagram ............................................................................................... 15-44
15-26 SCCxR0 — SCI Control Register 0 ..................................................................................... 15-46
15-27 SCI Control Register 1 (SCCxR1)........................................................................................ 15-47
15-28 SCIx Status Register (SCxSR).............................................................................................. 15-49
15-29 SCI Data Register (SCxDR) ................................................................................................. 15-51
15-30 Start Search Example............................................................................................................ 15-57
15-31 QSCI1 Control Register (QSCI1CR).................................................................................... 15-60
15-32 QSCI1 Status Register (QSCI1SR)....................................................................................... 15-61
15-33 Queue Transmitter Block Enhancements ............................................................................. 15-63
15-34 Queue Transmit Flow ........................................................................................................... 15-66
15-35 Queue Transmit Software Flow ............................................................................................ 15-66
15-36 Queue Transmit Example for 17 Data Bytes ........................................................................ 15-67
15-37 Queue Transmit Example for 25 Data Frames ..................................................................... 15-69
15-38 Queue Receiver Block Enhancements .................................................................................. 15-70
15-39 Queue Receive Flow ............................................................................................................. 15-73
15-40 Queue Receive Software Flow ............................................................................................. 15-74
15-41 Queue Receive Example for 17 Data Bytes.......................................................................... 15-75
16-1
TouCAN Block Diagram ........................................................................................................ 16-1
16-2
Typical CAN Network............................................................................................................ 16-3
16-3
Extended ID Message Buffer Structure .................................................................................. 16-4
16-4
Standard ID Message Buffer Structure ................................................................................... 16-4
16-5
Relationship between System Clock and CAN Bit Segments ................................................ 16-9
16-6
CAN Controller State Diagram............................................................................................. 16-12
16-7
Interrupt Levels on IRQ with ILBS ...................................................................................... 16-21
16-8
TouCAN Message Buffer Memory Map .............................................................................. 16-24
16-9
TouCAN Module Configuration Register (CANMCR) ....................................................... 16-25
16-10 TouCAN Interrupt Configuration Register (CANICR) ........................................................ 16-27
16-11 Control Register 0 (CANCTRL0)......................................................................................... 16-27
16-12 Control Register 1 (CANCTRL1)......................................................................................... 16-28
16-13 Prescaler Divide Register...................................................................................................... 16-29
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16-14 Control Register 2 (CANCTRL2)......................................................................................... 16-30
16-15 Free Running Timer Register (TIMER) ............................................................................... 16-31
16-16 Receive Global Mask Register: High (RXGMSKHI), Low (RXGMSKLO) ....................... 16-31
16-17 Receive Buffer 14 Mask Registers: High (RX14MSKHI), Low (RX14MSKLO)............... 16-32
16-18 Receive Buffer 15 Mask Registers: High (RX15MSKHI), Low (RX15MSKLO)............... 16-33
16-19 Error and Status Register (ESTAT) ...................................................................................... 16-33
16-20 Interrupt Mask Register (IMASK)........................................................................................ 16-35
16-21 Interrupt Flag Register (IFLAG)........................................................................................... 16-36
16-22 Receive Error Counter (RXECTR), Transmit Error Counter (TXECTR)............................ 16-36
17-1
MPC561/MPC563 MIOS14 Block Diagram .......................................................................... 17-2
17-2
MIOS14 Memory Map ......................................................................................................... 17-13
17-3
MBISM Registers ................................................................................................................. 17-13
17-4
Test and Signal Control Register (MIOS14TPCR) .............................................................. 17-14
17-5
Vector Register (MIOS14VECT) ......................................................................................... 17-14
17-6
MIOS14 Module/Version Number Register (MIOS14VNR)............................................... 17-14
17-7
Module Configuration Register (MIOS14MCR).................................................................. 17-15
17-8
MCPSM Block Diagram....................................................................................................... 17-16
17-9
MCPSM Status/Control Register (MCPSMSCR) ................................................................ 17-18
17-10 MMCSM Block Diagram ..................................................................................................... 17-20
17-11 MMCSM Modulus Up-Counter............................................................................................ 17-20
17-12 MMCSM Up-Counter Register (MMCSMCNT) ................................................................. 17-23
17-13 MMCSM Modulus Latch Register (MMCSMML) .............................................................. 17-24
17-14 MMCSM Status/Control Register (MMCSMSCR).............................................................. 17-24
17-15 MDASM Block Diagram...................................................................................................... 17-27
17-16 Input Pulse Width Measurement Example ........................................................................... 17-31
17-17 Input Period Measurement Example..................................................................................... 17-32
17-18 MDASM Input Capture Example ......................................................................................... 17-33
17-19 Single Shot Output Pulse Example ....................................................................................... 17-35
17-20 Single Shot Output Transition Example ............................................................................... 17-36
17-21 MDASM Output Pulse Width Modulation Example............................................................ 17-37
17-22 MDASM Data A Register (MDASMAR) ............................................................................ 17-41
17-23 MDASM DataB Register (MDASMBR).............................................................................. 17-42
17-24 MDASM Status/Control Register (MDASMSCR)............................................................... 17-44
17-25 MPWMSM Block Diagram .................................................................................................. 17-47
17-26 MPWMSM Period Register (MPWMPERR) ....................................................................... 17-57
17-27 MPWMSM Pulse Width Register (MPWMPULR).............................................................. 17-58
17-28 MPWMSM Counter Register (MPWMCNTR) .................................................................... 17-58
17-29 MPWMSM Status/Control Register (MPWMSCR)............................................................. 17-58
17-30 MPIOSM 1-Bit Block Diagram ............................................................................................ 17-60
17-31 MPIOSM — Register Organization ..................................................................................... 17-62
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17-32 MPIOSM Data Register (MPIOSMDR)............................................................................... 17-62
17-33 MPIOSM Data Direction Register (MPIOSMDDR)............................................................ 17-63
17-34 MIOS14 Interrupt Structure.................................................................................................. 17-64
17-35 Interrupt Status Register (MIOS14SR0)............................................................................... 17-66
17-36 Interrupt Enable Register (MIOS14ER0) ............................................................................. 17-66
17-37 Interrupt Request Pending Register (MIOS14RPR0) ........................................................... 17-67
17-38 Interrupt Status Register (MIOS14SR1)............................................................................... 17-67
17-39 Interrupt Enable Register (MIOS14ER1) ............................................................................. 17-68
17-40 Interrupt Request Pending Register (MIOS14RPR1) ........................................................... 17-68
17-41 MIOS14 Interrupt Level Register 0 (MIOS14LVL0)........................................................... 17-69
17-42 MIOS14 Interrupt Level Register 1 (MIOS14LVL1)........................................................... 17-70
17-43 MIOS14 Example: Double Capture Pulse Width Measurement .......................................... 17-71
17-44 MIOS14 Example: Double Capture Period Measurement ................................................... 17-72
17-45 MIOS14 Example: Double Edge Output Compare .............................................................. 17-73
17-46 MIOS14 Example: Pulse Width Modulation Output............................................................ 17-74
18-1
N-Signal I/O Compared with PPM I/O................................................................................... 18-2
18-2
Block Diagram of PPM Module ............................................................................................. 18-4
18-3
Internal Multiplexer Mechanism for Transmit Data............................................................... 18-5
18-4
Internal Multiplexer Mechanism for Received Data .............................................................. 18-5
18-5
PPM Clocks and Serial Data Signals ...................................................................................... 18-6
18-6
One Transmit and Receive Cycle in SPI Mode ...................................................................... 18-7
18-7
Examples Of Several TCLK Frequencies and Sample Rates ................................................. 18-8
18-8
Module Configuration Register (PPMMCR)........................................................................ 18-10
18-9
PPM Control Register (PPMPCR)........................................................................................ 18-12
18-10 Set ENRX While ENTX = 1................................................................................................. 18-14
18-11 Set ENTX while ENRX = 1.................................................................................................. 18-14
18-12 SPI Transfer Format with CP = 0 ......................................................................................... 18-15
18-13 SPI Transfer Format with CP = 1 ......................................................................................... 18-15
18-14 Transmit Configuration Register 1 (TX_CONFIG_1) ......................................................... 18-16
18-15 Transmit Configuration Register 2 (TX_CONFIG_2) ......................................................... 18-16
18-16 Receive Configuration Register 1 (RX_CONFIG_1)........................................................... 18-16
18-17 Receive Configuration Register 2 (RX_CONFIG_2)........................................................... 18-17
18-18 Receive Data Register (RX_DATA) .................................................................................... 18-18
18-19 Receive Shifter Register (RX_SHIFTER) ............................................................................ 18-18
18-20 Transmit Data Register (TX_DATA) ................................................................................... 18-18
18-21 General Purpose Data Out Register (GPDO) ....................................................................... 18-19
18-22 General Purpose Data In Register (GPDI)............................................................................ 18-19
18-23 Short Register (SHORT_REG)............................................................................................. 18-19
18-24 Example of TouCAN Internal Short with SH_TCAN = 0b110............................................ 18-21
18-25 Short Between TPU Channels .............................................................................................. 18-22
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18-26 Short Channels Register (SHORT_CH_REG) ..................................................................... 18-23
18-27 Scale Transmit Clock Register (SCALE_TCLK_REG)....................................................... 18-24
19-1
TPU3 Block Diagram ............................................................................................................. 19-1
19-2
TPU3 Interrupt Levels ............................................................................................................ 19-5
19-3
TCR1 Prescaler Control.......................................................................................................... 19-7
19-4
TCR2 Prescaler Control.......................................................................................................... 19-8
19-5
TPUMCR — TPU Module Configuration Register ............................................................. 19-11
19-6
DSCR — Development Support Control Register ............................................................... 19-12
19-7
DSSR — Development Support Status Register .................................................................. 19-14
19-8
TICR — TPU3 Interrupt Configuration Register ................................................................. 19-14
19-9
CIER — Channel Interrupt Enable Register......................................................................... 19-15
19-10 CFSR0 — Channel Function Select Register 0 .................................................................... 19-16
19-11 CFSR1 — Channel Function Select Register 1 .................................................................... 19-16
19-12 CFSR2 — Channel Function Select Register 2 .................................................................... 19-16
19-13 CFSR3 — Channel Function Select Register 3 .................................................................... 19-16
19-14 HSQR0 — Host Sequence Register 0................................................................................... 19-17
19-15 HSQR1 — Host Sequence Register 1................................................................................... 19-17
19-16 HSRR0 — Host Service Request Register 0 ........................................................................ 19-17
19-17 HSRR1 — Host Service Request Register 1 ........................................................................ 19-17
19-18 CPR0 — Channel Priority Register 0 ................................................................................... 19-18
19-19 CPR1 — Channel Priority Register 1 ................................................................................... 19-18
19-20 CISR — Channel Interrupt Status Register .......................................................................... 19-19
19-21 TPUMCR2 — TPU Module Configuration Register 2 ........................................................ 19-19
19-22 TPUMCR3 — TPU Module Configuration Register 3 ........................................................ 19-21
19-23 SIUTST — SIU Test Register .............................................................................................. 19-22
20-1
DPTRAM Configuration ........................................................................................................ 20-2
20-2
DPTRAM Memory Map......................................................................................................... 20-3
20-3
DPT Module Configuration Register (DPTMCR).................................................................. 20-3
20-4
RAM Array Base Address Register (RAMBAR)................................................................... 20-5
20-5
Multiple Input Signature Register High (MISRH) ................................................................. 20-5
20-6
Multiple Input Signature Register Low (MISRL) .................................................................. 20-6
20-7
MISC Counter (MISCNT) ...................................................................................................... 20-6
21-1
Block Diagram for a 512 Kbyte UC3F Module Configuration .............................................. 21-2
21-2
UC3F EEPROM Configuration Register (UC3FMCR) ......................................................... 21-5
21-3
UC3FMCRE— UC3F EEPROM Extended Configuration Register ..................................... 21-9
21-4
UC3F EEPROM High Voltage Control Register (UC3FCTL) ............................................ 21-11
21-5
PEGOOD Valid Time ........................................................................................................... 21-14
21-6
Shadow Information ............................................................................................................. 21-16
21-7
Hard Reset Configuration Word (UC3FCFIG) .................................................................... 21-16
21-8
512-Kbyte Array Configuration............................................................................................ 21-19
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21-9
Program State Diagram......................................................................................................... 21-23
21-10 Erase State Diagram.............................................................................................................. 21-27
21-11 Censorship States and Transitions ........................................................................................ 21-33
22-1
System Block Diagram ........................................................................................................... 22-2
22-2
MPC561/MPC563 Memory Map with CALRAM Address Ranges ...................................... 22-3
22-3
Standby Power Supply Configuration for CALRAM Array .................................................. 22-4
22-4
CALRAM Array ..................................................................................................................... 22-7
22-5
CALRAM Module Overlay Map of Flash (CLPS = 0) .......................................................... 22-8
22-6
CALRAM Address Map (CLPS = 0) ..................................................................................... 22-9
22-7
CALRAM Module Overlay Map of Flash (CLPS = 1) ........................................................ 22-10
22-8
CALRAM Address Map (CLPS = 1) ................................................................................... 22-11
22-9
CALRAM Module Configuration Register (CRAMMCR).................................................. 22-13
22-10 CALRAM Region Base Address Register (CRAM_RBAx) ................................................ 22-16
22-11 CALRAM Overlay Configuration Register (CRAM_OVLCR)........................................... 22-17
22-12 CALRAM Ownership Trace Register (CRAM_OTR) ......................................................... 22-18
23-1
Watchpoint and Breakpoint Support in the CPU.................................................................... 23-9
23-2
Partially Supported Watchpoint/Breakpoint Example.......................................................... 23-13
23-3
Instruction Support General Structure .................................................................................. 23-15
23-4
Load/Store Support General Structure.................................................................................. 23-18
23-5
Functional Diagram of MPC561/MPC563 Debug Mode Support ....................................... 23-21
23-6
Debug Mode Logic ............................................................................................................... 23-23
23-7
BDM Mode Selection ........................................................................................................... 23-24
23-8
Debug Mode Reset Configuration ........................................................................................ 23-25
23-9
Asynchronous Clock Serial Communications ...................................................................... 23-32
23-10 Synchronous Self Clock Serial Communication .................................................................. 23-32
23-11 Enabling Clock Mode Following Reset................................................................................ 23-33
23-12 Download Procedure Code Example .................................................................................... 23-37
23-13 Slow Download Procedure Loop .......................................................................................... 23-38
23-14 Fast Download Procedure Loop ........................................................................................... 23-38
23-15 Comparator A–D Value Register (CMPA–CMPD).............................................................. 23-41
23-16 Exception Cause Register (ECR).......................................................................................... 23-42
23-17 Debug Enable Register (DER).............................................................................................. 23-43
23-18
Breakpoint Counter A Value and Control Register (COUNTA)......................................... 23-45
23-19 Breakpoint Counter B Value and Control Register (COUNTB) .......................................... 23-46
23-20 Comparator E–F Value Registers (CMPE–CMPF) .............................................................. 23-46
23-21 Comparator G–H Value Registers (CMPG–CMPH)............................................................ 23-47
23-22 L-Bus Support Control Register 1 (LCTRL) ........................................................................ 23-47
23-23 L-Bus Support Control Register 2 (LCTRL2) ...................................................................... 23-48
23-24 I-Bus Support Control Register (ICTRL) ............................................................................. 23-51
23-25 Breakpoint Address Register (BAR) .................................................................................... 23-53
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23-26 Development Port Data Register (DPDR) ............................................................................ 23-53
24-1
READI Functional Block Diagram......................................................................................... 24-3
24-2
READI Ownership Trace Register (OTR).............................................................................. 24-9
24-3
READI Device ID Register .................................................................................................. 24-10
24-4
READI Development Control (DC) Register ....................................................................... 24-10
24-5
READI Mode Control (MC) Register .................................................................................. 24-12
24-6
READI User Base Address Register .................................................................................... 24-13
24-7
READI Read/Write Access Register .................................................................................... 24-14
24-8
READI Upload/Download Information Register ................................................................. 24-16
24-9
RWD Field Configuration .................................................................................................... 24-17
24-10 READI Data Trace Attributes 1 Register (DTA1)
READI Data Trace Attributes 2 Register (DTA2) ............................................................... 24-17
24-11 Functional Diagram of Signal Interface................................................................................ 24-22
24-12 Auxiliary Signal Packet Structure for Program Trace Indirect
Branch Message .................................................................................................................... 24-23
24-13 MSEI/MSEO Transfers......................................................................................................... 24-24
24-14 Transmission Sequence of Messages.................................................................................... 24-32
24-15 READI Module Enabled....................................................................................................... 24-34
24-16 Enabling Program Trace Out of System Reset ..................................................................... 24-36
24-17 READI Mode Selection ........................................................................................................ 24-36
24-18 READI Module Disabled...................................................................................................... 24-37
24-19 Direct Branch Message Format ............................................................................................ 24-38
24-20 Indirect Branch Message Format .......................................................................................... 24-39
24-21 Indirect Branch Message Format with Compressed Code.................................................... 24-39
24-22 Bit Pointer Format with Compressed Code .......................................................................... 24-39
24-23 Program Trace Correction Message Format ......................................................................... 24-42
24-24 Direct Branch Synchronization Message Format (PTSM = 0)............................................. 24-44
24-25 Direct Branch Synchronization Message Format (PTSM = 1)............................................. 24-44
24-26 Indirect Branch Synchronization Message Format (PTSM = 0) .......................................... 24-44
24-27 Indirect Branch Synchronization Message Format (PTSM = 1) .......................................... 24-44
24-28 Direct Branch Synchronization Message Format with Compressed
Code (PTSM = 0).................................................................................................................. 24-45
24-29 Direct Branch Synchronization Message Format with Compressed
Code (PTSM = 1).................................................................................................................. 24-45
24-30 Indirect Branch Synchronization Message Format with Compressed
Code (PTSM - 0)................................................................................................................... 24-45
24-31 Indirect Branch Synchronization Message Format with Compressed
Code (PTSM = 1).................................................................................................................. 24-45
24-32 Program Trace Full Message Format.................................................................................... 24-46
24-33 Relative Address Generation and Re-Creation ..................................................................... 24-47
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24-34 Error Message (Queue Overflow) Format ............................................................................ 24-47
24-35 Direct Branch Message ......................................................................................................... 24-49
24-36 Indirect Branch Message ...................................................................................................... 24-49
24-37 Indirect Branch Message with Compressed Code ................................................................ 24-49
24-38 Program Trace Correction Message ..................................................................................... 24-50
24-39 Error Message (Program/Data/Ownership Trace Overrun).................................................. 24-50
24-40 Direct Branch Synchronization Message.............................................................................. 24-50
24-41 Indirect Branch Synchronization Message ........................................................................... 24-51
24-42 Direct Branch Synchronization Message
with Compressed Code ......................................................................................................... 24-51
24-43 Indirect Branch Synchronization Message with Compressed Code ..................................... 24-51
24-44 Data Write Message Format ................................................................................................. 24-52
24-45 Data Read Message Format .................................................................................................. 24-53
24-46 Data Write Synchronization Message Format ...................................................................... 24-54
24-47 Data Read Synchronization Message Format ....................................................................... 24-54
24-48 Error Message (Queue Overflow) Format ............................................................................ 24-54
24-49 Data Trace Flow Diagram for Non-Pipelined Access .......................................................... 24-55
24-50 Date Write Message.............................................................................................................. 24-57
24-51 Data Read Message............................................................................................................... 24-58
24-52 Data Write Synchronization Message................................................................................... 24-58
24-53 Data Read Synchronization Message ................................................................................... 24-58
24-54 Error Message (Program/Data/Ownership Trace Overrun).................................................. 24-59
24-55 Target Ready Message.......................................................................................................... 24-59
24-56 Read Register Message ......................................................................................................... 24-59
24-57 Write Register Message ........................................................................................................ 24-60
24-58 Read/Write Response Message............................................................................................. 24-60
24-59 Read/Write Access Flow Diagram ....................................................................................... 24-61
24-60 Error Message (Read/Write Access Error) Format............................................................... 24-67
24-61 Error Message (Invalid Message) Format ............................................................................ 24-67
24-62 Error Message (Invalid Access Opcode) Format.................................................................. 24-67
24-63 Block Write Access .............................................................................................................. 24-69
24-64 Block Read Access ............................................................................................................... 24-70
24-65 Device Ready for Upload/Download Request Message....................................................... 24-70
24-66 Upload Request Message...................................................................................................... 24-71
24-67 Download Request Message ................................................................................................. 24-71
24-68 Upload/Download Information Message.............................................................................. 24-72
24-69 Error Message (Invalid Access Opcode) .............................................................................. 24-72
24-70 Watchpoint Message Format ................................................................................................ 24-73
24-71 Error Message (Watchpoint Overrun) Format...................................................................... 24-73
24-72 Watchpoint Message............................................................................................................. 24-74
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lv
Figures
Figure
Page
Title
Number
Number
24-73 Error Message (Watchpoint Overrun) .................................................................................. 24-74
24-74 Ownership Trace Message Format ....................................................................................... 24-75
24-75 Error Message Format .......................................................................................................... 24-75
24-76 Ownership Trace Message.................................................................................................... 24-76
24-77 Error Message (Program/Data/Ownership Trace Overrun).................................................. 24-76
24-78 RCPU Development Access Multiplexing between READI and BDM Signals .................. 24-77
24-79 DSDI Message Format.......................................................................................................... 24-78
24-80 DSDO Message Format ........................................................................................................ 24-78
24-81 BDM Status Message Format ............................................................................................... 24-79
24-82 Error Message (Invalid Message) Format ............................................................................ 24-79
24-83 RCPU Development Access Flow Diagram ......................................................................... 24-81
24-84 RCPU Development Access Timing Diagram — Debug Mode Entry Out-of-Reset........... 24-83
24-85 Transmission Sequence of DSDx Data Messages ................................................................ 24-83
24-86 Error Message (Invalid Message) ......................................................................................... 24-85
24-87 DSDI Data Message (Assert Non-Maskable Breakpoint) .................................................... 24-85
24-88 DSDI Data Message (CPU Instruction — rfi) ...................................................................... 24-85
24-89 DSDO Data Message (CPU Data Out) ................................................................................. 24-86
25-1
Pin Requirement on JTAG...................................................................................................... 25-1
25-2
Test Logic Block Diagram...................................................................................................... 25-3
25-3
JTAG Mode Selection ............................................................................................................ 25-3
25-4
TAP Controller State Machine ............................................................................................... 25-4
25-5
Bypass Register..................................................................................................................... 25-31
A-1
Instruction Compression Alternatives ..................................................................................... A-3
A-2
Addressing Instructions with Compressed Address ................................................................ A-4
A-3
Compressed Target Address Generation by Direct Branches.................................................. A-5
A-4
Branch Right Segment Compression #1 .................................................................................. A-7
A-5
Branch Right Segment Compression #2 .................................................................................. A-8
A-6
Global Bypass Instruction Layout ........................................................................................... A-8
A-7
CLASS_1 Instruction Layout .................................................................................................. A-9
A-8
CLASS_2 Instruction Layout .................................................................................................. A-9
A-9
CLASS_3 Instruction Layout ................................................................................................ A-10
A-10
CLASS_4 Instruction Layout ................................................................................................ A-11
A-11
Code Compression Process.................................................................................................... A-12
A-12
Code Decompression Process ................................................................................................ A-13
A-13
I-Bus Support Control Register (ICTRL) .............................................................................. A-16
A-14
Decompressor Class Configuration Registers1 (DCCRx) ..................................................... A-19
C-1
MPC561/MPC563 Power Distribution Diagram — 2.6 V .......................................................C-3
C-2
Power Distribution Diagram — 5 V and Analog .....................................................................C-3
C-3
Crystal Oscillator Circuit ..........................................................................................................C-4
C-4
RC Filter Example ....................................................................................................................C-5
MPC561/MPC563 Reference Manual, Rev. 1.2
lvi
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
C-5
Bypass Capacitors Example (Alternative) ................................................................................C-5
C-6
RC Filter Example ....................................................................................................................C-6
C-7
LC Filter Example (Alternative)...............................................................................................C-6
C-8
PLL Off-Chip Capacitor Example ............................................................................................C-7
C-9
IRAMSTBY Regulator Circuit .................................................................................................C-8
D-1
TPU3 Memory Map................................................................................................................. D-1
D-2
PTA Parameters ....................................................................................................................... D-4
D-3
QOM Parameters ..................................................................................................................... D-6
D-4
TSM Parameters — Master Mode ........................................................................................... D-8
D-5
TSM Parameters — Slave Mode ............................................................................................. D-9
D-6
FQM Parameters .................................................................................................................... D-11
D-7
UART Transmitter Parameters .............................................................................................. D-13
D-8
UART Receiver Parameters................................................................................................... D-14
D-9
NITC Parameters ................................................................................................................... D-16
D-10
COMM Parameters ................................................................................................................ D-18
D-10
COMM Parameters (continued)............................................................................................. D-20
D-11
HALLD Parameters ............................................................................................................... D-21
D-12
MCPWM Parameters — Master Mode ................................................................................. D-23
D-13
MCPWM Parameters — Slave Edge-Aligned Mode ............................................................ D-24
D-14
MCPWM Parameters — Slave Ch A Non-Inverted Center-Aligned Mode.......................... D-26
D-15
MCPWM Parameters — Slave Ch B Non-Inverted Center-Aligned Mode .......................... D-27
D-16
MCPWM Parameters — Slave Ch A Inverted Center-Aligned Mode .................................. D-28
D-17
MCPWM Parameters — Slave Ch B Inverted Center-Aligned Mode .................................. D-29
D-18
MULTI Parameters — FRINC .............................................................................................. D-31
D-19
MULTI Parameters — FREDEC........................................................................................... D-32
D-20
MULTI Parameters — SPEED.............................................................................................. D-33
D-21
MULTI Parameters — PWM_IN .......................................................................................... D-34
D-22
FQD Parameters — Primary Channel ................................................................................... D-36
D-23
FQD Parameters — Secondary Channel ............................................................................... D-37
D-24
PPWA Parameters.................................................................................................................. D-39
D-25
ID Parameters ........................................................................................................................ D-41
D-26
OC Parameters ....................................................................................................................... D-43
D-27
PWM Parameters ................................................................................................................... D-45
D-28
DIO Parameters...................................................................................................................... D-47
D-29
SPWM Parameters ................................................................................................................. D-49
D-30
RWTPIN Parameters ............................................................................................................. D-52
D-31
Two Possible SIOP Configurations ....................................................................................... D-53
D-32
SIOP Parameters .................................................................................................................... D-55
D-33
SIOP Function Data Transition Example .............................................................................. D-59
F-1
Option A Power-Up Sequence Without Keep-Alive Supply.................................................. F-14
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lvii
Figures
Figure
Page
Title
Number
Number
F-2
Option A Power-Up Sequence With Keep-Alive Supply....................................................... F-14
F-3
Option A Power-Down Sequence Without Keep-Alive Supply............................................. F-15
F-4
Option A Power-Down Sequence With Keep-Alive Supply.................................................. F-15
F-5
Option B Power-Up Sequence Without Keep-Alive Supply.................................................. F-16
F-6
Option B Power-Up Sequence With Keep-Alive Supply ....................................................... F-16
F-7
Option B Power-Down Sequence Without Keep-Alive Supply ............................................. F-17
F-8
Option B Power-Down Sequence with Keep-Alive Supply ................................................... F-17
F-9
Generic Timing Examples ...................................................................................................... F-19
F-10
CLKOUT Pin Timing ............................................................................................................. F-27
F-11
Synchronous Output Signals Timing ...................................................................................... F-28
F-12
Predischarge Timing ............................................................................................................... F-29
F-13
Synchronous Active Pull-Up And Open Drain
Outputs Signals Timing .......................................................................................................... F-30
F-14
Synchronous Input Signals Timing......................................................................................... F-31
F-15
Input Data Timing In Normal Case ........................................................................................ F-32
F-16
External Bus Read Timing (GPCM Controlled – ACS = ‘00’).............................................. F-33
F-17
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’).......................... F-34
F-18
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’).......................... F-35
F-19
External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’).... F-36
F-20
Address Show Cycle Bus Timing ........................................................................................... F-36
F-21
Address and Data Show Cycle Bus Timing............................................................................ F-37
F-22
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’) ....................... F-38
F-23
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’) ....................... F-39
F-24
External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’) ....................... F-40
F-25
External Master Read From Internal Registers Timing.......................................................... F-41
F-26
External Master Write To Internal Registers Timing ............................................................. F-42
F-27
Interrupt Detection Timing for External Edge Sensitive Lines .............................................. F-43
F-28
Debug Port Clock Input Timing ............................................................................................. F-44
F-29
Debug Port Timings................................................................................................................ F-44
F-30
Auxiliary Port Data Input Timing Diagram............................................................................ F-45
F-31
Auxiliary Port Data Output Timing Diagram ......................................................................... F-46
F-32
Enable Auxiliary From RSTI.................................................................................................. F-46
F-33
Disable Auxiliary From RSTI................................................................................................. F-46
F-34
Reset Timing – Configuration from Data Bus........................................................................ F-48
F-35
Reset Timing – Data Bus Weak Drive During Configuration................................................ F-49
F-36
Reset Timing – Debug Port Configuration ............................................................................. F-50
F-37
JTAG Test Clock Input Timing .............................................................................................. F-51
F-38
JTAG Test Access Port Timing Diagram ............................................................................... F-52
F-39
Boundary Scan (JTAG) Timing Diagram............................................................................... F-53
F-40
QSPI Timing – Master, CPHA = 0 ......................................................................................... F-58
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
F-41
QSPI Timing – Master, CPHA = 1 ......................................................................................... F-58
F-42
QSPI Timing – Slave, CPHA = 0 ........................................................................................... F-59
F-43
QSPI Timing – Slave, CPHA = 1 ........................................................................................... F-59
F-44
TPU3 Timing .......................................................................................................................... F-61
F-45
PPM_TCLK Timing ............................................................................................................... F-63
F-46
PPM Data Transfer Timing (SPI Mode)................................................................................. F-63
F-47
MCPSM Enable to VS_PCLK Pulse Timing Diagram .......................................................... F-64
F-48
MPWMSM Minimum Output Pulse Example Timing Diagram............................................ F-65
F-49
MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram .............................. F-66
F-50
MPWMSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ......................... F-66
F-51
MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram.............. F-66
F-52
MMCSM Minimum Input Pin (Either Load Or Clock) Timing Diagram .............................. F-67
F-53
MMCSM Clock Pin To Counter Bus Increment Timing Diagram ........................................ F-68
F-54
MMCSM Load Pin To Counter Bus Reload Timing Diagram............................................... F-68
F-55
MMCSM Counter Bus Reload To Interrupt Flag Setting Timing Diagram........................... F-68
F-56
MMCSM Prescaler Clock Select To Counter Bus Increment Timing Diagram .................... F-69
F-57
MDASM Minimum Input Pin Timing Diagram..................................................................... F-70
F-58
MDASM Input Pin To Counter Bus Capture Timing Diagram.............................................. F-70
F-59
MDASM Input Pin to MDASM Interrupt Flag Timing Diagram .......................................... F-70
F-60
MDASM Minimum Output Pulse Width Timing Diagram.................................................... F-71
F-61
Counter Bus to MDASM Output Pin Change Timing Diagram............................................. F-71
F-62
Counter Bus to MDASM Interrupt Flag Setting Timing Diagram ......................................... F-71
F-63
MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram ............................... F-72
F-64
MPC561/MPC563 Package Footprint (1 of 2) ....................................................................... F-84
F-65
MPC561/MPC563 Package Footprint (2 of 2) ....................................................................... F-85
F-66
MPC561/MPC563 Ball Map .................................................................................................. F-86
F-67
MPC561/MPC563 Ball Map (Black and White, page 1) ....................................................... F-87
F-68
MPC561/MPC563 Ball Map (Black and White, page 2) ....................................................... F-88
F-69
MPC561/MPC563 Ball Map (Black and White, page 3) ....................................................... F-89
F-70
MPC561/MPC563 Ball Map (Black and White, page 4) ....................................................... F-90
G-1
Option A Power-Up Sequence Without Keep-Alive Supply................................................. G-13
G-2
Option A Power-Up Sequence With Keep-Alive Supply...................................................... G-14
G-3
Option A Power-Down Sequence Without Keep-Alive Supply............................................ G-14
G-4
Option A Power-Down Sequence With Keep-Alive Supply................................................. G-15
G-5
Option B Power-Up Sequence Without Keep-Alive Supply................................................. G-16
G-6
Option B Power-Up Sequence With Keep-Alive Supply ...................................................... G-16
G-7
Option B Power-Down Sequence Without Keep-Alive Supply ............................................ G-17
G-8
Option B Power-Down Sequence with Keep-Alive Supply .................................................. G-17
G-9
Generic Timing Examples ..................................................................................................... G-19
G-10
CLKOUT Pin Timing ............................................................................................................ G-25
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lix
Figures
Figure
Page
Title
Number
Number
G-11
Synchronous Output Signals Timing ..................................................................................... G-26
G-12
Synchronous Active Pull-Up And Open Drain Outputs Signals Timing .............................. G-27
G-13
Synchronous Input Signals Timing........................................................................................ G-28
G-14
Input Data Timing In Normal Case ....................................................................................... G-29
G-15
External Bus Read Timing (GPCM Controlled – ACS = ‘00’)............................................. G-30
G-16
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’)......................... G-31
G-17
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’)......................... G-32
G-18
External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’)... G-33
G-19
Address Show Cycle Bus Timing .......................................................................................... G-34
G-20
Address and Data Show Cycle Bus Timing........................................................................... G-35
G-21
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’) ...................... G-36
G-22
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’) ...................... G-37
G-23
External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’) ...................... G-38
G-24
External Master Read From Internal Registers Timing......................................................... G-39
G-25
External Master Write To Internal Registers Timing ............................................................ G-40
G-26
Interrupt Detection Timing for External Edge Sensitive Lines ............................................. G-41
G-27
Debug Port Clock Input Timing ............................................................................................ G-42
G-28
Debug Port Timings............................................................................................................... G-42
G-29
Auxiliary Port Data Input Timing Diagram........................................................................... G-43
G-30
Auxiliary Port Data Output Timing Diagram ........................................................................ G-43
G-31
Enable Auxiliary From RSTI................................................................................................. G-44
G-32
Disable Auxiliary From RSTI................................................................................................ G-44
G-33
Reset Timing – Configuration from Data Bus....................................................................... G-45
G-34
Reset Timing – Data Bus Weak Drive During Configuration............................................... G-46
G-35
Reset Timing – Debug Port Configuration ............................................................................ G-47
G-36
JTAG Test Clock Input Timing ............................................................................................. G-48
G-37
JTAG Test Access Port Timing Diagram .............................................................................. G-48
G-38
Boundary Scan (JTAG) Timing Diagram.............................................................................. G-49
G-39
QSPI Timing – Master, CPHA = 0 ........................................................................................ G-54
G-40
QSPI Timing – Master, CPHA = 1 ........................................................................................ G-54
G-41
QSPI Timing – Slave, CPHA = 0 .......................................................................................... G-55
G-42
QSPI Timing – Slave, CPHA = 1 .......................................................................................... G-55
G-43
TPU3 Timing ......................................................................................................................... G-57
G-44
PPM_TCLK Timing .............................................................................................................. G-59
G-45
PPM Data Transfer Timing (SPI Mode)................................................................................ G-59
G-46
MCPSM Enable to VS_PCLK Pulse Timing Diagram ......................................................... G-60
G-47
MPWMSM Minimum Output Pulse Example Timing Diagram........................................... G-61
G-48
MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ............................. G-61
G-49
MPWMSM Enable To MPWMO Output Pin Rising Edge Timing Diagram ....................... G-62
G-50
MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram............. G-62
MPC561/MPC563 Reference Manual, Rev. 1.2
lx
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
G-51
MMCSM Minimum Input Pin (Either Load or Clock) Timing Diagram.............................. G-63
G-52
MMCSM Clock Pin to Counter Bus Increment Timing Diagram......................................... G-63
G-53
MMCSM Load Pin to Counter Bus Reload Timing Diagram ............................................... G-64
G-54
MMCSM Counter Bus Reload to Interrupt Flag Setting Timing Diagram ........................... G-64
G-55
MMCSM Prescaler Clock Select to Counter Bus Increment Timing Diagram..................... G-64
G-56
MDASM Minimum Input Pin Timing Diagram.................................................................... G-65
G-57
MDASM Input Pin To Counter Bus Capture Timing Diagram............................................. G-66
G-58
MDASM Input Pin to MDASM Interrupt Flag Timing Diagram ......................................... G-66
G-59
MDASM Minimum Output Pulse Width Timing Diagram................................................... G-66
G-60
Counter Bus to MDASM Output Pin Change Timing Diagram............................................ G-66
G-61
Counter Bus to MDASM Interrupt Flag Setting Timing Diagram ........................................ G-67
G-62
MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram .............................. G-67
G-63
MPC561/MPC563 Package Footprint (1 of 2) ...................................................................... G-79
G-64
MPC561/MPC563 Package Footprint (2 of 2) ...................................................................... G-80
G-65
MPC561/MPC563 Ball Map ................................................................................................. G-81
G-66
MPC561/MPC563 Ball Map (Black and White, page 1) ...................................................... G-82
G-67
MPC561/MPC563 Ball Map (Black and White, page 2) ...................................................... G-83
G-68
MPC561/MPC563 Ball Map (Black and White, page 3) ...................................................... G-84
G-69
MPC561/MPC563 Ball Map (Black and White, page 4) ...................................................... G-85
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxi
Figures
Figure
Number
Title
Page
Number
MPC561/MPC563 Reference Manual, Rev. 1.2
lxii
Freescale Semiconductor
Tables
Table
Number
i
ii
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
Title
Page
Number
Notational Conventions ..................................................................................................... 1-lxxxii
Acronyms and Abbreviated Terms .................................................................................... 1-lxxxii
MPC56x Family Features ......................................................................................................... 1-1
Differences Between MPC555 and MPC561/MPC563............................................................ 1-9
MPC561/MPC563 Signal Descriptions .................................................................................... 2-3
MPC561/MPC563 Signal Sharing.......................................................................................... 2-20
Reduced and Full Port Mode Pads.......................................................................................... 2-21
Full Port Only Mode Pads ...................................................................................................... 2-21
PDMCR Field Descriptions .................................................................................................... 2-22
PDMCR2 Field Description.................................................................................................... 2-24
TCNC Pad Functionalities ...................................................................................................... 2-25
PPMPAD Pad Functionalities................................................................................................. 2-25
Enhanced PCS Functionality ................................................................................................. 2-25
Enhanced PCS 4 & 5 Pad Function ........................................................................................ 2-26
Enhanced PCS 6 & 7 Pad Function ........................................................................................ 2-28
MPC561/MPC563 Development Support Shared Signals ..................................................... 2-28
MPC561/MPC563 Mode Selection Options.......................................................................... 2-29
MPC561/MPC563 Signal Reset State .................................................................................... 2-34
RCPU Execution Units ............................................................................................................. 3-4
Supervisor-Level SPRs ............................................................................................................. 3-9
Development Support SPRs.................................................................................................... 3-11
FPSCR Bit Categories ............................................................................................................ 3-13
FPSCR Bit Descriptions ......................................................................................................... 3-14
Floating-Point Result Flags in FPSCR ................................................................................... 3-16
Bit Settings for CR0 Field of CR............................................................................................ 3-17
Bit Settings for CR1 Field of CR............................................................................................ 3-17
CRn Field Bit Settings for Compare Instructions ................................................................... 3-18
Integer Exception Register Bit Descriptions .......................................................................... 3-18
Machine State Register Bit Descriptions ................................................................................ 3-20
Floating-Point Exception Mode Bits ...................................................................................... 3-22
Uses of SPRG0–SPRG3 ......................................................................................................... 3-24
Processor Version Register Bit Descriptions.......................................................................... 3-25
EIE, EID, AND NRI Registers ............................................................................................... 3-25
FPECR Bit Descriptions ......................................................................................................... 3-26
Instruction Set Summary ........................................................................................................ 3-28
RCPU Exception Classes........................................................................................................ 3-35
Exception Vector Offset Table .............................................................................................. 3-36
Instruction Latency and Blockage .......................................................................................... 3-39
Floating-Point Exception Mode Encoding ............................................................................. 3-44
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxiii
Tables
Table
Number
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37
3-38
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
Title
Page
Number
Settings Caused by Reset ....................................................................................................... 3-45
Register Settings following an NMI ....................................................................................... 3-45
Machine Check Exception Processor Actions ........................................................................ 3-47
Register Settings following a Machine Check Exception ...................................................... 3-47
Register Settings following External Interrupt ...................................................................... 3-49
Register Settings for Alignment Exception ........................................................................... 3-50
Register Settings following Program Exception.................................................................... 3-52
Register Settings following a Floating-Point Unavailable Exception ................................... 3-52
Register Settings Following a Decrementer Exception ......................................................... 3-53
Register Settings following a System Call Exception ........................................................... 3-54
Register Settings following a Trace Exception....................................................................... 3-55
Register Settings following Floating-Point Assist Exceptions ............................................... 3-55
Register Settings following a Software Emulation Exception................................................ 3-56
Register Settings following an Instruction Protection Exception ........................................... 3-57
Register Settings Following a Data Protection Error Exception ............................................ 3-59
Register Settings Following a Debug Exception .................................................................... 3-60
Register Settings for Data Breakpoint Match ......................................................................... 3-60
Exception Addresses Mapping ................................................................................................. 4-9
Exception Relocation Page Offset .......................................................................................... 4-10
BBC SPRs............................................................................................................................... 4-17
BBCMCR Field Descriptions ................................................................................................ 4-19
MI_RBA[0:3] Registers Bit Descriptions.............................................................................. 4-21
MI_RA[0:3] Registers Bit Descriptions ................................................................................ 4-22
Region Size Programming Possible Values............................................................................ 4-23
MI_GRA Field Descriptions.................................................................................................. 4-24
EIBADR External Interrupt Relocation Table Base Address Register Bit Descriptions ...... 4-25
USIU Address Map................................................................................................................... 5-3
USIU Special-Purpose Registers .............................................................................................. 5-7
Hex Address Format for SPR Cycles ....................................................................................... 5-7
USIU Pin Multiplexing Control................................................................................................ 6-4
SGPIO Configuration ............................................................................................................... 6-7
Priority of Interrupt Sources—Regular Operation.................................................................. 6-10
Priority of Interrupt Sources—Enhanced Operation .............................................................. 6-12
Interrupt Latency Estimation for Three Typical Cases........................................................... 6-16
Decrementer Time-Out Periods .............................................................................................. 6-18
SIUMCR Bit Descriptions ..................................................................................................... 6-25
Debug Pins Configuration ...................................................................................................... 6-27
General Pins Configuration .................................................................................................... 6-27
Single-Chip Select Field Pin Configuration ........................................................................... 6-27
MPC561/MPC563 Reference Manual, Rev. 1.2
lxiv
Freescale Semiconductor
Tables
Table
Number
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
7-1
7-2
7-3
7-4
7-5
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
9-1
9-2
9-3
9-4
9-5
Title
Page
Number
Multi-Level Reservation Control Pin Configuration .............................................................. 6-28
IMMR Bit Descriptions ......................................................................................................... 6-29
EMCR Bit Descriptions ......................................................................................................... 6-30
SIU Interrupt Controller – Bit Acronym Definitions.............................................................. 6-31
SYPCR Bit Descriptions........................................................................................................ 6-38
SWSR Bit Descriptions ......................................................................................................... 6-39
TESR Bit Descriptions........................................................................................................... 6-39
TBSCR Bit Descriptions........................................................................................................ 6-42
RTCSC Bit Descriptions........................................................................................................ 6-43
PISCR Bit Descriptions ......................................................................................................... 6-44
PITC Bit Descriptions............................................................................................................ 6-45
PIT Bit Descriptions .............................................................................................................. 6-45
SGPIODT1 Bit Descriptions ................................................................................................. 6-46
SGPIODT2 Bit Descriptions ................................................................................................. 6-47
SGPIOCR Bit Descriptions ................................................................................................... 6-48
Data Direction Control............................................................................................................ 6-48
Reset Action Taken for Each Reset Cause ............................................................................... 7-4
Reset Configuration Word and Data Corruption/Coherency.................................................... 7-4
Reset Status Register Bit Descriptions ..................................................................................... 7-5
Reset Configuration Options .................................................................................................... 7-7
RCW Bit Descriptions ............................................................................................................ 7-11
Reset Clocks Source Configuration .......................................................................................... 8-9
TMBCLK Divisions ............................................................................................................... 8-10
Status of Clock Source............................................................................................................ 8-16
Power Mode Control Bit Settings .......................................................................................... 8-17
Power Mode Descriptions...................................................................................................... 8-17
Power Mode Wake-Up Operation ......................................................................................... 8-18
Power Supplies ....................................................................................................................... 8-21
KAPWR Registers and Key Registers.................................................................................... 8-26
SCCR Bit Descriptions ........................................................................................................... 8-30
COM and CQDS Bits Functionality ....................................................................................... 8-33
PLPRCR Bit Descriptions ..................................................................................................... 8-34
COLIR Bit Descriptions ........................................................................................................ 8-36
VSRMCR Bit Descriptions.................................................................................................... 8-37
MPC561/MPC563 BIU Signals................................................................................................ 9-4
Data Bus Requirements For Read Cycles............................................................................... 9-31
Data Bus Contents for Write Cycles....................................................................................... 9-32
Priority Between Internal and External Masters over External Bus ....................................... 9-36
4 Word Burst Length and Order ............................................................................................. 9-38
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxv
Tables
Table
Number
9-6
9-7
9-8
9-9
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
12-1
12-2
12-3
12-4
12-5
12-6
12-7
13-1
13-2
13-3
13-4
13-5
13-6
Title
Page
Number
BURST/TSIZE Encoding ....................................................................................................... 9-38
Address Type Pins .................................................................................................................. 9-39
Address Types Definition ....................................................................................................... 9-39
Termination Signals Protocol ................................................................................................. 9-49
Timing Requirements for Reduced Setup Time ..................................................................... 10-6
Timing Attributes Summary ................................................................................................. 10-11
Programming Rules for Timing Strobes ............................................................................... 10-22
Write Enable/Byte Enable Signals Function ........................................................................ 10-24
Boot Bank Fields Values After Hard Reset .......................................................................... 10-28
Memory Controller Address Map......................................................................................... 10-31
MSTAT Bit Descriptions..................................................................................................... 10-32
BR0–BR3 Bit Descriptions.................................................................................................. 10-33
BRx[V] Reset Value ............................................................................................................ 10-34
OR0–OR3 Bit Descriptions ................................................................................................. 10-35
DMBR Bit Descriptions........................................................................................................ 10-36
DMOR Bit Descriptions ....................................................................................................... 10-38
DMPU Registers ..................................................................................................................... 11-6
Reservation Snoop Support .................................................................................................... 11-9
L2U_MCR LSHOW Modes ................................................................................................. 11-10
L2U Show Cycle Support Chart ........................................................................................... 11-12
L2U (PPC) Register Decode................................................................................................. 11-12
Hex Address For SPR Cycles ............................................................................................... 11-13
L2U_MCR Bit Descriptions ................................................................................................ 11-14
L2U_RBAx Bit Descriptions............................................................................................... 11-15
L2U_RAx Bit Descriptions ................................................................................................. 11-15
L2U_GRA Bit Descriptions................................................................................................. 11-16
STOP and HSPEED Bit Functionality.................................................................................... 12-2
Bus Cycles and System Clock Cycles .................................................................................... 12-3
ILBS Signal Functionality ...................................................................................................... 12-5
IRQMUX Functionality .......................................................................................................... 12-5
UIMB Interface Register Map ................................................................................................ 12-6
UMCR Bit Descriptions.......................................................................................................... 12-8
UIPEND Bit Descriptions....................................................................................................... 12-9
QADC64E_A Address Map ................................................................................................... 13-3
QADC64E_B Address Map.................................................................................................... 13-4
Multiplexed Analog Input Channels....................................................................................... 13-7
Analog Input Channels ........................................................................................................... 13-7
QADCMCR Bit Descriptions ................................................................................................. 13-8
QADC64E Bus Error Response............................................................................................ 13-11
MPC561/MPC563 Reference Manual, Rev. 1.2
lxvi
Freescale Semiconductor
Tables
Table
Number
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
Title
Page
Number
QADCINT Bit Descriptions ................................................................................................. 13-12
PORTQA, PORTQB Bit Descriptions.................................................................................. 13-14
QACR0 Bit Descriptions ...................................................................................................... 13-15
QACR1 Bit Descriptions ...................................................................................................... 13-16
Queue 1 Operating Modes .................................................................................................... 13-16
QACR2 Bit Descriptions ...................................................................................................... 13-18
Queue 2 Operating Modes .................................................................................................... 13-19
QASR0 Bit Descriptions....................................................................................................... 13-21
Pause Response..................................................................................................................... 13-25
Queue Status ......................................................................................................................... 13-25
QASR1 Bit Descriptions....................................................................................................... 13-27
CCW Bit Descriptions .......................................................................................................... 13-30
Non-Multiplexed Channel Assignments and Signal Designations....................................... 13-31
Multiplexed Channel Assignments and Signal Designations ............................................... 13-32
QADC64E Clock Programmability ...................................................................................... 13-50
Trigger Events....................................................................................................................... 13-54
Status Bits ............................................................................................................................. 13-55
External Circuit Settling Time to 1/2 LSB (10-Bit Conversions) ....................................... 13-75
Error Resulting from Input Leakage (IOFF)......................................................................... 13-76
QADC64E_A Address Map ................................................................................................... 14-3
QADC64E_B Address Map.................................................................................................... 14-4
Multiplexed Analog Input Channels....................................................................................... 14-6
Analog Input Channels ........................................................................................................... 14-7
QADCMCR Bit Descriptions ................................................................................................. 14-8
QADC64E Bus Error Response............................................................................................ 14-11
QADCINT Bit Descriptions ................................................................................................. 14-12
PORTQA, PORTQB Bit Descriptions.................................................................................. 14-13
QACR0 Bit Descriptions ...................................................................................................... 14-15
Prescaler fSYSCLK Divide-by Values.................................................................................... 14-15
QACR1 Bit Descriptions ...................................................................................................... 14-17
Queue 1 Operating Modes .................................................................................................... 14-17
QACR2 Bit Descriptions ...................................................................................................... 14-19
Queue 2 Operating Modes .................................................................................................... 14-20
QASR0 Bit Descriptions....................................................................................................... 14-22
Pause Response..................................................................................................................... 14-26
Queue Status ......................................................................................................................... 14-26
QASR1 Bit Descriptions....................................................................................................... 14-28
CCW Bit Descriptions .......................................................................................................... 14-31
QADC64E_A Multiplexed Channel Assignments and Signal Designations ....................... 14-32
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxvii
Tables
Table
Number
14-21
14-22
14-23
14-24
14-25
14-26
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
15-18
15-19
15-20
15-21
15-22
15-23
15-24
15-25
15-26
15-27
15-28
15-29
15-30
15-31
15-32
15-33
Title
Page
Number
QADC64E_B Multiplexed Channel Assignments and Signal Designations........................ 14-33
QADC64E Clock Programmability ...................................................................................... 14-50
Trigger Events....................................................................................................................... 14-53
Status Bits ............................................................................................................................. 14-54
External Circuit Settling Time to 1/2 LSB (10-Bit Conversions) ........................................ 14-73
Error Resulting From Input Leakage (IOFF)........................................................................ 14-74
QSMCM Register Map ........................................................................................................... 15-4
QSMCM Global Registers...................................................................................................... 15-6
Interrupt Levels....................................................................................................................... 15-7
QSMCMMCR Bit Descriptions.............................................................................................. 15-9
QDSCI_IL Bit Descriptions.................................................................................................... 15-9
QSPI_IL Bit Descriptions ..................................................................................................... 15-10
QSMCM Pin Control Registers ............................................................................................ 15-10
Effect of DDRQS on QSPI Pin Function.............................................................................. 15-11
QSMCM Pin Functions ........................................................................................................ 15-12
PQSPAR Bit Descriptions .................................................................................................... 15-13
DDRQS Bit Descriptions...................................................................................................... 15-14
QSPI Register Map ............................................................................................................... 15-16
SPCR0 Bit Descriptions....................................................................................................... 15-18
Bits Per Transfer ................................................................................................................... 15-18
SPCR1 Bit Descriptions........................................................................................................ 15-19
SPCR2 Bit Descriptions....................................................................................................... 15-20
SPCR3 Bit Descriptions....................................................................................................... 15-21
SPSR Bit Descriptions ......................................................................................................... 15-22
Command RAM Bit Descriptions........................................................................................ 15-24
QSPI Pin Functions............................................................................................................... 15-25
Example SCK Frequencies with a 40-MHz IMB3 Clock..................................................... 15-35
PCS Enhanced Functionality ................................................................................................ 15-37
SCI Registers ........................................................................................................................ 15-45
SCCxR0 Bit Descriptions ..................................................................................................... 15-46
SCCxR1 Bit Descriptions .................................................................................................... 15-47
SCxSR Bit Descriptions....................................................................................................... 15-49
SCxDR Bit Descriptions ...................................................................................................... 15-51
SCI Pin Functions ................................................................................................................. 15-51
Serial Frame Formats............................................................................................................ 15-52
Examples of SCIx Baud Rates.............................................................................................. 15-53
Effect of Parity Checking on Data Size ................................................................................ 15-53
QSCI1CR Bit Descriptions ................................................................................................... 15-60
QSCI1SR Bit Descriptions ................................................................................................... 15-61
MPC561/MPC563 Reference Manual, Rev. 1.2
lxviii
Freescale Semiconductor
Tables
Table
Number
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
16-20
16-21
16-22
16-23
16-24
16-25
16-26
16-27
16-28
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
Title
Page
Number
Common Extended/Standard Format Frames ........................................................................ 16-4
Message Buffer Codes for Receive Buffers............................................................................ 16-5
Message Buffer Codes for Transmit Buffers .......................................................................... 16-5
Extended Format Frames ........................................................................................................ 16-6
Standard Format Frames ......................................................................................................... 16-6
Receive Mask Register Bit Values ......................................................................................... 16-8
Mask Examples for Normal/Extended Messages .................................................................. 16-8
Example System Clock, CAN Bit Rate, and S-Clock Frequencies ........................................ 16-9
Interrupt Levels..................................................................................................................... 16-20
TouCAN Register Map ......................................................................................................... 16-21
CANMCR Bit Descriptions .................................................................................................. 16-25
CANICR Bit Descriptions ................................................................................................... 16-27
CANCTRL0 Bit Descriptions............................................................................................... 16-28
Rx MODE[1:0] Configuration.............................................................................................. 16-28
Transmit Signal Configuration ............................................................................................. 16-28
CANCTRL1 Bit Descriptions............................................................................................... 16-29
PRESDIV Bit Descriptions.................................................................................................. 16-30
CANCTRL2 Bit Descriptions.............................................................................................. 16-30
TIMER Bit Descriptions ....................................................................................................... 16-31
RXGMSKHI, RXGMSKLO Bit Descriptions...................................................................... 16-32
RX14MSKHI, RX14MSKLO Field Descriptions ................................................................ 16-32
RX15MSKHI, RX15MSKLO Field Descriptions ................................................................ 16-33
ESTAT Bit Descriptions ...................................................................................................... 16-34
Transmit Bit Error Status ...................................................................................................... 16-35
Fault Confinement State Encoding ....................................................................................... 16-35
IMASK Bit Descriptions ...................................................................................................... 16-36
IFLAG Bit Descriptions....................................................................................................... 16-36
RXECTR, TXECTR Bit Descriptions ................................................................................. 16-36
MIOS14 Configuration Description ....................................................................................... 17-6
MIOS14 I/O Ports ................................................................................................................. 17-13
MIOS14TPCR Bit Descriptions ........................................................................................... 17-14
MIOS14VNR Bit Descriptions ............................................................................................. 17-15
MIOS14MCR Bit Descriptions ............................................................................................ 17-15
MCPSM Register Address Map ........................................................................................... 17-17
MCPSMSCR Bit Descriptions ............................................................................................ 17-18
Clock Prescaler Setting ......................................................................................................... 17-18
MMCSM Address Map ........................................................................................................ 17-22
MMCSMCNT Bit Descriptions............................................................................................ 17-23
MMCSMML Bit Descriptions.............................................................................................. 17-24
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxix
Tables
Table
Number
17-12
17-13
17-14
17-15
17-16
17-17
17-18
17-19
17-20
17-21
17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
17-30
17-31
17-32
17-33
17-34
17-35
17-36
17-37
17-38
17-39
17-40
17-41
17-42
17-43
18-1
18-2
18-3
18-4
18-5
18-6
18-7
Title
Page
Number
MMCSMSCR Bit Descriptions ............................................................................................ 17-25
MMCSMCNT Edge Sensitivity............................................................................................ 17-25
MMCSMCNT Clock Signal ................................................................................................. 17-25
Prescaler Values................................................................................................................... 17-26
MDASM Modes of Operation .............................................................................................. 17-29
MDASM PWM Example Output Frequencies/Resolutions at fSYS = 40 MHz.................... 17-38
MDASM Address Map ......................................................................................................... 17-39
MDASMAR Bit Descriptions............................................................................................... 17-42
MDASMBR Bit Descriptions ............................................................................................... 17-43
MDASMSCR Bit Descriptions............................................................................................. 17-44
MDASM Mode Selects......................................................................................................... 17-45
MDASM Counter Bus Selection .......................................................................................... 17-46
PWM Pulse/Frequency Ranges (in Hz) Using /1 or /256 Option (40 MHz) ........................ 17-52
MPWMSM Address Map ..................................................................................................... 17-55
MPWMPERR Bit Descriptions ............................................................................................ 17-57
MPWMPULR Bit Descriptions ............................................................................................ 17-58
MPWMCNTR Bit Descriptions............................................................................................ 17-58
MPWMSCR Bit Descriptions............................................................................................... 17-59
PWMSM Output Signal Polarity Selection .......................................................................... 17-59
Prescaler Values.................................................................................................................... 17-60
MPIOSM I/O Signal Function .............................................................................................. 17-61
MPIOSMDR Bit Descriptions .............................................................................................. 17-63
MPIOSMDDR Bit Descriptions ........................................................................................... 17-63
MIOS14SR0 Bit Description ................................................................................................ 17-66
MIOS14ER0 Bit Descriptions .............................................................................................. 17-66
MIOS14PR0 Bit Descriptions .............................................................................................. 17-67
MIOS14SR1 Bit Descriptions .............................................................................................. 17-67
MIOS14ER1 Bit Descriptions .............................................................................................. 17-68
MIOS14RPR1 Bit Descriptions............................................................................................ 17-68
MBISM Interrupt Registers Address Map............................................................................ 17-69
MIOS14LVL0 Bit Descriptions............................................................................................ 17-70
MIOS14LVL1 Bit Descriptions............................................................................................ 17-70
PPM Memory Map ................................................................................................................. 18-2
PPMMCR Bit Descriptions .................................................................................................. 18-11
PPMPCR Bit Descriptions.................................................................................................... 18-12
SAMP[0:2] Bit Settings ........................................................................................................ 18-13
PPMPCR[CM] and PPMPCR[STR] Bit Operation.............................................................. 18-15
Configuration Register (TX and RX) Channel Settings ....................................................... 18-17
SHORT_REG Bit Descriptions ............................................................................................ 18-20
MPC561/MPC563 Reference Manual, Rev. 1.2
lxx
Freescale Semiconductor
Tables
Table
Number
18-8
18-9
18-10
18-11
18-12
18-13
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
20-1
20-2
20-3
21-1
21-2
21-3
21-4
21-5
21-6
Title
Page
Number
SHORT_REG[SH_TCAN] Bit Settings ............................................................................... 18-20
SHORT_REG[SH_TPU] Bit Settings .................................................................................. 18-21
SHORT_CH_REG Bit Descriptions..................................................................................... 18-23
Examples of the SHORT_CH Bits ....................................................................................... 18-23
SCALE_TCLK Frequencies ................................................................................................. 18-24
SCALE_TCLK_REG Bit Descriptions ................................................................................ 18-24
TPU Memory Map.................................................................................................................. 19-1
Enhanced TCR1 Prescaler Divide Values .............................................................................. 19-6
TCR1 Prescaler Values ........................................................................................................... 19-6
TCR2 Counter Clock Source .................................................................................................. 19-7
TCR2 Prescaler Control.......................................................................................................... 19-8
TPU3 Register Map ................................................................................................................ 19-8
TPUMCR Bit Description .................................................................................................... 19-11
DSCR Bit Descriptions ......................................................................................................... 19-12
DSSR Bit Descriptions ......................................................................................................... 19-14
TICR Bit Description............................................................................................................ 19-15
CIER Bit Descriptions .......................................................................................................... 19-15
CFSRn Bit Descriptions........................................................................................................ 19-16
HSQRn Bit Descriptions....................................................................................................... 19-17
HSSRn Bit Descriptions ....................................................................................................... 19-18
CPRn Bit Description ........................................................................................................... 19-18
Channel Priorities ................................................................................................................. 19-18
CISR Bit Descriptions .......................................................................................................... 19-19
TPUMCR2 Bit Descriptions ................................................................................................. 19-19
Entry Table Bank Location................................................................................................... 19-20
System Clock Frequency/Minimum Guaranteed Detected Pulse......................................... 19-20
TPUMCR3 Bit Descriptions ................................................................................................. 19-21
SIUTST Bit Descriptions...................................................................................................... 19-22
Registers Used for Factory Test Only .................................................................................. 19-22
Parameter RAM Address Offset Map .................................................................................. 19-23
DPTRAM Register Map ......................................................................................................... 20-3
DPTMCR Bit Settings ............................................................................................................ 20-4
RAMBAR Bit Settings ........................................................................................................... 20-5
UC3F External Interface Signals ............................................................................................ 21-4
UC3F Register Programming Model ...................................................................................... 21-5
UC3FMCR Bit Descriptions................................................................................................... 21-6
UC3FMCRE Bit Descriptions ................................................................................................ 21-9
UC3FCTL Bit Descriptions .................................................................................................. 21-11
RCW Bit Descriptions .......................................................................................................... 21-17
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxi
Tables
Table
Number
21-7
21-8
21-9
21-10
22-1
22-2
22-3
22-4
22-5
22-6
22-7
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
23-25
23-26
23-27
23-28
Title
Page
Number
Program Interlock State Descriptions ................................................................................... 21-23
Erase Interlock State Descriptions ........................................................................................ 21-27
Censorship States .................................................................................................................. 21-30
Censorship Modes and Censorship Status ............................................................................ 21-31
Priorities of Overlay Regions ............................................................................................... 22-12
CALRAM Control Registers ................................................................................................ 22-13
CRAMMCR Bit Descriptions............................................................................................... 22-14
CRAMMCR Privilege Bit Assignment for 8-Kbyte Array Blocks ...................................... 22-15
CRAM_RBAx Bit Descriptions ........................................................................................... 22-16
RGN_SIZE Encoding ........................................................................................................... 22-16
CRAMOVLCR Bit Descriptions .......................................................................................... 22-17
VF Pins Instruction Encodings ............................................................................................... 23-3
VF Pins Queue Flush Encodings ............................................................................................ 23-3
VFLS Pin Encodings .............................................................................................................. 23-4
Detecting the Trace Buffer Start Point ................................................................................... 23-6
Fetch Show Cycles Control .................................................................................................... 23-7
Instruction Watchpoints Programming Options ................................................................... 23-15
Load/Store Data Events ........................................................................................................ 23-16
Load/Store Watchpoints Programming Options................................................................... 23-17
Check Stop State and Debug Mode ...................................................................................... 23-27
Trap Enable Data Shifted into Development Port Shift Register ......................................... 23-34
Debug Port Command Shifted Into Development Port Shift Register ................................. 23-34
Status / Data Shifted Out of Development Port Shift Register............................................. 23-35
Debug Instructions / Data Shifted into Development Port Shift Register ............................ 23-36
Development Support Programming Model......................................................................... 23-39
Development Support Registers Read Access Protection .................................................... 23-40
Development Support Registers Write Access Protection ................................................... 23-41
CMPA-CMPD Bit Descriptions ........................................................................................... 23-41
ECR Bit Descriptions............................................................................................................ 23-42
DER Bit Descriptions ........................................................................................................... 23-43
Breakpoint Counter A Value and Control Register (COUNTA).......................................... 23-45
Breakpoint Counter B Value and Control Register (COUNTB) ......................................... 23-46
CMPE–CMPF Bit Descriptions............................................................................................ 23-46
CMPG-CMPH Bit Descriptions ........................................................................................... 23-47
LCTRL1 Bit Descriptions..................................................................................................... 23-47
LCTRL2 Bit Descriptions..................................................................................................... 23-49
ICTRL Bit Descriptions........................................................................................................ 23-51
ISCT_SER Bit Descriptions ................................................................................................. 23-52
BAR Bit Descriptions ........................................................................................................... 23-53
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxii
Tables
Table
Number
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
24-16
24-17
24-18
24-19
24-20
24-21
24-22
24-23
24-24
24-25
24-26
24-27
24-28
24-29
24-30
24-31
24-32
24-33
24-34
24-35
25-1
25-2
25-3
A-1
Title
Page
Number
Public Messages...................................................................................................................... 24-5
Vendor-Defined Messages...................................................................................................... 24-5
Terms and Definitions ............................................................................................................ 24-6
OTR Bit Descriptions ............................................................................................................. 24-9
Tool-Mapped Register Space.................................................................................................. 24-9
DID Bit Descriptions ............................................................................................................ 24-10
DC Bit Descriptions.............................................................................................................. 24-11
RCPU Development Access Modes ..................................................................................... 24-11
MC Bit Descriptions ............................................................................................................. 24-12
UBA Bit Descriptions ........................................................................................................... 24-13
RWA Read/Write Access Bit Descriptions .......................................................................... 24-14
UDI Bit Descriptions ............................................................................................................ 24-16
Read Access Status ............................................................................................................... 24-16
Write Access Status .............................................................................................................. 24-16
DTA 1 AND 2 Bit Descriptions ........................................................................................... 24-17
Data Trace Values................................................................................................................. 24-18
Description of READI Signals ............................................................................................. 24-21
MSEI/MSEO Protocol .......................................................................................................... 24-23
Public Messages Supported .................................................................................................. 24-24
Error Message Codes ............................................................................................................ 24-27
Vendor-Defined Messages Supported .................................................................................. 24-27
Message Field Sizes, ............................................................................................................. 24-29
Indirect Branch Message ...................................................................................................... 24-33
Direct Branch Message ......................................................................................................... 24-33
READI Reset Configuration Options ................................................................................... 24-34
Bit Pointer Format ................................................................................................................ 24-39
Program Trace Correction Due to a Mispredicted Branch ................................................... 24-40
Program Trace Correction Due to an Exception................................................................... 24-41
Resource Codes..................................................................................................................... 24-46
Special L-Bus Case Handling ............................................................................................... 24-56
Throughput Comparison for FPM and RPM MDO/MDI Configurations ............................ 24-68
Watchpoint Source................................................................................................................ 24-73
Development Port Access: DSDI Field ................................................................................ 24-84
Development Port Access: DSDO Field............................................................................... 24-84
Power Management Mechanism Overview .......................................................................... 24-86
MPC561 Boundary Scan Bit Definition ................................................................................. 25-5
MPC563 Boundary Scan Bit Definition ............................................................................... 25-17
Instruction Decoding............................................................................................................. 25-30
ICTRL Bit Descriptions......................................................................................................... A-17
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxiii
Tables
Table
Number
A-2
A-3
A-4
B-1
B-2
B-3
B-4
B-5
B-6
B-7
B-8
B-9
B-10
B-11
B-12
B-13
B-14
B-15
B-16
B-17
B-18
C-1
C-2
D-1
D-2
D-3
D-4
E-1
E-2
F-1
F-2
F-3
F-4
F-5
F-6
F-7
F-8
F-9
F-10
Title
Page
Number
ISCT_SER Bit Descriptions .................................................................................................. A-18
DCCR0-DCCR15 Field Descriptions .................................................................................... A-20
Instruction Layout Encoding ................................................................................................. A-21
SPR (Special Purpose Registers) ..............................................................................................B-2
UC3F Flash Array.....................................................................................................................B-4
DECRAM SRAM Array...........................................................................................................B-4
BBC (Burst Buffer Controller Module)....................................................................................B-4
USIU (Unified System Interface Unit) .....................................................................................B-5
CDR3 Flash Control Registers EEPROM (UC3F)...................................................................B-9
DPTRAM Control Registers...................................................................................................B-10
DPTRAM Memory Arrays .....................................................................................................B-10
Time Processor Unit 3 A and B (TPU3 A and B) ..................................................................B-10
QADC64E A and B (Queued Analog-to-Digital Converter)..................................................B-14
QSMCM (Queued Serial Multi-Channel Module) .................................................................B-16
Peripheral Pin Multiplexing (PPM) Module...........................................................................B-17
MIOS14 (Modular Input/Output Subsystem) .........................................................................B-18
TouCAN A, B and C (CAN 2.0B Controller) ........................................................................B-26
UIMB (U-Bus to IMB Bus Interface).....................................................................................B-31
CALRAM Control Registers ..................................................................................................B-31
CALRAM Array .....................................................................................................................B-32
READI Module Registers .......................................................................................................B-32
External Components Value For Different Crystals (Q1) ........................................................C-4
IRAMSTBY Regulator Operating Specifications ....................................................................C-8
Bank 0 and Bank 1 Functions .................................................................................................. D-2
QOM Bit Encoding .................................................................................................................. D-5
SIOP Function Valid CHAN_Control Options ..................................................................... D-56
SIOP State Timing ................................................................................................................. D-58
Memory Access Times Using Different Buses.........................................................................E-1
Instruction Timing Examples for Different Buses....................................................................E-2
Absolute Maximum Ratings (VSS = 0V) ................................................................................. F-1
Thermal Characteristics ............................................................................................................ F-3
ESD Protection ......................................................................................................................... F-6
DC Electrical Characteristics.................................................................................................... F-7
Oscillator and PLL.................................................................................................................. F-11
Array Program and Erase Characteristics ............................................................................... F-12
CENSOR Cell Program and Erase Characteristics................................................................. F-12
Flash Module Life................................................................................................................... F-12
Power Supply Pin Groups....................................................................................................... F-13
Bus Operation Timing ............................................................................................................ F-20
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Tables
Table
Number
F-12
F-11
F-13
F-14
F-15
F-16
F-17
F-18
F-19
F-20
F-21
F-22
F-23
F-24
F-25
F-26
F-27
F-28
G-1
G-2
G-3
G-4
G-5
G-6
G-7
G-8
G-9
G-10
G-11
G-12
G-13
G-14
G-15
G-16
G-17
G-18
G-19
G-20
G-21
Title
Page
Number
Debug Port Timing ................................................................................................................. F-43
Interrupt Timing...................................................................................................................... F-43
READI AC Electrical Characteristics..................................................................................... F-45
RESET Timing ....................................................................................................................... F-47
JTAG Timing .......................................................................................................................... F-50
QADC64E Conversion Characteristics .................................................................................. F-54
QSPI Timing ........................................................................................................................... F-56
QSCI Timing........................................................................................................................... F-57
GPIO Timing .......................................................................................................................... F-60
TPU3 Timing .......................................................................................................................... F-61
TouCAN Timing..................................................................................................................... F-62
PPM Timing............................................................................................................................ F-62
MCPSM Timing Characteristics............................................................................................. F-64
MPWMSM Timing Characteristics ........................................................................................ F-64
MMCSM Timing Characteristics ........................................................................................... F-67
MDASM Timing Characteristics............................................................................................ F-69
MPIOSM Timing Characteristics ........................................................................................... F-71
MPC561/MPC563 Signal Names and Pin Names .................................................................. F-73
Absolute Maximum Ratings (VSS = 0V) ................................................................................ G-1
Thermal Characteristics ........................................................................................................... G-3
ESD Protection ........................................................................................................................ G-6
DC Electrical Characteristics................................................................................................... G-7
Oscillator and PLL................................................................................................................. G-10
Array Program and Erase Characteristics .............................................................................. G-11
CENSOR Cell Program and Erase Characteristics................................................................ G-11
Flash Module Life.................................................................................................................. G-12
Power Supply Pin Groups...................................................................................................... G-12
Bus Operation Timing ........................................................................................................... G-20
Interrupt Timing..................................................................................................................... G-40
Debug Port Timing ................................................................................................................ G-41
READI AC Electrical Characteristics.................................................................................... G-43
RESET Timing ...................................................................................................................... G-44
JTAG Timing ......................................................................................................................... G-47
QADC64E Conversion Characteristics ................................................................................. G-50
QSPI Timing .......................................................................................................................... G-52
QSCI Timing.......................................................................................................................... G-53
GPIO Timing ......................................................................................................................... G-56
TPU3 Timing ......................................................................................................................... G-57
TouCAN Timing.................................................................................................................... G-58
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Tables
Table
Number
G-22
G-23
G-24
G-25
G-26
G-27
G-28
Title
Page
Number
PPM Timing........................................................................................................................... G-58
MCPSM Timing Characteristics............................................................................................ G-60
MPWMSM Timing Characteristics ....................................................................................... G-60
MMCSM Timing Characteristics .......................................................................................... G-62
MDASM Timing Characteristics........................................................................................... G-64
MPIOSM Timing Characteristics .......................................................................................... G-67
MPC561/MPC563 Signal Names and Pin Names ................................................................. G-68
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About This Book
This manual describes the capabilities, operation, and function of the Freescale MPC561/MPC563
microcontrollers. The documentation follows the modular construction of the devices in the MPC500
family product line. Each microcontroller in the MPC500 family has a comprehensive reference manual
that provides sufficient information for normal operation of the device. The reference manual is
supplemented by module-specific reference manuals that provide detailed information about module
operation and applications. Where information in this manual varies from information in other references,
this manual takes precedence. Refer to Suggested Reading for further information.
Unless otherwise noted, references to the MPC561 and MPC563 also apply to their code compressed
counterparts, the MPC562 and MPC564, respectively. Any functional differences between the
MPC561/MPC563 and MPC562/MPC564 are noted. MPC562/MPC564-specific information is located in
Appendix A, “MPC562/MPC564 Compression Features.”
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products for the MPC561/MPC563. It is assumed that the reader understands operating
systems and microprocessor and microcontroller system design.
Organization
Following is a summary and brief description of the major sections of this manual:
• Chapter 1, “Overview,” provides an overview of the MPC561/MPC563 microcontroller, including
a block diagram showing the major modular components, a features list, and a summary of
differences between the MPC561/MPC563 and the MPC555.
• Chapter 2, “Signal Descriptions,” describes the MPC561/MPC563 microcontroller’s external
signals.
• Chapter 3, “Central Processing Unit,” describes the RISC processor (RCPU) used in the MPC500
family of microcontrollers.
• Chapter 4, “Burst Buffer Controller 2 Module,” describes the three main functional parts: the bus
interface unit (BIU), the instruction memory protection unit (IMPU), and the instruction code
decompressor unit (ICDU).
• Chapter 5, “Unified System Interface Unit (USIU) Overview.” The unified system interface unit
(USIU) of the MPC561/MPC563 consists of several functional modules that control system
start-up, system initialization and operation, system protection, and the external system bus.
• Chapter 6, “System Configuration and Protection.” The MPC561/MPC563 incorporates many
system functions that normally must be provided in external circuits. In addition, it is designed to
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•
provide maximum system safeguards against hardware and software faults. This chapter provides
a detailed explanation of this functionality.
Chapter 7, “Reset.” This section describes the MPC561/MPC563 reset sources, operation, control,
and status.
Chapter 8, “Clocks and Power Control,” describes the main timing and power control reference for
the MPC561/MPC563.
Chapter 9, “External Bus Interface,” describes the functionality of the MPC561/MPC563 external
bus.
Chapter 10, “Memory Controller,” generates interface signals to support a glueless interface to
external memory and peripheral devices.
Chapter 11, “L-Bus to U-Bus Interface (L2U),” describes the interface between the load/store bus
(L-bus) and the unified bus (U-bus). The L2U module includes the Data Memory Protection Unit
(DMPU), which provides protection for data memory accesses.
Chapter 12, “U-Bus to IMB3 Bus Interface (UIMB).” The U-bus to IMB3 bus interface (UIMB)
structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3).
It controls bus communication between the U-bus and the IMB3.
Chapter 13, “QADC64E Legacy Mode Operation.” The two queued analog-to-digital converter
(QADC) modules on MPC561/MPC563 devices are 10-bit, unipolar, successive approximation
converters. The modules can be configured to operate in one of two modes, legacy mode (MPC555
compatible) and enhanced mode. This chapter describes how the modules operate in legacy mode,
which is the default mode of operation.
Chapter 14, “QADC64E Enhanced Mode Operation.” The two queued analog-to-digital converter
(QADC) modules on the MPC561/MPC563 devices are 10-bit, unipolar, successive approximation
converters. The modules can be configured to operate in one of two modes, legacy mode (for
MPC555 compatibility) and enhanced mode. This chapter describes how the module operates in
enhanced mode.
Chapter 15, “Queued Serial Multi-Channel Module.” The MPC561/MPC563 contains one queued
serial multi-channel module (QSMCM) which provides three serial communication interfaces: the
queued serial peripheral interface (QSPI) and two serial communications interfaces (SCI/UART).
This chapter describes the functionality of each.
Chapter 16, “CAN 2.0B Controller Module,” describes the three CAN 2.0B controller modules
(TouCAN) implemented on the MPC561/MPC563. Each TouCAN is a communication controller
that implements the Controller Area Network (CAN) protocol, an asynchronous communications
protocol used in automotive and industrial control systems. It is a high speed (one Mbit/sec), short
distance, priority based protocol that can run over a variety of mediums.
Chapter 17, “Modular Input/Output Subsystem (MIOS14).” The modular I/O system (MIOS)
consists of a library of flexible I/O and timer functions including I/O port, counters, input capture,
output compare, pulse and period measurement, and PWM. Because the MIOS14 is composed of
submodules, it is easily configurable for different kinds of applications.
Chapter 18, “Peripheral Pin Multiplexing (PPM) Module.” The PPM functions as a
parallel-to-serial communications module that reduces the number of signals required to connect
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•
the MPC561/MPC563 to an external device; and shorts internal signals to increase access to
multiple functions multiplexed on the same external signal.
Chapter 19, “Time Processor Unit 3,” describes an enhanced version of the original TPU, an
intelligent, semi-autonomous microcontroller designed for timing control.
Chapter 20, “Dual-Port TPU3 RAM (DPTRAM).” The dual-port RAM (DPTRAM) module
consists of a control register block and an 8-Kbyte array of static RAM that can be used either as
microcode storage for the TPU3 or as general-purpose memory. The MPC561/MPC563 has one
DPTRAM module that serves two TPU3 modules.
Chapter 21, “CDR3 Flash (UC3F) EEPROM.” The MPC563 U-bus CDR3 (UC3F) EEPROM
module is designed for use in embedded microcontroller applications targeted for high-speed read
performance and high-density byte count requirements.
Chapter 22, “CALRAM Operation.” This module provides the MPC561/MPC563 with a general
purpose memory that may be read from or written to as either bytes, half-words, or words. In
addition to this, a portion of the CALRAM, called the overlay region, can be used for calibration
(i.e., overlaying portions of the U-bus Flash with a portion of the CALRAM array).
Chapter 23, “Development Support,” covers program flow tracking support,
breakpoint/watchpoint support, development system interface support (debug mode) and software
monitor debugger support. These features allow efficiency in debugging systems based on the
MPC561/MPC563.
Chapter 24, “READI Module.” The READI module provides development support capabilities for
MCUs in single chip mode, without requiring address and data signals for internal visibility.
Chapter 25, “IEEE 1149.1-Compliant Interface (JTAG),” describes MPC561/MPC563
compatibility with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture as
well as any potential incompatibility issues.
Appendix A, “MPC562/MPC564 Compression Features,” includes information about code
compression features of the MPC562/MPC564.
Appendix B, “Internal Memory Map,” provides memory maps for the MPC561/MPC563 modules.
Appendix C, “Clock and Board Guidelines.” The MPC561/MPC563 built-in PLL, oscillator, and
other analog and sensitive circuits require that the board design follow special layout guidelines to
ensure proper operation of the chip clocks. This appendix describes how the clock supplies and
external components should be connected in a system.
Appendix D, “TPU3 ROM Functions,” provides a brief description of the pre-programmed
functions in the TPU3.
Appendix E, “Memory Access Timing,” lists memory access timings for internal and external
memory combinations.
Appendix F, “Electrical Characteristics,” contains detailed information on power considerations,
DC/AC electrical characteristics, and AC timing characteristics of the MPC561/MPC563 at the
default 40 MHz and optional 56 MHz operating frequencies.
Appendix G, “66-MHz Electrical Characteristics,” contains detailed information on power
considerations, DC/AC electrical characteristics, and AC timing characteristics of the
MPC561/MPC563 at the optional operating frequency of 66 MHz.
This document also includes a register index and comprehensive index.
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Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPCΤΜ architecture. Also listed are documents that further complement
this manual by providing in-depth functional descriptions of certain modules:
• QSM (Queued Serial Module) Reference Manual (QSMRM/AD)
• TPU (Time Processor Unit) documentation (TPULITPAK/D, including the TPURM/AD)
• RCPU (RISC Central Processor Unit) Reference Manual (RCPURM/AD)
• Nexus Standard Specification Rev 1.0 (IEEE-ISTO 5001-1999) available at:
http://www.nexus5001.org/
•
JTAG IEEE 1149.1 Specification
The following general documentation, available through Morgan-Kaufmann Publishers, 340 Pine Street,
Sixth Floor, San Francisco, CA, provides useful information about the PowerPC architecture:
• The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
Freescale documentation is available from the sources listed on the back cover of this manual. A brief
summary of available documentation is listed below:
• Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture
(MPCFPE32B/AD)—Describes resources defined by the PowerPC architecture.
• Reference manuals—These books provide details about individual implementations and are
intended for use with the Programming Environments Manual.
• Addenda/errata to reference manuals—Because some processors have follow-on parts, an
addendum is provided that describes the additional features and functionality changes and are
intended for use with the corresponding reference manuals.
• Product Briefs—Each device has a product brief that provides an overview of its features. This
document is roughly the equivalent to the overview chapter (Chapter 1) of an implementation’s
reference manual.
• The Programmer’s Reference Guide for the PowerPC Architecture (MPCPRG/D)—This concise
reference includes the register summary, exception vectors, and the PowerPC ISA instruction set.
• Application notes—These short documents address specific design issues useful to programmers
and engineers working with Freescale processors.
Additional literature is published as new processors become available. For a current list of documentation,
refer to http://www.motorola.com/semiconductors.
Conventions and Nomenclature
This document uses the following notational conventions:
cleared/set
When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
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ACTIVE_HIGH
ACTIVE_LOW
0x0
0b0
italics
REG[FIELD]
x
n
¬
&
|
Logic level one
Logic level zero
To set a bit or bits
To clear a bit or bits
LSB
MSB
Asserted
Negated
Names for signals that are active high are shown in uppercase text. Signals that are
active high are referred to as asserted when they are high and negated when they
are low.
Names for signals that are active low are shown in uppercase text with an overbar.
Active-low signals are referred to as asserted (active) when they are low and
negated when they are high.
Prefix to denote hexadecimal number
Prefix to denote binary number
Italics indicate variable command parameters.
Book titles in text are also set in italics.
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, CRAMMCR[DIS] identifies the array disable bit
(DIS) within the CALRAM module configuration register.
A range of bits or signals is referred to by mnemonic and the numbers that define
the range. For example, DATA[24:31] form the least significant byte of the data
bus.
In some contexts, such as signal encodings, x indicates a don’t care.
Used to express an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
is the voltage that corresponds to Boolean true (1) state.
is the voltage that corresponds to Boolean false (0) state.
means to establish logic level one on the bit or bits.
means to establish logic level zero on the bit or bits.
means least significant bit or bits.
means most significant bit or bits.
means that a signal is in active logic state. An active low signal changes from logic
level one to logic level zero when asserted, and an active high signal changes from
logic level zero to logic level one.
means that an asserted signal changes logic state. An active low signal changes
from logic level zero to logic level one when negated, and an active high signal
changes from logic level one to logic level zero.
Notational Conventions
Table i contains notational conventions that are used in this document.
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Table i. Notational Conventions
Symbol
Function
+
Addition
–
Subtraction (two’s complement) or negation
*
Multiplication
/
Division
>
Greater
<
Less
=
Equal
≥
Equal or greater
≤
Equal or less
≠
Not equal
•
AND
|
Inclusive OR (OR)
⊕
Exclusive OR (EOR)
NOT
Complementation
:
Concatenation
?
Transferred
⇔
Exchanges
±
Sign bit; also used to show tolerance
«
Sign extension
Acronyms and Abbreviations
Table ii contains acronyms and abbreviations that are used in this document.
Table ii. Acronyms and Abbreviated Terms
Term
Meaning
ALU
Arithmetic logic unit
BIST
Built-in self test
BIU
Bus interface unit
BPU
Branch processing unit
BSDL
Boundary-scan description language
CMOS
Complementary metal-oxide semiconductor
EA
Effective address
EAR
External access register
FIFO
First-in-first-out
FPR
Floating-point register
FPSCR
Floating-point status and control register
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Table ii. Acronyms and Abbreviated Terms (continued)
Term
Meaning
FPU
Floating-point unit
GPR
General-purpose register
IABR
Instruction address breakpoint register
IEEE
Institute for Electrical and Electronics Engineers
IU
Integer unit
JTAG
Joint Test Action Group
LIFO
Last-in-first-out
LR
Link register
LSB
Least-significant bit
LSU
Load/store unit
MSB
Most-significant bit
MSR
Machine state register
NaN
Not a number
No-op
No operation
OEA
Operating environment architecture
PLL
Phase-locked loop
POR
Power-on reset
PVR
Processor version register
RISC
Reduced instruction set computing
SPR
Special-purpose register
SRR0
Machine status save/restore register 0
SRR1
Machine status save/restore register 1
TB
Time base facility
TBL
Time base lower register
TBU
Time base upper register
TLB
Translation lookaside buffer
TTL
Transistor-to-transistor logic
UIMM
Unsigned immediate value
UISA
User instruction set architecture
VEA
Virtual environment architecture
XER
Register used for indicating conditions such as carries and overflows for integer operations
References
The Sematech Official Dictionary and the Reference Guide to Letter Symbols for Semiconductor Devices
by the JEDEC Council/Electronics Industries Association are recommended as references for terminology
and symbology.
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Chapter 1
Overview
This chapter provides an overview of the MPC561/MPC563 microcontrollers, including a block diagram
showing the major modular components and sections that list the major features, and differences between
the MPC561/MPC563 and the MPC555. The MPC561, MPC562, MPC563, and MPC564 devices are
members of the Freescale MPC500 RISC Microcontroller family. The parts herein will be referred to only
as MPC561/MPC563 unless specific parts need to be referenced.
Table 1-1. MPC56x Family Features
1.1
Device
Flash
Code Compression
MPC561
None
Not Supported
MPC562
None
Supported
MPC563
512-Kbytes Flash
Not Supported
MPC564
512-Kbytes Flash
Supported
Introduction
The MPC561/MPC563 devices offer the following features:
• PowerPC ISA-compliant 32-bit single issue RISC processor (RCPU)
• 64-bit floating-point unit (FPU)
• Unified system integration unit (USIU) with a flexible memory controller and enhanced interrupt
controller (EIC)
• 512-Kbytes of Flash EEPROM memory (available on the MPC563 only)
— Typical endurance of 100,000 write/erase cycles @ 25ºC
— Typical data retention of 100 years @ 25ºC
• 32-Kbytes of static RAM in one CALRAM module, configured as
— 28-Kbyte normal access only array
— 4-Kbyte normal access or overlay access array (eight 512-byte regions)
• Two time processing units (TPU3) with one 8-Kbyte dual port TPU RAM (DPTRAM)
• One 22-timer channel modular I/O system (MIOS14)
• Three TouCAN modules (TouCAN)
• Two enhanced queued analog systems (QADC64E)
• One queued serial multi-channel module (QSMCM), which contains one queued serial peripheral
interface (QSPI) and two serial controller interfaces (SCI/UART)
• One peripheral pin multiplexing module (PPM) with a parallel to serial driver
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Overview
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1.2
Debug features:
— Nexus debug port (Class 3)
— Background debug mode (BDM)
— IEEE 1194.1-compliant interface (JTAG) for boundary scan
Plastic ball grid array (PBGA) packaging
— 388 ball PBGA
— 27 mm x 27 mm body size
— 1.0 mm ball pitch
Default 40-, and optional 56-, and 66-MHz operation
-40°C–125°C
Independent power supplies
— 5-V I/O (5.0 ± 0.25 V)
— 2.6 ± 0.1-V external bus with a 5-V tolerant I/O system
— 2.6 ± 0.1-V internal logic
— SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) > (frB).
2
Equal, floating-point equal (EQ, FE).
For integer compare instructions, (rA) = SIMM, UIMM, or (rB).
For floating-point compare instructions, (frA) = (frB).
3
Summary overflow, floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the
instruction. For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN).
Here, the bit indicates the bit number in any one of the four-bit subfields, CR0–CR7
3.7.5
Integer Exception Register (XER)
The integer exception register (XER), SPR 1, is a user-level, 32-bit register.
MSB
0
LSB
1
2
3
4
Field SO OV CA
Reset
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
—
Unchanged
Addr
5
31
BYTES
00_0000_0000_0000_0000_0
Unchanged
SPR 1
Figure 3-8. Integer Exception Register (XER)
The bit descriptions for XER, shown in Table 3-10, are based on the operation of an instruction considered
as a whole, not on intermediate results. For example, the result of the subtract from carrying (subfcx)
instruction is specified as the sum of three values. This instruction sets bits in the XER based on the entire
operation, not on an intermediate sum.
In most cases, reserved fields in registers are ignored when written to and return zero when read. However,
XER[16:23] are set to the value written to them and return that value when read.
Table 3-10. Integer Exception Register Bit Descriptions
Bits
Name
Description
0
SO
Summary Overflow (SO). The summary overflow bit is set whenever an instruction sets the
overflow bit (OV) to indicate overflow and remains set until software clears it. It is not altered by
compare instructions or other instructions that cannot overflow.
1
OV
Overflow (OV). The overflow bit is set to indicate that an overflow has occurred during execution
of an instruction. Integer and subtract instructions having OE=1 set OV if the carry out of bit 0 is
not equal to the carry out of bit 1, and clear it otherwise. The OV bit is not altered by compare
instructions or other instructions that cannot overflow.
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Central Processing Unit
Table 3-10. Integer Exception Register Bit Descriptions
Bits
Name
Description
2
CA
Carry (CA). In general, the carry bit is set to indicate that a carry out of bit 0 occurred during
execution of an instruction. Add carrying, subtract from carrying, add extended, and subtract
from extended instructions set CA if there is a carry out of bit 0, and clear it otherwise. The CA
bit is not altered by compare instructions or other instructions that cannot carry, except that shift
right algebraic instructions set the CA bit to indicate whether any ‘1’ bits have been shifted out
of a negative quantity.
3:24
—
Reserved
25:31
BYTES
3.7.6
This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx)
or Store String Word Indexed (stswx) instruction.
Link Register (LR)
The link register (LR), SPR 8, supplies the branch target address for the branch conditional to link register
(bclrx) instruction, and can be used to hold the logical address of the instruction that follows a branch and
link instruction.
Note that although the two least-significant bits can accept any values written to them, they are ignored
when the LR is used as an address.
Both conditional and unconditional branch instructions include the option of placing the effective address
of the instruction after the branch instruction in the LR. This is done regardless of whether the branch is
taken.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
Branch Address
Reset
Unchanged
Addr
SPR 8
31
Figure 3-9. Link Register (LR)
3.7.7
Count Register (CTR)
The count register (CTR), SPR 9, is used to hold a loop count that can be decremented during execution
of branch instructions with an appropriately coded BO field. If the value in CTR is 0 before being
decremented, it is –1 afterward. The count register provides the branch target address for the branch
conditional to count register (bcctrx) instructio
MSB
0
LSB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
Loop Count
Reset
Unchanged
Addr
SPR 9
31
Figure 3-10. Count Register (CTR)
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3.8
VEA Register Set — Time Base (TB)
The virtual environment architecture (VEA) defines registers in addition to the UISA register set. The
VEA register set can be accessed by all software with either user- or supervisor-level privileges. Refer to
Section 6.1.7, “Time Base (TB),” for more information.
3.9
OEA Register Set
The operating environment architecture (OEA) includes a number of SPRs and other registers that are
accessible only by supervisor-level instructions. Some SPRs are RCPU-specific; some RCPU SPRs may
not be implemented in other PowerPC ISA processors, or may not be implemented in the same way.
3.9.1
Machine State Register (MSR)
The machine state register is a 32-bit register that defines the state of the processor. When an exception
occurs, the contents of the MSR are loaded into SRR1, and the MSR is updated to reflect the
exception-processing machine state. The MSR can also be modified by the mtmsr, sc, and rfi instructions.
It can be read by the mfmsr instruction.
11
MSB
0
1
2
3
4
5
Field
6
7
8
9
10
11
12
—
SRESET
13
14
15
POW
0
ILE
0000_0000_0000_0000
LSB
16
Field EE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PR
FP
ME
FE0
SE
BE
FE1
—
IP
IR
DR
—
DCMPEN
RI
LE
1
SRESET
000
U
0000_0
ID12
000
X3
00
Figure 3-11. Machine State Register (MSR)
1
This bit is available only on code compression-enabled options of the MPC561/MPC563.
The reset value is a reset configuration word value extracted from the internal bus line. Refer to Section 7.5.2, “Hard
Reset Configuration Word (RCW).”
3
The reset value is defined by the equation "BBCMCR[EN_COMP] AND BBCMCR[EXC_COMP]". At HRESET the
BBCMCR[EN_COMP] and BBCMCR[EXC_COMP] bits recieve their values from RCW bits 21 and 22. The BBCMCR
does not change at SRESET. Thus the DCMPEN reset value may be different on SRESET and HRESET, if software
changes these BBCMCR bits from their reset values.
2
Table 3-11 shows the bit definitions for the MSR.
Table 3-11. Machine State Register Bit Descriptions
Bits
Name
0:12
—
13
POW
Description
Reserved
Power management enable.
0 Power management disabled (normal operation mode)
1 Power management enabled (reduced power mode)
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Table 3-11. Machine State Register Bit Descriptions (continued)
Bits
Name
Description
14
—
Reserved
15
ILE
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to
select the endian mode for the context established by the exception. Little-endian mode is not
supported on the MPC561/MPC563. This bit should be cleared to 0 at all times.
0 The processor runs in big-endian mode during exception processing.
1 The processor runs in little-endian mode during exception processing.
16
EE
External interrupt enable. Interrupts should only be negated while the EE bit is disabled (0).
Software should disable interrupts (EE = 0) in the RCPU before clearing or masking any
interrupt source from the USIU or external pins. For external interrupts, it is recommended that
the edge-triggered interrupt scheme be used. See Section 6.1.4, “Enhanced Interrupt
Controller.”
0 The processor delays recognition of external interrupts and decrementer exception
conditions.
1 The processor is enabled to take an external interrupt or the decrementer exception.
17
PR
Privilege level.
0 The processor can execute both user- and supervisor-level instructions.
1 The processor can only execute user-level instructions.
18
FP
Floating-point available.
0 The processor prevents dispatch of floating-point instructions, including floating-point loads,
stores and moves. Floating-point enabled program exceptions can still occur and the FPRs
can still be accessed.
1 The processor can execute floating-point instructions, and can take floating-point enabled
exception type program exceptions.
19
ME
Machine check enable.
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
20
FE0
Floating-point exception mode 0 (See Table 3-12.)
21
SE
Single-step trace enable.
0 The processor executes instructions normally.
1 The processor generates a single-step trace exception when the next instruction executes
successfully. When this bit is set, the processor dispatches instructions in strict program
order. Successful execution means the instruction caused no other exception.
22
BE
Branch trace enable.
0 No trace exception occurs when a branch instruction is completed.
1 Trace exception occurs when a branch instruction is completed.
23
FE1
Floating-point exception mode 1 (See Table 3-12).
24
—
Reserved
25
IP
Exception prefix. The setting of this bit specifies the location of the exception vector table.
0 Exception vector table starts at the physical address 0x0000 0000.
1 Exception vector table starts at the physical address 0xFFF0 0000.
26
IR
Instruction relocation.
0 Instruction address translation is off; the BBC IMPU does not check for address permission
attributes.
1 Instruction address translation is on; the BBC IMPU checks for address permission
attributes.
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Table 3-11. Machine State Register Bit Descriptions (continued)
Bits
Name
27
DR
Data relocation.
0 Data address translation is off; the L2U DMPU does not check for address permission
attributes.
1 Data address translation is on; the L2U DMPU checks for addressn permission attributes.
28
—
Reserved
29
Description
DCMPEN Decompression On/Off. The reset value of this bit is (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP]).
Note: This bit should not be set for the MPC561/MPC563.
0 The RCPU runs in normal operation mode.
1 The RCPU runs in compressed mode.
Note: MSR[DCMPEN] should not be changed by software by a direct MSR register write
(MTMSR instruction). It can be changed only by the RFI instruction or by an exception.
30
RI
Recoverable exception (for machine check and non-maskable breakpoint exceptions).
0 Machine state is not recoverable.
1 Machine state is recoverable.
31
LE
Little-endian mode. This mode is not supported on MPC561/MPC563. This bit should be
cleared to 0 at all times.
0 The processor operates in big-endian mode during normal processing.
1 The processor operates in little-endian mode during normal processing.
The floating-point exception mode bits are interpreted as shown in Table 3-12.
Table 3-12. Floating-Point Exception Mode Bits
FE[0:1]
Mode
00
Ignore exceptions mode. Floating-point exceptions do not cause the
floating-point assist error handler to be invoked.
01, 10, 11
3.9.2
Floating-point precise mode. The system floating-point assist error
handler is invoked precisely at the instruction that caused the enabled
exception.
DAE/Source Instruction Service Register (DSISR)
The DSISR, SPR 18, identifies the cause of data access and alignment exceptions.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
DSISR
Reset
Unchanged
Addr
SPR 18
31
Figure 3-12. DAE/Source Instruction Service Register (DSISR)
For more information about bit settings, see Section 3.15.4.2, “Machine Check Exception (0x0200),”
Section 3.15.4.6, “Alignment Exception (0x00600),” and Section 3.15.4.15, “Implementation-Specific
Data Protection Error Exception (0x1400).”
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3.9.3
Data Address Register (DAR)
After an alignment exception, the DAR, SPR 19, is set to the effective address of a load or store element.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
Data Address
Reset
Unchanged
Addr
SPR 19
31
Figure 3-13. Data Address Register (DAR)
3.9.4
Time Base Facility (TB) — OEA
Refer to Section 6.1.7, “Time Base (TB),” for information.
3.9.5
Decrementer Register (DEC)
Refer to Section 6.1.6, “Decrementer (DEC),” for information.
3.9.6
Machine Status Save/Restore Register 0 (SRR0)
The machine status save/restore register 0 (SRR0), SPR 26, identifies where instruction execution should
resume when an rfi instruction is executed following an exception. It also holds the effective address of
the instruction that follows the system call (sc) instruction.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
SRR0
Reset
Undefined
Addr
SPR 26
31
Figure 3-14. Machine Status Save/Restore Register 0 (SRR0)
When an exception occurs, SRR0 is set to point to an instruction such that all prior instructions have
completed execution and no subsequent instruction has begun execution. The instruction addressed by
SRR0 may not have completed execution, depending on the exception type. SRR0 addresses either the
instruction causing the exception or the instruction immediately following. The instruction addressed can
be determined from the exception type and status bits.
3.9.7
Machine Status Save/Restore Register 1 (SRR1)
The machine status save/restore register 1 (SRR1), SPR 27, saves the machine status on exceptions and
restores the machine status when an rfi instruction is executed.
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MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
SRR1
Reset
Undefined
Addr
SPR 27
31
Figure 3-15. Machine Status Save/Restore Register 1 (SRR1)
In general, when an exception occurs, SRR1[0:15] are loaded with exception-specific information, and
MSR[16:31] are placed into SRR1[16:31].
3.9.8
General SPRs (SPRG0–SPRG3)
SPRG0–SPRG3, SPRs 272-275, are provided for general operating system use, such as fast-state saves
and multiprocessor-implementation support. SPRG0–SPRG3 are shown below.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
SPRG0
SPRG1
SPRG2
SPRG3
Reset
Unchanged
Figure 3-16. SPRG0–SPRG3 — General Special-Purpose Registers 0–3
Uses for SPRG0–SPRG3 are shown in Table 3-13.
Table 3-13. Uses of SPRG0–SPRG3
Register
Description
SPRG0
Software may load a unique physical address in this register to identify an area of memory reserved for use
by the exception handler. This area must be unique for each processor in the system.
SPRG1
This register may be used as a scratch register by the exception handler to save the content of a GPR. That
GPR then can be loaded from SPRG0 and used as a base register to save other GPRs to memory.
SPRG2
This register may be used by the operating system as needed.
SPRG3
This register may be used by the operating system as needed.
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3.9.9
Processor Version Register (PVR)
The PVR is a 32-bit, read-only register that identifies the version and revision level of the processor. The
contents of the PVR can be copied to a GPR by the mfspr instruction. Read access to the PVR is available
in supervisor mode only; write access is not provided.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
VERSION
REVISION
Reset
0000_0000_0000_0010
0000_0000_0010_0000
Addr
31
SPR 287
Figure 3-17. Processor Version Register (PVR)
Table 3-14. Processor Version Register Bit Descriptions
Bits
Name
Description
0:15
VERSION
A 16-bit number that identifies the version of the PowerPC ISA processor. The RCPU value
is 0x0002.
16:31
REVISION
A 16-bit number that distinguishes between various releases of a particular version. The
RCPU value is 0x0020.
3.9.10
Implementation-Specific SPRs
The MPC561/MPC563 includes several implementation-specific SPRs that are not defined by the
PowerPC ISA architecture. These registers, listed in Table 3-2 and Table 3-3, can be accessed by
supervisor-level instructions only.
3.9.10.1
EIE, EID, and NRI Special-Purpose Registers
The RCPU includes three implementation-specific SPRs that facilitate the software manipulation of the
MSR[RI] and MSR[EE] bits: External Interrupt Enable (EIE), External Interrupt Disable (EID), and
Non-recoverable Interrupt (NRI). Issuing the mtspr instruction with one of these registers as an operand
causes the RI and EE bits to be set or cleared as shown in Table 3-15.
Table 3-15. EIE, EID, AND NRI Registers
SPR Number
(Decimal)
Mnemonic
MSR[EE]
MSR[RI]
80
EIE
1
1
81
EID
0
1
82
NRI
0
0
A read (mfspr) of any of these locations is treated as an unimplemented instruction, resulting in a software
emulation exception.
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Central Processing Unit
3.9.10.2
Floating-Point Exception Cause Register (FPECR)
The FPECR, SPR 1022, is a supervisor-level internal status and control register used by the user’s
floating-point assist software envelope. It contains four status bits that indicate whether the result of the
operation is tiny and whether any of three source operands are denormalized. In addition, it contains one
control bit to enable or disable SIE mode. This register must not be accessed by user code.
MSB
0
1
2
3
4
5
6
7
8
Field SIE
9
10
11
12
13
14
26
27
28
29
30
15
—
SRESET
0000_0000_0000_0000
LSB
16
17
18
Field
19
20
21
22
23
24
25
—
SRESET
DNC DNB DNA
31
TR
0000_0000_0000_0000
Addr
SPR 1022
Figure 3-18. Floating-Point Exception Cause Register (FPECR)
A listing of FPECR bit settings is shown in Table 3-16.
Table 3-16. FPECR Bit Descriptions
Bits
Name
Description
0
SIE
1:27
—
28
DNC
Source operand C denormalized status bit.
0 Source operand C is not denormalized
1 Source operand C is denormalized
29
DNB
Source operand B denormalized status bit.
0 Source operand B is not denormalized
1 Source operand B is denormalized
30
DNA
Source operand A denormalized status bit.
0 Source operand A is not denormalized
1 Source operand A is denormalized
31
TR
Synchronized ignore exception mode control bit.
0 Disable SIE mode
1 Enable SIE mode
Reserved
Floating-point tiny result.
0 Floating-point result is not tiny
1 Floating-point result is tiny
NOTE
Software must insert a sync instruction before reading the FPECR.
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3.9.10.3
Additional Implementation-Specific Registers
Refer to the following sections for details on additional implementation-specific registers in the
MPC561/MPC563:
• Section 4.6, “BBC Programming Model”
• Section 6.2.2.1.2, “Internal Memory Map Register (IMMR)”
• Section 11.8, “L2U Programming Model”
• Chapter 23, “Development Support”
3.10
Instruction Set
All PowerPC ISA instructions are encoded as single words (32 bits) and are consistent among all
instruction types. The fixed instruction length and consistent format simplify instruction pipelining and
permit efficient decoding to occur in parallel with operand accesses.
The PowerPC ISA instructions are divided into the following categories:
• Integer instructions, which include computational and logical instructions
— Integer arithmetic instructions
— Integer compare instructions
— Integer logical instructions
— Integer rotate and shift instructions
• Floating-point instructions, which include floating-point computational instructions, as well as
instructions that affect the floating-point status and control register (FPSCR)
— Floating-point arithmetic instructions
— Floating-point multiply/add instructions
— Floating-point rounding and conversion instructions
— Floating-point compare instructions
— Floating-point status and control instructions
• Load/store instructions., which include integer and floating-point load and store instructions
— Integer load and store instructions
— Integer load and store multiple instructions
— Floating-point load and store
— Primitives used to construct atomic memory operations (lwarx and stwcx. instructions)
• Flow control instructions, which include branching instructions, condition register logical
instructions, trap instructions, and other instructions that affect the instruction flow
— Branch and trap instructions
— Condition register logical instructions
• Processor control instructions, which are used for synchronizing memory accesses.
— Move to/from SPR instructions
— Move to/from MSR
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— Synchronize
— Instruction synchronize
NOTE
This grouping of the instructions does not indicate which execution unit
executes a particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The
PowerPC ISA architecture uses instructions that are four bytes long and word-aligned. It provides for byte,
half-word, and word operand loads and stores between memory and a set of 32 GPRs.
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register,
modified, and then written back to the target location with distinct instructions.
PowerPC ISA-compliant processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an instruction or by an
asynchronous event. Either kind of exception may cause one of several components of the system software
to be invoked.
3.10.1
Instruction Set Summary
Table 3-17 provides a summary of RCPU instructions. Refer to the RCPU Reference Manual for a detailed
description of the instruction set.
Table 3-17. Instruction Set Summary
Mnemonic
Operand Syntax
Name
add (add. addo addo.)
rD,rA,rB
Add
addc (addc. addco addco.)
rD,rA,rB
Add Carrying
adde (adde. addeo addeo.)
rD,rA,rB
Add Extended
addi
rD,rA,SIMM
Add Immediate
addic
rD,rA,SIMM
Add Immediate Carrying
addic.
rD,rA,SIMM
Add Immediate Carrying and Record
addis
rD,rA,SIMM
Add Immediate Shifted
addme (addme. addmeo addmeo.)
rD,rA
Add to Minus One Extended
addze (addze. addzeo addzeo.)
rD,rA
Add to Zero Extended
and (and.)
rA,rS,rB
AND
andc (andc.)
rA,rS,rB
AND with Complement
andi.
rA,rS,UIMM
AND Immediate
andis.
rA,rS,UIMM
AND Immediate Shifted
b (ba bl bla)
target_addr
Branch
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Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
bc (bca bcl bcla)
BO,BI,target_addr
Branch Conditional
bcctr (bcctrl)
BO,BI
Branch Conditional to Count Register
bclr (bclrl)
BO,BI
Branch Conditional to Link Register
cmp
crfD,L,rA,rB
Compare
cmpi
crfD,L,rA,SIMM
Compare Immediate
cmpl
crfD,L,rA,rB
Compare Logical
cmpli
crfD,L,rA,UIMM
Compare Logical Immediate
cntlzw (cntlzw.)
rA,rS
Count Leading Zeros Word
crand
crbD,crbA,crbB
Condition Register AND
crandc
crbD,crbA, crbB
Condition Register AND with Complement
creqv
crbD,crbA, crbB
Condition Register Equivalent
crnand
crbD,crbA,crbB
Condition Register NAND
crnor
crbD,crbA,crbB
Condition Register NOR
cror
crbD,crbA,crbB
Condition Register OR
crorc
crbD,crbA, crbB
Condition Register OR with Complement
crxor
crbD,crbA,crbB
Condition Register XOR
divw (divw. divwo divwo.)
rD,rA,rB
Divide Word
divwu divwu. divwuo divwuo.
rD,rA,rB
Divide Word Unsigned
eieio
—
Enforce In-Order Execution of I/O
eqv (eqv.)
rA,rS,rB
Equivalent
extsb (extsb.)
rA,rS
Extend Sign Byte
extsh (extsh.)
rA,rS
Extend Sign Half Word
fabs (fabs.)
frD,frB
Floating Absolute Value
fadd (fadd.)
frD,frA,frB
Floating Add (Double-Precision)
fadds (fadds.)
frD,frA,frB
Floating Add Single
fcmpo
crfD,frA,frB
Floating Compare Ordered
fcmpu
crfD,frA,frB
Floating Compare Unordered
fctiw (fctiw.)
frD,frB
Floating Convert to Integer Word
fctiwz (fctiwz.)
frD,frB
Floating Convert to Integer Word with Round
Toward Zero
fdiv (fdiv.)
frD,frA,frB
Floating Divide (Double-Precision)
fdivs (fdivs.)
frD,frA,frB
Floating Divide Single
fmadd (fmadd.)
frD,frA,frC,frB
Floating Multiply-Add (Double-Precision)
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Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
fmadds (fmadds.)
frD,frA,frC,frB
Floating Multiply-Add Single
fmr (fmr.)
frD,frB
Floating Move Register
fmsub (fmsub.)
frD,frA,frC,frB
Floating Multiply-Subtract (Double-Precision)
fmsubs (fmsubs.)
frD,frA,frC,frB
Floating Multiply-Subtract Single
fmul (fmul.)
frD,frA,frC
Floating Multiply (Double-Precision)
fmuls (fmuls.)
frD,frA,frC
Floating Multiply Single
fnabs (fnabs.)
frD,frB
Floating Negative Absolute Value
fneg (fneg.)
frD,frB
Floating Negate
fnmadd (fnmadd.)
frD,frA,frC,frB
Floating Negative Multiply-Add (DoublePrecision)
fnmadds (fnmadds.)
frD,frA,frC,frB
Floating Negative Multiply-Add Single
fnmsub (fnmsub.)
frD,frA,frC,frB
Floating Negative Multiply-Subtract
(Double-Precision)
fnmsubs (fnmsubs.)
frD,frA,frC,frB
Floating Negative Multiply-Subtract Single
frsp (frsp.)
frD,frB
Floating Round to Single
fsub (fsub.)
frD,frA,frB
Floating Subtract (Double-Precision)
fsubs (fsubs.)
frD,frA,frB
Floating Subtract Single
isync
—
Instruction Synchronize
lbz
rD,d(rA)
Load Byte and Zero
lbzu
rD,d(rA)
Load Byte and Zero with Update
lbzux
rD,rA,rB
Load Byte and Zero with Update Indexed
lbzx
rD,rA,rB
Load Byte and Zero Indexed
lfd
frD,d(rA)
Load Floating-Point Double
lfdu
frD,d(rA)
Load Floating-Point Double with Update
lfdux
frD,rA,rB
Load Floating-Point Double with Update
Indexed
lfdx
frD,rA,rB
Load Floating-Point Double Indexed
lfs
frD,d(rA)
Load Floating-Point Single
lfsu
frD,d(rA)
Load Floating-Point Single with Update
lfsux
frD,rA,rB
Load Floating-Point Single with Update Indexed
lfsx
frD,rA,rB
Load Floating-Point Single Indexed
lha
rD,d(rA)
Load Half-Word Algebraic
lhau
rD,d(rA)
Load Half-Word Algebraic with Update
lhaux
rD,rA,rB
Load Half-Word Algebraic with Update Indexed
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Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
lhax
rD,rA,rB
Load Half-Word Algebraic Indexed
lhbrx
rD,rA,rB
Load Half-Word Byte-Reverse Indexed
lhz
rD,d(rA)
Load Half-Word and Zero
lhzu
rD,d(rA)
Load Half-Word and Zero with Update
lhzux
rD,rA,rB
Load Hal-Word and Zero with Update Indexed
lhzx
rD,rA,rB
Load Half-Word and Zero Indexed
lmw
rD,d(rA)
Load Multiple Word
lswi
rD,rA,NB
Load String Word Immediate
lswx
rD,rA,rB
Load String Word Indexed
lwarx
rD,rA,rB
Load Word and Reserve Indexed
lwbrx
rD,rA,rB
Load Word Byte-Reverse Indexed
lwz
rD,d(rA)
Load Word and Zero
lwzu
rD,d(rA)
Load Word and Zero with Update
lwzux
rD,rA,rB
Load Word and Zero with Update Indexed
lwzx
rD,rA,rB
Load Word and Zero Indexed
mcrf
crfD,crfS
Move Condition Register Field
mcrfs
crfD,crfS
Move to Condition Register from FPSCR
mcrxr
crfD
Move to Condition Register from XER
mfcr
rD
Move from Condition Register
mffs (mffs.)
frD
Move from FPSCR
mfmsr
rD
Move from Machine State Register
mfspr
rD,SPR
Move from Special Purpose Register
mftb
rD, TBR
Move from Time Base
mtcrf
CRM,rS
Move to Condition Register Fields
mtfsb0 (mtfsb0.)
crbD
Move to FPSCR Bit 0
mtfsb1 (mtfsb1.)
crbD
Move to FPSCR Bit 1
mtfsf (mtfsf.)
FM,frB
Move to FPSCR Fields
mtfsfi (mtfsfi.)
crfD,IMM
Move to FPSCR Field Immediate
mtmsr
rS
Move to Machine State Register
mtspr
SPR,rS
Move to Special Purpose Register
mulhw (mulhw.)
rD,rA,rB
Multiply High Word
mulhwu (mulhwu.)
rD,rA,rB
Multiply High Word Unsigned
mulli
rD,rA,SIMM
Multiply Low Immediate
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Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
mullw (mullw. mullwo mullwo.)
rD,rA,rB
Multiply Low
nand (nand.)
rA,rS,rB
NAND
neg (neg. nego nego.)
rD,rA
Negate
nor (nor.)
rA,rS,rB
NOR
or (or.)
rA,rS,rB
OR
orc
rA,rS,rB
OR with Complement
ori
rA,rS,UIMM
OR Immediate
oris
rA,rS,UIMM
OR Immediate Shifted
(orc.)
rfi
—
Return from Interrupt
rlwimi (rlwimi.)
rA,rS,SH,MB,ME
Rotate Left Word Immediate then Mask Insert
rlwinm (rlwinm.)
rA,rS,SH,MB,ME
Rotate Left Word Immediate then AND with
Mask
rlwnm (rlwnm.)
rA,rS,rB,MB,ME
Rotate Left Word then AND with Mask
sc
—
System Call
slw (slw.)
rA,rS,rB
Shift Left Word
sraw (sraw.)
rA,rS,rB
Shift Right Algebraic Word
srawi (srawi.)
rA,rS,SH
Shift Right Algebraic Word Immediate
srw (srw.)
rA,rS,rB
Shift Right Word
stb
rS,d(rA)
Store Byte
stbu
rS,d(rA)
Store Byte with Update
stbux
rS,rA,rB
Store Byte with Update Indexed
stbx
rS,rA,rB
Store Byte Indexed
stfd
frS,d(rA)
Store Floating-Point Double
stfdu
frS,d(rA)
Store Floating-Point Double with Update
stfdux
frS,rB
Store Floating-Point Double with Update
Indexed
stfdx
frS,rB
Store Floating-Point Double Indexed
stfiwx
frS,rB
Store Floating-Point as Integer Word Indexed
stfs
frS,d(rA)
Store Floating-Point Single
stfsu
frS,d(rA)
Store Floating-Point Single with Update
stfsux
frS,rB
Store Floating-Point Single with Update Indexed
stfsx
frS,r B
Store Floating-Point Single Indexed
sth
rS,d(rA)
Store Half-Word
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Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
sthbrx
rS,rA,rB
Store Half-Word Byte-Reverse Indexed
sthu
rS,d(rA)
Store Half-Word with Update
sthux
rS,rA,rB
Store Half-Word with Update Indexed
sthx
rS,rA,rB
Store Half-Word Indexed
stmw
rS,d(rA)
Store Multiple Word
stswi
rS,rA,NB
Store String Word Immediate
stswx
rS,rA,rB
Store String Word Indexed
stw
rS,d(rA)
Store Word
stwbrx
rS,rA,rB
Store Word Byte-Reverse Indexed
stwcx.
rS,rA,rB
Store Word Conditional Indexed
stwu
rS,d(rA)
Store Word with Update
stwux
rS,rA,rB
Store Word with Update Indexed
stwx
rS,rA,rB
Store Word Indexed
subf (subf. subfo subfo.)
rD,rA,rB
Subtract From
subfc (subfc. subfco subfco.)
rD,rA,rB
Subtract from Carrying
subfe (subfe. subfeo subfeo.)
rD,rA,rB
Subtract from Extended
subfic
rD,rA,SIMM
Subtract from Immediate Carrying
subfme (subfme. subfmeo subfmeo.)
rD,rA
Subtract from Minus One Extended
subfze (subfze. subfzeo subfzeo.)
rD,rA
Subtract from Zero Extended
sync
—
Synchronize
tw
TO,rA,rB
Trap Word
twi
TO,rA,SIMM
Trap Word Immediate
xor (xor.)
rA,rS,rB
XOR
xori
rA,rS,UIMM
XOR Immediate
xoris
rA,rS,UIMM
XOR Immediate Shifted
Note: The dot (.) suffix on a mnemonic indicates that the CR register update is enabled. The o suffix on a mnemonic indicates
that the overflow bit update in the XER is enabled.
3.10.2
Recommended Simplified Mnemonics
To simplify assembly language coding, a set of alternative mnemonics is provided for some frequently
used operations (such as no-op, load immediate, load address, move register, and complement register).
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For a complete list of simplified mnemonics, see the RCPU Reference Manual. Programs written to be
portable across the various assemblers for the PowerPC ISA architecture should not assume the existence
of mnemonics not described in that manual.
3.10.3
Calculating Effective Addresses
The effective address (EA) is the 32-bit address computed by the processor when executing a memory
access or branch instruction or when fetching the next sequential instruction.
The PowerPC ISA architecture supports two simple memory addressing modes:
• EA = (rA|0) + 16-bit offset (including offset = 0) (register indirect with immediate index)
• EA = (rA|0) + rB (register indirect with index)
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the
effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address, the storage operand is considered to wrap around from the maximum effective
address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned binary
arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
3.11
Exception Model
The PowerPC ISA exception mechanism allows the processor to change to supervisor state as a result of
external signals, errors, or unusual conditions that arise in the execution of instructions. When exceptions
occur, information about the state of the processor is saved to certain registers, and the processor begins
execution at an address (exception vector) predetermined for each exception. Processing of exceptions
occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition
may be determined by examining a register associated with the exception — for example, the DAE/source
instruction service register (DSISR). Additionally, some exception conditions can be explicitly enabled or
disabled by software.
The PowerPC ISA architecture requires that exceptions be taken in program order; therefore, although a
particular implementation may recognize exception conditions out of order, they are handled strictly in
order with respect to the instruction stream. When an instruction-caused exception is recognized, any
unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered
the execute state, are required to complete before the exception is taken. For example, if a single
instruction encounters multiple exception conditions, those exceptions are taken and handled sequentially.
Likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not
handled until all instructions currently in the execute stage successfully complete execution and report
their results.
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Note that exceptions can occur while an exception handler routine is executing, and multiple exceptions
can become nested. It is up to the exception handler to save the appropriate machine state if it is desired
that control be returned to the excepting program.
In many cases, after the exception handler handles an exception, there is an attempt to execute the
instruction that caused the exception. Instruction execution continues until the next exception condition is
encountered. This method of recognizing and handling exception conditions sequentially guarantees that
the machine state is recoverable and processing can resume without losing instruction results.
To prevent the loss of state information, exception handlers must save the information stored in SRR0 and
SRR1 soon after the exception is taken to prevent this information from being lost due to another exception
being taken.
3.11.1
Exception Classes
The RCPU exception classes are shown in Table 3-18.
Table 3-18. RCPU Exception Classes
3.11.2
Class
Exception Type
Asynchronous, unordered
Machine check
System reset
Asynchronous, ordered
External interrupt
Decrementer
Synchronous (ordered, precise)
Instruction-caused exceptions
Ordered Exceptions
In the RCPU, all exceptions except for reset, debug port non-maskable interrupts, and machine check
exceptions are ordered. Ordered exceptions satisfy the following criteria:
• Only one exception is reported at a time. If, for example, a single instruction encounters multiple
exception conditions, those conditions are encountered sequentially. After the exception handler
handles an exception, instruction execution continues until the next exception condition is
encountered.
• When the exception is taken, no program state is lost.
3.11.3
Unordered Exceptions
Unordered exceptions may be reported at any time and are not guaranteed to preserve program state
information. The processor can never recover from a reset exception. It can recover from other unordered
exceptions in most cases. However, if a debug port non-maskable interrupt or machine check exception
occurs during the servicing of a previous exception, the machine state information in SRR0 and SRR1
(and, in some cases, the DAR and DSISR) may not be recoverable; the processor may be in the process of
saving or restoring these registers.
To determine whether the machine state is recoverable, the RI (recoverable exception) bit in SRR1 can be
read. During exception processing, the RI bit in the MSR is copied to SRR1 and then cleared. The
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operating system should set the RI bit in the MSR at the end of each exception handler’s prologue (after
saving the program state) and clear the bit at the start of each exception handler’s epilogue (before
restoring the program state). Then, if an unordered exception occurs during the servicing of an exception
handler, the RI bit in SRR1 will contain the correct value.
3.11.4
Precise Exceptions
In the RCPU, all synchronous (instruction-caused) exceptions are precise. When a precise exception
occurs, the processor backs the machine up to the instruction causing the exception. This ensures that the
machine is in its correct architecturally-defined state. The following conditions exist at the point a precise
exception occurs:
1. Architecturally, no instruction following the faulting instruction in the code stream has begun
execution.
2. All instructions preceding the faulting instruction appear to have completed with respect to the
executing processor.
3. SRR0 addresses either the instruction causing the exception or the immediately following
instruction. Which instruction is addressed can be determined from the exception type and the
status bits.
4. Depending on the type of exception, the instruction causing the exception may not have begun
execution, may have partially completed, or may have completed execution.
3.11.5
Exception Vector Table
The setting of the exception prefix (IP) bit in the MSR determines how exceptions are vectored. If the bit
is cleared, the exception vector table begins at the physical address 0x0000 0000; if IP is set, the exception
vector table begins at the physical address 0xFFF0 0000. Table 3-19 shows the exception vector offset of
the first instruction of the exception handler routine for each exception type.
NOTE
In the MPC561/MPC563, the exception table can additionally be relocated
by the BBC module to internal memory and reduce the total size required by
the exception table (see Section 4.3, “Exception Table Relocation (ETR).”
Table 3-19. Exception Vector Offset Table
Vector Offset
(hex)
Exception Type
Section
00000
Reserved
—
00100
System reset, NMI interrupt
Section 3.15.4.1, “System Reset Exception and NMI (0x0100)”
00200
Machine Check
Section 3.15.4.2, “Machine Check Exception (0x0200)”
00300
Data Storage
Section 3.15.4.3, “Data Storage Exception (0x0300)”
00400
Reserved
Instruction Storage1
00500
External Interrupt
Section 3.15.4.5, “External Interrupt (0x0500)”
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Table 3-19. Exception Vector Offset Table (continued)
1
Vector Offset
(hex)
Exception Type
Section
00600
Alignment
Section 3.15.4.6, “Alignment Exception (0x00600)”
00700
Program
Section 3.15.4.7, “Program Exception (0x0700)”
00800
Floating-Point Unavailable
Section 3.15.4.8, “Floating-Point Unavailable Exception
(0x0800)”
00900
Decrementer
Section 3.15.4.9, “Decrementer Exception (0x0900)”
00A00
Reserved
—
00B00
Reserved
—
00C00
System call
Section 3.15.4.10, “System Call Exception (0x0C00)”
00D00
Trace.
Section 3.15.4.11, “Trace Exception (0x0D00)”
00E00
Floating-Point Assist
Section 3.15.4.12, “Floating-Point Assist Exception (0x0E00)”
01000
Implementation-Dependent
Software Emulation
Section 3.15.4.13, “Implementation-Dependent Software
Emulation Exception (0x1000)”
01100
Reserved
—
01200
Reserved
—
01300
Implementation-Dependent
Instruction
Protection Exception
Section 3.15.4.14, “Implementation-Dependent Instruction
Protection Exception (0x1300)”
01400
Implementation-Dependent Data
Protection Error
Section 3.15.4.15, “Implementation-Specific Data Protection
Error Exception (0x1400)”
01500–01BFF
Reserved
—
01C00
Implementation-Dependent
Data Breakpoint
Section 3.15.4.16, “Implementation-Dependent Debug
Exceptions”
01D00
Implementation-Dependent
Instruction Breakpoint
Section 3.15.4.16, “Implementation-Dependent Debug
Exceptions”
01E00
Implementation-Dependent
Maskable
External Breakpoint
Section 3.15.4.16, “Implementation-Dependent Debug
Exceptions”
01F00
Implementation-Dependent
Non-Maskable External Breakpoint
Section 3.15.4.16, “Implementation-Dependent Debug
Exceptions”
This exception will not be generated by hardware.
3.12
Instruction Timing
The RCPU processor is pipelined. Because the processing of an instruction is broken into a series of stages,
an instruction does not require the processor’s full resources.
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The instruction pipeline in the MPC561/MPC563 has four stages:
1. The dispatch stage is implemented using a distributed mechanism. The central dispatch unit
broadcasts the instruction to all units. In addition, scoreboard information (regarding data
dependencies) is broadcast to each execution unit. Each execution unit decodes the instruction. If
the instruction is not implemented, a program exception is taken. If the instruction is legal and no
data dependency is found, the instruction is accepted by the appropriate execution unit, and the data
found in the destination register is copied to the history buffer. If a data dependency exists, the
machine is stalled until the dependency is resolved.
2. In the execute stage, each execution unit that has an executable instruction executes the instruction.
(For some instructions, this occurs over multiple cycles.)
3. In the writeback stage, the execution unit writes the result to the destination register and reports to
the history buffer that the instruction is completed.
4. In the retirement stage, the history buffer retires instructions in architectural order. An instruction
retires from the machine if it completes execution with no exceptions and if all instructions
preceding it in the instruction stream have finished execution with no exceptions. As many as six
instructions can be retired in one clock.
The history buffer maintains the correct architectural machine state. An exception is taken only when the
instruction is ready to be retired from the machine (i.e., after all previously-issued instructions have
already been retired from the machine). When an exception is taken, all instructions following the
excepting instruction are canceled, (i.e., the values of the affected destination registers are restored using
the values saved in the history buffer during the dispatch stage).
Figure 3-19 shows basic instruction pipeline timing.
FETCH
i1
i2
DECODE
i3
i1
i2
READ AND EXECUTE
i1
i2
i1
WRITE BACK (TO DEST REG)
L ADDRESS DRIVE
i2
i1
store
L DATA
LOAD WRITE BACK
BRANCH DECODE
BRANCH EXECUTE
load
i1
i1
i1
Figure 3-19. Basic Instruction Pipeline
Table 3-20 indicates the latency and blockage for each type of instruction. Latency refers to the interval
from the time an instruction begins execution until it produces a result that is available for use by a
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subsequent instruction. Blockage refers to the interval from the time an instruction begins execution until
its execution unit is available for a subsequent instruction.
NOTE
When the blockage equals the latency, it is not possible to issue another
instruction to the same unit in the same cycle in which the first instruction
is being written back.
Table 3-20. Instruction Latency and Blockage
1
3.13
3.13.1
Instruction Type
Precision
Latency
Blockage
Floating-point
multiply-add
Double
Single
7
6
7
6
Floating-point
add or subtract
Double
Single
4
4
4
4
Floating-point multiply
Double
Single
5
4
5
4
Floating-point divide
Double
Single
17
10
17
10
Integer multiply
—
2
1 or 21
Integer divide
—
2 to 111
2 to 111
Integer load/store
—
See note1
See note1
Refer to Section 7, “Instruction Timing,” in the RCPU Reference Manual
(RCPURM/AD) for details.
User Instruction Set Architecture (UISA)
Computation Modes
The RCPU is a 32-bit implementation of the PowerPC ISA architecture. Any reference in the PowerPC
ISA architecture books (UISA, VEA, OEA) regarding 64-bit implementations are not supported by the
core. All registers except the floating-point registers are 32 bits wide.
3.13.2
Reserved Fields
Reserved fields in instructions are described under the specific instruction definition sections. Unless
otherwise noted, reserved fields should be written with a zero when written and return a zero when read.
Thus, this type of invalid form instructions yield results of the defined instructions with the appropriate
field zero.
In most cases, the reserved fields in registers are ignored on write and return zeros for them on read on any
control register implemented by the MPC561/MPC563. Exception to this rule are bits [16:23] of the
fixed-point exception cause register (XER) and the reserved bits of the machine state register (MSR),
which are set by the source value on write and return the value last set for it on read.
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3.13.3
Classes of Instructions
Non-optional instructions are implemented by the hardware. Optional instructions are executed by
implementation-dependent code and any attempt to execute one of these commands causes the RCPU to
take the implementation-dependent software emulation interrupt (offset 0x01000 of the vector table).
Illegal and reserved instruction class instructions are supported by implementation- dependent code and,
thus, the RCPU hardware generates the implementation-dependent software emulation interrupt. Invalid
and preferred instruction forms treatment by the RCPU is described under the specific processor
compliance sections.
3.13.4
Exceptions
Invocation of the system software for any instruction-caused exception in the RCPU is precise, regardless
of the type and setting.
3.13.5
Branch Processor
The RCPU implements all the instructions defined for the branch processor in the UISA in the hardware.
3.13.6
Instruction Fetching
The core fetches a number of instructions into its internal buffer (the instruction pre-fetch queue) prior to
execution. If a program modifies the instructions it intends to execute, it should call a system library
program to ensure that the modifications have been made visible to the instruction fetching mechanism
prior to execution of the modified instructions.
3.13.7
Branch Instructions
The core implements all the instructions defined for the branch processor by the UISA in the hardware.
For performance of various instructions, refer to Table 3-20 of this manual.
3.13.7.1
Invalid Branch Instruction Forms
Bits marked with z in the BO encoding definition are discarded by the MPC561/MPC563 decoding. Thus,
these types of invalid form instructions yield results of the defined instructions with the z-bit zero. If the
decrement and test CTR option is specified for the bcctr or bcctrl instructions, the target address of the
branch is the new value of the CTR. Condition is evaluated correctly, including the value of the counter
after decrement.
3.13.7.2
Branch Prediction
The core uses the y bit to predict path for pre-fetch. Prediction is only done for not-ready branch
conditions. No prediction is done for branches to the link or count register if the target address is not ready.
Refer to the RCPU Reference Manual (conditional branch control) for more information.
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3.13.8
3.13.8.1
Fixed-Point Processor
Fixed-Point Instructions
The core implements the following instructions:
• Fixed-point arithmetic instructions
• Fixed-point compare instructions
• Fixed-point trap instructions
• Fixed-point logical instructions
• Fixed-point rotate and shift instructions
• Move to/from system register instructions
All instructions are defined for the fixed-point processor in the UISA in the hardware. For performance of
the various instructions, refer to Table 3-20.
— Move To/From System Register Instructions. Move to/from invalid special registers in which
SPR0 = 1 yields invocation of the privilege instruction error interrupt handler if the processor
is in problem state. For a list of all implemented special registers, refer to Table 3-2, and
Table 3-3.
— Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of the divisions in
the divw[o][.] instruction (0x80000000 ÷ -1, ÷ 0), then the contents of rD are
0x80000000; if Rc =1, the contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is
set to the correct value. If an attempt is made to perform any of the divisions in the divw[o][.]
instruction, ÷ 0. In cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable
for 64-bit implementations. In 32-bit implementations, if L = 1 the instruction form is invalid.
The core ignores this bit and therefore, the behavior when L = 1 is identical to the valid form
instruction with L = 0
3.13.9
3.13.9.1
Floating-Point Processor
General
The RCPU implements all floating-point features as defined in the UISA, including the non-IEEE working
mode. Some features require software assistance. For more information refer to the RCPU Reference
Manual (Floating-point Load Instructions).
3.13.9.2
Optional Instructions
The only optional instruction implemented by RCPU hardware is store floating-point as integer word
indexed (stfiwx). An attempt to execute any other optional instruction causes an implementation
dependent software emulation exception.
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3.13.10 Load/Store Processor
The load/store processor supports all of the 32-bit implementation fixed-point PowerPC ISA load/store
instructions in the hardware.
3.13.10.1 Fixed-Point Load with Update and Store with Update Instructions
For load with update and store with update instructions, when rA = 0, the EA is written into R0. For load
with update instructions, when rA = rD, rA is boundedly undefined.
3.13.10.2 Fixed-Point Load and Store Multiple Instructions
For these types of instructions, EA must be a multiple of four. If it is not, the system alignment error
handler is invoked. For a lmw instruction (if rA is in the range of registers to be loaded), the instruction
completes normally. rA is then loaded from the memory location as follows:
rA ← MEM(EA+(rA-rD)*4, 4)
3.13.10.3 Fixed-Point Load String Instructions
Load string instructions behave the same as load multiple instructions, with respect to invalid format in
which rA is in the range of registers to be loaded. When rA is in range, it is updated from memory.
3.13.10.4 Storage Synchronization Instructions
For these type of instructions, EA must be a multiple of four. If it is not, the system alignment error handler
is invoked.
3.13.10.5 Floating-Point Load and Store With Update Instructions
For Load and Store with update instructions, if rD = 0 then the EA is written into R0.
3.13.10.6 Floating-Point Load Single Instructions
When the operand falls in the range of a single denormalized number, the floating-point assist interrupt
handler is invoked.
Refer to the RCPU Reference Manual (Floating-point Assist For Denormalized Operands) for complete
description of handling denormalized floating-point numbers.
3.13.10.7 Floating-Point Store Single Instructions
When the operand falls in the range of a single denormalized number, the floating-point assist interrupt
handler is invoked.
When the operand is ZERO it is converted to the correct signed ZERO in single-precision format.
When the operand is between the range of single denormalized and double denormalized it is considered
a programming error. The hardware will handle this case as if the operand was single denormalized.
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When the operand falls in the range of double denormalized numbers it is considered a programming error.
The hardware will handle this case as if the operand was ZERO.
The following check is done on the stored operand in order to determine whether it is a denormalized
single-precision operand and invoke the floating-point assist interrupt handler:
(frS[1:11] ≠ 0) AND (frS[1:11]
≤ 896)
Eqn. 3-1
Refer to the RCPU Reference Manual (Floating-Point Assist for Denormalized Operands) for complete
description of handling denormalized floating-point numbers.
3.13.10.8 Optional Instructions
No optional instructions are supported.
3.14
3.14.1
Virtual Environment Architecture (VEA)
Atomic Update Primitives
Both the lwarx and stwcx instructions are implemented according to the PowerPC ISA architecture
requirements. The MPC561/MPC563 does not provide support for snooping an external bus activity
outside the chip. The provision is made to cancel the reservation inside the MPC561/MPC563 by using the
CR and KR input signals. Internal buses are snooped for RCPU accesses, and the reservation mechanism
can be used for multitask single master applications.
3.14.2
Effect of Operand Placement on Performance
The load/store unit hardware supports all of the PowerPC ISA load/store instructions. An optimal
performance is obtained for naturally aligned operands. These accesses result in optimal performance (one
bus cycle) for up to four bytes in size and good performance (two bus cycles) for double precision
floating-point operands. Unaligned operands are supported in hardware and are broken into a series of
aligned transfers. The effect of operand placement on performance is as stated in the VEA, except for the
case of 8-byte operands. In that case, since the RCPU uses a 32-bit wide data bus, the performance is good
rather than optimal.
3.14.3
Storage Control Instructions
The RCPU does not implement the following cache control instructions: icbi, dcbt, dcbi, dcbf, dcbz, dcbst,
and dcbtst .
3.14.4
Instruction Synchronize (isync) Instruction
The isync instruction causes a reflect which waits for all prior instructions to complete and then executes
the next sequential instruction. Any instruction after an isync will see all effects of prior instructions.
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3.14.5
Enforce In-Order Execution of I/O (eieio) Instruction
When executing an eieio instruction, the load/store unit will wait until all previous accesses have
terminated before issuing cycles associated with load/store instructions following the eieio instruction.
3.14.6
Time Base
A description of the time base register may be found in Chapter 6, “System Configuration and Protection,”
and in Chapter 8, “Clocks and Power Control.”
3.15
Operating Environment Architecture (OEA)
The MPC561/MPC563 has an internal memory space that includes memory-mapped control registers and
internal memory used by various modules on the chip. This memory is part of the main memory as seen
by the RCPU and can be accessed by an external system master.
3.15.1
3.15.1.1
Branch Processor Registers
Machine State Register (MSR)
The floating-point exception mode encoding in the RCPU is as shown in Table 3-21.
:
Table 3-21. Floating-Point Exception Mode Encoding
Mode
FE0
FE1
Ignore exceptions
0
0
Precise
0
1
Precise
1
0
Precise
1
1
The SF bit is reserved set to zero. The IP bit initial state after reset is set as programmed by the reset
configuration as specified by the USIU characteristics.
3.15.1.2
Branch Processors Instructions
The RCPU implements all the instructions defined for the branch processor in the UISA in the hardware.
3.15.2
3.15.2.1
•
•
Fixed-Point Processor
Special Purpose Registers
Unsupported Registers — The following registers are not supported by the MPC561/MPC563:
SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U, IBAT2L, IBAT3U, IBAT3L,
DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L, DBAT3U, DBAT3L.
Added Registers — For a list of added special purpose registers, refer to Table 3-2, and Table 3-3.
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3.15.3
Storage Control Instructions
Storage control instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented
by the MPC561/MPC563.
3.15.4
Exceptions
The following paragraphs define the types of OEA exceptions. The exception table vector defines the
offset value by exception type. Refer to Table 3-19.
3.15.4.1
System Reset Exception and NMI (0x0100)
A system reset exception occurs when:
• Any reset signal is asserted: PORESET, HRESET, or SRESET
• An internal reset is requested, such as from the software watchdog timer
Settings caused by reset as shown in Table 3-22.
Table 3-22. Settings Caused by Reset
Register
Setting
MSR
IP depends on internal data bus configuration word; ME is unchanged.
DCMPEN is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP]). All other bits are cleared
SRR0
Undefined
SRR1
Undefined
FPECR
0x0000 0000
ICTRL
0x0000 0000
LCTRL1
0x0000 0000
LCTRL2
0x0000 0000
COUNTA[16:31]
0x0000 0000
COUNTB[16:31]
0x0000 0000
A non-maskable interrupt (NMI) occurs when the IRQ0 is asserted and the following registers are set.
Table 3-23. Register Settings following an NMI
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the next instruction the
processor executes if no interrupt conditions are present
Save/Restore Register 1 (SRR1)
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
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Table 3-23. Register Settings following an NMI (continued)
Register Name
Bits
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Other
1
Description
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the RCPU is in decompression on mode, SRR0 will contain a compressed address.
Execution begins at physical address 0x0100 if the hard reset configuration word IP bit is cleared to 0.
Execution begins at physical address 0xFFF0 0100 if the hard reset configuration word IP bit is set to 1.
3.15.4.2
Machine Check Exception (0x0200)
A machine-check exception is assumed to be caused by one of the following conditions:
• The accessed address does not exist.
• A data error was detected.
• A storage protection violation was detected by chip-select logic.
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When a machine-check exception occurs, the processor does one of the following:
• Takes a machine check exception;
• Enters the checkstop state; or
• Enters debug mode.
Which action is taken depends on the value of the MSR[ME] bit, whether or not debug mode was enabled
at reset, and (if debug mode is enabled) the values of the CHSTPE (checkstop enable) and MCIE (machine
check enable) bits in the debug enable register (DER). Table 3-24 summarizes the possibilities. When the
processor is in the checkstop state, instruction processing is suspended and cannot be restarted without
resetting the core.
Table 3-24. Machine Check Exception Processor Actions
MSR[ME]
Debug Mode
Enable
CHSTPE
MCIE
Action Performed when Exception Detected
0
0
X
X
Enter checkstop state
1
0
X
X
Branch to machine-check exception handler
0
1
0
X
Enter checkstop state
0
1
1
X
Enter debug mode
1
1
X
0
Branch to machine-check exception handler
1
1
X
1
Enter debug mode
An indication is sent to the USIU which may generate an automatic reset in this condition. Refer to
Chapter 7, “Reset,” for more details.
The register settings for machine check exceptions are shown in Table 3-25.
Table 3-25. Register Settings following a Machine Check Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 1 (SRR1)
02
MSR0
1
Set to 1 for instruction fetch-related errors and 0 for
load/store-related errors
2:4
5:9
2
10:15
16:31 2
Cleared to 0
MSR[5:9]
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
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Table 3-25. Register Settings following a Machine Check Exception (continued)
Register Name
Bits
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Data/Storage Interrupt Status
Register (DSISR)3
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Other
Cleared to 0
0:14
Cleared to 0
15:16
Set to bits [29:30] of the instruction if X-form and to 0b00 if
D-form
17
Data Address Register (DAR)3
Description
Set to bit 25 of the instruction if X-form and to Bit 5 if D-form
18:21
Set to bits [21:24] of the instruction if X-form and to bits [1:4] if
D-form
22:31
Set to bits [6:15] of the instruction
All
Set to the effective address of the data access that caused the
interrupt
1
If the exception occurs due to a data error caused by a Load/Store instruction and the processor in Decompression
On mode, the SRR0 register will contain the address of the Load/Store instruction in compressed format. If the
exception occurs due to an instruction fetch in Decompression On mode, the SRR0 register will contain an
indeterminate value.
2 This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in MSR is
loaded from this bit when an RFI is executed.
3 DSISR and DAR registers are only updated when the machine check exception is caused by a data access violation.
when a machine check exception is taken, instruction execution resumes at offset 0x0200 from the base
address indicated by MSR[IP].
3.15.4.3
Data Storage Exception (0x0300)
A data storage exception is never generated by the RCPU. The software may branch to this location as a
result of implementation-specific data storage protection error exception.
3.15.4.4
Instruction Storage Exception (0x0400)
An instruction storage interrupt is never generated by them RCPU. The software may branch to this
location as a result of an implementation-specific instruction storage protection error exception.
3.15.4.5
External Interrupt (0x0500)
The external interrupt exception is taken on assertion of the internal IRQ line to the RCPU, that is driven
by on-chip interrupt controller. The interrupt may be caused by the assertion of an external IRQ signal, by
a USIU timer, or by an internal chip peripheral. Refer to Section 6.1.4, “Enhanced Interrupt Controller,”
for more information on the interrupt controller.
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The interrupt may be delayed by other higher priority exceptions or if the MSR[EE] bit is cleared when
the exception occurs. MSR[EE] is automatically cleared by hardware to disable external interrupts when
any exception is taken.
Upon detecting an external interrupt, the processor assigns it to the instruction at the head of the history
buffer (after retiring all instructions that are ready to retire).
The enhanced interrupt controller mode is available for interrupt-driven applications on
MPC561/MPC563. It allows the single external interrupt exception vector 0x500 to be split into up to 48
different vectors corresponding to 48 interrupt sources to speed up interrupt processing. It also supports a
low priority source masking feature in hardware to handle nested interrupts more easily. See Section 6.1.4,
“Enhanced Interrupt Controller,” and Chapter 4, “Burst Buffer Controller 2 Module.”
The register settings for the external interrupt exception are shown in Table 3-26.
Table 3-26. Register Settings following External Interrupt
Register
Bits
Setting Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that the processor would
have attempted to execute next if no interrupt conditions were present.
Save/Restore Register 1 (SRR1)
[0:15]
Cleared to 0
[16:31]
Loaded from bits [16:31] of MSR. In the current implementation, bit 30
of the SRR1 is never cleared, except by loading a zero value from
MSR[RI]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPE This bit is set according to (BBCMCR[EN_COMP] AND
N
BBCMCR[EXC_COMP])
Other
1
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain an
address in compressed format.
When an external interrupt is taken, instruction execution resumes at offset 0x00500 from the physical
base address indicated by MSR[IP].
3.15.4.6
Alignment Exception (0x00600)
The following conditions cause an alignment exception:
• The operand of a floating-point load or store instruction is not word-aligned.
• The operand of a load or store multiple instruction is not word-aligned.
• The operand of lwarx or stwcx. is not word-aligned.
Alignment exceptions use the SRR0 and SRR1 to save the machine state and the DSISR to determine the
source of the exception.
The register settings for alignment exceptions are shown in Table 3-27.
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Table 3-27. Register Settings for Alignment Exception
Register
Bits
Save/Restore Register 0 (SRR0)1
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Set to the effective address of the instruction that caused the
exception.
[0:15]
Cleared to 0
[16:31]
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Data/Storage Interrupt Status
Register (DSISR)
1
Setting Description
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Other
Cleared to 0
[0:11]
Cleared to 0
[12:13]
Cleared to 0
14
Cleared to 0
[15:16]
For instructions that use register indirect with index addressing,
set to bits [29:30] of the instruction.
For instructions that use register indirect with immediate index
addressing, cleared.
17
For instructions that use register indirect with index addressing,
set to bit 25 of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bit 5 of the instruction.
[18:21]
For instructions that use register indirect with index addressing,
set to bits [21:24] of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bits [1:4] of the instruction.
[22:26]
Set to bits [6:10] (source or destination) of the instruction.
[27:31]
Set to bits [11:15] of the instruction (rA). Set to either bits
[11:15] of the instruction or to any register number not in the
range of registers loaded by a valid form instruction, for lmw,
lswi, and lswx instructions. Otherwise undefined.
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
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NOTE
For load or store instructions that use register indirect with index
addressing, the DSISR can be set to the same value that would have resulted
if the corresponding instruction uses register indirect with immediate index
addressing had caused the exception. Similarly, for load or store instructions
that use register indirect with immediate index addressing, DSISR can hold
a value that would have resulted from an instruction that uses register
indirect with index addressing. (If there is no corresponding instruction, no
alternative value can be specified.)
When an alignment exception is taken, instruction execution resumes at offset 0x00600 from the physical
base address indicated by MSR[IP].
3.15.4.7
Program Exception (0x0700)
A program exception occurs when no higher priority exception exists and one or more of the following
exception conditions, which correspond to bit settings in SRR1, occur during execution of an instruction:
• System floating-point enabled exception — A system floating-point enabled exception is
generated when the following condition is met as a result of a move to FPSCR instruction, move
to MSR (mtmsr) instruction, or return from interrupt (rfi) instruction:
• (MSR[FE0] | MSR[FE1]) and- FPSCR[FEX] = 1.
• Notice that in the RCPU implementation of the PowerPC ISA architecture, a program interrupt is
not generated by a floating-point arithmetic instruction that results in the condition shown above;
a floating-point assist exception is generated instead.
• Privileged instruction — A privileged instruction type program exception is generated by any of
the following conditions:
— The execution of a privileged instruction (mfmsr, mtmsr, or rfi) is attempted and the processor
is operating at the user privilege level (MSR[PR] = 1).
— The execution of mtspr or mfspr where SPR0 = 1 in the instruction encoding (indicating a
supervisor-access register) and MSR[PR] = 1 (indicating the processor is operating at the user
privilege level), provided the SPR instruction field encoding represents either:
— a valid internal-to-the-processor special-purpose register; or
— an external-to-the-processor special-purpose register (either valid or invalid).
• Trap — A trap type program exception is generated when any of the conditions specified in a trap
instruction is met.
The register settings for program exceptions are shown in Table 3-28.
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Table 3-28. Register Settings following Program Exception
Register
Bits
Save/Restore Register 0 (SRR0)1
All
Save/Restore Register 1 (SRR1)2
[0:10]
Machine State Register (MSR)
Setting Description
Contains the effective address of the excepting instruction
Cleared to 0
11
Set for a floating-point enabled program exception; otherwise
cleared.
12
Cleared to 0.
13
Set for a privileged instruction program exception; otherwise
cleared.
14
Set for a trap program exception; otherwise cleared.
15
Cleared to 0 if SRR0 contains the address of the instruction
causing the exception, and set if SRR0 contains the address of
a subsequent instruction.
[16:31]
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Other
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
2
Only one of bits 11, 13, and 14 can be set.
When a program exception is taken, instruction execution resumes at offset 0x0700 from the physical base
address indicated by MSR[IP].
3.15.4.8
Floating-Point Unavailable Exception (0x0800)
A floating-point unavailable exception occurs when no higher priority exception exists, an attempt is made
to execute a floating-point instruction (including floating-point load, store, and move instructions), and the
floating-point available bit in the MSR is disabled, (MSR[FP] = 0).
Table 3-29. Register Settings following a Floating-Point Unavailable Exception
Register
Bits
Setting Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
exception.
Save/Restore Register 1 (SRR1)
[0:15]
Cleared to 0
[16:31]
Loaded from MSR[16:31]
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Table 3-29. Register Settings following a Floating-Point Unavailable Exception (continued)
Register
Bits
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Other
1
Setting Description
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
3.15.4.9
Decrementer Exception (0x0900)
A decrementer exception occurs when no higher priority exception exists, the decrementer register has
completed decrementing, and MSR[EE] = 1. The decrementer exception request is canceled when the
exception is handled. The decrementer register counts down, causing an exception (unless masked) when
passing through zero. The decrementer implementation meets the following requirements:
• Loading a GPR from the decrementer does not affect the decrementer.
• Storing a GPR value to the decrementer replaces the value in the decrementer with the value in the
GPR.
• Whenever bit 0 of the decrementer changes from zero to one, an exception request is signaled. If
multiple decrementer exception requests are received before the first can be reported, only one
exception is reported. The occurrence of a decrementer exception cancels the request.
• If the decrementer is altered by software and if bit 0 is changed from zero to one, an interrupt
request is signaled.
The register settings for the decrementer exception are shown in Table 3-30.
Table 3-30. Register Settings Following a Decrementer Exception
Register
Bits
Setting Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that the processor
would have attempted to execute next if no exception
conditions were present.
Save/Restore Register 1 (SRR1)
[0:15]
Cleared to 0
[16:31]
Loaded from MSR[16:31]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Other
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
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1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
When a decrementer exception is taken, instruction execution resumes at offset 0x0900 from the physical
base address indicated by MSR[IP].
3.15.4.10 System Call Exception (0x0C00)
A system call exception occurs when a system call instruction is executed. The effective address of the
instruction following the sc instruction is placed into SRR0. MSR[16:31] are placed into SRR1[16:31],
and SRR1[0:15] are set to undefined values. Then a system call exception is generated.
The system call instruction is context synchronizing. That is, when a system call exception occurs,
instruction dispatch is halted and the following synchronization is performed:
1. The exception mechanism waits for all instructions in execution to complete to a point where they
report all exceptions they will cause.
2. The processor ensures that all instructions in execution complete in the context in which they began
execution.
3. Instructions dispatched after the exception is processed are fetched and executed in the context
established by the exception mechanism.
Register settings are shown in Table 3-31.
Table 3-31. Register Settings following a System Call Exception
Register
Setting Description
1
Save/Restore Register 0 (SRR0)
All
Save/Restore Register 1 (SRR1)
[0:15]
Undefined
[16:31]
Loaded from MSR[16:31]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Other
1
Set to the effective address of the instruction following the
System Call instruction
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the exception occurs during a data access in Decompression On mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format. If the exception occurs during an instruction fetch in
decompression on mode, the SRR0 register will contain an indeterminate value.
When a system call exception is taken, instruction execution resumes at offset 0x00C00 from the physical
base address indicated by MSR[IP].
3.15.4.11 Trace Exception (0x0D00)
A trace interrupt occurs if MSR[SE] = 1 and any instruction except rfi is successfully completed or
MSR[BE]= 1 and a branch is completed. Notice that the trace interrupt does not occur after an instruction
that caused an interrupt (for instance, sc). Monitor/debugger software must change the vectors of other
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possible interrupt addresses to single-step such instructions. If this is unacceptable, other debug features
can be used. Refer to Chapter 23, “Development Support,” for more information. See Table 3-32 for Trace
Exception register settings.
Table 3-32. Register Settings following a Trace Exception
Register Name
Bits
Save/Restore Register 0 (SRR0)
All
Set to the effective address of the instruction following the
executed instruction
Save/Restore Register 1 (SRR1)
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Other
1
Description
1
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Execution resumes at offset 0x0D00 from the base address indicated by MSR[IP].
3.15.4.12 Floating-Point Assist Exception (0x0E00)
A floating point assist exception occurs when the following conditions are true:
• A floating-point enabled exception condition is detected;
• The corresponding floating-point enable bit in the FPSCR (floating point status and control
register) is set (exception enabled); and
• MSR[FE0] | MSR[FE1] = 1
These conditions are summarized in the following equation:
(MSR[FE0] | MSR[FE1]) AND FPSCR[FEX] = 1
Note that when ((MSR[FE0] | MSR[FE1]) AND FPSCR[FEX]) is set as a result of move to FPSCR, move
to MSR or rfi, a program exception is generated, rather than a floating-point assist exception.
A floating point assist exception also occurs when a tiny result is detected and the floating point underflow
exception is disabled (FPSCR[UE] = 0).
The register settings for floating-point assist exceptions are shown in Table 3-33.
Table 3-33. Register Settings following Floating-Point Assist Exceptions
Register Name
1
Save/Restore Register 0 (SRR0)
Bits
Description
All
Set to the effective address of the instruction that caused the
interrupt
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Table 3-33. Register Settings following Floating-Point Assist Exceptions
Register Name
Bits
Description
Save/Restore Register 1 (SRR1)
1:4
10:15
Other
Machine State Register (MSR)
IP
ME
LE
DCMPEN
Cleared to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
Other
1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
When a floating-point exception is taken, instruction execution resumes at offset 0x0E00 from the base
address indicated by MSR[IP].
3.15.4.13 Implementation-Dependent Software Emulation Exception (0x1000)
An implementation-dependent software emulation exception occurs in the following instances:
• When executing any non-implemented instruction. This includes all illegal and unimplemented
optional instructions and all floating-point instructions.
• When executing a mtspr or mfspr instruction that specifies an un-implemented
internal-to-the-processor SPR, regardless of the value of bit 0 of the SPR.
• When executing a mtspr or mfspr that specifies an un-implemented external-to-the-processor
register and SPR0 = 0 or MSR[PR] = 0 (no program interrupt condition).
Table 3-34 shows the register settings set when a software emulation exception occurs.
Table 3-34. Register Settings following a Software Emulation Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 1 (SRR1)
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
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Table 3-34. Register Settings following a Software Emulation Exception
Register Name
Bits
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Other
1
Description
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Execution resumes at offset 0x01000 from the base address indicated by MSR[IP].
3.15.4.14 Implementation-Dependent Instruction Protection Exception (0x1300)
The implementation-specific instruction storage protection error interrupt occurs in the following cases:
• The fetch access violates storage protection and MSR[IR] = 1.
• The fetch access is to guarded storage and MSR[IR] = 1.
The register settings for instruction protection exceptions are shown in Table 3-35.
Table 3-35. Register Settings following an Instruction Protection Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
exception
Save/Restore Register 1 (SRR1)
0:2
Cleared to 0
Machine State Register (MSR)
3
Set to 1 if the fetch access was to a guarded storage when
MSR[IR] = 1, otherwise clear to 0
4
Set to 1 if the storage access is not permitted by the protection
mechanism (IMPU in BBC) and MSR[IR] = 1; otherwise clear
to 0
5:15
Cleared to 0
16:31
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[IR]
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Other
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
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1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain an
indeterminate value.
Execution resumes at offset 0x1300 from the base address indicated by MSR[IP].
3.15.4.15 Implementation-Specific Data Protection Error Exception (0x1400)
The implementation-specific data protection error exception occurs in the following case:
• The data access violates the storage protection and MSR[DR]=1. See Chapter 11, “L-Bus to U-Bus
Interface (L2U).”
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See Table 3-36 for data-protection-error exception register settings.
Table 3-36. Register Settings Following a Data Protection Error Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
exception
Save/Restore Register 1 (SRR1)
0:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Data/Storage Interrupt Status
Register (DSISR)
Other
Cleared to 0
0:3
Cleared to 0
4
Set to 1 if the storage access is not permitted by the protection
mechanism. Otherwise cleared to 0
5
Cleared to 0
6
Set to 1 for a store operation and cleared to 0 for a load
operation
7:31
Data Address Register (DAR)
1
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
All
Cleared to 0
Set to the effective address of the data access that caused the
exception
If the exception occurs during a data access in Decompression On mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format.
When a data protection error exception is taken, instruction execution resumes at offset 0x1400 from the
base address indicated by MSR[IP].
3.15.4.16 Implementation-Dependent Debug Exceptions
Implementation-dependent debug exceptions occur in the following cases:
• When there is an internal breakpoint match (for more details, refer to Chapter 23, “Development
Support.”
• When a peripheral breakpoint request is asserted to the RCPU.
• When the development port request is asserted to the RCPU. Refer to Chapter 23, “Development
Support,” for details on how to generate the development port-interrupt request.
See Table 3-37 for debug-exception register settings.
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Table 3-37. Register Settings Following a Debug Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
For I-breakpoints, set to the effective address of the instruction
that caused the interrupt. For L-breakpoint, set to the effective
address of the instruction following the instruction that caused
the interrupt. For development port maskable request or a
peripheral breakpoint, set to the effective address of the
instruction that the processor would have executed next if no
interrupt conditions were present. If the development port
request is asserted at reset, the value of SRR0 is undefined.
Save/Restore Register 1 (SRR1)
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
If the development port request is asserted at reset, the value
of SRR1 is undefined.
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPE This bit is set according to (BBCMCR[EN_COMP] AND
N
BBCMCR[EXC_COMP])
Other
1
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain
the instruction address in compressed format.
For data breakpoint exceptions, the register shown in Table 3-38 is set.
Table 3-38. Register Settings for Data Breakpoint Match
Register Name
BAR
Bits
Description
Set to the effective address of the data access as computed by
the instruction that caused the interrupt
Execution resumes at offset from the base address indicated by MSR[IP] as follows:
• 0x01C00 – For data breakpoint match
• 0x01D00 – For instruction breakpoint match
• 0x01E00 – For development port maskable request or a peripheral breakpoint
• 0x01F00 – For development port non-maskable request
3.15.5
Partially Executed Instructions
In general, the architecture permits instructions to be partially executed when an alignment or data storage
interrupt occurs. In the core, instructions are not executed at all if an alignment interrupt condition is
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detected and data storage interrupt is never generated by the hardware. In the RCPU, the instruction can
be partially executed only in the case of the load/store instructions that cause multiple accesses to the
memory subsystem. These instructions are:
• Multiple/string instructions
• Unaligned load/store instructions
In the last case, the store instruction can be partially completed if one of the accesses (except the first one)
causes the data storage protection error. The implementation-specific data storage protection interrupt is
taken in this case. For the update forms, the update register (rA) is not altered.
3.15.6
Timer Facilities
Descriptions of the timebase and decrementer registers can be found in Chapter 6, “System Configuration
and Protection,” and in Chapter 8, “Clocks and Power Control.”
3.15.7
Optional Facilities and Instructions
Any other OEA optional facilities and instructions (except those that are discussed here) are not
implemented by the RCPU hardware. Attempting to execute any of these instructions causes an
implementation dependent software emulation interrupt to be taken.
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Chapter 4
Burst Buffer Controller 2 Module
The burst buffer controller module (BBC) consists of four main functional parts: the bus interface unit
(BIU), the instruction memory protection unit (IMPU), branch target buffer (BTB) and the instruction code
decompressor unit (ICDU). See Figure 4-1. Information about decompression features of the BBC is found
in Appendix A, “MPC562/MPC564 Compression Features.”
The BBC master BIU interfaces between the RCPU instruction port and the internal U-bus and can support
burstable and non-burstable U-bus accesses.
The IMPU allows the instruction memory to be divided into four regions with different protection
attributes. The IMPU compares the attributes of the RCPU memory access request with the attributes of
the appropriate region. If the access is allowed, the proper signals are sent to the BIU. If access to the
memory region is disallowed because the region is protected, an interrupt is sent to the RCPU and the
master BIU cancels U-bus access.
The IMPU is able to relocate the RCPU exception vectors. The IMPU always maps the exception vectors
into the internal memory space of the MPC561/MPC563. This feature is important for a
multi-MPC561/MPC563 system, where, although the internal memories of some controllers are not
shifted to the lower 4 Mbytes, they can still have their own internal exception vector tables with the same
exception addresses issued by their RCPU cores.
The IMPU also supports an MPC561/MPC563-enhanced interrupt controller by extending an exception
vector’s relocation mechanism to translate the RCPU external interrupt exception vector separately and
splitting it into 48 different vectors, corresponding to the code generated by the interrupt controller. See
also Section 6.1.4.4, “Enhanced Interrupt Controller Operation.”
The branch target buffer (BTB) improves the performance of the MPC561/MPC563 by holding and
supplying previously accessed or decompressed instructions to the RCPU core. The BTB can be enabled
in either decompression on or off mode.
The ICDU provides decompressed instructions to RCPU in the decompression ON mode and contains a 2
Kbyte RAM (DECRAM) to hold decompression vocabularies. The DECRAM can serve as a general
purpose RAM memory on the U-bus if code compression is not used.
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BBC
IMPU
Registers
Address
Buffer
To
Addresses
U-bus
Slave
Machine
32
30
BTB
32
IMPU
Compression
Address
Decompressor
Control Logic
RCPU Core (Sequencer)
Compress/
Uncompress
Data
32
32
Data
Buffer
1 x 32
DECRAM
2 Kbytes
ICDU
U-bus Data
32
/
U-bus
Sequencer
Address
Address and Data
Buffers Control
Pipelined and
Burstable
Access Control
U-bus
Master
Machine
BIU
U-bus Controls
L/U Interface
SIU Interface
Figure 4-1. BBC Module Block Diagram
4.1
4.1.1
•
•
Key Features
BIU Key Features
Supports pipelined and burstable and single accesses to internal and external memories
Supports the decoupled interface with the RCPU instruction unit
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•
•
•
•
•
4.1.2
•
•
•
•
•
•
•
•
•
•
•
4.1.3
Implements a parked master on the U-bus, resulting in zero clock delays for RCPU fetch accesses
to the U-bus
Fully utilizes the U-bus pipeline for fetch accesses
Avoids undesirable delays through a tight interface with the L2U module (fully utilizing U-bus
bandwidth and back-to-back accesses)
Supports program trace and show cycles
Supports a special attribute for debug port fetch accesses.
IMPU Key Features
There are four regions in which the base address and size can be programmed.
Available region sizes include 2 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes,
256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes....4 Gbytes.
Overlap between regions is allowed.
Each of the four regions supports the following attributes:
— User/supervisor
— Guard attribute (causes an interrupt in case of speculative fetch attempt)
— Compressed/non-compressed (MPC562/MPC564 only)
— Regions are enabled or disabled in software.
Global region entry declares the default access attributes for all memory areas not covered by the
four regions:
The RCPU gets the instruction storage protection exception generated upon
— An access violation of protection attributes
— A fetch from a guarded region.
The RCPU MSR[IR] bit controls IMPU protection.
Programming is performed by using the RCPU mtspr/mfspr instructions to/from implementation
specific special-purpose registers.
The IMPU supplies relocation addresses of all the exceptions within the internal memory space.
The IMPU implements external interrupt vector splitting to reduce the external interrupt latency.
There is a special reset exception vector for decompression on mode (MPC562/MPC564 only).
ICDU Key Features
The following are instruction code decompression unit key features of the MPC562/MPC564. See
Appendix A, “MPC562/MPC564 Compression Features” for more information.
• Instruction code on-line decompression based on “instruction classes” algorithm.
• No need for address translation between compressed and non-compressed address spaces — ICDU
provides “next instruction address” to the RCPU
• In most cases, instruction decompression takes one clock
• Code decompression is pipelined:
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•
•
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Two operation modes are available: decompression on and decompression off. Switch between
compressed and non-compressed user application software parts is possible.
Adaptive vocabularies scheme is supported; each user application can have its own optimum
vocabularies.
4.1.4
•
•
•
•
•
•
DECRAM Key Features
2 Kbytes RAM for decompression vocabulary tables
2 clock read/write accesses when used as a U-bus general-purpose RAM
4 clock load/store accesses from the L-bus
Byte, half-word (16-bit) or word (32-bit) read/write accesses and fetches
Special access protection functions
Low-power standby operation for data retention
4.1.5
•
•
•
•
Branch Target Buffer Key Features
Consists of eight “branch target entries” (BTE). Each entry contains:
— A 32-bit register that stores the target of historical change of flow (COF) address
— Four RAM entries, 38 bits each, which hold up to four valid instruction OPCODES (32 bits).
The six extra bits are used by ICDU in decompression on mode.
— A 32-bit register that stores the values used to calculate the address following the last valid
instruction.
FIFO removal policy management is implemented for the eight BTEs
Software-controlled BTB enable/disable and invalidate
User transparent (that is, no user management is required)
4.2
4.2.1
Operation Modes
Instruction Fetch
The BBC provides two instruction fetch modes: decompression off and decompression on. The operational
modes are defined by RCPU MSR[DCMPEN] bit. If the bit is set, the mode is decompression on.
Otherwise, it is in decompression off.
4.2.1.1
Decompression Off Mode
In this mode, the BBC bus interface unit (BIU) module transfers fetch accesses from the RCPU to the
U-bus. When a new access is issued by the RCPU, it is transferred in parallel to both the IMPU and the
BIU. The IMPU compares the address of the access to its region programming. The BIU checks if the
access can be immediately transferred to the U-bus, otherwise it requests the U-bus for the next clock.
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The BIU may be programmed for burstable or non-burstable access. If the BIU is programmed for
burstable access, the U-bus address phase transaction is accompanied by the burst request attribute. If
burstable access is allowed by the U-bus slave, the BIU continues current access as burstable, otherwise
current access is executed as a single access. If any protection violation is detected by the IMPU, the
current U-bus access is aborted by the BIU and an exception is signaled to the RCPU.
Show cycle, program trace and debug port access attributes accompanying the RCPU access are forwarded
by the BIU along with the U-bus access.
4.2.1.2
Decompression On Mode
See Appendix A, “MPC562/MPC564 Compression Features” for explanation of the decompression on
mode.
4.2.2
Burst Operation of the BBC
The BBC may initiate and handle burst accesses on the U-bus. The BBCMCR[BE] bit determines whether
the BBC operates burst cycles or not. Burst requests are enabled when the BE bit is set. The BBC handles
non-wrap-around bursts with up to 4 data beats on the internal U-bus.
NOTE
The burst operation in the MPC561/MPC563 is useful if a user system
implements burstable memory devices on the external bus. Otherwise the
mode will cause performance degradation when running code from external
memory.
When the RCPU runs in serialized mode it is recommended that bursts be
disabled by the BBC to speed up MPC561/MPC563 operation.
Burst operation for decompression on and in debug mode is disabled
regardless of BBCMCR[BE] bit setting.
The BBC burst should be turned off if the USIU burst feature is enabled.
4.2.3
Access Violation Detection
Instruction memory protection is assigned on a regional basis. Default operation of IMPU is done on a
global region. The IMPU has control registers which contain the following information: region protection
on/off, region base address, size and access permissions.
Protection logic is activated only if the RCPU MSR[IR] bit is set.
During each fetch request from the RCPU core to instruction memory, the address is compared to a value
in the region base address of enabled regions. Any address matching the specific region within its
appropriate size as defined in the region attribute register sets a match indication.
When more than one match indication occurs, the effective region is the region with the highest priority.
Priority is determined by region number. The lowest region number has the highest priority and the global
region has lowest priority.
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When no match happens, the effective region is the global region.
The region attribute registers contain the region protection fields: PP, G, and CMPR. The protection fields
are compared to address attributes issued by the RCPU. If the access is permitted, the address is passed to
the BIU and further to the U-bus.
Whenever the IMPU detects access violation, the following actions are taken:
1. The request forwarded to the BIU is canceled
2. The RCPU is informed that the requested address caused an access violation by exception request.
However, if the required address contains a show cycle attribute, the BIU delivers the access onto the
U-bus to obtain program tracking.
The exception vector (address) that the RCPU issues for this exception has a 0x1300 offset in the RCPU
exception vector table. The access violation status is provided in the RCPU SRR1 special purpose register.
The encoding of the status bits is as follows:
• SRR1 [1] = 0
• SRR1 [3] = Guarded storage
• SRR1 [4] = Protected storage or compression violation
• SRR1 [10] = 0
Only one bit is set at a time.
4.2.4
Slave Operation
The BBC is operating as a U-bus slave when the IMPU registers, decompressor RAM (DECRAM) or
ICDU registers are accessed from the U-bus. The IMPU register programming is done using PowerPC ISA
mtspr/mfspr instructions. The ICDU configuration registers (DCCRs) and DECRAM are mapped into the
chip memory space and accessed by load/store instructions. DCCR and DECRAM accesses may be
disabled by BBCMCR[DCAE]. Refer to Section 4.6.2.1, “BBC Module Configuration Register
(BBCMCR).”
4.2.5
Reset Behavior
Upon soft reset, the BBC switches to an idle state and all pending U-bus accesses are ignored, the ICDU
internal queue is flushed and the IMPU switches to a disabled state where all memory space is accessible
for both user and supervisor.
Hard reset sets some of the fields and bits in the BBC configuration registers to their default reset state.
Some bits in the BBCMCR register get their values from the reset configuration word.
All the registers are reset using HRESET; SRESET alone has no effect on them.
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NOTE
Because HRESET resets the EN_COMP bit and the EXC_COMP bit but
SRESET does not, there may be different behavior between HRESET and
SRESET when both EN_COMP and EXC_COMP are set. Special care must
be taken to ensure operation in a known mode whenever reset occurs. The
reset states of these bits are determined by reset configuration words. The
location of the reset vector is dependent on the value of the MSR[IP] bit in
the RCPU. If MSR[IP] is set, the exception table relocation feature can be
used. See Section 4.3.1, “ETR Operation.”
4.2.6
Debug Operation Mode
When the MPC561/MPC563 RCPU core is in debug mode, the BBC initiates non-burstable access to the
debug port and ICDU is bypassed (i.e., instructions transmitted to the debug port must be non-compressed
regardless of RCPU MSR[DCMPEN] bit state).
4.3
Exception Table Relocation (ETR)
The BBC is able to relocate the exception addresses of the RCPU. The relocation feature always maps the
exception addresses into the internal memory space of the MPC561/MPC563. See Figure 4-2. This feature
is important in multi-MPC561/MPC563 systems, where, although the memory map in some was shifted
to not be on the lower 4 Mbytes, their RCPU cores can still access their own exception handlers in their
internal Flash in spite of several RCPUs issuing the same exception addresses.
The relocation also saves wasted space between the exception table entries in the case where each
exception entry contained only a branch instruction to the exception routine, which is located elsewhere.
The exception vector table may be programmed to be located in four places in the MPC561/MPC563
internal memory space.
The exception table relocation is supported in both decompression on and decompression off operation
modes.
The RESET routine vector is relocated differently in decompression on and in decompression off modes.
This feature may be used by a software code compression tool to guarantee that a vocabulary table
initialization routine is always executed before application code is running.
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Exception Pointer by Core
Internal Memory Structure
0
0
Decompression
ON
Y
100
N
branch to...
8
branch to...
10
branch to...
branch to...
branch to...
200
branch to...
branch to...
300
branch to...
branch to...
400
500
branch to...
B8
branch to...
.
.
.
.
600
700
1F00
Exception Table
branch to...
.
.
.
.
branch to...
branch to...
Free Memory Space
1FFC
1FFC
Figure 4-2. Exception Table Entries Mapping
4.3.1
ETR Operation
The exception vectors generated by the RCPU are 0x100 bytes apart from each other, starting at address
0x0000 0100 or 0xFFF0 0100, depending on the value of MSR[IP] bit in the RCPU.
If the exception table relocation is disabled by the ETRE bit in the BBCMCR register, the BBC transfers
the exception fetch address to the U-bus of the MPC561/MPC563 with no interference. In this case, normal
PowerPC ISA exception addressing is implemented.
If the exception table relocation is enabled, the BBC translates the exception vector into the exception
relocation address as shown in Table 4-1. At that location, a branch instruction with absolute addressing
(ba) must be placed. Each ba instruction branches to the required exception routine. These branch
instructions should be successive in that region of memory. That way, a table of branch instructions is
implemented. Executing the branch instruction causes the core to branch twice until it gets to the exception
routine.
Each exception relocation table entry occupies two words to support decompression on mode, where a
branch instruction can be more than 32 bits long. The branch table can be located in four locations in the
internal memory, the location is defined by BBCMCR[OERC] as shown in Table 4-2.
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NOTE
The 8 Kbytes allocated for the original PowerPC ISA exception table can be
almost fully utilized. This is possible if the MPC561/MPC563 system
memory is not mapped to the exception address space, (i.e., the addresses
0xFFF0 0000 to 0xFFF0 1FFF are not used).
In such case, these 8 Kbytes can be fully utilized by the compiler, except
for the lower 64 words (256 bytes) which are dedicated for the branch
instructions.
If the RCPU, while executing an exception, issues any address between two
successive exception entries (e.g., 0xFFF0 0104), then the operation of the
MPC561/MPC563 is not guaranteed if the ETR is enabled.
In order to activate the exception table relocation feature, the following steps are required:
1. Set the RCPU MSR[IP] bit
2. Set the BBCMCR[ETRE] bit. See Section 4.6.2.1, “BBC Module Configuration Register
(BBCMCR),” for programming details.
The ETR feature can be activated from reset, by setting corresponding bits in the reset configuration word.
.
Table 4-1. Exception Addresses Mapping
Original Address Issues by
Core
Mapped Address by Exception Table
Relocation Logic
Reserved
0xFFF0 0000
Page_Offset+0x000
System Reset
0xFFF0 0100
Name of Exception
Compression disabled
Compression enabled
Page_Offset1+0x08
Page_Offset1+0x0B8
Machine Check
0xFFF0 0200
Page_Offset+0x010
Reserved
0xFFF0 0300
Page_Offset+0x018
Reserved
0xFFF0 0400
Page_Offset+0x020
External Interrupt2
0xFFF0 0500
Page_Offset+0x028
Alignment
0xFFF0 0600
Page_Offset+0x030
Program
0xFFF0 0700
Page_Offset+0x038
Floating Point unavailable
0xFFF0 0800
Page_Offset+0x040
Decrementer
0xFFF0 0900
Page_Offset+0x048
Reserved
0xFFF0 0A00
Page_Offset+0x050
Reserved
0xFFF0 0B00
Page_Offset+0x058
System Call
0xFFF0 0C00
Page_Offset+0x060
Trace
0xFFF0 0D00
Page_Offset+0x068
Floating Point Assist
0xFFF0 0E00
Page_Offset+0x070
Implementation Dependent
Software Emulation
0xFFF0 1000
Page_Offset+0x080
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Table 4-1. Exception Addresses Mapping (continued)
Original Address Issues by
Core
Mapped Address by Exception Table
Relocation Logic
Implementation Dependent
Instruction Storage
Protection Error
0xFFF0 1300
Page_Offset+0x098
Implementation Dependent
Data Storage Protection
Error
0xFFF0 1400
Page_Offset+0x0A0
Implementation Dependent
Data Breakpoint
0xFFF0 1C00
Page_Offset+0x0E0
Implementation Dependent
Instruction Breakpoint
0x0FFF 1D00
Page_Offset+0x0E8
Implementation Dependent
Maskable External
Breakpoint
0xFFF0 1E00
Page_Offset+0x0F0
Non-Maskable External
Breakpoint
0xFFF0 1F00
Page_Offset+0x0F8
Name of Exception
1
2
Refer to Table 4-2.
0x500 is remapped if the EEIR feature is enabled. See Section 4.3.2, “Enhanced External Interrupt Relocation
(EEIR).”
Table 4-2. Exception Relocation Page Offset
BBCMCR(OERC[0:1])
1
2
4.3.2
Page Offset
0x0 + ISB
offset1
Comments
0
0
0
0
1
0x1 0000 + ISB offset
64 Kbytes2
1
0
0x8 0000 + ISB offset
512 Kbytes
1
1
0x3F E000 + ISB offset
L-bus (CALRAM)
Address
ISB offset is equal 4M * ISB (0x400000 * ISB), where ISB is value of bit field in USIU IMMR register.
This offset is different from the MPC555.
Enhanced External Interrupt Relocation (EEIR)
The BBC also supports the enhanced external interrupt model of the MPC561/MPC563 which allows the
removal of the interrupt requesting a source detection stage from the interrupt routine. The interrupt
controller provides the interrupt vector to the BBC together with an interrupt request to the RCPU. When
the RCPU acknowledges an interrupt request, it issues an external interrupt vector to the BBC. The BBC
logic detects this address and replaces it with another address corresponding to the interrupt controller
vector, which is defined by the highest priority interrupt request from a peripherial module or external
interrupt request pin. See Figure 4-3.
The external interrupt relocation table should be placed at the physical address defined in the external
interrupt relocation table base address register. See Section 4.6.2.5, “External Interrupt Relocation Table
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Burst Buffer Controller 2 Module
Base Address Register (EIBADR).” This is the base address of a branch table. See Table 6-4 and
Figure 4-3.
Each table entry must contain a branch absolute (ba) instruction to the first instruction of an interrupt
service routine. Each table entry occupies two words (eight bytes) to support decompression on mode,
where a branch instruction can be more than 32 bits long.
The memory space allocated for the external interrupt relocation table is up to 2 Kbytes. If part of the
external interrupt relocation table entry is not used, it may be utilized for another purpose such as
instruction code space or data space.
In order to activate the external interrupt relocation feature, the following steps are required:
1. Program the EIBADR register to the external interrupt branch table base address. See
Section 4.6.2.5, “External Interrupt Relocation Table Base Address Register (EIBADR).”
2. Set the MSR[IP] bit.
3. Set the BBCMCR[EIR] bit. See Section 4.6.2.1, “BBC Module Configuration Register
(BBCMCR),” for programming details.
NOTE
If both the enhanced external interrupt relocation and exception table
relocation functions are activated simultaneously, the final external interrupt
vector is defined by EEIR mechanism.
When the EEIR function is activated, any branch instruction execution with
the 0xFFF0 0500 target address may cause unpredictable program
execution.
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Burst Buffer Controller 2 Module
Internal Memory Structure
EIBADR
Branch absolute to handler
Branch absolute to handler
Branch absolute to handler
External
Interrupt
0x500
Relocation Table
Interrupt
Vector
Offset
000
Base Address
(EIBADR)
External Interrupt Handlers Table
External Interrupt
Vector Relocator
Translated Vectors
Interrupt Pointer by Core
Branch absolute to handler
Interrupt Code
from Interrupt
Controller
Branch absolute to handler
Main code can start here
Figure 4-3. External Interrupt Vectors Splitting
4.4
Decompressor RAM (DECRAM) Functionality
Decompressor RAM (DECRAM) is a part of the ICDU. It occupies a 2-Kbyte physical RAM array block.
It is mapped both in the ICDU internal address space and in the chip memory address space. It is a single
port memory and may not be accessed simultaneously from the ICDU and U-bus.
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Burst Buffer Controller 2 Module
U-bus Address
U-bus Data
Slave BIU
ICDU
Vocabulary Table (VT1)
Array (1 Kbyte)
Vocabulary Table (VT2)
Array (1 Kbyte)
DECRAM
VT1 Data
VT1 Address
VT2 Data
VT2 Address
ICDU Control Logic
Figure 4-4. DECRAM Interfaces Block Diagram
4.4.1
General-Purpose Memory Operation
In the case of decompression off mode, the DECRAM can serve as a two-clock access general-purpose
RAM for U-bus instruction fetches or four-clock access for read/write data operations. The base address
of the DECRAM is 0x2F 8000. See Figure 4-6. The proper access rights to the DECRAM array may be
defined by programming the R, D, and S bits of the BBCMCR register:
• Read/write or read only
• Instruction/data or data only
• Supervisor/user or supervisor only
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Burst Buffer Controller 2 Module
U-bus access mode of the RAM is activated by the BBCMCR[DCAE] bit setting (see Section 4.6.2.1,
“BBC Module Configuration Register (BBCMCR)”). In this mode the DECRAM can be accessed from
the U-bus and cannot be accessed by the ICDU logic.
In this mode:
• The DECRAM supports word, half-word and byte operations.
• The DECRAM is emulated to be 32 bits wide. For example: a load access from offset 0 in the
DECRAM will deliver the concatenation of the first word in each of the DECRAM banks when
RAM 1 contains the 16 LSB of the word and RAM 2 contains the 16 MSB.
• Load accesses at any width are supplied with 32 bits of valid data.
• The DECRAM communicates with the U-bus pipeline but does not support pipelined accesses to
itself. If a store operation is second in the U-bus pipe, the store is carried out immediately and the
U-bus acknowledgment is performed when the previous transaction in the pipe completes.
• Burst access is not supported.
NOTE
Instructions running from the DECRAM should not also perform store
operations to the DECRAM.
4.4.1.1
Memory Protection Violations
The DECRAM module does not acknowledge U-bus accesses that violate the configuration defined in the
BBCMCR. This causes the machine check exception for the internal RCPU or an error condition for the
MPC561/MPC563 external master.
4.4.1.2
DECRAM Standby Operation Mode
The bus interface and DECRAM control logic are powered by VDD supply. The memory array is supplied
by a separate power pin (IRAMSTBY).
4.5
Branch Target Buffer
The burst buffer controller contains a branch target buffer (BTB) to reduce the impact of branches on
processor performance. Following is a summary of the BTB features:
• Software controlled BTB enable/disable, inhibit, and invalidate
• User transparent — no user management required
The BTB consists of eight branch target entries (BTE). Refer to Figure 4-5. All entries are managed as a
fully associative cache. Each entry contains a tag and several data buffers related to this tag.
4.5.1
BTB Operation
When the RCPU generates a change of flow (COF) address for instruction fetch, the BTB control logic
compares it to the tag values currently stored in the tag register file where the following events can happen:
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Burst Buffer Controller 2 Module
•
•
BTE Miss — The target address and instruction code data will be stored in one of the BTE entries
defined by its control logic. Up to four instructions and their corresponding addresses subsequent
to the COF target instruction may be saved in each BTE entry. The number of valid instructions
currently stored in the BTE entry is written into the VDC field of the current BTE entry. The valid
flag is set at the end of this process. The entry to be replaced upon miss is chosen based on FIFO
replacement method. Thus the BTB can support up to eight different branch target addresses in a
program loop.
BTE Hit — When the target address of a branch matches one of the valid BTE entries, two
activities take place in parallel:
— The BTB supplies all the valid instructions in the matched entry to the RCPU.
— The BIU starts to prefetch new instructions (and ICDU decompresses them in compressed
mode) from the address following the last instruction that is stored in the matched BTB entry.
The BBC will supply these new instructions to the RCPU after all the stored instructions in the
matched BTB entry were delivered.
In case of a BTB hit, the impact of instruction decompression latency (in compressed mode) is eliminated
as well as a latency of instruction storage memory device.
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Burst Buffer Controller 2 Module
BTE TAG Register File
BTE Memory Array
32-bit
Instruction
Address
Tag Register/Comparator
Next Address
VDC
Hit
V
Instruction Buffers
Tag Register/Comparator
Next Address
VDC
Hit
V
Instruction Buffers
Tag Register/Comparator
Next Address
VDC
Hit
V
Instruction Buffers
Tag Register/Comparator
Next Address
VDC
Hit
Tag Register/Comparator
Next Address
VDC
Hit
VDC
Hit
VDC
Hit
VDC
Instruction Buffers
V
Tag Register/Comparator
Next Address
Instruction Buffers
V
Tag Register/Comparator
Next Address
Instruction Buffers
V
Tag Register/Comparator
Next Address
Instruction Buffers
V
Hit
Instruction Buffers
V
BTB Hit
Figure 4-5. BTB Block Diagram
4.5.1.1
BTB Invalidation
Write access to any BBC special purpose register invalidates all BTB entries.
NOTE
To guarantee that the BTB does not contain instructions that may have been
changed, the BTB contents should be invalidated any time instruction
memory is modified.
4.5.1.2
BTB Enabling/Disabling
The BTB operation may be enabled or disabled by programming the BTEE bit in the BBCMCR register.
4.5.1.3
BTB Inhibit Regions
The BTB operation may be inhibited regarding some memory regions. The BTB caching is inhibited for
a region if the BTBINH bit is set in the region attribute register (or global region attribute register). See
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Burst Buffer Controller 2 Module
Section 4.6.2.3, “Region Attribute Registers (MI_RA[0:3]),” and Section 4.6.2.4, “Global Region
Attribute Register (MI_GRA)” for details.
4.6
BBC Programming Model
4.6.1
Address Map
The BBC consists of three separately addressable sections within the internal chip address space:
1. BBC and IMPU control registers. These are mapped in the SPR registers area and may be
programmed by using the RCPU mtspr/mfspr instructions.
2. Decompressor vocabulary RAM (DECRAM). The DECRAM array occupies the 2-Kbyte physical
memory (8 Kbytes of the MPC561/MPC563 address space is allocated for DECRAM).
3. Decompressor class configuration registers (DCCR) block. It consists of 15 decompression class
configuration registers. These registers are available for word wide read/write accesses through
U-bus. The registers occupy a 64-byte physical block (8-Kbyte chip address space is allocated for
the register block).
0x2F 8000
0x2F 87FF
0x2F 8800
DECRAM
2 Kbytes
Reserved
0x2F 9FFF
0x2F A000
DCCR0 – DCCR15
0x2F A03F
Figure 4-6. MPC561/MPC563 Memory Map
4.6.1.1
BBC Special Purpose Registers (SPRs)
Table 4-3. BBC SPRs
SPR Number
(Decimal)
Address for
External
Master
Access (Hex)
528
0x2100
IMPU Global Region Attribute Register (MI_GRA). See Table 4-8 for bits
descriptions.
529
0x2300
External Interrupt Relocation Table Base Address Register (EIBADR). See
Table 4-9 for bits descriptions.
560
0x2110
BBC Module Configuration Register (BBCMCR). See Table 4-4 for bits descriptions
Register Name
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Burst Buffer Controller 2 Module
Table 4-3. BBC SPRs (continued)
SPR Number
(Decimal)
Address for
External
Master
Access (Hex)
784
0x2180
IMPU Region Base Address Register 0 (MI_RBA0). See Table 4-5 for bits
descriptions.
785
0x2380
IMPU Region Base Address Register 1 (MI_RBA1). See Table 4-5 for bits
descriptions.
786
0x2580
IMPU Region Base Address Register 2 (MI_RBA2). See Table 4-5 for bits
descriptions.
787
0x2780
IMPU Region Base Address Register 3 (MI_RBA3). See Table 4-5 for bits
descriptions.
816
0x2190
IMPU Region Attribute Register 0 (MI_RA0). See Table 4-6 for bits descriptions.
817
0x2390
IMPU Region Attribute Register 1 (MI_RA1). See Table 4-6 for bits descriptions.
818
0x2590
IMPU Region Attribute Register 2 (MI_RA2). See Table 4-6 for bits descriptions.
819
0x2790
IMPU Region Attribute Register 3 (MI_RA3). See Table 4-6 for bits descriptions.
Register Name
All the above registers may be accessed in the supervisor mode only. An exception is internally generated
by the RCPU if there is an attempt to access them in user mode. An external master receives a transfer
error acknowledge when attempting to access a register in user mode.
NOTE
If one of these registers is written within 4 instructions of a branch target,
the user application may crash. To prevent this, ensure that any instruction
writing to these registers is preceded by 4 instructions that are not the target
of any branch, and is followed by an isync instruction.
4.6.1.2
DECRAM and DCCR Block
The DECRAM occupies addresses from 0x2F 8000 to 0x2F 87FF. The DCCR block occupies addresses
from 0x2F A000 to 0x2F A03F.
The address for non-implemented memory blocks is not acknowledged, and causes an error condition.
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Burst Buffer Controller 2 Module
4.6.2
BBC Register Descriptions
4.6.2.1
BBC Module Configuration Register (BBCMCR)
,
MSB
Field
0
1
2
R
D
S
3
4
5
6
7
8
9
10
TEST
HRESET
11 12 13
14
15
—
0000_0000_0000_0000
LSB
16
Field
HRESET
17
—
18
BE
19
21
ETRE EIR
ID192
000
20
0
22
23
1
EN_ EXC_COMP
COMP1
ID212
ID222
Addr
24
25
26
DECOMP_SC_ OERC[0:1] BTEE
EN1
ID212
ID(24:25)2
27 28 29
—
30
31
DCAE TST
00_0000
SPR 560
Figure 4-7. BBC Module Configuration Register (BBCMCR)
1
MPC562/MPC564 only.
2 The reset value is a reset configuration word value extracted from the internal bus line. Refer to Section 7.5.2, “Hard Reset
Configuration Word (RCW).”
Table 4-4. BBCMCR Field Descriptions
Bits
Name
Description
0
R
Read Only. Any attempt to write to the DECRAM array while R is set is terminated with
an error. This causes a machine check exception for RCPU.
0 DECRAM array is Readable and Writable.
1 DECRAM array is Read only.
1
D
Data Only. The DECRAM array may be used for Instructions and Data or for Data
storage only. Any attempt to load instructions from the DECRAM array, while D is set, is
terminated with an error This causes a machine check exception for the RCPU.
0 DECRAM array holds Data and/or Instruction.
1 DECRAM array holds Data only.
2
S
Supervisor Only.
When the bit is set (S = 1), only a Supervisor program may access the DECRAM. If a
Supervisor program is accessing the array, normal read/write operation will occur. If a
User program is attempting to access the array, the access will be terminated with an
error This causes a machine check exception for the RCPU.
If S = 0, the RAM array is placed in Unrestricted Space and access by both Supervisor
and User programs is allowed.
3:7
TEST
8:17
—
18
BE1
These bits can be set in Factory test mode only. The User should treat these bits as
reserved and always write as zeros.
Reserved
Burst Enable
0 Burst access is disabled.
1 Burst access is enabled.
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Burst Buffer Controller 2 Module
Table 4-4. BBCMCR Field Descriptions (continued)
Bits
Name
Description
19
ETRE
Exception Table Relocation Enable
0 Exception Table Relocation is off: BBC does NOT map exception addresses.
1 Exception Table Relocation is on: BBC maps exception addresses to a table holding
branch instructions two memory words apart from each other.
The reset value is taken from the reset configuration word bit 19.
Note: On the MPC562/MPC564, do not put compressed code at addresses 0xFFF0
0000 to 0xFFFF FFFF if ETRE = 1.
20
EIR
Enhanced External Interrupt Relocation Enable— This bit activates the external
interrupt relocation table mechanism. This bit is independent from the value of ETRE
bit, but if EIR and ETRE are enabled, the mapping of external interrupt will be via EIR.
0 EIR function is disabled.
1 EIR function is active.
21
EN_COMP2
Enable Compression. This bit enables the operation of the MPC562/MPC564 in
compression on mode.
NOTE: For Rev A and later versions of the MPC563 and rev B and later of the MPC561,
the default state is defined by bit 21 of the reset configuration word, and is writable. In
earlier versions, the bit can only be set by the reset configuration word.
0 decompression on mode is disabled.
1 decompression on mode is enabled.
The MPC561/MPC563 operates only in decompression off mode. The
MPC562/MPC564 may operate with both decompression on and decompression off
modes.
22
EXC_COMP2
Exception Compression. This bit determines the operation of the MPC562/MPC564
with exceptions. If this bit is set, the MPC562/MPC564 assumes that the all exception
routine codes are compressed; otherwise it is assumed that all exception routine codes
are not compressed. The reset value is determined by reset configuration word bit 22.
0 The RCPU assumes that exception routines are noncompressed.
1 The RCPU assumes that all exception routines are compressed.
This bit has effects only when the EN_COMP bit is set. The MPC561/MPC563 operates
only in decompression off mode. The MPC562/MPC564 may operate with both
decompression on and decompression off modes.
23
DECOMP_SC_EN2 Decompression Show Cycle Enable. This bit determines the way the MPC562/MPC564
executes instruction show cycles.
The reset value is determined by configuration word bit 21. For further details regarding
show cycles execution in “Decompression ON” mode see Section 4.2.1.2,
“Decompression On Mode.”
0 Decompression Show Cycles do not include the bit pointer.
1 Decompression Show Cycles include the bit pointer information on the data bus.
24:25
OERC[0:1]
Other Exceptions Relocation Control. These bits have effect only if ETRE was enabled;
See details in Section 4.3.1, “ETR Operation.”
00: offset 0
01 Offset 64 Kbytes
10 Offset 512 Kbytes
11 Offset to 0x003FE000
The reset value is determined by reset configuration word bits 24 and 25
26
BTEE1
Branch Target Entries Enable. This bit enables Branch Target Entries of BTB operation
0 BTE operation is disabled
1 BTE operation is enabled
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Burst Buffer Controller 2 Module
Table 4-4. BBCMCR Field Descriptions (continued)
1
2
Bits
Name
27:29
—
30
DCAE
31
TST
Description
Reserved.
NOTE: Bit 27 was BCMEE and should be written as 0.
Decompressor Configuration Access Enable. This bit enables DECRAM and DCCR
registers access from the U-bus master (i.e., RCPU, external master).
0 DECRAM and DCCR registers are locked.
1 DECRAM allows accesses from the U-bus only.
DCAE bit should be set before vocabulary tables are loaded via the U-bus.
Reserved for BBC Test Operations.
BE and BTEE should not both be set at the same time, setting the BE bit disables the BTB.
This bit is available on the MPC562/MPC564 only, software should write "0" to this bit for MPC561/MPC563.
NOTE
When writing to the BBCMCR register, the following instruction after
mtspr BBCMCR, Rx should be ISYNC, to make sure that the programmed
value will come into effect before any further action.
4.6.2.2
Region Base Address Registers (MI_RBA[0:3])
The following registers contain 32 bits and define the starting address of the protected regions. There is
one register for each of four regions.
,
MSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
25
26
27
28
29
30
15
RA
HRESET
Unchanged
LSB
16
17
Field
HRESET
18
19
20
21
22
23
24
RA
—
Undefined
0000_0000_0000
Addr
31
SPR 784 (MI_RBA0), SPR 785 (MI_RBA1), SPR 786 (MI_RBA2), SPR 787 (MI_RBA3)
Figure 4-8. Region Base Address Register (MI_RBA[0:3])
Table 4-5. MI_RBA[0:3] Registers Bit Descriptions
Bits
Name
Description
0:19
RA
Region Base address. The RA field provides the base address of the region. The region base
address should start on the memory block boundary for the corresponding region size, specified
in the region attribute register MI_RA.
20:31
—
Reserved
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Burst Buffer Controller 2 Module
NOTE
When the MPC562/MPC564 operates in decompression on mode, a
minimum of four unused words MUST be left after the last instruction in
any region.
4.6.2.3
Region Attribute Registers (MI_RA[0:3])
The following registers define protection attributes and size for four memory regions.
,
MSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
25
26
27
28
29
30
15
RS
HRESET
Unchanged
LSB
16
17
Field
18
19
RS
HRESET
21
PP
Undefined
Addr
20
22
23
—
24
G
000
CMPR
BTBINH
Undefined
31
—
000
SPR 816 (MI_RA0), SPR 817 (MI_RA1), SPR 818 (MI_RA2), 819 (MI_RA3)
Figure 4-9. Region Attribute Register (MI_RA0[0:3])
Table 4-6. MI_RA[0:3] Registers Bit Descriptions
Bits
Name
Description
0:19
RS
Region size. For byte size by region, see Table 4-7.
20:21
PP1
Protection bits:
00 Supervisor — No Access, User — No Access.
01 Supervisor — Fetch, User — No Access.
1x Supervisor — Fetch, User — Fetch.
22:24
—
Reserved
25
G1
Guard attribute for region
0 Speculative fetch is not prohibited from region. Region is not guarded.
1 Speculative fetch is prohibited from guarded region. An exception will occur under such attempt.
26:27
CMPR2
Compressed Region.
x0 The region in not restricted
01 Region is considered a non-compressed code region. Access to the region is allowed only in
“Decompression Off” mode
11 Region is considered a compressed code region. Access to the region is allowed only in
“Decompression On” mode
28
BTBINH
BTB Inhibit region
0 BTB operation is not prohibited for current memory region
1 BTB operation is prohibited for current memory region.
29:31
—
Reserved
1
G and PP attributes perform similar protection activities on a region. The more protective attribute will be implied on the
region if the attributes programming oppose each other.
2
This field is available only on the MPC562/MPC564.
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Burst Buffer Controller 2 Module
Table 4-7. Region Size Programming Possible Values
RS Field Value (Binary)
4.6.2.4
Size
0000_0000_0000_0000_0000
4 Kbytes
0000_0000_0000_0000_0001
8 Kbytes
0000_0000_0000_0000_0011
16 Kbytes
0000_0000_0000_0000_0111
32 Kbytes
0000_0000_0000_0000_1111
64 Kbytes
0000_0000_0000_0001_1111
128 Kbytes
0000_0000_0000_0011_1111
256 Kbytes
0000_0000_0000_0111_1111
512 Kbytes
0000_0000_0000_1111_1111
1 Mbyte
0000_0000_0001_1111_1111
2 Mbytes
0000_0000_0011_1111_1111
4 Mbytes
0000_0000_0111_1111_1111
8 Mbytes
0000_0000_1111_1111_1111
16 Mbytes
0000_0001_1111_1111_1111
32 Mbytes
0000_0011_1111_1111_1111
64 Mbytes
0000_0111_1111_1111_1111
128 Mbytes
0000_1111_1111_1111_1111
256 Mbytes
0001_1111_1111_1111_1111
512 Mbytes
0011_1111_1111_1111_1111
1 Gbyte
0111_1111_1111_1111_1111
2 Gbytes
1111_1111_1111_1111_1111
4 Gbytes
Global Region Attribute Register (MI_GRA)
The MI_GRA register defines protection attributes for memory region, not covered by
MI_RB[0:3]/MI_RBA[0:3] registers. It also contains protection regions 0-3 enable bits.
,
MSB
0
1
2
3
4
5
6
7
8
9
Field ENR 0 ENR1 ENR2 ENR3
10
11
12
13
14
27
28
29
30
15
—
HRESET
0000_0000_0000_0000
LSB
16
17
Field
HRESET
Addr
18
—
19
20
21
PP
22
23
24
—
25
G
26
CMPR
BTBINH
31
—
0000_0000_0000_0000
SPR 528
Figure 4-10. Global Region Attribute Register (MI_GRA)
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Burst Buffer Controller 2 Module
Table 4-8. MI_GRA Field Descriptions
1
Bits
Name
Description
0
ENR0
Enable IMPU Region 0
0 Region 0 is off.
1 Region 0 is on.
1
ENR1
Enable IMPU Region 1
0 Region 1 is off.
1 Region 1 is on.
2
ENR2
Enable IMPU Region 2
0 Region 2 is off.
1 Region 2 is on.
3
ENR3
Enable IMPU Region 3
0 Region 3 is off.
1 Region 3 is on.
4:19
—
Reserved
20:21
PP
Protection Bits
00 Supervisor – No Access, User – No Access.
01 Supervisor – Fetch, User – No Access.
1x Supervisor – Fetch, User – Fetch.
22:24
—
Reserved
25
G
Guard attribute for region
0 Fetch is not prohibited from region. Region is not guarded.
1 Fetch is prohibited from guarded region. An exception will occur under such attempt.
26:27
CMPR1
Compressed Region.
x0 The region is not restricted
01 Region is considered a non-compressed code region Access to the region is allowed only in
“Decompression Off” mode
11 Region is considered a compressed code region. Access to the region is allowed only in
“Decompression On” mode
28
BTBINH
BTB Inhibit region
0 BTB operation is not prohibited for current memory region
1 BTB operation is prohibited for current memory region.
29:31
—
Reserved
This field is available only on the MPC562/MPC564.
NOTE
The MI_GRA register should be programmed to enable fetch access (PP and
G bits) before RCPU MSR[IR] is set.
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Burst Buffer Controller 2 Module
4.6.2.5
External Interrupt Relocation Table Base Address Register (EIBADR)
,
MSB
0
LSB
1
2
Field
HRESET
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
18 19 20 21 22 23 24 25 26 27 28 29 30
BA
—
Unchanged
000_0000_0000
31
Figure 4-11. External Interrupt Relocation Table Base Address Register (EIBADR)
Table 4-9. EIBADR External Interrupt Relocation Table Base Address Register Bit Descriptions
Bits
Name
0:20
BA
External Interrupt Relocation Table Base Address bits [0:20]
21:31
—
Reserved. EIBADR must be set on a 4K page boundary.
4.6.3
Description
Decompressor Class Configuration Registers
See Section A.4, “Decompressor Class Configuration Registers (DCCR0-15)” for the registers of the
ICDU.
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Chapter 5
Unified System Interface Unit (USIU) Overview
The unified system interface unit (USIU) of the MPC561/MPC563 consists of several functional modules
that control system start-up, system initialization and operation, system protection, and the external system
bus. The MPC561/MPC563 USIU functions include the following and are discussed in the designated
chapters:
• System configuration and protection with GPIO capability and an enhanced interrupt controller.
Refer to Chapter 6, “System Configuration and Protection.”
• System reset monitoring and generation, refer to Chapter 7, “Reset.”
• Clock synthesis, power management, and debug support. Refer to Chapter 8, “Clocks and Power
Control.”
• External bus interface (EBI), refer to Chapter 9, “External Bus Interface.”
• Memory controller that supports four memory banks. Refer to Chapter 10, “Memory Controller.”
The USIU provides system configuration and protection features that control the overall system
configuration and supply various monitors and timers including the bus monitor, software watchdog timer,
periodic interrupt timer, decrementer, time base, and real-time clock. Freeze support and low power stop
is provided. The interrupt controller supports up to eight external interrupts, eight levels for all internal
USIU interrupt sources and 32 levels for internal peripheral modules on the IMB bus. It has an enhanced
mode of operation, which simplifies the MPC561/MPC563 interrupt structure and speeds up interrupt
processing.
Additionally, the USIU provides several pinout configurations that allow up to 64 general-purpose I/O,
external 32-bit port that supports internal and external masters, and various debug functions.
Reset logic for the MPC561/MPC563 provides soft and hard resets, checkstop and watchdog resets, and
other types of reset. The reset status register (RSR) reflects the most recent source to cause a reset.
The clock synthesizer generates the clock signals used by the USIU as well as the other modules and
external devices. This circuitry can generate a system clock from a range of crystals, typically in the 4 MHz
or 20 MHz range.
The USIU supports various low-power modes. Each one supplies a different range of power consumption,
functionality and wake-up time. Refer to Chapter 8, “Clocks and Power Control,” for details.
The EBI handles the transfer of information between the internal busses and the memory or peripherals in
the external address space. The MPC561/MPC563 is designed to allow external bus masters to request and
obtain mastership of the system bus, and if required access the on-chip memory and registers. Refer to
Chapter 9, “External Bus Interface,” for details.
The memory controller module provides glueless interface to many types of memory devices and
peripherals. It supports up to four memory banks. Refer to Chapter 10, “Memory Controller,” for details.
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Unified System Interface Unit (USIU) Overview
The USIU supports the internal Flash censorship mechanism on the MPC561/MPC563 to protect the Flash
contents. Refer to Chapter 21, “CDR3 Flash (UC3F) EEPROM.” It is not possible to operate the
MPC561/MPC563 from the external world while the Flash is in censorship mode and in a censorship state.
The internal Flash array will be either locked or accessible only after the entire array contents have been
erased. The MPC561/MPC563 is in censored mode if one of the following events occurs:
• booting from external memory
• operating in peripheral mode or if accessed from an external master
• operating in debug mode (BDM or Nexus)
Figure 5-1 shows the USIU block diagram.
USIU
Memory Control Lines
Memory
Controller
U-Bus
U-bus
Interface
Address
E-bus
Interface
E-Bus
•
•
•
•
•
•
•
•
Configuration Registers
Software Watchdog
Bus Monitor
Periodic Interrupt
Timer and Decrementer
Real-time Clock
Debug
Pin Multiplexing
Interrupt Controller
Sub bus
Data
Slave
Interface
SGPIO
Clocks & Reset
Figure 5-1. USIU Block Diagram
5.1
Memory Map and Registers
Table 5-1 is an address map of the USIU registers and, unless otherwise noted, registers are 32 bits wide.
The address shown for each register is relative to the base address of the MPC561/MPC563 internal
memory map. The internal memory block can reside in one of eight possible 4 Mbyte memory spaces. See
Figure 1-3 for details.
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Unified System Interface Unit (USIU) Overview
Table 5-1. USIU Address Map
Address
Register
0x2F C000
USIU Module Configuration Register (SIUMCR)
See Table 6-7 for bit descriptions.
0x2F C004
System Protection Control Register (SYPCR)
See Table 6-15 for bit descriptions.
0x2F C008
Reserved
0x2F C00E1
Software Service Register (SWSR)
See Table 6-16 for bit descriptions.
0x2F C010
Interrupt Pending Register (SIPEND).
0x2F C014
Interrupt Mask Register (SIMASK)
See Section 6.2.2.2.4, “SIU Interrupt Mask Register (SIMASK),” for bit descriptions.
0x2F C018
Interrupt Edge Level Mask (SIEL)
See Section 6.2.2.2.7, “SIU Interrupt Edge Level Register (SIEL),” for bit descriptions.
0x2F C01C
Interrupt Vector (SIVEC)
See Section 6.2.2.2.8, “SIU Interrupt Vector Register (SIVEC),” for bit descriptions.
0x2F C020
Transfer Error Status Register (TESR)
See Table 6-17 for bit descriptions.
0x2F C024
USIU General-Purpose I/O Data Register (SGPIODT1)
See Table 6-23 for bit descriptions.
0x2F C028
USIU General-Purpose I/O Data Register 2 (SGPIODT2)
See Table 6-24 for bit descriptions.
0x2F C02C
USIU General-Purpose I/O Control Register (SGPIOCR)
See Table 6-25 for bit descriptions.
0x2F C030
External Master Mode Control Register (EMCR)
See Table 6-13 for bit descriptions.
0x2F C038
Pads Module Configuration Register 2 (PDMCR2)
See Table 2-6 for bit descriptions.
0x2F C03C
Pads Module Configuration Register (PDMCR)
See Table 2-5 for bit descriptions.
0x2F C040
Interrupt Pend2 Register (SIPEND2)
See Section 6.2.2.2.2, “SIU Interrupt Pending Register 2 (SIPEND2),” for bit descriptions.
0x2F C044
Interrupt Pend3 Register (SIPEND3)
See Section 6.2.2.2.3, “SIU Interrupt Pending Register 3 (SIPEND3),” for bit descriptions.
0x2F C048
Interrupt Mask2 Register (SIMASK2)
See Section 6.2.2.2.5, “SIU Interrupt Mask Register 2 (SIMASK2),” for details.
0x2F C04C
Interrupt Mask3 Register (SIMASK3)
See Section 6.2.2.2.6, “SIU Interrupt Mask Register 3 (SIMASK3),” for details.
0x2F C050
Interrupt In-Service2 Register (SISR2)
See Section 6.2.2.2.9, “Interrupt In-Service Registers (SISR2 and SISR3),” for details.
0x2F C054
Interrupt In-Service3 Register (SISR3)
See Section 6.2.2.2.9, “Interrupt In-Service Registers (SISR2 and SISR3),” for details.
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Unified System Interface Unit (USIU) Overview
Table 5-1. USIU Address Map (continued)
Address
0x2F C0FC–0x2F
C0FF
Register
Reserved
Memory Controller Registers
0x2F C100
Base Register 0 (BR0)
See Table 10-8 for bit descriptions.
0x2F C104
Option Register 0 (OR0)
See Table 10-10 for bit descriptions.
0x2F C108
Base Register 1 (BR1)
See Table 10-8 for bit descriptions.
0x2F C10C
Option Register 1 (OR1)
See Table 10-10 for bit descriptions.
0x2F C110
Base Register 2 (BR2)
See Table 10-8 for bit descriptions.
0x2F C114
Option Register 2 (OR2)
See Table 10-10 for bit descriptions.
0x2F C118
Base Register 3 (BR3)
See Table 10-8 for bit descriptions.
0x2F C11C
Option Register 3 (OR3)
See Table 10-10 for bit descriptions.
0x2F C120–0x2F C13C Reserved
0x2F C140
Dual-Mapping Base Register (DMBR)
See Table 10-11 for bit descriptions.
0x2F C144
Dual-Mapping Option Register (DMOR)
See Table 10-12 for bit descriptions.
0x2F C148–0x2F C174 Reserved
0x2F C1781
0x2F C17A–0x2F
C1FC
Memory Status (MSTAT)
See Table 10-7 for bit descriptions.
Reserved
System Integration Timers
0x2F C200
Time Base Status and Control (TBSCR)
See Table 6-18 for bit descriptions.
0x2F C204
Time Base Reference 0 (TBREF0)
See Section 6.2.2.4.3, “Time Base Reference Registers (TBREF0 and TBREF1),” for bit
descriptions.
0x2F C208
Time Base Reference 1 (TBREF1)
See Section 6.2.2.4.3, “Time Base Reference Registers (TBREF0 and TBREF1),” for bit
descriptions.
0x2F C20C–0x2F
C21C
Reserved
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Unified System Interface Unit (USIU) Overview
Table 5-1. USIU Address Map (continued)
Address
Register
0x2F C220
Real-Time Clock Status and Control (RTCSC)
See Table 6-19 for bit descriptions.
0x2F C224
Real-Time Clock (RTC)
See Section 6.2.2.4.6, “Real-Time Clock Register (RTC),” for bit descriptions.
0x2F C228
Real-Time Alarm Seconds (RTSEC) — Reserved
0x2F C22C
Real-Time Alarm (RTCAL)
See Section 6.2.2.4.7, “Real-Time Clock Alarm Register (RTCAL),” for bit descriptions.
0x2F C230–0x2F C23C Reserved
0x2F C240
PIT Status and Control (PISCR)
See Table 6-20 for bit descriptions.
0x2F C244
PIT Count (PITC)
See Table 6-21 for bit descriptions.
0x2F C248
PIT Register (PITR)
See Table 6-22 for bit descriptions.
0x2F C24C–0x2F
C27C
Reserved
Clocks and Reset
0x2F C280
System Clock Control Register (SCCR)
See Table 8-9 for bit descriptions.
0x2F C284
PLL Low-Power and Reset Control Register (PLPRCR)
See Table 8-11 for bit descriptions.
0x2F C2881
Reset Status Register (RSR)
See Table 7-3 for bit descriptions.
0x2F C28C1
Change of Lock Interrupt Register (COLIR)
See Table 8-12 for bit descriptions.
0x2F C2901
IRAMSTBY Control Register (VSRCR)
See Table 8-13 for bit descriptions.
0x2F C294–0x2F C2FC Reserved
System Integration Timer Keys
0x2F C300
Time Base Status and Control Key (TBSCRK)
See Table 8-8 for bit descriptions.
0x2F C304
Time Base Reference 0 Key (TBREF0K)
See Table 8-8 for bit descriptions.
0x2F C308
Time Base Reference 1 Key (TBREF1K)
See Table 8-8 for bit descriptions.
0x2F C30C
Time Base and Decrementor Key (TBK)
See Table 8-8 for bit descriptions.
0x2F C310–0x2F C31C Reserved
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Table 5-1. USIU Address Map (continued)
Address
Register
0x2F C320
Real-Time Clock Status and Control Key (RTCSCK)
See Table 8-8 for bit descriptions.
0x2F C324
Real-Time Clock Key (RTCK)
See Table 8-8 for bit descriptions.
0x2F C328
Real-Time Alarm Seconds Key (RTSECK)
See Table 8-8 for bit descriptions.
0x2F C32C
Real-Time Alarm Key (RTCALK)
See Table 8-8 for bit descriptions.
0x2F C330–0x2F C33C Reserved
0x2F C340
PIT Status and Control Key (PISCRIK)
See Table 8-8 for bit descriptions.
0x2F C344
PIT Count Key (PITCK)
See Table 8-8 for bit descriptions.
0x2F C348–0x2F C37C Reserved
Clocks and Reset Keys
0x2F C380
System Clock Control Key (SCCRK)
See Table 8-8 for bit descriptions.
0x2F C384
PLL Low-Power and Reset Control Register Key (PLPRCRK)
See Table 8-8 for bit descriptions.
0x2F C388
Reset Status Register Key (RSRK)
See Table 8-8 for bit descriptions.
0x2F C38C–0x2F
C3FC
1
5.1.1
Reserved
16-bit register.
USIU Special-Purpose Registers
Table 5-2 lists the MPC561/MPC563 special purpose registers (SPR) used by the USIU. These registers
reside in an alternate internal memory space that can only be accessed with the mtspr and mfspr
instructions, or from an external master (refer to Section 6.1.2, “External Master Modes,” for details). All
registers are 32 bits wide.
NOTE
RCPU special purpose registers cannot be accessed by an external master.
Only SPRs in the USIU can be accessed by an external master.
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Unified System Interface Unit (USIU) Overview
Table 5-2. USIU Special-Purpose Registers
Internal
Address[0:31]
1
Decimal Address
spr[5:9]:spr[0:4]1
Register
0x2C00
Decrementer (DEC).
See Section 3.9.5, “Decrementer Register
(DEC),” for more information.
22
0x1880
Time Base Lower — Read (TBL).
See Section 6.2.2.4.2, “Time Base SPRs (TB),”
for bit descriptions.
268
0x1A80
Time Base Upper — Read (TBU).
See Section 6.2.2.4.2, “Time Base SPRs (TB),”
for bit descriptions.
269
0x3880
Time Base Lower — Write (TBL).
SeeSee Section 6.2.2.4.2, “Time Base SPRs
(TB),” for bit descriptions.
284
0x3A80
Time Base Upper — Write (TBU).
See Section 6.2.2.4.2, “Time Base SPRs (TB),”
for bit descriptions.
285
0x3D30
Internal Memory Mapping Register (IMMR).
See Table 6-12 for bit descriptions.
638
Bits [0:17] and [28:31] are all 0.
Table 5-3 shows the MPC561/MPC563 address format for special purpose register access. For an external
master, accessing an MPC500 SPR, address bits [0:17] and [28:31] are compared to zeros to confirm that
an SPR access is valid. See Section 6.1.2.1, “Operation in External Master Modes,” for more details.
.
Table 5-3. Hex Address Format for SPR Cycles
A[0:17]
A[18:22]
A[23:27]
A[28:31]
0
spr5:9
spr0:4
0
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Chapter 6
System Configuration and Protection
The MPC561/MPC563 incorporateDMAes many system functions that normally must be provided in
external circuits. In addition, it is designed to provide maximum system safeguards against hardware and
software faults. The system configuration and protection sub-module provides the following features:
• System Configuration (Section 6.1.1, “System Configuration”)—The USIU allows the
configuration of the system according to the particular requirements. The functions include control
of show cycle operation, pin multiplexing, and internal memory map location. System
configuration also includes a register containing part and mask number constants to identify the
part in software.
• External Master Modes Support (Section 6.1.2, “External Master Modes”)—External master
modes are special modes of operation that allow an alternate master on the external bus to access
the internal modules for debugging and backup purposes.
• General-Purpose I/O (Section 6.1.3, “USIU General-Purpose I/O ”)—The USIU provides 64 pins
for general-purpose I/O. The SGPIO pins are multiplexed with the address and data pins.
• Enhanced Interrupt Controller (Section 6.1.4, “Enhanced Interrupt Controller”)—The interrupt
controller receives interrupt requests from a number of internal and external sources and directs
them on a single interrupt-request line to the RCPU.
• Bus Monitor (Section 6.1.5, “Hardware Bus Monitor”)—The SIU provides a bus monitor to watch
internal to external accesses. It monitors the transfer acknowledge (TA) response time for internal
to external transfers. A transfer error acknowledge (TEA) is asserted if the TA response limit is
exceeded. This function can be disabled.
• Decrementer (Section 6.1.6, “Decrementer (DEC)”)—The DEC is a 32-bit decrementing counter
defined by the MPC500 architecture to provide a decrementer interrupt. This binary counter is
clocked by the same frequency as the time base (also defined by the MPC561/MPC563
architecture). The period for the DEC when driven by a 4-MHz oscillator can be up to 4295
seconds, which is approximately 71.6 minutes. Refer to Table 6-6.
• Time Base Counter (Section 6.1.7, “Time Base (TB)”)—The TB is a 64-bit counter defined by the
MPC500 architecture to provide a time base reference for the operating system or application
software. The TB has four independent reference registers that can generate a maskable interrupt
when the time-base counter reaches the value programmed in one of the four reference registers.
The associated bit in the TB status register will be set for the reference register which generated
the interrupt.
• Real-Time Clock (Section 6.1.8, “Real-Time Clock (RTC)”)—The RTC is used to provide
time-of-day information to the operating system or application software. It is composed of a 45-bit
counter and an alarm register. A maskable interrupt is generated when the counter reaches the value
programmed in the alarm register. The RTC is clocked by the same clock as the PIT.
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System Configuration and Protection
•
•
•
•
Periodic Interrupt Timer (Section 6.1.9, “Periodic Interrupt Timer (PIT)”)—The SIU provides a
timer to generate periodic interrupts for use with a real-time operating system or the application
software. The PIT provides a period from 1 µs to 4 seconds with a four-MHz crystal or 200 ns to
0.8 ms with a 20-MHz crystal. The PIT function can be disabled.
Software Watchdog Timer (Section 6.1.10, “Software Watchdog Timer (SWT)”)—The SWT
asserts a reset or non-maskable interrupt, as selected by the system protection control register
(SYPCR), if the software fails to service the SWT for a designated period of time (e.g., because the
software is trapped in a loop or lost). After a system reset, this function is enabled with a maximum
time-out period and asserts a system reset if the time-out is reached. The SWT can be disabled or
its time-out period can be changed in the SYPCR. Once the SYPCR is written, it cannot be written
again until a system reset.
Freeze Support (Section 6.1.11, “Freeze Operation”)—The SIU allows control of whether the
SWT, PIT, TB, DEC, and RTC should continue to run during freeze mode.
Low Power Stop (Section 6.1.12, “Low Power Stop Operation”)—In low power modes, specific
timers are frozen but others are not.
Figure 6-1 shows a block diagram of the system configuration and protection logic.
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System Configuration and Protection
Module
Configuration
Internal and
External Interrupt Requests
TA
Interrupt
Controller
Bus
Monitor
TS
Clock
TEA
Periodic Interrupt
Timer
Interrupt
Software
Watchdog Timer
Interrupt or
System Reset
Decrementer
Decrementer
Exception
Time Base Counter
Interrupt
Real-Time
Clock
Interrupt
Figure 6-1. System Configuration and Protection Logic
6.1
System Configuration and Protection Features
The system configuration and protection sub-module provides features described in the following sections.
6.1.1
System Configuration
The SIU allows the configuration of the system according to the particular requirements. The functions
include control of show cycle operation, pin multiplexing, and internal memory map location. System
configuration also includes a register containing part and mask number constants to identify the part in
software.
System configuration registers include the SIU module configuration register (SIUMCR), and the internal
memory mapping register (IMMR). Refer to Section 6.2.2, “System Configuration and Protection
Registers,” for register diagrams and bit descriptions.
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System Configuration and Protection
6.1.1.1
USIU Pin Multiplexing
Some of the functions defined in the various sections of the USIU (external bus interface, memory
controller, and general-purpose I/O) share pins. Table 6-1 summarizes how the pin functions of these
multiplexed pins are assigned.
.
Table 6-1. USIU Pin Multiplexing Control
Pin Name
Multiplexing Controlled by:
IRQ0 / SGPIOC0 / MDO4
IRQ1 / RSV / SGPIOC1
IRQ2 / CR / SGPIOC2 / MTS
IRQ3 / KR / RETRY / SGPIOC3
IRQ4 / AT2 / SGPIOC4
IRQ5 / SGPIOC5 / MODCK1
IRQ6 / MODCK2
IRQ7 / MODCK3
At Power-On Reset: MODCK[1:3]
Otherwise: Programmed in SIUMCR
Note:MDO4 is controlled by READI enable.
SGPIOC6 / FRZ / PTR
SGPIOC7 / IRQOUT / LWP0
BG / VF0 / LWP1
BR / VF1 / IWP2
BB / VF2 / IWP3
IWP[0:1] / VFLS[0:1]
BI / STS
WE[0:3] / BE[0:3] / AT[0:3]
TDI/DSDI / MDI0
TCK / DSCK / MCKI
TDO / DSDO / MDO0
Programmed in SIUMCR and Hard Reset Configuration
Note:MDIO, MCKI, and MDO0 are controlled by READI enable.
DATA[0:31] / SGPIOD[0:31]
ADDR[8:31] / SGPIOA[8:31]
Programmed in SIUMCR
RSTCONF /TEXP
6.1.1.2
At Power-On Reset: RSTCONF
Otherwise: Programmed in SIUMCR
Arbitration Support
Two bits in the SIUMCR control USIU bus arbitration. The external arbitration (EARB) bit determines
whether arbitration is performed internally or externally. If EARB is cleared (internal arbitration), the
external arbitration request priority (EARP) bit determines the priority of an external master’s arbitration
request. The operation of the internal arbiter is described in Section 9.5.7.4, “Internal Bus Arbiter.”
6.1.2
External Master Modes
External master modes are special modes of operation that allow an alternative master on the external bus
to access the internal modules for debugging and backup purposes. They provide access to the internal
buses (U-bus and L-bus) and to the intermodule bus (IMB3).
There are two external master modes:
•
Peripheral mode (enabled by setting PRPM in the external master control (EMCR) register) uses a
special slave mechanism that shuts down the RCPU and an alternative master on the external bus
can perform accesses to any internal bus slave.
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System Configuration and Protection
•
Slave mode (enabled by setting EMCR[SLVM] and clearing EMCR[PRPM]) enables an external
master to access any internal bus slave while the RCPU is fully operational.
Both modes can be enabled and disabled by software. In addition, peripheral mode can be selected from
reset.
The internal bus is not capable of providing priority between internal RCPU accesses and external master
accesses. If the bandwidth of external master accesses is large, it is recommended that the system force
gaps between external master accesses in order to avoid suspension of internal RCPU activity.
The MPC561/MPC563 does not support burst accesses from an external master; only single accesses of 8,
16, or 32 bits can be performed. The MPC561/MPC563 asserts burst inhibit (BI) on any attempt to initiate
a burst access to internal memory.
The MPC561/MPC563 provides memory controller services for external master accesses (single and
burst) to external memories. See Chapter 10, “Memory Controller,” for details.
6.1.2.1
Operation in External Master Modes
The external master modes are controlled by the EMCR register, which contains the internal bus attributes.
The default attributes in the EMCR allow an external master to configure the EMCR with the required
attributes and access internal registers. The external master must be granted external bus ownership in
order to initiate the external master access. The SIU compares the address on the external bus to the
allocated internal address space. If the address is within the internal space, the access is performed with
the internal bus. The internal address space is determined according to IMMR[ISB] (see Section 6.2.2.1.2,
“Internal Memory Map Register (IMMR),” for details). The external master access is terminated by the
TA, TEA, or RETRY signal on the external bus.
A deadlock situation might occur if an internal-to-external access is attempted on the internal bus while an
external master access is initiated on the external bus. In this case, the SIU will assert RETRY on the
external bus in order to relinquish and retry the external access until the internal access is completed. The
internal bus will deny other internal accesses for the next eight clocks in order to complete the pending
accesses and prevent additional internal accesses from being initiated on the internal bus. The SIU will
also mask internal accesses to support consecutive external accesses if the delay between the external
accesses is less than four clocks. The external master access and retry timings are described in
Section 9.5.12, “Bus Operation in External Master Modes.”
The external master may access the internal MPC561/MPC563 special registers that are located outside
the RCPU. To access one of these special purpose registers (see Section 5.1.1, “USIU Special-Purpose
Registers”), EMCR[CONT] must be set and EMCR[SUPU] must be cleared. The external master can then
access the special register when it is provided the address according to the MPC561/MPC563 address map.
Only the first external master access that follows EMCR setting will be assigned to the special register
map; any subsequent accesses will be directed to the normal address map. This is done in order to enable
access to the EMCR again after the required MPC561/MPC563 special register access.
Peripheral mode does not require external bus arbitration between the external master and the internal
RCPU, since the internal RCPU is disabled. The BR and BB signals should be connected to ground, and
the internal bus arbitration should be selected in order to prevent the “slave” MPC561/MPC563 from
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System Configuration and Protection
occupying the external bus. Internal bus arbitration is selected by clearing SIUMCR[EARB] (see
Section 6.2.2.1.1, “SIU Module Configuration Register (SIUMCR)”).
6.1.2.2
Address Decoding for External Accesses
During an external master access, the USIU compares the external address with the internal address block
to determine if MPC561/MPC563 operation is required. Since only 24 of the 32 internal address bits are
available on the external bus, the USIU assigns zeros to the most significant address bits (ADDR[0:7]).
The address compare sequence can be summarized as follows:
• Normal external access. If EMCR[CONT] is cleared, the address is compared to the internal
address map. Refer to Section 6.2.2.1.3, “External Master Control Register (EMCR)”.
— MPC561/MPC563 special register external access. If EMCR[CONT] is set by the previous
external master access, the address is compared to the MPC561/MPC563 special address
range. See Section 5.1.1, “USIU Special-Purpose Registers,” for a list of the SPRs in the USIU.
— Memory controller external access. If the first two comparisons do not match, the internal
memory controller determines whether the address matches an address assigned to one of the
regions. If it finds a match, the memory controller generates the appropriate chip select and
attribute accordingly
When trying to fetch an MPC561/MPC563 special register from an external master, the address might be
aliased to one of the external devices on the external bus. If this device is selected by the
MPC561/MPC563 internal memory controller, this aliasing does not occur since the chip select is
disabled. If the device has its own address decoding or is being selected by external logic, this case is
resolved.
NOTE
This section does not address slave accesses to internal resources. For
internal resources, the accesses compare against ADDR[8:9] = ISB[1:2].
ISB0 must be cleared.
6.1.3
USIU General-Purpose I/O
The USIU provides 64 general-purpose I/O (SGPIO) pins (See Table 6-2). The SGPIO pins are
multiplexed with the address and data pins. In single-chip mode, where communicating with external
devices is not required, all 64 SGPIO pins can be used. In multiple-chip mode, only eight SGPIO pins are
available. Another configuration allows the use of the address bus for instruction show cycles while the
data bus is dedicated to SGPIO functionality. The functionality of these pins is assigned by the single-chip
(SC) bit in the SIUMCR. (See Section 6.2.2.1.1, “SIU Module Configuration Register (SIUMCR).”)
SGPIO pins are grouped as follows:
• Six groups of eight pins each, whose direction is set uniformly for the whole group
• 16 single pins whose direction is set separately for each pin
Table 6-2 describes the SGPIO signals, and all available configurations. The SGPIO registers are
described in Section 6.2.2.5, “General-Purpose I/O Registers.”
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
System Configuration and Protection
Table 6-2. SGPIO Configuration
SGPIO
Group Name
1
Individual
Pin Control
Direction
Control
Available
Available
Available
Available
When SC = 10
When SC = 00 When SC = 01
When SC = 11
(Single-Chip
(32-bit Port
(16-bit Port
(Single-Chip
Mode with
Size Mode)
Size Mode)
Mode)
Trace)
SGPIOD[0:7]
GDDR0
X
X
SGPIOD[8:15]
GDDR1
X
X
SGPIOD[16:23]
GDDR2
X
X
X
X
X
X
SGPIOD[24:31]
X
SDDRD[23:31]
SGPIOC[0:7]1
X
SDDRC[0:7]
SGPIOA[8:15]
GDDR3
X
SGPIOA[16:23]
GDDR4
X
SGPIOA[24:31]
GDDR5
X
SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See Section 6.2.2.1.1, “SIU Module
Configuration Register (SIUMCR).”
Figure 6-2 illustrates the functionality of the SGPIO.
Read Path
Internal
Bus
Read
GPIO
Read
Register
GPIO
Write
Register
Write
Write Path
OE
Clock
Write
SGPIO
Pad
Read
Path of Write Operation
Path of Read Operation
SGPIO Circuitry
Figure 6-2. Circuit Paths of Reading and Writing to SGPIO
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-7
System Configuration and Protection
6.1.4
Enhanced Interrupt Controller
6.1.4.1
•
•
•
•
•
•
Key Features
Significant interrupt latency reduction from that of the MPC555.
Simplified interrupt structure
Up to 48 different interrupt requests
Splitting of single external interrupt vector into up to 48 vectors, one for each source
Automatic lower priority requests masking
Full backward compatibility with MPC555/MPC556 (enhanced mode is software programmable.)
6.1.4.2
Interrupt Configuration
An overview of the MPC561/MPC563 interrupt structure is shown in Figure 6-3. The interrupt controller
receives interrupts from USIU internal sources, such as PIT, RTC, from the UIMB module (which has its
own interrupt controller) or from the IMB3 bus (directly from IMB modules) and from external pins
IRQ[0:7].
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System Configuration and Protection
DEC_IRQ to RCPU
SWT
I0
Level 7
U-bus INT Levels [0:7]
Level 4
Level 3
Level 2
Level 1
Level 0
8
I6
I5
I4
I3
I2
I1
I0
NMI to RCPU
Wake up from
low-power mode
16
IRQOUT
MUX
UIMB
Timers,
Change
of Lock
SIUMCR
[EICEN, LPMASKEN]
LPMASKEN
IMB3
Levels[0:7]
ilbs[0:1]
IMBIRQ
Sequencer
Enhanced Interrupt Controller
Internal
Bus
IREQ to RCPU
EICEN
48
SIVEC
Level7
Level5
imb_irq [0:6]
imb_irq [0:6] Level[0:6]
Level 6
I7
NMI
GEN
Regular Interrupt Controller
EDGE
DET
IRQ[0:7]
Selector
DEC
6
Offset in
BBC/IMPU
branch table
USIU
Figure 6-3. MPC561/MPC563 Interrupt Structure
If programmed to generate an interrupt, the SWT and external pin IRQ0 always generate an NMI,
non-maskable interrupt to the RCPU.
NOTE
The RCPU takes the system reset exception when an NMI is asserted, the
external interrupt exception for any other asserted interrupt request, and the
decrementer exception when the decrementer MSB changes from 0 to 1.
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Freescale Semiconductor
6-9
System Configuration and Protection
The decrementer interrupt request is not a part of the interrupt controller. Each one of the external pins
IRQ[1:7] has its own dedicated assigned priority level. IRQ0 is also mapped, but it should be used only as
a status bit indicating that IRQ0 was asserted and generated NMI interrupt. There are eight additional
interrupt priority levels. Each one of the SIU internal interrupt sources, or any of the peripheral module
interrupt sources can be assigned by software to any one of the eight interrupt priority levels. Thus, a very
flexible interrupt scheme is implemented. The interrupt request signal generated by the interrupt controller
is driven to the RPCU core and to the IRQOUT pin (optionally). This pin may be used in peripheral mode,
when the RCPU is disabled, and the internal modules are accessed externally. The IMB interrupts are
controlled by the UIMB. The IMB provides 32 interrupt levels, and any interrupt source could be
configured to any IMB interrupt level. The UIMB contains a 32-bit register that holds the IMB interrupt
requests, and maps them to the USIU eight interrupt levels.
NOTE
If one interrupt level was configured to more than one interrupt source, the
software should read the UIPEND register in the UIMB module, and the
particular status bits in order to identify which interrupt was asserted.
The interrupt controller may be programmed to operate in two modes—a regular mode or an enhanced
mode.
6.1.4.3
Regular Interrupt Controller Operation (MPC555/MPC556-Compatible
Mode)
In regular operation mode (default setting) the interrupt controller receives interrupt requests from internal
sources, such as timers, PLL lock detector, IMB modules and from external pins IRQ[0:7]. All the internal
interrupt sources may be programmed to drive one or more of eight U-bus interrupt level lines while the
RCPU, upon receiving an interrupt request, has to read the USIU and UIMB status register in order to
determine the interrupt source.
The SIVEC register contains an 8-bit code representing the unmasked interrupt request which has the
highest priority level. The priority between all interrupt sources for the regular interrupt controller
operation is shown in Table 6-3.
Table 6-3. Priority of Interrupt Sources—Regular Operation
Number
Priority
Level
Interrupt Source
Description
Offset in Branch
Table (Hex)
SIVEC Interrupt Code1
0
Highest
EXT_IRQ0
0x0000
00000000
1
—
Level 0
0x0008
00000100
2
—
EXT_IRQ1
0x0010
00001000
3
—
Level 1
0x0018
00001100
4
—
EXT_IRQ2
0x0020
00010000
5
—
Level 2
0x0028
00010100
6
—
EXT_IRQ3
0x0030
00011000
7
—
Level 3
0x0038
00011100
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Freescale Semiconductor
System Configuration and Protection
Table 6-3. Priority of Interrupt Sources—Regular Operation
1
Number
Priority
Level
Interrupt Source
Description
Offset in Branch
Table (Hex)
SIVEC Interrupt Code1
8
—
EXT_IRQ4
0x0040
00100000
9
—
Level 4
0x0048
00100100
10
—
EXT_IRQ5
0x0050
00101000
11
—
Level 5
0x0058
00101100
12
—
EXT_IRQ6
0x0060
00110000
13
—
Level 6
0x0068
00110100
14
—
EXT_IRQ7
0x0070
00111000
15
Lowest
Level 7
0x0078
00111100
This is the value in the 8 most significant bits of the SIVEC register (SIVEC[25:31]).
Each interrupt request from external lines and from USIU internal interrupt sources in the case of its
assertion will set a corresponding bit in SIPEND register. The individual SIPEND bits may be masked by
clearing an appropriate bit in SIMASK register.
6.1.4.4
Enhanced Interrupt Controller Operation
The enhanced interrupt controller operation may be turned on by setting the EICEN control bit in the
SIUMCR register. In this mode the 32 IMB interrupt levels will be latched by USIU using eight IMB
interrupt lines and two lines of ilbs via the time multiplexing scheme defined by the UIMB module. In
addition to the IMB interrupt sources the external interrupts and timer interrupts are available in the same
way as in the regular scheme. In this mode, the UIMB module does not drive U-bus interrupt level lines.
Each interrupt request will set a corresponding bit in SIPEND2 or SIPEND3 registers. SIPEND2 an
SIPEND3 may be masked by clearing an appropriate bit in SIMASK2 or SIMASK3 registers.
The priority logic is provided in order to determine the highest unmasked interrupt request, and interrupt
code is generated in the SIVEC register. See Table 6-4.
NOTE
If the enhanced interrupt controller is enabled, a delay is required prior to
re-enabling interrupts. Before clearing an interrupt related register, clear the
MSR[EE] bit (EE = 0). Expect a vector offset of 0x0 if an interrupt is cleared
or disabled while MSR[EE] = 1. This vector should be handled as if no
interrupt has occured, that is, perform an rfi instruction. After clearing an
interrupt source, sufficient time must elapse before re-enabling the
MSR[EE] bit (EE = 1). This time should take longer than the time needed
for a load of the same register that was just cleared. To guarantee enough
time, include this load instruction before the instruction that sets MSR[EE].
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Freescale Semiconductor
6-11
System Configuration and Protection
Table 6-4. Priority of Interrupt Sources—Enhanced Operation
Number
Priority Level
Interrupt Source
Description
Offset in Branch
,
Table (Hex)1 2
SIVEC Interrupt Code3
0
Highest
(see note above)4
0x0000
00000000
1
—
Level 0
0x0008
00000100
2
—
IMB_IRQ 0
0x0010
00001000
3
—
IMB_IRQ 1
0x0018
00001100
4
—
IMB_IRQ 2
0x0020
00010000
5
—
IMB_IRQ 3
0x0028
00010100
6
—
EXT_IRQ2
0x0030
00011000
7
—
Level 1
0x0038
00011100
8
—
IMB_IRQ 4
0x0040
00100000
9
—
IMB_IRQ 5
0x0048
00100100
10
—
IMB_IRQ 6
0x0050
00101000
11
—
IMB_IRQ 7
0x0058
00101100
12
—
EXT_IRQ2
0x0060
00110000
13
—
Level 2
0x0068
00110100
14
—
IMB_IRQ 8
0x0070
00111000
15
—
IMB_IRQ 9
0x0078
00111100
16
—
IMB_IRQ 10
0x0080
01000000
17
—
IMB_IRQ 11
0x0088
01000100
18
—
EXT_IRQ3
0x0090
01001000
19
—
Level 3
0x0098
01001100
20
—
IMB_IRQ 12
0x00A0
01010000
21
—
IMB_IRQ 13
0x00A8
01010100
22
—
IMB_IRQ 14
0x00B0
01011000
23
—
IMB_IRQ 15
0x00B8
01011100
24
—
EXT_IRQ4
0x00C0
01100000
25
—
Level 4
0x00C8
01100100
26
—
IMB_IRQ 16
0x00D0
01101000
27
—
IMB_IRQ 17
0x00D8
01101100
28
—
IMB_IRQ 18
0x00E0
01110000
29
—
IMB_IRQ 19
0x00E8
01110100
30
—
EXT_IRQ5
0x00F0
01111000
31
—
Level 5
0x00F8
01111100
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System Configuration and Protection
Table 6-4. Priority of Interrupt Sources—Enhanced Operation (continued)
Number
Priority Level
Interrupt Source
Description
Offset in Branch
,
Table (Hex)1 2
SIVEC Interrupt Code3
32
—
IMB_IRQ 20
0x0100
10000000
33
—
IMB_IRQ 21
0x0108
10000100
34
—
IMB_IRQ 22
0x0110
10001000
35
—
IMB_IRQ 23
0x0118
10001100
36
—
EXT_IRQ6
0x0120
10010000
37
—
Level 6
0x0128
10010100
38
—
IMB_IRQ 24
0x0130
10011000
39
—
IMB_IRQ 25
0x0138
10011100
40
—
IMB_IRQ 26
0x0140
10100000
41
—
IMB_IRQ 27
0x0148
10100100
42
—
EXT_IRQ7
0x0150
10101000
43
—
Level 7
0x0158
10101100
44
—
IMB_IRQ 28
0x0160
10110000
45
—
IMB_IRQ 29
0x0168
10110100
46
—
IMB_IRQ 30
0x0170
10111000
47
Lowest
IMB_IRQ 31
0x0178
10111100
1
The branch table feature can be used only if the BBCMCR[EIR] is set.
This offset is added to the table base address from the EIBDR register.
3 This is the value in the 8 most significant bits of the SIVEC register.
4 This vector is reserved and normally is not generated. It may be generated, if any other interrupt source disappears,
before being acknowleged by the RCPU as a result of any change in the interrupt scheme, module stopping, masking
interrupt sources in a module by application software while interrupts are enabled in the RCPU by setting MSR[EE].
2
The value of the SIVEC register is supplied internally to the BBC module and can be used as an offset to
the branch table start address for the external interrupt relocation feature. Thus a fast way to a specific
interrupt source routine is provided without software overhead. The BBCMCR (see Section 4.6.2.1, “BBC
Module Configuration Register (BBCMCR)”) and EIBADR (see Section 4.6.2.5, “External Interrupt
Relocation Table Base Address Register (EIBADR)”) registers must be programmed to enable this feature
in the BBC. Additionally, the SIPEND2 and SIPEND3 registers contain the information about all the
interrupt requests that are asserted at a given time, so that software can always read them.
NOTE
When the enhanced interrupt controller is enabled the SIPEND and
SIMASK registers are not used.
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System Configuration and Protection
6.1.4.4.1
Lower Priority Request Masking
This feature (if enabled) simplifies the masking of lower priority interrupt requests when a request of
certain priority is in service in applications that require interrupt nesting. The highest (pending) request is
also masked by itself. The masking is accomplished in the following way.
Upon asserting an interrupt request the BBC generates an acknowledge signal to notify the interrupt
controller that the request and the branch table offset have been latched. The interrupt controller then sets
a bit in the SISR register (interrupt in-service register), according to the asserted request. All other requests
whose priority is lower than or equal to the one that is currently in-service, become masked. The mask
remains set until the SISR bit is cleared by software (by the interrupt handler routine), writing a ‘1’ value
to the corresponding bit. The lower priority request masking diagram is presented in Figure 6-4.
The lower priority request masking feature is disabled by HRESET and it may be enabled by setting the
LPMASK_EN bit in the SIUMCR register.
NOTE
In the regular mode of the interrupt controller the lower priority request
masking feature is not available.
The feature must be activated only together with exception table relocation in the BBC module.
From bit i - 1
Enable
control bit
(LPMASK_EN)
To SIVEC
generation
SIPEND [i]
To RCPU
External
interrupt
request
generation
(OR between
all the bits)
SIMASK [i]
IMPU
acknowledge
Reset by
software
Set
SISR[i]
Reset
To bit i + 1
Figure 6-4. Lower Priority Request Masking—One Bit Diagram
6.1.4.4.2
Backward Compatibility with MPC555/MPC556
The enhanced interrupt controller is a feature that may be enabled according to a user’s application using
the EICEN control bit in SIUMCR register, which can be set and cleared at any time by software. If the bit
is cleared, the default interrupt controller operation is available, as described in Section 6.1.4.3, “Regular
Interrupt Controller Operation (MPC555/MPC556-Compatible Mode).” The regular operation is fully
compatible with the interrupt controller already implemented in MPC555/MPC556.
Figure 6-5 illustrates the interrupt controller functionality in the MPC561/MPC563.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-14
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System Configuration and Protection
IRQ
...... ...... ...... ......
8
SIEL
External
SIMASK
8
Synchronizer
U-bus INT
Levels[0:7]
SIPEND
Wake up from
low-power mode
16
......
From IMB:
ilbs[0:1]
5
SISR3
S
I
V
E
C
5
(6 from 48)
(Enables branch
to the highest priority
interrupt routine)
SISR2
48
Encoder
Enhanced Interrupt
Controller Enabled
32
Sequencer
IMB IRQ
8
SIPEND2 SIPEND3
IRQ[0:7]
SIMASK2 SIMASK3
Priority
Interrupt Vector
(offset to branch
table – to BBC)
0
MUX
1
Interrupt Request
(to RCPU and IRQOUT pad)
Figure 6-5. MPC561/MPC563 Interrupt Controller Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
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System Configuration and Protection
6.1.4.5
Interrupt Overhead Estimation for Enhanced Interrupt Controller Mode
The interrupt overhead consists of two main parts:
• Storage of general and special purpose registers
• Recognition of the interrupt source
The interrupt overhead can increase latency, and decrease the overall system performance. The overhead
of register saving time can be reduced by improving the operating system. The number of registers that
should be saved can be reduced if each interrupt event has its own interrupt vector. This solution solves
the interrupt source recognition overhead. Table 6-5 below illustrates the improvements.
Only registers required for the recognition routine are considered to be saved in the calculations below.
Recognition of module internal events/channels is out of the scope of the calculations. See also the typical
interrupt handler flowchart in Figure 6-6.
Table 6-5. Interrupt Latency Estimation for Three Typical Cases
MPC561/MPC563
Architecture Without Using
SIVEC
MPC561/MPC563
Architecture Using
Enhanced Interrupt
Controller Features
MPC561/MPC563 Architecture
Using SIVEC
Operation
Details
Interrupt propagation from
request module to RCPU —
8 clocks
Store of some GPR and
SPR—10 clocks
Read SIPEND—4 clocks
Read SIMASK—4 clocks
SIPEND data processing —
20 clocks
(find first set, access to LUT in
the Flash, branches)
Read UIPEND—4 clocks
UIPEND data processing—20
clocks
(find first set, access to LUT in
the Flash, branches)
Interrupt propagation from
request module to RCPU —
8 clocks
Store of some GPR and SPR
—10 clocks
Read SIVEC—4 clocks
Branch to routine—10 clocks
Read UIPEND—4 clocks
UIPEND data processing —
20 clocks
(find first set, access to LUT in
the Flash, branches)
Notes:
If there is a need to enable
nesting of interrupts during
source recognition procedure,
at least 30 clocks should be
added to the interrupt latency
estimation
To use this feature in compressed —
mode some undetermined
latency is added to make a
branch to compressed address of
the routine. This latency is
dependant on how the user code
is implemented.
Total:
At Least 70-80 Clocks
At Least 50-60 Clocks
Interrupt propagation from
request module to RCPU —
6 clocks
Store of some GPR and
SPR—10 clocks
Only one branch is executed to
reach the interrupt handler
routine of the device requesting
interrupt servicing—2 clocks
20 Clocks
NOTE
Compiler and bus collision overhead are not included in the calculations.
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System Configuration and Protection
.
Start
Saving the CPU
context
Masking lower
priority requests
Enabling
Interrupt
Handler body
Clearing interrupt
source
Disabling interrupt
Clearing in-service bit
Clearing mask
Restoring the CPU
context
Flow without lower priority
masking enabled
Flow with lower priority
masking enabled
RFI
Figure 6-6. Typical Interrupt Handler Routine
6.1.5
Hardware Bus Monitor
The bus monitor ensures that each bus cycle is terminated within a reasonable period of time. The USIU
provides a bus monitor option to monitor internal to external bus accesses on the external bus. The monitor
counts from transfer start to transfer acknowledge and from transfer acknowledge to transfer acknowledge
within bursts. If the monitor times out, transfer error acknowledge (TEA) is asserted internally by the
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System Configuration and Protection
MPC561/MPC563, and RCPU access is terminated with a data error, causing a machine check state or
exception.
The bus monitor timing bit in the system protection control register (SYPCR[BMT]) defines the bus
monitor time-out period. The programmability of the time-out allows for variation in system peripheral
response time. The timing mechanism is clocked by the external bus clock divided by eight. The maximum
value is 2040 system clock cycles.
SYPCR[BME] enables or disables the bus monitor. But regardless of the state of this bit the bus monitor
is always enabled when freeze is asserted in debug mode.
6.1.6
Decrementer (DEC)
The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC561/MPC563 architecture
to provide a decrementer interrupt. This binary counter is clocked by the same frequency as the time base
(also defined by the MPC500 architecture). The operation of the time base and decrementer are therefore
coherent. The DEC is clocked by the TMBCLK clock. The decrementer period is computed as follows:
TDEC =
232
FTMBCLK
The state of the DEC is not affected by any resets and should be initialized by software. The DEC runs
continuously after power-up once the time base is enabled by setting the TBE bit of the TBSCR (see
Table 6-18) (unless the clock module is programmed to turn off the clock). The decrementer continues
counting while reset is asserted.
Reading from the decrementer has no effect on the counter value. Writing to the decrementer replaces the
value in the decrementer with the value in the GPR.
Whenever bit 0 (the MSB) of the decrementer changes from zero to one, a decrementer exception occurs.
If software alters the decrementer such that the content of bit 0 is changed to a value of 1, a decrementer
exception occurs.
A decrementer exception causes a decrementer interrupt request to be pending in the RCPU. When the
decrementer exception is taken, the decrementer interrupt request is automatically cleared.
Table 6-6 illustrates some of the periods available for the decrementer, assuming a 4-MHz or 20-MHz
crystal, and TBS = 0 which selects TMBCLK division to 4.
NOTE
Time base must be enabled to use the decrementer. See Section 6.2.2.4.4,
“Time Base Control and Status Register (TBSCR),” for more information.
Table 6-6. Decrementer Time-Out Periods
Count Value
Time-Out @ 4 MHz
Time-Out @ 20 MHz
0
1.0 µs
0.2 µs
9
10 µs
2.0 µs
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System Configuration and Protection
Table 6-6. Decrementer Time-Out Periods (continued)
Count Value
Time-Out @ 4 MHz
Time-Out @ 20 MHz
99
100 µs
20 µs
999
1.0 ms
200 µs
9999
10.0 ms
2 ms
999999
1.0 s
200 ms
9999999
10.0 s
2.0 s
99999999
100.0 s
20 s
999999999
1000 s
200 s
(hex) FFFFFFFF
4295 s
859 s
Refer to Section 3.9.5, “Decrementer Register (DEC),” for more information.
6.1.7
Time Base (TB)
The time base (TB) is a 64-bit free-running binary counter defined by the MPC500 architecture. The TB
has two independent reference registers which can generate a maskable interrupt when the time base
counter reaches the value programmed in one of the two reference registers. The period of the TB depends
on the driving frequency. The TB is clocked by the TMBCLK clock. The period for the TB is:
64
2
T TB = -----------------------------F TMBCLK
The state of TB is not affected by any resets and should be initialized by software. Reads and writes of the
TB are restricted to special instructions. Separate special-purpose registers are defined in the MPC500
architecture for reading and writing the TB. For the MPC561/MPC563 implementation, it is not possible
to read or write the entire TB in a single instruction. Therefore, the mttb and mftb instructions are used to
move the lower half of the time base (TBL) while the mttbu and mftbu instructions are used to move the
upper half (TBU).
Two reference registers are associated with the time base: TBREF0 and TBREF1. A maskable interrupt is
generated when the TB count reaches to the value programmed in one of the two reference registers. Two
status bits in the time base control and status register (TBSCR) indicate which one of the two reference
registers generated the interrupt.
Refer to Section 6.2.2.4, “System Timer Registers,” for diagrams and bit descriptions of TB registers.
Refer to Section 3.9.4, “Time Base Facility (TB) — OEA,” and to the RCPU Reference Manual for
additional information.
6.1.8
Real-Time Clock (RTC)
The RTC is a 32-bit counter and pre-divider used to provide a time-of-day indication to the operating
system and application software as show in Figure 6-7. It is clocked by the PITRTCLK clock. The counter
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System Configuration and Protection
is not affected by reset and operates in all low-power modes. It is initialized by software. The RTC can be
programmed to generate a maskable interrupt when the time value matches the value programmed in its
associated alarm register. It can also be programmed to generate an interrupt once a second. A control and
status register is used to enable or disable the different functions and to report the interrupt source.
NOTE
PITRTCLK can be divided by 4 or 256. See Table 8-1 for default settings.
FREEZE
RTSEC
PITRTCLK
Clock
Clock
Disable
Sec
Interrupt
Divide
By 15625
MUX
32-bit Counter (RTC)
Divide
By 78125
Alarm
Interrupt
=
4-MHz/20-MHz crystal
32-bit Register (RTCAL)
Figure 6-7. RTC Block Diagram
6.1.9
Periodic Interrupt Timer (PIT)
The periodic interrupt timer consists of a 16-bit counter clocked by the PITRTCLK clock signal supplied
by the clock module as shown in Figure 6-8.
The 16-bit counter counts down to zero when loaded with a value from the PITC register. After the timer
reaches zero, the PS bit is set and an interrupt is generated if the PIE bit is a logic one. The software service
routine should read the PS bit and then write a zero to terminate the interrupt request. At the next input
clock edge, the value in the PITC is loaded into the counter, and the process starts over again.
When a new value is written into the PITC, the periodic timer is updated, the divider is reset, and the
counter begins counting. If the PS bit is not cleared, an interrupt request is generated. The request remains
pending until PS is cleared. If the PS bit is set again prior to being cleared, the interrupt remains pending
until PS is cleared.
Any write to the PITC stops the current countdown, and the count resumes with the new value in PITC. If
the PISCR[PTE] bit is not set, the PIT is unable to count and retains the old count value. Reads of the PIT
have no effect on the counter value.
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Freescale Semiconductor
System Configuration and Protection
PTE
PITC
(PISCR)
(PISCR)
16-bit
Modulus
Counter
Clock
Disable
PITRTCLK
Clock
PS (PISCR)
PIT
Interrupt
PIE (PISCR)
PITF (PISCR)
Figure 6-8. PIT Block Diagram
The timeout period is calculated as:
PITC + 1
PITC + 1
PIT PERIOD = ----------------------------------- = ----------------------------------------------F PITRTCLK
ExternalClock
〈 -----------------------------------------〉
4 or 256
Solving this equation using a 4-MHz external clock and a pre-divider of 256 gives:
PITC + 1
PIT PERIOD = -----------------------15625
This gives a range from 64 microseconds, with a PITC of 0x0000, to 4.19 seconds, with a PITC of 0xFFFF.
When a 20-MHz crystal is used with a pre-divider of 256, the range is between 12.8 microseconds to 0.84
seconds.
6.1.10
Software Watchdog Timer (SWT)
The software watchdog timer (SWT) prevents system lockout in case the software becomes trapped in
loops with no controlled exit. The SWT is enabled after system reset to cause a system reset if it times out.
The SWT requires a special service sequence to be executed on a periodic basis. If this periodic servicing
action does not occur, the SWT times out and issues a reset or a non-maskable interrupt (NMI), depending
on the value of the SWRI bit in the SYPCR register.
The SWT can be disabled by clearing the SWE bit in the SYPCR. Once the SYPCR is written by software,
the state of the SWE bit cannot be changed.
The SWT service sequence consists of the following two steps:
1. Write 0x556C to the software service register (SWSR)
2. Write 0xAA39 to the SWSR
The service sequence clears the watchdog timer and the timing process begins again. If any value other
than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start over.
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System Configuration and Protection
Although the writes must occur in the correct order prior to time-out, any number of instructions may be
executed between the writes. This allows interrupts and exceptions to occur, if necessary, between the two
writes.
Not 0x556C/Don’t Reload
Reset
0x556C/Don’t Reload
State 0
Waiting for 0x556C
State 1
Waiting for 0xAA39
0xAA39/Reload
Not 0x556C/Don’t Reload
Not 0xAA39/Don’t Reload
Figure 6-9. SWT State Diagram
Although most software disciplines support the watchdog concept, different systems require different
time-out periods. For this reason, the software watchdog provides a selectable range for the time-out
period.
In Figure 6-10, the range is determined by the value in the SWTC field. The value held in the SWTC field
is then loaded into a 16-bit decrementer clocked by the system clock. An additional divide by 2048
prescaler is used if necessary. The decrementer begins counting when loaded with a value from the
software watchdog timing count field (SWTC). After the timer reaches 0x0, a software watchdog
expiration request is issued to the reset or NMI control logic.
Upon reset, the value in the SWTC is set to the maximum value and is again loaded into the software
watchdog register (SWR), starting the process over. When a new value is loaded into the SWTC, the
software watchdog timer is not updated until the servicing sequence is written to the SWSR. If the SWE
is loaded with the value zero, the modulus counter does not count (i.e. SWTC is disabled).
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
System Configuration and Protection
SWSR
Service
Logic
SWE
(SYPCR)
System
Clock
Clock
Disable
SWTC
Divide By
2048
Reload
MUX
16-bit
SWR/Decrementer
Rollover = 0
Reset
or NMI
FREEZE
Time-out
SWP
(SYPCR)
Figure 6-10. SWT Block Diagram
6.1.11
Freeze Operation
When the FREEZE line is asserted, the clocks to the software watchdog, the periodic interrupt timer, the
real-time clock, the time base counter, and the decrementer can be disabled. This is controlled by the
associated bits in the control register of each timer. If programmed to stop during FREEZE assertion, the
counters maintain their values while FREEZE is asserted. The bus monitor remains enabled regardless of
this signal.
6.1.12
Low Power Stop Operation
When the processor is set in a low-power mode (doze, sleep, or deep-sleep), the software watchdog timer
is frozen. It remains frozen and maintains its count value until the processor exits this state and resumes
executing instructions.
The periodic interrupt timer, decrementer, and time base are not affected by these low-power modes. They
continue to run at their respective frequencies. These timers are capable of generating an interrupt to bring
the MCU out of these low-power modes.
6.2
Memory Map and Register Definitions
This section provides the MPC561/MPC563 memory map, register diagrams and bit descriptions of the
system configuration and protection registers.
6.2.1
Memory Map
The MPC561/MPC563 internal memory space can be assigned to one of eight locations.
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System Configuration and Protection
The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of
eight locations by programming the ISB field in the internal memory mapping register (IMMR). The eight
possible locations are the first eight 4-Mbyte memory blocks starting with address 0x0000 0000. (Refer to
Figure 6-11.)
0x0000 0000
0x003F FFFF
0x0040 0000
0X007F FFFF
0X0080 0000
0x00BF FFFF
0x00C0 0000
Internal 4-Mbyte Memory Block
(Resides in one of eight locations)
0x00FF FFFF
0x0100 0000
0x013F FFFF
0x0140 0000
0x017F FFFF
0x0180 0000
0x01BF FFFF
0x01C0 0000
0x01FF FFFF
0xFFFF FFFF
Figure 6-11. MPC561/MPC563 Memory Map
6.2.2
System Configuration and Protection Registers
This section describes the MPC561/MPC563 registers.
6.2.2.1
System Configuration Registers
System configuration registers include the SIUMCR, the IMMR, and the EMCR registers.
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System Configuration and Protection
6.2.2.1.1
SIU Module Configuration Register (SIUMCR)
The SIUMCR contains bits which configure various features in the SIU module. The register contents are
shown below.
MSB
0
1
Field EARB
2
3
4
EARP
5
6
7
—
HRESET ID01
8
9
11
12
DBGC
—
ATWC
ID[9:10]1
ID111
ID121
27
28
LPMASK
_EN
BURST
_EN
DSHW
000_0000_0
Addr
10
13
14
GPC
15
DLK
000
0x2F C000
LSB
16
1
17
18
Field
—
SC
HRESET
0
ID[17:18]1
19
20
21
RCTX MLRC
22
23
—
24
25
26
NOS EICEN
MTSC HOW
29
30
31
—
0_0000_0000_0000
The reset value is a reset configuration word value, extracted from the internal data bus line. Refer to Section 7.5.2, “Hard
Reset Configuration Word (RCW).”
Figure 6-12. SIU Module Configuration Register (SIUMCR)
WARNING
All SIUMCR fields which are controlled by the reset configuration word
should not be changed by software while the corresponding functions are
active.
Table 6-7. SIUMCR Bit Descriptions
Bits
Name
Description
0
EARB
External arbitration
0 Internal arbitration is performed
1 External arbitration is assumed
1:3
EARP
External arbitration request priority. This field defines the priority of an external master’s
arbitration request. This field is valid when EARB is cleared. Refer to Section 9.5.7.4, “Internal
Bus Arbiter,” for details.
4:7
—
8
DSHW
Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data
cycles to IMB modules and Flash EEPROM). This field is locked by the DLK bit. Note that
instruction show cycles are programmed in the ICTRL and L-bus data show cycles are
programmed in the L2UMCR.
0 Disable show cycles for all internal data cycles
1 Show address and data of all internal data cycles
9:10
DBGC
Debug pins configuration. Refer to Table 6-8.
11
DBPC
Reserved.
12
ATWC
Address write type enable configuration. This bit configures the pins to function as byte write
enables or address types for debugging purposes.
0 WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]1
1 WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
Reserved
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System Configuration and Protection
Table 6-7. SIUMCR Bit Descriptions (continued)
Bits
Name
13:14
GPC
This bit configures the pins as shown in Table 6-9.
15
DLK
Debug register lock
0 Normal operation
1 SIUMCR is locked and can be written only in test mode or when the internal freeze signal is
asserted.
16
—
Reserved
17:18
SC
Single-chip select. This field configures the functionality of the address and data buses.
Changing the SC field while external accesses are performed is not supported. Refer to
Table 6-10.
19
RCTX
Reset configuration/timer expired. During reset the RSTCONF/TEXP pin functions as
RSTCONF. After reset the pin can be configured to function as TEXP, the timer expired signal
that supports the low-power modes.
0 RSTCONF/TEXP functions as RSTCONF
1 RSTCONF/TEXP functions as TEXP
20:21
MLRC
Multi-level reservation control. This field selects between the functionality of the reservation logic
and IRQ pins, refer to Table 6-11.
22:23
—
24
MTSC
25
NOSHOW
Instruction show cycles disabled. If the NOSHOW bit is set (1), then all instruction show cycles
are NOT transmitted to the external bus.
26
EICEN
Enhanced interrupt controller enable. See Section 6.1.4.4, “Enhanced Interrupt Controller
Operation,” for more information.
0 Enhanced interrupt controller operates in regular mode (compatible with MPC555/MPC556)
1 Enhanced interrupt controller is enabled
27
1
Description
Reserved
Memory transfer start control.
0 IRQ2/CR/SGPIOC2/MTS functions according to the MLRC bits setting
1 IRQ2/CR/SGPIOC2/MTS functions as MTS
LPMASK_EN Low priority request masking enable.
0 Lower priority interrupt request masking is disabled
1 Lower priority interrupt request masking is enabled
28
BURST_EN
29:31
—
Burst enable.
0 Burst operation is enabled by the BBCMCR[BE]. Maximum burst length is fixed at 4 beats.
1 USIU initiated burst accesses on the external bus. Maximim burst length can be 4 or 8 beats
and this may be programmed per memory region. Refer to Section 10.2.5, “Burst Support,”
for more information.
Note: Do not assert TEA on the external bus for instruction fetch while
SIUMCR[BURST_EN] = 1. Do not place code at the last 8 words of a memory controller
region while SIUMCR[BURST_EN] = 1.
Reserved
WE/BE is selected per memory region by WEBS in the appropriate BR register in the memory controller.
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System Configuration and Protection
Table 6-8. Debug Pins Configuration
Pin Function
DBGC
IWP[0:1]/VFLS[0:1]
BI/STS
BG/VF0/LWP1
BR/VF1/IWP2
BB/VF2/IWP3
00
VFLS[0:1]
BI
BG
BR
BB
01
IWP[0:1]
STS
BG
BR
BB
10
VFLS[0:1]
STS
VF0
VF1
VF2
11
IWP[0:1]
STS
LWP1
IWP2
IWP3
Table 6-9. General Pins Configuration
Pin Function
GPC
FRZ/PTR/SGPIOC6
IRQOUT/LWP0/SGPIOC7
00
PTR
LWP0
01
SGPIOC6
SGPIOC7
10
FRZ
LWP0
11
FRZ
IRQOUT
Table 6-10. Single-Chip Select Field Pin Configuration
Pin Function
SC
DATA[0:15]/
SGPIOD[0:15]
DATA[16:31]
SGPIOD[16:31]
ADDR[8:31]/
SGPIOA[8:31]
00 (multiple chip, 32-bit port size)
DATA[0:15]
DATA[16:31]
ADDR[8:31]
01 (multiple chip, 16-bit port size
DATA[0:15]
SPGIOD[16:31]
ADDR[8:31]
10 (single-chip with address show
cycles for debugging)
SPGIOD[0:15]
SPGIOD[16:31]
ADDR[8:31]
11 (single-chip)
SPGIOD[0:15]
SPGIOD[16:31]
SPGIOA[8:31]
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System Configuration and Protection
Table 6-11. Multi-Level Reservation Control Pin Configuration
Pin Function
MLRC
IRQ0/
SGPIOC0/
MDO4
IRQ1/RSV/
SGPIOC1
IRQ2/CR/
SGPIOC2/MTS
IRQ3/KR/
RETRY /SGPIOC3
IRQ4/AT2/
SGPIOC4
IRQ5/
SGPIOC5/MODCK11
00
IRQ0
IRQ1
IRQ22
IRQ3
IRQ4
IRQ5/MODCK1
KR/RETRY
AT2
IRQ5/ MODCK1
SGPIOC3
SGPIOC4
SGPIOC5/MODCK1
KR/RETRY
AT2
SGPIOC5/MODCK1
01
IRQ0
RSV
CR
10
SGPIOC0
SGPIOC1
SGPIOC22
11
1
2
IRQ0
2
IRQ1
SGPIOC2
Operates as MODCK1 during reset.
This is true if MTSC is reset to 0. Otherwise, IRQ2/CR/SGPIOC2/MTS will function as MTS.
2
6.2.2.1.2
Internal Memory Map Register (IMMR)
The internal memory map register (IMMR) is a register located within the MPC561/MPC563 special
register space. The IMMR contains identification of a specific device as well as the base for the internal
memory map. Based on the value read from this register, software can deduce availability and location of
any on-chip system resources.
This register can be read by the mfspr instruction. The ISB field can be written by the mtspr instruction.
The PARTNUM and MASKNUM fields are mask programmed and cannot be changed.
MSB
0
1
2
Field
HRESET
3
4
5
6
7
8
9
10
PARTNUM
11
12
13
14
15
MASKNUM
0
0
1
1
0
X1
X1
X1
16
17
18
19
20
21
22
23
Read-Only Fixed Value
LSB
Field
HRESET
Addr
—
FLEN
0000
ID201
—
—
00
ID232
24
25
26
27
28
29
30
31
—
ISB
—
0000
ID[28:30]1
0
SPR 638
1 The
reset value is 101 for MPC561 and 110 for MPC563.
reset value is a reset configuration word value extracted from the indicated bits of the internal data bus. Refer to
Section 7.5.2, “Hard Reset Configuration Word (RCW).”
2 The
Figure 6-13. Internal Memory Mapping Register (IMMR)
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
System Configuration and Protection
Table 6-12. IMMR Bit Descriptions
Bits
Name
Description
0:7
PARTNUM
This read-only field is mask programmed with a code corresponding to the part number of
the part on which the SIU is located. It is intended to help factory test and user code which
is sensitive to part changes. This changes when the part number changes. For example, it
would change if any new module is added, if the size of any memory module is changed. It
would not change if the part is changed to fix a bug in an existing module. The MPC561 has
an ID of 0x35. The MPC563 has an ID of 0x36.
8:15
MASKNUM
This read-only field is mask programmed with a code corresponding to the mask number of
the part. It is intended to help factory test and user code which is sensitive to part changes.
16:19
—
20
FLEN
21:22
—
Reserved
23
—
Reserved. This bit should be programmed to 0 at all times.
24:27
—
Reserved
28:30
ISB
31
—
6.2.2.1.3
Reserved
Flash enable is a read-write bit. The default state of FLEN is negated, meaning that the boot
is performed from external memory. This bit can be set at reset by the reset configuration
word.
0 On-chip Flash memory is disabled, and all internal cycles to the allocated Flash address
space are mapped to external memory
1 On-chip Flash memory is enabled
This read-write field defines the base address of the internal memory space. The initial value
of this field can be configured at reset to one of eight addresses, and then can be changed
to any value by software. Internal base addresses are as follows:
000 0x0000 0000
001 0x0040 0000
010 0x0080 0000
011 0x00C0 0000
100 0x0100 0000
101 0x0140 0000
110 0x0180 0000
111 0x01C0 0000
Reserved
External Master Control Register (EMCR)
The external master control register selects the external master modes and determines the internal bus
attributes for external-to-internal accesses.
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6-29
System Configuration and Protection
MSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
26
27
28
29
30
15
—
0000_0000_0000_0000
HRESET
Addr
0x2F C030
LSB
16
17
Field PRPM SLVM
1
HRESET ID16
1
0
18
19
20
—
SIZE
0
01
21
22
SUPU INST
0
1
23
24
—
00
25
RESV CONT
1
1
—
0
TRAC SIZEN
1
1
31
—
00
The reset value is a reset configuration word value, extracted from the indicated internal data bus line. Refer to Section 7.5.2,
“Hard Reset Configuration Word (RCW).”
Figure 6-14. External Master Control Register (EMCR)
Table 6-13. EMCR Bit Descriptions
Bits
Name
Description
0:15
—
16
PRPM
Peripheral mode. In this mode, the internal RCPU core is shut off and an alternative master on
the external bus can access any internal slave module. The reset value of this bit is determined
by the reset configuration word bit 16. The bit can also be written by software.
0 Normal operation
1 Peripheral mode operation
17
SLVM
Slave mode (valid only if PRPM = 0). In this mode, an alternative master on the external bus can
access any internal slave module while the internal RCPU core is fully operational. If PRPM is
set, the value of SLVM is a “don’t care.”
0 Normal operation
1 Slave mode
18
—
19:20
SIZE
Size attribute. If SIZEN = 1, the SIZE bits controls the internal bus attributes as follows:
00 Double word (8 bytes)
01 Word (4 bytes)
10 Half word (2 bytes)
11 Byte
21
SUPU
Supervisor/user attribute. SUPU controls the supervisor/user attribute as follows:
0 Supervisor mode access permitted to all registers
1 User access permitted to registers designated “user access”
22
INST
Instruction attribute. INST controls the internal bus instruction attribute as follows:
0 Instruction fetch
1 Operand or non-CPU access
23:24
—
25
RESV
Reserved
Reserved
Reserved
Reservation attribute. RESV controls the internal bus reservation attribute as follows:
0 Storage reservation cycle
1 Not a reservation
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Freescale Semiconductor
System Configuration and Protection
Table 6-13. EMCR Bit Descriptions (continued)
Bits
Name
26
CONT
27
—
28
TRAC
Trace attribute. TRAC controls the internal bus program trace attribute as follows:
0 Program trace
1 Not program trace
29
SIZEN
External size enable control bit. SIZEN determines how the internal bus size attribute is driven:
0 Drive size from external bus signals TSIZE[0:1]
1 Drive size from SIZE0, SIZE1 in EMCR
30:31
—
6.2.2.2
Description
Control attribute. CONT drives the internal bus control bit attribute as follows:
0 Access to MPC561/MPC563 control register, or control cycle access
1 Access to global address map
Reserved
Reserved
SIU Interrupt Controller Registers
The SIU interrupt controller contains the following registers: SIPEND, SIPEND2 and SIPEND3 (interrupt
pending registers), SIMASK, SIMASK2 and SIMASK3 (interrupt mask registers), SIEL, SIVEC, SISR2
and SISR3.
The SIPEND and SIMASK registers are used when the interrupt controller is configured for regular,
MPC555/MPC556 compatible, operation. SIPEND2, SIPEND3, SIMASK2, SIMASK3, SISR2 and
SISR3 registers are used only when the interrupt controller is operating in enhanced interrupt mode.
SIPEND, SIPEND2 and SIPEND3 are 32-bit registers. Each bit in the register corresponds to an interrupt
request. The bits associated with internal exceptions indicate, if set, that an interrupt service is requested.
These bits reflect the status of the internal requesting device, and will be cleared when the appropriate
actions are initiated by software in the device itself. Writing to these bits has no effect.
The bits associated with the IRQ pins have a different behavior depending on the sensitivity defined for
them in the SIEL register. When the IRQ is defined as a “level” interrupt the corresponding bit behaves in
a manner similar to the bits associated with internal interrupt sources, (i.e., it reflects the status of the IRQ
pin). This bit can not be changed by software, it will be cleared when the external signal is negated. When
the IRQ is defined as an “edge” interrupt, if the corresponding bit is set, it indicates that a falling edge was
detected on the line. The bit must be reset by software by writing a ‘1’ to it.
The following acronym definitions apply to the various bits implemented in the SIU interrupt controller
registers.
Table 6-14. SIU Interrupt Controller – Bit Acronym Definitions
Name
Description
IRQn
Interrupt Signal n Request
LVLn
Interrupt Level n Request
IMBIRQn
Intermodule Bus Interrupt Level n Request
IRMn
Interrupt Signal n Mask
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System Configuration and Protection
Table 6-14. SIU Interrupt Controller – Bit Acronym Definitions
6.2.2.2.1
Name
Description
LVMn
Interrupt Level n Mask
EDn
Falling Edge Detect, Interrupt Signal n
WMn
Wakeup Mask, Interrupt Signal n
SIU Interrupt Pending Register (SIPEND)
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field IRQ0 LVL0 IRQ1 LVL1 IRQ2 LVL2 IRQ3 LVL3 IRQ4 LVL4 IRQ5 LVL5 IRQ6 LVL6 IRQ7 LVL7
SRESET
0000_0000_0000_0000
Addr
0x2F C010
LSB
16
17
18
19
20
21
22
23
Field
24
25
26
27
28
29
30
31
—
SRESET
0000_0000_0000_0000
Figure 6-15. SIU Interrupt Pending Register (SIPEND)
6.2.2.2.2
SIU Interrupt Pending Register 2 (SIPEND2)
MSB
0
Field IRQ0
1
LVL0
2
3
4
IMB IMB
IMB
IRQ0 IRQ1 IRQ2
5
6
7
IMB
IRQ3
IRQ1
LVL1
8
9
10
IMB IMB IMB
IRQ4 IRQ5 IRQ6
11
12
13
IMB
IRQ7
IRQ2
LVL2
27
28
29
14
15
IMB IMB
IRQ8 IRQ9
0000_0000_0000_0000
SRESET
Addr
0x2F C040
LSB
16
Field
SRESET
17
18
19
20
21
22
23
24
25
26
30
31
IMB
IMB IRQ3 LVL3 IMB
IMB
IMB
IMB IRQ4 LVL4 IMB
IMB
IMB
IMB IRQ5 LVL5
IRQ10 IRQ1
IRQ12 IRQ13 IRQ14 IRQ15
IRQ16 IRQ17 IRQ18 IRQ19
1
0000_0000_0000_0000
Figure 6-16. SIU Interrupt Pending Register 2 (SIPEND2)
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System Configuration and Protection
6.2.2.2.3
SIU Interrupt Pending Register 3 (SIPEND3)
MSB
0
Field
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB
IRQ20 IRQ21 IRQ22 IRQ23 6
6 IRQ24 IRQ25 IRQ26 IRQ27 7
7 IRQ28 IRQ29 IRQ30 IRQ31
SRESET
0000_0000_0000_0000
Addr
0x2F C044
LSB
16
17
Field
18
19
20
21
22
23
24
25
26
27
28
29
30
31
—
SRESET
0000_0000_0000_0000
Figure 6-17. SIU Interrupt Pending Register 3 (SIPEND3)
6.2.2.2.4
SIU Interrupt Mask Register (SIMASK)
SIMASK is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND register.
SIMASK2 is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND2 register.
SIMASK3 is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND3 register.
When the bit is set, it enables the generation of an interrupt request to the RCPU. SIMASK, SIMASK2,
SIMASK3 are updated by software and cleared upon reset. It is the responsibility of the software to
determine which of the interrupt sources are enabled at a given time.
NOTE
Disable external interrupts in the core prior to changing any interrupt
controller related register (SIMASK, SIPEND, SIEL, or SISR). Refer to
MSR[EE] bit description in Table 3-11 and the note regarding special
handling of the EIC in Section 6.1.4.4, “Enhanced Interrupt Controller
Operation.”
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-33
System Configuration and Protection
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
Field IRM0 LVM0 IRM1 LVM1 IRM2 LVM2 IRM3 LVM3 IRM4 LVM4 IRM5 LVM5 IRM6 LVM6 IRM7 LVM7
0000_0000_0000_0000
SRESET
Addr
0x2F C014
LSB
16
17
18
19
20
21
22
23
Field
25
26
27
28
29
30
31
—
SRESET
1
24
0000_0000_0000_0000
IRQ0 of the SIPEND register is not affected by the setting or clearing of the IRM0 bit of the SIMASK register. IRQ0 is a
non-maskable interrupt.
Figure 6-18. SIU Interrupt Mask Register (SIMASK)
6.2.2.2.5
SIU Interrupt Mask Register 2 (SIMASK2)
MSB
Field
0
1
IRQ01
LVL0
2
3
4
IMB IMB
IMB
IRQ0 IRQ1 IRQ2
5
6
7
IMB
IRQ3
IRQ1
LVL1
8
9
10
IMB IMB IMB
IRQ4 IRQ5 IRQ6
11
12
13
IMB
IRQ7
IRQ2
LVL2
27
28
29
14
15
IMB IMB
IRQ8 IRQ9
0000_0000_0000_0000
SRESET
Addr
0x2F C048
LSB
16
Field
SRESET
1
17
18
19
20
21
22
23
24
25
26
30
31
IMB
IMB IRQ3 LVL3 IMB
IMB
IMB
IMB IRQ4 LVL4 IMB
IMB
IMB
IMB IRQ5 LVL5
IRQ10 IRQ1
IRQ12 IRQ13 IRQ14 IRQ15
IRQ16 IRQ17 IRQ18 IRQ19
1
0000_0000_0000_0000
IRQ0 of the SIPEND2 register is not affected by the setting or clearing of the IRQ0 bit of the SIMASK2 register. IRQ0 is a
non-maskable interrupt
Figure 6-19. SIU Interrupt Mask Register 2 (SIMASK2)
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Freescale Semiconductor
System Configuration and Protection
6.2.2.2.6
SIU Interrupt Mask Register 3 (SIMASK3)
MSB
0
Field
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB
IRQ20 IRQ21 IRQ22 IRQ23 6
6 IRQ24 IRQ25 IRQ26 IRQ27 7
7 IRQ28 IRQ29 IRQ30 IRQ31
0000_0000_0000_0000
SRESET
Addr
0x2F C04C
LSB
16
17
18
19
20
21
22
23
Field
24
25
26
27
28
29
30
31
—
SRESET
0000_0000_0000_0000
Figure 6-20. SIU Interrupt Mask Register 3 (SIMASK3)
6.2.2.2.7
SIU Interrupt Edge Level Register (SIEL)
The SIEL is a 32-bit read/write register. Each pair of bits corresponds to an external interrupt request. The
EDx bit, if set, specifies that a falling edge in the corresponding IRQ line will be detected as an interrupt
request. When the EDx bit is 0, a low logical level in the IRQ line will be detected as an interrupt request.
The WMx (wake-up mask) bit, if set, indicates that an interrupt request detection in the corresponding line
causes the MPC561/MPC563 to exit low-power mode.
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7
HRESET
0000_0000_0000_0000
Addr
0x2F C018
LSB
16
17
Field
18
19
20
21
22
23
24
25
26
27
28
29
30
31
—
HRESET
0000_0000_0000_0000
Figure 6-21. SIU Interrupt Edge Level Register (SIEL)
6.2.2.2.8
SIU Interrupt Vector Register (SIVEC)
The SIVEC is a 32-bit read-only register that contains an 8-bit code representing the unmasked interrupt
source of the highest priority level. The SIVEC can be read as either a byte, half word, or word. When read
as a byte, a branch table can be used in which each entry contains one instruction (branch). When read as
a half-word, each entry can contain a full routine of up to 256 instructions. The interrupt code is defined
such that its two least significant bits are 0, thus allowing indexing into the table. The two possible ways
of the code usage are shown on Figure 6-23.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-35
System Configuration and Protection
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
Field
INTERRUPT CODE
—
Reset
0011_1100
0000_0000
Addr
13
14
29
30
15
0x2F C01C
LSB
16
17
18
19
20
21
22
23
24
Field
—
Reset
0000_0000_0000_0000
25
26
27
28
31
Figure 6-22. SIU Interrupt Vector Register (SIVEC)
INTR:...
Save state
R3 ← @SIVEC
R4 ← Base of branch table
...
lbz RX, R3 (0)# load as byte
add RX, RX, R4
mtsprCTR, RX
bctr
BASE
b
Routine1
BASE + 4
b
Routine2
BASE + 8
b
Routine3
BASE + C
b
Routine4
BASE +10
•
BASE + n
•
INTR:...
Save state
R3 ← @SIVEC
R4 ← Base of branch table
...
lhz RX, R3 (0)# load as half
add RX, RX, R4
mtspr CTR, RX
bctr
BASE
BASE + 400
BASE + 800
BASE + C00
BASE +1000
BASE + n
1st Instruction of Routine1
•
•
1st Instruction of Routine2
•
•
1st Instruction of Routine3
•
•
1st Instruction of Routine4
•
•
•
•
•
•
•
•
Figure 6-23. Example of SIVEC Register Usage for Interrupt Table Handling
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
System Configuration and Protection
6.2.2.2.9
Interrupt In-Service Registers (SISR2 and SISR3)
SISR2, SISR3 are 32-bit read/write registers. Each bit in the register corresponds to an interrupt request.
A bit is set if:
• There is a pending interrupt request (SIPEND2/3), that is not masked by (SIMASK2/3), and
• The BBC/IMPU acknowledges interrupt request and latches SIVEC value.
Once a bit is set, all requests with lower or equal priority become masked (i.e. they will not generate any
interrupt request to the RCPU) until the bit is cleared. A bit is cleared by writing a ‘1’ to it. Writing zero
has no effect.
MSB
0
1
Field IRQ0
2
LVL0
3
4
IMB IMB IMB
IRQ0 IRQ1 IRQ2
5
6
7
IMB
IRQ3
IRQ1
LVL1
SRESET
8
9
10
IMB IMB
IMB
IRQ4 IRQ5 IRQ6
11
12
13
IMB
IRQ7
IRQ2
LVL2
27
28
29
14
15
IMB IMB
IRQ8 IRQ9
0000_0000_0000_0000
Addr
0x2F C050
LSB
16
Field
17
18
19
20
21
22
23
24
25
26
30
31
IMB
IMB IRQ3 LVL4 IMB
IMB
IMB
IMB IRQ4 LVL4 IMB
IMB
IMB
IMB IRQ5 LVL5
IRQ10 IRQ11
IRQ12 IRQ13 IRQ14 IRQ15
IRQ16 IRQ17 IRQ18 IRQ19
SRESET
0000_0000_0000_0000
Figure 6-24. Interrupt In-Service Register 2 (SISR2)
MSB
0
Field
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB
IRQ20 IRQ21 IRQ22 IRQ23 6
6 IRQ24 IRQ25 IRQ26 IRQ27 7
7 IRQ28 IRQ29 IRQ30 IRQ31
SRESET
0000_0000_0000_0000
Addr
0x2F C054
LSB
16
17
18
19
20
21
22
Field
23
24
25
26
27
28
29
30
31
—
SRESET
0000_0000_0000_0000
Figure 6-25. Interrupt In-Service Register 3 (SISR3)
6.2.2.3
6.2.2.3.1
System Protection Registers
System Protection Control Register (SYPCR)
The system protection control register (SYPCR) controls the system monitors, the software watchdog
period, and the bus monitor timing. This register can be read at any time, but can be written only once after
system reset.
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Freescale Semiconductor
6-37
System Configuration and Protection
MSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
26
27
28
29
30
15
SWTC
1111_1111_1111_1111
HRESET
Addr
0x2F C004
LSB
16
17
18
19
Field
HRESET
20
21
22
23
24
25
BMT
BME
—
1111_1111
0
000
31
SWF SWE SWRI SWP
0
1
1
1
Figure 6-26. System Protection Control Register (SYPCR)
Table 6-15. SYPCR Bit Descriptions
Bits
Name
0:15
SWTC
16:23
BMT
Bus monitor timing. This field specifies the time-out period, in eight-system-clock resolution, of
the bus monitor. BMT must be set to non zero even if the bus monitor is not enabled.
24
BME
Bus monitor enable
0 Disable bus monitor
1 Enable bus monitor
25:27
—
28
SWF
Software watchdog freeze
0 Software watchdog continues to run while FREEZE is asserted
1 Software watchdog stops while FREEZE is asserted
29
SWE
Software watchdog enable. Software should clear this bit after a system reset to disable the
software watchdog timer.
0 Watchdog is disabled
1 Watchdog is enabled
30
SWRI
Software watchdog reset/interrupt select
0 Software watchdog time-out causes a non-maskable interrupt to the RCPU
1 Software watchdog time-out causes a system reset
31
SWP
Software watchdog prescale
0 Software watchdog timer is not prescaled
1 Software watchdog timer is prescaled by 2048
6.2.2.3.2
Description
Software watchdog timer count. This field contains the count value of the software watchdog
timer.
Reserved
Software Service Register (SWSR)
The SWSR is the location to which the SWT servicing sequence is written. To prevent SWT time-out, a
0x556C followed by 0xAA39 should be written to this register. The SWSR can be written at any time but
returns all zeros when read.
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
System Configuration and Protection
MSB
LSB
0
1
2
3
4
5
6
7
8
9
Field
SWSR
Reset
0000_0000_0000_0000
Addr
0x2F C00E
10
11
12
13
14
15
Figure 6-27. Software Service Register (SWSR)
Table 6-16. SWSR Bit Descriptions
Bits
Name
Description
0:15
SWSR
SWT servicing sequence is written to this register. To prevent SWT time-out, a 0x556C followed
by 0xAA39 should be written to this register. The SWSR can be written at any time but returns
all zeros when read.
6.2.2.3.3
Transfer Error Status Register (TESR)
The transfer error status register contains a bit for each exception source generated by a transfer error. A
bit set to logic 1 indicates what type of transfer error exception occurred since the last time the bits were
cleared by reset or by the normal software status bit-clearing mechanism.
NOTE
These bits may be set due to canceled speculative accesses which do not
cause an interrupt. The register has two identical sets of bit fields; one is
associated with instruction transfers and the other with data transfers.
MSB
0
1
2
3
4
5
6
7
8
9
Field
—
Reset
0000_0000_0000_0000
Addr
0x2F C020
10
11
12
13
14
26
27
28
29
30
15
LSB
16
Field
17
—
18
19
IEXT IBMT
Reset
20
21
22
23
24
25
—
DEXT DBM
31
—
0000_0000_0000_0000
Figure 6-28. Transfer Error Status Register (TESR)
Table 6-17. TESR Bit Descriptions
Bits
Name
Description
0:17
—
18
IEXT
Instruction external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when an instruction fetch was initiated.
19
IBMT
Instruction transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor
time-out when an instruction fetch was initiated.
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-39
System Configuration and Protection
Table 6-17. TESR Bit Descriptions (continued)
Bits
Name
20:25
—
26
DEXT
Data external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when a data load or store is requested by an internal master.
27
DBM
Data transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor time-out
when a data load or store is requested by an internal master.
28:31
—
6.2.2.4
Description
Reserved
Reserved
System Timer Registers
The following sections describe registers associated with the system timers. These facilities are powered
by the KAPWR and can preserve their value when the main power supply is off. Refer to Section 8.2.3,
“Pre-Divider,” for details on the required actions needed in order to guarantee this data retention.
A list of KAPWR registers affected by the key/lock mechanism is found in Table 8-8.
6.2.2.4.1
Decrementer Register (DEC)
The 32-bit decrementer register is defined by the PowerPC architecture. The values stored in this register
are used by a down counter to cause decrementer exceptions. The decrementer causes an exception
whenever bit zero changes from a logic zero to a logic one. A read of this register always returns the current
count value from the down counter.
Contents of this register can be read or written to by the mfspr or the mtspr instruction. The decrementer
register is reset by PORESET. HRESET and SRESET do not affect this register. The decrementer is
powered by standby power and can continue to count when standby power is applied.
Decrementer counts down the time base clock and the counting is enabled by TBE bit in TBCSR register
Section 6.2.2.4.4, “Time Base Control and Status Register (TBSCR).”
MSB
LSB
0
31
Field
PORESET
DECREMENTING COUNTER
0000_0000_0000_0000_0000_0000_0000_0000
Unaffected
HRESET
SRESET
Addr
SPR 22
Figure 6-29. Decrementer Register (DEC)
Refer to Section 3.9.5, “Decrementer Register (DEC)” for more information on this register.
6.2.2.4.2
Time Base SPRs (TB)
The TB is a 64-bit register containing a 64-bit integer that is incremented periodically. There is no
automatic initialization of the TB; the system software must perform this initialization. The contents of the
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
System Configuration and Protection
register may be written by the mttbl or the mttbu instructions, see Section 3.9.4, “Time Base Facility (TB)
— OEA.”
Refer to Section 3.8, “VEA Register Set — Time Base (TB)’ and Section 3.9.4, “Time Base Facility (TB)
— OEA” for more information on reading and writing the TBU and TBL registers.
MSB
LSB
0
Field
31 32
TBU
PORESET
63
TBL
Unaffected
Addr
SPR 269, SPR 268
Figure 6-30. Time Base (Reading) (TB)
MSB
LSB
0
Field
31 32
TBU
PORESET
63
TBL
Unaffected
Addr
SPR 285, SPR 284
Figure 6-31. Time Base (Writing) (TB)
6.2.2.4.3
Time Base Reference Registers (TBREF0 and TBREF1)
Two reference registers (TBREF0 and TBREF1) are associated with the lower part of the time base (TBL).
Each is a 32-bit read/write register. Upon a match between the contents of TBL and the reference register,
a maskable interrupt is generated.
MSB
LSB
0
31
Field
TBREF0
Reset
Unaffected
Addr
0x2F C204
Figure 6-32. Time Base Reference Register 0 (TBREF0)
MSB
LSB
0
31
Field
TBREF1
Reset
Unaffected
Addr
0x2F C208
Figure 6-33. Time Base Reference Register 1 (TBREF1)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-41
System Configuration and Protection
6.2.2.4.4
Time Base Control and Status Register (TBSCR)
The TBSCR is 16-bit read/write register. It controls the TB, decrementer count enable, and interrupt
generation and is used for reporting the source of the interrupts. The register can be read anytime. A status
bit is cleared by writing a one to it. (Writing a zero has no effect.) More than one bit can be cleared at a time.
MSB
0
Field
LSB
1
2
3
4
TBIRQ
PORESET
5
6
7
8
9
10
REFA REFB
11
—
12
13
14
15
REFAE
REFBE
TBF
TBE
0000_0000_0000_0000
Addr
0x2F C200
Figure 6-34. Time Base Control and Status Register (TBSCR)
Table 6-18. TBSCR Bit Descriptions
Bits
Name
Description
0:7
TBIRQ
Time base interrupt request. These bits determine the interrupt priority level of the time base.
Refer to Section 6.1.4, “Enhanced Interrupt Controller” for interrupt level encoding.
8
REFA
Reference A (TBREF0) interrupt status.
0 No match detected
1 TBREF0 value matches value in TBL
9
REFB
Reference B (TBREF1) interrupt status.
0 No match detected
1 TBREF1 value matches value in TBL
10:11
—
12
REFAE
Reference A (TBREF0) interrupt enable. If this bit is set, the time base generates an interrupt
when the REFA bit is set.
13
REFBE
Reference B (TBREF1) interrupt enable. If this bit is set, the time base generates an interrupt
when the REFB bit is set.
14
TBF
Time base freeze. If this bit is set, the time base and decrementer stop while FREEZE is
asserted.
15
TBE
Time base enable
0 Time base and decrementer are disabled
1 Time base and decrementer are enabled
6.2.2.4.5
Reserved
Real-Time Clock Status and Control Register (RTCSC)
The RTCSC enables the different RTC functions and reports the source of the interrupts. The register can
be read anytime. A status bit is cleared by writing a one to it. (Writing a zero does not affect a status bit’s
value.) More than one status bit can be cleared at a time. This register is locked after reset by default.
Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See Section 8.8.3.2,
“Keep-Alive Power Registers Lock Mechanism.”
MPC561/MPC563 Reference Manual, Rev. 1.2
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System Configuration and Protection
MSB
LSB
0
1
Field
2
3
4
5
6
7
RTCIRQ
8
9
10
11
12
13
14
15
SEC
ALR
—
4M
SIE
ALE
RTF
RTE
0000_0000_000
PORESET
U
Addr
000
U
0x2F C220
Figure 6-35. Real-Time Clock Status and Control Register (RTCSC)
Table 6-19. RTCSC Bit Descriptions
Bits
Name
0:7
RTCIRQ
8
SEC
Once per second interrupt. This status bit is set every second. It should be cleared by the
software.
9
ALR
Alarm interrupt. This status bit is set when the value of the RTC equals the value programmed in
the alarm register.
10
—
Reserved
11
4M
Real-time clock source
0 RTC assumes that it is driven by 20 MHz to generate the seconds pulse.
1 RTC assumes that it is driven by 4 MHz
12
SIE
Second interrupt enable. If this bit is set, the RTC generates an interrupt when the SEC bit is set.
13
ALE
Alarm interrupt enable. If this bit is set, the RTC generates an interrupt when the ALR bit is set.
14
RTF
Real-time clock freeze. If this bit is set, the RTC stops while FREEZE is asserted.
15
RTE
Real-time clock enable
0 RTC is disabled
1 RTC is enabled
6.2.2.4.6
Description
Real-time clock interrupt request. Thee bits determine the interrupt priority level of the RTC.
Refer to Section 6.1.4, “Enhanced Interrupt Controller” for interrupt level encoding.
Real-Time Clock Register (RTC)
The real-time clock register is a 32-bit read write register. It contains the current value of the real-time
clock. A write to the RTC resets the seconds timer to zero. This register is locked after reset by default.
Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See Section 8.8.3.2,
“Keep-Alive Power Registers Lock Mechanism.”
MSB
LSB
0
31
Field
RTC
Reset
Unaffected
Addr
0x2F C224
Figure 6-36. Real-Time Clock Register (RTC)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-43
System Configuration and Protection
6.2.2.4.7
Real-Time Clock Alarm Register (RTCAL)
The RTCAL is a 32-bit read/write register. When the value of the RTC is equal to the value programmed
in the alarm register, a maskable interrupt is generated.
The alarm interrupt will be generated as soon as there is a match between the ALARM field and the
corresponding bits in the RTC. The resolution of the alarm is 1 second. This register is locked after reset
by default. Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See
Section 8.8.3.2, “Keep-Alive Power Registers Lock Mechanism.”
MSB
LSB
0
31
Field
ALARM
Reset
Unaffected
Addr
0x2F C22C
Figure 6-37. Real-Time Clock Alarm Register (RTCAL)
6.2.2.4.8
Periodic Interrupt Status and Control Register (PISCR)
The PISCR contains the interrupt request level and the interrupt status bit. It also contains the controls for
the 16-bits to be loaded into a modulus counter. This register can be read or written at any time.
MSB
0
LSB
1
2
Field
3
4
PIRQ
PORESET
5
6
7
8
9
10
PS
11
12
—
13
14
15
PIE
PITF
PTE
0000_0000_0000_0000
Addr
0x2F C240
Figure 6-38. Periodic Interrupt Status and Control Register (PISCR)
Table 6-20. PISCR Bit Descriptions
Bits
Name
Description
0:7
PIRQ
8
PS
Periodic interrupt status. This bit is set if the PIT issues an interrupt. The PIT issues an interrupt
after the modulus counter counts to zero. PS can be negated by writing a one to it. A write of zero
has no affect.
9:12
—
Reserved
13
PIE
14
PITF
PIT freeze. If this bit is set, the PIT stops while FREEZE is asserted.
15
PTE
Periodic timer enable
0 PIT stops counting and maintains current value
1 PIT continues to decrement
Periodic interrupt request. These bits determine the interrupt priority level of the PIT. Refer to
Section 6.1.4, “Enhanced Interrupt Controller” for interrupt level encoding.
Periodic interrupt enable. If this bit is set, the time base generates an interrupt when the PS bit
is set.
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
System Configuration and Protection
6.2.2.4.9
Periodic Interrupt Timer Count Register (PITC)
The PITC register contains the 16-bits to be loaded in a modulus counter. This register is readable and
writable at any time.
MSB
0
1
2
3
4
5
6
7
8
Field
PITC
Reset
Unaffected
Addr
0x2F C244
9
10
11
12
13
14
25
26
27
28
29
30
15
LSB
16
17
18
19
20
21
22
23
24
Field
—
Reset
Unaffected
31
Figure 6-39. Periodic Interrupt Timer Count (PITC)
Table 6-21. PITC Bit Descriptions
Bits
Name
Description
0:15
PITC
Periodic interrupt timing count. This field contains the 16-bit value to be loaded into the modulus
counter that is loaded into the periodic timer. This register is readable and writable at any time.
16:31
—
6.2.2.4.10
Reserved
Periodic Interrupt Timer Register (PITR)
The periodic interrupt register is a read-only register that shows the current value in the periodic interrupt
down counter. Read or writing this register does not affect the register.
MSB
0
1
2
3
4
5
6
7
8
Field
PIT
Reset
Unaffected
Addr
0x2F C248
9
10
11
12
13
14
25
26
27
28
29
30
15
LSB
16
17
18
19
20
21
22
23
24
Field
—
Reset
Unaffected
31
Figure 6-40. Periodic Interrupt Timer Register (PITR)
Table 6-22. PIT Bit Descriptions
Bits
Name
Description
0:15
PIT
Periodic interrupt timing count—This field contains the current count remaining for the periodic
timer. Writes have no effect on this field.
16:31
—
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-45
System Configuration and Protection
6.2.2.5
General-Purpose I/O Registers
6.2.2.5.1
SGPIO Data Register 1 (SGPIODT1)
MSB
0
1
2
Field
3
4
5
6
7
8
9
10
SGPIOD[0:7]
11
12
13
14
29
30
15
SGPIOD[8:15]
Reset
0000_0000_0000_00001
Addr
0x2F C024
LSB
16
17
18
Field
20
21
22
23
24
25
26
SGPIOD[16:23]
27
28
31
SGPIOD[24:31]
0000_0000_0000_00001
Reset
1
19
If the device is configured NOT in full bus mode (i.e., SIUMCR[SC]=0b01, 0x10, or 0b11), the GPIO pins will be in input
mode and this register will reflect the state of the pins.
Figure 6-41. SGPIO Data Register 1 (SGPIODT1)
Table 6-23. SGPIODT1 Bit Descriptions
Bits
Name
Description
0:7
SGPIOD[0:7]
SIU general-purpose I/O Group D[0:7]. This 8-bit register controls the data of
general-purpose I/O pins SGPIOD[0:7]. The direction (input or output) of this group of pins
is controlled by the GDDR0 bit in the SGPIO control register.
8:15
SGPIOD[8:15]
SIU general-purpose I/O Group D[8:15]. This 8-bit register controls the data of
general-purpose I/O pins SGPIOD[8:15]. The direction (input or output) of this group of
pins is controlled by the GDDR1 bit in the SGPIO control register.
16:23
SGPIOD[16:23]
SIU general-purpose I/O Group D[16:23]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOD[16:23]. The direction (input or output) of this group of
pins is controlled by the GDDR2 bit in the SGPIO control register
24:31
SGPIOD[24:31]
SIU general-purpose I/O Group D[24:31]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOD[24:31]. The direction of SGPIOD[24:31] is controlled by
eight dedicated direction control signals SDDRD[24:31]. Each pin in this group can be
configured separately as general-purpose input or output.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-46
Freescale Semiconductor
System Configuration and Protection
6.2.2.5.2
SGPIO Data Register 2 (SGPIODT2)
MSB
0
1
2
Field
3
4
5
6
7
8
9
10
11
SGPIOC[0:7]
12
13
14
29
30
15
SGPIOA[8:15]
1
Reset
0000_0000_0000_0000
Addr
0x2F C028
LSB
16
17
18
Field
20
21
22
23
24
25
26
SGPIOA[16:23]
27
28
31
SGPIOA[24:31]
1
Reset
1
19
0000_0000_0000_0000
If the device is configured NOT in full bus mode (i.e., SIUMCR[SC]=0b01, 0x10, or 0b11), the GPIO pins will be in input
mode and this register will reflect the state of the pins.
Figure 6-42. SGPIO Data Register 2 (SGPIODT2)
Table 6-24. SGPIODT2 Bit Descriptions
Bits
Name
Description
0:7
SGPIOC[0:7]
SIU general-purpose I/O Group C[0:7]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOC[0:7]. The direction of SGPIOC[0:7] is controlled by 8
dedicated direction control signals SDDRC[0:7] in the SGPIO control register. Each pin in
this group can be configured separately as general-purpose input or output.
8:15
SGPIOA[8:15] SIU general-purpose I/O Group A[8:15]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[8:15]. The GDDR3 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
16:23
SGPIOA
[16:23]
SIU general-purpose I/O Group A[16:23]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[16:23]. The GDDR4 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
24:31
SGPIOA
[24:31]
SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-47
System Configuration and Protection
6.2.2.5.3
SGPIO Control Register (SGPIOCR)
1
MSB
0
1
2
Field
3
4
5
6
7
8
9
10
11
SDDRC[0:7]
HRESET
12
13
14
28
29
30
15
—
0000_0000_0000_0000
Addr
0x2F C02C
LSB
16
17
18
19
20
21
22
23
Field GDDR GDDR GDDR GDDR GDDR GDDR
0
1
2
3
4
5
24
25
26
—
27
31
SDDRD[24:31]
0000_0000_0000_0000
HRESET
Figure 6-43. SGPIO Control Register (SGPIOCR)
Table 6-25. SGPIOCR Bit Descriptions
Bits
Name
Description
0:7
SDDRC[0:7]
SGPIO data direction for SGPIOC[0:7]. Each SDDR bit zero to seven controls the direction
of the corresponding SGPIOC pin zero to seven
8:15
—
16
GDDR0
Group data direction for SGPIOD[0:7]
17
GDDR1
Group data direction for SGPIOD[8:15]
18
GDDR2
Group data direction for SGPIOD[16:23]
19
GDDR3
Group data direction for SGPIOA[8:15]
20
GDDR4
Group data direction for SGPIOA[16:23]
21
GDDR5
Group data direction for SGPIOA[24:31]
22:23
—
24:31
SDDRD
[24:31]
Reserved
Reserved
SGPIO data direction for SGPIOD[24:31]. Each SDDRD bits 24:31 controls the direction
of the corresponding SGPIOD pin [24:31].
Table 6-26 describes the bit values for data direction control.
Table 6-26. Data Direction Control
SDDR/GDDR
Operation
0
SGPIO configured as input
1
SGPIO configured as output
MPC561/MPC563 Reference Manual, Rev. 1.2
6-48
Freescale Semiconductor
Chapter 7
Reset
This section describes the MPC561/MPC563 reset sources, operation, control, and status.
7.1
Reset Operation
The MPC561/MPC563 has several inputs to the reset logic which include the following:
• Power-on reset
• External hard reset pin (HRESET)
• External soft reset pin (SRESET)
• Loss of PLL lock
• On-chip clock switch
• Software watchdog reset
• Checkstop reset
• Debug port hard reset
• Debug port soft reset
• JTAG reset
• Illegal bit change (ILBC)
All of these reset sources are fed into the reset controller. The control logic determines the cause of the
reset, synchronizes it, and resets the appropriate logic modules, depending on the source of the reset. The
memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only
on hard reset. External soft reset initializes internal logic while maintaining system configuration.
The reset status register (RSR) reflects the most recent source to cause a reset.
7.1.1
Power-On Reset
The power-on reset pin, PORESET, is an active low input. In a system with power-down low-power mode,
this pin should be activated only as a result of a voltage failure on the KAPWR pin. After detecting the
assertion of PORESET, the MPC561/MPC563 enters the power-on reset state. During this state the
MODCK[1:3] signals determine the oscillator frequency, PLL multiplication factor, and the PITRTCLK
and TMBCLK clock sources. In addition, the MPC561/MPC563 asserts the SRESET and HRESET pins
at the rising edge of PORESET.
The PORESET pin should be asserted for a minimum time of 100,000 of clock oscillator cycles after a
valid level has been reached on the KAPWR supply. After detecting the assertion of PORESET, the
MPC561/MPC563 remains in the power-on reset state until the last of the following two events occurs:
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-1
Reset
•
•
The Internal PLL enters the lock state and the system clock is active.
The PORESET pin is negated.
If limp mode is enabled, the internal PLL is not required to be locked before the chip exits power-on reset.
The internal MODCK[1:3] values are sampled at the rising edge of PORESET. After exiting the power-on
reset state, the MPC561/MPC563 continues to drive the HRESET and SRESET pins for 512 system clock
cycles. When the timer expires (after 512 cycles), the configuration is sampled from data bus pins, if
required (see Section 7.5.1, “Hard Reset Configuration”) and the MPC561/MPC563 stops driving the
HRESET and SRESET pins.
The PORESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The
internal PORESET signal asserts only if the PORESET pin asserts for more than 100 ns.
7.1.2
Hard Reset
HRESET (hard reset) is an active low, bidirectional I/O pin. The MPC561/MPC563 can detect an external
assertion of HRESET only if it occurs while the MPC561/MPC563 is not asserting HRESET.
When the MPC561/MPC563 detects assertion of the external HRESET pin or a cause to assert the internal
HRESET line is detected, the chip starts to drive the HRESET and SRESET for 512 cycles. When the timer
expires (after 512 cycles) the configuration is sampled from data pins (refer to Section 7.5.1, “Hard Reset
Configuration”) and the chip stops driving the HRESET and SRESET pins. An external pull-up resistor
should drive the HRESET and SRESET pins high. After detecting the negation of HRESET or SRESET,
the MPC561/MPC563 waits 16 clock cycles before testing the presence of an external hard or soft reset.
The HRESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The internal
HRESET will be asserted only if HRESET is asserted for more than 100 ns.
The HRESET is an open collector type pin.
7.1.3
Soft Reset
SRESET (soft reset) is an active low, bidirectional I/O pin. The MPC561/MPC563 can only detect an
external assertion of SRESET if it occurs while the MPC561/MPC563 is not asserting SRESET.
When the MPC561/MPC563 detects the assertion of external SRESET or a cause to assert the internal
SRESET line, the chip starts to drive the SRESET for 512 cycles. When the timer expires (after 512 cycles)
the debug port configuration is sampled from the DSDI and DSCK pins and the chip stops driving the
SRESET pin. An external pull-up resistor should drive the SRESET pin high. After the MPC561/MPC563
detects the negation of SRESET, it waits 16 clock cycles before testing the presence of an external soft
reset.
The SRESET is an open collector type pin.
7.1.4
Loss of PLL Lock
If the PLL detects a loss of lock, erroneous external bus operation will occur if synchronous external
devices use the MPC561/MPC563 input clock. Erroneous operation could also occur if devices with a PLL
MPC561/MPC563 Reference Manual, Rev. 1.2
7-2
Freescale Semiconductor
Reset
use the MPC561/MPC563 CLKOUT signal. This source of reset can be optionally asserted if the LOLRE
bit in the PLL, low-power, and reset control register (PLPRCR) is set. The enabled PLL loss of lock event
generates an internal hard reset sequence. Refer to Chapter 8, “Clocks and Power Control,” for more
information on loss of PLL lock.
7.1.5
On-Chip Clock Switch
If the system clock is switched to the backup clock or switched from backup clock to another clock source
an internal hard reset sequence is generated. Refer to Chapter 8, “Clocks and Power Control.”
7.1.6
Software Watchdog Reset
When the MPC561/MPC563 software watchdog counts to zero, a software watchdog reset is asserted. The
enabled software watchdog event generates an internal hard reset sequence.
7.1.7
Checkstop Reset
When the RCPU enters a checkstop state, and the checkstop reset is enabled (the CSR bit in the PLPRCR
is set), a checkstop reset is asserted. The enabled checkstop event generates an internal hard reset sequence.
Refer to the RCPU Reference Manual for more information.
7.1.8
Debug Port Hard Reset
When the development port receives a hard reset request from the development tool, an internal hard reset
sequence is generated. In this case the development tool must reconfigure the debug port. Refer to
Chapter 23, “Development Support,” for more information.
7.1.9
Debug Port Soft Reset
When the development port receives a soft reset request from the development tool, an internal soft reset
sequence is generated. In this case the development tool must reconfigure the debug port. Refer to
Chapter 23, “Development Support,” for more information.
7.1.10
JTAG Reset
When the JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated. Refer
to Chapter 25, “IEEE 1149.1-Compliant Interface (JTAG),” for more information.
7.1.11
ILBC Illegal Bit Change
When locked bits in the PLPRCR register are changed, an internal hard reset sequence is generated. Refer
to Chapter 8, “Clocks and Power Control.”
7.2
Reset Actions Summary
Table 7-1 summarizes the action taken for each reset.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-3
Reset
Table 7-1. Reset Action Taken for Each Reset Cause
Reset Source
Reset
Logic and
PLL
States
Reset
Other
System
Clock HRESET Debug Port
SRESET
Internal
Configuratio Module
Pin
Configuratio
Pin
Logic
n Reset
Reset
Driven
n
Driven
Reset
Power-On Reset
(PORESET)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Hard Reset (HRESET)
Sources:
• External Hard Reset
• Loss of Lock
• On-Chip Clock Switch
• Illegal Low-Power Mode
• Software Watchdog
• Checkstop
• Debug Port Hard Reset
No
Yes
Yes
Yes
Yes
Yes
Yes
Soft Reset (SRESET)
Sources:
• External Soft Reset
• Debug Port Soft Reset
• JTAG Reset
No
No
No
No
Yes
Yes
Yes
7.3
Data Coherency During Reset
The MPC561/MPC563 supports data coherency and avoids data corruption during reset. If a cycle is
executing when any SRESET or HRESET source is detected, then the cycle will either complete or will
not start before generating the corresponding reset control signal. There are reset sources, however, when
the MPC561/MPC563 generates an internal reset due to special internal situations where this protection is
not supported. See Section 7.4, “Reset Status Register (RSR).”
In the case of large operand size (32 or 16 bits) transactions to a smaller port size, the cycle is split into
two 16-bit or four 8-bit cycles. In this case, data coherency is assured and data will not be corrupted.
In the case where the core executes an unaligned load/store cycle which is broken down into multiple
cycles, data coherency is NOT assured between these cycles (i.e., data could be corrupted).
Contention may occur if a write access is in progress to external memory and SRESET/HRESET is
asserted and the external reset configuration word (RCW) is used. In this case, the external RCW drivers,
usually activated by HRESET/SRESET lines, will drive the data bus together with the MPC561/MPC563.
Thus the data in the RAM may be corrupted regardless of the data coherency mechanism in the
MPC561/MPC563.
Table 7-2. Reset Configuration Word and Data Corruption/Coherency
Reset Driven
HRESET
Reset to Use for Data
Coherency (EXT_RESET)
Comments
SRESET
MPC561/MPC563 Reference Manual, Rev. 1.2
7-4
Freescale Semiconductor
Reset
Table 7-2. Reset Configuration Word and Data Corruption/Coherency (continued)
Reset to Use for Data
Coherency (EXT_RESET)
Reset Driven
SRESET
HRESET
HRESET & SRESET
HRESET || SRESET
7.4
Comments
Provided only one of them is driven into the
MPC561/MPC563 at a time
Reset Status Register (RSR)
All of the reset sources are fed into the reset controller. The 16-bit reset status register (RSR) reflects the
most recent source, or sources, of reset. (Simultaneous reset requests can cause more than one bit to be set
at the same time.) This register contains one bit for each reset source. A bit set to logic one indicates the
type of reset that occurred.
Once set, individual bits in the RSR remain set until software clears them. Bits in the RSR can be cleared
by writing a one to the bit. A write of zero has no effect on the bit. The register can be read at all times.
The reset status register receives its default reset values during power-on reset. The RSR is powered by the
KAPWR pin.
MSB
0
LSB
1
2
3
4
5
6
7
8
9
10
11
12
Field EHRS ESRS LLRS SWRS CSRS DBHRS DBSRS JTRS OCCS ILBC GPOR GHRST GSRST
PORESET
HRESET
0
0000_0000_000
SRESET
0000_0000_0000
Addr
1
01
0000_0000
1
13 14
15
—
1
1
000
1
1
000
1
000
0x2F C288
OCCS will be set (1) if limp mode is enabled (SCCR[LME]=1).
Figure 7-1. Reset Status Register (RSR)
Table 7-3. Reset Status Register Bit Descriptions
Bits
Name
Description
0
EHRS1
External hard reset status
0 No external hard reset has occurred
1 An external hard reset has occurred
1
ESRS1
External soft reset status
0 No external soft reset has occurred
1 An external soft reset has occurred
2
LLRS
Loss of lock reset status
0 No enabled loss-of-lock reset has occurred
1 An enabled loss-of-lock reset has occurred
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-5
Reset
Table 7-3. Reset Status Register Bit Descriptions (continued)
1
Bits
Name
Description
3
SWRS
Software watchdog reset status
0 No software watchdog reset has occurred
1 A software watchdog reset has occurred
4
CSRS
Checkstop reset status
0 No enabled checkstop reset has occurred
1 An enabled checkstop reset has occurred
5
DBHRS
Debug port hard reset status
0 No debug port hard reset request has occurred
1 A debug port hard reset request has occurred
6
DBSRS
Debug port soft reset status
0 No debug port soft reset request has occurred
1 A debug port soft reset request has occurred
7
JTRS
JTAG reset status
0 No JTAG reset has occurred
1 A JTAG reset has occurred
8
OCCS
On-chip clock switch
0 No on-chip clock switch reset has occurred
1 An on-chip clock switch reset has occurred
9
ILBC
Illegal bit change. This bit is set when the MPC561/MPC563 changes any of the following bits
when they are locked:
LPM[0:1], locked by the LPML bit
MF[0:11], locked by the MFPDL bit
DIVF[0:4], locked by the MFPDL bit
10
GPOR
Glitch detected on PORESET pin. This bit is set when the PORESET pin is asserted for more
than 20ns
0 No glitch was detected on the PORESET pin
1 A glitch was detected on the PORESET pin
11
GHRST
Glitch detected on HRESET pin. This bit is set when the HRESET pin is asserted for more than
20ns
0 No glitch was detected on the HRESET pin
1 A glitch was detected on the HRESET pin
12
GSRST
Glitch detected on SRESET pin. If the SRESET pin is asserted for more than 20ns the GHRST
bit will be set. If an internal or external SRESET is generated the SRESET pin is asserted and
the GSRST bit will be set.
0 No glitch was detected on SRESET pin
1 A glitch was detected on SRESET pin.
13:15
—
Reserved
In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal. The EHRS and ESRS bits in RSR
register are set for any internal reset source in addition to external HRESET and external SRESET events. If both
internal and external indicator bits are set, then the reset source is internal.
MPC561/MPC563 Reference Manual, Rev. 1.2
7-6
Freescale Semiconductor
Reset
7.5
7.5.1
Reset Configuration
Hard Reset Configuration
When a hard reset event occurs, the MPC561/MPC563 reconfigures its hardware system as well as the
development port configuration. The logical value of the bits that determine its initial mode of operation,
are sampled from the following:
• The external data bus pins DATA[0:31]
• An internal default constant (0x0000 0000)
• An internal NVM register value (UC3FCFIG). Available on the MPC563/MPC564 only.
If at the sampling time RSTCONF is asserted, then the configuration is sampled from the external data
bus. If RSTCONF is negated and a valid NVM value exists (UC3FCFIG[HC]=0), then the configuration
is sampled from the NVM register in the UC3F module. If RSTCONF is negated and no valid NVM value
exists (UC3FCFIG[HC]=1), then the configuration word is sampled from the internal default (all zeros).
HC will be “1” if the internal Flash is erased. Table 7-4 summarizes the reset configuration options.
Table 7-4. Reset Configuration Options
RSTCONF
Has Configuration (HC)
Internal Configuration Word
0
x
DATA[0:31] pins
1
0
NVM Flash EEPROM register (UC3FCFIG)
1
1
Internal data word default (0x0000 0000)
If the PRDS control bit in the PDMCR register is cleared and HRESET and RSTCONF are asserted, the
MPC561/MPC563 pulls the data bus low with a weak resistor. The user can overwrite this default by
driving the appropriate bit high. See Figure 7-2 for the basic reset configuration scheme.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-7
Reset
Has Configuration (HC)
Reset
Config.
Word
32
Flash
32
MUX
32
OE
Dx (Data line)
INT_RESET
Data
Coherency
EXT_RESET
(See Table 7-2)
HRESET/SRESET
RSTCONF
Figure 7-2. Reset Configuration Basic Scheme
During the assertion of the PORESET input signal, the chip assumes the default reset configuration. This
assumed configuration changes if the input signal RSTCONF is asserted when the PORESET is negated
or the CLKOUT starts to oscillate. To ensure that stable data is sampled, the hardware configuration is
sampled every eight clock cycles on the rising edge of CLKOUT with a double buffer. The setup time
required for the data bus is approximately 15 cycles (defined as Tsup in the following figures) and the
maximum rise time of HRESET should be less than six clock cycles. In systems where an external reset
configuration word and the TEXP output function are both required, RSTCONF should be asserted until
SRESET is negated.
Figure 7-3 to Figure 7-6 provide sample reset configuration timings.
NOTE
Timing diagrams in the following figures are not to scale.
MPC561/MPC563 Reference Manual, Rev. 1.2
7-8
Freescale Semiconductor
Reset
CLKOUT
PORESET
Internal PORESET
HRESET
RSTCONF
Tsup
Internal data[0:31]
Default
RSTCONF Controlled
Figure 7-3. Reset Configuration Sampling Scheme for “Short” PORESET Assertion, Limp Mode Disabled
CLKOUT
(Backup Clock)
PORESET
Internal
PORESET
512 clocks
HRESET
Tsup
RSTCONF
Internal data(0:31)
Default
RSTCONF Controlled
Figure 7-4. Reset Configuration Timing for “Short” PORESET Assertion, Limp Mode Enabled
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-9
Reset
CLKOUT
PORESET
PLL lock
Internal
PORESET
HRESET
Tsup
RSTCONF
Internal data[0:31]
Default
RSTCONF Controlled
Figure 7-5. Reset Configuration Timing for “Long” PORESET Assertion, Limp Mode Disabled
1
2
3
8
8
9
10
8
9
10
11
12
13
14
15
16
CLKOUT
HRESET
Maximum time of reset recognition
(maximum rise time - up to 6 clocks)
RSTCONF
DATA
Internal
reset
Reset Configuration Word
Tsup = Minimum Setup time of reset recognition = 15 clocks
Sample Data Configuration
Sample Data Configuration
Figure 7-6. Reset Configuration Sampling Timing Requirements
MPC561/MPC563 Reference Manual, Rev. 1.2
7-10
Freescale Semiconductor
Reset
7.5.2
Hard Reset Configuration Word (RCW)
Following is the hard reset configuration word that is sampled from the internal data bus,
data_sgpiod(0:31) on the negation of HRESET. If the external reset config word is selected (RSTCONF =
0), the internal data bus will reflect the state of external data bus. If the internal reset config word is selected
and neither of the Flash reset config words are enabled (UC3FCFIG[HC] = 1), the internal data bus is
internally driven with all zeros. The reset configuration word is not a register in the memory map. Most of
the bits in the configuration are located in registers in the SIU. Refer to Table 7-5 for a detailed description
of each control bit.
MSB
0
1
Field EARB
2
3
4
IP BDRV BDIS
5
6
BPS[0:1]
HRESET
7
8
—
9
10
11
DBGC[0:1]
—
12
13
14
ATWC EBDF[0:1]
15
—
0000_0000_0000_0000
LSB
16
17
Field PRPM
HRESET
18
SC
19
20
ETRE FLEN
21
22
EN_
EXC_
COMP1 COMP1
23
—
24
25
26
OERC
27
28
—
29
ISB
30
31
DME
0000_0000_0000_0000
Figure 7-7. Reset Configuration Word (RCW)
1
Available only on the MPC562/MPC564, software should write "0" to this bit for MPC561/MPC563.
Table 7-5. RCW Bit Descriptions
Bits
Name
Description
0
EARB
1
IP
Initial Interrupt Prefix — This bit defines the initial value of MSR[IP] immediately after reset.
MSR[IP] defines the Interrupt Table location. If IP is zero then the initial value of MSR[IP] is zero,
If the IP is one, then the initial value of MSR[IP] is one. Default value is zero. See Table 3-11 for
more information.
0 MSR[IP] = 0 after reset
1 MSR[IP] = 1 after reset
2
BDRV
Bus Pins Drive Strength — This bit determines the bus pins (address, data and control) driving
capability to be either full or reduced drive. The bus default drive strength is full; Upon default, it
also effects the CLKOUT drive strength to be full. See Table 6-7 for more information. BDRV
controls the default state of COM1 in the SIUMCR.
0 Full drive
1 Reduced drive
3
BDIS
Boot Disable — If the BDIS bit is set, then memory controller is not activated after reset. If it is
cleared then the memory controller bank 0 is active immediately after reset such that it matches
any addresses. If a write to the OR0 register occurs after reset this bit definition is ignored. The
default value is that the memory controller is enabled to control the boot with the CS0 pin. See
Section 10.7, “Global (Boot) Chip-Select Operation,” for more information.
0 Memory controller bank 0 is active and matches all addresses immediately after reset
1 Memory controller is not activated after reset.
External Arbitration — Refer to Section 9.5.7, “Arbitration Phase,” for a detailed description of
Bus arbitration. The default value is that internal arbitration hardware is used.
0 Internal arbitration is performed
1 External arbitration is assumed
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-11
Reset
Table 7-5. RCW Bit Descriptions (continued)
Bits
Name
Description
4:5
BPS
Boot Port Size — This field defines the port size of the boot device on reset (BR0[PS]). If a write
to the OR0 register occurs after reset this field definition is ignored. See Table 10-5 and
Table 10-8 for more information.
00 32-bit port (default)
01 8-bit port
10 16-bit port
11 Reserved
6:8
—
9:10
Reserved. These bits must not be high in the reset configuration word.
DBGC[0:1] Debug Pins Configuration — See Section 6.2.2.1.1, “SIU Module Configuration Register
(SIUMCR),” for this field definition. The default value is that these pins function as: VFLS[0:1], BI,
BR, BG and BB. See Table 6-8.
11
—
Reserved.
12
ATWC
Address Type Write Enable Configuration — The default value is that these pins function as WE
pins. See Table 6-7.
0 WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1 WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
13:14
EBDF
External Bus Division Factor — This field defines the initial value of the external bus frequency.
The default value is that CLKOUT frequency is equal to that of the internal clock (no division).
See Table 8-9.
151
—
16
PRPM
Peripheral Mode Enable — This bit determines if the chip is in peripheral mode. A detailed
description is in Table 6-13 The default value is no peripheral mode enabled.
17:18
SC
Single Chip Select — This field defines the mode of theMPC562/MPC564. See Table 6-10.
00 Extended chip, 32 bits data
01 Extended chip, 16 bits data
10 Single chip and show cycles (address)
11 Single chip
19
ETRE
Exception Table Relocation Enable — This field defines whether the Exception Table Relocation
feature in the BBC is enabled or disabled; The default state for this field is disabled. For more
details, see Table 4-4.
202,3
FLEN
Flash Enable — This field determines whether the on-chip Flash memory is enabled or disabled
out of reset. The default state is disabled, which means that by default, the boot is from external
memory. Refer to Table 6-12 for more details.
0 Flash disabled — boot is from external memory
1 Flash enabled
21
EN_
COMP4
Enable Compression — This bit enables the operation of the MPC562/MPC564 with compressed
code. The default state is disabled. See Table 4-4 and Appendix A,
“MPC562/MPC564 Compression Features."
22
EXC_
COMP4
Exception Compression — This bit determines the operation of the MPC562/MPC564 with
exceptions. If this bit is set, then the MPC562/MPC564 assumes that ALL the exception routines
are in compressed code. The default indicates the exceptions are all non-compressed. See
Table 4-4 and Appendix A, “MPC562/MPC564 Compression Features."
23
—
Reserved. This bit must be 0 in the reset configuration word.
Reserved. This bit must not be high in the reset configuration word.
MPC561/MPC563 Reference Manual, Rev. 1.2
7-12
Freescale Semiconductor
Reset
Table 7-5. RCW Bit Descriptions (continued)
Bits
Name
Description
24:25
OERC
26:27
—
28:30
ISB
Internal Space Base Select — This field defines the initial value of the ISB field in the IMMR
register. A detailed description is in Table 6-12. The default state is that the internal memory map
is mapped to start at address 0x0000_0000. This bit must not be high in the reset configuration
word.
31
DME
Dual Mapping Enable — This bit determines whether Dual mapping of the internal Flash is
enabled. For a detailed description refer to Table 10-11. The default state is that dual mapping is
disabled.
0 Dual mapping disabled
1 Dual mapping enabled
Other Exceptions Relocation Control — These bits effect only if ETRE was enabled. See
Table 4-2. Relocation offset:
00 Offset 0
01 Offset 64 Kbytes
10 Offset 512 Kbytes
11 Offset to 0x003F E000
Reserved
1
Bit 15 always comes from the internal Flash Reset Configuration Word (MPC563 only).
This bit should not be set on the MPC561/MPC562.
3 This bit is HC if read from the internal Flash Reset Configuration Word. See Section 21.2.3.1, “Reset Configuration
Word (UC3FCFIG)."
4 Available only on the MPC562/MPC564, software should write "0" to this bit for MPC561/MPC563.
2
7.5.3
Soft Reset Configuration
When a soft reset event occurs, the MPC561/MPC563 reconfigures the development port. Refer to
Chapter 23, “Development Support,” for details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-13
Reset
MPC561/MPC563 Reference Manual, Rev. 1.2
7-14
Freescale Semiconductor
Chapter 8
Clocks and Power Control
The main timing reference for the MPC561/MPC563 can monitor any of the following:
• An external crystal with a frequency of 4 or 20 MHz
• An external frequency source with a frequency of 4 MHz
• An external frequency source at the system frequency
The system operating frequency is generated through a programmable phase-locked loop, the system PLL
(SPLL). The SPLL runs at twice the system speed. The SPLL is programmable in integer multiples of the
input frequency to generate the internal (VCO/2) operating frequency. A pre-divider before the SPLL
enables the division of the high frequency crystal oscillator. The internal operating SPLL frequency should
be at least 30 MHz. It can be divided by a power-of-two divider to generate the system operating
frequencies.
In addition to the system clock, the clocks submodule provides the following:
• TMBCLK to the time base (TB) and decrementer (DEC)
• PITRTCLK to the periodic interrupt timer (PIT) and real-time clock (RTC)
The oscillator, TB, DEC, RTC, and the PIT are powered from the keep alive power supply (KAPWR) pin.
This allows the counters to continue to increment/decrement at the oscillator frequency even when the
main power to the MCU is off. While the power is off, the PIT may be used to signal the power supply IC
to enable power to the system at specific intervals. This is the power-down wake-up feature. When the chip
is not in power-down low-power mode, the KAPWR is powered to the same voltage value as the voltage
of the I/O buffers and logic.
The MPC561/MPC563 clock module consists of the main crystal oscillator, the SPLL, the low-power
divider, the clock generator, the system low-power control block, and the limp mode control block. The
clock module receives control bits from the system clock control register (SCCR), change of lock interrupt
register (COLIR), the PLL low-power and reset-control register (PLPRCR), and the PLL.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-1
Clocks and Power Control
Figure 8-1 is a functional block diagram of the clock unit.
MODCK[1:3]
XFC VDDSYN VSSSYN
EXTCLK
VCOOUT
2:1
MUX
2:1 MUX
SPLL
Lock
GCLK2
TBCLK
System
Low
Power
Control
3:1 MUX
(/4 or /16)
Low
Power
Dividers
(1/2N)
Clock
Drivers
GCLK1 / GCLK2
System Clock
GCLK1C / GCLK2C
System Clock
to RCPU and BBC
CLKOUT
Drivers
ENGCLK
TMBCLK
Driver
Backup Clock
Oscillator Loss
Detector
3:1
MUX
/4 or
/256
XTAL
EXTAL
TMBCLK
RTC / PIT Clock
and Driver
PITRTCLK
Main Clock
Oscillator
Figure 8-1. Clock Unit Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
8-2
Freescale Semiconductor
Clocks and Power Control
8.1
System Clock Sources
The system clock can be provided by the main system oscillator, an external clock input, or the backup
clock (BUCLK) on-chip ring oscillator, see Figure 8-1.
The main system oscillator uses either a 4-MHz or 20-MHz crystal to generate the PLL reference clock.
When the main system oscillator output is the timing reference to the system PLL, skew elimination
between the XTAL/EXTAL pins and CLKOUT is not guaranteed. There is also an on-chip crystal
feedback resistor on the MPC561/MPC563; however, space should be reserved for an off-chip resistor to
allow for future configurations. Figure 8-2 illustrates the main system oscillator crystal configuration.
The external clock input (EXTCLK pin) can receive a clock signal from an external source. The clock
frequency must be in the range of 3-5 MHz or, for 1:1 mode, at the system frequency of at least 15 MHz.
When the external clock input is the timing reference to the system PLL, the skew between the EXTCLK
pin and the CLKOUT is less than ± 1 ns.
The backup clock on-chip ring oscillator allows the MPC561/MPC563 to function with a less precise
clock. When operating from the backup clock, the MPC561/MPC563 is in limp mode. This enables the
system to continue minimum functionality until the system is fixed. The BUCLK frequency is
approximately 11 MHz for the MPC561/MPC563 (see Appendix F, “Electrical Characteristics” for the
complete frequency range).
For normal operation, at least one clock source (EXTCLK or main system oscillator) must be active. A
configuration with both clock sources active is possible as well. At this configuration EXTCLK provides
the system clock and main system oscillator provides the PITRTCLK. The input of an unused timing
reference (EXTCLK or EXTAL) must be grounded.
XTAL
EXTAL
1 MΩ
CL
1
CL
1. Resistor is not currently required on the board but space should be available for its addition in the future.
Figure 8-2. Main System Oscillator Crystal Configuration
8.2
System PLL
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock
input, a feature which offers two benefits: reduces the overall electromagnetic interference generated by
the system, and the ability to oscillate at different frequencies reduces cost by eliminating the need to add
an additional oscillator to a system.
The PLL can perform the following functions:
• Frequency multiplication
• Skew elimination
• Frequency division
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-3
Clocks and Power Control
8.2.1
Frequency Multiplication
The PLL can multiply the input frequency by any integer between one and 4096. The multiplication factor
depends on the value of the MF[0:11] bits in the PLPRCR register. While any integer value from one to
4096 can be programmed, the resulting VCO output frequency must be at least 15 MHz. The multiplication
factor is set to a predetermined value during power-on reset as defined in Table 8-1.
8.2.2
Skew Elimination
The PLL is capable of eliminating the skew between the external clock entering the chip (EXTCLK) and
both the internal clock phases and the CLKOUT pin, making it useful for tight synchronous timings. Skew
elimination is active only when the PLL is enabled and programmed with a multiplication factor of one or
two (MF = 0 or 1). The timing reference to the system PLL is the external clock input (EXTCLK pin).
8.2.3
Pre-Divider
A pre-divider before the phase comparator enables additional system clock resolution when the crystal
oscillator frequency is 20 MHz. The division factor is determined by the DIVF[0:4] bits in the PLPRCR.
8.2.4
PLL Block Diagram
As shown in Figure 8-3, the reference signal, OSCCLK, goes to the phase comparator. The phase
comparator controls the direction (up or down) that the charge pump drives the voltage across the external
filter capacitor (XFC). The direction depends on whether the feedback signal phase lags or leads the
reference signal. The output of the charge pump drives the VCO. The output frequency of the VCO is
divided down and fed back to the phase comparator for comparison with the reference signal, OSCCLK.
The MF values, zero to 4095, are mapped to multiplication factors of one to 4096. Note that when the PLL
is operating in 1:1 mode (refer to Table 8-1), the multiplication factor is one (MF = 0). The PLL output
frequency is twice the maximum system frequency. This double frequency is needed to generate GCLK1
and GCLK2 clocks. On power-up, with a 4-MHz or 20-MHz crystal and the default MF settings,
VCOOUT will be 40 MHz and the system clock will be 20 MHz.
The equation for VCOOUT is:
VCOOUT =
OSCCLK
x (MF + 1) x 2
DIVF + 1
NOTE
When operating with the backup clock, the system clock (and CLKOUT) is
one-half of the ring oscillator frequency, (i.e., the system clock is
approximately 11 MHz). The time base and PIT clocks will be twice the
system clock frequency.
In the case of initial system power up, or if KAPWR is lost, an external circuit must assert power on reset
(PORESET). Once KAPWR is valid, PORESET must be asserted long enough to allow the external
oscillator to start up and stabilize for the device to come out of reset in normal (non limp) mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-4
Freescale Semiconductor
Clocks and Power Control
If limp mode is enabled (by the MODCK[1:3] pins), and PORESET is negated before the external
oscillator has started up, the backup clock, BUCLK, will be used to clock the device. The device will start
to run in limp mode. Software can then switch the clock mode from BUCLK to PLL. If an application
requires that the device always comes out of reset in normal mode, PORESET should be asserted long
enough for the external oscillator to start up. The maximum start-up time of an external oscillator is given
in Appendix F, “Electrical Characteristics” and PORESET should be asserted for this time and at least an
additional 100, 000 input clock cycles.
If limp mode is disabled at reset, a short reset of at least 3 µs is enough to obtain normal chip operation,
because the BUCLK will not start. The system will wait for the external oscillator to start-up and stabilize.
The PLL will begin to lock once PORESET has been negated, assuming stable KAPWR and VDDSYN
power supplies and internal oscillator (or external clock). The PLL maximum lock time is determined by
the input clock to the phase comparator. The PLL locks within 500 input clock cycles if the PLPRCR[MF]
4. HRESET will be released 512
system clock cycles after the PLL locks.
Whenever PORESET is asserted, the MF bits are set according to Table 8-1, and the division factor high
frequency (DFNH) and division factor low frequency (DFNL) bits in SCCR are set to the value of 0 (÷1
for DFNH and ÷2 for DFNL).
XFC
VDDSYN
OSCCLK
Division Factor
DIVF[0:4]
Feedback
Phase
Comparator
Up
Down
VSSSYN
Charge
Pump
VCO
VCOOUT
Clock
Delay
Multiplication Factor
MF[0:11]
Figure 8-3. System PLL Block Diagram
8.2.5
PLL Pins
The following pins are dedicated to the PLL operation:
• VDDSYN — Drain voltage. This is the VDD dedicated to the analog PLL circuits. The voltage
should be well-regulated and the pin should be provided with an extremely low impedance path to
the VDD power rail. VDDSYN should be bypassed to VSSSYN by a 0.1 µF capacitor located as
close as possible to the chip package.
• VSSSYN — Source voltage. This is the VSS dedicated to the analog PLL circuits. The pin should
be provided with an extremely low impedance path to ground. VSSSYN should be bypassed to
VDDSYN by a 0.1 µF capacitor located as close as possible to the chip package.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-5
Clocks and Power Control
•
8.3
XFC — External filter capacitor. XFC connects to the off-chip capacitor for the PLL filter. One
terminal of the capacitor is connected to XFC, and the other terminal is connected to VDDSYN.
— The off-chip capacitor must have the following values:
– 0 < MF + 1 < 4 (1130 x (MF + 1) – 80) pF
– MF + 1 ≥ 42100 x (MF + 1) pF
Where MF = the value stored on MF[0:11]. This is one less than the desired
frequency multiplication.
System Clock During PLL Loss of Lock
At reset, until the SPLL is locked, the SPLL output clock is disabled.
During normal operation (once the PLL has locked), either the oscillator or an external clock source is
generating the system clock. In this case, if loss of lock is detected and the LOLRE (loss of lock reset
enable) bit in the PLPRCR is cleared, the system clock source continues to function as the PLL’s output
clock. The USIU timers can operate with the input clock to the PLL, so that these timers are not affected
by the PLL loss of lock. Software can use these timers to measure the loss-of-lock period. If the timer
reaches the user-preset software criterion, the MPC561/MPC563 can switch to the backup clock by setting
the switch to backup clock (STBUC) bit in the SCCR, provided the limp mode enable (LME) bit in the
SCCR is set.
If loss of lock is detected during normal operation, assertion of HRESET (for example, if LOLRE is set)
disables the PLL output clock until the lock condition is met. During hard reset, the STBUC bit is set as
long as the PLL lock condition is not met and clears when the PLL is locked. If STBUC and LME are both
set, the system clock switches to the backup clock (BUCLK), and the chip operates in limp mode until
STBUC is cleared.
Every change in the lock status of the PLL can generate a maskable interrupt.
NOTE
When the VCO is the system clock source, chip operation is unpredictable
while the PLL is unlocked. Note further that a switch to the backup clock is
possible only if the LME bit in the SCCR is set.
8.4
Low-Power Divider
The output of the PLL is sent to a low-power divider block. (In limp mode the BUCLK is sent to a
low-power divider block.) This block generates all other clocks in normal operation, but has the ability to
divide the output frequency of the VCO before it generates the general system clocks sent to the rest of the
MPC561/MPC563. The PLL VCOOUT is always divided by at least two.
The purpose of the low-power divider block is to allow reduction and restoration of the operating
frequencies of different sections of the MPC561/MPC563 without losing the PLL lock. Using the
low-power divider block, full chip operation can still be obtained, but at a lower frequency. This is called
gear mode. The selection and speed of gear mode can be changed at any time, with changes occurring
immediately.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-6
Freescale Semiconductor
Clocks and Power Control
The low-power divider block is controlled in the system clock control register (SCCR). The default state
of the low-power divider is to divide all clocks by one. Thus, for a 40-MHz system, the general system
clocks are each 40 MHz. Whenever power-on reset is asserted, the MF bits are set according to Table 8-1,
and the division factor high frequency (DFNH) and division factor low frequency (DFNL) bits in SCCR
are set to the value of 0 (÷1 for DFNH and ÷2 for DFNL).
8.5
Internal Clock Signals
The internal clocks generated by the clocks module are shown in Figure 8-4. The clocks module also
generates the CLKOUT and ENGCLK external clock signals. The PLL synchronizes these signals to each
other. The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR.
When the backup clock is functioning as the system clock, the backup clock is automatically selected as
the time base clock source and is twice the MPC561/MPC563 system clock.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-7
Clocks and Power Control
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
T1
T2
T3
T4
Figure 8-4. MPC561/MPC563 Clocks
Note that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than GCLK1 and GCLK2.
This is to enable the external bus operation at lower frequencies (controlled by EBDF in the SCCR).
GCLK2_50 always rises simultaneously with GCLK2. When DFNH = 0, GCLK2_50 has a 50% duty
cycle. With other values of DFNH or DFNL, the duty cycle is less than 50%. Refer to Figure 8-7.
GCLK1_50 rises simultaneously with GCLK1. When the MPC561/MPC563 is not in gear mode, the
falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50. EBDF determines the
division factor between GCLK1/GCLK2 and GCLK1_50/GCLK2_50.
During power-on reset, the MODCK1, MODCK2, and MODCK3 pins determine the clock source for the
PLL and the clock drivers. These pins are latched on the positive edge of PORESET. Their values must be
stable as long as this line is asserted. The configuration modes are shown in Table 8-1. MODCK1 specifies
MPC561/MPC563 Reference Manual, Rev. 1.2
8-8
Freescale Semiconductor
Clocks and Power Control
the input source to the SPLL (main system oscillator or EXTCLK). MODCK1, MODCK2, and MODCK3
together determine the multiplication factor at reset and the functionality of limp mode.
If the configuration of PITRTCLK and TMBCLK and the SPLL multiplication factor is to remain
unchanged in power-down low-power mode, the MODCK signals should not be sampled at wake-up from
this mode. In this case the PORESET pin should remain negated and HRESET should be asserted during
the power supply wake-up stage.
When MODCK1 is cleared, the output of the main oscillator is selected as the input to the SPLL. When
MODCK1 is asserted, the external clock input (EXTCLK pin) is selected as the input to the SPLL. In all
cases, the system clock frequency (freqgclk2) can be reduced by the DFNH[0:2] bits in the SCCR. Note
that freqgclk2(max) occurs when the DFNH bits are cleared.
The TBS bit in the SCCR selects the time base clock to be either the SPLL input clock or GCLK2. When
the backup clock is functioning as the system clock, the backup clock is automatically selected as the time
base clock source.
The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR. When
the backup clock is functioning as the system clock, the backup clock is automatically selected as the time
base clock source.
When the PORESET pin is negated (driven to a high value), the MODCK1, MODCK2, and MODCK3
values are not affected. They remain the same as they were defined during the most recent power-on reset.
Table 8-1 shows the clock configuration modes during power-on reset (PORESET asserted).
NOTE
The MODCK[1:3] are shared functions with IRQ[5:7]. If IRQ[5:7] are used
as interrupts, the interrupt source should be removed during PORESET to
insure the MODCK pins are in the correct state on the rising edge of
PORESET.
Table 8-1. Reset Clocks Source Configuration
Default Values after PORESET
MODCK[1:3]1
000
001
010
011
SPLL Options
LME
RTSEL
RTDIV
MF + 1
PITCLK
Division
TMBCLK
Division
0
0
0
1
4
4
Used for testing purposes.
16
Normal operation, PLL enabled.
Main timing reference is crystal
osc (20 MHz).
Limp mode disabled.
4
Normal operation, PLL enabled.
Main timing reference is crystal
osc (4 MHz).
Limp mode enabled.
16
Normal operation, PLL enabled.
Main timing reference is crystal
osc (20 MHz).
Limp mode enabled.
0
1
1
0
0
0
1
1
1
1
5
1
256
256
256
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-9
Clocks and Power Control
Table 8-1. Reset Clocks Source Configuration (continued)
Default Values after PORESET
MODCK[1:3]1
100
101
110
111
1
LME
RTSEL
RTDIV
PITCLK
Division
MF + 1
SPLL Options
TMBCLK
Division
Normal operation, PLL enabled.
1:1 Mode
0
0
1
1
1
1
1
1
1
1
256
5
16
4
Normal operation, PLL enabled.
Main timing reference is EXTCLK (3-5 MHz).
Limp mode disabled.
16
Normal operation, PLL enabled.
1:1 Mode
Main timing reference is EXTCLK pin (>15MHz)
Limp mode enabled.
256
1
256
Main timing reference is EXTCLK pin (>15MHz)
Limp mode disabled.
indicates MODCK pins value during power-on reset
NOTE
The reset value of the PLL pre-divider is one.
The values of the PITRTCLK clock division and TMBCLK clock division can be changed by software.
The RTDIV bit value in the SCCR register defines the division of PITRTCLK. All possible combinations
of the TMBCLK divisions are listed in Table 8-2.
Table 8-2. TMBCLK Divisions1
1
8.5.1
SCCR[TBS]
MF + 1
TMBCLK
Division
1
—
16
0
1, 2
16
0
>2
4
To ensure correct operation of the time base, keep the system clock to time
base clock ratio above 4 and always set SCCR[TBS] = 1 when running on
the backup clock (limp mode).
General System Clocks
The general system clocks (GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and GCLK2_50) are the
basic clock supplied to all modules and sub-modules on the MPC561/MPC563. GCLK1C and GCLK2C
are supplied to the RCPU and to the BBC. GCLK1C and GCLK2C are stopped when the chip enters the
doze-low power mode. GCLK1 and GCLK2 are supplied to the SIU and the clock module. The external
bus clock GCLK2_50 is the same as CLKOUT. The general system clock defaults to VCO/2 = 20 MHz
(assuming a 20-MHz system frequency) with default power-on reset MF values.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-10
Freescale Semiconductor
Clocks and Power Control
The general system clock frequency can be switched between different values. The highest operational
frequency can be achieved when the system clock frequency is determined by DFNH (CSRC bit in the
PLPRCR is cleared) and DFNH = 0 (division by one). The general system clock can be operated at a low
frequency (gear mode) or a high frequency. The DFNL bits in SCCR define the low frequency. The DFNH
bits in SCCR define the high frequency.
The frequency of the general system clock can be changed dynamically with the system clock control
register (SCCR), as shown in Figure 8-5.
VCO/2 (e.g., 40 MHz)
O
DFNH Divider
DFNH
Normal
O
O
General System Clock
DFNL Divider
DFNL
O
Low Power
Figure 8-5. General System Clocks Select
The frequency of the general system clock can be changed “on the fly” by software. The user may simply
cause the general system clock to switch to its low frequency. However, in some applications, there is a
need for a high frequency during certain periods. Interrupt routines, for example, may require more
performance than the low frequency operation provides, but must consume less power than in maximum
frequency operation. The MPC561/MPC563 provides a method to automatically switch between low and
high frequency operation whenever one of the following conditions exists:
• There is a pending interrupt from the interrupt controller. This option is maskable by the PRQEN
bit in the SCCR.
• The (POW) bit in the MSR is clear in normal operation. This option is maskable by the PRQEN
bit in the SCCR.
When neither of these conditions exists and the CSRC bit in PLPRCR is set, the general system clock
switches automatically back to the low frequency.
Abrupt changes in the divide ratio can cause linear changes in the operating currents of the
MPC561/MPC563.
When the multiplication factor (PLPRCR[MF]) for the PLL is changed, the PLL stops all internal clocks
until the PLL adjusts to the new frequency. This includes stopping the clock to the watchdog timer,
therefore SWT cannot reset the system during this period.
When the clock stops, the current consumed by the device from VDD will fall; it will then rise sharply
when the PLL turns on the PLL output clocks at the new frequency. These abrupt changes in the divide
ratio can cause linear changes in the operating currents of the device. Insure that the proper power supply
filtering is available to handle changes instantaneously. The gear modes (DFNH and DFNL) can be used
to temporarily decrease the system frequency to minimize the demand on the power supply when the MF
or DIVF multiply/divide ratio is changed.
When the general system clock is divided, its duty cycle is changed. One phase remains the same (for
example, 12.5 ns at 40 MHz) while the other becomes longer.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-11
Clocks and Power Control
NOTE
CLKOUT does not have a 50% duty cycle when the general system clock is
divided. The CLKOUT wave form is the same as that of GCLK2_50.
GCLK1 Divide by 1
GCLK2 Divide by 1
GCLK1 Divide by 2
GCLK2 Divide by 2
GCLK1 Divide by 4
GCLK2 Divide by 4
Figure 8-6. Divided System Clocks Timing Diagram
The system clocks GCLK1 and GCLK2 frequency is:
FREQsysmax
FREQ sys = ------------------------------------------------------------------DFNH
DFNL + 1
(2
)or ( 2
)
where FREQsysmax = VCOOUT/2
Therefore, the complete equation for determining the system clock frequency is:
System Frequency=
OSCCLK
DIVF + 1
x
(MF + 1)
(2DNFH) or (2DFNL + 1)
2
x
2
MPC561/MPC563 Reference Manual, Rev. 1.2
8-12
Freescale Semiconductor
Clocks and Power Control
The clocks GCLK1_50 and GCLK2_50 frequency is:
1
FREQsysmax
FREQ 50 = ------------------------------------------------------------------- x -------------------------EBDF
+1
DFNH
DFNL + 1
(2
)or ( 2
)
Figure 8-7 shows the timing of USIU clocks when DFNH = 1 or DFNL = 0.
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
Figure 8-7. Clocks Timing For DFNH = 1 (or DFNL = 0)
8.5.2
Clock Out (CLKOUT)
CLKOUT has the same frequency as the general system clock (GCLK2_50). Unlike the main system clock
GCLK1/GCLK2 however, CLKOUT (and GCLK2_50) represents the external bus clock, and thus will be
one-half of the main system clock if the external bus is running at half speed (EBDF = 0b01). The
CLKOUT frequency (system frequency) defaults to VCO/2. CLKOUT can drive full, half, or quarter
strength; it can also be disabled. The drive strength is controlled in the system clock and reset-control
register (SCCR) by the COM[0:1] and CQDS bits. (See Section 8.11.1, “System Clock Control Register
(SCCR)”). Disabling or decreasing the strength of CLKOUT can reduce power consumption, noise, and
electromagnetic interference on the printed circuit board.
When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low state (provided
that BUCS = 0).
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-13
Clocks and Power Control
8.5.3
Engineering Clock (ENGCLK)
ENGCLK is an output clock with a 50% duty cycle. Its frequency defaults to VCO/128, which is 1/64 of
the main system frequency. ENGCLK frequency can be programmed to the main system frequency
divided by a factor from one to 64, as controlled by the ENGDIV[0:5] bits in the SCCR. ENGCLK can
drive full- or half-strength, or it can also be disabled (remaining in the high state). The drive strength is
controlled by the EECLK[0:1] bits in the SCCR. Disabling ENGCLK can reduce power consumption,
noise, and electromagnetic interference on the printed circuit board.
NOTE
The full strength ENGCLK setting (SCCR[EECLK]=0b01) selects a 5-V
driver while the half-strength selection (SCCR[EECLK]=0b00) is a 2.6-V
driver.
When the PLL is acquiring lock, the ENGCLK signal is disabled and remains in the low state (provided
that BUCS = 0).
NOTE
Skew elimination between CLKOUT and ENGCLK is not guaranteed.
8.6
Clock Source Switching
For limp mode support, clock source switching is supported. If for any reason the clock source for the chip
is not functioning, the option is to switch the system clock to the backup clock ring oscillator, BUCLK.
This circuit consists of a loss-of-clock detector, which sets the LOCS status bit and LOCSS sticky bit in
the PLPRCR. If the LME bit in the SCCR is set, whenever LOCS is asserted, the clock logic switches the
system clock automatically to BUCLK and asserts hard reset to the chip. Switching the system clock to
BUCLK is also possible by software setting the STBUC bit in SCCR. Switching from limp mode to normal
system operation is accomplished by clearing STBUC and LOCSS bits. This operation also asserts hard
reset to the chip.
At HRESET assertion, if the PLL output clock is not valid, the BUCLK will be selected until software
clears LOCSS bit in SCCR. At HRESET assertion, if the PLL output clock is valid, the system will switch
to oscillator/external clock. If during HRESET the PLL loses lock or the clock frequency becomes slower
than the required value, the system will switch to the BUCLK. After HRESET negation the PLL lock
condition does not effect the system clock source selection.
If the LME bit is clear, the switch to the backup clock is disabled and assertion of STBUC bit is ignored.
If the chip is in limp mode, clearing the LME bit switches the system to normal operation and asserts hard
reset to the chip.
Figure 8-8 describes the clock switching control logic. Table 8-3 summarizes the status and control for
each state.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-14
Freescale Semiconductor
Clocks and Power Control
LME = 1
poreset_b = 0
poreset_b = 0
1,BUCLK
poreset_b = 1
LME = 1
else
buclk_enable = 1
& hreset_b = 0
bu
cl
hr k_e
es na
et b
_b le
= =1
1
LME = 0
hreset_b = 0
LOCS=0
buclk_enable = 0
& hreset_b = 0
bu
hreset_b = 1
hresert_b = 0
bu
c
hr lk_e
es n
et ab
_b l e
= =0
1
buclk_enable=0
& hreset_b=0
4, osc
cl
k
as _en
se ab
rt
l
hr e =
es 1
et
_b
3,BUCLK
hreset_b = 1
else
2,BUCLK
6,BULCK
buclk_enable = 1
& hreset_b = 0
5, osc
else
Figure 8-8. Clock Source Switching Flow Chart
NOTE
buclk_enable = (STBUC | LOC) and LME lock indicates loss of lock status
bit (LOCS) for all cases and loss of clock sticky bit (LOCSS) when state 3
is active. When buclk_enable is changed, the chip asserts HRESET to
switch the system clock to BUCLK or PLL.
At PORESET negation, if the PLL is not locked, the loss-of-clock sticky bit
(LOCSS) is asserted, and the chip should operate with BUCLK.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-15
Clocks and Power Control
The switching from state three to state four is accomplished by clearing the
STBUC and LOCSS bits. If the switching is done when the PLL is not
locked, the system clock will not oscillate until lock condition is met.
Table 8-3. Status of Clock Source
STATE
PORESET
HRESET
LME
LOCS
(status)
LOCSS
(sticky)
STBUC
BUCS
Chip
Clock
Source
1
0
0
1
0
0
0
1
BUCLK
2
1
0
1
0/1
0
0
1
BUCLK
1
x2
0/1
0/1
1
BUCLK
0
x2
0
0
Oscillator
2
1
3
4
1
2
1
1
1
0
0/1
5
1
1
0/1
0
x
0
0
Oscillator
6
1
0
1
0/1
1
0/1
1
BUCLK
At least one of the two bits, LOCSS or BUCS, must be asserted (one) in this state.
X = don’t care.
The default value of the LME bit is determined by MODCK[1:3] during assertion of the PORESET line.
The configuration modes are shown in Table 8-1.
8.7
Low-Power Modes
The LPM and other bits in the PLPRCR are encoded to provide one normal operating mode and four
low-power modes. In normal and doze modes the system can be in high state with frequency defined by
the DFNH bits, or in the low state with frequency defined by the DFNL bits. The normal-high operating
mode is the state out of reset. This is also the state of the bits after the low-power mode exit signal arrives.
There are four low-power modes:
• Doze mode
• Sleep mode
• Deep-sleep mode
• Power-down mode
8.7.1
Entering a Low-Power Mode
Low-power modes are enabled by setting the MSR[POW] and clearing the SCCR[LPML]. Once enabled,
a low-power mode is entered by setting the LPM bits to the appropriate value. This can be done only in
one of the normal modes. The user cannot change the PLPRCR[LPM or CSRC] when the MCU is in doze
mode.
NOTE
Higher than desired currents during low-power mode can be avoided by
executing a mullw instruction before entering the low-power mode, i.e.,
anytime after reset and prior to entering the low-power mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-16
Freescale Semiconductor
Clocks and Power Control
Table 8-6 summarizes the control bit settings for the different clock power modes.
Table 8-4. Power Mode Control Bit Settings
8.7.2
Power Mode
LPM[0:1]
CSRC
TEXPS
Normal-high
00
0
X
Normal-low (“gear”)
00
1
X
Doze-high
01
0
X
Doze-low
01
1
X
Sleep
10
X
X
Deep-sleep
11
X
1
Power-down
11
X
0
Power Mode Descriptions
Table 8-5 describes the clock frequency and chip functionality for each power mode.
Table 8-5. Power Mode Descriptions
8.7.3
Power Pins that Need
to be Powered-Up
Operation Mode
SPLL
Clocks
Functionality
Normal-high
Active
Full frequency ÷
2DFNH
Full functions not in use
are shut off
Normal-low (“gear”)
Active
Full frequency ÷
2DFNL+1
Doze-high
Active
Full frequency ÷
2DFNH
Doze-low
Active
Full frequency ÷
2DFNL+1
Sleep
Active
Not active
Deep-sleep
Not active
Not active
KAPWR, IRAMSTBY
Power-down
Not active
Not active
KAPWR, IRAMSTBY
SRAM Standby
Not active
Not active
All On
All On
Enabled: RTC, PIT,
TB and DEC,
controller
Disabled: extended
core
(RCPU, BBC, FPU)
KAPWR, VDDSYN,
VDD, QVDDL, NVDDL,
IRAMSTBY
Enabled: RTC, PIT, TB
and DEC
KAPWR, VDDSYN,
IRAMSTBY
SRAM data
retention
KAPWR, VDDSYN,
VDD, QVDDL, NVDDL,
IRAMSTBY
IRAMSTBY
Exiting from Low-Power Modes
Exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt
generated by the interrupt controller. Any enabled asynchronous interrupt clears the LPM bits but does not
change the PLPRCR[CSRC] bit.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-17
Clocks and Power Control
The return to normal-high mode from normal-low, doze-high, low, and sleep mode is accomplished with
the asynchronous interrupt. The sources of the asynchronous interrupt are:
• Asynchronous wake-up interrupt from the interrupt controller
• RTC, PIT, or time base interrupts (if enabled)
• Decrementer exception
The system responds quickly to asynchronous interrupts. The wake-up time from normal-low, doze-high,
doze-low, and sleep mode caused by an asynchronous interrupt or a decrementer exception is only three
to four clock cycles of maximum system frequency. In 40-MHz systems, this wake-up requires 75 to 100
ns. The asynchronous wake-up interrupt from the interrupt controller is level sensitive one. It will therefore
be negated only after the reset of interrupt cause in the interrupt controller.
The timers’ (RTC, PIT, time base, or decrementer) interrupts indications set status bits in the PLPRCR
(TMIST). The clock module considers this interrupt to be pending asynchronous interrupt as long as the
TMIST is set. The TMIST status bit should be cleared before entering any low-power mode.
Table 8-7 summarizes wake-up operation for each of the low-power modes.
Table 8-6. Power Mode Wake-Up Operation
Wake-up
Method
Return Time from Wake-up
Event to Normal-High
Normal-low (“gear”)
Software
or
Interrupt
Doze-high
Interrupt
Asynchronous interrupts:
3-4 maximum system cycles
Synchronous interrupts:
3-4 actual system cycles
Doze-low
Interrupt
Sleep
Interrupt
3-4 maximum system clocks
Deep-sleep
Interrupt
< 500 Oscillator Cycles
125 µs – 4 MHz
25 µs – 20 MHz
Power-down
Interrupt
< 500 oscillator cycles + power
supply wake-up
IRAMSTBY
External
Power-on sequence
Operation Mode
8.7.3.1
Exiting from Normal-Low Mode
In normal mode (as well as doze mode), if the PLPRCR[CSRC] bit is set, the system toggles between low
frequency (defined by PLPRCR[DFNL]) and high frequency (defined by PLPRCR[DFNH]. The system
switches from normal-low mode to normal-high mode if either of the following conditions is met:
• An interrupt is pending from the interrupt controller; or
• The MSR[POW] bit is cleared (power management is disabled).
When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the asynchronous interrupt
status bits are reset, the system returns to normal-low mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-18
Freescale Semiconductor
Clocks and Power Control
8.7.3.2
Exiting from Doze Mode
The system changes from doze mode to normal-high mode whenever an interrupt is pending from the
interrupt controller.
8.7.3.3
Exiting from Deep-Sleep Mode
The system switches from deep-sleep mode to normal-high mode if any of the following conditions is met:
• An interrupt is pending from the interrupt controller
• An interrupt is requested by the RTC, PIT, or time base
• A decrementer exception
In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500 PLL input
frequency clocks. In one-to-one mode the wake-up time may be up to 100 PLL input frequency clocks.
For a PLL input frequency of 4 MHz, the wake-up time is less than 125 µs.
8.7.3.4
Exiting from Power-Down Mode
Exit from power-down mode is accomplished through hard reset. External logic should assert HRESET in
response to the TEXPS bit being set and TEXP pin being asserted. The TEXPS bit is set by an enabled
RTC, PIT, time base, or decrementer interrupt. The hard reset should be asserted for no longer than the
time it takes for the power supply to wake-up in addition to the PLL lock time. When the TEXPS bit is
cleared (and the TEXP signal is negated), assertion of hard reset sets the bit, causes the pin to be asserted,
and causes an exit from power-down low-power mode. Refer to Section 8.8.3, “Keep-Alive Power” for
more information.
8.7.3.5
Low-Power Modes Flow
Figure 8-9 shows the flow among the different power modes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-19
Clocks and Power Control
(MSR[POW]+Interrupt)+PLPRCR[CSRC]
Software 1
Normal-Low
LPM = 00, CSRC = 1
Software 1
Doze-Low
LPM = 01, CSRC = 1
((MSR[POW]+Interrupt))*CSRC3
Interrupt
Wake-up: 3 - 4 SysFreq
Clocks
Software 1
Software
1
Software 1
Software 1
Doze-High
LPM = 01, CSRC = 0/1
Asynchronous
Interrupts
Wake-up: 3 - 4 Sys
Freqmax Clocks
LPM = 00
CSRC = 0/1
Sleep Mode
LPM = 10, CSRC = 0
Deep-Sleep Mode
LPM = 11, CSRC = 0,
TEXPS = 1
Power-Down Mode
LPM = 11, CSRC = 0,
TEXPS = 02
Normal
High Mode
Async. Wake-up or
RTC/PIT/TB/DEC Interrupt
Wake-up: 500 Input
Frequency Clocks
RTC/PIT/TB/DEC Interrupt
followed by External Hard Reset
Software 1
Hard Reset
1Software
is active only in normal-high/low modes.
TEXPS receives the zero value by writing one. Writing of zero has no effect on TEXPS.
3The switch from normal-high to normal-low is enable only if the conditions to asynchronous interrupt are cleared.
2
Figure 8-9. Low-Power Modes Flow Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
8-20
Freescale Semiconductor
Clocks and Power Control
8.8
8.8.1
Basic Power Structure
General Power Supply Definitions
KAPWR and VSS power the following clock unit modules: oscillator, PITRTCLK and TMBCLK
generation logic, timebase, decrementer, RTC, PIT, system clock control register (SCCR), low-power and
reset-control register (PLPRCR), and reset status register (RSR). All other circuits are powered by the
normal supply pins: VDD, QVDDL, NVDDL, VDDF, VDDSYN, VFLASH, VDDH and VSS. The power
supply for each block is listed in Table 8-7.
Table 8-7. Power Supplies
Circuit
CLKOUT
SPLL (digital),
System low-power control
Internal logic
Clock drivers
Power Supply
NVDDL/QVDDL
SPLL (analog)
VDDSYN
Main oscillator
Reset machine
Limp mode mechanism
Register control
SCCR, PLLRCR and RSR
PPC RTC, PIT, TB, and DEC
KAPWR
CALRAM, DPTRAM, DECRAM
1
IRAMSTBY/VDD1
Keep-alive power is supplied by IRAMSTBY, but run
current is provided through VDD
The following are the relations between different power supplies:
• VDD = QVDDL = NVDDL = VDDSYN = VDDF = 2.6 V ± 0.1 V
• KAPWR = VDD ± 0.2 V (during normal operation)
• VDDH = VDDA = VFLASH = 5.0 ± 5%
• KAPWR = 2.6 ± 0.1 V (during standby operation)
• IRAMSTBY = current source > 50 µA, < 1.75 mA (average)
NOTE
The power supply inputs VDD, QVDDL, NVDDL, VDDSYN, and VDDF
should all be connected to the same 2.6-V power supply. The KAPWR
power supply can be connected to a 2.6-V standby power supply. If
KAPWR is not connected to a standby power supply, it should be connected
to the same power supply as VDD. IRAMSTBY is the input to an
approximately 1.7 volt regulator. It must be connected through a resistor to
a standby power supply. The power supply inputs VDDH and VFLASH
should be connected to the same 5.0-V supply. VDDA can be isolated from
VDDH, but should be the same approximate voltage.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-21
Clocks and Power Control
8.8.2
Chip Power Structure
The MPC561/MPC563 provides a wide range of possibilities for power supply connections. Figure 8-11
illustrates the different power supply sources for each of the basic units on the chip.
8.8.2.1
NVDDL
This supplies the final output stage of the 2.6-V pad output drivers.
8.8.2.2
QVDDL
This supplies all pad logic and pre-driver circuitry, except for the final output stage of the 2.6-V pad output
drivers.
8.8.2.3
VDD
VDD powers the internal logic of the MPC561/MPC563, nominally 2.6V.
8.8.2.4
VDDSYN, VSSSYN
The charge pump and the VCO of the SPLL are fed by a separate 2.6-V power supply (VDDSYN) in order
to improve noise immunity and achieve a high stability in its output frequency. VSSSYN provides an
isolated ground reference for the PLL.
8.8.2.5
KAPWR
The oscillator, time base counter, decrementer, periodic interrupt timer and the real-time clock are fed by
the KAPWR rail. This allows the external power supply unit to disconnect all other sub-units of the MCU
in low-power deep-sleep mode. The TEXP pin (fed by the same rail) can be used by the external power
supply unit to switch between sources. The IRQ[6:7]/MODCK[2:3], IRQ5/MODCK1, XTAL, EXTAL,
EXTCLK, PORESET, HRESET, SRESET, and RSTCONF/TEXP input pins are powered by KAPWR.
Circuits, including pull-up resisters, driving these inputs should be powered by KAPWR.
8.8.2.6
VDDA, VSSA
VDDA supplies power to the analog subsystems of the QADC64E_A and QADC64E_B modules; it is
nominally 5.0 V. VSSA is the ground reference for the analog subsystems.
8.8.2.7
VFLASH
VFLASH supplies the UC3F normal operating voltage. It is nominally 5.0 V. The MPC561 has no
VFLASH signal.
8.8.2.8
VDDF, VSSF
VDDF provides internal core voltage to the UC3F Flash module; it should be a nominal 2.6V. VSSF
provides an isolated ground for the UC3F Flash module. The MPC561 has no VDDF or VSSF signal.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-22
Freescale Semiconductor
Clocks and Power Control
8.8.2.9
VDDH
VDDH provides power for the 5-V I/O operations. It is a nominal 5.0 V.
8.8.2.10
IRAMSTBY
IRAMSTBY is the data retention power supply for all on-board RAM arrays (CALRAM, DPTRAM,
DECRAM). It has a shunt regulator circuit of approximately 1.7 volts that diverts excess current to ground
in order to regulate voltage on the IRAMSTBY power supply pin. Run current is supplied by normal VDD.
IRAMSTBY must be connected to a positive power supply, via a register, and bypassed by a capacitor to
ground (see Figure 8-10. The resistor should sized according to the following equations:
(VSUPPLYMIN – 1.95 V)
> 50 µA
RSUPPLY
(VSUPPLYMAX – 1.35 V)
200-300/freqoscm).
8.8.3.2
Keep-Alive Power Registers Lock Mechanism
The USIU timer, clocks, reset, power, decrementer, and time base registers are powered by the KAPWR
supply. When the main power supply is disconnected after power-down mode is entered, the value stored
in any of these registers is preserved. If power-down mode is not entered before power disconnect, there
is a chance of data loss in these registers. To minimize the possibility of data loss, the MPC561/MPC563
includes a key mechanism that ensures data retention as long as a register is locked. While a register is
locked, writes to this register are ignored.
Each of the registers in the KAPWR region have a key that can be in one of two states: open or locked. At
power-on reset the following keys are locked by default: RTC, RTSEC, RTCAL, and RTCSC. All other
registers are unlocked. Each key has an address associated with it in the internal map.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-25
Clocks and Power Control
A write of 0x55CCAA33 to the associated key register changes the key to the open state. A write of any
other data to this location changes the key to the locked state. The key registers are write-only. A read of
the key register has undefined side effects and may be interpreted as a write that locks the associated
register.
Table 8-8 lists the registers powered by KAPWR and the associated key registers.
Table 8-8. KAPWR Registers and Key Registers
KAPWR Register
Address or
SPR Number
Register
Associated Key Register
Address
Register
0x2F C200
Time Base Status and Control (TBSCR)
See Table 6-18 for bit descriptions.
0x2F C300
Time Base Status and Control Key
(TBSCRK)
0x2F C204
Time Base Reference 0 (TBREF0)
See Section 6.2.2.4.3, “Time Base
Reference Registers (TBREF0 and
TBREF1)” for bit descriptions.
0x2F C304
Time Base Reference 0 Key (TBREF0K)
0x2F C208
Time Base Reference 1 (TBREF1)
See Section 6.2.2.4.3, “Time Base
Reference Registers (TBREF0 and
TBREF1) for bit descriptions.
0x2F C308
Time Base Reference 1 Key (TBREF1K)
0x2F C220
Real Time Clock Status and Control
(RTCSC)
See Table 6-19 for bit descriptions. This
register is locked after reset by default.
0x2F C320
Real Time Clock Status and Control Key
(RTCSCK)
0x2F C224
Real Time Clock (RTC)
See Section 6.2.2.4.6, “Real-Time Clock
Register (RTC)” for bit descriptions. This
register is locked after reset by default.
0x2F C324
Real Time Clock Key (RTCK)
0x2F C228
Real Time Alarm Seconds (RTSEC)
Reserved. This register is locked after
reset by default.
0x2F C328
Real Time Alarm Seconds Key (RTSECK)
0x2F C22C
Real Time Alarm (RTCAL)
See Section 6.2.2.4.7, “Real-Time Clock
Alarm Register (RTCAL)” for bit
descriptions. This register is locked after
reset by default.
0x2F C32C
Real Time Alarm Key (RTCALK)
0x2F C240
PIT Status and Control (PISCR)
See Table 6-20 for bit descriptions.
0x2F C340
PIT Status and Control Key (PISCRK)
0x2F C244
PIT Count (PITC)
See Table 6-21 for bit descriptions.
0x2F C344
PIT Count Key (PITCK)
0x2F C280
System Clock Control Register (SCCR)
See Table 8-9 for bit descriptions.
0x2F C380
System Clock Control Key (SCCRK)
0x2F C284
PLL Low-Power and Reset-Control
Register (PLPRCR)
See Table 8-11 for bit descriptions.
0x2F C384
PLL Low-Power and Reset-Control
Register Key (PLPRCRK)
MPC561/MPC563 Reference Manual, Rev. 1.2
8-26
Freescale Semiconductor
Clocks and Power Control
Table 8-8. KAPWR Registers and Key Registers (continued)
KAPWR Register
Address or
SPR Number
0x2F C288
Associated Key Register
Register
Address
Register
Reset Status Register (RSR)
See Table 7-3 for bit descriptions.
0x2F C388
Reset Status Register Key (RSRK)
SPR 22
Decrementer
See Section 3.9.5, “Decrementer Register
(DEC)” for bit descriptions.
0x2F C30C
Time Base and Decrementer Key (TBK)
SPR 268, 269,
284, 285,
Time Base
See Section 6.2.2.4.2, “Time Base SPRs
(TB),” for bit descriptions.
Figure 8-13 illustrates the process of locking or unlocking a register powered by KAPWR.
Power-On Reset
(Valid for other registers)
Open
Write to the Key 0x55CCAA33
Write to the key other value
Locked
Power On Reset
(Valid for RTC, RTSEC,
RTCAL and RTCSC)
Figure 8-13. Keep-Alive Register Key State Diagram
8.9
IRAMSTBY Supply Failure Detection
A special circuit for IRAMSTBY supply failure detection is provided. In the case of supply failure
detection, the dedicated sticky bits LVSRS in the VSRMCR register are asserted. Software can read or
clear these bits. The user should enable the detector and then clear these bits. If any of the LVSR bits are
read as one, then a power failure of IRAMSTBY has occurred. The circuit is capable of detecting supply
failure below a voltage level to be determined. Also, enable/disable control bit for the IRAMSTBY
detector may be used to disconnect the circuit and save the detector power consumption.
8.10
Power-Up/Down Sequencing
Figure 8-14 and Figure 8-15 detail the power-up sequencing for MPC561/MPC563 during normal
operation. Note that for each of the conditions detailing the voltage relationships the absolute bounds of
the minimum and maximum voltage supply cannot be violated; that is, the value of VDDL cannot fall
below 2.5 V or exceed 2.7 V, and the value of VDDH cannot fall below 4.75 V or exceed 5.25 V for normal
operation. Power consumption during power up sequencing will be below the operating power
consumption.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-27
Clocks and Power Control
During the power down sequence PORESET needs to be asserted while VDD, NVDDL, and QVDDL are
at a voltage greater than or equal to 2.5 V. Below this voltage the power supply chip can be turned off.
If the turn-off voltage of the power supply chip is greater than 0.74 V for the 2.6-V supply and greater than
0.8 V for the 5-V supply, then the circuitry inside the MPC561/MPC563 will act as a load to the respective
supply and will discharge the supply line down to these values. Since the 2.6-V logic represents a larger
load to the supply chip, the 2.6-V supply line will decay faster than the 5-V supply line.
Power On
Operating
See Note 1.
Power Off
See Note 2.
VDDH
VDD, NVVL,
QVDDL
KAPWR
IRAMSTBY
VDDA, VRH
VDDSYN
VFLASH (5 V)
PORESET
HRESET
1
2
3
4
5
VDDH ≥ QVDDL - 0.5 V
VDDA can lag VDDH, and VDDSYN can lag QVDDL, but both must be at a valid level before resets are negated.
If keep-alive functions are NOT used, then when system power is on: KAPWR = QVDDL ± 0.1 V; KAPWR ≤ 2.7 V
If keep-alive functions ARE used, then KAPWR = QVDDL = NVDDL = 2.6 V ± 0.1 V when system power is on
KAPWR = 2.6 V ± 0.1 V when system power is off. IRAMSTBY should be powered prior to the other supplies. If
IRAMSTBY is powered at the same time as the other supplies, it should be allowed to stabilize before PORESET
is negated. Normal system power is defined as QVDDL = VDD = VDDF = VDDSYN = KAPWR = 2.6 ± 0.1 V and
VDDA = VDDH = VFLASH = 5.0 ± 0.25 V. Flash programming requirements are the same as normal system
power. VFLASH should always be 5.0 ± 0.25 V. Note: Flash is not implemented on the MPC561.
Do not hold the 2.6-V supplies at ground while VDDH/VDDA is ramping to 5 V.
If 5 V is applied before the 2.6-V supply, all 5-V outputs will be in indeterminate states until the 2.6-V supply
reaches a level that allows reset to be distributed throughout the device If 5 V is applied before the 2.6-V supply,
all 5-V outputs will be in indeterminate states until the 2.6-V supply reaches a level that allows reset to be
distributed throughout the device
Figure 8-14. No Standby, No KAPWR, All System Power-On/Off
MPC561/MPC563 Reference Manual, Rev. 1.2
8-28
Freescale Semiconductor
Clocks and Power Control
No Battery Connect Battery Power On
Operating
Power Off
No Battery
VDDH
VDD, NVVL,
QVDDL
KAPWR
IRAMSTBY
VDDA, VRH
VDDSYN
VFLASH (5 V)
PORESET
HRESET
1
2
3
4
5
VDDH ≥ QVDDL - 0.5 V
VDDA can lag VDDH, and VDDSYN can lag QVDDL, but both must be at a valid level before resets are negated.
If keep-alive functions are NOT used, then when system power is on: KAPWR = QVDDL ± 0.1 V; KAPWR ≤ 2.7 V
If keep-alive functions ARE used, then KAPWR = QVDDL = NVDDL = 2.6 V ± 0.1 V when system power is on
KAPWR = 2.6 V ± 0.1 V when system power is off. IRAMSTBY should be powered prior to the other supplies. If
IRAMSTBY is powered at the same time as the other supplies, it should be allowed to stabilize before PORESET
is negated. Normal system power is defined as QVDDL = VDD = VDDF = VDDSYN = KAPWR = 2.6 ± 0.1 V and
VDDA = VDDH = VFLASH = 5.0 ± 0.25 V. Flash programming requirements are the same as normal system
power. VFLASH should always be 5.0 ± 0.25 V. Note: Flash is not implemented on the MPC561.
Do not hold the 2.6-V supplies at ground while VDDH/VDDA is ramping to 5 V.
If 5 V is applied before the 2.6-V supply, all 5-V outputs will be in indeterminate states until the 2.6-V supply
reaches a level that allows reset to be distributed throughout the device If 5 V is applied before the 2.6-V supply,
all 5-V outputs will be in indeterminate states until the 2.6-V supply reaches a level that allows reset to be
distributed throughout the device
Figure 8-15. Standby and KAPWR, Other Power-On/Off
NOTE
For more detailed information on power sequencing see Section F.8,
“Power-Up/Down Sequencing.”
8.11
8.11.1
Clocks Unit Programming Model
System Clock Control Register (SCCR)
The SPLL has a 32-bit control register, SCCR, which is powered by keep-alive power.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-29
Clocks and Power Control
MSB
0
1
Field DBCT
2
COM
PORESET
1
0
ID21
HRESET
U
0
ID21
3
4
5
6
7
8
4
DCSLR MFPDL LPML TBS RTDIV
0000
1
9
10
12
13
14
15
STBUC CQDS PRQEN RTSEL BUCS EBDF[0:1] LME
1
0
EQ22
1
Unaffected
Addr
11
1
0
Unaffected
ID[13:14]1 EQ33
ID[13:14]1
U
0x2F C280
LSB
16
17
18
19
EECLK[0:1]
PORESET
0
0
20
21
22
23
ENGDIV[0:5]
1
HRESET
1
1
1
24
25
—
1
26
27
28
DFNL[0:2]
1
—
29
30
31
DFNH[0:2]
0000_0000
Unaffected
0000_0000
1 The hard reset value is a reset configuration word value, extracted from the indicated internal data bus lines. Refer to Section
7.5.2,
“Hard Reset Configuration Word (RCW).”
2 EQ2 = MODCK1
3 EQ3 = (MODCK1 AND MODCK2 AND MODCK3) | (MODCK1 AND MODCK2 AND MODCK3) | (MODCK1 AND MODCK2 AND
MODCK3). See Table 8-1.
4 RTDIV will be 0 if MODCK[1:3] = 000.
Figure 8-16. System Clock and Reset Control Register (SCCR)
NOTE
COM[1] bit default value is determined during by BDRV reset
configuration bit; See Section 7.5.2, “Hard Reset Configuration Word
(RCW).”
Table 8-9. SCCR Bit Descriptions
Bits
Name
Description
0
DBCT
Disable backup clock for timers. The DBCT bit controls the timers clock source while the
chip is in limp mode. If DBCT is set, the timers clock (TMBLCK, PITRCLK) source will not
be the backup clock, even if the system clock source is the backup clock ring oscillator. The
real-time clock source will be EXTAL or EXTCLK according to RTSEL bit (see description
in bit 11 below), and the time base clocks source will be determined according to TBS bit
and MODCK1.
0 If the chip is in limp mode, the timer clock source is the backup (limp) clock
1 The timer clock source is either the external clock or the crystal (depending on the current
clock mode selected)
1:2
COM
Clock Output Mode – The COM and CQDS bits control the output buffer strength of the
CLKOUT and external bus pins. When both COM bits are set the CLKOUT pin is held in
the high (1) state and external bus pins are driven at reduced drive. These bits can be
dynamically changed without generating spikes on the CLKOUT and external bus pins. If
CLKOUT pin is not connected to external circuits, set both bits (disabling CLKOUT) to
minimize noise and power dissipation. The default value for COM[1] is determined by the
BDRV bit in the reset configuration word. See Table 7-5. For CLKOUT control see
Table 8-10.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-30
Freescale Semiconductor
Clocks and Power Control
Table 8-9. SCCR Bit Descriptions (continued)
Bits
Name
Description
3
DCSLR
Disable clock switching at loss of lock during reset. When DCSLR is clear and limp mode
is enabled, the chip will switch automatically to the backup clock if the PLL losses lock
during HRESET. When DCSLR is asserted, a PLL loss-of-lock event does not cause clock
switching. If HRESET is asserted and DCSLR is set, the chip will not negate HRESET until
the PLL acquires lock.
0 Enable clock switching if the PLL loses lock during reset
1 Disable clock switching if the PLL loses lock during reset
4
MFPDL
MF and pre-divider lock. Setting this control bit disables writes to the MF and DIVF bits.
This helps prevent runaway software from changing the VCO frequency and causing the
SPLL to lose lock. In addition, to protect against hardware interference, a hardware reset
will be asserted if these fields are changed while LPML is asserted. This bit is writable once
after power-on reset.
0 MF and DIVF fields are writable
1 MF and DIVF fields are locked
5
LPML
LPM lock. Setting this control bit disables writes to the LPM and CSRC control bits. In
addition, for added protection, a hardware reset is asserted if any mode is entered other
than normal-high mode. This protects against runaway software causing the MCU to enter
low-power modes. (The MSR[POW] bit provides additional protection). LPML is writable
once after power-on reset.)
0 LPM and CSRC bits are writable
1 LPM and CSRC bits are locked and hard reset will occur if the MCU is not in normal-high
mode
6
TBS
7
RTDIV
RTC (and PIT) clock divider. At power-on reset this bit is cleared if MODCK[1:3] are all low;
otherwise the bit is set.
0 RTC and PIT clock divided by 4
1 RTC and PIT clock divided by 256
8
STBUC
Switch to backup clock control. When software sets this bit, the system clock is switched
to the on-chip backup clock ring oscillator, and the chip undergoes a hard reset. The
STBUC bit is ignored if LME is cleared.
0 Do not switch to the backup clock ring oscillator
1 Switch to backup clock ring oscillator
9
CQDS
Clock quarter drive strength — The COM and CQDS bits control the output buffer strength
of the CLKOUT, see Table 8-10.
10
PRQEN
Power management request enable
0 Remains in the lower frequency (defined by DFNL) even if the power management bit in
the MSR is reset (normal operational mode) or if there is a pending interrupt from the
interrupt controller
1 Switches to high frequency (defined by DFNH) when the power management bit in the
MSR is reset (normal operational mode) or there is a pending interrupt from the interrupt
controller
Time base source.
0 Source is OSCCLK divided by either 4 or 16
1 Source is system clock divided by 16
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-31
Clocks and Power Control
Table 8-9. SCCR Bit Descriptions (continued)
Bits
Name
Description
11
RTSEL
RTC circuit input source select. At power-on reset RTSEL receives the value of the
MODCK1 signal. Refer to Table 8-1. Note that if the chip is operating in limp mode (BUCS
= 0), the RTSEL bit is ignored, and the backup clock is the clock source for the RT and PIT
clocks
0 OSCM clock is selected as input to RTC and PIT
1 EXTCLK clock is selected as the RTC and PIT clock source
12
BUCS
Backup clock status. This status bit indicates the current system clock source. When loss
of clock is detected and the LME bit is set, the clock source is the backup clock and this bit
is set. When the STBUC bit and LME bit are set, the system switches to the backup clock
and BUCS is set.
0 System clock is not the backup clock
1 System clock is the backup clock
13:14
EBDF[0:1]
External bus division factor. These bits define the frequency division factor between
(GCLK1 and GCLK2) and (GCLK1_50 and GCLK2_50). CLKOUT is similar to GCLK2_50.
The GCLK2_50 and GCKL1_50 are used by the external bus interface and controller in
order to interface to the external system. The EBDF bits are initialized during hard reset
using the hard reset configuration mechanism.
00 CLKOUT is GCKL2 divided by 1
01 CLKOUT is GCKL2 divided by 2
1x Reserved
Note: If EBDF > 0, an external burst access with short setup timing will corrupt any USIU
register load/store. Refer to Section 10.2.6, “Reduced Data Setup Time.”
15
LME
Limp mode enable. When LME is set, the loss-of-clock monitor is enabled and any
detection of loss of clock will switch the system clock automatically to backup clock. It is
also possible to switch to the backup clock by setting the STBUC bit.
If LME is cleared, the option of using limp mode is disabled. The loss of clock detector is
not active, and any write to STBUC is ignored.
The LME bit is writable once, by software, after power-on reset, when the system clock is
not backup clock (BUCS = 0).
During power-on reset, the value of LME is determined by the MODCK[1:3] bits. (Refer to
Table 8-1.)
0 Limp mode disabled
1 Limp mode enabled
16:17
EECLK[0:1]
Enable engineering clock. This field controls the output buffer voltage of the ENGCLK pin.
When both bits are set the ENGCLK pin is held in the high state. These bits can be
dynamically changed without generating spikes on the ENGCLK pin. If ENGCLK is not
connected to external circuits, set both bits (disabling ENGCLK) to minimize noise and
power dissipation. For measurement purposes the backup clock (BUCLK) can be driven
externally on the ENGCLK pin.
00 Engineering clock enabled, 2.6 V output buffer
01 Engineering clock enabled (slew rate controlled), 5 V output buffer
10 BUCLK is the output on the ENGCLK 2.6 V output buffer
11 Engineering clock disabled
18:23
ENGDIV[0:5] Engineering clock division factor. These bits define the frequency division factor between
VCO/2 and ENGCLK. Division factor can be from 1 (ENGDIV = 000000) to 64 (ENGDIV =
111111). These bits can be read and written at any time. They are not affected by hard
reset but are cleared during power-on reset.
NOTE: If the engineering clock division factor is not a power of two, synchronization
between the system and ENGCLK is not guaranteed.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-32
Freescale Semiconductor
Clocks and Power Control
Table 8-9. SCCR Bit Descriptions (continued)
Bits
Name
24
—
25:27
DFNL[0:2]
28
—
29:31
DFNH
Description
Reserved
Division factor low frequency. The user can load these bits with the desired divide value
and the CSRC bit to change the frequency. Changing the value of these bits does not result
in a loss of lock condition. These bits are cleared by power-on or hard reset. Refer to
Section 8.5.1, “General System Clocks” and Figure 8-5 for details on using these bits.
000 Divide by 2
001 Divide by 4
010 Divide by 8
011 Divide by 16
100 Divide by 32
101 Divide by 64
110 Reserved
111 Divide by 256
Reserved
Division factor high frequency. These bits determine the general system clock frequency
during normal mode. Changing the value of these bits does not result in a loss of lock
condition. These bits are cleared by power-on or hard reset. The user can load these bits
at any time to change the general system clock rate. Note that the GCLKs generated by
this division factor are not 50% duty cycle (i.e. CLKOUT).
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Reserved
Table 8-10. COM and CQDS Bits Functionality
8.11.2
COM[0:1]
CQDS
Function
00
x
Clock Output Enabled Full-Strength Output Buffer, Bus pins full
drive
01
0
Clock Output Enabled Half-Strength Output Buffer, Bus pins
reduced drive
01
1
Clock Output Enabled Quarter-Strength Output Buffer, Bus pins
reduced drive
10
x
Clock Output Disabled, Bus pins full drive
11
x
Clock Output Disabled, Bus pins reduced drive
PLL, Low-Power, and Reset-Control Register (PLPRCR)
The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered by the keep-alive
power supply.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-33
Clocks and Power Control
MSB
0
1
2
3
Field
4
5
6
7
8
9
10
11
12
13
14
15
MF
— LOCS LOCSS SPLS
PORESET
0000_0000_0000 or 0000_0000_1000
0000
HRESET
Unaffected
Addr
0x2F C284
LSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Field SPLSS TEXPS TEXP_INV TMIST — CSRC LPM CSR LOLRE —
PORESET
0
1
HRESET
U
1
30
31
DIVF
00_0000_0000_0000
U
0
U
000
Unaffected
—
Unaffected
Figure 8-17. PLL, Low-Power, and Reset-Control Register (PLPRCR)
Table 8-11. PLPRCR Bit Descriptions
Bits
Name
Description
0:11
MF
Multiplication factor bits. The output of the VCO is divided to generate the feedback signal to
the phase comparator. The MF bits control the value of the divider in the SPLL feedback loop.
The phase comparator determines the phase shift between the feedback signal and the
reference clock. This difference results in either an increase or decrease in the VCO output
frequency.
The MF bits can be read and written at any time. However, this field can be write-protected
by setting the MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the MF bits
causes the SPLL to lose lock. Also, the MF field should not be modified when entering or
exiting from low power mode (LPM change), or when back-up clock is active.
The normal reset value for the DFNH bits is zero (divide by 1). When the PLL is operating in
one-to-one mode, the multiplication factor is set to x1 (MF = 0).
12
—
Reserved
13
LOCS
Loss of clock status. When the oscillator or external clock source is not at the minimum
frequency, the loss-of-clock circuit asserts the LOCS bit. This bit is cleared when the
oscillator or external clock source is functioning normally. This bit is reset only on power-on
reset. Writes to this bit have no effect.
0 No loss of oscillator is currently detected
1 Loss of oscillator is currently detected
14
LOCSS
Loss of clock sticky. If, after negation of PORESET, the loss-of-clock circuit detects that the
oscillator or external clock source is not at a minimum frequency, the LOCSS bit is set.
LOCSS remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. The reset value is determined during hard reset. The STBUC bit will be set
provided the PLL lock condition is not met when HRESET is asserted, and cleared if the PLL
is locked when HRESET is asserted.
0 No loss of oscillator has been detected
1 Loss of oscillator has been detected
15
SPLS
System PLL lock status bit
0 SPLL is currently not locked
1 SPLL is currently locked
MPC561/MPC563 Reference Manual, Rev. 1.2
8-34
Freescale Semiconductor
Clocks and Power Control
Table 8-11. PLPRCR Bit Descriptions (continued)
Bits
Name
Description
16
SPLSS
SPLL lock status sticky bit. An out-of-lock sets the SPLSS bit. The bit remains set until
software clears it by writing a one to it. A write of zero has no effect on this bit. The bit is
cleared at power-on reset. This bit is not affected due to a software initiated loss-of-lock (MF
change and entering deep-sleep or power-down mode). The SPLSS bit is not affected by
hard reset.
0 SPLL has remained in lock
1 SPLL has gone out of lock at least once (not due to software-initiated loss of lock)
17
TEXPS
Timer expired status bit. This bit controls whether the chip negates the TEXP pin in
deep-sleep mode, thus enabling external circuitry to switch off the VDD (power-down mode).
When LPM = 11, CSRC = 0, and TEXPS is high, the TEXP pin remains asserted. When LPM
= 11, CSRC = 0, and TEXPS is low, the TEXPS pin is negated.
To enable automatic wake-up TEXPS is asserted when one of the following occurs:
• The PIT is expired
• The real-time clock alarm is set
• The time base clock alarm is set
• The decrementer exception occurs
• The bit remains set until software clears it by writing a one to it. A write of zero has no
effect on this bit. TEXPS is set by power-on or hard reset.
0 TEXP is negated in deep-sleep mode
1 TEXP pin remains asserted always
18
TEXP_INVP Timer Expired Pin Inversed Polarity – The TEX_INVP bit controls whether the polarity of the
TEXP pin will be active high (normal default) or active low.
0 The TEXP pin is active high
1 The TEXP pin is active low
19
TMIST
Timers interrupt status.TMIST is set when an interrupt from the RTC, PIT, TB or DEC occurs.
The TMIST bit is cleared by writing a one to it. Writing a zero has no effect on this bit. The
system clock frequency remains at its high frequency value (defined by DFNH) if the TMIST
bit is set, even if the CSRC bit in the PLPRCR is set (DFNL enabled) and conditions to switch
to normal-low mode do not exist. This bit is cleared during power-on or hard reset.
0 No timer expired event was detected
1 A timer expire event was detected
20
—
21
CSRC
22:23
LPM
Low-power mode select. These bits are encoded to provide one normal operating mode and
four low-power modes. In normal and doze modes, the system can be in high state
(frequency determined by the DFNH bits) or low state (frequency defined by the DFNL bits).
The LPM field can be write-protected by setting the LPM and CSRC lock (LPML) bit in the
SCCR Refer to Table 8-4 and Table 8-5.
24
CSR
Checkstop reset enable. If this bit is set, then an automatic reset is generated when the
RCPU signals that it has entered checkstop mode, unless debug mode was enabled at reset.
If the bit is clear and debug mode is not enabled, then the USIU will not do anything upon
receiving the checkstop signal from the RCPU. If debug mode is enabled, then the part
enters debug mode upon entering checkstop mode. In this case, the RCPU will not assert
the checkstop signal to the reset circuitry. This bit is writable once after soft reset.
0 No reset will occur when checkstop is asserted
1 Reset will occur when checkstop is asserted
Reserved
Clock source. This bit is cleared at hard reset.
0 General system clock is determined by the DFNH value
1 General system clock is determined by the DFNL value
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-35
Clocks and Power Control
Table 8-11. PLPRCR Bit Descriptions (continued)
Bits
Name
Description
25
LOLRE
Loss of lock reset enable
0 Loss of lock does not cause HRESET assertion
1 Loss of lock causes HRESET assertion
Note: if limp mode is enabled, use the COLIR feature instead of setting the LOLRE bit. See
Section 8.11.3, “Change of Lock Interrupt Register (COLIR).”
26
—
27:31
DIVF
8.11.3
Reserved
The DIVF bits control the value of the pre-divider in the SPLL circuit. The DIVF bits can be
read and written at any time. However, the DIVF field can be write-protected by setting the
MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the DIVF bits causes the SPLL
to lose lock.
Change of Lock Interrupt Register (COLIR)
The COLIR is 16-bit read/write register. It controls the change of lock interrupt generation, and is used for
reporting a loss of lock interrupt source. It contains the interrupt request level and the interrupt status bit.
This register is readable and writable at any time. A status bit is cleared by writing a one (writing a zero
does not affect a status bit’s value). The COLIR is mapped into the MPC561/MPC563 USIU register map.
MSB
0
LSB
1
Field
2
3
4
5
COLIRQ
SRESET
6
7
8
9
10
COLIS
—
COLIE
11
0000_0000_00
Addr
12
13
14
15
—
Unaffected
0x2F C28C
Figure 8-18. Change of Lock Interrupt Register (COLIR)
Table 8-12. COLIR Bit Descriptions
Bits
Name
Description
0:7
COLIRQ
Change of lock interrupt request level. These bits determine the interrupt priority level of the
change of lock. To specify a certain level, the appropriate one of these bits should be set.
8
COLIS
If set (1), the bit indicates that a change in the PLL lock status was detected. The PLL was
locked and lost lock, or the PLL was unlocked and got locked. The bit should be cleared by
writing a one.
9
—
10
COLIE
11:15
—
Reserved
Change of Lock Interrupt enable. If COLIE bit is asserted, an interrupt will be generated
when the COLIS bit is asserted.
0 Change of lock Interrupt disable
1 Change of lock Interrupt enable
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
8-36
Freescale Semiconductor
Clocks and Power Control
8.11.4
IRAMSTBY Control Register (VSRMCR)
This register contains control bits for enabling or disabling the IRAMSTBY supply detection circuit. There
are also four bits that indicate the failure detection. All four bits have the same function and are required
to improve the detection capability in extreme cases.
MSB
0
Field
LSB
1
—
PORESET
2
3
4
5
LVSRS
VSRDE
Unaffected
0
Addr
6
1
7
8
9
10
LVDRS ZOREG
U
11
12
13
14
15
—
0_0000_0000
0x2F C290
U = Unaffected by reset
Figure 8-19. IRAMSTBY Control Register (VSRMCR)
1
This bit is reserved on mask sets which implement bit 7 (ZOREG)
Table 8-13. VSRMCR Bit Descriptions
Bits
Name
0
—
1:4
LVSRS
5
VSRDE1
6
LVDRS
Description
Reserved
Loss of IRAMSTBY sticky. These status bits indicate whether a IRAMSTBY supply failure
occurred. In addition, when the power is turned on for the first time, IRAMSTBY rises and
these bits are set. The LVSRS bits are cleared by writing them to ones. A write of zero has
no effect on these bits.
0 No IRAMSTBY supply failure was detected
1 IRAMSTBY supply failure was detected
IRAMSTBY detector disable.
0 IRAMSTBY detection circuit is enabled
1 IRAMSTBY detection circuit is disabled
Loss of IRAMSTBY for DECRAM Sticky — The status bit, dedicated especially for the BBC
DECRAM, which indicates if there was IRAMSTBY supply failure. When the power is turned
on for the first time, IRAMSTBY rises also and the bits will be asserted. The LVDECRAM bit
can be cleared by writing ones to LVDECRAM. A write of zero has no effect on this bit. The
bit may be used by application software, to decide if there is need to load decompression
vocabularies during reset routine.
0 IRAMSTBY supply failure was not detected
1 IRAMSTBY supply failure was detected
NOTE: The LVDRS bit is provided as a convenience for indicating that the DECRAM has lost
power. It requires that the IRAMSTBY pins are connected to the same power supply. It
actually only monitors the IRAMSTBY supply.
This bit indicates the status of the internal IRAMSTBY supply. This bit is cleared by writing
a 1 to it.
1
7
ZOREG2
8:15
—
0 Internal IRAMSTBY zener regulator has not gone out of regulation
1 Internal IRAMSTBY zener regulator has gone out of regulation.
Note: ZOREG may get set inadvertently if IRAMSTBY is not supplied with at least 150µA.
Reserved
Removed on all parts that have the ZOREG bit.
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Freescale Semiconductor
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Clocks and Power Control
2
ZOREG is not in Rev 0 of the MPC561 but is in all later revisions. It is not in Rev 0 or 0A of the MPC563, but is in Rev
A and later revisions.
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Chapter 9
External Bus Interface
The MPC561/MPC563 external bus is a synchronous, burstable bus. Signals driven on this bus must
adhere to the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support
multiple masters. The MPC561/MPC563 external bus interface architecture supports byte, half-word, and
word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles
controlled by the size outputs (TSIZ0, TSIZ1). For accesses to 16- and 8-bit ports, the slave must be
controlled by the memory controller. For more information, refer to Appendix F, “Electrical
Characteristics.”
9.1
Features
The external bus interface features are listed below:
• 32-bit address bus with transfer size indication (only 24 available on pins)
• 32-bit data bus
• Bus arbitration logic on-chip with external master support
• Chip-select and wait state generation to support peripheral or static memory devices through the
memory controller
• Supports various memory (SRAM, EEPROM) types: synchronous and asynchronous, burstable
and non-burstable
• Supports non-wrap bursts with up to four data beats
• Flash ROM programming support
• Implements the PowerPC ISAarchitecture
• Easy to interface to slave devices
• Bus is synchronous (all signals are referenced to rising edge of bus clock)
• Bus can operate at the same frequency as the internal RCPU core of MPC561/MPC563 or half the
frequency.
9.2
Bus Transfer Signals
The bus transfers information between the MPC561/MPC563 and external memory of a peripheral device.
External devices can accept or provide 8, 16, and 32 data bits in parallel and must follow the handshake
protocol described in this section. The maximum number of bits accepted or provided during a bus transfer
is defined as the port width.
The MPC561/MPC563 has non-multiplexed address and data buses. Control signals indicate the
beginning and type of the cycle, as well as the address space and size of the transfer. The selected device
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9-1
External Bus Interface
then controls the length of the cycle with the signal(s) used to terminate the cycle. A strobe signal for the
address lines indicates the validity of the address.
The MPC561/MPC563 bus is synchronous with a synchronous support. The bus and control input signals
must be timed to setup and hold times relative to the rising edge of the clock. Bus cycles can be completed
in two clock cycles.
For all inputs, the MPC561/MPC563 latches the level of the input during a sample window around the
rising edge of the clock signal. This window is illustrated in Figure 9-1, where tsu and tho are the input
setup and hold times, respectively. To ensure that an input signal is recognized on a specific rising edge of
the clock, that input must be stable during the sample window. If an input makes a transition during the
window time period, the level recognized by the MPC561/MPC563 is not predictable; however, the
MPC561/MPC563 always resolves the latched level to either a logic high or low before using it. In
addition to meeting input setup and hold times for deterministic operation, all input signals must obey the
protocols described in this section.
tho
tsu
Clock
Signal
Sample
Window
Figure 9-1. Input Sample Window
9.3
Bus Control Signals
The MPC561/MPC563 initiates a bus cycle by driving the address, size, address type, cycle type, and
read/write outputs. At the beginning of a bus cycle, TSIZ[0:1] are driven with the address type signals.
TSIZ0 and TSIZ1 indicate the number of bytes remaining to be transferred during an operand cycle
(consisting of one or more bus cycles). These signals are valid at the rising edge of the clock in which the
transfer start (TS) signal is asserted.
The read/write (RD/WR) signal determines the direction of the transfer during a bus cycle. Driven at the
beginning of a bus cycle, RD/WR is valid at the rising edge of the clock in which TS is asserted. The logic
level of RD/WR only changes when a write cycle is preceded by a read cycle or vice versa. The signal may
remain low for consecutive write cycles.
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External Bus Interface
24
1
1
2
4
Bus
Interface
ADDR[8:31]
RD/WR
BURST
TSIZ[0:1]
AT[0:3]
1
PTR
1
BDIP
1
TS
1
RSV
1
KR
1
CR
32
1
Address
and
Transfer
Attributes
Transfer
Start
Reservation
Protocol
DATA[0:31]
Data
BI / STS
1
TA
1
TEA
1
BR
1
BG
1
BB
1
RETRY
Transfer
Cycle
Termination
Arbitration
Figure 9-2. MPC561/MPC563 Bus Signals
9.4
Bus Interface Signal Descriptions
Table 9-1 describes each signal in the bus interface unit. More detailed descriptions can be found in
subsequent subsections. The buses are described in big endian manner, which means that bit 0 is the most
significant bit in a bus (MSB), and bit 31 is the least significant bit (LSB).
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9-3
External Bus Interface
.
Table 9-1. MPC561/MPC563 BIU Signals
Signal Name
Pins
Active
I/O
Description
Address and Transfer Attributes
ADDR[8:31]
Address bus
24
[8:31]
High
O
Specifies the physical address of the bus transaction.
I
Driven by an external bus master when it owns the
external bus. An input for testing purposes only.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Driven high
indicates that a read access is in progress. Driven low
indicates that a write access is in progress.
I
Driven by an external master when it owns the
external bus. Driven high indicates that a read access
is in progress. Driven low indicates that a write access
is in progress.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Driven low
indicates that a burst transfer is in progress. Driven
high indicates that the current transfer is not a burst.
I
Driven by an external master when it owns the
external bus. Driven low indicates that a burst transfer
is in progress. Driven high indicates that the current
transfer is not a burst. The MPC561/MPC563 does
not support burst accesses to internal slaves.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Specifies the
data transfer size for the transaction.
I
Driven by an external master when it owns the
external bus. Specifies the data transfer size for the
transaction.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Indicates
additional type on the current transaction.
I
Only for testing purposes.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Indicates
additional information about the address on the
current transaction.
I
Only for testing purposes.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Indicates
additional information about the address on the
current transaction.
I
Only for testing purposes.
RD/WR
1
HIgh
Read/write
BURST
1
Low
Burst transfer
TSIZ[0:1]
2
High
Transfer size
AT[0:3]
3
High
Address type
RSV
1
Low
Reservation transfer
PTR
1
High
Program trace
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External Bus Interface
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Signal Name
Pins
Active
I/O
Description
O
Driven by the MPC561/MPC563 when it owns the
external bus. It is part of the burst protocol. When
BDIP is asserted, the second beat in front of the
current one is requested by the master. This signal is
negated prior to the end of a burst to terminate the
burst data phase early.
I
Driven by an external master when it owns the
external bus. When BDIP is asserted, the second beat
in front of the current one is requested by the master.
This signal is negated prior to the end of a burst to
terminate the burst data phase early. The
MPC561/MPC563 does not support burst accesses to
internal slaves.
BDIP
1
Low
Burst data in progress
Transfer Start
O
Driven by the MPC561/MPC563 when it owns the
external bus. Indicates the start of a transaction on the
external bus.
I
Driven by an external master when it owns the
external bus. It indicates the start of a transaction on
the external bus or (in show cycle mode) signals the
beginning of an internal transaction.
TS
1
Low
Transfer start
Reservation Protocol
CR
1
Low
I
Cancel reservation
KR
1
Kill reservation
Low
I
Each MPC500 CPU has its own CR signal. Assertion
of CR instructs the bus master to clear its reservation;
some other master has touched its reserved space.
This is a pulsed signal.
In case of a bus cycle initiated by a STWCX
instruction issued by the RCPU to a non-local bus on
which the storage reservation has been lost, this
signal is used by the non-local bus interface to
back-off the cycle. Refer to Section 9.5.10, “Storage
Reservation” for details.
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9-5
External Bus Interface
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Signal Name
Pins
Active
I/O
Description
Data
The data bus has the following byte lane assignments:
Data Byte
Byte Lane
DATA[0:7]
0
DATA[8:15]
1
DATA[16:23]
2
DATA[24:31]
3
O
DATA[0:31]
32
High
Driven by the MPC561/MPC563 when it owns the
external bus and it initiated a write transaction to a
slave device. For single beat transactions, the byte
lanes not selected for the transfer by ADDR[30:31]
and TSIZ[0:1] do not supply valid data.
Data bus
In addition, the MPC561/MPC563 drives the
DATA[0:31] when an external master owns the
external bus and initiated a read transaction to an
internal slave module.
I
Driven by the slave in a read transaction. For single
beat transactions, the MPC561/MPC563 does not
sample byte lanes that are not selected for the transfer
by ADDR[30:31] and TSIZ[0:1].
In addition, an external master that owns the bus and
initiated a write transaction to an internal slave module
drives DATA[0:31].
Transfer Cycle Termination
I
TA
1
Low
Transfer acknowledge
O
TEA
Transfer error
acknowledge
1
Driven by the slave device to which the current
transaction was addressed. Indicates that the slave
has received the data on the write cycle or returned
data on the read cycle. If the transaction is a burst, TA
should be asserted for each one of the transaction
beats.
Driven by the MPC561/MPC563 when the slave
device is controlled by the on-chip memory controller
or when an external master initiated a transaction to
an internal slave module.
I
Driven by the slave device to which the current
transaction was addressed. Indicates that an error
condition has occurred during the bus cycle.
O
Driven by the MPC561/MPC563 when the internal
bus monitor detected an erroneous bus condition, or
when an external master initiated a transaction to an
internal slave module and an internal error was
detected.
Low
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External Bus Interface
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Signal Name
BI / STS
Pins
1
Active
Low
I/O
Description
I
Burst Inhibit: Driven by the slave device to which the
current transaction was addressed. Indicates that the
current slave does not support burst mode.
O
Burst Inhibit: Driven by the MPC561/MPC563 when
the slave device is controlled by the on-chip Memory
Controller. The MPC561/MPC563 also asserts BI for
any external master burst access to internal
MPC561/MPC563 memory space.
Special Transfer Start: Driven by the
MPC561/MPC563 when it owns the external bus.
Indicates the start of a transaction on the external bus
or signals the beginning of an internal transaction in
show cycle mode.
Burst inhibit/
Special Transfer Start
Arbitration
BR
1
I
When the internal arbiter is enabled, BR assertion
indicates that an external master is requesting the
bus.
O
Driven by the MPC561/MPC563 when the internal
arbiter is disabled and the chip is not parked.
Low
Bus request
O
BG
1
Low
Bus grant
I
O
BB
1
Low
Bus busy
I
When the internal arbiter is enabled, the
MPC561/MPC563 asserts this signal to indicate that
an external master may assume ownership of the bus
and begin a bus transaction. The BG signal should be
qualified by the master requesting the bus in order to
ensure it is the bus owner:
Qualified bus grant = BG & ~ BB
When the internal arbiter is disabled, BG is sampled
and properly qualified by the MPC561/MPC563 when
an external bus transaction is to be executed by the
chip.
When the internal arbiter is enabled, the
MPC561/MPC563 asserts this signal to indicate that it
is the current owner of the bus.
When the internal arbiter is disabled, the
MPC561/MPC563 asserts this signal after the
external arbiter has granted the ownership of the bus
to the chip and it is ready to start the transaction.
When the internal arbiter is enabled, the
MPC561/MPC563 samples this signal to get
indication of when the external master ended its bus
tenure (BB negated).
When the internal arbiter is disabled, the BB is
sampled to properly qualify the BG line when an
external bus transaction is to be executed by the chip.
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Freescale Semiconductor
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External Bus Interface
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Signal Name
Pins
Active
I/O
I
RETRY
1
Low
O
Retry
9.5
Description
In the case of regular transaction, this signal is driven
by the slave device to indicate that the
MPC561/MPC563 must relinquish the ownership of
the bus and retry the cycle.
When an external master owns the bus and the
internal MPC561/MPC563 bus initiates access to the
external bus at the same time, this signal is used to
cause the external master to relinquish the bus for one
clock to solve the contention.
Bus Operations
This section provides a functional description of the system bus, the signals that control it, and the bus
cycles provided for data transfer operations. It also describes the error conditions, bus arbitration, and reset
operation.
The MPC561/MPC563 generates a system clock output (CLKOUT). This output sets the frequency of
operation for the bus interface directly. Internally, the MPC561/MPC563 uses a phase-lock loop (PLL)
circuit to generate a master clock for all of the MPC561/MPC563 circuitry (including the bus interface)
which is phase-locked to the CLKOUT output signal.
All signals for the MPC561/MPC563 bus interface are specified with respect to the rising edge of the
external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that
edge. Since the same clock edge is referenced for driving or sampling the bus signals, the possibility of
clock skew could exist between various modules in a system due to routing or the use of multiple clock
lines. It is the responsibility of the system to handle any such clock skew problems that could occur.
9.5.1
Basic Transfer Protocol
The basic transfer protocol defines the sequence of actions that must occur on the MPC561/MPC563 bus
to perform a complete bus transaction. A simplified scheme of the basic transfer protocol is illustrated in
Figure 9-3.
Arbitration
Address Transfer
Data Transfer
Termination
Figure 9-3. Basic Transfer Protocol
The basic transfer protocol provides for an arbitration phase and an address and data transfer phase. The
address phase specifies the address for the transaction and the transfer attributes that describe the
transaction. The data phase performs the transfer of data (if any is to be transferred). The data phase may
transfer a single beat of data (four bytes or less) for nonburst operations, a 4-beat burst of data (4 x 4 bytes),
an 8-beat burst of data (8 x 2 bytes) or a 16-beat burst of data (16 x 1 bytes).
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External Bus Interface
9.5.2
Single Beat Transfer
During the data transfer phase, the data is transferred from master to slave (in write cycles) or from slave
to master (on read cycles).
During a write cycle, the master drives the data as soon as it can, but never earlier than the cycle following
the address transfer phase. The master has to take into consideration the “one dead clock cycle” switching
between drivers to avoid electrical contentions. The master can stop driving the data bus as soon as it
samples the TA line asserted on the rising edge of the CLKOUT.
During a read cycle, the master accepts the data bus contents as valid at the rising edge of the CLKOUT
in which the TA signal is sampled/asserted.
9.5.2.1
Single Beat Read Flow
The basic read cycle begins with bus arbitration, followed by the address transfer, then the data transfer.
The handshakes illustrated in the following flow and timing figures (Figure 9-4, Figure 9-5, and
Figure 9-6) are applicable to the fixed transaction protocol.
Master
Slave
1. Request bus (BR)
2. Receive bus grant (BG) from arbiter
3. Assert bus busy (BB) if no other master is driving bus
4. Assert transfer start (TS)
5. Drive address and attributes
1. Receive address
2. Return data
3. Assert transfer acknowledge (TA)
Figure 9-4. Basic Flow Diagram of a Single Beat Read Cycle
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External Bus Interface
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is valid
Figure 9-5. Single Beat Read Cycle – Basic Timing – Zero Wait States
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External Bus Interface
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
Wait state
Data is valid
Figure 9-6. Single Beat Read Cycle – Basic Timing – One Wait State
9.5.2.2
Single Beat Write Flow
The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer.
The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed
transaction protocol.
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External Bus Interface
Master
Slave
1. Request bus (BR)
2. Receive bus grant (BG) from arbiter
3. Assert bus busy (BB) if no other master is driving bus
4. Assert transfer start (TS)
5. Drive address and attributes
1. Drive data
1. Assert transfer acknowledge (TA)
1. Interrupt data driving
Figure 9-7. Basic Flow Diagram of a Single Beat Write Cycle
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External Bus Interface
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is sampled by slave
Figure 9-8. Single Beat Basic Write Cycle Timing – Zero Wait States
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External Bus Interface
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
Wait state
O
Data is sampled
Figure 9-9. Single Beat Basic Write Cycle Timing – One Wait State
9.5.2.3
Single Beat Flow with Small Port Size
The general case of single beat transfers assumes that the external memory has a 32-bit port size. The
MPC561/MPC563 provides an effective mechanism for interfacing with 16-bit and 8-bit port size
memories, allowing transfers to these devices when they are controlled by the internal memory controller.
In this case, the MPC561/MPC563 attempts to initiate a transfer as in the normal case. If the bus interface
receives a small port size (16 or 8 bits) indication before the transfer acknowledge to the first beat (through
the internal memory controller), the MCU initiates successive transactions until the completion of the data
transfer. Note that all the transactions initiated to complete the data transfer are considered to be part of an
atomic transaction, so the MCU does not allow other unrelated master accesses or bus arbitration to
intervene between the transfers. If any of the transactions except the first is re-tried during an access to a
small port, then a machine-check exception is generated to the RCPU.
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External Bus Interface
CLKOUT
BR
BG
BB
ADDR[0:1]
ADDR + 2
ADDR
RD/WR
TSIZ[0:1]
10
00
BURST, BDIP
TS
STS
Data1
ABCDEFGH
EFGHEFGH
TA
1. For an illustration of device connections on the data bus, see Figure 9-23.
Figure 9-10. Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size
9.5.3
Data Bus Pre-Discharge Mode
Pre-discharge mode is provided for applications that use 3.3-V/5-V external memories while the
MPC561/MPC563 data bus pads are optimized to 2.6-V memories, and cannot tolerate more than 3.1 V.
When connecting 3.3-V devices to the E-bus, and performing read and write operations, this mode should
be invoked in order to avoid long term reliability issues of the data pads.
When the PDMCR2[PREDIS_EN] bit is set, the MPC561/MPC563 will discharge the bus during the
address phase of any write cycle prior to the data phase. The data bus will be discharged from up to 5 V to
a level which is suitable to the low voltage drivers. In most cases, the ORx[EHTR] bit of the relevant
memory bank, should be set along with the PREDIS_EN bit in order to reserve sufficient time for the
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9-15
External Bus Interface
memory to three-state the bus before the bus discharge is initiated. EHTR has a slight performance
reduction impact since it adds a clock gap between some read and write cycles.
NOTE
EHTR also adds one idle clock for two consecutive read cycles from
different memory banks.
NOTE
The pre-disharge will not occur, when using multiple processors with a
common bus accessing an external device, if the processor that initiates a
read is different from the processor that initiated the previous write. Perform
a write to the external device to discharge the external bus, or read a value
of 0x0 from the external device, prior to accessing another MCU on the
same bus.
9.5.3.1
Operating Conditions
Pre-discharge mode should be enabled in the following cases:
• When external devices can charge the data bus to a higher voltage level than 3.1 volts
• And when one or more of the following occurs:
— The MPC561/MPC563 uses write accesses to any external memory
— Data show cycles are enabled
— Instruction show cycles are enabled in code compression mode (MPC562/MPC564 only)
NOTE
In the case of code compression program tracking (3rd case above), the
PREDIS_EN bit should only be set when program tracking is not required
since pre-discharge mode overwrites the compression show cycles data. The
user should not set PREDIS_EN bit when program tracking is required on
development system, and set PREDIS_EN bit on the production version.
EHTR can always be set to keep the same system performance during
development, and production phases.
9.5.3.2
Initialization Sequence
Systems that require pre-discharge operation should include the following steps:
• Execute boot sequence
• Set EHTR bit in all relevant memory banks during the memory controller initialization phase
(configure ORx, and BRx) if it is required to extend the time between read cycles, and
pre-discharge phase of write cycles.
• Set PREDIS_EN in PDMCR2 register
• Start to write data to external devices
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External Bus Interface
Refer to Section 2.4, “Pad Module Configuration Register (PDMCR2),” and Section 10.9.4, “Memory
Controller Option Registers (OR0–OR3),” for more information on PREDIS_EN, and EHTR
configuration bits.
CLKOUT
ADDR[8:31]
Read Cycle
Write Cycle
EHTR provides 1 clock
gap to three-state data bus
TS
RD/WR
TA
OE
Pre-discharge
to low voltage
Data
Read Data
Write Data
Figure 9-11. Read Followed by Write when Pre-Discharge Mode is Enabled, and EHTR is Set
9.5.4
Burst Transfer
The MPC561/MPC563 uses non-wrapping burst transfers to access operands of up to 32 bytes (eight
words). A non-wrapping burst access stops accessing the external device when the word address is modulo
four/eight. Burst configuration is determined by the value of BURST_EN in the SIUMCR register. See
Chapter 5, “Unified System Interface Unit (USIU) Overview” for further details. The MPC561/MPC563
begins the access by supplying a starting address that points to one of the words in the array and requires
the memory to sequentially drive or sample each word on the data bus. The selected slave device must
internally increment ADDR28 and ADDR29 (and ADDR30 in the case of a 16-bit port slave device, and
also ADDR31 in the case of an 8-bit port slave device) of the supplied address for each transfer, causing
the address to reach a four/eight word boundary, and then stop. The address and transfer attributes supplied
by the MPC561/MPC563 remain stable during the transfers. The selected device terminates each transfer
by driving or sampling the word on the data bus and asserting TA.
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9-17
External Bus Interface
The MPC561/MPC563 also supports burst-inhibited transfers for slave devices that are unable to support
bursting. For this type of bus cycle, the selected slave device supplies or samples the first word the
MPC561/MPC563 points to and asserts the burst-inhibit signal with TA for the first transfer of the burst
access. The MPC561/MPC563 responds by terminating the burst and accessing the remainder of the
16-byte block. These remaining accesses use up to three read/write bus cycles (each one for a word) in the
case of a 32-bit port width slave, up to seven read/write bus cycles in the case of a 16-bit port width slave,
or up to fifteen read/write bus cycles in the case of a 8-bit port width slave.
The general case of burst transfers assumes that the external memory has a 32-bit port size. The
MPC561/MPC563 provides an effective mechanism for interfacing with 16-bit and 8-bit port size
memories, allowing bursts transfers to these devices when they are controlled by the internal memory
controller.
In this case, the MPC561/MPC563 attempts to initiate a burst transfer as in the normal case. If the memory
controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the
burst is accepted, the bus interface completes a burst of 16 or 8 beats respectively for four words. Eight
words requires 32 or 16 beats. Each beat of the burst transfers only one or two bytes effectively. Note that
this burst of 8 or 16 beats is considered an atomic transaction, so the MPC561/MPC563 does not allow
other unrelated master accesses or bus arbitration to intervene between the transfers.
9.5.5
Burst Mechanism
In addition to the standard bus signals, the MPC561/MPC563 burst mechanism uses the following signals:
• The BURST signal indicates that the cycle is a burst cycle.
• The burst data in progress (BDIP) signal indicates the duration of the burst data.
• The burst inhibit (BI) signal indicates whether the slave is burstable.
At the start of the burst transfer, the master drives the address, the address attributes, and the BURST signal
to indicate that a burst transfer is being initiated, and asserts TS. If the slave is burstable, it negates the
burst-inhibit (BI) signal. If the slave cannot burst, it asserts BI. For additional details, refer to
Section 10.2.5, “Burst Support.”
During the data phase of a burst-write cycle, the master drives the data. It also asserts BDIP if it intends to
drive the data beat following the current data beat. When the slave has received the data, it asserts TA to
indicate to the master that it is ready for the next data transfer. The master again drives the next data and
asserts or negates the BDIP signal. If the master does not intend to drive another data beat following the
current one, it negates BDIP to indicate to the slave that the next data beat transfer is the last data of the
burst-write transfer.
BDIP has two basic timings: normal and late (see Figure 9-14 and Figure 9-15). In the late timing mode,
assertion of BDIP is delayed by the number of wait states in the first data beat. This implies that for
zero-wait-state cycles, BDIP assertion time is identical in normal and late modes. Cycles with late BDIP
generation can occur only during cycles for which the memory controller generates TA internally. Refer
to Chapter 10, “Memory Controller” for more information.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-18
Freescale Semiconductor
External Bus Interface
In the MPC561/MPC563, no internal master initiates write bursts. The MPC561/MPC563 is designed to
perform this kind of transaction in order to support an external master that is using the memory controller
services. Refer to Section 10.8, “Memory Controller External Master Support.”
During the data phase of a burst-read cycle, the master receives data from the addressed slave. If the master
needs more than one data beat, it asserts BDIP. Upon receiving the second-to-last data beat, the master
negates BDIP. The slave stops driving new data after it receives the negation of the BDIP signal at the
rising edge of the clock.
Burst inputs (reads) in the MPC561/MPC563 are used only for instruction cycles. Data load cycles are not
supported.
Figures 9-12 through 9-21 are examples of various burst cycles, including illustrations of burst-read and
burst-write cycles for both the 16- and 32-bit port sizes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-19
External Bus Interface
Master
Slave
1. Request Bus (BR)
2. Receive bus grant (BG) from arbiter
3. Assert Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drive Address and Attributes
6. Drive BURST Asserted
ADDR[28:29] mod 4 =?
Receive Address
=0
Assert BDIP
Return Data
Assert Transfer Acknowledge (TA)
Receive Data
=1
BDIP Asserted
Assert BDIP
Receive Data
Assert BDIP
Drive Last Data
& Assert TA
Return Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
No
Drive Last Data
& Assert TA
Yes
Negate Burst Data in Progress (BDIP)
Return Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Receive Data
=4
No
Yes
Receive Data
=3
Drive Last Data
& Assert TA
Yes
Return Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
=2
No
No
Drive Last Data
& Assert TA
Yes
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9-20
Freescale Semiconductor
External Bus Interface
Figure 9-12. Basic Flow Diagram Of A Burst-Read Cycle
CLKOUT
BR
BG
BB
ADDR[8:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
O
Expects Another Data
BDIP
O
O
O
Data
No Data
Expected
TA
O
O
Data
is Valid
O
Data
is Valid
O
Data
is Valid
Data
is Valid
Figure 9-13. Burst-Read Cycle – 32-Bit Port Size – Zero Wait State
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Freescale Semiconductor
9-21
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[8:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
O
Expects Another Data
BDIP
Normal
Late
O
O
No Data
Expected
O
Data
TA
O
Wait State
O
Data
is Valid
O
O
Data
is Valid
Data
is Valid
Data
is Valid
Figure 9-14. Burst-Read Cycle – 32-Bit Port Size – One Wait State
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Freescale Semiconductor
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[8:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Normal or Late
BDIP
Last Beat
O
Expects Another Data
O
O
O
O
No Data
Expected
O
Data
TA
Data
is Valid
O
Data
is Valid
O
Data
is Valid
Data
is Valid
Wait State
Figure 9-15. Burst-Read Cycle – 32-Bit Port Size – Wait States Between Beats
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-23
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[8:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
BDIP
Data[0:15]
TA
Figure 9-16. Burst-Read Cycle – 16-Bit Port Size
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9-24
Freescale Semiconductor
External Bus Interface
External Master
Slave
1. Request Bus (BR)
2. Receive Bus Grant (BG) from Arbiter
3. Assert Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drive Address and Attributes
6. Drive BURST Asserted
7. MTS Asserted (from MPC500 Device)
Drive data
Receive Address
ADDR[28:29] mod 4 =?
=0
Assert BDIP
Drive Data
=1
Assert BDIP
Drive Data
=2
Assert BDIP
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Don’t Sample
Next Data
Yes
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
No
Don’t Sample
Next Data
No
Don’t Sample
Next Data
Yes
Sample Data
Assert Transfer Acknowledge (TA)
Drive Data
BDIP Asserted
=3
No
Yes
Negate Burst Data in Progress (BDIP)
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Stop Driving Data
No
Don’t Sample
Next Data
Yes
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-25
External Bus Interface
Figure 9-17. Basic Flow Diagram of a Burst-Write Cycle
CLKOUT
BR1
BG1
BB1
ADDR[8:31]
ADDR[28:29] = 00
RD/WR1
TSIZ[0:1]
00
BURST1
TS1
MTS
BDIP1
Will Drive Another Data
O
O
Last Beat
O
O
No Data
Expected
Data
TA
O
O
O
O
Data
Data
Data
Data
is Sampled is Sampled is Sampledis Sampled
1From
external master
Figure 9-18. Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
(Only for External Master Memory Controller Service Support)
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Freescale Semiconductor
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[0:27]
ADDR[28:29]
0
1
2
3
ADDR[30:31]
RD/WR
TSIZ[0:1]
00
BURST1
TS
BDIP1
Data
TA
BI
1
BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst, but the USIU splits it into a sequence of
normal cycles.
Figure 9-19. Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst)
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Freescale Semiconductor
9-27
External Bus Interface
CLKOUT
BR
BG
BB
ADDR(0:29)
n (n modulo 4 = 1)
ADDR[30:31]
RD/WR
TSIZ[0:1]
00
BURST
TS
Expects Another Data
BDIP
O
O
Data
TA
BI
Figure 9-20. Non-Wrap Burst with Three Beats
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9-28
Freescale Semiconductor
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[0:29]
ADDR[30:31]
n (n modulo 4 = 3)
00
RD/WR
TSIZ[0:1]
00
BURST
TS
Is Never Asserted
BDIP
First and Last Beat
Data
TA
O
DATA
is Sampled
Figure 9-21. Non-Wrap Burst with One Data Beat
9.5.6
Alignment and Packaging of Transfers
The MPC561/MPC563 external bus requires natural address alignment:
• Byte accesses allow any address alignment
• Half-word accesses require address bit 31 to equal zero
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-29
External Bus Interface
•
•
Word accesses require address bits 30 – 31 to equal zero
Burst accesses require address bits 30 – 31 to equal zero
The MPC561/MPC563 performs operand transfers through its 32-bit data port. If the transfer is controlled
by the internal memory controller, the MPC561/MPC563 can support 8- and 16-bit data port sizes.
The bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed.
A 32-bit port resides on DATA[0:31], a 16-bit port must reside on DATA[0:15], and an 8-bit port must
reside on DATA[0:7]. The MPC561/MPC563 always tries to transfer the maximum amount of data on all
bus cycles. For a word operation, it always assumes that the port is 32 bits wide when beginning the bus
cycle.
In Figure 9-22, Figure 9-23, Table 9-2, and Table 9-3, the following conventions are used:
• OP0 is the most-significant byte of a word operand and OP3 is the least-significant byte.
• The two bytes of a half-word operand are either OP0 (most-significant) and OP1 or OP2
(most-significant) and OP3, depending on the address of the access.
• The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of
the access.
0
31
OP0
OP1
OP0
OP1
OP2
OP3
OP2
OP3
Word
Half-word
OP0
OP1
Byte
OP2
OP3
Figure 9-22. Internal Operand Representation
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Freescale Semiconductor
External Bus Interface
Figure 9-23 illustrates the device connections on the data bus.
0
31
OP0
OP1
DATA[0:7]
OP2
DATA[8:15]
OP0
OP1
OP0
OP1
OP2
OP3
Interface
Output
Register
OP3
DATA[16:23]
OP2
DATA[24:31]
OP3
32-bit Port Size
16-bit Port Size
OP0
OP1
8-bit Port Size
OP2
OP3
Figure 9-23. Interface To Different Port Size Devices
Table 9-2 lists the bytes required on the data bus for read cycles.
Table 9-2. Data Bus Requirements For Read Cycles
Address
Transfer
Size
Byte
Half-word
Word
32-bit Port Size
16-bit Port Size
8-bit
Port
Size
TSIZE
[0:1]
ADDR
[30:31]
DATA
[0:7]
DATA
[8:15]
DATA
[16:23]
DATA
[24:31]
DATA
[0:7]
DATA
[8:15]
DATA
[0:7]
01
00
OP0
—
—
—
OP0
—
OP0
01
01
—
OP1
—
—
—
OP1
OP1
01
10
—
—
OP2
—
OP2
—
OP2
01
11
—
—
—
OP3
—
OP3
OP3
10
00
OP0
OP1
—
—
OP0
OP1
OP0
10
10
—
—
OP2
OP3
OP2
OP3
OP2
00
00
OP0
OP1
OP2
OP3
OP0
OP1
OP0
Note: “—” denotes a byte not required during that read cycle.
MPC561/MPC563 Reference Manual, Rev. 1.2
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9-31
External Bus Interface
Table 9-3 lists the patterns of the data transfer for write cycles when the MPC561/MPC563 initiates an
access.
Table 9-3. Data Bus Contents for Write Cycles
Address
Transfer
Size
TSIZE[0:1]
Byte
Half-word
Word
External Data Bus Pattern
ADDR
[30:31]
DATA
[0:7]
DATA
[8:15]
DATA
[16:23]
DATA
[24:31]
01
00
OP0
—
—
—
01
01
OP1
OP1
—
—
01
10
OP2
—
OP2
—
01
11
OP3
OP3
—
OP3
10
00
OP0
OP1
—
—
10
10
OP2
OP3
OP2
OP3
00
00
OP0
OP1
OP2
OP3
Note: “—” denotes a byte not driven during that write cycle.
9.5.7
Arbitration Phase
The external bus design provides for a single bus master at any one time, either the MPC561/MPC563 or
an external device. One or more of the external devices on the bus can have the capability of becoming bus
master for the external bus. Bus arbitration may be handled either by an external central bus arbiter or by
the internal on-chip arbiter. In the latter case, the system is optimized for one external bus master besides
the MPC561/MPC563. The arbitration configuration (external or internal) is set at system reset.
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. The device that
needs the bus asserts BR. The device then waits for the arbiter to assert BG. In addition, the new master
must look at BB to ensure that no other master is driving the bus before it can assert BB to assume
ownership of the bus. Any time the arbiter has taken the bus grant away from the master and the master
wants to execute a new cycle, the master must re-arbitrate before a new cycle can be executed. The
MPC561/MPC563, however, guarantees data coherency for access to a small port size and for decomposed
bursts. This means that the MPC561/MPC563 will not release the bus before the completion of the
transactions that are considered atomic. Figure 9-24 describes the basic protocol for bus arbitration.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-32
Freescale Semiconductor
External Bus Interface
Requesting Device
Arbiter
Request the Bus
1. Assert BR
Grant Bus arbitration
Acknowledge Bus Mastership
1. Wait for BB to be negated.
2. Assert BB to become next master
3. Negate BR
Operate as Bus Master
1. Assert BG
Terminate Arbitration
1. Negate BG (or keep asserted to park
bus master
1. Perform data transfer
Release Bus Mastership
1. Negate BB
Figure 9-24. Bus Arbitration Flowchart
9.5.7.1
Bus Request
The potential bus master asserts BR to request bus mastership. BR should be negated as soon as the bus is
granted, the bus is not busy, and the new master can drive the bus. If more requests are pending, the master
can keep asserting its bus request as long as needed. When configured for external central arbitration, the
MPC561/MPC563 drives this signal when it requires bus mastership. When the internal on-chip arbiter is
used, this signal is an input to the internal arbiter and should be driven by the external bus master.
9.5.7.2
Bus Grant
The arbiter asserts BG to indicate that the bus is granted to the requesting device. This signal can be
negated following the negation of BR or kept asserted for the current master to park the bus.
When configured for external central arbitration, BG is an input signal to the MPC561/MPC563 from the
external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter
to the external bus master.
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Freescale Semiconductor
9-33
External Bus Interface
9.5.7.3
Bus Busy
BB assertion indicates that the current bus master is using the bus. New masters should not begin transfer
until this signal is negated. The bus owner should not relinquish or negate this signal until the transfer is
complete. To avoid contention on the BB line, the master should three-state this signal when it gets a
logical one value. This requires the connection of an external pull-up resistor to ensure that a master that
acquires the bus is able to recognize the BB line negated, regardless of how many cycles have passed since
the previous master relinquished the bus. Refer to Figure 9-25.
Master
External Bus
MPC500 Device
(Slave 1)
TS
BB
Slave 2
Figure 9-25. Master Signals Basic Connection
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Freescale Semiconductor
External Bus Interface
CLKOUT
BR0
BG0
BR1
BG1
BB
ADDR[8:31]
and Attributes
TS
TA
Master 0
“Turns On” and
Drives Signals
Master 0
Negates BB
and “Turns Off”
(Three-state Controls)
Master 1
“Turns On” and
Drives Signals
Figure 9-26. Bus Arbitration Timing Diagram
9.5.7.4
Internal Bus Arbiter
The MPC561/MPC563 can be configured at system reset to use the internal bus arbiter. In this case, the
MPC561/MPC563 will be parked on the bus. The parking feature allows the MPC561/MPC563 to skip the
bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from
the arbiter.
The priority of the external device relative to the internal MPC561/MPC563 bus masters is programmed
in the SIU module configuration register. If the external device requests the bus and the MPC561/MPC563
does not require it, or if the external device has higher priority than the current internal bus master, the
MPC561/MPC563 grants the bus to the external device.
Table 9-4 describes the priority mechanism used by the internal arbiter.
MPC561/MPC563 Reference Manual, Rev. 1.2
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External Bus Interface
Table 9-4. Priority Between Internal and External Masters over External Bus1
1
2
Type
Direction
Priority
Parked access2
Internal → external
0
Instruction access
Internal → external
3
Data access
Internal → external
4
External access
external → external/internal
EARP (could be programmed to 0 – 7)
External master will be granted external bus ownership if EARP is greater than the internal access priority.
Parked access is instruction or data access from the RCPU which is initiated on the internal bus without
requesting it first in order to improve performance.
Figure 9-27 illustrates the internal finite-state machine that implements the arbiter protocol.
External
Owner
BG = 0
BB = three
state
BB
=
1,
BR = 1
BR
BR
=1
=
0
External Master
Requests Bus
MPC500 Device
Internal Master With Higher
Priority than the External Device
Requires the Bus
External Master
Release Bus
BB = 0
MPC500
Device
Bus Wait
BG = 1
BB = three
state
IDLE
BG = 1
BB = three
state
MCU Needs
the Bus
BB = 1
MPC500 Device
No Longer
Needs the Bus
MPC500
Device Owner
BR = 0
External Device With Higher
Priority than the Current Internal
Bus Master Requests the Bus
BG = 1
BB = 0
MPC500 Device
Still Needs
the Bus
Figure 9-27. Internal Bus Arbitration State Machine
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External Bus Interface
9.5.8
Address Transfer Phase Signals
Address transfer phase signals include the following:
• Transfer start
• Address bus
• Transfer attributes
Transfer attributes signals include RD/WR, BURST, TSIZ[0:1], AT[0:3], STS, and BDIP. With the
exception of the BDIP, these signals are available at the same time as the address bus.
9.5.8.1
Transfer Start
This signal (TS) indicates the beginning of a transaction on the bus addressing a slave device. This signal
should be asserted by a master only after the ownership of the bus was granted by the arbitration protocol.
This signal is asserted for the first cycle of the transaction only and is negated in successive clock cycles
until the end of the transaction. The master should three-state this signal when it relinquishes the bus to
avoid contention between two or more masters in this line. This situation indicates that an external pull-up
resistor should be connected to the TS signal to avoid having a slave recognize this signal as asserted when
no master drives it. Refer to Figure 9-25.
9.5.8.2
Address Bus
The address bus consists of 32 bits, with ADDR0 the most significant bit and ADDR31 the least significant
bit. Only 24 bits (ADDR[8:31]) are available external to the MPC561/MPC563. The bus is
byte-addressable, so each address can address one or more bytes. The address and its attributes are driven
on the bus with the transfer start signal and kept valid until the bus master receives the transfer
acknowledge signal from the slave. To distinguish the individual byte, the slave device must observe the
TSIZ signals.
9.5.8.3
Read/Write
A high value on the RD/WR line indicates a read access. A low value indicates a write access.
9.5.8.4
Burst Indicator
BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate that
the transfer is a burst transfer.
The MPC561/MPC563 supports a non-wrapping, 8-beat maximum (with 32-bit port), critical word first
burst type. The maximum burst size is 32 bytes. For a 16-bit port, the burst includes 16 beats. For an 8-bit
port, the burst includes 32 beats at most.
NOTE
8- and 16-bit ports must be controlled by the memory controller.
The actual size of the burst is determined by the address of the starting word of the burst. Refer to Table 9-5
and Table 9-6.
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External Bus Interface
Table 9-5. 4 Word Burst Length and Order
Starting
Address
ADDR[28:29]
Burst Order (Assuming
32-bit Port Size)
Burst Length in
Words (Beats)
Burst Length
in Bytes
00
word 0 → word 1 →
word 2 → word 3
4
16
01
word 1 → word 2 → word 3
3
12
10
word 2 → word 3
2
8
11
word 3
1
4
9.5.8.5
Comments
BDIP never asserted
Transfer Size
The transfer size signals (TSIZ[0:1]) indicate the size of the requested data transfer. During each transfer,
the TSIZ signals indicate how many bytes are remaining to be transferred by the transaction. The TSIZ
signals can be used with BURST and ADDR[30:31] to determine which byte lanes of the data bus are
involved in the transfer. For non-burst transfers, the TSIZ signals specify the number of bytes starting from
the byte location addressed by ADDR[30:31]. In burst transfers, the value of TSIZ is always 00.
Table 9-6. BURST/TSIZE Encoding
9.5.8.6
BURST
TSIZ[0:1]
Transfer Size
Negated
01
Byte
Negated
10
Half-word
Negated
11
x
Negated
00
Word
Asserted
00
Burst (16 or 32 bytes)
Address Types
The address type (AT[0:3]), program trace (PTR), and reservation transfer (RSV) signals are outputs that
indicate one of 16 address types. These types are designated as either a normal or alternate master cycle,
user or supervisor, and instruction or data type. The address type signals are valid at the rising edge of the
clock in which the special transfer start (STS) signal is asserted.
A special use of the PTR and RSV signals is for the reservation protocol described in Section 9.5.10,
“Storage Reservation.” Refer to Section 9.5.14, “Show Cycle Transactions” for information on show
cycles.
Table 9-7 summarizes the pins used to define the address type. Table 9-8 lists all the definitions achieved
by combining these pins.
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External Bus Interface
Table 9-7. Address Type Pins
Pin
:
Function
STS
0 Special transfer
1 Normal transfer
TS
0 Start of transfer
1 No transfer
AT0
Must equal zero on MPC561/MPC563
AT1
0 Supervisor mode
1 User mode
AT2
0 Instruction
1 Data
AT3
Reservation/Program Trace
PTR
0 Program trace
1 No program trace
RSV
0 Reservation data
1 No reservation
Table 9-8. Address Types Definition
STS
TS
AT0
AT1
AT2
AT3
PTR
RSV
1
x
x
x
x
x
1
1
No transfer
0
01
0
0
0
0
0
1
RCPU, normal instruction, program trace, supervisor mode
1
1
1
RCPU, normal instruction, supervisor mode
0
1
0
RCPU, reservation data, supervisor mode
1
1
1
RCPU, normal data, supervisor mode
0
0
1
RCPU, normal instruction, program trace, user mode
1
1
1
RCPU, normal instruction, user mode
0
1
0
RCPU, reservation data, user mode
1
1
1
RCPU, normal data, user mode
1
1
0
1
1
Address Space Definitions
1
?
?
?
1
1
Reserved
0
0
0
0
0
1
RCPU, show cycle address instruction, program trace,
supervisor mode
1
1
1
RCPU, show cycle address instruction, supervisor mode
0
1
0
RCPU, reservation show cycle data, supervisor mode
1
1
1
RCPU, show cycle data, supervisor mode
0
0
1
RCPU, show cycle address instruction, program trace, user
mode
1
1
1
RCPU, show cycle address instruction, user mode
0
1
0
RCPU, reservation show cycle data, user mode
1
1
1
RCPU, show cycle data, user mode
?
1
1
Reserved
1
1
0
1
1
?
?
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External Bus Interface
1
Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute.
9.5.8.7
Burst Data in Progress
This signal is sent from the master to the slave to indicate that there is a data beat following the current
data beat. The master uses this signal to give the slave advance warning of the remaining data in the burst.
BDIP can also be used to terminate the burst cycle early. Refer to Section 9.5.4, “Burst Transfer” and
Section 9.5.5, “Burst Mechanism” for more information. Refer to Section 10.9.3, “Memory Controller
Base Registers (BR0–BR3)” for memory controller BDIP options.
9.5.9
Termination Signals
The EBI uses three termination signals:
• Transfer acknowledge (TA)
• Burst inhibit (BI)
• Transfer error acknowledge (TEA)
9.5.9.1
Transfer Acknowledge
Transfer acknowledge (TA) indicates normal completion of the bus transfer. During a burst cycle, the slave
asserts this signal with every data beat returned or accepted.
9.5.9.2
Burst Inhibit
A slave sends the BI signal to the master to indicate that the addressed device does not have burst
capability. If this signal is asserted, the master must transfer in multiple cycles and increment the address
for the slave to complete the burst transfer. For a system that does not use the burst mode at all, this signal
can be tied low permanently. Refer to Section 10.9.3, “Memory Controller Base Registers (BR0–BR3)”
for BI options.
9.5.9.3
Transfer Error Acknowledge
The TEA signal terminates a bus cycle under one or more bus error conditions. The current bus cycle must
be aborted. This signal overrides any other cycle termination signals, such as transfer acknowledge.
9.5.9.4
Termination Signals Protocol
The transfer protocol was defined to avoid electrical contention on lines that can be driven by various
sources. To this end, a slave must not drive signals associated with the data transfer until the address phase
is completed and it recognizes the address as its own. The slave must disconnect from signals immediately
after it has acknowledged the cycle and no later than the termination of the next address phase cycle. This
means that the termination signals must be connected to power through a pull-up resistor to avoid the
situation in which a master samples an undefined value in any of these signals when no real slave is
addressed.
Refer to Figure 9-28 and Figure 9-29.
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External Bus Interface
Slave 1
External Bus
MCU
Acknowledge
Signals
TA
TEA
Slave 2
Figure 9-28. Termination Signals Protocol Basic Connection
CLKOUT
ADDR[8:31]
Slave 1
Slave 2
RD/WR
TSIZ[0:1]
TS
Data
TA, BI, TEA
Slave 1
allowed to drive
acknowledge signals
Slave 1
negates acknowledge
signals and turns off
Slave 2
allowed to drive
acknowledge signals
Slave 2
negates acknowledge
signals and turns off
Figure 9-29. Termination Signals Protocol Timing Diagram
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External Bus Interface
9.5.10
Storage Reservation
Reservation occurs when a master loads data from memory. The memory location must not be overwritten
until the master finishes processing the data and writing the results back to the reserved location. The
MPC561/MPC563 storage reservation protocol supports a multi-level bus structure. For each local bus,
storage reservation is handled by the local reservation logic.
The protocol tries to optimize reservation cancellation such that an MPC500 processor is notified of
storage reservation loss on a remote bus only when it has issued a conditional storeword (stwcx) cycle to
that address. That is, the reservation loss indication comes as part of the stwcx cycle. This method avoids
the need to have very fast storage reservation loss indication signals routed from every remote bus to every
MPC500 master.
The storage reservation protocol makes the following assumptions:
• Each processor has, at most, one reservation flag
• lwarx sets the reservation flag
• lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and
again sets the reservation flag
• stwcx by the same processor clears the reservation flag
• Store by the same processor does not clear the reservation flag
• Some other processor (or other mechanism) store to the same address as an existing reservation
clears the reservation flag
• In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
The reservation protocol for a single-level (local) bus is illustrated in Figure 9-30. The protocol assumes
that an external logic on the bus carries out the following functions:
• Snoops accesses to all local bus slaves
• Holds one reservation for each local master capable of storage reservations
• Sets the reservation when that master issues a load and reserve request
• Clears the reservation when some other master issues a store to the reservation address
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External Bus Interface
MPC500 Device
External Bus
External Bus
Interface
Bus
Master
lwarx
S
Q
R
Enable
external stwcx access
AT[0:3], RSV, R/W, TS
ADDR[0:29]
CR
Reservation
Logic
CR
CLKOUT
Figure 9-30. Reservation on Local Bus
The MPC561/MPC563 samples the CR line at the rising edge of CLKOUT. When this signal is asserted,
the reservation flag is reset (negated).
The external bus interface (EBI) samples the logical value of the reservation flag prior to externally
starting a bus cycle initiated by the RCPU stwcx instruction. If the reservation flag is set, the EBI begins
with the bus cycle. If the reservation flag is reset, no bus cycle is initiated externally, and this situation is
reported to the RCPU.
The reservation protocol for a multi-level (local) bus is illustrated in Figure 9-31. The system describes the
situation in which the reserved location is sited in the remote bus.
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External Bus Interface
External Bus (Local Bus)
External Bus
Interface
AT[0:3], RSV, R/W, TS
MPC500 Device
ADDR[0:29]
Local Master Accesses with
lwarx to Remove Bus Address
KR
Q
Bus
Interface
S
R
A Master in the Remote Bus Write
to the Reserved Location
Remote Bus
Figure 9-31. Reservation on Multi-level Bus Hierarchy
In this case, the bus interface block implements a reservation flag for the local bus master. The reservation
flag is set by the bus interface when a load with reservation is issued by the local bus master and the
reservation address is located on the remote bus. The flag is reset (negated) when an alternative master on
the remote bus accesses the same location in a write cycle. If the MPC561/MPC563 begins a memory cycle
to the previously reserved address (located in the remote bus) as a result of an stwcx instruction, the
following two cases can occur:
• If the reservation flag is set, the buses interface acknowledges the cycle in a normal way
• If the reservation flag is reset, the bus interface should assert the KR. However, the bus interface
should not perform the remote bus write-access or abort it if the remote bus supports aborted
cycles. In this case the failure of the stwcx instruction is reported to the RCPU.
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External Bus Interface
9.5.11
Bus Exception Control Cycles
The MPC561/MPC563 bus architecture requires assertion of TA from an external device to signal that the
bus cycle is complete. TA is not asserted in the following cases:
• The external device does not respond
• Various other application-dependent errors occur
External circuitry can provide TEA when no device responds by asserting TA within an appropriate period
of time after the MPC561/MPC563 initiates the bus cycle (it can be the internal bus monitor). This allows
the cycle to terminate and the processor to enter exception-processing for the error condition (each one of
the internal masters causes an internal interrupt under this situation). To properly control termination of a
bus cycle for a bus error, TEA must be asserted at the same time or before TA is asserted. TEA should be
negated before the second rising edge after it was sampled as asserted to avoid the detection of an error for
the next initiated bus cycle. TEA is an open drain pin that allows the “wired-or” of any different sources
of error generation.
9.5.11.1
Retrying a Bus Cycle
When an external device asserts the RETRY signal during a bus cycle, the MPC561/MPC563 enters a
sequence in which it terminates the current transaction, relinquishes the ownership of the bus, and retries
the cycle using the same address, address attributes, and data (in the case of a write cycle).
Figure 9-32 illustrates the behavior of the MPC561/MPC563 when the RETRY signal is detected as a
termination of a transfer. As seen in this figure, in the case when the internal arbiter is enabled, the
MPC561/MPC563 negates BB and asserts BG in the clock cycle following the retry detection. This allows
any external master to gain bus ownership. In the next clock cycle, a normal arbitration procedure occurs
again. As shown in the figure, the external master did not use the bus, so the MPC561/MPC563 initiates a
new transfer with the same address and attributes as before.
In Figure 9-33, the same situation is shown except that the MPC561/MPC563 is working with an external
arbiter. In this case, in the clock cycle after the RETRY signal is detected asserted, BR is negated together
with BB. One clock cycle later, the normal arbitration procedure occurs again.
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External Bus Interface
CLKOUT
BR
BG (output)
BB
ADDR[8:31]
Allow External
Master to Gain the Bus
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
O
Figure 9-32. Retry Transfer Timing – Internal Arbiter
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External Bus Interface
CLKOUT
BR (output)
BG
Allow External
Master to Gain the Bus
BB
ADDR[8:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
O
Figure 9-33. Retry Transfer Timing – External Arbiter
When the MPC561/MPC563 initiates a burst access, the bus interface recognizes the RETRY assertion as
a retry termination only if it detects it before the first data beat was acknowledged by the slave device.
When the RETRY signal is asserted as a termination signal on any data beat of the access after the first
(being the first data beat acknowledged by a normal TA assertion), the MPC561/MPC563 recognizes
RETRY as a transfer error acknowledge.
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External Bus Interface
CLKOUT
BR
BG (output)
Allow External Master
to Gain the Bus
BB
ADDR[8:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
BI
RETRY
O
If Asserted Will
Cause Transfer Error
Figure 9-34. Retry on Burst Cycle
If a burst access is acknowledged on its first beat with a normal TA but with the BI signal asserted, the
following single-beat transfers initiated by the MPC561/MPC563 to complete the 16-byte transfer
recognizes the RETRY signal assertion as a transfer error acknowledge.
In the case in which a small port size causes the MPC561/MPC563 to break a bus transaction into several
small transactions, terminating any transaction with RETRY causes a transfer error acknowledge. See
Section 9.5.2.3, “Single Beat Flow with Small Port Size.”
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External Bus Interface
9.5.11.2
Termination Signals Protocol Summary
Table 9-9 summarizes how the MPC561/MPC563 recognizes the termination signals provided by the slave
device that is addressed by the initiated transfer.
Table 9-9. Termination Signals Protocol
9.5.12
TEA
TA
RETRY
Action
Asserted
X
X
Transfer error termination
Negated
Asserted
X
Normal transfer termination
Negated
Negated
Asserted
Retry transfer termination
Bus Operation in External Master Modes
When an external master takes ownership of the external bus and the MPC561/MPC563 is programmed
for external master mode operation, the external master can access the internal space of the
MPC561/MPC563 (see Section 6.1.2, “External Master Modes”). In external master mode, the external
master owns the bus, and the direction of most of the bus signals is inverted, relative to its direction when
the MPC561/MPC563 owns the bus.
The external master gets ownership of the bus and asserts TS in order to initiate an external master access.
The access is directed to the internal bus only if the input address matches the internal address space. The
access is terminated with one of the followings outputs: TA, TEA, or RETRY. If the access completes
successfully, the MPC561/MPC563 asserts TA, and the external master can proceed with another external
master access or relinquish the bus. If an address or data error is detected internally, the MPC561/MPC563
asserts TEA for one clock. TEA should be negated before the second rising edge after it is sampled asserted
in order to avoid the detection of an error for the next bus cycle initiated. TEA is an open drain pin, and
the negation timing depends on the attached pull-up. The MPC561/MPC563 asserts the RETRY signal for
one clock in order to retry the external master access.
If the address of the external access does not match the internal memory space, the internal memory
controller can provide the chip-select and control signals for accesses that belong to one of the memory
controller regions. This feature is explained in Chapter 10, “Memory Controller.”
Figure 9-35 and Figure 9-36 illustrate the basic flow of read and write external master accesses.
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External Bus Interface
External Master
MPC500 Device
1. Request Bus (BR)
2. Receives Bus Grant (BG) From Arbiter
3. Asserts Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
1. Receives Address
Address in Internal
Memory Map
No
Yes
1. Returns Data
Memory
Controller
Asserts CSx
If In Range
1. Asserts Transfer Acknowledge (TA)
1. Receives Data
Figure 9-35. Basic Flow of an External Master Read Access
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External Bus Interface
External Master
MPC500 Device
1. Request Bus (BR)
2. Receives Bus Grant (BG) From Arbiter
3. Asserts Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
1. Receives Address
1. Drives Data
Address in Internal
Memory Map
No
Yes
Memory
Controller
Asserts CSx
If In Range
1. Receives Data
1. Asserts Transfer Acknowledge (TA)
Figure 9-36. Basic Flow of an External Master Write Access
Figure 9-37, Figure 9-38, and Figure 9-39 describe read and write cycles from an external master
accessing internal space in the MPC561/MPC563.
NOTE
The minimum number of wait states for such access is two clocks. The
accesses in these figures are valid for both peripheral mode and slave mode.
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External Bus Interface
CLKOUT
BR (input)
Use the Internal Arbiter
Receive Bus Grant and Bus Busy Negated
BG
O
O
Assert BB, Drive Address and Assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output)
Minimum 2 Wait States
O
Data is valid
Figure 9-37. Peripheral Mode: External Master Reads from MPC561/MPC563 (Two Wait States)
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External Bus Interface
CLKOUT
BR (input)
Use the Internal Arbiter
BG
Receive Bus Grant and Bus Busy Negated
O
O
Assert BB, Drive Address and Assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output)
O
Minimum 2 Wait States
Data is sampled
Figure 9-38. Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States)
9.5.13
Contention Resolution on External Bus
When the MPC561/MPC563 is in slave mode, external master access to the MPC561/MPC563 internal
bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to
be executed. The RETRY signal functions as an output that signals the external master to release the bus
ownership and retry the access after one clock.
Figure 9-39 describes the flow of an external master retried access. Figure 9-40 shows the timing when an
external access is retried and a pending internal-to-external access follows.
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External Bus Interface
External Master
MPC500 Device
1. Request Bus (BR)
2. Receives Bus Grant (BG) from Arbiter
3. Asserts Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
1. Assert Retry
1. Release Bus Request (BR) for One Clock and Request Bus (BR) Again
2. Wait Until Bus Busy Negated (No Other Master is Driving)
3. Assert Bus Busy (BB)
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
1. Receives Address
No
Address in Internal
Memory Map
Yes
Memory
Controller
Asserts CSx
If In Range
1. Returns Data
1. Asserts Transfer Acknowledge (TA)
1. Receives Data
Figure 9-39. Flow of Retry of External Master Read Access
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External Bus Interface
CLKOUT
BR
BG (output)
Allow Internal
Access to Gain the
Bus
BB
ADDR[8:31]
ADDR (external)
ADDR (internal)
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (output)
O
Note: the delay for the internal to external cycle may be one clock or greater.
Figure 9-40. Retry of External Master Access (Internal Arbiter)
9.5.14
Show Cycle Transactions
Show cycles are representations of RCPU accesses to internal devices of the MPC561/MPC563. These
accesses are driven externally for emulation, visibility, and debugging purposes. A show cycle can have
one address phase and one data phase, or just an address phase in the case of instruction show cycles. The
cycle can be a write or a read access. The data for both the read and write accesses should be driven by the
bus master. (This is different from normal bus read and write accesses.) The address and data of the show
cycle must each be valid on the bus for one clock. The data phase must not require a transfer acknowledge
to terminate the bus show cycle.
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External Bus Interface
Show cycles are activated by properly setting the SIUMCR register bits. Refer to Section 6.2.2.1.1, “SIU
Module Configuration Register (SIUMCR).” Construction visibility is controlled by the ISCT_SER bits
in the ICTRL register. Refer to Table 23-26. Data visibility is controlled by the LSHOW bits of the
L2U_MCR register. Refer to Table 11-7.
In a burst show cycle only the first data beat is shown externally. Refer to Table 9-8 for show cycle
transaction encodings.
Instruction show cycle bus transactions have the following characteristics (see Figure 9-41):
• One clock cycle
• Address phase only; in decompression on mode part of the compressed address is driven on data
lines together with address lines. The external bus interface adds one clock delay between a read
cycle and such show cycle.
• STS assertion only (no TA assertion)
The compressed address is driven on the external bus in the following manner:
• ADDR[0:29] = the word base address;
• DATA[0] = operating mode:
— 0 = decompression off mode;
— 1 = decompression on mode;
• DATA[1:4] = bit pointer
See Chapter 4, “Burst Buffer Controller 2 Module” and Appendix A, “MPC562/MPC564 Compression
Features” for more details about decompression mode.
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External Bus Interface
I
CLKOUT
PTR
BB
ADDR[8:31]
ADDR2
ADDR1
RD/WR
TSIZ[0:1]
BURST
TS
STS
Data
(three-state)
TA
“Compressed” address on data lines
“Normal” Non-Show Cycle Bus Transaction
Instruction Show Cycle Bus Transaction
Figure 9-41. Instruction Show Cycle Transaction
Both read and write data show cycles have the following characteristics: (see Figure 9-42)
• Two clock cycle duration
• Address valid for two clock cycles
• Data is valid only in the second clock cycle
• STS signal only is asserted (no TA or TS)
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External Bus Interface
CLKOUT
BR (in)
BG (out)
BB
ADDR[8:31]
ADDR1
ADDR2
RD/WR
TSIZ[0:1]
BURST
TS
STS
Data
DATA1
DATA2
TA
Read Data Show Cycle Bus Transaction
Write Data Show Cycle Bus Transaction
Figure 9-42. Data Show Cycle Transaction
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Chapter 10
Memory Controller
The memory controller generates interface signals to support a glueless interface to external memory and
peripheral devices. It supports four regions, each with its own programmed attributes. The four regions are
controlled by four chip-select signals. Read and write strobes are also provided.
The memory controller operates in parallel with the external bus interface to support external cycles. When
an access to one of the memory regions is initiated, the memory controller takes ownership of the external
signals and controls the access until its termination. Refer to Figure 10-1.
ADDR[0:31]
EBI Bus
External Bus
Interface
DATA[0:31]
Control Bus
Internal Bus
U-bus
Interface
WE[0:3]/BE[0:3]
Memory Controller
Bus
Memory
Controller
OE
CS[0:3]
Figure 10-1. Memory Controller Function within the USIU
10.1
Overview
The memory controller provides a glueless interface to external EPROM, static RAM (SRAM), Flash
(EEPROM), and other peripherals. The general-purpose chip-selects are available on lines CS0 through
CS3. CS0 also functions as the global (boot) chip-select for accessing the boot Flash EEPROM. The chip
select allows zero to 30 wait states.
Figure 10-2 is a block diagram of the MPC561/MPC563 memory controller.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-1
Memory Controller
Internal Addresses [0:16], AT[0:2]
Base
Register
Option
Register
0 (BR0)
1 (BR1)
2 (BR2)
Base Register 3 (BR3)
Dual Mapping
Base Register (DMBR)
0 (OR0)
1 (OR1)
2 (OR2)
Option Register 3 (OR3)
Dual Mapping
Option Register (DMOR)
Region Match Logic
Attributes
CS[0:3]
Expired
Wait State
Counter
Load
General-Purpose WE/BE[0:3]
Chip-Select
Machine
OE
(GPCM)
Figure 10-2. Memory Controller Block Diagram
Most memory controller features are common to all four banks. (For features unique to the CS0 bank, refer
to Section 10.7, “Global (Boot) Chip-Select Operation.”) A full 32-bit address decode for each memory
bank is possible with 17 bits having address masking. The full 32-bit decode is available, even if all 32
address bits are not MPC561/MPC563 signals connected to the external device.
Each memory bank includes a variable block size of 32 Kbytes, 64 Kbytes and up to four Gbytes. Each
memory bank can be selected for read-only or read/write operation. The access to a memory bank can be
restricted to certain address type codes for system protection. The address type comparison occurs with a
mask option as well.
From 0 to 30 wait states can be programmed with TA generation. Four write-enable and byte-enable
signals (WE/BE[0:3]) are available for each byte that is written to memory. An output enable (OE) signal
is provided to eliminate external glue logic. A memory transfer start (MTS) strobe permits one master on
a bus to access external memory through the chip selects on another.
The memory controller functionality allows MPC561/MPC563-based systems to be built with little or no
glue logic. A minimal system using no glue logic is shown in Figure 10-3. In this example CS0 is used for
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Memory Controller
a 16-bit boot EPROM and CS1 is used for a 32-bit SRAM. The WE/BE[0:3] signals are used both to
program the EPROM and to enable write access to various bytes in the RAM.
Address
Address
CS0
CE
OE
OE
WE/BE[0:1]
Data
[0:15]
DATA[0:15]
EPROM
MPC500
Address
CS1
CE
WE/BE[0:3]
WE/BE[0:3]
[0:31]
Data
OE
SRAM
Figure 10-3. MPC561/MPC563 Simple System Configuration
10.2
Memory Controller Architecture
The memory controller consists of a basic machine that handles the memory access cycle: the
general-purpose chip-select machine (GPCM).
When any of the internal masters request a new access to external memory, the address of the transfer (with
17 bits having a mask) and the address type (with three bits having a mask) are compared to each one of
the valid banks defined in the memory controller. Refer to Figure 10-4.
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10-3
Memory Controller
.............
Address Mask
RBA15
RBA4
RBA3
RBA2
RBA1
RBA0
Base Address
M0 M1 M2 M3 M4 M5 M6 M7 . . . . M16
M[0:16]
A[0:16]
cmp cmp cmp cmp cmpcmpcmp cmp cmp cmp cmp
Match
Figure 10-4. Bank Base Address and Match Structure
When a match is found on one of the memory banks, its attributes are selected for the functional operation
of the external memory access:
• Read-only or read/write operations
• Number of wait states for a single memory access, and for any beat in a burst access
• Burst-inhibit indication. Internal burst requests are still possible during burst-inhibited cycles; the
memory controller emulates the burst cycles
• Port size of the external device
Note that if more than one region matches the internal address supplied, then the lowest numbered region
is selected to provide the attributes and the chip select. If the dual mapping region is matched, it has the
highest priority (refer to Section 10.5, “Dual Mapping of the Internal Flash EEPROM Array”).
10.2.1
Associated Registers
Status bits for each memory bank are found in the memory control status register (MSTAT). The MSTAT
reports write-protect violations for all the banks.
Each of the four memory banks has a base register (BR) and an option register (OR). The BRx and ORx
registers contain the attributes specific to memory bank x. The base register contains a valid bit (V) that
indicates the register information for that particular chip select is valid.
10.2.2
Port Size Configuration
The memory controller supports dynamic bus sizing. Defined 8-bit ports can be accessed as odd or even
bytes. Defined 16-bit ports, when connected to data bus lines zero to 15, can be accessed as odd bytes, even
bytes, or even half-words. Defined 32-bit ports can be accessed as odd bytes, even bytes, odd half-words,
even half-words, or words on word boundaries. The port size is specified by the PS bits in the base register.
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Freescale Semiconductor
Memory Controller
10.2.3
Write-Protect Configuration
The WP bit in each base register can restrict write access to its range of addresses. Any attempt to write
this area results in the associated WPER bit being set in the MSTAT.
If an attempt to access an external device results in a write-protect violation, the memory controller
considers the access to be no match. No chip-select line is asserted externally, and the memory controller
does not terminate the cycle. The external bus interface generates a normal cycle on the external bus. Since
the memory controller does not acknowledge the cycle internally, the cycle may be terminated by external
logic asserting TA or by the on-chip bus monitor asserting TEA.
10.2.4
Address and Address Space Checking
The base address is written to the BRx. The address mask bits for the address are written to the OR. The
address type access value, if desired, is written to the AT bits in the BRx. The ATM bits in the ORx can be
used to mask this value. If address type checking is not desired, program the ATM bits to zero.
Each time an external bus cycle access is requested, the address and address type are compared with each
one of the banks. If a match is found, the attributes defined for this bank in its BRx and ORx are used to
control the memory access. If a match is found in more than one bank, the lowest bank matched handles
the memory access (e.g., bank zero is selected over bank one).
NOTE
When an external master accesses a slave on the bus, the internal AT[0:2]
lines reaching the memory controller are forced to 100.
10.2.5
Burst Support
The memory controller supports burst accesses of external burstable memory. To enable bursts, clear the
burst inhibit (BI) bit in the appropriate base register. Burst support is for read only.
Bursts can be four or eight beats depending on the value of the BURST_EN bit in the SIUMCR register
and the BL bit in the BRx register. That is, the memory controller executes up to eight one-word accesses,
but when a modulo eight limit is reached, the burst is terminated (even if fewer than eight words have been
accessed).
When the SIU initiates a burst access, if no match is found in any of the memory controller’s regions then
a burst access is initiated to the external bus. The termination of each beat for this access is externally
controlled.
To support different types of memory devices, the memory controller supports two types of timing for the
BDIP signal: normal and late.
NOTE
The BDIP signal itself is controlled by the external bus interface logic. Refer
to Figure 9-13 and Figure 9-14 in Chapter 9, “External Bus Interface."
If the memory controller is used to support an external master accessing an external device with bursts, the
BDIP input signal is used to indicate to the memory controller when the burst is terminated.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-5
Memory Controller
For addition details, refer to Section 9.5.4, “Burst Transfer."
10.2.6
Reduced Data Setup Time
In order to meet timing requirements when interfacing to external memories, the data setup time can be
reduced. This mode can be selected by programming the BRx registers. Thus there is flexibility in how
each region can be configured to operate. The operation mode will be determined dynamically according
to a particular access type. This means that for a memory region with the reduced setup time mode enabled,
the mode will automatically switch to disabled when there is no requirement for the reduced setup time,
(e.g., a back-to-back load/store access). For a new access with burst length more than 1, the operation
mode will be automatically switched back to the reduced setup time mode.
Reduced setup time can be selected via the SST bit in BR[0:3]. See Section 10.9.3, “Memory Controller
Base Registers (BR0–BR3)” for more details. If SCCR[EBDF] is greater than 0, however, an external burst
access with reduced data setup time will corrupt a load/store to any USIU register.
The reduced setup time mode may or may not have a performance impact, depending on the properties of
the memory. Namely, there is always an additional empty cycle between two burst sequences. On the other
hand, this additional cycle, under certain conditions, may be compensated for by reducing the number of
cycles in initial data access and sequential burst beats.
Table 10-1. Timing Requirements for Reduced Setup Time
CPU Specification
Memory Device Requirements
Cycle time at 56 MHz = 17.9 ns
Initial access time = 49 ns
Short setup time = 3 ns
Burst access time = 13 ns
Normal setup time = 6 ns
Additional delay arising from on-board wires and clock skew between
internal clock and CLKOUT
10.2.6.1
Case 1: Normal Setup Time
Initial access:
Initial access time of memory + Data setup time of CPU + Delays = 49 + 6 + 1 = 56ns
To derive the number of clocks required, divide by the system clock cycle time:
56
---------- = 3.13
17.9
therefore 4 cycles are required
Burst access:
Burst access time of memory + Data setup time of CPU + Delays = 13 + 6 + 1 = 20ns
The number of clocks required
20
= ---------- = 1.11
17.9
therefore 2 clocks are required.
This case is illustrated in Figure 10-5.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-6
Freescale Semiconductor
Memory Controller
10.2.6.2
Case 2: Short Setup Time
Initial access:
Enabling short setup time requires one clock cycle:
Initial access time of memory + Data setup time of CPU + Delays = 49 + 3 + 1 = 53ns
53
The number of clocks required = ---------- = 2.96 + 1(SST Enable Clock) = 3.96 therefore 4 clocks are
17.9
required.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-7
Memory Controller
Burst access:
Burst access time of memory + Data setup time of CPU + Delays = 13 + 3 + 1 = 17ns
17
17.9
The number of clocks required = ---------- = 0.95 therefore 1 clock is required.
This case is illustrated in Figure 10-6.
10.2.6.3
Summary of Short Setup Time
With normal setup time and a 4-beat burst, a 4-2-2-2 burst cycle is required which is reduced to a 4-1-1-1
burst cycle with a short setup time. Short setup time creates a saving of three clock cycles with a 4-beat
burst and can result in even better performance with an 8-beat burst, saving seven clock cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-8
Freescale Semiconductor
Memory Controller
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0b0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Normal
BDIP
Late
Last Beat
Expects Another Data
No Data
Expected
Data
TA
1
2
3
4
1st Data
Is Valid
5
6
2nd Data
Is Valid
7
8
3rd Data
Is Valid
9
10
4th Data
Is Valid
Figure 10-5. A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-9
Memory Controller
CLKOUT
BR
BG
BB
ADDR
[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
Expects Another Data
NO DATA
EXPECTED
BDIP
Data
TA
1
2
3
4
5
1st Data
is Valid
6
2nd Data
is Valid
7
3rd Data
is Valid
4th Data
is Valid
Figure 10-6. 4 Beat Burst Read with Short Setup Time (Zero Wait State)
NOTE
An extra clock cycle is required to enable short set-up time, resulting in a
4-1-1-1 cycle.
10.3
Chip-Select Timing
The general-purpose chip-select machine (GPCM) allows a glueless and flexible interface between the
MPC561/MPC563 and external SRAM, EPROM, EEPROM, ROM peripherals. When an address and
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Freescale Semiconductor
Memory Controller
address type match the values programmed in the BR and OR for one of the memory controller banks, the
attributes for the memory cycle are taken from the OR and BR registers. These attributes include the
following fields: CSNT, ACS, SCY, BSCY, WP, TRLX, BI, PS, and SETA. Table 10-2 summarizes the
chip-select timing options.
Byte write and read-enable signals (WE/BE[0:3]) are available for each byte that is written to or read from
memory. An output enable (OE) signal is provided to eliminate external glue logic for read cycles. Upon
system reset, a global (boot) chip select is available. (Refer to Section 10.7, “Global (Boot) Chip-Select
Operation” for more information on the global chip select.) This provides a boot ROM chip select before
the system is fully configured.
Table 10-2. Timing Attributes Summary
Timing Attribute
Bits/Fields
Description
Access speed
TRLX
The TRLX (timing relaxed) bit determines strobe timing to be fast or
relaxed.
Intercycle space time
EHTR
The EHTR (extended hold time on read accesses) bit is provided for
devices that have long disconnect times from the data bus on read
accesses. EHTR specifies whether the next cycle is delayed one clock
cycle following a read cycle, to avoid data bus contentions. EHTR
applies to all cycles following a read cycle except for another read cycle
to the same region.
Synchronous or
asynchronous device
ACS, CSNT
The ACS (address-to-chip-select setup) and CSNT (chip-select
negation time) bits cause the timing of the strobes to be the same as the
address bus timing, or cause the strobes to have setup and hold times
relative to the address bus.
Wait states
SCY, BSCY,
SETA, TRLX
From zero to 15 wait states can be programmed for any cycle that the
memory controller generates. The transfer is then terminated internally.
In simplest case, the cycle length equals (2 + SCY) clock cycles, where
SCY represents the programmed number of wait states (cycle length in
clocks). The number of wait states is doubled if the TRLX bit is set (2 +
(SCY x 2)).
When the SETA (external transfer acknowledge) bit is set, TA must be
generated externally, so that external hardware determines the number
of wait states.
NOTE
When a bank is configured for TA to be generated externally (SETA bit is
set) and the TRLX is set, the memory controller requires the external device
to provide at least one wait state before asserting TA to complete the
transfer. In this case, the minimum transfer time is three clock cycles.
The internal TA generation mode is enabled if the SETA bit in the OR register is cleared. However, if the
TA signal is asserted externally at least two clock cycles before the wait states counter has expired, this
assertion terminates the memory cycle. When SETA is cleared, it is forbidden to assert external TA less
than two clocks before the wait states counter expires.
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Freescale Semiconductor
10-11
Memory Controller
10.3.1
Memory Devices Interface Example
Figure 10-7 describes the basic connection between the MPC561/MPC563 and a static memory device. In
this case CSx is connected directly to the chip enable (CE) of the memory device. The WE/BE[0:3] lines
are connected to the respective WE in the memory device where each WE/BE line corresponds to a
different data byte.
MPC5xx
Memory
Address
Address
CSx
CE
OE
OE
WE/BE
WE
Data
Data
Figure 10-7. GPCM–Memory Devices Interface
In Figure 10-8, the CSx timing is the same as that of the address lines output. The strobes for the
transaction are supplied by the OE and the WE/BE lines (if programmed as WE/BE). When the ACS bits
in the corresponding ORx register = 00, CS is asserted at the same time that the address lines are valid.
NOTE
If CSNT is set, the WE signal is negated a quarter of a clock earlier than
normal.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-12
Freescale Semiconductor
Memory Controller
Clock
Address
TS
CSNT = 1, ACS = 00
TA
CS
WE/BE
OE
Data
Note: In this and subsequent timing diagrams in this section, the data bus refers to a read cycle. In a write cycle, the data
immediately follows TS.
Figure 10-8. Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)
10.3.2
Peripheral Devices Interface Example
Figure 10-9 illustrates the basic connection between the MPC561/MPC563 and an external peripheral
device. In this case CSx is connected directly to the chip enable (CE) of the memory device and the R/W
line is connected to the R/W in the peripheral device. The CSx line is the strobe output for the memory
access.
Peripheral
MPC5xx
Address
CSx
RD/WR
Data
Address
CE
RD/WR
Data
Figure 10-9. Peripheral Devices Interface
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-13
Memory Controller
The CSx timing is defined by the setup time required between the address lines and the CE line. The
memory controller allows specification of the CS timing to meet the setup time required by the peripheral
device. This is accomplished through the ACS field in the base register. In Figure 10-10, the ACS bits are
set to 0b11, so CSx is asserted half a clock cycle after the address lines are valid.
CLOCK
ACS = 11
Address
CSNT = 1
TS
TA
CS
RD/WR
Data
Figure 10-10. Peripheral Devices Basic Timing (ACS = 11, TRLX = 0)
10.3.3
Relaxed Timing Examples
The TRLX field is provided for memory systems that need a more relaxed timing between signals. When
TRLX is set and ACS = 0b00, the memory controller inserts an additional cycle between address and
strobes (CS line and WE/OE).
When TRLX and CSNT are both set in a write to memory, the strobe lines (WE/BE[0:3] and CS, if ACS
= 0b00) are negated one clock earlier than in the regular case.
NOTE
In the case of a bank selected to work with external transfer acknowledge
(SETA = 1) and TRLX = 1, the memory controller does not support external
devices that provide TA to complete the transfer with zero wait states. The
minimum access duration in this case equals three clock cycles.
Figure 10-11 shows a read access with relaxed timing. Note the following:
• Strobes (OE and CS) assertion time is delayed one clock relative to address (TRLX bit set effect).
• Strobe (CS) is further delayed (half-clock) relative to address due to ACS field being set to 11.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-14
Freescale Semiconductor
Memory Controller
•
Total cycle length = 5, is determined as follows:
— Two clocks for basic cycle
— SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being set (2 + (SCY
x 2)).
— Extra clock is added due to TRLX effect on the strobes.
CLOCK
Address
TS
ACS = ‘00’ & TRLX = ‘1’
ACS = ‘11’ & TRLX = ‘1’
TA
CS
RD/WR
WEBS = ‘1’,Line Acts as BE
in Read.
WE/BE
OE
Data
Figure 10-11. Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1)
Figure 10-12 through Figure 10-14 are examples of write accesses using relaxed timing. In Figure 10-12,
note the following points:
• Because TRLX is set, assertion of the CS and WE strobes is delayed by one clock cycle.
• CS assertion is delayed an additional one quarter clock cycle because ACS = 10.
• The total cycle length = three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— An extra clock cycle is required due to the effect of TRLX on the strobes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-15
Memory Controller
CLOCK
Address
TS
TA
ACS = 10
ACS = 00
CS
RD/WR
WE/BE
OE
Data
Figure 10-12. Relaxed Timing — Write Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1)
In Figure 10-13, note the following:
• Because the TRLX bit is set, the assertion of the CS and WE strobes is delayed by one clock cycle.
• Because ACS = 11, the assertion of CS is delayed an additional half clock cycle.
• Because CSNT = 1, WE is negated one clock cycle earlier than normal. (Refer to Figure 10-8.) The
total cycle length is four clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— Two extra clock cycles are required due to the effect of TRLX on the assertion and negation of
the CS and WE strobes.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-16
Freescale Semiconductor
Memory Controller
Clock
Address
TS
ACS =11
ACS=00 & CSNT = 1
TA
CS
RD/WR
WE/BE
OE
CSNT = 1
Data
Figure 10-13. Relaxed Timing — Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1)
In Figure 10-14, notice the following:
• Because ACS = 0, TRLX being set does not delay the assertion of the CS and WE strobes.
• Because CSNT = 1, WE/BE is negated one clock cycle earlier than normal. (Refer to Figure 10-8).
• CS is not negated one clock cycle earlier, since ACS = 00.
• The total cycle length is three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— One extra clock cycle is required due to the effect of TRLX on the negation of the WE/BE
strobes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-17
Memory Controller
Clock
Address
TS
No Effect, ACS = 00
TA
CS
RD/WR
WE/BE
OE
CSNT = 1
Data
Figure 10-14. Relaxed Timing — Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1
10.3.4
Extended Hold Time on Read Accesses
For devices that require a long disconnection time from the data bus on read accesses, the bit EHTR in the
corresponding OR register can be set. In this case any MPC561/MPC563 access to the external bus
following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access
to the same bank. Figure 10-15 through Figure 10-18 show the effect of the EHTR bit on memory
controller timing.
Figure 10-15 shows a write access following a read access. Because EHTR = 0, no extra clock cycle is
inserted between memory cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-18
Freescale Semiconductor
Memory Controller
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Figure 10-15. Consecutive Accesses (Write After Read, EHTR = 0)
Figure 10-16 shows a write access following a read access when EHTR = 1. An extra clock is inserted
between the cycles. For a write cycle following a read, this is true regardless of whether both accesses are
to the same region.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-19
Memory Controller
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Extra Clock Before Next Cycle Starts.
Long Tdt Allowed
Figure 10-16. Consecutive Accesses (Write After Read, EHTR = 1)
Figure 10-17 shows consecutive accesses from different banks. Because EHTR = 1 (and the accesses are
to different banks), an extra clock cycle is inserted.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-20
Freescale Semiconductor
Memory Controller
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Extra Clock Before Next Cycle Starts
Long Tdt Allowed
Figure 10-17. Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1)
Figure 10-18 shows two consecutive read cycles from the same bank. Even though
EHTR = 1, no extra clock cycle is inserted between the memory cycles. (In the case of two consecutive
read cycles to the same region, data contention is not a concern.)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-21
Memory Controller
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Figure 10-18. Consecutive Accesses (Read After Read from Same Bank, EHTR = 1)
10.3.5
Summary of GPCM Timing Options
Table 10-3 summarizes the different combinations of timing options.
Table 10-3. Programming Rules for Timing Strobes
WE/BE
Address to
OE
CS
Negated to WE/BE or Negated to Negated to
Add/Data
Add/Data
Add/Data
OE
Asserted
Invalid
Invalid
Invalid
Total
Number of
Cycles
TRLX
Access
Type
ACS
CSNT
Address
to CS
Asserted
0
read
00
X
0
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
read
10
X
1/4 * clock
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
read
11
X
1/2 * clock
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
write
00
0
0
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
10
0
1/4 * clock
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
11
0
1/2 * clock
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
00
1
0
1/4 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
0
write
10
1
1/4 * clock
1/2 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
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10-22
Freescale Semiconductor
Memory Controller
Table 10-3. Programming Rules for Timing Strobes (continued)
CSNT
Address
to CS
Asserted
Address to
WE/BE
OE
CS
Negated to WE/BE or Negated to Negated to
Add/Data
OE
Add/Data
Add/Data
Invalid
Asserted
Invalid
Invalid
11
1
1/2 * clock
1/2 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
read
00
X
0
1/4 * clock
3/4 clock
X
1/4 * clock
2+
2 * SCY
1
read
10
X
(1 + 1/4) *
clock
1/4 * clock
(1 + 3/4) *
clock
X
1/4 * clock
3+
2 * SCY
1
read
11
X
(1 + 1/2) *
clock
1/4 * clock
(1 + 3/4) *
clock
X
1/4 * clock
3+
2 * SCY
1
write
00
0
0
1/4 * clock
3/4 clock
1/4 * clock
X
2+
2 * SCY
1
write
10
0
(1 + 1/4) *
clock
1/4 * clock
(1 + 3/4) *
clock
1/4 * clock
X
3+
2 * SCY
1
write
11
0
(1 + 1/2) *
clock
1/4 * clock
(1 + 3/4)
clock
1/4 * clock
X
3+
2 * SCY
1
write
00
1
0
1/4 * clock
3/4 clock
(1 + 1/2) *
clock
X
3+
2 * SCY
1
write
10
1
(1 + 1/4) *
clock
(1 + 1/2) *
clock
(1 + 3/4)
clock
(1 + 1/2) *
clock
X
4+
2 * SCY
1
write
11
1
(1 + 1/2) *
clock
(1 + 1/2) *
clock
(1 + 3/4)
clock
(1 + 1/2) *
clock
X
4+
2 * SCY
TRLX
Access
Type
ACS
0
write
1
Total
Number of
Cycles
Note: Timing in this table refers to the typical timing only. Consult the electrical characteristics for exact worst-case timing values.
1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock.
Additional timing rules not covered in Table 10-3 include the following:
• If SETA = 1, an external TA signal is required to terminate the cycle.
• If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if SCY = 0000)
• If TRLX = 1, the number of wait states = 2 ∗ SCY & 2 ∗ BSCY
• ACS = 01 is not defined (reserved).
• If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a following read cycle
to another region, or between a read cycle and a following write cycle to any region.
• If LBDIP = 1 (late BDIP assertion), the BDIP signal is asserted only after the number of wait states
for the first beat in a burst have elapsed. See Figure 9-13 in Chapter 9, “External Bus Interface,”
as well as Section 9.5.5, “Burst Mechanism.”
NOTE
The LBDIP/TBDIP function can operate only when the cycle termination is
internal, using the number of wait states programmed in one of the ORx
registers. The LBDIP/TBDIP function cannot be activated at the same
time—results are unknown.
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Freescale Semiconductor
10-23
Memory Controller
10.4
Write and Byte Enable Signals
The GPCM determines the timing and value of the WE/BE signals if allowed by the port size of the
accessed bank, the transfer size of the transaction and the address accessed.
The functionality of the WE/BE[0:3] signals depends upon the value of the write enable/byte select
(WEBS) bit in the corresponding BR register. Setting WEBS to 1 will enable these signals as BE, while
clearing it to zero will enable them as WE. WE is asserted only during write access, while BE is asserted
for both read and write accesses. The timing of the WE/BE signals remains the same in either case, and is
determined by the TRLX, ACS and CSNT bits.
The upper WE/BE (WE0/BE0) indicates that the upper eight bits of the data bus (D0–D7) contains valid
data during a write/read cycle. The upper-middle write byte enable (WE1/BE1) indicates that the
upper-middle eight bits of the data bus (D8–D15) contains valid data during a write/read cycle. The
lower-middle write byte enable (WE2/BE2) indicates that the lower-middle eight bits of the data bus
(D16–D23) contains valid data during a write/read cycle. The lower write/read enable (WE3/BE3)
indicates that the lower eight bits of the data bus contains valid data during a write cycle.
The write/byte enable lines affected in a transaction for 32-bit port (PS = 00), a 16-bit port (PS = 10) and
a 8-bit port (PS = 01) are shown in Table 10-4.
Table 10-4. Write Enable/Byte Enable Signals Function1
Address
Transfer
Size
TSIZ
A30 A31
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
HalfWord
1
0
0
0
1
0
1
0
Word
0
0
0
0
32-bit Port Size
16-bit Port Size
WE0/ WE1/ WE2 WE3/ WE0/ WE1/ WE2/
BE0 BE1 BE2 BE3 BE0 BE1 BE2
X
X
X
8-bit Port Size
WE3/
BE3
WE0
WE
WE1
WE3/
2
/
/BE1
BE3
BE2
BE0
X
X
X
Byte
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
This table shows which write enables are asserted (indicated with an ‘X’) for different combinations of port size and
transfer size.
10.5
Dual Mapping of the Internal Flash EEPROM Array
The internal Flash EEPROM (UC3F) module can be mapped to an external memory region controlled by
the memory controller. Only one region can be programmed to be dual-mapped. When dual mapping is
enabled (DME bit is set in the DMBR register) and when an internal address matches the dual-mapped
address range (as programmed in the DMBR) with the cycle type matching the AT/ATM field in
DMBR/DMOR registers, the following occurs:
• The internal Flash memory does not respond to that address
• The memory controller takes control of the external access
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Memory Controller
•
•
The attributes for the access are taken from one of the base and option registers of the appropriate
chip select
The chip-select region selected is determined by the CS line select bit field (Section 10.9.5,
“Dual-Mapping Base Register (DMBR)”).
With dual mapping, aliasing of address spaces may occur. This happens when the region is dual-mapped
into a region which is also mapped into one of the four regions available in the memory controller. If code
or data is written to the dual-mapped region, care must be taken to avoid overwriting this code or data by
normal accesses of the chip-select region.
There is a match if:
bus_address[0:16] == {0000000,ISB[0:2],0,BA[1:6]}
Eqn. 10-1
where BA represents the bit field in the DMBR register.
Eqn. 10-2
Care must also be taken to avoid overwriting “normal” CSx data with dual-mapped code or data.
One way to avoid this situation is by disabling the chip-select region and enabling only the dual-mapped
region (DMBR[DME] = 1, but BRx[V] = 0). Figure 10-19 illustrates the phenomenon.
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10-25
Memory Controller
MPC5xx Memory Map
Dual Mapping
Physical External Memory
CSx
Dual-Map region
Flash
External CSx
Figure 10-19. Aliasing Phenomenon Illustration
NOTE
The default state is to allow dual-mapping data accesses only; this means
that dual mapping is possible only for data accesses on the internal bus.
Also, the default state takes the lower 2 Mbytes of the MPC563 internal
Flash memory. Hence, caution should be taken to change the dual-mapping
setup before the first data access. Dual mapping is not supported for an
external master when the memory controller serves the access; in such a
case, the MPC561/MPC563 terminates the cycle by asserting TEA.
10.6
Dual Mapping of an External Flash Region
The dual mapping feature also enables mapping of external memory to alternative memory regions
controlled by the memory controller. When dual mapping is enabled and an external address matches a
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Memory Controller
dual mapped address, and the cycle type matches AT/ATM field in DMBR/DMOR register, then the
following occur:
• The chip-select that is mapped to the access does not respond to that address (it remains negated)
• The chip-select region selected is determined by the DMCS bit field in the DMBR register
• The attributes for the access are taken from the corresponding chip select region
Dual mapping can only be enabled over memory addresses in the range 0x0000 0000 through 0x000F
FFFF.
NOTE
Internal Flash must be disabled to use dual mapping over an external
memory.
10.7
Global (Boot) Chip-Select Operation
Global (boot) chip-select operation allows address decoding for a boot ROM before system initialization.
If the global chip-select feature is enabled then the memory controller is enabled from reset.
The global chip select port size is programmable at system reset using RCW[BPS]. The global chip select
does not provide write protection and responds to all address types, allowing a boot ROM to be located
anywhere in the address space.
The memory controller will operate in this boot mode until the first write to any chip select option register
(ORx).The chip select signal can be programmed to continue decoding a range of addresses after this write,
provided the preferred address range is first loaded into the chip select base register (BRx). After the first
write to ORx, the global chip select can only be restarted with a system reset.
Which chip-select line is used as the global chip select, and how it operates, is determined by the reset
configuration parameters:
• FLEN – Internal Flash enable (bit 20)
• BDIS – Boot disable (bit 3)
• DME – Dual mapping enable (bit 31)
Table 10-6 summarizes global chip select operations for all combinations of values on these reset
configuration word lines.In case 1, where FLEN, BDIS, DME = 0b000 (all cleared) at reset, CS0 is the
global chip-select output. When the RCPU begins accessing memory after system reset, CS0 is asserted
for every address, for accesses to both internal and external instructions and data.
In case 2, where FLEN, BDIS, DME = 0b001 at reset, CS0 is asserted for all external address accesses
(instructions and data) and for internal instruction accesses. However, CS3 is asserted for all internal data
accesses. CS3 is used in this case to allow dual mapping of loads/stores to/from an alternative bank which
is not the memory bank normally used for instructions/data. In this way CS3 can be used to allow
load/store from a different memory bank from reset. DME can then be disabled as required.
The global chip select feature is disabled by driving only the BDIS line of the RCW (FLEN, BDIS,
DME = 0b010). This is shown in case 3 of Table 10-6.
Table 10-5 shows the initial values of the “boot bank” in the memory controller.
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Memory Controller
Table 10-5. Boot Bank Fields Values After Hard Reset
10.8
Field
Value (Binary)
PS
RCW[4:5] BPS
SST
0
BL
0
WP
0
SETA
0
BI
0b1
V
CS0 = ID3
CS3 = ID20 & ID31
AM[0:16]
0 0000 0000 0000 0000
ATM[0:2]
000
CSNT
0
ACS[0:1]
00
EHTR
0
SCY[0:3]
0b1111
BSCY[0:2]
0b011
TRLX
0
Memory Controller External Master Support
The memory controller in the MPC561/MPC563 supports accesses initiated by both internal and external
bus masters to external memories. If the address of any master is mapped within the internal
MPC561/MPC563 address space, the access will be directed to the internal device, and will be ignored by
the memory controller. If the address is not mapped internally, but rather mapped to one of the memory
controller regions, the memory controller will provide the appropriate chip select and strobes as
programmed in the corresponding region (see Section 6.2.2.1.3, “External Master Control Register
(EMCR)”).
The MPC561/MPC563 supports only synchronous external bus masters. This means that the external
master works with CLKOUT and implements the MPC561/MPC563 bus protocol to access a slave device.
A synchronous master initiates a transfer by asserting TS. The ADDR[0:31] signals must be stable from
the rising edge of CLKOUT during which TS is sampled, until the last TA acknowledges the transfer. Since
the external master works synchronously with the MPC561/MPC563, only setup and hold times around
the rising edge of CLKOUT are important. Once the TS is detected/asserted, the memory controller
compares the address with each one of its defined valid banks to find a possible match. But, since the
external address space is shorter than the internal space, the actual address that is used for comparing
against the memory controller regions is in the format of: {00000000, bits [8:16] of the external address}.
In the case where a match is found, the controls to the memory devices are generated and the transfer
acknowledge indication (TA) is supplied to the master.
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Memory Controller
Because it takes two clocks for the external address to be recognized and handled by the memory
controller, the TS which is generated by the external master is ahead of the corresponding CS and strobes
which are asserted by the memory controller. This 2-clock delay might cause problems in some
synchronous memories. To overcome this, the memory controller generates the MTS (memory transfer
start) strobe which can be used in the slave’s memory instead of the external master’s TS signal. As seen
in Figure 10-20, the MTS strobe is synchronized to the assertion of CS by the memory controller so that
the external memory can latch the external master’s address correctly. To activate this feature, the MTSC
bit must be set in the SIUMCR register. Use external logic to control devices that can have burst accesses
from an external master.
On the MPC563, when the external master accesses the internal Flash when it is disabled, the access is
terminated with the transfer error acknowledge (TEA) signal asserted, and the memory controller does not
support this access in any way.
When the memory controller serves an external master, the BDIP signal becomes an input signal. This
signal is watched by the memory controller to detect when the burst is terminated.
Synchronous External Master
TA
TS
BDIP
Data
ADDR
BURST
Memory
MPC5xx
TA
TS
MTS
TS
Address
Address
CSx
CE
OE
OE
WE/BE
W
BDIP
BDIP
Data
Data
BURST
BURST
NOTE: The memory controller’s BDIP line is used as a burst_in_progress signal.
Figure 10-20. Synchronous External Master
Configuration for GPCM-Handled Memory Devices
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Memory Controller
Address
Match
&
Compare
Memory
Device
Access
CLOCK
ADDR[0:31]
RD/WR
BURST
TSIZE
TS
MTS
TA
CS
WE/BE
OE
Data
Figure 10-21. Synchronous External Master Basic Access (GPCM Controlled)
NOTE
Because the MPC561/MPC563 has only 24 address signals, the eight most
significant internal address lines are driven as 0b0000_0000, and so
compared in the memory controller’s regions.
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Memory Controller
10.9
Programming Model
The registers in Table 10-6 are used to control the memory controller.
Table 10-6. Memory Controller Address Map
10.9.1
Address
Register
0x2F C100
Base Register Bank 0 (BR0)
0x2F C104
Option Register Bank 0 (OR0)
0x2F C108
Base Register Bank 1 (BR1)
0x2F C10C
Option Register Bank 1 (OR1)
0x2F C110
Base Register Bank 2 (BR2)
0x2F C114
Option Register Bank 2 (OR2)
0x2F C118
Base Register Bank 3 (BR3)
0x2F C11C
Option Register Bank 3 (OR3)
0x2F C120 — 0x13F
Reserved
0x2F C140
Dual-Mapping Base Register (DMBR)
0x2F C144
Dual-Mapping Option Register (DMOR)
0x2F C148 — 0x2F C174
Reserved
0x2F C178
Memory Status Register (MSTAT)
General Memory Controller Programming Notes
1. In the case of an external master that accesses an internal MPC561/MPC563 module (in slave or
peripheral mode), if that slave device address also matches one of the memory controller’s regions,
the memory controller will not issue any CS for this access, nor will it terminate the cycle. Thus,
this practice should be avoided. Be aware also that any internal slave access prevents memory
controller operation.
2. If the memory controller serves an external master, then it can support accesses to 32-bit port
devices only. This is because the MPC561/MPC563 external bus interface cannot initiate extra
cycles to complete an access to a smaller port-size device as it does not own the external bus.
3. When the SETA bit in the base register is set, then the timing programming for the various strobes
(CS, OE and WE/BE) may become meaningless.
4. When configuring a chip select for a memory region with the intent to access that region
immediately after configuration, then an ISYNC instruction should be executed in order to ensure
that the configuration takes effect before any accesses are initiated.
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10-31
Memory Controller
10.9.2
Memory Controller Status Registers (MSTAT)
,
MSB
0
LSB
1
2
3
Field
4
5
6
7
—
8
9
10
11
12
13
WPER0 WPER1 WPER2 WPER3
HRESET
14
15
—
0000_0000_0000_0000
Addr
0x2F C178
Figure 10-22. Memory Controller Status Register (MSTAT)
Table 10-7. MSTAT Bit Descriptions
Bits
Name
0:7
—
8:11
12:15
10.9.3
Description
Reserved
WPER0 – Write protection error for bank x. This bit is asserted when a write-protect error occurs for the
WPER3 associated memory bank. A bus monitor (responding to TEA assertion) will, if enabled, prompt
the read of this register if TA is not asserted during a write cycle. WPERx is cleared by writing
one to the bit or by performing a system reset. Writing a zero has no effect on WPER.
—
Reserved
Memory Controller Base Registers (BR0–BR3)
,
MSB
0
1
2
3
4
5
6
7
8
Field
9
10
11
12
13
14
15
BA
HRESET(BR0)
Unchanged
HRESET(BR[1:3])
Unchanged
Addr
0x2F C100 (BR0); 0x2F C108 (BR1); 0x2F C110 (BR2); 0x2F C118 (BR3)
LSB
16
BA
HRESET(BR0)
HRESET(BR[1:3])
1
2
17
18
19
AT
Unchanged
20
21
22
23
PS
SST WP
ID[4:5]
00
24
25
—
BL
Undefined
26
27
28
29
WEBS TBDIP LBDIP SETA
0
Undefined
30
31
BI
V
1
ID3
X2
Unchanged
The reset value is determined by the value on the internal data bus during reset (reset-configuration word).
See Table 10-9 for reset value.
Figure 10-23. Memory Controller Base Registers 0–3 (BR0–BR3)
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Memory Controller
Table 10-8. BR0–BR3 Bit Descriptions
Bits
Name
Description
0:16
BA
Base address. These bits are compared to the corresponding unmasked address signals among
ADDR[0:16] to determine if a memory bank controlled by the memory controller is being
accessed by an internal bus master. (The address types are also compared.) These bits are used
in conjunction with the AM[0:16] bits in the OR.
17:19
AT
Address type. This field can be used to require accesses of the memory bank to be limited to a
certain address space type. These bits are used in conjunction with the ATM bits in the OR. Note
that the address type field uses only AT[0:2] and does not need AT3 to define the memory type
space. For a full definition of address types, refer to Section 9.5.8.6, “Address Types.”
20:21
PS
Port size
00 32-bit port
01 8-bit port
10 16-bit port
11 Reserved
22
SST
Short Setup Time – This field specifies the setup time required for this memory region.
0 Normal setup time (like the MPC555)
1 Short Setup Time selected
Note that an external burst access with short setup timing will corrupt any USIU register
load/store if SCCR[EBDF] is not 0b00. Refer to Table 8-9.
23
WP
Write protect. An attempt to write to the range of addresses specified in a base address register
that has this bit set can cause the TEA signal to be asserted by the bus-monitor logic (if enabled),
causing termination of this cycle.
0 Both read and write accesses are allowed
1 Only read accesses are allowed. The CSx signal and TA are not asserted by the memory
controller on write cycles to this memory bank. WPER is set in the MSTAT register if a write to
this memory bank is attempted
24
—
Reserved
25
BL
Burst Length – This field specifies the maximum number of words that may comprise a burst
access for this memory region. This field has an effect only in the case when the burst accesses
are initiated by the USIU (SIUMCR[BURST_EN] =1).
0 Burst access of up to 4 words
1 Burst access of up to 8 words
26
WEBS
Write-enable/byte-select. This bit controls the functionality of the WE/BE pads.
0 The WE/BE pads operate as WE
1 The WE/BE pads operate as BE
27
TBDIP
Toggle-burst data in progress. TBDIP determines how long the BDIP strobe will be asserted for
each data beat in the burst cycles.
28
LBDIP
Late-burst-data-in-progress (LBDIP). This bit determines the timing of the first assertion of the
BDIP signal in burst cycles.
NOTE: Do not set both LBDIP and TBDIP bits in a region’s base registers; behavior in such cases
is unpredictable.
0 Normal timing for BDIP assertion (asserts one clock after negation of TS)
1 Late timing for BDIP assertion (asserts after the programmed number of wait states)
29
SETA
External transfer acknowledge
0 TA generated internally by memory controller
1 TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may
have no meaning when this bit is set
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Memory Controller
Table 10-8. BR0–BR3 Bit Descriptions (continued)
Bits
Name
Description
30
BI
Burst inhibit
0 Memory controller drives BI negated (high). The bank supports burst accesses.
1 Memory controller drives BI asserted (low). The bank does not support burst accesses.
NOTE: Following a system reset, the BI bit is set.
31
V
Valid bit. When set, this bit indicates that the contents of the base-register and option-register
pair are valid. The CS signal does not assert until the V-bit is set.
NOTE: An access to a region that has no V-bit set may cause a bus monitor timeout. See
Table 10-9 for the reset value of this bit in BR0.
Table 10-9. BRx[V] Reset Value
10.9.4
Branch Register
BRx[V] Reset Value
BR0
ID3
BR1
0
BR2
0
BR3
ID20 & ID31
Memory Controller Option Registers (OR0–OR3)
1,
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AM1
Field
HRESET
0000_0000_0000_0000
Addr
0x2F C104 (OR0); 0x2F C10C (OR1); 0x2F C114 (OR2), 0x2F C11C (OR3)
LSB
16
AM
HRESET
1
17
18
ATM
19
20
CSNT
0000_0000
21
22
ACS
23
EHTR
24
25
26
27
28
SCY
1111
It is recommended that this field hold values that are the power of 2 minus 1 (e.g.,
29
30
BSCY
0
23 -
1
31
TRLX
1
0
1 = 7 [0b111]).
Figure 10-24. Memory Controller Option Registers 1–3 (OR0–OR3)
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Memory Controller
Table 10-10. OR0–OR3 Bit Descriptions
Bits
Name
Description
0:16
AM
Address mask. This field allows masking of any corresponding bits in the associated base
register. Masking the address bits independently allows external devices of different size address
ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the
corresponding address bit to be used in comparison with the address signals. Address mask bits
can be set or cleared in any order in the field, allowing a resource to reside in more than one area
of the address map. This field can be read or written at anytime.
Following a system reset, the AM bits are cleared in OR0.
17:19
ATM
Address type mask. This field masks selected address type bits, allowing more than one address
space type to be assigned to a chip-select. Any set bit causes the corresponding address type
code bits to be used as part of the address comparison. Any cleared bit masks the corresponding
address type code bit. Clear the ATM bits to ignore address type codes as part of the address
comparison. Note that the address type field uses only AT[0:2] and does not need AT3 to define
the memory type space.
Following a system reset, the ATM bits are cleared in OR0.
20
CSNT
21:22
ACS
23
EHTR
Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after
a read access from the current bank and any MPC561/MPC563 write accesses or read accesses
to a different bank.
0 Memory controller generates normal timing
1 Memory controller generates extended hold timing
Following a system reset, the EHTR bits are cleared in OR0.
24:27
SCY
Cycle length in clocks. This four-bit value represents the number of wait states inserted in the
single cycle, or in the first beat of a burst, when the GPCM handles the external memory access.
Values range from 0 (0b0000) to 15 (0b1111). This is the main parameter for determining the
length of the cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length is (2 + SCY) x Clocks.
If an external TA response is selected for this memory bank (by setting the SETA bit), then the
SCY field is not used.
Following a system reset, the SCY bits are set to 0b1111 in OR0.
Chip-select negation time. Following a system reset, the CSNT bit is reset in OR0.
0 CS/WE are negated normally.
1 CS/WE are negated a quarter of a clock earlier than normal
Following a system reset, the CSNT bit is cleared in OR0.
Address to chip-select setup. Following a system reset, the ACS bits are reset in OR0.
00 CS is asserted at the same time that the address lines are valid.
01 Reserved
10 CS is asserted a quarter of a clock after the address lines are valid.
11 CS is asserted half a clock after the address lines are valid
Following a system reset, the ACS bits are cleared in OR0.
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Memory Controller
Table 10-10. OR0–OR3 Bit Descriptions (continued)
Bits
Name
Description
28:30
BSCY
Burst beats length in clocks. This field determines the number of wait states inserted in all burst
beats except the first, when the GPCM starts handling the external memory access and thus
using SCY[0:3] as the main parameter for determining the length of that cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length for the beat is (1 + BSCY) x Clocks.
If an external TA response has been selected for this memory bank (by setting the SETA bit) then
BSCY[0:3] are not used.
000 0-clock-cycle (1 clock per data beat)
001 1-clock-cycle wait states (2 clocks per data beat)
010 2-clock-cycle wait states (3 clocks per data beat)
011 3-clock-cycle wait states (4 clocks per data beat)
1xx Reserved
Following a system reset, the BSCY bits are set to 0b011 in OR0.
31
TRLX
Timing relaxed. This bit, when set, modifies the timing of the signals that control the memory
devices during a memory access to this memory region. Relaxed timing multiplies by two the
number of wait states determined by the SCY and BSCY fields. Refer to Section 10.3.5,
“Summary of GPCM Timing Options,” for a full list of the effects of this bit on signals timing.
0 Normal timing is generated by the GPCM.
1 Relaxed timing is generated by the GPCM
Following a system reset, the TRLX bit is set in OR0.
10.9.5
Dual-Mapping Base Register (DMBR)
,
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Field
—
BA
—
AT
—
HRESET
0
Undefined
000
001
000
Addr
15
0x2F C140
LSB
16
17
18
19
Field
21
22
23
24
25
26
27
—
HRESET
1
20
28
29
30
DMCS
ID201
0000_0000_0000_0
31
DME
ID311
The reset value is a reset configuration word value extracted from the indicated internal data bus lines. Refer to
Section 7.5.2, “Hard Reset Configuration Word (RCW).”
Figure 10-25. Dual-Mapping Base Register (DMBR)
Table 10-11. DMBR Bit Descriptions
Bits
Name
Description
0
—
Reserved
1:6
BA
Base address. BA field corresponds to address bits [11:16]. The base address field is
compared (along with the address type field) to the address of the address bus to determine
whether an address should be dual-mapped by one of the memory banks controlled by the
memory controller. These bits are used in conjunction with the AM[11:16] bits in the DMOR.
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Table 10-11. DMBR Bit Descriptions
Bits
Name
7:9
—
Reserved
10:12
AT
Address type. This field can be used to specify that accesses involving the memory bank are
limited to a certain address space type. These bits are used in conjunction with the ATM bits
in the OR. The default value at reset is to map data only. For a full definition of address types,
refer to Section 9.5.8.6, “Address Types.”
13:27
—
Reserved
28:30
DMCS
Dual-mapping chip select. This field determines which chip-select signal is assigned for dual
mapping.
000 CS0
001 CS1
010 CS2
011 CS3
1xx Reserved
31
DME
Dual mapping enabled. This bit indicates that the contents of the dual-mapping registers and
associated base and option registers are valid and enables the dual-mapping operation. The
default value at reset comes from the internal data bus that reflects the reset configuration
word. See Section 10.5, “Dual Mapping of the Internal Flash EEPROM Array,” for more
information.
0 Dual mapping is not active
1 Dual mapping is active
10.9.6
Description
Dual-Mapping Option Register (DMOR)
,
MSB
0
Field
1
2
3
4
5
6
7
8
AM1
—
HRESET
9
10
—
0000_0000_00
Addr
11
12
13
14
ATM
—
001
000
15
0x2F C144
LSB
16
17
Field
HRESET
1
18
19
20
21
22
23
24
25
26
27
28
29
30
31
—
0000_0000_0000_0000
It is recommended that this field hold values that are the power of 2 minus 1 (e.g., 23 - 1 = 7 [0b111]).
Figure 10-26. Dual-Mapping Option Register (DMOR)
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Memory Controller
Table 10-12. DMOR Bit Descriptions
Bits
Name
Description
0
—
Reserved
1:6
AM
Address mask. The address mask field of each option register provides for masking any of the
corresponding bits in the associated base register. By masking the address bits independently,
external devices of different size address ranges can be used. Any clear bit masks the
corresponding address bit. Any set causes the corresponding address bit to be used in the
comparison with the address signals. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map. This field
can be read or written at any time.
7:9
—
Reserved
10:12
ATM
13:31
—
Address type mask. This field can be used to mask certain address type bits, allowing more
than one address space type to be assigned to a chip select. Any set bit causes the
corresponding address type code bits to be used as part of the address comparison. Any
cleared bit masks the corresponding address type code bit.
To instruct the memory controller to ignore address type codes as part of the address
comparison, clear the ATM bits.
NOTE: Following a system reset, the ATM bits are cleared in DMOR, except the ATM2 bit. This
means that only data accesses are dual mapped. Refer to the address types definition in
Table 9-8.
Reserved
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Chapter 11
L-Bus to U-Bus Interface (L2U)
The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the
unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides
protection for data memory accesses.
The L2U is bidirectional. It allows load/store accesses not intended for the L-bus data RAM to go to the
U-bus. It also allows code execution from the L-bus data RAM and read/write accesses from the U-bus to
the L-bus.
The L2U directs bus traffic between the L-bus and the U-bus. When transactions start concurrently on both
buses, the L2U interface arbitrates to select which transaction is handled. The top priority is assigned to
U-bus to L-bus accesses; lower priority is assigned to the load/store accesses by the RCPU.
11.1
•
•
•
•
•
•
11.2
•
•
General Features
Non-pipelined master and slave on U-bus
— Does not start two back-to-back accesses on the U-bus
— Supports U-bus pipelining
— Retries back-to-back accesses from U-bus masters
Non-pipelined master and slave on the L-bus
Generates module selects for L-bus memory-mapped resources within a programmable,
contiguous block of storage
Programmable data memory protection unit (DMPU)
L-bus and U-bus snoop logic for the reservation protocol compatible with the PowerPC ISA
architecture
Show cycles for RCPU accesses to the CALRAM (none, all, writes)
— Protection for CALRAM accesses from the U-bus side (all accesses to the CALRAM from the
U-bus side are blocked once the CALRAM protection bit is set)
Data Memory Protection Unit Features
Supports four memory regions whose base address and size can be programmed
— Available sizes are 4 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes, 256
Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, and 16 Mybtes
— Region must start on the specified region size boundary (modulo addressing)
— Overlap between regions is allowed
Each of the four regions supports the following attributes:
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11-1
L-Bus to U-Bus Interface (L2U)
•
•
•
•
•
11.3
– Access protection: user or supervisor
– Guarded attribute: speculative or non-speculative
– Enable/disable option
– Read only option
Supports a default global entry for memory space not covered by other regions:
— Default access protection
— Default guarded attribute
Interrupt generated upon:
— Access violation
— Load from guarded region
— Write to read-only region
The MSR[DR] bit (data relocate) controls DMPU protection on/off operation
Programming is done using the mtspr/mfspr instructions to/from implementation-specific special
purpose registers.
No protection for accesses to the CALRAM module on the L-bus (CALRAM has its own
protection options)
L2U Block Diagram
Figure 11-1 shows a block diagram of the L-bus to U-bus interface as implemented in the overall
MPC561/MPC563 bus architecture.
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L-Bus to U-Bus Interface (L2U)
U-Bus
Burst Buffer
Controller
MPC500
DMPU
Core
+
FP
L-Bus
L-Bus
Interface
Reservation
Control
USIU
E-Bus
U-Bus
Interface
Address
Decode
L-Bus to U-Bus Interface
UIMB
Interface
IMB3
Figure 11-1. L2U Bus Interface Block Diagram
11.4
Modes Of Operation
The L2U module can operate in the following modes:
• Normal mode
• Reset operation
• Peripheral mode
• Factory test mode
11.4.1
Normal Mode
In normal mode (master or slave) the L2U module acts as a bidirectional protocol translator.
• In master mode the RCPU is fully operational, and there is no external master access to the U-bus.
• Slave mode enables an external master to access any internal bus slave while the RCPU is fully
operational. The L2U transfers load/store accesses from the RCPU to the U-bus and the read/write
accesses by the U-bus master to the L-bus.
In addition to the bus protocol translation, the L2U supports other functions such as show cycles, data
memory protection, and MPC500 reservation protocol.
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11-3
L-Bus to U-Bus Interface (L2U)
When a load to or store from the U-bus resource is issued by the RCPU, it is compared against the DMPU
region access (address and attribute) comparators. If none of the access attributes are violated, the access
is directed to the U-bus by the L2U module. If the DMPU detects an access violation, it informs the error
status to the master initiating the cycle.
When show cycles are enabled, accesses to all of the L-bus resources by the RCPU are made visible on
the U-bus side by the L2U.
The L2U is responsible for handling the effects of reservations on the L-bus and the U-bus. For the L-bus
and the U-bus, the L2U detects reservation losses and updates the RCPU core with the reservation status.
11.4.2
Reset Operation
While hard or soft reset is asserted on the U-bus, the L2U asserts the corresponding L-bus reset signals.
Upon soft reset assertion, the L2U goes to an idle state and all pending accesses are ignored. Additionally,
the L2U module control registers are not initialized on soft reset, keeping the system configuration
unchanged.
Upon assertion of hard reset, the L2U control registers are initialized to their reset states. The L2U also
drives the reset configuration word from the U-bus to the L-bus upon hard reset.
11.4.3
Peripheral Mode
In the peripheral mode of operation the RCPU is shut down and an alternative master on the external bus
can perform accesses to any internal bus (U-bus and L-bus) slave.
The external master can also access the internal MPC500 special registers that are located in the L2U
module. In order to access one of these MPC500 registers the EMCR[CONT] bit in the USIU must be
cleared.
11.4.4
Factory Test Mode
Factory test mode is a special mode of operation that allows access to the internal modules for testing. This
mode is not intended for general use and is not supported for normal applications.
11.5
Data Memory Protection
The data memory protection unit (DMPU) in the L2U module provides access protection for the memory
regions on the U-bus side from load/store accesses by the RCPU. (Only U-bus space is protected.) The
DMPU does not protect MPC500 register accesses initiated by the RCPU on the L-bus. The user can assign
up to four regions of access protection attributes and can assign global attributes to any space not included
in the active regions. When it detects an access violation, the L2U generates an exception request to the
CPU. A functional diagram of the DMPU is shown in Figure 11-2.
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L-Bus to U-Bus Interface (L2U)
Address
Access Attribute
Region0 Address and size
Region1 Address and size
Region2 Address and size
Region0 protection/attribute
Match
Select
Region1 protection/attribute
Region2 protection/attribute
Region3 protection/attribute
Region3 Address and size
Global protection/attribute
Specific
Error Interrupts
to Core
Region Protection/Attribute
MSR[DR]
Exception
Logic
Access
Granted
Figure 11-2. DMPU Basic Functional Diagram
11.5.1
Functional Description
Data memory protection is assigned on a regional basis. Default manipulation of the DMPU is done on a
global region. The DMPU has control registers that contain the following information: region protection
on/off, region base address, region size, and the region’s access permissions. Each region’s protection
attributes can be turned on or off by configuring the global region attribute register’s enable attribute bit
(L2U_GRA[ENRx]).
During each load or store access from the RCPU to the U-bus, the address is compared to the value in the
region base address register of each enabled region. Any access that matches the specific region within its
appropriate size, as defined by the region attribute register’s region size field (L2U_RAx[RS]), sets a
match indication.
When more than one match indication occurs, the effective region is the region with the highest priority.
Priority is determined by region number; highest priority corresponds to the lowest region number, e.g.
region 0 is highest priority, while region 3 is lowest.
When no match occurs, the effective region is the global region, which has the lowest priority.
The region attribute register also contains the region’s protection fields. The protection field (PP) of the
effective region is compared to the access attributes. If the attributes match, the access is permitted. When
the access is permitted, a U-bus access may be generated according to the specific attribute of the effective
region.
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11-5
L-Bus to U-Bus Interface (L2U)
When the access by the RCPU is not permitted, the L2U module asserts a data memory storage exception
to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded (G bit of region attribute
register is set), the L2U asks the RCPU to retry the L-bus cycle until either the access is not speculative,
or is canceled by the RCPU.
In the case of attempted accesses to a guarded region together with any other protection violation (no
access), the L2U retries the access. The L2U handles this event as a data storage violation only when the
access becomes non-speculative.
Note that access protection is active only when the MPC500’s MSR[DR] = 1. When MSR[DR] = 0, DMPU
exceptions are disabled, all accesses are considered to be to a guarded memory area, and no speculative
accesses are allowed. In this case, if the L-bus master [RCPU] initiates a non-CALRAM cycle (access
through the L2U) that is marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either
the access is not speculative, or it is canceled by the RCPU Core.
NOTE
The programmer must not overlap the CALRAM memory space with any
enabled region. Overlapping an enabled region with CALRAM memory
space disables the L2U data memory protection for that region.
If an enabled region overlaps with the L-bus space, the DMPU ignores all
accesses to addresses within the L-bus space. If an enabled region overlaps
with MPC500 register addresses, the DMPU ignores any access marked as
an MPC500 access.
11.5.2
Associated Registers
Table 11-1 shows registers that are used to control the DMPU of the L2U module. All the registers are
special purpose registers that are accessed via the MPC500 mtspr/mfspr instructions. The registers are also
accessed by an external master when EMCR[CONT] = 0. See Section 11.8, “L2U Programming Model,”
for register diagrams and bit descriptions.
.
Table 11-1. DMPU Registers
Name
Description
L2U_RBA0
Region Base Address Register 0
L2U_RBA1
Region Base Address Register 1
L2U_RBA2
Region Base Address Register 2
L2U_RBA3
Region Base Address Register 3
L2U_RA0
Region Attribute Register 0
L2U_RA1
Region Attribute Register 1
L2U_RA2
Region Attribute Register 2
L2U_RA3
Region Attribute Register 3
L2U_GRA
Global Region Attribute
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L-Bus to U-Bus Interface (L2U)
NOTE
The appropriate DMPU registers must be programmed before the MSR[DR]
bit is set. Otherwise, DMPU operation is not guaranteed.
Program the region base address in the L2U_RBAx registers to the lower boundary of the region specified
by the corresponding L2U_RAx[RS] field. If the region base address does not correspond to the boundary
of the block size programmed in the L2U_RAx, the DMPU snaps the region base to the lower boundary
of that block. For example, if the block size is programmed to 16 Kbytes for region zero (i.e.,
L2U_RA0[RS] = 0x3) and the region base address is programmed to 0x1FFF(i.e., L2U_RBA0[RBA] =
0x1), then the effective base address of region zero is 0x0. See Figure 11-3.
0x0000 0000
Region 0
(16 Kbytes)
Resulting Region
0x0000 1FFF
Actual Programmed Region
0x0000 3FFF
0x0000 5FFF
Figure 11-3. Region Base Address Example
External action is required to program only legal region sizes. The L2U does not check whether the value
is legal. If an illegal region size is programmed, the region calculation may not be successful.
11.5.3
L-Bus Memory Access Violations
All L-bus slaves have their own access protection logic. For consistency, all storage access violations have
the same termination result. Thus access violations for load/store accesses started by the RCPU always
have the same termination from all slaves: assertion of the data storage exception. All other L-bus masters
cause machine check exceptions.
11.6
Reservation Support
In general terms, a reservation activity is the process whereby a load and store instruction pair is
accompanied by a reservation of the data, the goal being to achieve an atomic operation. If a bus master
other than the one holding the reservation accesses the data (or some other specific condition occurs as
described in Section 11.6.1, “Reservation Protocol”) the reservation is lost and is indicated accordingly.
The RCPU storage reservation protocol supports a multi-level bus structure. For each local bus, storage
reservation is handled by the local reservation logic. The protocol tries to optimize reservation cancellation
such that an MPC500 processor (RCPU) is notified of storage reservation loss on a remote bus (U-bus,
IMB or external bus) only when it has issued a stwcx cycle to that address. That is, the reservation loss
indication comes as part of the stwcx cycle.
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L-Bus to U-Bus Interface (L2U)
11.6.1
Reservation Protocol
The reservation protocol operates under the following assumptions:
• Each processor has at most 1 reservation flag
• A lwarx instruction sets the reservation flag
• Another lwarx instruction by same processor clears the reservation flag related to a previous lwarx
instruction and sets again the reservation flag
• A stwcx instruction by the same processor clears the reservation flag
• A store instruction by the same processor does not clear the reservation flag
• Some other processor (or other mechanism) store to an address with an existing reservation clears
the reservation flag
• In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
11.6.2
L2U Reservation Support
The L2U is responsible for handling the effects of reservations on the L-bus and the U-bus. For the L-bus
and the U-bus, the L2U detects reservation losses.
The reservation logic in the L2U performs the following functions:
• Snoops accesses to all L-bus and U-bus slaves
• Holds one reservation (address) for the core
• Sets the reservation flag when the RPCU issues a load-with-reservation request
The unit for reservation is one word. A byte or half-word store request by another master will clear the
reservation flag.
A load-with-reservation request by the RPCU updates the reservation address related to a previous
load-with-reservation request and sets the reservation flag for the new location. A store-with-reservation
request by the RPCU clears the reservation flag. A store request by the RPCU does not clear the flag. A
store request by some other master to the reservation address clears the reservation flag.
If the storage reservation is lost, it is guaranteed that a store-with-reservation request by the RPCU will not
modify the storage.
The L2U does not start a store-with-reservation cycle on the U-bus if the reserved location on the U-bus
has been touched by another master. The L2U drives the reservation status back to the core.
When the reserved location in the CALRAM on the L-bus is touched by an alternate master, on the
following clock the L2U indicates to the RPCU that the reservation has been touched. On assertion of the
cancel-reservation signal, the RCPU clears the internal reservation bit. If an stwcx cycle has been issued
at the same time, the RCPU aborts the cycle. Software must check the CR0[EQ] bit to determine if the
stwcx instruction completed successfully.
Storage reservation is set regardless of the termination status (address or data phase) of the lwarx access.
Storage reservation is cleared regardless of the data phase termination status of the stwcx access if the
address phase is terminated normally.
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L-Bus to U-Bus Interface (L2U)
Storage reservation will be cleared regardless of the data phase termination status of the write requests by
another master to the reserved address if the address phase of the write access is terminated normally on
the destination (U-bus/L-bus) bus.
If the programmable memory map of the part is modified between a lwarx and a stwcx instruction, the
reservation is not guaranteed.
11.6.3
Reserved Location (Bus) and Possible Actions
Once the RPCU core reserves a memory location, the L2U module is responsible for snooping the L-bus
and U-bus for possible intrusion of the reserved location. Under certain circumstances, the L2U depends
on the USIU or the UIMB to provide status of reservation on external bus and the IMB3 respectively.
Table 11-2 lists all reservation protocol cases supported by the L2U snooping logic.
Table 11-2. Reservation Snoop Support
Reserved Location On
Intruding Alternate Master
L-bus
L-master
Request to cancel the reservation.1
U-master
Request to cancel the reservation.
L-master
Block stwcx2
U-master
Block stwcx
L-master
Block stwcx
U-master
Block stwcx
U-bus
External Bus
Ext-master
IMB3
Action Taken on stwcx cycle
Transfer Status3
L-master
Block stwcx
U-master
Block stwcx
IMB3-master
Transfer Status
1
If the RCPU tries to modify (stwcx) that location, the L2U does not have enough time to stop the write access
from completing. In this case, the L2U will drive cancel-reservation signal back to the core as soon as it
comes to know that the alternate master on the U-bus has touched the reserved location.
2 If the RCPU tries to modify (stwcx) that location, the L2U does not start the cycle on the U-bus and it
communicates to the core that the current write has been aborted by the slave with no side effects.
3 If the RCPU tries to modify (stwcx) that location, the L2U runs a write-cycle-with-reservation request on the
U-bus. The L2U samples the status of the reservation along with the U-bus cycle termination signals and it
communicates to the core if the current write has been aborted by the slave with no side effects.
11.7
L-Bus Show Cycle Support
The L2U module provides support for L-bus show cycles. L-bus show cycles are external visibility cycles
that reflect activity on the L-bus that would otherwise not be visible to the external bus. L-bus show cycles
are software controlled.
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L-Bus to U-Bus Interface (L2U)
11.7.1
Programming Show Cycles
L-bus show cycles are disabled during reset and must be configured by setting the LSHOW[0:1] bits in the
L2U_MCR. Table 11-3 shows the configurations of the LSHOW[0:1] bits.
Table 11-3. L2U_MCR LSHOW Modes
11.7.2
LSHOW
Action
00
Disable L-bus show cycles
01
Show address and data of all L-bus space write cycles
10
Reserved (Disable L-bus show cycles)
11
Show address and data of all L-bus space read and write cycles
Performance Impact
When show cycles are enabled in the L2U module, there is a performance penalty on the L-bus. This
occurs because the L2U module does not support more than one access being processed at any time. To
ensure that only one access at a time is processed, and not lose an L-bus access that would have been show
cycled, the L2U module will arbitrate for the L-bus whenever it is processing any access. This L-bus
arbitration will prevent any other L-bus master from starting a cycle that might turn out to be a qualifiable
L-bus show cycle.
For L-bus show cycles, the minimum performance impact on the L-bus will be three clocks. This minimum
impact assumes that the L-bus slave access is a 1-clock access, and the L2U module acquires immediate
bus grant on the U-bus. The L2U has to wait two clocks before completing the show cycle on the U-Bus,
thus using up five clocks for the complete process.
A retried access on the L-bus (no address acknowledge) that qualifies to be show cycled, will be accepted
when it is actually acknowledged. This will cause a 1-clock delay before an L-bus master can retry the
access on the L-bus, because the L2U module will release L-bus one clock later.
L2U asserts the internal bus request signal on the U-bus for a minimum of two clocks when starting a show
cycle on the U-bus.
11.7.3
Show Cycle Protocol
The L2U module behaves as both a master and a slave on the U-bus during show cycles. The L2U starts
the U-bus transfer as a bus master and then completes the address phase and data phase of the cycle as a
slave. The L2U follows U-bus protocol of in-order termination of the data phase.
The USIU can control the start of show cycles on the U-bus by asserting the no-show cycle indicator. This
will cause the L2U module to release the U-bus for at least one clock before retrying the show cycle.
11.7.4
L-Bus Write Show Cycle Flow
The L2U performs the following sequence of actions for an L-bus-write show cycle.
1. Arbitrates for the L-bus to prevent any other L-bus cycles from starting
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L-Bus to U-Bus Interface (L2U)
2. Latches the address and the data of the L-bus access, along with all address attributes
3. Waits for the termination of the L-bus access and latches the termination status (data error)
4. Arbitrate for the U-bus, and when granted, starts the U-bus access, asserting show cycle request on
the U-bus, along with address, attributes and the write data. The L2U module provides address
recognition and acknowledgment for the address phase. If the no-show cycle indicator from the
U-bus is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until
the no-show cycle indicator is negated and then arbitrates for the U-bus again.
5. When the L2U module has U-bus data bus grant, it drives the data phase termination handshakes
on the U-bus.
6. Releases the L-bus
11.7.5
L-Bus Read Show Cycle Flow
The L2U performs the following sequence of actions for an L-bus read show cycle.
1. Arbitrates for the L-bus to prevent any other L-bus cycle from starting
2. Latches the address of the L-bus access, along with all address attributes
3. Waits for the data phase termination on the L-bus and latches the read data, and the termination
status from the L-bus
4. Arbitrates for the U-bus, and when granted, starts the U-bus access, asserting the show cycle
request on the U-bus, along with address attributes. The L2U module provides address
recognition/acknowledgment for the address phase. If the no-show cycle indicator from the U-bus
is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until the
no-show cycle indicator is negated and then arbitrates for the U-bus again.
5. When the L2U module has U-bus data bus grant, it drives the read data and the data phase
termination handshakes on the U-bus
6. Release the L-bus.
11.7.6
Show Cycle Support Guidelines
The following are the guidelines for L2U show cycle support:
• The L2U module provides address and data for all qualifying L-bus cycles when the appropriate
mode bits are set in the L2U_MCR.
• The L2U-module-only provides show cycles L-bus activity that is not targeted for the U-bus or the
L2U module internal registers, regardless of the termination status of such activity.
• The L2U module does not provide show cycle access to any MPC500 special purpose register.
• The L2U does not start a show cycle for an L-bus access that is retried. This decision to not start
the show cycle causes a clock delay before the cycle can be retried, since the L2U module will have
arbitrated away the L-bus immediately on detecting the show cycle, before the retry information is
available.
• The L2U module does not show cycle any L-bus activity that is aborted.
• The L2U module does not access the U-bus if the USIU inhibits show cycle activity on the U-bus.
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L-Bus to U-Bus Interface (L2U)
•
The L2U does not provide show cycle for any L-bus addresses that fall in the L-bus CALRAM
address space if the CALRAM protection [SP] bit is set in the L2U_MCR.
Table 11-4 summarizes the L2U show cycle support.
Table 11-4. L2U Show Cycle Support Chart
Case
Destination
1
L-bus Slave
2
L2U 4
3
1
U-bus/E-bus
4
L-bus
LB ABORT
2
Comments
No
X
Not show cycled
[Cycle will be retried one clock later]3
X
X
Not show cycled
X
X
Not show cycled
1
Yes
No
Show cycled
slave1
Yes
Yes
Not show cycled
[L-bus will be released next clock]
L-bus slave
5
5
LB AACK
1
L-bus slave includes all address in the L-bus address space.
X indicates don’t care conditions.
3 There will be a 1-clock turnaround because the L-bus retry information is not available in time to
negate the L-bus arbitration.
4
L2U indicates L2U registers.
5 U-bus/E-bus refers to all destinations through the L2U interface.
2
11.8
L2U Programming Model
The L2U control registers control the L2U bus interface and the DMPU. They are accessible via the mtspr
and mfspr instructions. They are also accessible by an external master when EMCR[CONT] bit is cleared.
L2U control registers are accessible from both the L-bus side and the U-bus side in one clock cycle. As
with all SPRs, L2U registers are accessible in supervisor mode only.
Any unimplemented bits in L2U registers return 0’s on a read, and the writes to those register bits are
ignored.
Table 11-5 shows L2U registers along with their SPR numbers and hexadecimal addresses that are used to
access L2U registers during a peripheral mode access.
.
Table 11-5. L2U (PPC) Register Decode
Name
SPR #
SPR[5:9]
SPR[0:4]
Address for
External Master
Access1
Access
Description
L2U_MCR
568
10001
11000
0x0000_3110
SUPR
L2U Module Configuration Register
L2U_RBA0
792
11000
11000
0x0000_3180
SUPR
Region Base Address Register 0
L2U_RBA1
793
11000
11001
0x0000_3380
SUPR
Region Base Address Register 1
L2U_RBA2
794
11000
11010
0x0000_3580
SUPR
Region Base Address Register 2
L2U_RBA3
795
11000
11011
0x0000_3780
SUPR
Region Base Address Register 3
L2U_RA0
824
11001
11000
0x0000_3190
SUPR
Region Attribute Register 0
L2U_RA1
825
11001
11001
0x0000_3390
SUPR
Region Attribute Register 1
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L-Bus to U-Bus Interface (L2U)
Table 11-5. L2U (PPC) Register Decode (continued)
1
Name
SPR #
SPR[5:9]
SPR[0:4]
Address for
External Master
Access1
Access
Description
L2U_RA2
826
11001
11010
0x0000_3590
SUPR
Region Attribute Register 2
L2U_RA3
827
11001
11011
0x0000_3790
SUPR
Region Attribute Register 3
L2U_GRA
536
10000
11000
0x0000_3100
SUPR
Global Region Attribute
When EMCR[CONT] = 0, for external master access only.
For these registers a bus cycle will be performed on the L-bus and the U-bus with the address as shown in
Table 11-6.
.
11.8.1
Table 11-6. Hex Address For SPR Cycles
A[0:17]
A[18:22]
A[23:27]
A[28:31]
0
spr[5:9]
spr[0:4]
0
U-Bus Access
The L2U registers are accessible from the U-bus side only if it is a supervisor mode data access and the
register address is correct and it is indicated on the U-bus that it is a PPC register access.
A user mode access, or an access marked as instruction, to L2U registers from the U-bus side will cause a
data error on the U-bus.
11.8.2
Transaction Size
All L2U registers are defined by MPC500 architecture as being 32-bit registers in normal mode. There is
no MPC500 instruction to access either a half word or a byte of the special purpose register.
All L2U registers are only word accessible (read and write) in peripheral mode. A half-word or byte access
in peripheral mode will result in a word transaction.
11.8.3
L2U Module Configuration Register (L2U_MCR)
The L2U module configuration register (L2U_MCR) is used to control the L2U module operation.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-13
L-Bus to U-Bus Interface (L2U)
MSB
0
Field
1
SP
2
3
4
5
6
7
8
9
LSHOW
10
11
12
13
14
26
27
28
29
30
15
—
Reset
0000_0000_0000_0000
LSB
16
17
18
19
20
21
22
23
24
25
Field
—
Reset
0000_0000_0000_0000
Addr
SPR 568
31
Figure 11-4. L2U Module Configuration Register (L2U_MCR)
Table 11-7. L2U_MCR Bit Descriptions
Bits
Name
Description
0
SP
CALRAM Protection (SP) bit is used to protect the CALRAM on the L-bus from U-bus accesses.
Any attempt to set or clear the SP bit from the U-bus side has no affect.
Once this bit is set, the L2U blocks all CALRAM accesses initiated by the U-bus masters and the
access is terminated with a data error on the U-bus.
If L-bus show cycles are enabled, setting this bit will disable L-bus CALRAM show cycles.
1:2
LSHOW
LSHOW bits are used to configure the show cycle mode for cycles accessing the L-bus slave e.g.
CALRAM
00 Disable show cycles
01 Show address and data of all L-bus space write cycles
10 Reserved
11 Show address and data of all L-bus space read and write cycles
3:31
—
11.8.4
Reserved
Region Base Address Registers (L2U_RBAx)
The L2U region base address register (L2U_RBAx) defines the base address of a specific region protected
by the data memory protection unit. There are four registers (x = 0...3), one for each supported region.
MSB
0
1
2
3
4
5
6
7
8
Field
RBA
Reset
Undefined
9
10
11
12
13
14
25
26
27
28
29
30
15
LSB
16
17
18
19
20
21
22
23
24
Field
RBA
—
Reset
Undefined
0000_0000_0000
Addr
31
SPR 792–795
Figure 11-5. L2U Region x Base Address Register (L2U_RBAx)
MPC561/MPC563 Reference Manual, Rev. 1.2
11-14
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
Table 11-8. L2U_RBAx Bit Descriptions
Bits
Name
Description
0:19
RBA
Region base address. The RBA field provides the base address of the region. The region base
address should start on the block boundary for the corresponding block size attribute specified
in the region attribute register (L2U_RAx).
20:31
—
11.8.5
Reserved
Region Attribute Registers (L2U_RAx)
Each L2U region attribute register defines the protection attributes associated with a specific region
protected by the data memory protection unit. There are four registers (x = 0...3), one for each supported
region.
MSB
0
1
2
3
Field
4
5
6
7
8
9
10
11
—
12
13
14
28
29
30
15
RS
Reset
0000_0000_0000_0000
LSB
16
17
Field
18
RS
19
20
21
22
PP
23
24
—
25
26
27
G
Reset
0000_0000_0000_0000
Addr
SPR 824–827
31
—
Figure 11-6. L2U Region X Attribute Register (L2U_RAx)
Table 11-9. L2U_RAx Bit Descriptions
Bits
Name
Description
0:7
—
Reserved
8:19
RS
Region size
0000_0000_0000 = 4 Kbytes
0000_0000_0001 = 8 Kbytes
0000_0000_0011 = 16 Kbytes
0000_0000_0111 = 32 Kbytes
0000_0000_1111 = 64 Kbytes
0000_0001_1111 = 128 Kbytes
0000_0011_1111 = 256 Kbytes
0000_0111_1111 = 512 Kbytes
0000_1111_1111 = 1 Mbyte
0001_1111_1111 = 2 Mbytes
0011_1111_1111 = 4 Mbytes
0111_1111_1111 = 8 Mbytes
1111_1111_1111 = 16 Mbytes
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-15
L-Bus to U-Bus Interface (L2U)
Table 11-9. L2U_RAx Bit Descriptions (continued)
Bits
Name
20:21
PP
Protection bits
00 No supervisor access, no user access
01 Supervisor read/write access, no user access
10 Supervisor read/write access, user read-only access
11 Supervisor read/write access, user read/write access
22:24
—
Reserved
25
G
Guarded attribute
0 Not guarded from speculative accesses
1 Guarded from speculative accesses
26:31
—
Reserved
11.8.6
Description
Global Region Attribute Register (L2U_GRA)
The L2U global region attribute register (L2U_GRA) defines the protection attributes associated with the
memory region which is not protected under the four DMPU regions. This register also provides
enable/disable control for the four DMPU regions.
MSB
0
1
2
3
4
5
6
7
8
9
Field ENR0 ENR1 ENR2 ENR3
10
11
12
13
14
26
27
28
29
30
15
—
Reset
0000_0000_0000_0000
LSB
16
Field
17
18
—
19
20
21
PP
22
23
24
—
25
G
Reset
0000_0000_0000_0000
Addr
SPR 536
31
—
Figure 11-7. L2U Global Region Attribute Register (L2U_GRA)
Table 11-10. L2U_GRA Bit Descriptions
Bits
Name
Description
0
ENR0
Enable attribute for region 0
0 Region attribute is off
1 Region attribute is on
1
ENR1
Enable attribute for region 1
0 Region attribute is off
1 Region attribute is on
2
ENR2
Enable attribute for region 2
0 Region attribute is off
1 Region attribute is on
MPC561/MPC563 Reference Manual, Rev. 1.2
11-16
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
Table 11-10. L2U_GRA Bit Descriptions (continued)
Bits
Name
Description
3
ENR3
4:19
—
Reserved
20:21
PP
Protection bits
00 No supervisor access, no user access
01 Supervisor read/write access, no user access
10 Supervisor read/write access, user read-only access
11 Supervisor read/write access, user read/write access
22:24
—
Reserved
25
G
Guarded attribute
0 Not guarded from speculative accesses
1 Guarded from speculative accesses
26:31
—
Reserved
Enable attribute for region 3
0 Region attribute is off
1 Region attribute is on
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-17
L-Bus to U-Bus Interface (L2U)
MPC561/MPC563 Reference Manual, Rev. 1.2
11-18
Freescale Semiconductor
Chapter 12
U-Bus to IMB3 Bus Interface (UIMB)
The U-bus to IMB3 bus interface (UIMB) structure is used to connect the CPU internal unified bus (U-bus)
to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3. The
UIMB interface (see Figure 12-1) consists of seven submodules that control bus interface timing, address
decode, data multiplexing, intrasystem communication (interrupts), and clock generation to allow
communication between U-bus and the IMB3. The seven submodules are:
• U-bus interface
• IMB3 interface
• Address decoder
• Data multiplexer
• Interrupt synchronizer
• Clock control
• Scan control
12.1
•
•
•
•
•
Features
Provides complete interfacing between the U-bus and the IMB3:
— 15 bits (32 Kbytes) of address decode on IMB3
— 32-bit data bus
— Read/write access to IMB3 module registers
— Interrupt synchronizer
— Monitoring of accesses to unimplemented addresses within UIMB interface address range
— Burst-inhibited accesses to the modules on IMB3
Support of 32-bit and 16-bit bus interface units (BIUs) for IMB3 modules
Half and full speed operation of IMB3 bus with respect to U-bus
Simple “slave only” U-bus interface implementation
— Transparent mode operation not supported
— Relinquish and retry not supported
Supports scan control for modules on the IMB3 and on the U-bus
NOTE
Modules on the IMB3 bus can only be reset by SRESET. Some modules
may have a module reset, as well.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-1
U-Bus to IMB3 Bus Interface (UIMB)
WARNING
The user should not perform instruction fetches from modules on the IMB3.
12.2
UIMB Block Diagram
U-bus
Interface
U-bus
Address
Decode
IMB3
Interface
IMB3
Data
Mux
Scan Control
Interrupt
Synchronizer
Clock Control
Figure 12-1. UIMB Interface Module Block Diagram
12.3
Clock Module
The clock module within the UIMB interface generates the IMB3 clock. The IMB3 clock is the main
timing reference used within the IMB3 modules.
The IMB3 clock is generated based on the STOP and HSPEED bits in the UIMB module configuration
register (UMCR). If the STOP = 1, the IMB3 clock is not generated. If the STOP = 0 and the HSPEED =
0, the IMB3 clock is generated as the inversion of the internal system clock. This is the same frequency as
the CLKOUT if SCCR[EBDF] = 0b00 – full speed external bus. (See Figure 12-2.) If the HSPEED = 1,
then the IMB3 clock is one-half of the internal system frequency. (See Figure 12-3.)
Table 12-1. STOP and HSPEED Bit Functionality
STOP
HSPEED
Functionality
0
0
IMB3 bus frequency is the same as U-bus frequency.
0
1
IMB3 bus frequency is half that of the U-bus frequency.
1
X
IMB3 clock is not generated.
MPC561/MPC563 Reference Manual, Rev. 1.2
12-2
Freescale Semiconductor
U-Bus to IMB3 Bus Interface (UIMB)
CLKOUT
IMB3 Clock
Figure 12-2. IMB3 Clock – Full-Speed IMB3 Bus
CLKOUT
IMB3 Clock
Figure 12-3. IMB3 Clock – Half-Speed IMB3 Bus
Table 12-2 shows the number of system clock cycles that the UIMB requires to perform each type of bus
cycle. It is assumed that the IMB3 is available to the UIMB at all times (fastest possible case).
Table 12-2. Bus Cycles and System Clock Cycles
Bus Cycle (from U-bus Transfer Start
to U-bus Transfer Acknowledge)
Number of System Clock Cycles
Full Speed
Half Speed
Normal write
4
6
Normal read
4
6
Dynamically-sized write
6
10
Dynamically-sized read
6
10
NOTE
The UIMB interface dynamically interprets the port size of the addressed
module during each bus cycle, allowing bus transfers to and from 16-bit and
32-bit IMB3 modules. During a bus transaction, the slave module on the
IMB3 signals its port size (16- or 32-bit) via an internal port size signal.
12.4
Interrupt Operation
The interrupts from the modules on the IMB3 are propagated to the interrupt controller in the USIU
through the UIMB interface. The UIMB interrupt synchronizer latches the interrupts from the modules on
the IMB3 and drives them onto the U-bus, where they are latched by the USIU interrupt controller.
12.4.1
Interrupt Sources and Levels on IMB3
The IMB3 has eight interrupt lines. There can be a maximum of 32 levels of interrupts from the modules
on IMB3 bus. A single module can be a source for more than one interrupt. For example, the QSMCM can
generate two interrupts (one for QSCI1/QSCI2 and another for QSPI). In this case, the QSMCM has two
interrupt sources. Each of these two sources can assert the interrupt on any of the 32 levels.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-3
U-Bus to IMB3 Bus Interface (UIMB)
It is possible for multiple interrupt sources to assert the same interrupt level. To reduce the latency, it is a
good practice for each interrupt source to assert an interrupt on a level on which no other interrupt source
is mapped.
12.4.2
IMB3 Interrupt Multiplexing
The IMB3 has 10 lines for interrupt support. Eight lines are for interrupts and two are for interrupt level
byte select (ILBS). These lines will transfer the 32 interrupt levels to the interrupt synchronizer. A diagram
of the interrupt flow is shown in Figure 12-4.
UIPEND
Register
IMB3 Interrupt
U-bus Interrupt
Level[0:7]
8
[0:7]
8
[8:15]
Byte Count
Byte-enable
to IMB3
Block
Byte-enables
4
[16:23]
U-bus
Data[0:31]
[24:31]
2
Figure 12-4. Interrupt Synchronizer Signal Flow
Latching 32 interrupt levels using eight IMB3 interrupt lines is accomplished with a 4:1 time-multiplexing
scheme. The UIMB drives two signals (ILBS[0:1]) with a multiplexer select code that tells all interrupting
modules on the IMB3 about which group of signals to drive during the next clock. See Figure 12-5.
12.4.3
ILBS Sequencing
The IMB3 interface drives the ILBS signals continuously, incrementing through a code sequence (0b00,
0b01, 0b10, 0b11) once every clock. The UMCR[IRQMUX] bits in the IMB3 module configuration
register select which type of multiplexing the interrupt synchronizer will perform. The IRQMUX field can
select time-multiplexing protocols for 8, 16, 24 or 32 interrupt sources. These protocols would take one,
two, three or four clocks, respectively.
Table 12-4 shows ILBS sequencing. Programming IRQMUX[0:1] to 0b00 disables time multiplexing. In
this case the ILBS lines remain at 0b00 at all times. In this mode, no interrupts from IMB3 modules which
assert on levels 8 through 31 are ever latched by the interrupt synchronizer. SRESET will not clear the
IRQMUX bits, so time multiplexing will be enabled with the previous setup after SRESET is released.
The timing for the scheme and the values of ILBS and the interrupt levels driven onto the IMB3 IRQ lines
are shown in Figure 12-5. This scheme causes a maximum latency of four clocks and an average latency
of two clocks before the interrupt request can reach the interrupt synchronizer.
MPC561/MPC563 Reference Manual, Rev. 1.2
12-4
Freescale Semiconductor
U-Bus to IMB3 Bus Interface (UIMB)
IMB3 CLOCK
ILBS [0:1]
00
IMB3 LVL[0:7]
01
10
11
00
01
LVL
[0:7]
LVL
[8:15]
LVL
16:23
LVL
24:31
LVL
0:7
10
11
Note: This diagram represents the ILBS behavior when IRQMUX[0:1] = 11
Figure 12-5. Time-Multiplexing Protocol for IRQ Signals
Table 12-3. ILBS Signal Functionality
ILBS[0:1]
Description
00
IMB3 interrupt sources mapped onto 0:7 levels will
drive interrupts onto IMB3 LVL[0:7]
01
IMB3 interrupt sources mapped onto 8:15 levels will
drive interrupts onto IMB3 LVL[0:7]
10
IMB3 interrupt sources mapped onto 16:23 levels will
drive interrupts onto IMB3 LVL[0:7]
11
IMB3 interrupt sources mapped onto 24:31 levels will
drive interrupts onto IMB3 LVL[0:7]
The IRQMUX bits determine how many levels of IMB3 interrupts are sampled. Refer to Table 12-4.
Table 12-4. IRQMUX Functionality
IRQMUX[0:1]
12.4.4
ILBS sequence
Description
00
00, 00, 00.....
Latch 0:7 IMB3 interrupt levels
01
00, 01, 00, 01....
Latch 0:15 IMB3 interrupt levels
10
00, 01, 10, 00, 01, 10,.....
Latch 0:23 IMB3 interrupt levels
11
00, 01, 10, 11, 00, 01, 10, 11,....
Latch 0:31 IMB3 interrupt levels
Interrupt Synchronizer
The interrupt synchronizer latches the 32 levels of interrupts from the IMB3 bus into a register which can
be read by the CPU or other U-bus master. Since there are only eight lines for interrupts on the IMB3 and
32 levels of interrupts are possible, the 32 interrupt levels are multiplexed onto eight IMB3 interrupt lines.
Apart from latching these interrupts in the register (UIPEND), the interrupt synchronizer drives the
interrupts onto the U-bus, where they are latched by the interrupt controller in the USIU.
If IMB3 modules drive interrupts on any of the 24 levels (levels eight through 31), they will be latched in
UIPEND in the UIMB. If any of the register bits 7 to 31 are set, then bit 7 will be set as well.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-5
U-Bus to IMB3 Bus Interface (UIMB)
NOTE
Software must poll this register to find out which of the levels 7 to 31 are
asserted.
The UIPEND register contains a status bit for each of the 32 interrupt levels. Each bit of the register is a
read-only status bit, reflecting the current state of the corresponding interrupt signal. For each of the 32
interrupt levels, a corresponding bit of the UIPEND register is set.
Figure 12-4 shows how the eight interrupt lines are connected to the UIPEND register to represent 32
levels of interrupts. Figure 12-6 shows the implementation of the interrupt synchronizer.
UIPEND
Register
U-bus Interrupt Level[0:7]
LVL[0:7]
8
7
LVL7
IMB3 LVL [0:7]
OR
LVL [8:31]
24
RESET
State
Machine
32
IMBCLOCK
ILBS [0:1]
U-bus
Data[0:31]
4
Figure 12-6. Interrupt Synchronizer Block Diagram
12.5
Programming Model
Table 12-5 lists the registers used for configuring and testing the UIMB module. The address offset shown
in this table is from the start of the block reserved for UIMB registers. As shown in Figure 1-2, this block
begins at offset 0x30 7F80 from the start of the MPC561/MPC563 internal memory map (the last 128-byte
sub-block of the UIMB interface memory map).
Table 12-5. UIMB Interface Register Map
Access1
Base Address
S
0x30 7F80
—
Register
UIMB Module Configuration Register (UMCR)
See Table 12-6 for bit descriptions.
0x30 7F84 — 0x30 7F8F Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
12-6
Freescale Semiconductor
U-Bus to IMB3 Bus Interface (UIMB)
Table 12-5. UIMB Interface Register Map (continued)
Access1
Base Address
S/T
0x30 7F90
—
UIMB Test Control Register (UTSTCREG)
Reserved
0x30 7F94 — 0x30 7F9F Reserved
S
1
Register
0x30 7FA0
Pending Interrupt Request Register (UIPEND)
See Section 12.5.3, “Pending Interrupt Request Register (UIPEND)” for bit
descriptions.
S = Supervisor mode only; T = Test mode only
Any word, half-word or byte access to a 32-bit location within the UIMB interface register decode block
that is unimplemented (defined as reserved) causes the UIMB interface to assert a data error exception on
the U-bus.The entire 32-bit location must be defined as reserved in order for a data error exception to be
asserted.
Unimplemented bits in a register return zero when read.
12.5.1
UIMB Module Configuration Register (UMCR)
The UIMB module configuration register (UMCR) is accessible in supervisor mode only.
MSB
0
Field STOP
HRESET
1
2
3
4
5
6
7
8
9
10
IRQMUX
HSPEED
—
00
1
0000_0000_0000
0
Addr
11
12
13
14
27
28
29
30
15
0x30 7F80
LSB
16
17
Field
HRESET
18
19
20
21
22
23
24
25
26
31
—
0000_0000_0000_0000
Figure 12-7. UIMB Module Configuration Register (UMCR)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-7
U-Bus to IMB3 Bus Interface (UIMB)
Table 12-6. UMCR Bit Descriptions
Bits
Name
Description
0
STOP
Stop enable.
0 Enable system clock for IMB3 bus
1 Disable IMB3 system clock
To avoid complications at restart and data corruption, system software must stop each slave on
the IMB3 before setting the STOP bit. Software must also ensure that all IMB3 interrupts have
been serviced before setting this bit.
1:2
IRQMUX
Interrupt request multiplexing. These bits control the multiplexing of the 32 possible interrupt
requests onto the eight IMB3 interrupt request lines.
00 Disables the multiplexing scheme on the interrupt controller within this interface. What this
means is that the IMB3 IRQ [0:7] signals are non-multiplexed, only providing 8 [0:7] interrupt
request lines to the interrupt controller
01 Enables the IMB3 IRQ control logic to perform a 2-to-1 multiplexing to allow transferring of 16
[0:15] interrupt sources
10 Enables the IMB3 IRQ control logic to perform a 3-to-1 multiplexing to allow transferring of 24
[0:23]interrupt sources
11 Enables the IMB3 IRQ control logic to perform a 4-to-1 multiplexing to allow transferring of 32
[0:31] interrupt sources
3
HSPEED
Half speed. The HSPEED bit controls the frequency at which the IMB3 runs with respect to the
U-bus. This is a modify-once bit. Software can write the reset value of this bit any number of
times. However, once logic 0 is written to this location, any attempt to rewrite this bit to a logic 1
will have no effect.
0 IMB3 frequency is the same as that of the U-bus
1 IMB3 frequency is one half that of the U-bus
4:31
—
12.5.2
Reserved
Test Control Register (UTSTCREG)
The UTSTCREG register is used for factory testing only.
12.5.3
Pending Interrupt Request Register (UIPEND)
The UIPEND register is a read-only status register which reflects the state of the 32 interrupt levels. The
state of IRQ0 is shown in bit 0, the state of IRQ1 is shown in bit 1 and so on. This register is accessible
only in supervisor mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
12-8
Freescale Semiconductor
U-Bus to IMB3 Bus Interface (UIMB)
MSB
0
1
2
3
4
5
6
7
8
9
Field LVL0 LVL1 LVL2 LVL3 LVL4 LVL5 LVL6 LVL7 LVL8 LVL9
10
11
12
13
14
15
LVL
10
LVL
11
LVL
12
LVL
13
LVL
14
LVL
15
0000_0000_0000_0000
HRESET
Addr
0x30 7FA0
LSB
16
Field LVL
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LVL
17
LVL
18
LVL
19
LVL
20
LVL
21
LVL
22
LVL
23
LVL
24
LVL
25
LVL
26
LVL
27
LVL
28
LVL
29
LVL
30
LVL
31
0000_0000_0000_0000
HRESET
Figure 12-8. Pending Interrupt Request Register (UIPEND)
Table 12-7. UIPEND Bit Descriptions
Bits
Name
Description
0:31
LVLx
Pending interrupt request level. Accessible only in supervisor mode. LVLx identifies the interrupt
source as UIMB LVLx, where x is the interrupt number.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-9
U-Bus to IMB3 Bus Interface (UIMB)
MPC561/MPC563 Reference Manual, Rev. 1.2
12-10
Freescale Semiconductor
Chapter 13
QADC64E Legacy Mode Operation
The two queued analog-to-digital converter (QADC) modules on MPC561/MPC563 devices are 10-bit,
unipolar, successive approximation converters. The modules can be configured to operate in one of two
modes, legacy mode (MPC555 compatible) and enhanced mode. This chapter describes how the modules
operate in legacy mode, which is the default mode of operation. Refer to Chapter 14, “QADC64E
Enhanced Mode Operation,” for information regarding the QADC64E functionality in enhanced mode.
For this revision of the QADC, the name QADC64E implies the enhanced version of the QADC module,
not just enhanced mode of operation. For simplicity, the names QADC and QADC64E may be used
interchangeably throughout this document.
13.1
QADC64E Block Diagram
Figure 13-1 displays the major components of the QADC64E modules on the MPC561/MPC563.
EXTERNAL
Triggers
EXTERNAL
MUX Address
Up to 16 ANALOG
Input Signals
REFERENCE ANALOG POWER
Inputs
Inputs
ANALOG Input Multiplexor and
DIGITAL Signal Functions
DIGITAL
CONTROL
10-bit ANALOG to DIGITAL CONVERTER
Queues OF 10-BIT Conversion
Command Words (CCW), 64 Entries
BUS INTERFACE UNIT
(BIU)
10-bit RESULT Table,
64 Entries
10-bit to 16-bit
RESULT Alignment
IMB3
Figure 13-1. QADC64E Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-1
QADC64E Legacy Mode Operation
13.2
Key Features and Quick Reference Diagrams
This section gives an overview of the implementation of the two QADC64E modules on
MPC561/MPC563. It can also be used as a quick reference guide while programming the modules.
13.2.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features of the QADC64E Legacy Mode Operation
Internal sample and hold
Directly supports up to four external multiplexers (for example the MC14051)
Up to 41 analog input channels using QADC64E external multiplexing
Programmable input sample time for various source impedances
Minimum conversion time of 7 µs (with typical QCLK frequency, 2 MHz)
Two conversion command queues with a total of 64 entries
Sub-queues possible using pause mechanism
Queue complete and pause software interrupts available on both queues
Queue pointers indicate current location for each queue
Automated queue modes initiated by
— External edge trigger
— Periodic/Interval timer, within QADC64E module
— Software command
— External gated trigger (Queue 1 only)
Single-scan or continuous-scan of queues
64 result registers in each QADC64E module
Output readable in three formats
— Right-justified unsigned
— Left-justified signed
— Left-justified unsigned
Unused analog channels on Port A can be used as digital input/output signals, unused analog
channels on Port B can be used as digital input signals.
The analog section includes input signals, an analog multiplexer, and the sample and hold circuits. The
analog conversion is performed by the digital-to-analog converter (DAC) resistor-capacitor array and a
high-gain comparator.
The digital control section contains queue control logic to sequence the conversion process and interrupt
generation logic. Also included are the periodic/interval timer, control and status registers, the conversion
command word (CCW) table RAM, and the result table RAM.
The bus interface unit (BIU) allows the QADC64E to operate with the applications software through the
IMB3 environment.
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Freescale Semiconductor
QADC64E Legacy Mode Operation
13.2.2
Memory Map
The QADC64E occupies 1 Kbyte, or 512 16-bit entries, of address space. Ten 16-bit registers are control,
port, and status registers, 64 16-bit entries are the CCW table, and 64 16-bit entries are the result table, and
occupy 192 16-bit address locations because the result data is readable in three data alignment formats.
Each QADC64E module on the MPC561/MPC563 has its own memory space. Table 13-1 shows the
memory map for QADC64E module A, it occupies 0x30 4800 to 0x30 4BFF. Table 13-2 displays the
memory map for module B. Module B has the same offset scheme starting at 0x30 4C00. QADC64E B
occupies 0x30 4C00 to 0x30 4FFF.
Z
Address
Table 13-1. QADC64E_A Address Map
MSB
0
0x30 4800
LSB
1
2
3
4
5
STOP FRZ
0x30 4802
TEST MODE
0x30 4804
IRL1
6
7
8
9
LOC
K
FLI
P
SUPV
10
11
12
13
Module
Config.1
Interrupt1
IRL2
PORTQA
0x30 4808
DDRQA
PORTQB
EMU
X
TR
G
0x30 480C
CIE1
PIE
1
SSE
1
MQ1
0x30 480E
CIE2
PIE
2
SSE
2
MQ2
0x30 4810
CF1
PF1
CF2 PF2 TOR
1
TOR
2
0x30 4812
Port Data
Port Direction
0x30 480A
PSH
PSA
RESUM
E
QS
CWPQ1
1
Control 0
BQ2
Control 2
CWP
Status 0
CWPQ2
Status 1
Reserved
0x30
4A000x30 4A7F
0x30 4B80
0x30 4BFF
PSL
Control 1
0x30 48140x30 49FF
0x30
SIGN
4B000x30 4B7F
Register
15
Test1
0x30 4806
0x30
4A800x30 4AFF
14
P
BY
P
0000 00
IST
CHAN
UNSIGNED RIGHT JUSTIFIED
SIGNED LEFT JUSTIFIED
UNSIGNED LEFT JUSTIFIED
CCWs
Results
00 0000
Results
00 0000
Results
Registers are accessible only as supervisor data space
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Freescale Semiconductor
13-3
QADC64E Legacy Mode Operation
Table 13-2. QADC64E_B Address Map
Address
0x30 4C00
MSB
LSB
0
1
STO
P
FRZ
2
3
0x30 4C02
TEST MODE
0x30 4C04
IRL1
4
7
8
9
LOC
K
FLI
P
SUPV
10
11
12
13
0x30 4C08
DDRQA
Interrupt1
TRG
PSH
SSE
1
MQ1
0x30 4C0E CIE2
PIE
2
SSE
2
MQ2
0x30 4C10
PF1
CF2
PF2
TOR
1
PS
A
PSL
Control 0
Control 1
RESUM
E
TOR
2
QS
CWPQ1
0x30 4C12
Port Data
Port Direction
PIE
1
BQ2
Control 2
CWP
Status 0
CWPQ2
Status 1
0x30
4C140x30 4DFF
Reserved
P
0x30
4E000x30 4E7F
0x30
4E800x30 4EFF
BYP
0000 00
0x30 4F00- SIGN
0x30 4F7F
1Registers
Register
15
Module
Config.1
PORTQB
0x30 4C0C CIE1
0x30 4F80
0x30 4FFF
14
IRL2
PORTQA
CF1
6
Test1
0x30 4C06
0x30 4C0A EMU
X
5
IST
CHAN
UNSIGNED RIGHT JUSTIFIED
SIGNED LEFT JUSTIFIED
UNSIGNED LEFT JUSTIFIED
CCWs
Results
00 0000
Results
00 0000
Results
are accessible only as supervisor data space
Accesses to supervisor-only data space is permitted only when the bus master is operating in supervisor
access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user data space addresses. See Section 13.3.1.4, “Supervisor/Unrestricted Address
Space.”
13.2.3
Legacy and Enhanced Modes of Operation
The QADC64E modules can be configured to operate in legacy or enhanced mode. Legacy mode is the
default state out of reset. Configuring bits in the QADC64E module configuration register enables
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13-4
Freescale Semiconductor
QADC64E Legacy Mode Operation
enhanced mode. This will be described in Section 13.3.1.3, “Switching Between Legacy and Enhanced
Modes of Operation.”
13.2.4
Using the Queue and Result Word Table
The heart of the QADC is its conversion command word (CCW) queues. This is where the module is
programmed to convert a particular channel according to a particular requirement. The queues are created
by writing CCWs into the CCW table in the register memory. The queues are controlled by the three
control registers, and their status can be read from the two status registers. As conversions are completed
the digital value is written into the result word table. Figure 13-2 shows the CCW queue and the result
word table.
Conversion Command
Word (CCW) Table
00
Result Word Table
A/D Converter
Begin Queue 1
00
Channel Select,
Sample, Hold,
and
Analog to Digital
Conversion
End of Queue 1
Begin Queue 2
BQ2
End of Queue 2
MSB
6
7
8
9 10
P BYP IST
LSB
15
CHAN
P = Pause Until Next Trigger
BYP = Bypass Buffer Amplifier
MSB
0
LSB
15
56
0 0 0 0 0 0
Result
Right Justified, Unsigned Result Format
0 1
9 10
15
IST = Input Sample Time
0 0 0 0 0 0
S
Result
Left Justified, Signed Result Format
CHAN = Channel Number and End_of_Queue Code
0
9 10
15
Result
0 0 0 0 0 0
Left Justified, Unsigned Result Format
10-bit Conversion
Command Word
(CCW) Format
10-bit Result is
Software Readable
in Three Different 16-bit Formats
Figure 13-2. QADC64E Conversion Queue Operation
13.2.5
External Multiplexing
The QADC can use from one to four 8-input external multiplexer chips to expand the number of analog
signals that may be converted. The externally multiplexed channels are automatically selected from the
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Freescale Semiconductor
13-5
QADC64E Legacy Mode Operation
channel field of the conversion command word (CCW) table. External Multiplex mode is software
selectable, by setting the EMUX bit of control register 0, QACR0.
Figure 13-3 shows the maximum configuration of four external multiplexer chips connected to the QADC.
The QADC provides three multiplexer address signals – MA[0], MA[1], MA[2] – to select one of the
multiplexer chips. These outputs are the multiplexer control lines and they are connected to all external
multiplexer chips.
The analog output of each of the four multiplexer chips is connected to four separate QADC inputs – ANw,
ANx, ANy, ANz. These signals are the first four signals of port B and each one can represent eight analog
input channels. The QADC converts the proper input channel (ANw, ANx, ANy, ANz) by interpreting the
channel number in the CCW. Refer to Table 13-3.
AN[1]
AN[3]
AN[5]
AN[7]
AN[9]
AN[11]
AN[13]
AN[15]
MUX
AN[16]
AN[18]
AN[20]
AN[22]
AN[24]
AN[26]
AN[28]
AN[30]
MUX
AN[17]
AN[19]
AN[21]
AN[23]
AN[25]
AN[27]
AN[29]
AN[31]
MUX
V
RH
VRL
AN[0]/ANw/PQB[0]
AN[1]/ANx/PQB[1]
AN[2]/ANy/PQB[2]
AN[3]/ANz/PQB[3]
AN[48]/PQB[4]
AN[49]/PQB[5]
AN[50]/PQB[6]
AN[51]/PQB[7]
AN[52]/MA[0]/PQA[0]
AN[53]/MA[1]/PQA[1]
AN[54]/MA[2]/PQA[2]
AN[55]/PQA[3]
AN[56]/PQA[4]
AN[57]PQA[5]
AN[58]/PQA[6]
AN[59]/PQA[7]
ANALOG POWER
ANALOG REFERENCES
PORT B
MUX
V SSA
V DDA
PORT A
AN[0]
AN[2]
AN[4]
AN[6]
AN[8]
AN[10]
AN[12]
AN[14]
QADC
ANALOG
MULTIPLEXER
AND
PORT LOGIC
ANALOG
CONVERTER
DIGITAL
CONTROL
External Triggers:
ETRIG1
ETRIG2
Figure 13-3. Example of External Multiplexing
In the external multiplexed mode, four of the port B signals are redefined to each represent eight input
channels. Refer to Table 13-3 for more information.
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Freescale Semiconductor
QADC64E Legacy Mode Operation
I
Table 13-3. Multiplexed Analog Input Channels
Multiplexed Analog Input
Channels
ANw (AN[0])
0, 2, 4, 6, 8, 10, 12, 14
ANx (AN[1])
1, 3, 5, 7, 9, 11, 13, 15
ANy (AN[2])
16, 18, 20, 22, 24, 26, 28, 30
ANz (AN[3])
17, 19, 21, 23, 25, 27, 29, 31
Table 13-4 shows the total number of analog input channels supported with zero to four external
multiplexer chips using one QADC module.
Table 13-4. Analog Input Channels
Number of Analog Input Channels Available
Directly Connected + External Multiplexed = Total Channels
No External
MUX Chips
One External
MUX Chip
Two External
MUX Chips
Three External
MUX Chips
Four External
MUX Chips
16
20
27
34
41
NOTE: QADC64E External MUX Users
If either QADC64E_A or QADC64E_B is in external multiplexing
(EMUX) mode then the multiplexer address signal channels, AN[52:54]
should not be programmed into queues.
13.3
Programming the QADC64E Registers
The QADC64E has three global registers for configuring module operation:
• Module configuration register (Section 13.3.1, “QADC64E Module Configuration Register
(QADMCR)”)
• Interrupt register (Section 13.3.2, “QADC64E Interrupt Register (QADCINT)”
• Test register (QADCTEST) for factory tests.
The global registers are always defined to be in supervisor-only data space. Refer to Table 13-1 for the
QADC64E_A address map and Table 13-2 for the QADC64E_B address map. See Section 13.3.1.4,
“Supervisor/Unrestricted Address Space” for access modes of these registers.
The remaining five registers in the control register block control the operation of the queuing mechanism,
and provide a means of monitoring the operation of the QADC64E.
• Control register 0 (QACR0) contains hardware configuration information (Section 13.3.5,
“Control Register 0 (QACR0)”)
• Control register 1 (QACR1) is associated with queue 1 (Section 13.3.6, “Control Register 1
(QACR1)”)
• Control register 2 (QACR2) is associated with queue 2 (Section 13.3.7, “Control Register 2
(QACR2)”)
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Freescale Semiconductor
13-7
QADC64E Legacy Mode Operation
•
Status registers (QASR0 and QASR1) provide visibility on the status of each queue and the
particular conversion that is in progress (Section 13.3.8, “Status Registers (QASR0 and QASR1)”)
The CCW table follows the register block in the address map. There are 64 table entries to hold the desired
analog conversion sequences. Each CCW table entry is 16-bits, with ten implemented bits in four fields.
The final block of address space belongs to the result word table, which appears in three places in the
memory map. Each result word table location holds one 10-bit conversion value.
13.3.1
QADC64E Module Configuration Register (QADMCR)
The QADCMCR contains five implemented bits that control the operating modes of the QADC64E
module. The configurable modes are freeze, stop and supervisor. The QADCMCR also implements a pair
of bits that together select either legacy or enhanced mode for the QADC module, and lock that operating
mode.
.
MSB
0
LSB
1
2
3
Field STOP FRZ
SRESET
4
—
0000_0000
Addr
5
6
7
8
9
10
11
LOCK FLIP SUPV
1
12
13
14
15
—
000_0000
0x30 4800 (QADCMCR_A); 0x30 4C00 (QADCMCR_B)
Figure 13-4. Module Configuration Register (QADCMCR)
Table 13-5. QADCMCR Bit Descriptions
Bits
Name
0
STOP
1
FRZ
2:5
—
6
LOCK
7
FLIP
Description
Stop Enable. Refer to Section 13.3.1.1, “Low Power Stop Mode,” for more information.
0 = Disable stop mode
1 = Enable stop mode
Freeze Enable. Refer to Section 13.3.1.2, “Freeze Mode,” for more information.
0 = Ignores the IMB3 internal FREEZE signal
1 = Finish any conversion in progress, then freeze
Reserved
Lock/Unlock QADC Mode of operation as defined by FLIP bit. Refer to Section 13.3.1.3,
“Switching Between Legacy and Enhanced Modes of Operation,” for more information.
0 = QADC mode is locked
1 = QADC mode is unlocked and changeable using FLIP bit
QADC Mode of Operation – The FLIP bit allows selection of the mode of operation of the QADC
module, either legacy mode (default) or enhanced mode. This bit can only be written when the
LOCK is set (unlocked). Refer to Section 13.3.1.3, “Switching Between Legacy and Enhanced
Modes of Operation,” for more information.
0 = Legacy mode enabled
1 = Enhanced mode enabled
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QADC64E Legacy Mode Operation
Table 13-5. QADCMCR Bit Descriptions (continued)
Bits
Name
Description
8
SUPV
Supervisor/Unrestricted Data Space. Refer to Section 13.3.1.4, “Supervisor/Unrestricted
Address Space,” and Table 13-6 for more information.
0 = Only the module configuration register, test register, and interrupt register are designated as
supervisor-only data space. Access to all other locations is unrestricted.
1 = All QADC64E registers and CCW/result tables are designated as supervisor-only data space.
9:15
—
13.3.1.1
Reserved. Write as zeros.
Low Power Stop Mode
When the STOP bit in the QADCMCR is set, the QADC64E clock (QCLK) which clocks the A/D
converter, is disabled and the analog circuitry is powered down. This results in a static, low power
consumption, idle condition. The stop mode aborts any conversion sequence in progress. Because the bias
currents to the analog circuits are turned off in stop mode, the QADC64E requires some recovery time (TSR
in Appendix F, “Electrical Characteristics”) to stabilize the analog circuits after the stop enable bit is
cleared.
In stop mode:
• BIU state machine and logic do not shut down
• The CCW and result is not reset and is not accessible
• The module configuration register (QADCMCR), the interrupt register (QADCINT), and the test
register (QADCTEST) are fully accessible and are not reset
• The data direction register (DDRQA), port data register (PORTQA/PORTQB), and control register
0 (QACR0) are not reset and are read-only accessible
• Control register 1 (QACR1), control register 2 (QACR2), and the status registers (QASR0 and
QASR1) are reset and are read-only accessible
• In addition, the periodic/interval timer is held in reset during stop mode
If the STOP bit is clear, stop mode is disabled.
13.3.1.2
Freeze Mode
Freeze mode occurs when the background debug mode is enabled in the USIU and a breakpoint is
encountered. This is indicated by the assertion of the internal FREEZE line on the IMB3. The FRZ bit in
the QADCMCR determines whether or not the QADC64E responds to an IMB3 internal FREEZE signal
assertion. Freeze is very useful when debugging an application.
When the internal FREEZE signal is asserted and the FRZ bit is set, the QADC64E finishes any conversion
in progress and then freezes.
Depending on when the FREEZE signal is asserted, there are three possible queue "freeze" scenarios:
• When a queue is not executing, the QADC64E freezes immediately
• When a queue is executing, the QADC64E completes the conversion in progress and then freezes
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-9
QADC64E Legacy Mode Operation
•
If, during the execution of the current conversion, the queue operating mode for the active queue
is changed, or a queue 2 abort occurs, the QADC64E freezes immediately
During freeze mode, both the analog clock, QCLK, and periodic/interval timer are held in reset. When the
QADC64E enters the freeze mode while a queue is active, the current CCW location of the queue pointer
is saved.
During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer is held in reset.
External trigger events that occur during the freeze mode are not captured. The BIU remains active to
allow IMB3 access to all QADC64E registers and RAM. Although the QADC64E saves a pointer to the
next CCW in the current queue, the software can force the QADC64E to execute a different CCW by
writing new queue operating modes for normal operation. The QADC64E looks at the queue operating
modes, the current queue pointer, and any pending trigger events to decide which CCW to execute when
exiting freeze.
If the FRZ bit is clear, the internal FREEZE signal is ignored.
13.3.1.3
Switching Between Legacy and Enhanced Modes of Operation
The LOCK and FLIP bits of the QADCMCR register control the operating mode of the QADC64E
modules. Out of reset, the QADC64E modules are in legacy mode (FLIP = 0) and the LOCK bit is clear,
indicating that the module is locked in legacy mode. In order to change the value of the FLIP bit, the
operating mode must first be unlocked, by setting the LOCK bit. Only then can the FLIP bit be changed.
Finally, the LOCK bit must be cleared again to protect the state of the FLIP bit from future writes.
1. Write LOCK = 1 to unlock operating mode bit.
2. Modify the value of FLIP as required.
— FLIP = 0 Legacy mode enabled
— FLIP = 1 Enhanced mode enabled
3. Write LOCK = 0 and new FLIP bit value to preserve the value of FLIP bit
• Example 1 Switching from legacy mode to enhanced mode
— QADCMCR = 0x280; LOCK =1, SUPV = 1
— QADCMCR = 0x380; LOCK =1, write FLIP = 1, SUPV = 1
— QADCMCR = 0x180; LOCK = 0, FLIP = 1, SUPV = 1
Subsequent writes to the FLIP bit will have no effect while LOCK = 0.
• Example 2 Switching from enhanced mode to legacy mode
— QADCMCR = 0x280 or 0x380; LOCK = 1, SUPV =1
(Can write FLIP = x because value will not change)
— QADCMCR = 0x280; LOCK = 1, FLIP = 0, SUPV = 1
— QADCMCR = 0x080; LOCK = 0, FLIP = 0, SUPV =1
13.3.1.4
Supervisor/Unrestricted Address Space
The QADC64E memory map is divided into two segments: supervisor-only data space and assignable data
space. Access to supervisor-only data space is permitted only when the software is operating in supervisor
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Freescale Semiconductor
QADC64E Legacy Mode Operation
access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user data space accesses. The SUPV bit in the QADCMCR designates the assignable
space as supervisor or unrestricted.
The following information applies to accesses to address space located within the module’s 16-bit
boundaries and where the response is a bus error. See Table 13-6 for more information.
• Attempts to read a supervisor-only data space when not in the supervisor access mode and
SUPV = 1, causes the bus master to assert a bus error condition. No data is returned. If SUPV = 0,
the QADC64E asserts a bus error condition and no data is returned.
• Attempts to write to supervisor-only data space when not in the supervisor access mode and
SUPV = 1, causes the bus master to assert a bus error condition. No data is written. If SUPV = 0,
the QADC64E asserts a bus error condition and the register is not written.
• Attempts to read unimplemented data space in the unrestricted access mode and SUPV = 1, causes
the bus master to assert a bus error condition and no data is returned. In all other attempts to read
unimplemented data space, the QADC64E causes a bus error condition and no data is returned.
• Attempts to write unimplemented data space in the unrestricted access mode and SUPV = 1, causes
the bus master to assert a bus error condition and no data is written. In all other attempts to write
unimplemented data space, the QADC64E causes a bus error condition and no data is written.
• Attempts to read assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and no data
is returned.
• Attempts to write assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and the
register is not written.
Table 13-6. QADC64E Bus Error Response
S/U1
Mode
SUPV Bit
Supervisor-Only
Register
Supervisor/
Unrestricted Register
Reserved/
Unimplemented
Register
U
0
QADC64E bus error2
Valid access4
QADC64E bus error2
U
1
Master bus error3
Master bus error3
Master bus error3
S
0
Valid access
Valid access
QADC64E bus error2
S
1
Valid access
Valid access
QADC64E bus error2
1
S/U = Supervisor/Unrestricted
QADC64E bus error = Caused by QADC64E
3 Master bus error = Caused by bus master
4 Access to QADCTEST register will act as a reserved/unimplemented register unless in factory
test mode
2
The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the
IMB3. For privilege violations, refer to the Chapter 9, “External Bus Interface” to determine the
consequence of a bus error cycle termination.
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Freescale Semiconductor
13-11
QADC64E Legacy Mode Operation
The supervisor-only data space segment contains the QADC64E global registers, which include the
QADCMCR, the QADCTEST, and the QADCINT. The supervisor/unrestricted space designation for the
CCW table, the result word table, and the remaining QADC64E registers is programmable.
13.3.2
QADC64E Interrupt Register (QADCINT)
QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level for queue 1 and
queue 2 may be different. The interrupt register is read/write accessible in supervisor data space only. The
implemented interrupt register fields can be read and written, reserved bits read zero and writes have no
effect. They are typically written once when the software initializes the QADC64E, and not changed
afterwards.
MSB
LSB
0
1
Field
2
3
IRL1
4
5
6
7
8
9
10
11
IRL2
SRESET
12
13
14
15
—
0000_0000_0000_0000
Addr
0x30 4804 (QADCINT_A); 0x30 4C04 (QADCINT_B)
Figure 13-5. QADC Interrupt Register (QADCINT)
Table 13-7. QADCINT Bit Descriptions
Bit(s)
Name
Description
0:4
IRL1
Queue 1 Interrupt Request Level. The IRL1 field establishes the queue 1 interrupt request level.
The 00000 state provides a level 0 interrupt, while 11111 provides a level 31 interrupt. All
interrupts are presented on the IMB3. Interrupt level priority software determines which level has
the highest priority request.
5:9
IRL2
Queue 2 Interrupt Request Level. The IRL2 field establishes the queue 2 interrupt request level.
The 00000 state provides a level 0 interrupt, while 11111 provides a level 31 interrupt. All
interrupts are presented on the IMB3. Interrupt level priority software determines which level has
the highest priority request.
10:15
—
Reserved.
The QADC64E conditionally generates interrupts to the bus master via the IMB3 IRQ signals. When the
QADC64E sets a status bit assigned to generate an interrupt, the QADC64E drives the IRQ bus. The value
driven onto IRQ[7:0] represents the interrupt level assigned to the interrupt source. Under the control of
ILBS, each interrupt request level is driven during the time multiplexed bus during one of four different
time slots, with eight levels communicated per time slot. No hardware priority is assigned to interrupts.
Furthermore, if more than one source on a module requests an interrupt at the same level, the system
software must assign a priority to each source requesting at that level. Figure 13-6 displays the interrupt
levels on IRQ with ILBS. Refer to Chapter 12, “U-Bus to IMB3 Bus Interface (UIMB),” for more
information.
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13-12
Freescale Semiconductor
QADC64E Legacy Mode Operation
IMB3 CLOCK
ILBS [1:0]
00
IMB3 IRQ [7:0]
01
10
11
00
01
IRQ
7:0
IRQ
15:8
IRQ
23:16
IRQ
31:24
IRQ
7:0
10
11
Figure 13-6. Interrupt Levels on IRQ with ILBS
13.3.3
Port Data Register (PORTQA and PORTQB)
QADC64E ports A and B are accessed through two 8-bit port data registers (PORTQA and PORTQB) in
each QADC64E.
Port A signals are referred to as PQA[7:0] when used as 8-bit general-purpose digital input or output
signals. It is configured as a digital input or digital output using the data direction register, DDRQA. When
Port A is configured as an input, a read of the PORTQA register returns the actual PQA[7:0] signal values.
When Port A is configured as an output, the contents of port register PQA are driven on the port A signals.
Port A can also be used as analog inputs AN[59:52] and external multiplexer address outputs MA[2:0].
Port B signals are referred to as PQB[7:0] when used as 8-bit general-purpose digital input-only signals.
Digital input signal states are read from the 8-bit PORTQB register. Port B can also be used as
non-multiplexed analog inputs AN[51:48] and AN[3:0], and external multiplexer analog inputs, ANw,
ANx, ANy, ANz.
During a port data register read, the actual value of the signal is reported when its corresponding bit in the
data direction register defines the signal to be an input. When the data direction bit specifies the signal to
be an output, the content of the port data register is read. PORTQA and PORTQB are not initialized by
reset.
MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
LSB
15
Field
PQA PQA PQA PQA PQA PQA PQA PQA
7
6
5
4
3
2
1
0
PQB PQB PQB PQB PQB PQB PQB PQB
7
6
5
4
3
2
1
0
SRESET
Unaffected
Unaffected
Addr
(PORTQA) 0x30 4806 ; 0x30 4C06
(PORTQB) 0x30 4807, 0x30 4C07
ANALOG CHANNEL:
AN5
9
AN5
8
AN5 AN5
7
6
AN5
5
AN5 AN5
4
3
AN5
2
AN5
1
AN5
0
AN4
9
AN4
8
AN3
AN2
AN1
AN0
MULTIPLEXED ADDRESS OUTPUTS:
MA2 MA1 MA0
Figure 13-7. Port x Data Register (PORTQA and PORTQB)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-13
QADC64E Legacy Mode Operation
MULTIPLEXED ANALOG INPUTS:
ANz
ANy
ANx
ANw
Figure 13-7. Port x Data Register (PORTQA and PORTQB)
Table 13-8. PORTQA, PORTQB Bit Descriptions
Bits
Name
0:7
PQA[7:0]
Port A signals are referred to as PQA when used as an 8-bit input/output port. Port A can also
be used for analog inputs (AN[59:52]), and external multiplexer address outputs (MA[2:0]).
8:15
PQB[7:0]
Port B signals are referred to as PQB when used as an 8 input-only port. Port B can also be used
for non-multiplexed (AN[51:48]/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog inputs.
13.3.4
Description
Port Data Direction Register (DDRQA)
The port data direction register, DDRQA, is associated with port A digital input/output signals only. Any
bit set in this register configures the corresponding signal as an output. Any bit cleared in this register
configures the corresponding signal as an input. The software is responsible for ensuring that DDR bits are
not set on signals used for analog inputs. When the DDR bit is set, thereby selecting the signal for analog
conversion, the voltage sampled is that of the output digital driver as influenced by the load.
NOTE
Caution should be exercised when mixing digital and analog inputs. This
should be isolated as much as possible. Rise and fall times should be as large
as possible to minimize AC coupling effects.
There are two special cases to consider for the digital I/O port operation. When QACR0[EMUX] is set,
enabling external multiplexing, the data direction register settings are ignored for the bits corresponding
to PORTQA[2:0], which are the three multiplexed address (MA[2:0]) output signals. The MA[2:0] signals
are forced to be digital outputs, regardless of the data direction setting, and the multiplexed address outputs
are driven. The data returned during a port data register read is the value of the multiplexed address latches
which drive MA[2:0], regardless of the data direction setting.
MSB
0
LSB
1
2
3
4
5
6
7
8
9
10
11
Field DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ
A7
A6
A5
A4
A3
A2
A1
A0
SRESET
Addr
12
13
14
15
—
0000_0000_0000_0000
0x30 4808 (DDRQA_A); 0x30 4C08 (DDRQA_B)
Figure 13-8. Port A Data Direction Register (DDRQA)
13.3.5
Control Register 0 (QACR0)
Control Register 0 is used to define whether external multiplexing is enabled, assign external triggers to
the conversion queues and to sets up the QCLK prescaler parameter field. All of the implemented control
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
QADC64E Legacy Mode Operation
register fields can be read or written but reserved fields read zero and writes have no effect. Typically, they
are written once when software initializes the QADC64E and are not changed afterwards.
MSB
LSB
0
1
Field EMUX
SRESET
0
2
3
4
5
6
7
8
9
10
11
12
13
14
—
TRG
—
PSH
PSA
PSL
00
0
000
0_0001
0
011
Addr
15
0x30 480A (QACR0_A); 0x30 4C0A (QACR0_B)
Figure 13-9. Control Register 0 (QACR0)
Table 13-9. QACR0 Bit Descriptions
Bits
Name
Description
0
EMUX
Externally multiplexed mode. The EMUX bit configures the QADC64E for externally multiplexed
mode, which affects the interpretation of the channel numbers and forces the MA[2:0] signals to
be outputs. See Table 13-7 for more information.
0 Internally multiplexed, 16 possible channels
1 Externally multiplexed, 41 possible channels
1:2
—
3
TRG
4:6
—
7:11
PSH
Prescaler clock high time. The PSH field selects the QCLK high time in the prescaler. PSH value
plus 1 represents the high time in IMB3 clocks
12
PSA
Note that this bit location is maintained for software compatibility with previous versions of the
QADC64E. It serves no functional benefit in the MPC561/MPC563 and is not operational.
13:15
PSL
Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value
plus 1 represents the low time in IMB3 clocks
Reserved
Trigger assignment. TRG allows the software to assign the ETRIG[2:1] signals to queue 1 and
queue 2.
0 ETRIG1 triggers queue 1; ETRIG2 triggers queue 2
1 ETRIG1 triggers queue 2; ETRIG2 triggers queue 1
Refer to Section 13.7.2, “External Trigger Input Signals.”
Reserved
NOTE
Details of how to calculate values for PSH, PSA, and PSL, as well as
examples, are given in Section 13.5.5, “QADC64E Clock (QCLK)
Generation.”
13.3.6
Control Register 1 (QACR1)
Control register 1 is the mode control register for the operation of queue 1. The application software
defines the queue operating mode for the queue, and may enable a completion and/or pause interrupt. All
of the control register fields are read/write data. However, the SSE1 bit always reads as zero. Most of the
bits are typically written once when the software initializes the QADC64E, and not changed afterwards.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-15
QADC64E Legacy Mode Operation
MSB
0
Field CIE1
LSB
1
2
3
4
PIE1 SSE1
5
6
7
8
9
10
11
MQ1
12
13
14
15
—
0000_0000_0000_0000
SRESET
Addr
0x30 480C (QACR1_A); 0x30 4C0C (QACR1_B)
Figure 13-10. Control Register 1 (QACR1)
Table 13-10. QACR1 Bit Descriptions
Bits
Name
Description
0
CIE1
Queue 1 Completion Interrupt Enable. CIE1 enables an interrupt upon completion of
queue 1. The interrupt request is initiated when the conversion is complete for the CCW in
queue 1.
0 Disable the queue completion interrupt associated with queue 1
1 Enable an interrupt after the conversion of the sample requested by the last CCW in
queue 1
1
PIE1
Queue 1 Pause Interrupt Enable. PIE1 enables an interrupt when queue 1 enters the
pause state. The interrupt request is initiated when conversion is complete for a CCW that
has the pause bit set.
0 Disable the pause interrupt associated with queue 1
1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 1
which has the pause bit set
2
SSE1
Queue 1 Single-Scan Enable Bit. SSE1 enables a single-scan of queue 1 to start after a
trigger event occurs. The SSE1 bit may be set to a one during the same write cycle when
the MQ1 bits are set for one of the single-scan queue operating modes. The single-scan
enable bit can be written as a one or a zero, but is always read as a zero. The SSE1 bit
enables a trigger event to initiate queue execution for any single-scan operation on queue
1. The QADC64E clears the SSE1 bit when the single-scan is complete. Refer to
Table 13-11 for more information.
0 Trigger events are not accepted for single-scan modes
1 Accept a trigger event to start queue 1 in a single-scan mode
3:7
MQ1
Queue 1 Operating Mode. The MQ1 field selects the queue operating mode for queue 1.
Table 13-11 shows the bits in the MQ1 field which enable different queue 1 operating mode
8:15
—
Reserved
Table 13-11. Queue 1 Operating Modes
MQ1[3:7]
Operating Modes
00000
Disabled mode, conversions do not occur
00001
Software triggered single-scan mode (started with SSE1)
00010
External trigger rising edge single-scan mode
00011
External trigger falling edge single-scan mode
00100
Interval timer single-scan mode: time = QCLK period x 27
00101
Interval timer single-scan mode: time = QCLK period x 28
00110
Interval timer single-scan mode: time = QCLK period x 29
00111
Interval timer single-scan mode: time = QCLK period x 210
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
QADC64E Legacy Mode Operation
Table 13-11. Queue 1 Operating Modes (continued)
MQ1[3:7]
13.3.7
Operating Modes
01000
Interval timer single-scan mode: time = QCLK period x 211
01001
Interval timer single-scan mode: time = QCLK period x 212
01010
Interval timer single-scan mode: time = QCLK period x 213
01011
Interval timer single-scan mode: time = QCLK period x 214
01100
Interval timer single-scan mode: time = QCLK period x 215
01101
Interval timer single-scan mode: time = QCLK period x 216
01110
Interval timer single-scan mode: time = QCLK period x 217
01111
External gated single-scan mode (started with SSE1)
10000
Reserved mode
10001
Software triggered continuous-scan mode
10010
External trigger rising edge continuous-scan mode
10011
External trigger falling edge continuous-scan mode
10100
Periodic timer continuous-scan mode: time = QCLK period x 27
10101
Periodic timer continuous-scan mode: time = QCLK period x 2 8
10110
Periodic timer continuous-scan mode: time = QCLK period x 2 9
10111
Periodic timer continuous-scan mode: time = QCLK period x 210
11000
Periodic timer continuous-scan mode: time = QCLK period x 211
11001
Periodic timer continuous-scan mode: time = QCLK period x 212
11010
Periodic timer continuous-scan mode: time = QCLK period x 21
11011
Periodic timer continuous-scan mode: time = QCLK period x 214
11100
Periodic timer continuous-scan mode: time = QCLK period x 215
11101
Periodic timer continuous-scan mode: time = QCLK period x 216
11110
Periodic timer continuous-scan mode: time = QCLK period x 217
11111
External gated continuous-scan mode
Control Register 2 (QACR2)
Control register 2 is the mode control register for the operation of queue 2. Software specifies the queue
operating mode of queue 2, and may enable a completion and/or a pause interrupt. All control register
fields are read/write data, except the SSE2 bit, which is readable only when the test mode is enabled. Most
of the bits are typically written once when the software initializes the QADC64E, and not changed
afterwards.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-17
QADC64E Legacy Mode Operation
MSB
LSB
0
Field CIE2
SRESET
1
2
PIE2 SSE2
0
0
Addr
0
3
4
5
6
7
8
9
10
11
12
13
MQ2
RESUME
BQ2
0_0000
0
111_1111
14
15
0x30 480E (QACR2_A), 0x30 4C0E (QACR2_B)
Figure 13-11. Control Register 2 (QACR2)
Table 13-12. QACR2 Bit Descriptions
Bits
Name
Description
0
CIE2
Queue 2 Completion Software Interrupt Enable. CIE2 enables an interrupt upon completion of
queue 2. The interrupt request is initiated when the conversion is complete for the CCW in
queue 2.
0 Disable the queue completion interrupt associated with queue 2
1 Enable an interrupt after the conversion of the sample requested by the last CCW in queue 2
1
PIE2
Queue 2 Pause Software Interrupt Enable. PIE2 enables an interrupt when queue 2 enters the
pause state. The interrupt request is initiated when conversion is complete for a CCW that has
the pause bit set.
0 Disable the pause interrupt associated with queue 2
1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 2 which
has the pause bit set
2
SSE2
Queue 2 Single-Scan Enable Bit. SSE2 enables a single-scan of queue 2 to start after a trigger
event occurs. The SSE2 bit may be set to a one during the same write cycle when the MQ2 bits
are set for one of the single-scan queue operating modes. The single-scan enable bit can be
written as a one or a zero, but is always read as a zero. The SSE2 bit enables a trigger event
to initiate queue execution for any single-scan operation on queue 2. The QADC64E clears the
SSE2 bit when the single-scan is complete. Refer to Table 13-13 for more information.
0 Trigger events are not accepted for single-scan modes
1 Accept a trigger event to start queue 2 in a single-scan mode
3:7
MQ2
Queue 2 Operating Mode. The MQ2 field selects the queue operating mode for queue 2. Refer
to Table 13-13 for more information.
8
RESUME
0 After suspension, begin executing with the first CCW in queue 2 or the current sub-queue
1 After suspension, begin executing with the aborted CCW in queue 2
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
QADC64E Legacy Mode Operation
Table 13-12. QACR2 Bit Descriptions (continued)
Bits
Name
Description
9:15
BQ2
Beginning of queue 2. The BQ2 field indicates the CCW location where queue 2 begins. To
allow the length of queue 1 and queue 2 to vary, a programmable pointer identifies the CCW
table location where queue 2 begins. The BQ2 field also serves as an end-of-queue condition
for queue 1. Setting BQ2 beyond physical CCW table memory space allows queue 1 all 64
entries.
Software defines the beginning of queue 2 by programming the BQ2 field in QACR2. BQ2 is
usually programmed before or at the same time as the queue operating mode for queue 2 is
selected. If BQ2 is 64 or greater, queue 2 has no entries, and the entire CCW table is dedicated
to queue 1 and CCW63 is the end-of-queue 1. If BQ2 is zero, the entire CCW table is dedicated
to queue 2. As a special case, when a queue operating mode for queue 1 is selected and a
trigger event occurs for queue 1 with BQ2 set to zero, queue 1 execution is terminated after
CCW0 is read. Conversions do not occur.
The BQ2 pointer may be changed dynamically, to alternate between queue 2 scan sequences.
A change in BQ2 after queue 2 has begun or if queue 2 has a trigger pending does not affect
queue 2 until queue 2 is started again.For example, two scan sequences could be defined as
follows: the first sequence starts at CCW10, with a pause after CCW11 and an EOQ
programmed in CCW15; the second sequence starts at CCW16, with a pause after CCW17
and an EOQ programmed in CCW39.
With BQ2 set to CCW10 and the continuous-scan mode selected, queue execution begins.
When the pause is encountered in CCW11, a software interrupt routine can redefine BQ2 to be
CCW16. Therefore, after the end-of-queue is recognized in CCW15, an internal retrigger event
is generated and execution restarts at CCW16. When the pause software interrupt occurs
again, software can change BQ2 back to CCW10. After the end-of-queue is recognized in
CCW39, an internal retrigger event is created and execution now restarts at CCW10.
If BQ2 is changed while queue 1 is active, the effect of BQ2 as an end-of-queue indication for
queue 1 is immediate. However, beware of the risk of losing the end-of-queue 1 through moving
BQ2. Recommend use of EOQ (chan63) to end queue 1.
Note: Be sure to do a mode change when changing BQ2 and setting SSE2. Setting BQ2 first
is recommended.
Table 13-13 shows the bits in the MQ2 field that enable different queue 2 operating modes.
Table 13-13. Queue 2 Operating Modes
MQ2[3:7]
Operating Modes
00000
Disabled mode, conversions do not occur
00001
Software triggered single-scan mode (started with SSE2)
00010
External trigger rising edge single-scan mode
00011
External trigger falling edge single-scan mode
00100
Interval timer single-scan mode: time = QCLK period x 27
00101
Interval timer single-scan mode: time = QCLK period x 28
00110
Interval timer single-scan mode: time = QCLK period x 29
00111
Interval timer single-scan mode: time = QCLK period x 210
01000
Interval timer single-scan mode: time = QCLK period x 211
01001
Interval timer single-scan mode: time = QCLK period x 212
01010
Interval timer single-scan mode: time = QCLK period x 213
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-19
QADC64E Legacy Mode Operation
Table 13-13. Queue 2 Operating Modes (continued)
MQ2[3:7]
Operating Modes
01011
Interval timer single-scan mode: time = QCLK period x 214
01100
Interval timer single-scan mode: time = QCLK period x 215
01101
Interval timer single-scan mode: time = QCLK period x 216
01110
Interval timer single-scan mode: time = QCLK period x 217
01111
Reserved mode
10000
Reserved mode
10001
Software triggered continuous-scan mode
10010
External trigger rising edge continuous-scan mode
10011
External trigger falling edge continuous-scan mode
10100
Periodic timer continuous-scan mode: time = QCLK period x 27
10101
Periodic timer continuous-scan mode: time = QCLK period x 28
10110
Periodic timer continuous-scan mode: time = QCLK period x 29
10111
Periodic timer continuous-scan mode: time = QCLK period x 210
11000
Periodic timer continuous-scan mode: time = QCLK period x 211
11001
Periodic timer continuous-scan mode: time = QCLK period x 212
11010
Periodic timer continuous-scan mode: time = QCLK period x 213
11011
Periodic timer continuous-scan mode: time = QCLK period x 214
11100
Periodic timer continuous-scan mode: time = QCLK period x 215
11101
Periodic timer continuous-scan mode: time = QCLK period x 216
11110
Periodic timer continuous-scan mode: time = QCLK period x 217
11111
Reserved mode
NOTE
If BQ2 was assigned to the CCW that queue 1 is currently working on, then
that conversion is completed before BQ2 takes effect.
Each time a CCW is read for queue 1, the CCW location is compared with the current value of the BQ2
pointer to detect a possible end-of-queue condition. For example, if BQ2 is changed to CCW3 while queue
1 is converting CCW2, queue 1 is terminated after the conversion is completed. However, if BQ2 is
changed to CCW1 while queue 1 is converting CCW2, the QADC64E would not recognize a BQ2
end-of-queue condition until queue 1 execution reached CCW1 again, presumably on the next pass
through the queue.
13.3.8
Status Registers (QASR0 and QASR1)
The status registers contains information about the state of each queue and the current A/D conversion.
Except for the four flag bits (CF1, PF1, CF2, and PF2) and the two trigger overrun bits (TOR1 and TOR2),
MPC561/MPC563 Reference Manual, Rev. 1.2
13-20
Freescale Semiconductor
QADC64E Legacy Mode Operation
all of the status register fields contain read-only data. The four flag bits and the two trigger overrun bits
are cleared by writing a zero to the bit after the bit was previously read as a one.
MSB
0
Field CF1
LSB
1
2
3
PF1
CF2
PF2
SRESET
4
5
6
TOR1 TOR2
7
8
9
10
QS
11
12
13
14
15
CWP
0000_0000_0000_0000
Addr
0x30 4810 (QASR0_A); 0x30 4C10 (QASR0_B)
Figure 13-12. Status Register 0 (QASR0)
Table 13-14. QASR0 Bit Descriptions
Bits
Name
Description
0
CF1
Queue 1 Completion Flag. CF1 indicates that a queue 1 scan has been completed. The
scan completion flag is set by the QADC64E when the input channel sample requested by
the last CCW in queue 1 is converted, and the result is stored in the result table.
The end-of-queue 1 is identified when execution is complete on the CCW in the location
prior to that pointed to by BQ2, when the current CCW contains an end-of-queue code
instead of a valid channel number, or when the currently completed CCW is in the last
location of the CCW RAM.
When CF1 is set and interrupts are enabled for that queue completion flag, the QADC64E
asserts an interrupt request at the level specified by IRL1 in the interrupt register
(QADCINT). The software reads the completion flag during an interrupt service routine to
identify the interrupt request. The interrupt request is cleared when the software writes a
zero to the completion flag bit, when the bit was previously read as a one. Once set, only
software or reset can clear CF1.
CF1 is maintained by the QADC64E regardless of whether the corresponding interrupt is
enabled. The software polls for CF1 bit to see if it is set. This allows the software to
recognize that the QADC64E is finished with a queue 1 scan. The software acknowledges
that it has detected the completion flag being set by writing a zero to the completion flag
after the bit was read as a one.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-21
QADC64E Legacy Mode Operation
Table 13-14. QASR0 Bit Descriptions (continued)
Bits
Name
Description
1
PF1
Queue 1 Pause Flag. PF1 indicates that a queue 1 scan has reached a pause. PF1 is set
by the QADC64E when the current queue 1 CCW has the pause bit set, the selected input
channel has been converted, and the result has been stored in the result table.
Once PF1 is set, the queue enters the paused state and waits for a trigger event to allow
queue execution to continue. However, if the CCW with the pause bit set is the last CCW
in a queue, the queue execution is complete. The queue status becomes idle, not paused,
and both the pause and completion flags are set. Another exception occurs in software
controlled mode, where the PF1 can be set but queue 1 never enters the pause state since
queue 1 continues without pausing.
When PF1 is set and interrupts are enabled for the corresponding queue, the QADC64E
asserts an interrupt request at the level specified by IRL1 in the interrupt register. The
software may read PF1 during an interrupt service routine to identify the interrupt request.
The interrupt request is cleared when the software writes a zero to PF1, when the bit was
previously read as a one. Once set, only software or reset can clear PF1.
In external gated single-scan and continuous-scan mode the definition of PF1 has been
redefined. When the gate closes before the end-of-queue 1 is reached, PF1 becomes set
to indicate that an incomplete scan has occurred.In single-scan mode, setting PF1 can be
used to cause an interrupt and software can then determine if queue 1 should be enabled
again. In either external gated mode, setting PF1 indicates that the results for queue 1 have
not been collected during one scan (coherently).
NOTE: If a pause in a CCW is encountered in external gated mode for either single-scan
and continuous-scan mode, the pause flag will not set, and execution continues without
pausing. This has allowed for the added definition of PF1 in the external gated modes.
PF1 is maintained by the QADC64E regardless of whether the corresponding interrupts
are enabled. The software may poll PF1 to find out when the QADC64E has reached a
pause in scanning a queue.The software acknowledges that it has detected a pause flag
being set by writing a zero to PF1 after the bit was last read as a one.
0 = queue 1 has not reached a pause (or gate has not closed before end-of-queue in gated
mode)
1 = queue 1 has reached a pause (or gate closed before end-of-queue in gated mode)
Refer to Table 13-15 for a summary of pause response in all scan modes.
2
CF2
Queue 2 Completion Flag. CF2 indicates that a queue 2 scan has been completed. CF2 is
set by the QADC64E when the input channel sample requested by the last CCW in queue
2 is converted, and the result is stored in the result table.
The end-of-queue 2 is identified when the current CCW contains an end-of-queue code
instead of a valid channel number, or when the currently completed CCW is in the last
location of the CCW RAM.
When CF2 is set and interrupts are enabled for that queue completion flag, the QADC64E
asserts an interrupt request at the level specified by IRL2 in the interrupt register
(QADCINT). The software reads CF2 during an interrupt service routine to identify the
interrupt request. The interrupt request is cleared when the software writes a zero to the
CF2 bit, when the bit was previously read as a one. Once set, only software or reset can
clear CF2.
CF2 is maintained by the QADC64E regardless of whether the corresponding interrupts
are enabled. The software polls for CF2 to see if it is set. This allows the software to
recognize that the QADC64E is finished with a queue 2 scan. The software acknowledges
that it has detected the completion flag being set by writing a zero to the completion flag
after the bit was read as a one.
MPC561/MPC563 Reference Manual, Rev. 1.2
13-22
Freescale Semiconductor
QADC64E Legacy Mode Operation
Table 13-14. QASR0 Bit Descriptions (continued)
Bits
Name
Description
3
PF2
Queue 2 Pause Flag. PF2 indicates that a queue 2 scan has reached a pause. PF2 is set
by the QADC64E when the current queue 2 CCW has the pause bit set, the selected input
channel has been converted, and the result has been stored in the result table.
Once PF2 is set, the queue enters the paused state and waits for a trigger event to allow
queue execution to continue. However, if the CCW with the pause bit set is the last CCW
in a queue, the queue execution is complete. The queue status becomes idle, not paused,
and both the pause and completion flags are set. Another exception occurs in software
controlled mode, where the PF2 can be set but queue 2 never enters the pause state.
When PF2 is set and interrupts are enabled for the corresponding queue, the QADC64E
asserts an interrupt request at the level specified by IRL2 in the interrupt register. The
software reads PF2 during an interrupt service routine to identify the interrupt request. The
interrupt request is cleared when the software writes a zero to PF2, when the bit was
previously read as a one. Once set, only software or reset can clear PF2.
PF2 is maintained by the QADC64E regardless of whether the corresponding interrupts
are enabled. The software may poll PF2 to find out when the QADC64E has reached a
pause in scanning a queue. The software acknowledges that it has detected a pause flag
being set by writing a zero to PF2 after the bit was last read as a one.
0 queue 2 has not reached a pause
1 queue 2 has reached a pause
Refer to Table 13-15 for a summary of pause response in all scan modes.
4
TOR1
Queue 1 Trigger Overrun. TOR1 indicates that an unexpected trigger event has occurred
for queue 1. TOR1 can be set only while queue 1 is in the active state.
A trigger event generated by a transition on the external trigger signal or by the
periodic/interval timer may be captured as a trigger overrun. TOR1 cannot occur when the
software initiated single-scan mode or the software initiated continuous-scan mode are
selected.
TOR1 occurs when a trigger event is received while a queue is executing and before the
scan has completed or paused. TOR1 has no effect on the queue execution.
After a trigger event has occurred for queue 1, and before the scan has completed or
paused, additional queue 1 trigger events are not retained. Such trigger events are
considered unexpected, and the QADC64E sets the TOR1 error status bit. An unexpected
trigger event may be a system overrun situation, indicating a system loading mismatch.
In external gated continuous-scan mode the definition of TOR1 has been redefined. In the
case when queue 1 reaches an end-of-queue condition for the second time during an open
gate, TOR1 becomes set. This is considered an overrun condition. In this case CF1 has
been set for the first end-of-queue 1 condition and then TOR1 becomes set for the second
end-of-queue 1 condition. For TOR1 to be set, software must not clear CF1 before the
second end-of-queue 1.
The software acknowledges that it has detected a trigger overrun being set by writing a
zero to the trigger overrun, after the bit was read as a one. Once set, only software or reset
can clear TOR1.
0 No unexpected queue 1 trigger events have occurred
1 At least one unexpected queue 1 trigger event has occurred (or queue 1 reaches an
end-of-queue condition for the second time in gated mode)
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13-23
QADC64E Legacy Mode Operation
Table 13-14. QASR0 Bit Descriptions (continued)
Bits
Name
Description
5
TOR2
Queue 2 Trigger Overrun. TOR2 indicates that an unexpected trigger event has occurred
for queue 2. TOR2 can be set when queue 2 is in the active, suspended, and trigger
pending states.
The TOR2 trigger overrun can only occur when using an external trigger mode or a
periodic/interval timer mode. Trigger overruns cannot occur when the software initiated
single-scan mode and the software initiated continuous-scan mode are selected.
TOR2 occurs when a trigger event is received while queue 2 is executing, suspended, or
a trigger is pending. TOR2 has no effect on the queue execution. A trigger event that
causes a trigger overrun is not retained since it is considered unexpected.
An unexpected trigger event may be a system overrun situation, indicating a system
loading mismatch. The software acknowledges that it has detected a trigger overrun being
set by writing a zero to the trigger overrun, after the bit was read as a one. Once set, only
software or reset can clear TOR2.
0 No unexpected queue 2 trigger events have occurred
1 At least one unexpected queue 2 trigger event has occurred
6:9
QS
Queue Status. The 4-bit read-only QS field indicates the current condition of queue 1 and
queue 2. The following are the five queue status conditions:
• Idle
• Active
• Paused
• Suspended
• Trigger pending
The two most significant bits are associated primarily with queue 1, and the remaining two
bits are associated with queue 2. Since the priority scheme between the two queues
causes the status to be interlinked, the status bits are considered as one 4-bit field.
Table 13-16 shows the bits in the QS field and how they affect the status of queue 1 and
queue 2. Refer to Section 13.6, “Trigger and Queue Interaction Examples,” which shows
the 4-bit queue status field transitions in typical situations.
10:15
CWP
Command Word Pointer. The CWP allows the software to know which CCW is executing
at present, or was last completed. The command word pointer is a software read-only field,
and write operations have no effect. The CWP allows software to monitor the progress of
the QADC64E scan sequence. The CWP field is a CCW word pointer with a valid range of
0 to 63.
When a queue enters the paused state, the CWP points to the CCW with the pause bit set.
While in pause, the CWP value is maintained until a trigger event occurs on the same
queue or the other queue. Usually, the CWP is updated a few clock cycles before the queue
status field shows that the queue has become active. For example, software may read a
CWP pointing to a CCW in queue 2, and the status field shows queue 1 paused, queue 2
trigger pending.
When the QADC64E finishes the scan of the queue, the CWP points to the CCW where
the end-of-queue (EOQ) condition was detected. Therefore, when the end-of-queue
condition is a CCW with the EOQ code (channel 63), the CWP points to the CCW
containing the EOQ.
When the last CCW in a queue is in the last CCW table location (CCW63), and it does not
contain the EOQ code, the end-of-queue is detected when the following CCW is read, so
the CWP points to word CCW0.
Finally, when queue 1 operation is terminated after a CCW is read that is defined as BQ2,
the CWP points to the same CCW as BQ2.
During the stop mode, the CWP is reset to zero, since the control registers and the analog
logic are reset. When the freeze mode is entered, the CWP is unchanged; it points to the
last executed CCW.
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QADC64E Legacy Mode Operation
Table 13-15. Pause Response
Scan Mode
Q Operation
PF Asserts?
External Trigger Single-scan
Pauses
Yes
External Trigger Continuous-scan
Pauses
Yes
Periodic/Interval Timer Trigger Single-scan
Pauses
Yes
Periodic/Interval Timer Continuous-scan
Pauses
Yes
Software Initiated Single-scan
Continues
Yes
Software Initiated Continuous-scan
Continues
Yes
External Gated Single-scan
Continues
No
External Gated Continuous-scan
Continues
No
Table 13-16. Queue Status
QS[9:6]
Queue 1/Queue 2 States
0000
queue 1 idle, queue 2 idle
0001
queue 1 idle, queue 2 paused
0010
queue 1 idle, queue 2 active
0011
queue 1 idle, queue 2 trigger pending
0100
queue 1 paused, queue 2 idle
0101
queue 1 paused, queue 2 paused
0110
queue 1 paused, queue 2 active
0111
queue 1 paused, queue 2 trigger pending
1000
queue 1 active, queue 2 idle
1001
queue 1 active, queue 2 paused
1010
queue 1 active, queue 2 suspended
1011
queue 1 active, queue 2 trigger pending
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
One or both queues may be in the idle state. When a queue is idle, CCWs are not being executed for that
queue, the queue is not in the pause state, and there is not a trigger pending.
The idle state occurs when a queue is disabled, when a queue is in a reserved mode, or when a queue is in
a valid queue operating mode awaiting a trigger event to initiate queue execution.
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13-25
QADC64E Legacy Mode Operation
A queue is in the active state when a valid queue operating mode is selected, when the selected trigger
event has occurred, or when the QADC64E is performing a conversion specified by a CCW from that
queue.
Only one queue can be active at a time. Either or both queues can be in the paused state. A queue is paused
when the previous CCW executed from that queue had the pause bit set. The QADC64E does not execute
any CCWs from the paused queue until a trigger event occurs. Consequently, the QADC64E can service
queue 2 while queue 1 is paused.
Only queue 2 can be in the suspended state. When a trigger event occurs on queue 1 while queue 2 is
executing, the current queue 2 conversion is aborted. The queue 2 status is reported as suspended. Queue
2 transitions back to the active state when queue 1 becomes idle or paused.
A trigger pending state is required since both queues cannot be active at the same time. The status of queue
2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. In the
opposite case, when a trigger event occurs for queue 1 while queue 2 is active, queue 2 is aborted and the
status is reported as queue 1 active, queue 2 suspended. So due to the priority scheme, only queue 2 can
be in the trigger pending state.
There are two transition cases which cause the queue 2 status to be trigger pending before queue 2 is shown
to be in the active state. When queue 1 is active and there is a trigger pending on queue 2, after queue 1
completes or pauses, queue 2 continues to be in the trigger pending state for a few clock cycles. The
following are fleeting status conditions:
• Queue 1 idle with queue 2 trigger pending
• Queue 1 paused with queue 2 trigger pending
Figure 13-13 displays the status conditions of the queue status field as the QADC64E goes through the
transition from queue 1 active to queue 2 active.
Queue 1
Queue 2
Active
Idle
Active
Trigger Pending
Idle (Paused)
Trigger Pending
Idle (Paused)
Active
Figure 13-13. QADC64E Queue Status Transition
The queue status field is affected by the stop mode. Because all of the analog logic and control registers
are reset, the queue status field is reset to queue 1 idle, queue 2 idle.
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QADC64E Legacy Mode Operation
During the freeze mode, the queue status field is not modified. The queue status field retains the status it
held prior to freezing. As a result, the queue status can show queue 1 active, queue 2 idle, even though
neither queue is being executed during freeze.
MSB
LSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Field
—
CWPQ1
—
CWPQ2
SRESET
00
11_1111
00
11_1111
Addr
14
15
0x30 4812 (QASR1_A); 0x30 4C12 (QASR1_B)
Figure 13-14. Status Register 1 (QASR1)
Table 13-17. QASR1 Bit Descriptions
Bits
Name
0:1
—
2:7
CWPQ1
8:9
—
10:15
CWPQ2
13.3.9
Description
Reserved
Command Word Pointer for Q1 . CWPQ1 allows the software to know what CCW was last
completed for queue 1. This field is a software read-only field, and write operations have
no effect. CWPQ1 allows software to read the last executed CCW in queue 1, regardless
of which queue is active. The CWPQ1 field is a CCW word pointer with a valid range of 0
to 63.
In contrast to CWP, CPWQ1 is updated when the conversion result is written. When the
QADC64E finishes a conversion in queue 1, both the result register is written and the
CWPQ1 are updated.
Finally, when queue 1 operation is terminated after a CCW is read that is defined as BQ2,
CWP points to BQ2 while CWPQ1 points to the last CCW queue 1.
During the stop mode, the CWPQ1 is reset to 63, since the control registers and the analog
logic are reset. When the freeze mode is entered, the CWPQ1 is unchanged; it points to
the last executed CCW in queue 1.
Reserved
Command Word Pointer for Q2. CWPQ2 allows the software to know what CCW was last
completed for queue 2. This field is a software read-only field, and write operations have
no effect. CWPQ2 allows software to read the last executed CCW in queue 2, regardless
which queue is active. The CWPQ2 field is a CCW word pointer with a valid range of 0 to
63.
In contrast to CWP, CPWQ2 is updated when the conversion result is written. When the
QADC64E finishes a conversion in queue 2, both the result register is written and the
CWPQ2 are updated.
During the stop mode, the CWPQ2 is reset to 63, since the control registers and the analog
logic are reset. When the freeze mode is entered, the CWP is unchanged; it points to the
last executed CCW in queue 2.
Conversion Command Word Table
The conversion command word (CCW) table is a RAM, 64 words long on 16-bit address boundaries where
10-bits of each entry are implemented. A CCW can be programmed by the software to request a conversion
of one analog input channel. The CCW table is written by software and is not modified by the QADC64E.
Each CCW requests the conversion of an analog channel to a digital result. The CCW specifies the analog
channel number, the input sample time, and whether the queue is to pause after the current CCW. The ten
implemented bits of the CCW word are read/write data, where they may be written when the software
initializes the QADC64E. The remaining 6-bits are unimplemented so these read as zeros, and write
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QADC64E Legacy Mode Operation
operations have no effect. Each location in the CCW table corresponds to a location in the result word
table. When a conversion is completed for a CCW entry, the 10-bit result is written in the corresponding
result word entry. The QADC64E provides 64 CCW table entries.
The beginning of queue 1 is the first location in the CCW table. The first location of queue 2 is specified
by the beginning of queue 2 pointer (BQ2) in QACR2. To dedicate the entire CCW table to queue 1, queue
2 is programmed to be in the disabled mode, and BQ2 is programmed to 64 or greater. To dedicate the
entire CCW table to queue 2, queue 1 is programmed to be in the disabled mode, and BQ2 is specified as
the first location in the CCW table.Figure 13-15 illustrates the operation of the queue structure.
Conversion Command
Word (CCW) Table
0x200 (ccw0)1
Result Word Table
A/D Converter
Begin Queue 1
Result 0
BQ2
End of Queue 1
Begin Queue 2
0x27E (ccw63)1
End of Queue 2
Channel Select,
Sample, Hold,
and
Analog to Digital
Conversion
Result 63
0
P BYP IST
CHAN
P = Pause After Conversion
BYP = Bypass Buffer Amplifier
IST = Input Sample Time
CHAN = Channel Number
and End_of_Queue Code
10-bit Conversion
Command Word
(CCW) Format
15 Address Offsets
56
0x280-0x2FF1
Result
Right Justified, Unsigned Result Format
0 0 0 0 0 0
0
S
9 10
15
0 0 0 0 0 0
Result
Left Justified, Signed Result Format
0
9 10
0x300-0x37F1
S = Sign bit
15
Result
0 0 0 0 0 0
Left Justified, Unsigned Result Format
0x380-0x3FF1
10-bit Result is
Software Readable
in 3 Different 16-bit Formats
Note 1: These offsets must be added to the module base address: A = 0x30 4800 or B = 0x30 4C00.
Figure 13-15. QADC64E Conversion Queue Operation
To prepare the QADC64E for a scan sequence, the software writes to the CCW table to specify the desired
channel conversions. The software also establishes the criteria for initiating the queue execution by
programming the queue operating mode. The queue operating mode determines what type of trigger event
causes queue execution to begin. A “trigger event” is used to refer to any of the ways to cause the
QADC64E to begin executing the CCWs in a queue or sub-queue. An “external trigger” is only one of the
possible “trigger events.”
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QADC64E Legacy Mode Operation
A scan sequence may be initiated by the following:
• A software command
• Expiration of the periodic/interval timer
• External trigger signal
• External gated signal (queue 1 only)
The software also specifies whether the QADC64E is to perform a single pass through the queue or is to
scan continuously. When a single-scan mode is selected, the software selects the queue operating mode
and sets the single-scan enable bit. When a continuous-scan mode is selected, the queue remains active in
the selected queue operating mode after the QADC64E completes each queue scan sequence.
During queue execution, the QADC64E reads each CCW from the active queue and executes conversions
in three stages:
• Initial sample - During initial sample, a buffered version of the selected input channel is connected
to the sample capacitor at the input of the sample buffer amplifier.
• Final sample - During the final sample period, the sample buffer amplifier is bypassed, and the
multiplexer input charges the sample capacitor directly. Each CCW specifies a final input sample
time of 2, 4, 8, or 16 cycles.
• Resolution - When an analog-to-digital conversion is complete, the result is written to the
corresponding location in the result word table. The QADC64E continues to sequentially execute
each CCW in the queue until the end of the queue is detected or a pause bit is found in a CCW.
When the pause bit is set in the current CCW, the QADC64E stops execution of the queue until a new
trigger event occurs. The pause status flag bit is set, which may cause an interrupt to notify the software
that the queue has reached the pause state. After the trigger event occurs, the paused state ends and the
QADC64E continues to execute each CCW in the queue until another pause is encountered or the end of
the queue is detected.
The following indicate the end-of-queue condition:
• The CCW channel field is programmed with 63 (0x3F) to specify the end of the queue
• The end-of-queue 1 is implied by the beginning of queue 2, which is specified in the BQ2 field in
QACR2
• The physical end of the queue RAM space defines the end of either queue
When any of the end-of-queue conditions is recognized, a queue completion flag is set, and if enabled, an
interrupt is issued to the software.
The following situations prematurely terminate queue execution:
• Because queue 1 is higher in priority than queue 2, when a trigger event occurs on queue 1 during
queue 2 execution, the execution of queue 2 is suspended by aborting the execution of the CCW in
progress, and the queue 1 execution begins. When queue 1 execution is completed, queue 2
conversions restart with the first CCW entry in queue 2 or the first CCW of the queue 2 sub-queue
being executed when queue 2 was suspended. Alternately, conversions can restart with the aborted
queue 2 CCW entry. The RESUME bit in QACR2 allows the software to select where queue 2
begins after suspension. By choosing to re-execute all of the suspended queue 2 queue and
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13-29
QADC64E Legacy Mode Operation
•
•
•
•
sub-queue CCWs, all of the samples are guaranteed to have been taken during the same scan pass.
However, a high trigger event rate for queue 1 can prohibit the completion of queue 2. If this
occurs, the software may choose to begin execution of queue 2 with the aborted CCW entry.
Software can change the queue operating mode to disabled mode. Any conversion in progress for
that queue is aborted. Putting a queue into the disabled mode does not power down the converter.
Software can change the queue operating mode to another valid mode. Any conversion in progress
for that queue is aborted. The queue restarts at the beginning of the queue, once an appropriate
trigger event occurs.
For low power operation, software can set the stop mode bit to prepare the module for a loss of
clocks. The QADC64E aborts any conversion in progress when the stop mode is entered.
When the freeze enable bit is set by software and the IMB3 internal FREEZE line is asserted, the
QADC64E freezes at the end of the conversion in progress. When internal FREEZE is negated, the
QADC64E resumes queue execution beginning with the next CCW entry. Refer to Section 13.5.7,
“Configuration and Control Using the IMB3 Interface” for more information.
MSB
LSB
0
1
Field
2
3
—
Reset
4
5
6
7
P
BYP
8
9
10
11
IST
12
13
14
15
CHAN[5:0]
Unaffected
Addr
0x30 4A00 – 0x30 4A7F, 0x30 4E00 – 0x30 4E7F
Figure 13-16. Conversion Command Word Table (CCW)
Table 13-18. CCW Bit Descriptions
Bits
Name
Description
0:5
—
Reserved
6
P
Pause. The pause bit allows the creation of sub-queues within queue 1 and queue 2. The
QADC64E performs the conversion specified by the CCW with the pause bit set, and then the
queue enters the pause state. Another trigger event causes execution to continue from the pause
to the next CCW.
0 Do not enter the pause state after execution of the current CCW.
1 Enter the pause state after execution of the current CCW.
7
BYP
Sample amplifier bypass. Setting BYP enables the amplifier bypass mode for a conversion, and
subsequently changes the timing. Refer to Section 13.4.1.2, “Amplifier Bypass Mode Conversion
Timing,” for more information.
0 Amplifier bypass mode disabled.
1 Amplifier bypass mode enabled.
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QADC64E Legacy Mode Operation
Table 13-18. CCW Bit Descriptions (continued)
Bits
Name
Description
8:9
IST
Input sample time. The IST field specifies the length of the sample window. Longer sample times
permit more accurate A/D conversions of signals with higher source impedances, especially if
BYP = 1.
00 QCKL period x 2
01 QCKL period x 4
10 QCKL period x 8
11 QCKL period x 16
10:15
CHAN
Channel number. The CHAN field selects the input channel number corresponding to the analog
input signal to be sampled and converted. The analog input signal channel number assignments
and the signal definitions vary depending on whether the QADC64E is operating in multiplexed
or non-multiplexed mode. The queue scan mechanism sees no distinction between an internally
or externally multiplexed analog input.
If CHAN specifies a reserved channel number (channels 32 to 47) or an invalid channel number
(channels 4 to 31 in non-multiplexed mode), the low reference level (VRL) is converted.
Programming the channel field to channel 63 indicates the end of the queue. Channels 60 to 62
are special internal channels. When one of these channels is selected, the sample amplifier is
not used. The value of VRL, VRH, or (VRH – VRL)/2 is placed directly into the converter.
Programming the input sample time to any value other than two for one of the internal channels
has no benefit except to lengthen the overall conversion time.
Table 13-19 shows the channel number assignments for non-multiplexed mode. Table 13-20
shows the channel number assignments for multiplexed mode.
Table 13-19. Non-Multiplexed Channel Assignments and Signal Designations
Non-multiplexed Input Signals
Channel Number in CHAN
Port Signal
Name
Analog Signal
Name
Other Functions
Signal Type
(I/O)
Binary
Decimal
PQB0
PQB1
PQB2
PQB3
AN0
AN1
AN2
AN3
—
—
—
—
I
I
I
I
000000
000001
000010
000011
0
1
2
3
—
—
PQB4
PQB5
—
—
AN48
AN49
Invalid
Reserved
—
—
—
—
I
I
000100 to 011111
10XXXX
110000
110001
4 to 31
32 to 47
48
49
Port Signal
Name
Analog Signal
Name
Other Functions
Signal Type
(I/O)
Binary
Decimal
PQB6
PQB7
PQA0
PQA1
AN50
AN51
AN52
AN53
—
—
—
—
I
I
I/O
I/O
110010
110011
110100
110101
50
51
52
53
PQA2
PQA3
PQA4
PQA5
AN54
AN55
AN56
AN57
—
—
—
—
I/O
I/O
I/O
I/O
110110
110111
111000
111001
54
55
56
57
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QADC64E Legacy Mode Operation
Table 13-19. Non-Multiplexed Channel Assignments and Signal Designations (continued)
Non-multiplexed Input Signals
Channel Number in CHAN
PQA6
PQA7
—
—
AN58
AN59
VRL
VRH
—
—
—
—
I/O
I/O
I
I
111010
111011
111100
111101
58
59
60
61
—
—
—
—
(VRH – VRL)/2
End of Queue Code
—
—
111110
111111
62
63
Table 13-20. Multiplexed Channel Assignments and Signal Designations
Multiplexed Input Signals
Channel Number in CHAN
Port Signal
Name
Analog Signal
Name
Other Functions
Signal Type
(I/O)
Binary
Decimal
PQB0
PQB1
PQB2
PQB3
ANw
ANx
ANy
ANz
—
—
—
—
I
I
I
I
00xxx0
00xxx1
01xxx0
01xxx1
0 to 14 even
1 to 15 odd
16 to 30 even
17 to 31 odd
—
PQB4
PQB5
PQB6
—
AN48
AN49
AN50
Reserved
—
—
—
—
I
I
I
10xxxx
110000
110001
110010
32 to 47
48
49
50
PQB7
PQA0
PQA1
PQA2
AN51
—
—
—
—
MA0
MA1
MA2
I
I/O
I/O
I/O
110011
110100
110101
110110
51
52
53
54
PQA3
PQA4
PQA5
PQA6
AN55
AN56
AN57
AN58
—
—
—
—
I/O
I/O
I/O
I/O
110111
111000
111001
111010
55
56
57
58
PQA7
—
—
—
AN59
VRL
VRH
—
—
—
—
(VRH -VRL)/2
I/O
I
I
—
111011
111100
111101
111110
59
60
61
62
—
—
End of Queue Code
—
111111
63
The channel field is programmed for channel 63 to indicate the end of the queue. Channels 60 to 62 are
special internal channels. When one of the special channels is selected, the sampling amplifier is not used.
The value of VRL, VRH, or (VRH - VRL)/2 is placed directly onto the converter. Also for the internal
special channels, programming any input sample time other than two has no benefit except to lengthen the
overall conversion time.
13.3.10 Result Word Table
The result word table is a RAM, 64 words long and 10 bits wide. An entry is written by the QADC64E
after completing an analog conversion specified by the corresponding CCW table entry. Software can read
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QADC64E Legacy Mode Operation
or write the result word table, but in normal operation, the software reads the result word table to obtain
analog conversions from the QADC64E. Unimplemented bits are read as zeros, and write operations do
not have any effect. See Figure 13-17 for a diagram of the result word table
While there is only one result word table, the data can be accessed in three different data formats:
• Right justified in the 16-bit word, with zeros in the higher order unused bits
• Left justified, with the most significant bit inverted to form a sign bit, and zeros in the unused lower
order bits
• Left justified, with zeros in the lower order unused bits
The left justified, signed format corresponds to a half-scale, offset binary, two’s complement data format.
The data is routed onto the IMB3 according to the selected format. The address used to access the table
determines the data alignment format. All write operations to the result word table are right justified.
MSB
0
LSB
1
2
Field
SRESET
3
4
5
6
7
8
9
10
11
—
RESULT
0000_00
Undefined
Addr
12
13
14
13
14
15
0x30 4A80–4AFF (RJURR_A); 0x30 4E80–4EFF (RJURR_B)
Figure 13-17. Right Justified, Unsigned Result Format (RJURR)
MSB
LSB
0
Field
1
2
3
4
S1
5
6
7
8
9
10
11
12
RESULT
—
Undefined
SRESET
Addr
15
00_0000
0x30 4B00–4B7F (LJSRR_A); 0x30 4F00–4F7F (LJSRR_B)
Figure 13-18. Left Justified, Signed Result Format (LJSRR)
1
S = Sign bit.
MSB
0
LSB
1
Field
SRESET
Addr
2
3
4
5
6
7
8
9
10
11
12
13
RESULT
—
Undefined
00_0000
14
15
0x30 4B80–4BFF (LJURR_A); 0x30 4F80–4FFF (LJURR_B)
Figure 13-19. Left Justified, Unsigned Result Register (LJURR)
The three result data formats are produced by routing the RAM bits onto the data bus. The software
chooses among the three formats by reading the result at the memory address which produces the desired
data alignment.
The result word table is read/write accessible by software. During normal operation, application software
only needs to read the result table. Write operations to the table may occur during test or debug breakpoint
operation. When locations in the CCW table are not used by an application, software could use the
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QADC64E Legacy Mode Operation
corresponding locations in the result word table as scratch pad RAM, remembering that only 10 bits are
implemented. The result alignment is only implemented for software read operations. Since write
operations are not the normal use for the result registers, only one write data format is supported, which is
right justified data.
NOTE
Some write operations, like bit manipulation, may not operate as expected
because the hardware cannot access a true 16-bit value.
13.4
Analog Subsystem
This section describes the QADC64E analog subsystem, which includes the front-end analog multiplexer
and analog-to-digital converter.
13.4.1
Analog-to-Digital Converter Operation
The analog subsystem consists of the path from the input signals to the A/D converter block. Signals from
the queue control logic are fed to the multiplexer and state machine. The end of convert (EOC) signal and
the successive-approximation register (SAR) are the result of the conversion. Figure 13-20 shows a block
diagram of the QADC64E analog subsystem.
BIAS
STOP
2
Final
.
..
AN44
Buffer
+
AN59
Decoder
-
Sample
CAP Array
Equals CDAC
Buffer
AMP
COMP.
+
6 Sample
Zero
CONV.
VRH
RDAC
(7 BIT)
VRL
7
CDAC
(4 BIT)
CRH
CRL
4 (one is offset)
CHAN
IST
REF
CCW Buffer
State Mach, SAR and SAR Buffer
WCCW EOS/EOC CLK
Result
10
Data Bus
Standard Converter Interface
Figure 13-20. QADC64E Analog Subsystem Block Diagram
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13.4.1.1
Conversion Cycle Times
Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial
sample time refers to the time during which the selected input channel is coupled through the buffer
amplifier to the sample capacitor. This buffer is used to quickly reproduce its input signal on the sample
capacitor and minimize charge sharing errors. During the final sampling period the amplifier is bypassed,
and the multiplexer input charges the sample capacitor array directly for improved accuracy. During the
resolution period, the voltage in the sample capacitor is converted to a digital value and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 6, 8, or 16 QCLK cycles,
depending on the value of the IST field in the CCW. Resolution time is ten QCLK cycles.
Therefore, conversion time requires a minimum of 14 QCLK clocks (7 µs with a 2.0-MHz QCLK). If the
maximum final sample time period of 16 QCLKs is selected, the total conversion time is 28 QCLKs or 14
µs (with a 2.0-MHz QCLK)
Figure 13-21 illustrates the timing for conversions.
BUFFER Final Sample
Time
Sample
N cycles:
Time
2 cycles
(2, 4, 8, 16)
Resolution
Time
10 cycles
QCLK
Sample TIME
Successive Approximation Resolution
Sequence
Figure 13-21. Conversion Timing
13.4.1.2
Amplifier Bypass Mode Conversion Timing
If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) bit in the
CCW, the timing changes to that shown in Figure 13-22. The buffered sample time is eliminated, reducing
the potential conversion time by two QCLKs. However, due to internal RC effects, a minimum final
sample time of four QCLKs must be allowed. This results in no savings of QCLKs. When using the bypass
mode, the external circuit should be of low source impedance, typically less than 10 kΩ. Also, the loading
effects of the external circuitry by the QADC64E need to be considered, since the benefits of the sample
amplifier are not present.
NOTE
Because of internal RC time constants, a sample time of two QCLKs in
bypass mode for high frequency operation is not recommended.
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Sample
Time
N cycles:
(2, 4, 8, 16)
Resolution
Time
10 cycles
Sample
Time
Successive Approximation Resolution
Sequence
QCLK
Figure 13-22. Bypass Mode Conversion Timing
13.4.2
Channel Decode and Multiplexer
The internal multiplexer selects one of the 16 analog input signals for conversion. The selected input is
connected to the sample buffer amplifier. The multiplexer also includes positive and negative stress
protection circuitry, which prevents deselected channels from affecting the selected channel when current
is injected into the deselected channels. Refer to Appendix F, “Electrical Characteristics,” for specific
current levels.
13.4.3
Sample Buffer Amplifier
The sample buffer is used to raise the effective input impedance of the A/D converter, so that external
components (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is
buffered onto the sample capacitor to reduce crosstalk between channels.
13.4.4
Digital-to-Analog Converter (DAC) Array
The digital to analog converter (DAC) array consists of binary-weighted capacitors and a resistor-divider
chain. The reference voltages, VRH and VRL, are used by the DAC to perform ratiometric conversions. The
DAC also converts the following three internal channels:
• VRH — Reference voltage high
• VRL — Reference voltage low
• (VRH – VRL)/2 — Reference voltage
The DAC array serves to provide a mechanism for the successive approximation A/D conversion.
Resolution begins with the most significant bit (MSB) and works down to the least significant bit (LSB).
The switching sequence is controlled by the comparator and successive-approximation register (SAR)
logic.
• Sample capacitor — The sample capacitor is employed to sample and hold the voltage to be
converted.
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13.4.5
Comparator
The comparator is used during the approximation process to sense whether the digitally selected
arrangement of the DAC array produces a voltage level higher or lower than the sampled input. The
comparator output feeds into the SAR which accumulates the A/D conversion result sequentially,
beginning with the MSB.
13.4.6
Bias
The bias circuit is controlled by the STOP signal to power-up and power-down all the analog circuits.
13.4.7
Successive Approximation Register
The input of the successive approximation register (SAR) is connected to the comparator output. The SAR
sequentially receives the conversion value one bit at a time, starting with the MSB. After accumulating the
10 bits of the conversion result, the SAR data is transferred to the appropriate result location, where it may
be read from the IMB3 by user software.
13.4.8
State Machine
The state machine receives the QCLK, RST, STOP, BYP, IST, CHAN[5:0], and START CONV signals,
from which it generates all timing to perform an A/D conversion. The start convert (START CONV) signal
indicates to the A/D converter that the desired channel has been sent to the MUX. IST indicates the desired
sample time. BYP indicates whether to bypass the sample amplifier. The end of conversion (EOC) signal,
notifies the queue control logic that a result is available for storage in the result RAM.
13.5
Digital Subsystem
The digital control subsystem includes the control logic to sequence the conversion activity, the clock and
periodic/interval timer, control and status registers, the conversion command word table RAM, and the
result word table RAM.
The central element for control of the QADC64E conversions is the 64-entry CCW table. Each CCW
specifies the conversion of one input channel. Depending on the application, one or two queues can be
established in the CCW table. A queue is a scan sequence of one or more input channels. By using a pause
mechanism, sub-queues can be created in the two queues. Each queue can be operated using one of several
different scan modes. The scan modes for queue 1 and queue 2 are programmed in QACR1 and QACR2
(control registers 1 and 2). Once a queue has been started by a trigger event (any of the ways to cause the
QADC64E to begin executing the CCWs in a queue or sub-queue), the QADC64E performs a sequence
of conversions and places the results in the result word table.
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13.5.1
Queue Priority
Queue 1 has priority over queue 2 execution. The following cases show the conditions under which queue
1 asserts its priority:
• When a queue is not active, a trigger event for queue 1 or queue 2 causes the corresponding queue
execution to begin.
• When queue 1 is active and a trigger event occurs for queue 2, queue 2 cannot begin execution until
queue 1 reaches completion or the paused state. The status register records the trigger event by
reporting the queue 2 status as trigger pending. Additional trigger events for queue 2, which occur
before execution can begin, are captured as trigger overruns.
• When queue 2 is active and a trigger event occurs for queue 1, the current queue 2 conversion is
aborted. The status register reports the queue 2 status as suspended. Any trigger events occurring
for queue 2 while queue 2 is suspended are captured as trigger overruns. Once queue 1 reaches the
completion or the paused state, queue 2 begins executing again. The programming of the RESUME
bit in QACR2 determines which CCW is executed in queue 2. Refer to Section 13.3.7, “Control
Register 2 (QACR2)” for more information.
• When simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and
the queue 2 status is changed to trigger pending.
13.5.2
Paused Sub-Queues
The pause feature can be used to divide queue 1 and/or queue 2 into multiple sub-queues. A sub-queue is
defined by setting the pause bit in the last CCW of the sub-queue.
Figure 13-23 shows the CCW format and an example of using pause to create sub-queues. Queue 1 is
shown with four CCWs in each sub-queue and queue 2 has two CCWs in each sub-queue.
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Conversion Command Word
(CCW) Table
00
P
0
0
0
1
0
0
0
1
0
0
1
0
P
1
63 0
00
BEGIN Queue 1
PAUSE
PAUSE
Channel
Select,
Sample,
P
0
0
BQ2 0
1
0
1
Result Word Table
Hold, And
END OF Queue 1
BEGIN Queue 2
PAUSE
A/D
Conversion
PAUSE
PAUSE
PAUSE
END OF Queue 2
63
QADC64E CQP
Figure 13-23. QADC64E Queue Operation with Pause
The queue operating mode selected for queue 1 determines what type of trigger event causes the execution
of each of the sub-queues within queue 1. Similarly, the queue operating mode for queue 2 determines the
type of trigger event required to execute each of the sub-queues within queue 2.
For example, when the external trigger rising edge continuous-scan mode is selected for queue 1, and there
are six sub-queues within queue 1, a separate rising edge is required on the external trigger signal after
every pause to begin the execution of each sub-queue (refer to Figure 13-23). Refer to Section 13.5.4,
“Scan Modes,” for information on different scan modes.
The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each
sub-queue. Once a sub-queue is initiated, each CCW is executed sequentially until the last CCW in the
sub-queue is executed and the pause state is entered. Execution can only continue with the next CCW,
which is the beginning of the next sub-queue. A sub-queue cannot be executed a second time before the
overall queue execution has been completed. Refer to Section 13.3.7, “Control Register 2 (QACR2),” for
more information.
Trigger events which occur during the execution of a sub-queue are ignored, except that the trigger overrun
flag is set. When a continuous-scan mode is selected, a trigger event occurring after the completion of the
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last sub-queue (after the queue completion flag is set), causes the execution to continue with the first
sub-queue, starting with the first CCW in the queue.
When the QADC64E encounters a CCW with the pause bit set, the queue enters the paused state after
completing the conversion specified in the CCW with the pause bit. The pause flag is set and a pause
software interrupt may optionally be issued. The status of the queue is shown to be paused, indicating
completion of a sub-queue. The QADC64E then waits for another trigger event to again begin execution
of the next sub-queue.
13.5.3
Boundary Conditions
The following are queue operation boundary conditions:
• The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code. The queue becomes
active and the first CCW is read. The end-of-queue is recognized, the completion flag is set, and
the queue becomes idle. A conversion is not performed.
• BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger event occurs on
queue 2. Refer to Section 13.3.7, “Control Register 2 (QACR2),” for more information on BQ2.
The end-of-queue condition is recognized, a conversion is performed, the completion flag is set,
and the queue becomes idle.
• BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0, the end-of-queue
condition is recognized, the completion flag is set, and the queue becomes idle. A conversion is not
performed.
• BQ2 is set beyond the end of the CCW table (64 – 127) and a trigger event occurs on queue 2. The
end-of-queue condition is recognized immediately, the completion flag is set, and the queue
becomes idle. A conversion is not performed.
NOTE
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in the QADC64E behavior. For example, if BQ2
is set to CCW0, CCW0 contains the EOQ code, and a trigger event occurs
on queue 1, the QADC64E reads CCW0 and detects both end-of-queue
conditions. The completion flag is set and queue 1 becomes idle.
Boundary conditions also exist for combinations of pause and end-of-queue. One case is when a pause bit
is in one CCW and an end-of-queue condition is in the next CCW. The conversion specified by the CCW
with the pause bit set completes normally. The pause flag is set. However, since the end-of-queue condition
is recognized, the completion flag is also set and the queue status becomes idle, not paused. Examples of
this situation include:
• The pause bit is set in CCW5 and the EOQ code is in CCW6
• The pause is set in CCW63
• During queue 1 operation, the pause bit is set in CCW20 and BQ2 points to CCW21
Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue
condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized
simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW
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and the pause flag is not set. The QADC64E sets the completion flag and the queue status becomes idle.
Examples of this situation are:
• The pause bit is set in CCW10 and EOQ is programmed into CCW10
• During queue 1 operation, the pause bit set in CCW32, which is also BQ2
13.5.4
Scan Modes
The QADC64E queuing mechanism allows the application to utilize different requirements for
automatically scanning input channels.
In single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. In
continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are
executed. The possible modes are:
• Disabled and reserved mode
• Single-scan modes
— Software initiated single-scan mode
— External trigger single-scan mode
— External gated single-scan mode
— Periodic/Interval timer single-scan mode
• Continuous-scan modes
— Software initiated continuous-scan mode
— External trigger continuous-scan mode
— External gated continuous-scan mode
— Periodic/Interval timer continuous-scan mode
The following paragraphs describe single-scan and continuous-scan operations.
13.5.4.1
Disabled Mode
When the disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution.
When both queue 1 and queue 2 are disabled, wait states are not encountered for IMB3 accesses of the
RAM. When both queues are disabled, it is safe to change the QCLK prescaler values.
13.5.4.2
Reserved Mode
Reserved mode allows for future mode definitions. When the reserved mode is selected, the queue is not
active. It functions the same as disabled mode.
CAUTION
Do not use a reserved mode. Unspecified operations may result.
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13.5.4.3
Single-Scan Modes
When the application software wants to execute a single pass through a sequence of conversions defined
by a queue, a single-scan queue operating mode is selected. By programming the MQ field in QACR1 or
QACR2, the following modes can be selected:
• Software initiated single-scan mode
• External trigger single-scan mode
• External gated single-scan mode
• Periodic/Interval timer single-scan mode
NOTE
Queue 2 cannot be programmed for external gated single-scan mode.
In all single-scan queue operating modes, the software must also enable the queue to begin execution by
writing the single-scan enable bit to a one in the queue’s control register. The single-scan enable bits, SSE1
and SSE2, are provided for queue 1 and queue 2 respectively.
Until the single-scan enable bit is set, any trigger events for that queue are ignored. The single-scan enable
bit may be set to a one during the write cycle, which selects the single-scan queue operating mode. The
single-scan enable bit is set through software, but will always read as a zero. Once set, writing the
single-scan enable bit to zero has no effect. Only the QADC64E can clear the single-scan enable bit. The
completion flag, completion interrupt, or queue status are used to determine when the queue has
completed.
After the single-scan enable bit is set, a trigger event causes the QADC64E to begin execution with the
first CCW in the queue. The single-scan enable bit remains set until the queue is completed. After the
queue reaches completion, the QADC64E resets the single-scan enable bit to zero. If the single-scan
enable bit is written to a one or a zero by the software before the queue scan is complete, the queue is not
affected. However, if the software changes the queue operating mode, the new queue operating mode and
the value of the single-scan enable bit are recognized immediately. The conversion in progress is aborted
and the new queue operating mode takes effect.
In the software-initiated single-scan mode, the writing of a one to the single-scan enable bit causes the
QADC64E to internally generate a trigger event and the queue execution begins immediately. In the other
single-scan queue operating modes, once the single-scan enable bit is written, the selected trigger event
must occur before the queue can start. The single-scan enable bit allows the entire queue to be scanned
once. A trigger overrun is captured if a trigger event occurs during queue execution in an edge-sensitive
external trigger mode or a periodic/interval timer mode.
In the periodic/interval timer single-scan mode, the next expiration of the timer is the trigger event for the
queue. After the queue execution is complete, the queue status is shown as idle. The software can restart
the queue by setting the single-scan enable bit to a one. Queue execution begins with the first CCW in the
queue.
13.5.4.3.1
Software Initiated Single-Scan Mode
Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated
single-scan mode, and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is
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generated internally and the QADC64E immediately begins execution of the first CCW in the queue. If a
pause occurs, another trigger event is generated internally, and then execution continues without pausing.
The QADC64E automatically performs the conversions in the queue until an end-of-queue condition is
encountered. The queue remains idle until the software again sets the single-scan enable bit. While the time
to internally generate and act on a trigger event is very short, software can momentarily read the status
conditions, indicating that the queue is paused. The trigger overrun flag is never set while in the software
initiated single-scan mode.
The software initiated single-scan mode is useful in the following applications:
• Allows software complete control of the queue execution
• Allows the software to easily alternate between several queue sequences.
13.5.4.3.2
External Trigger Single-Scan Mode
The external trigger single-scan mode is available on both queue 1 and queue 2. The software programs
the polarity of the external trigger edge that is to be detected, either a rising or a falling edge. The software
must enable the scan to occur by setting the single-scan enable bit for the queue.
The first external trigger edge causes the queue to be executed one time. Each CCW is read and the
indicated conversions are performed until an end-of-queue condition is encountered. After the queue is
completed, the QADC64E clears the single-scan enable bit. Software may set the single-scan enable bit
again to allow another scan of the queue to be initiated by the next external trigger edge.
The external trigger single-scan mode is useful when the input trigger rate can exceed the queue execution
rate. Analog samples can be taken in sync with an external event, even though the software is not interested
in data taken from every edge. The software can start the external trigger single-scan mode and get one set
of data, and at a later time, start the queue again for the next set of samples.
When a pause bit is encountered during external trigger single-scan mode, another trigger event is required
for queue execution to continue. Software involvement is not needed to enable queue execution to continue
from the paused state.
13.5.4.3.3
External Gated Single-Scan Mode
The QADC64E provides external gating for queue 1 only. When external gated single-scan mode is
selected, the input level on the associated external trigger signal enables and disables queue execution. The
polarity of the external gated signal is fixed so only a high level opens the gate and a low level closes the
gate. Once the gate is open, each CCW is read and the indicated conversions are performed until the gate
is closed. Software must enable the scan to occur by setting the single-scan enable bit for queue 1. If a
pause in a CCW is encountered, the pause flag will not set, and execution continues without pausing.
While the gate is open, queue 1 executes one time. Each CCW is read and the indicated conversions are
performed until an end-of-queue condition is encountered. When queue 1 completes, the QADC64E sets
the completion flag (CF1) and clears the single-scan enable bit. Software may set the single-scan enable
bit again to allow another scan of queue 1 to be initiated during the next open gate.
If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1
stops, the single-scan enable bit is cleared, and the PF1 bit is set. Software can read the CWPQ1 to
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determine the last valid conversion in the queue. Software must set the single-scan enable bit again and
should clear the PF1 bit before another scan of queue 1 is initiated during the next open gate. The start of
queue 1 is always the first CCW in the CCW table.
Since the condition of the gate is only sampled after each conversion during queue execution, closing the
gate for a period less than a conversion time interval does not guarantee the closure will be captured.
13.5.4.3.4
Periodic/Interval Timer Single-Scan Mode
Both queues can use the periodic/interval timer in a single-scan queue operating mode. The timer interval
can range from 128- to 128-Kbyte QCLK cycles in binary multiples. When the periodic/ interval timer
single-scan mode is selected and the software sets the single-scan enable bit in QACR1 or QACR2, the
timer begins counting. When the time interval elapses, an internal trigger event is created to start the queue
and the QADC64E begins execution with the first CCW.
The QADC64E automatically performs the conversions in the queue until a pause or an end-of-queue
condition is encountered. When a pause occurs, queue execution stops until the timer interval elapses
again, and then queue execution continues. When the queue execution reaches an end-of-queue situation,
the single-scan enable bit is cleared. Software may set the single-scan enable bit again, allowing another
scan of the queue to be initiated by the periodic/interval timer.
The periodic/interval timer generates a trigger event whenever the time interval elapses. The trigger event
may cause the queue execution to continue following a pause, or may be considered a trigger overrun.
Once the queue execution is completed, the single-scan enable bit must be set again to enable the timer to
count again.
Normally only one queue will be enabled for periodic/interval timer single-scan mode and the timer will
reset at the end-of-queue. However, if both queues are enabled for either single-scan or continuous
periodic/interval timer mode, the end-of-queue condition will not reset the timer while the other queue is
active. In this case, the timer will reset when both queues have reached end-of-queue. See Section 13.5.6,
“Periodic / Interval Timer” for a definition of periodic/interval timer reset conditions.
The periodic/interval timer single-scan mode can be used in applications which need coherent results, for
example:
• When it is necessary that all samples are guaranteed to be taken during the same scan of the analog
signals
• When the interrupt rate in the periodic/interval timer continuous-scan mode would be too high
• In sensitive battery applications, where the single-scan mode uses less power than the software
initiated continuous-scan mode
13.5.4.4
Continuous-Scan Modes
When the application software wants to execute multiple passes through a sequence of conversions defined
by a queue, a continuous-scan queue operating mode is selected.
By programming the MQ1 field in QACR1 or the MQ2 field in QACR2, the following software initiated
modes can be selected:
• Software initiated continuous-scan mode
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•
•
•
External trigger continuous-scan mode
External gated continuous-scan mode
Periodic/interval timer continuous-scan mode
When a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control
register does not have any meaning or effect. As soon as the queue operating mode is programmed, the
selected trigger event can initiate queue execution.
In the case of the software-initiated continuous-scan mode, the trigger event is generated internally and
queue execution begins immediately. In the other continuous-scan queue operating modes, the selected
trigger event must occur before the queue can start. A trigger overrun is captured if a trigger event occurs
during queue execution in the external trigger continuous-scan mode and the periodic/interval timer
continuous-scan mode.
After the queue execution is complete, the queue status is shown as idle. Since the continuous-scan queue
operating modes allow the entire queue to be scanned multiple times, software involvement is not needed
to enable queue execution to continue from the idle state. The next trigger event causes queue execution
to begin again, starting with the first CCW in the queue.
NOTE
Coherent samples are guaranteed. The time between consecutive
conversions has been designed to be consistent. However, there is one
exception. For queues that end with a CCW containing EOQ code (channel
63), the last queue conversion to the first queue conversion requires 1
additional CCW fetch cycle. Therefore continuous samples are not coherent
at this boundary.
In addition, the time from trigger to first conversion cannot be guaranteed since it is a function of clock
synchronization, programmable trigger events, queue priorities, and so on.
13.5.4.4.1
Software Initiated Continuous-Scan Mode
When the software initiated continuous-scan mode is programmed, the trigger event is generated
automatically by the QADC64E. Queue execution begins immediately. If a pause is encountered, another
trigger event is generated internally, and then execution continues without pausing. When the
end-of-queue is reached, another internal trigger event is generated, and queue execution begins again
from the beginning of the queue.
While the time to internally generate and act on a trigger event is very short, software can momentarily
read the status conditions, indicating that the queue is idle. The trigger overrun flag is never set while in
the software-initiated continuous-scan mode.
The software initiated continuous-scan mode keeps the result registers updated more frequently than any
of the other queue operating modes. The software can always read the result table to get the latest
converted value for each channel. The channels scanned are kept up to date by the QADC64E without
software involvement. Software can read a result value at any time.
The software initiated continuous-scan mode may be chosen for either queue, but is normally used only
with queue 2. When the software initiated continuous-scan mode is chosen for queue 1, that queue operates
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continuously and queue 2, being lower in priority, never gets executed. The short interval of time between
a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin.
The software initiated continuous-scan mode is a useful choice with queue 2 for converting channels that
do not need to be synchronized to anything, or for the slow-to-change analog channels. Interrupts are
normally not used with the software initiated continuous-scan mode. Rather, the software reads the latest
conversion result from the result table at any time. Once initiated, software action is not needed to sustain
conversions of channel.
13.5.4.4.2
External Trigger Continuous-Scan Mode
The QADC64E provides external trigger signals for both queues. When the external trigger software
initiated continuous-scan mode is selected, a transition on the associated external trigger signal initiates
queue execution. The polarity of the external trigger signal is programmable, so that the software can select
a mode which begins queue execution on the rising or falling edge. Each CCW is read and the indicated
conversions are performed until an end-of-queue condition is encountered. When the next external trigger
edge is detected, the queue execution begins again automatically. Software initialization is not needed
between trigger events.
When a pause bit is encountered in external trigger continuous-scan mode, another trigger event is required
for queue execution to continue. Software involvement is not needed to enable queue execution to continue
from the paused state.
Some applications need to synchronize the sampling of analog channels to external events. There are cases
when it is not possible to use software initiation of the queue scan sequence, since interrupt response times
vary.
13.5.4.4.3
External Gated Continuous-Scan Mode
The QADC64E provides external gating for queue 1 only. When external gated continuous-scan mode is
selected, the input level on the associated external trigger signal enables and disables queue execution. The
polarity of the external gated signal is fixed so a high level opens the gate and a low level closes the gate.
Once the gate is open, each CCW is read and the indicated conversions are performed until the gate is
closed. When the gate opens again, the queue execution automatically begins again from the beginning of
the queue. Software initialization is not needed between trigger events. If a pause in a CCW is encountered,
the pause flag will not set, and execution continues without pausing.
The purpose of external gated continuous-scan mode is to continuously collect digitized samples while the
gate is open and to have the most recent samples available. It is up to the programmer to ensure that the
queue is large enough so that a maximum gate open time will not reach an end-of-queue. However it is
useful to take advantage of a smaller queue in the manner described in the next paragraph.
In the event that the queue completes before the gate closes, a completion flag will be set and the queue
will roll over to the beginning and continue conversions until the gate closes. If the gate remains open and
the completion flag is not cleared, when the queue completes a second time the trigger overrun flag will
be set and the queue will roll-over again. The queue will continue to execute until the gate closes or the
mode is disabled.
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QADC64E Legacy Mode Operation
If the gate closes before queue 1 completes execution, the current CCW completes execution of queue 1
stops and QADC64E sets the PF1 bit to indicate an incomplete queue. Software can read the CWPQ1 to
determine the last valid conversion in the queue. In this mode, if the gate opens again, execution of queue
1 begins again. The start of queue 1 is always the first CCW in the CCW table.
Since the condition of the gate is only sampled after each conversion during queue execution, closing the
gate for a period less than a conversion time interval does not guarantee the closure will be captured.
13.5.4.4.4
Periodic/Interval Timer Continuous-Scan Mode
The QADC64E includes a dedicated periodic/interval timer for initiating a scan sequence on queue 1
and/or queue 2. Software selects a programmable timer interval ranging from 128 to 128 Kbytes times the
QCLK period in binary multiples. The QCLK period is prescaled down from the IMB3 MCU clock.
When a periodic/interval timer continuous-scan mode is selected for queue 1 and/or queue 2, the timer
begins counting. After the programmed interval elapses, the timer generated trigger event starts the
appropriate queue. Meanwhile, the QADC64E automatically performs the conversions in the queue until
an end-of-queue condition or a pause is encountered. When a pause occurs, the QADC64E waits for the
periodic interval to expire again, then continues with the queue. Once end-of-queue has been detected, the
next trigger event causes queue execution to begin again with the first CCW in the queue.
The periodic/interval timer generates a trigger event whenever the time interval elapses. The trigger event
may cause the queue execution to continue following a pause or queue completion, or may be considered
a trigger overrun. As with all continuous-scan queue operating modes, software action is not needed
between trigger events. Since both queues may be triggered by the periodic/interval timer, see
Section 13.5.6, “Periodic / Interval Timer” for a summary of periodic/interval timer reset conditions.
Software enables the completion interrupt when using the periodic/interval timer continuous-scan mode.
When the interrupt occurs, the software knows that the periodically collected analog results have just been
taken. The software can use the periodic interrupt to obtain non-analog inputs as well, such as contact
closures, as part of a periodic look at all inputs.
13.5.5
QADC64E Clock (QCLK) Generation
Figure 13-24 is a block diagram of the clock subsystem. The QCLK provides the timing for the A/D
converter state machine which controls the timing of the conversion. The QCLK is also the input to a
17-stage binary divider which implements the periodic/interval timer. To retain the specified analog
conversion accuracy, the QCLK frequency (FQCLK) must be within the tolerance specified in Appendix F,
“Electrical Characteristics.”
Before using the QADC64E, the software must initialize the prescaler with values that put the QCLK
within the specified range. Though most software applications initialize the prescaler once and do not
change it, write operations to the prescaler fields are permitted.
For software compatibility with earlier versions of QADC64E, the definition of PSL, PSH, and PSA have
been maintained. However, the requirements on minimum time and minimum low time no longer exist.
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QADC64E Legacy Mode Operation
NOTE
A change in the prescaler value while a conversion is in progress is likely to
corrupt the result from any conversion in progress. Therefore, any prescaler
write operation should be done only when both queues are in the disabled
modes.
Reset QCLK
Zero
Detect
5
IMB3 Clock
(FSYS)
5-Bit
Down Counter
5
Load PSH
3
Prescaler Rate Selection
(From Control Register 0):
One’s Complement
Compare
High Time
Cycles (PSH)
Low Time
Cycles (PSL)
QCLK
Clock
Generate
Set QCLK
3
QADC64E Clock
(FSYS/ 2 to FSYS//40 )
2
Input Sample Time
from (CCW)
A/D Converter
State Machine
SAR Control
SAR
10
Binary Counter
27 28 29 210 211212213214 215216217
Queue 1 & 2 Timer
Mode Rate Selection
8
PERIODIC/INTERVAL
Timer Select
2
Periodic / Interval
Trigger Event
for Q1 AND Q2
Figure 13-24. QADC64E Clock Subsystem Functions
To accommodate wide variations of the main MCU clock frequency (IMB3 clock — fSYS), QCLK is
generated by a programmable prescaler which divides the MCU IMB3 clock to a frequency within the
specified QCLK tolerance range. To allow the A/D conversion time to be maximized across the spectrum
of IMB3 clock frequencies, the QADC64E prescaler permits the frequency of QCLK to be software
selectable. It also allows the duty cycle of the QCLK waveform to be programmable.
The software establishes the basic high phase of the QCLK waveform with the PSH (prescaler clock high
time) field in QACR0, and selects the basic low phase of QCLK with the prescaler clock low time (PSL)
field. The combination of the PSH and PSL parameters establishes the frequency of the QCLK.
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QADC64E Legacy Mode Operation
NOTE
The guideline for selecting PSH and PSL is select is to maintain
approximately 50% duty cycle. So for prescaler values less then 16, or PSH
~= PSL. For prescaler values greater than 16 keep PSL as large as possible.
Figure 13-24 shows that the prescaler is essentially a variable pulse width signal generator. A 5-bit down
counter, clocked at the IMB3 clock rate, is used to create both the high phase and the low phase of the
QCLK signal. At the beginning of the high phase, the 5-bit counter is loaded with the 5-bit PSH value.
When the zero detector finds that the high phase is finished, the QCLK is reset. A 3-bit comparator looks
for a one’s complement match with the 3-bit PSL value, which is the end of the low phase of the QCLK.
The PSA bit was maintained for software compatibility, but has no effect on QADC64E.
The following equations define QCLK frequency:
High QCLK Time = (PSH + 1) ÷ fSYS
Low QCLK Time = (PSL + 1) ÷ fSYS
FQCLK= 1 ÷ (High QCLK Time + Low QCLK Time)
Where:
• PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
• PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
• fSYS = IMB3 clock frequency
• FQCLK = QCLK frequency
The following are equations for calculating the QCLK high/low phases in Example 1:
High QCLK Time = (19 + 1) ÷ 56 x 106 = 357 ns
Low QCLK Time = (7 + 1) ÷ 56 x 106 = 143 ns
FQCLK = 1/(357 + 143) = 2 MHz
The following are equations for calculating the QCLK high/low phases in Example 2:
High QCLK Time = (11 + 1) ÷ 40 x 106 = 300 ns
Low QCLK Time = (7 + 1) ÷ 40 x 106 = 200 ns
FQCLK = 1/(300 + 200) = 2 MHz
The following are equations for calculating the QCLK high/low phases in Example 3:
High QCLK Time = (7 + 1) ÷ 32 x 106 = 250 ns
Low QCLK Time = (7 + 1) ÷ 32 x 106 = 250 ns
FQCLK = 1/(250 + 250) = 2 MHz
Figure 13-25 and Table 13-21 show examples of QCLK programmability. The examples include
conversion times based on the following assumption:
• Input sample time is as fast as possible (IST = 0, 2 QCLK cycles).
Figure 13-25 and Table 13-21 also show the conversion time calculated for a single conversion in a queue.
For other MCU IMB3 clock frequencies and other input sample times, the same calculations can be made.
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QADC64E Legacy Mode Operation
IMB3 CLOCK
FSYS
QCLK EXAMPLES
56 MHz EX1
40 MHz EX2
32 MHz EX3
30 CYCLES
QADC64E QCLK EX
Figure 13-25. QADC64E Clock Programmability Examples
Table 13-21. QADC64E Clock Programmability
Control Register 0 Information
Input Sample Time (IST) =0b00
Example
Number
Frequency
PSH
PSA
PSL
QCLK
(MHz)
Conversion Time
(µs)
1
56 MHz
19
0
7
2.0
7.0
2
40 MHz
11
0
7
2.0
7.0
3
32 MHz
7
0
7
2.0
7.0
NOTE
PSA is maintained for software compatibility but has no functional benefit
to this version of the module.
The MCU IMB3 clock frequency is the basis of the QADC64E timing. The QADC64E requires that the
IMB3 clock frequency be at least twice the QCLK frequency. The QCLK frequency is established by the
combination of the PSH and PSL parameters in QACR0. The 5-bit PSH field selects the number of IMB3
clock cycles in the high phase of the QCLK wave. The 3-bit PSL field selects the number of IMB3 clock
cycles in the low phase of the QCLK wave.
Example 1 in Table 13-21 shows that when the PSH = 19, the QCLK remains high for 20 cycles if the
IMB3 clock and with PSL = 7 the QCLK remains low for 8 IMB3 clock cycles. Example 2 shows that
when PSH = 11, QCLK is high for 12 IMB3 clock cycles and with PSL = 7, QCLK is low for 8 IMB3
clock cycles. Finally, example 3 shows that with PSH = 7 and PSL = 7, QCLK alternates between high and
low every 8 IMB3 cycles.
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QADC64E Legacy Mode Operation
13.5.6
Periodic / Interval Timer
The on-chip periodic/interval timer can be used to generate trigger events at a programmable interval,
initiating execution of queue 1 and/or queue 2. The periodic/interval timer stays reset under the following
conditions:
• Both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval
timer
• IMB3 system reset or the master reset is asserted
• Stop mode is selected
• Freeze mode is selected
NOTE
Interval timer single-scan mode does not use the periodic/interval timer
until the single-scan enable bit is set.
The following two conditions will cause a pulsed reset of the periodic/interval timer during use:
• A queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue
2 is already using the timer
• A queue 2 operating mode change to a mode which uses the periodic/interval timer, provided queue
1 is not in a mode which uses the periodic/interval timer
• Roll over of the timer
During the low power stop mode, the periodic timer is held in reset. Since low power stop mode causes
QACR1 and QACR2 to be reset to zero, a valid periodic or interval timer mode must be written after stop
mode is exited to release the timer from reset.
When the IMB3 internal FREEZE line is asserted and a periodic or interval timer mode is selected, the
timer counter is reset after the conversion in progress completes. When the periodic or interval timer mode
has been enabled (the timer is counting), but a trigger event has not been issued, the freeze mode takes
effect immediately, and the timer is held in reset. When the internal FREEZE line is negated, the timer
counter starts counting from the beginning. Refer to Section 13.5.7, “Configuration and Control Using the
IMB3 Interface,” for more information.
13.5.7
Configuration and Control Using the IMB3 Interface
The QADC64E module communicates with other microcontroller modules via the IMB3. The QADC64E
bus interface unit (BIU) coordinates IMB3 activity with internal QADC64E bus activity. This section
describes the operation of the BIU, IMB3 read/write accesses to QADC64E memory locations, module
configuration, and general-purpose I/O operation.
13.5.7.1
QADC64E Bus Interface Unit
The BIU is designed to act as a slave device on the IMB3. The BIU has the following functions:
• Respond with the appropriate bus cycle termination
• Supply IMB3 interface timing to all internal module signals
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QADC64E Legacy Mode Operation
BIU components consist of:
• IMB3 buffers
• Address match and module select logic
• The BIU state machine
• Clock prescaler logic
• Data bus routing logic
• Interface to the internal module data bus
NOTE
Normal accesses from the IMB3 to the QADC64E require two clocks.
However, if the CPU tries to access table locations while the QADC64E is
accessing them, the QADC64E produces IMB3 wait states. From one to
four IMB3 wait states may be inserted by the QADC64E in the process of
reading and writing.
13.5.7.2
QADC64E Bus Accessing
The QADC64E supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses. Coherency of
results read (ensuring that all results read were taken consecutively in one scan) is not guaranteed. For
example, if a read of two consecutive 16-bit locations in a result area is made, the QADC64E could change
one 16-bit location in the result area between the bus cycles. There is no holding register for the second
16-bit location. All read and write accesses that require more than one 16-bit access to complete occur as
two or more independent bus cycles. Depending on bus master protocol, these accesses could include
misaligned and 32-bit accesses.
Figure 13-26 shows the three bus cycles which are implemented by the QADC64E. The following
paragraphs describe how the three types of accesses are used, including misaligned 16-bit and 32-bit
accesses.
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QADC64E Legacy Mode Operation
W
Intermodule Bus
QADC Location
R
W
R
Byte 0
Byte 1
Byte 0
Byte 1
8-bit Access of an Even Address (ISIZ = 01, A0 = 0)
W
Intermodule Bus
QADC Location
R
W
R
Byte 0
Byte 1
Byte 0
Byte 1
8-bit Access of an Odd Address (ISIZ = 01, A0 = 1; OR ISIZ = 10, A0 = 1)
W
Intermodule Bus
QADC Location
R
W
R
BYTE 0
BYTE 1
BYTE 0
BYTE 1
16-Bit Aligned Access (ISIZ = 10, A0 = 0)
QADC64E Bus CYC ACC
Figure 13-26. Bus Cycle Accesses
Byte access to an even address of a QADC64E location is shown in the top illustration of Figure 13-26. In
the case of write cycles, byte 1 of the register is not disturbed. In the case of a read cycle, the QADC64E
provides both byte 0 and byte 1.
Byte access to an odd address of a QADC64E location is shown in the center illustration of Figure 13-26.
In the case of write cycles, byte 0 of the register is not disturbed. In the case of read cycles, the QADC64E
provides both byte 0 and byte 1.
16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest illustration of
Figure 13-26. The full 16 bits of data is written to and read from the QADC64E location with each access.
16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit QADC64E
locations is accessed. The first bus cycle is treated by the QADC64E as an 8-bit read or write of an odd
address. The second cycle is an 8-bit read or write of an even address. The QADC64E address space is
organized into 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides
the lower half of one QADC64E location, and the upper half of the following QADC64E location.
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13-53
QADC64E Legacy Mode Operation
32-bit accesses to an even address require two bus cycles to complete the access, and two full 16-bit
QADC64E locations are accessed. The first bus cycle reads or writes the addressed 16-bit QADC64E
location and the second cycle reads or writes the following 16-bit location.
32-bit accesses to an odd address require three bus cycles. Portions of three different QADC64E locations
are accessed. The first bus cycle is treated by the QADC64E as an 8-bit access of an odd address, the
second cycle is a 16-bit aligned access, and the third cycle is an 8-bit access of an even address. The
QADC64E address space is organized into 16-bit even address locations, so a 32-bit read or write of an
odd address provides the lower half of one QADC64E location, the full 16-bit content of the following
QADC64E location, and the upper half of the third QADC64E location.
13.6
Trigger and Queue Interaction Examples
This section contains examples describing queue priority and conversion timing schemes.
13.6.1
Queue Priority Schemes
Since there are two conversion command queues and only one A/D converter, there is a priority scheme
to determine which conversion is to occur. Each queue has a variety of trigger events that are intended to
initiate conversions, and they can occur asynchronously in relation to each other and other conversions in
progress. For example, a queue can be idle awaiting a trigger event, a trigger event can have occurred but
the first conversion has not started, a conversion can be in progress, a pause condition can exist awaiting
another trigger event to continue the queue, and so on.
The following paragraphs and figures outline the prioritizing criteria used to determine which conversion
occurs in each overlap situation.
NOTE
The situations in Figure 13-27 through Figure 13-45 are labeled S1 through
S19. In each diagram, time is shown increasing from left to right. The
execution of queue 1 and queue 2 (Q1 and Q2) is shown as a string of
rectangles representing the execution time of each CCW in the queue. In
most of the situations, there are four CCWs (labeled C1 to C4) in both queue
1 and queue 2. In some of the situations, CCW C2 is presumed to have the
pause bit set, to show the similarities of pause and end-of-queue as
terminations of queue execution.
Trigger events are described in Table 13-22.
Table 13-22. Trigger Events
Trigger
Events
T1
Events that trigger queue 1 execution (external trigger, software initiated single-scan
enable bit, or completion of the previous continuous loop)
T2
Events that trigger queue 2 execution (external trigger, software initiated single-scan
enable bit, timer period/interval expired, or completion of the previous continuous loop)
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QADC64E Legacy Mode Operation
When a trigger event causes a CCW execution in progress to be aborted, the aborted conversion is shown
as a ragged end of a shortened CCW rectangle.
The situation diagrams also show when key status bits are set. Table 13-23 describes the status bits.
Table 13-23. Status Bits
Bit
Function
CF Flag
Set when the end of the queue is reached
PF Flag
Set when a queue completes execution up through a pause bit
Trigger Overrun
Error (TOR)
Set when a new trigger event occurs before the queue is finished serving the previous trigger
event
Below the queue execution flows are three sets of blocks that show the status information that is made
available to the software. The first two rows of status blocks show the condition of each queue as:
• Idle
• Active
• Pause
• Suspended (queue 2 only)
• Trigger pending
The third row of status blocks shows the 4-bit QS status register field that encodes the condition of the two
queues. Two transition status cases, QS = 0011 and QS = 0111, are not shown because they exist only very
briefly between stable status conditions.
The first three examples in Figure 13-27 through Figure 13-29 (S1, S2, and S3) show what happens when
a new trigger event is recognized before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1 (Figure 13-27), one trigger event is being recognized on each queue while that queue is still
working on the previously recognized trigger event. The trigger overrun error status bit is set, and
otherwise, the premature trigger event is ignored. A trigger event that occurs before the servicing of the
previous trigger event is completed does not disturb the queue execution in progress.
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13-55
QADC64E Legacy Mode Operation
T1
Q1:
T1
C1
C2
C3
TOR1
C4
T2
CF1
Q2:
T2
C1
C2
C3
TOR2
IDLE
Q1
IDLE
0000
QS
CF2
IDLE
ACTIVE
Q2
C4
IDLE
ACTIVE
1000
0000
0010
0000
QADC S1
Figure 13-27. CCW Priority Situation 1
In situation S2 (Figure 13-27), more than one trigger event is recognized before servicing of a previous
trigger event is complete, the trigger overrun bit is again set, but otherwise, the additional trigger events
are ignored. After the queue is complete, the first newly detected trigger event causes queue execution to
begin again. When the trigger event rate is high, a new trigger event can be seen very soon after completion
of the previous queue, leaving software little time to retrieve the previous results. Also, when trigger events
are occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all.
T1 T1
Q1:
C1
T1
C2
T1
C3
T1
C4
C1
C2
C3
TOR1TOR1TOR1 CF1
C4
CF1
T2
T2
T2
Q2: C1
C2
C3
C4
TOR2TOR2
Q1 IDLE
ACTIVE
IDLE
ACTIVE
IDLE
Q2
QS
IDLE
1000
1000
CF2
0000
ACTIVE
IDLE
0010
0000
QADC S2
Figure 13-28. CCW Priority Situation 2
Situation S3 (Figure 13-28) shows that when the pause feature is in use, the trigger overrun error status bit
is set the same way, and that queue execution continues unchanged.
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QADC64E Legacy Mode Operation
T1
Q1:
T1
C1
T1
C2
T1
C3
TOR1 PF1
T2
Q2:
T2
C1
C4
TOR1 CF1
T2
C2
T2
C3
TOR2 PF2
Q1
IDLE
0000
TOR2 CF2
PAUSE
ACTIVE
1000
0100
IDLE
ACTIVE
PAUSE
IDLE
Q2
QS
ACTIVE
0110
C4
0101
ACTIVE
IDLE
0010
0000
0001
1001
QADC S3
Figure 13-29. CCW Priority Situation 3
The next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is
actively being serviced.
Situation S4 (Figure 13-30) shows that a queue 2 trigger event that is recognized while queue 1 is active
is saved, and as soon as queue 1 is finished, queue 2 servicing begins.
T1
Q1:
C1
C2
C3
C4
CF1
T2
C1
Q2:
C2
C3
C4
CF2
Q1
IDLE
IDLE
Q2
QS
0000
IDLE
ACTIVE
1000
TRIGGERED
ACTIVE
IDLE
1011
0010
0000
QADC S4
Figure 13-30. CCW Priority Situation 4
Situation S5 (Figure 13-31) shows that when multiple queue 2 trigger events are detected while queue 1 is
busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. Situation S5 also shows
that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in
use in either queue.
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13-57
QADC64E Legacy Mode Operation
T1
Q1:
T1
C1
C2
C3
T2 T2
T2 T2
PF1
Q2:
C1
Q2
QS
IDLE
1000 1011
ACTIVE
CF2
IDLE
ACTIVE
ACTIVE
PAUSE TRIG
0101 1001 1011
0110
C4
TOR2
PAUSE
TRIG
0000
C3
PF2
ACTIVE
IDLE
CF1
C2
TOR2
Q1
C4
ACTIVE
IDLE
0010
0000
QADC S5
Figure 13-31. CCW Priority Situation 5
The remaining situations, S6 through S11, show the impact of a queue 1 trigger event occurring during
queue 2 execution. Queue 1 is higher in priority the conversion taking place in queue 2 is aborted, so that
there is not a variable latency time in responding to queue 1 trigger events.
In situation S6 (Figure 13-32), the conversion initiated by the second CCW in queue 2 is aborted just
before the conversion is complete, so that queue 1 execution can begin. Queue 2 is considered suspended.
After queue 1 is finished, queue 2 starts over with the first CCW, when the RES (resume) control bit is set
to 0. Situation S7 (Figure 13-33) shows that when pause operation is not in use with queue 2, queue 2
suspension works the same way.
T1
Q1:
T1
C1
C2
C3
C4
T2
PF1
Q2:
C1
CF1
C1
C2
RESUME=0
C2
C3
C4
CF2
Q1
Q2
QS
IDLE
ACTIVE
PAUSE
IDLE
0000
ACTIVE
ACTIVE
ACTIVE SUSPEND
1000
0100
0110
1010
IDLE
ACTIVE
0010
IDLE
0000
QADC S6
Figure 13-32. CCW Priority Situation 6
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QADC64E Legacy Mode Operation
T1
Q1:
T1
C1
C2
T2
Q2:
C3
PF1
C1
C2
C4
T2
C1
CF1
C3
C2
C3
C4
PF2
IDLE
Q1
ACTIVE
CF2
PAUSE
Q2
IDLE
ACTIVE
SUSPEND
QS
0000
0010
1010
RESUME=0
IDLE
ACTIVE
ACTIVE PAUSEACT SUSPEND
ACTIVE
IDLE
0101 0110
0010
0000
0110
1010
QADC S7
Figure 13-33. CCW Priority Situation 7
Situations S8 and S9 (Figure 13-34 and Figure 13-35) repeat the same two situations with the resume bit
set to a one. When the RES bit is set, following suspension, queue 2 resumes execution with the aborted
CCW, not the first CCW in the queue.
T1
Q1:
T1
C1
C2
C3
T2
PF1
Q2: C1
C4
CF1
C2
C2
RESUME=1
C3
C4
CF2
Q1
IDLE
PAUSE
IDLE
Q2
QS
ACTIVE
0000
ACTIVE
ACTIVE
ACTIVE SUSPEND
1000
0100
0110
1010
IDLE
ACTIVE
IDLE
0010
0000
QADC S8
Figure 13-34. CCW Priority Situation 8
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QADC64E Legacy Mode Operation
T1
Q1:
T1
C1
C2
T2
Q2:
C3
PF1
C1
C1
C2
C4
T2
CF1
C3
C2
C4
C4
PF2
ACTIVE
IDLE
Q1
Q2
IDLE
ACTIVE
QS
0000
0010
RESUME=1
CF2
IDLE
ACTIVE
PAUSE
IDLE
SUSPEND ACT PAUSE ACTIVE SUSPEND ACT
0110
0110 0101
1010
1010
0000
0010
QADC S9
Figure 13-35. CCW Priority Situation 9
Situations S10 and S11 (Figure 13-36 and Figure 13-37) show that when an additional trigger event is
detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue
2 were being executed when a new trigger event occurs. Trigger overrun on queue 2 thus permits the
software to know that queue 1 is taking up so much QADC64E time that queue 2 trigger events are being
lost.
T1
T1
Q1: ACTIVE
C1 C2
T2
Q2:
T2
C1
ACTIVE
C3 C4
PF1
T2
C1
C2
C2
TOR2
IDLE
Q1
Q2
IDLE
QS
0000
ACTIVE
ACTIVE SUSPEND
0010
1010
T2
CF1
C3
C3
PF2
PAUSE
0101 0110
IDLE
ACTIVE
1010
RESUME=0
CF2
TOR2
ACTIVE PAUS ACT SUSPEND
0110
C4
ACTIVE
IDLE
0010
0000
QADC S10
Figure 13-36. CCW Priority Situation 10
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Freescale Semiconductor
QADC64E Legacy Mode Operation
T1
C1
Q1:
T2
Q2:
T1
C2
T2
C1
PF1
C2
IDLE
Q2
IDLE
QS
0000
T2
ACTIVE SUSPEND
0010
1010
CF1
C4
C4
TOR2
PF2
ACTIVE
C4
T2
C3
C2
TOR2
Q1
C3
CF2
IDLE
ACTIVE
PAUSE
RESUME=1
ACT PAUSE ACTIVE SUSPEND ACT
IDLE
0110 0101
0000
0110
1010
0010
QADC S11
Figure 13-37. CCW Priority Situation 11
The above situations cover normal overlap conditions that arise with asynchronous trigger events on the
two queues. An additional conflict to consider is that the freeze condition can arise while the QADC64E
is actively executing CCWs. The conventional use for the freeze mode is for software/hardware
debugging. When the CPU background debug mode is enabled and a breakpoint occurs, the freeze signal
is issued, which can cause peripheral modules to stop operation. When freeze is detected, the QADC64E
completes the conversion in progress, unlike queue 1 suspending queue 2. After the freeze condition is
removed, the QADC64E continues queue execution with the next CCW in sequence.
Trigger events that occur during freeze are not captured. When a trigger event is pending for queue 2 before
freeze begins, that trigger event is remembered when the freeze is passed. Similarly, when freeze occurs
while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished.
Situations 12 through 19 (Figure 13-38 to Figure 13-45) show examples of all of the freeze situations.
FREEZE
T1
Q1:
C1
C2
C3
C4
CF1
QADC S12
Figure 13-38. CCW Freeze Situation 12
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Freescale Semiconductor
13-61
QADC64E Legacy Mode Operation
FREEZE
T2
Q2: C1
C2
C3
C4
QADC S13
CF2
Figure 13-39. CCW Freeze Situation 13
(TRIGGERS IGNORED)
FREEZE
T1
T1 T1
Q1: C1
C2
C3
C4
QADC S14
T2 T2
CF1
Figure 13-40. CCW Freeze Situation 14
(Triggers Ignored)
FREEZE
T2
T2 T2
Q2: C1
C2
C3
C4
T1 T1
QADC S15
CF2
Figure 13-41. CCW Freeze Situation 15
(Triggers Ignored)
FREEZE
T1
Q1: C1
T1
T1
C2
C3
PF1
C4
CF1
QADC S16
Figure 13-42. CCW Freeze Situation 16
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QADC64E Legacy Mode Operation
(Triggers Ignored)
FREEZE
T2
T2
Q2: C1
T2
C2
C3
C4
PF2
CF2
QADC S17
Figure 13-43. CCW Freeze Situation 17
FREEZE
T1
Q1: C1
C2
C3
C4
T2
CF1
Q2: C1
C2
C3
C4
(Trigger Captured, Response Delayed After Freeze)
CF2
QADC S18
Figure 13-44. CCW Freeze Situation 18
FREEZE
T1
Q1: C1
C2
C3
C4
T2
Q2: C1
CF1
C2
C3
C4
C4
CF2
QADC S19
Figure 13-45. CCW Freeze Situation 19
13.6.2
Conversion Timing Schemes
This section contains some conversion timing examples. Example 1 below shows the timing for basic
conversions where the following is assumed:
• Q1 begins with CCW0 and ends with CCW3
• CCW0 has pause bit set
• CCW1 does not have pause bit set
• External trigger rise-edge for Q1
• CCW4 = BQ2 and Q2 is disabled
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Freescale Semiconductor
13-63
QADC64E Legacy Mode Operation
•
Q1 RES shows relative result register updates
Conversion time is >= 14 QCLKS
Time between triggers
QCLK
Trig1
EOC
QS
CWP
CWPQ1
Q1 RES
0
4
LAST
8
4
8
CCW1
CCW0
LAST
CCW0
CCW2
CCW1
R0
R1
Figure 13-46. External Trigger Mode (Positive Edge) Timing with Pause
Recall QS = 0 => Queues disabled; QS = 8 => Q1 active, Q2 disabled; QS= 4 => Q1 paused, Q2 disabled.
A time separator was provided between the triggers and end of conversion (EOC). The relationship to
QCLK displayed is not guaranteed.
CWPQ1 and CWPQ2 typically lag CWP and only match CWP when the associated queue is inactive.
Another way to view CWPQ1 and CWPQ2 is that these registers update when EOC triggers the result
register to be written.
When the pause bit is set (CCW0), please note that CWP does not increment until triggered. When the
pause is not set (CCW1), the CWP increments with EOC.
The conversion results Q1 RES(x) show the result associated with CCW(x). So that R0 represents the
result associated with CCW0.
Example 2 below shows the timing for conversions in gated mode single-scan with the
same assumptions as example 1 except:
• No pause bits set in any CCW
• External trigger gated single-scan mode for Q1
• Single-scan bit is set
When the gate closes and opens again the conversions start with the first CCW in Q1.
When the gate closes the active conversion completes before the queue goes idle.
When Q1 completes both the CF1 bit sets and the SSE bit clears.
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QADC64E Legacy Mode Operation
Trig1
(gate)
EOC
QS
CWP
CWPQ1
8
0
LAST
CCW0
LAST
LAST
Q1 RES
SSE
0
8
CCW1
CCW0
0
CCW1
CCW2
CCW3
CCW0
CCW1
CCW0
CCW1
CCW2
CCW3
R0
R1
R0
R1
R2
R3
Software must set SSE
CF1
PF1
Software must clear PF1
Figure 13-47. Gated Mode, Single-Scan Timing
Example 3 below shows the timing for conversions in gated continuous-scan mode with the same
assumptions in the amended definition for the PF bit in this mode to reflect the condition that a gate closing
occurred before the queue completed is a proposal under consideration at this time as example 2.
NOTE
At the end of Q1,the completion flag CF1 sets and the queue restarts. Also,
note that if the queue starts a second time and completes, the trigger overrun
flag TOR1 sets.
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Freescale Semiconductor
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QADC64E Legacy Mode Operation
Trig1
(gate)
EOC
8
0
QS
LAST
CWP
CWPQ1
Q1 RES
CCW0
CCW1
CCW2
CCW3
CCW0
CCW3
CCW0
LAST
CCW0
CCW1
CCW2
CCW3
CCW2
CCW3
R0
R1
R2
R3
R2
R3
XX
CF1
TOR1
Q restart
Q restart
Figure 13-48. Gated Mode, Continuous Scan Timing
13.7
QADC64E Integration Requirements
The QADC64E requires accurate, noise-free input signals for proper operation. This section discusses the
design of external circuitry to maximize QADC64E performance.
The QADC64E uses the external signals shown in Figure 13-1. There are 16 channel signals that can also
be used as general-purpose digital input signals, 8 of which can be configured as either digital input or
output signals.
13.7.1
Port Digital Input/Output Signals
The 16 port signals on the QADC64E module can be used as analog inputs. Port A signals can be
configured as digital input or digital output signals and Port B signals can be used as 8-bit digital input
signals.
Port A signals are referred to as PQA[7:0] when used as a bidirectional 8-bit digital input/output port.
These eight signals may be used for general-purpose digital input signals or push-pull digital output
signals. Port B signals are referred to as PQB[7:0] when used as digital input signals.
Port A and B signals are connected to a digital input synchronizer during reads and may be used as general
purpose digital inputs when the applied voltages meet high voltage input (VIH) and low voltage input (VIL)
requirements. Refer to Appendix F, “Electrical Characteristics,” for more information on voltage
requirements.
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QADC64E Legacy Mode Operation
Port A signals are configured as inputs or outputs by programming the port data direction register,
DDRQA. The digital input signal states are read from the port data register, PORTQA, when the port data
direction register specifies that the signals are inputs. The digital data in the port data register is driven onto
the port A signals when the corresponding bit in the port data direction register specifies that the signals
are outputs. Refer to Appendix B, “Internal Memory Map,” for more information. Since the outputs are
configured as push-pull drivers, external pull-up provisions are not necessary when the output is used to
drive another integrated circuit.
13.7.2
External Trigger Input Signals
The QADC64E uses two external trigger signals (ETRIG[2:1]). Each of the two input external trigger
signals is associated with one of the scan queues, queue 1 or queue 2 The assignment of ETRIG[2:1] to a
queue is made in the QACR0 register by the TRG bit. When TRG=0, ETRIG[1] triggers queue 1 and
ETRIG[2] triggers queue 2. When TRG=1, ETRIG[1] triggers queue 2 and ETRIG[2] triggers queue 1.
NOTE
The ETRIG[2:1] pins on the MPC561/MPC563 are multiplexed with the
PCS[7:6] pins.
13.7.3
Analog Power Signals
VDDA and VSSA signals supply power to the analog subsystems of the QADC64E module. Dedicated
power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the
digital power supply. Refer to Appendix F, “Electrical Characteristics,” for more information.
The analog supply signals (VDDA and VSSA) define the limits of the analog reference voltages (VRH and
VRL) and of the analog multiplexer inputs. Figure 13-49 is a diagram of the analog input circuitry.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-67
QADC64E Legacy Mode Operation
VDDA
VRH
Sample
AMP
S/H
RC DAC
Comparator
16 Channels
CP
VSSA
VRL
QADC64E 16CH SAMPLE AMP
Figure 13-49. Equivalent Analog Input Circuitry
Since the sample amplifier is powered by VDDA and VSSA, it can accurately transfer input signal levels up
to but not exceeding VDDA and down to but not below VSSA. If the input signal is outside of this range, the
output from the sample amplifier is clipped.
In addition, VRH and VRL must be within the range defined by VDDA and VSSA. As long as VRH is less than
or equal to VDDA and VRL is greater than or equal to VSSA and the sample amplifier has accurately
transferred the input signal, resolution is ratiometric within the limits defined by VRL and VRH. If VRH is
greater than VDDA, the sample amplifier can never transfer a full-scale value. If VRL is less than VSSA, the
sample amplifier can never transfer a zero value.
Figure 13-50 shows the results of reference voltages outside the range defined by VDDA and VSSA. At the
top of the input signal range, VDDA is 10 mV lower than VRH. This results in a maximum obtainable 10-bit
conversion value of 0x3FE. At the bottom of the signal range, VSSA is 15 mV higher than VRL, resulting in
a minimum obtainable 10-bit conversion value of three.
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QADC64E Legacy Mode Operation
3FF
10-Bit Result (Hexadecimal)
3FE
3FD
3FC
3FB
3FA
8
7
6
5
4
3
2
1
0
.010
.020
.030
5.100 5.110
5.120
Input in Volts (V RH = 5.120, VRL = 0 V)
5.130
QADC64E CLIPPING
Figure 13-50. Errors Resulting from Clipping
13.7.3.1
Analog Supply Filtering and Grounding
Two important factors influencing performance in analog integrated circuits are supply filtering and
grounding. Generally, digital circuits use bypass capacitors on every VDD/VSS signal pair. This applies
to analog sub-modules also. The distribution of power and ground is equally important.
Analog supplies should be isolated from digital supplies as much as possible. This necessity stems from
the higher performance requirements often associated with analog circuits. Therefore, deriving an analog
supply from a local digital supply is not recommended. However, if for economic reasons digital and
analog power are derived from a common regulator, filtering of the analog power is recommended in
addition to the bypassing of the supplies already mentioned.
For example, an RC low pass filter could be used to isolate the digital and analog supplies when generated
by a common regulator. If multiple high precision analog circuits are locally employed (i.e., two A/D
converters), the analog supplies should be isolated from each other as sharing supplies introduces the
potential for interference between analog circuits.
Grounding is the most important factor influencing analog circuit performance in mixed signal systems (or
in stand-alone analog systems). Care must be taken to not introduce additional sources of noise into the
analog circuitry. Common sources of noise include ground loops, inductive coupling, and combining
digital and analog grounds together inappropriately.
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QADC64E Legacy Mode Operation
The problem of how and when to combine digital and analog grounds arises from the large transients
which the digital ground must handle. If the digital ground is not able to handle the large transients, the
current from the large transients can return to ground through the analog ground. It is the excess current
overflowing into the analog ground which causes performance degradation by developing a differential
voltage between the true analog ground and the microcontroller’s ground signal. The end result is that the
ground observed by the analog circuit is no longer true ground and often ends in skewed results.
Two similar approaches designed to improve or eliminate the problems associated with grounding excess
transient currents involve star-point ground systems. One approach is to star-point the different grounds at
the power supply origin, thus keeping the ground isolated. Refer to Figure 13-51.
Another approach is to star-point the different grounds near the analog ground signal on the
microcontroller by using small traces for connecting the non-analog grounds to the analog ground. The
small traces are meant only to accommodate DC differences, not AC transients.
NOTE
This star-point scheme still requires adequate grounding for digital and
analog subsystems in addition to the star-point ground.
Other suggestions for PCB layout in which the QADC64E is employed include:
• Analog ground must be low impedance to all analog ground points in the circuit.
• Bypass capacitors should be as close to the power signals as possible.
The analog ground should be isolated from the digital ground. This can be done by cutting a separate
ground plane for the analog ground
• Non-minimum traces should be utilized for connecting bypass capacitors and filters to their
corresponding ground/power points.
• Distance for trace runs should be minimized where possible
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Freescale Semiconductor
QADC64E Legacy Mode Operation
Digital Power Supply
Analog Power Supply
PGND
+5V
VDDA
+5V
VSSA
AGND
VRL
VRH
+5V
VSS
QADC64E
VDD
PCB
Figure 13-51. Star-Ground at the Point of Power Supply Origin
13.7.4
Analog Reference Signals
VRH and VRL are the dedicated input signals for the high and low reference voltages. Separating the
reference inputs from the power supply signals allows for additional external filtering, which increases
reference voltage precision and stability, and subsequently contributes to a higher degree of conversion
accuracy.
No A/D converter can be more accurate than its analog reference. Any noise in the reference can result in
at least that much error in a conversion. The reference for the QADC64E, supplied by signals VRH, and
VRL, should be low-pass filtered from its source to obtain a noise-free, clean signal. In many cases, simple
capacitive bypassing may sufficed. In extreme cases, inductors or ferrite beads may be necessary if noise
or RF energy is present. Series resistance is not advisable since there is an effective DC current
requirement from the reference voltage by the internal resistor string in the RC DAC array. External
resistance may introduce error in this architecture under certain conditions. Any series devices in the filter
network should contain a minimum amount of DC resistance.
13.7.5
Analog Input Signals
Analog inputs should have low AC impedance at the signals. Low AC impedance can be realized by
placing a capacitor with good high frequency characteristics at the input signal of the part. Ideally, that
capacitor should be as large as possible (within the practical range of capacitors that still have good high
frequency characteristics). This capacitor has two effects:
• It helps attenuate any noise that may exist on the input.
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Freescale Semiconductor
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QADC64E Legacy Mode Operation
•
It sources charge during the sample period when the analog signal source is a high-impedance
source.
Series resistance can be used with the capacitor on an input signal to implement a simple RC filter. The
maximum level of filtering at the input signals is application dependent and is based on the bandpass
characteristics required to accurately track the dynamic characteristics of an input. Simple RC filtering at
the signal may be limited by the source impedance of the transducer or circuit supplying the analog signal
to be measured. Refer to Section 13.7.5.3, “Error Resulting from Leakage,” for more information. In some
cases, the size of the capacitor at the signal may be very small.
Figure 13-52 is a simplified model of an input channel. Refer to this model in the following discussion of
the interaction between the external circuitry and the circuitry inside the QADC64E.
Source
RSRC
External Filter
RF
Internal Circuit Model
S1
S2
S3
AMP
CSAMP
VSRC
CF
VI
CP
VSRC =Source Voltage
RSRC = Source Impedance
RF = Filter Impedance
CF = Filter Capacitor
CP = Internal Parasitic Capacitance
CSAMP = Sample Capacitor
VI = Internal Voltage Source during Sample and Hold
QADC64E Sample AMP Model
Figure 13-52. Electrical Model of an A/D Input Signal
In Figure 13-52, RF, RSRC and CF comprise the external filter circuit. CP is the internal parasitic capacitor.
CSAMP is the capacitor array used to sample and hold the input voltage. VI is an internal voltage source used
to provide charge to CSAMP during sample phase.
The following paragraphs provide a simplified description of the interaction between the QADC64E and
the external circuitry. This circuitry is assumed to be a simple RC low-pass filter passing a signal from a
source to the QADC64E input signal. The following simplifying assumptions are made:
• The external capacitor is perfect (no leakage, no significant dielectric absorption characteristics,
etc.)
• All parasitic capacitance associated with the input signal is included in the value of the external
capacitor
• Inductance is ignored
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QADC64E Legacy Mode Operation
•
The “on” resistance of the internal switches is 0 Ω and the “off” resistance is infinite
13.7.5.1
Analog Input Considerations
The source impedance of the analog signal to be measured and any intermediate filtering should be
considered whether external multiplexing is used or not. Figure 13-53 shows the connection of eight
typical analog signal sources to one QADC64E analog input signal through a separate multiplexer chip.
Also, an example of an analog signal source connected directly to a QADC64E analog input channel is
displayed.
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13-73
QADC64E Legacy Mode Operation
Analog Signal Source
RSOURCE2
~
Filtering and
Interconnect
Typical Mux Chip
(MC54HC4051, MC74HC4051,
MC54HC4052, MC74HC4052,
MC54HC4053, etc.)
QADC64E
R FILTER2
0.01 µF1
C
SOURCE
RSOURCE2
~
CFILTER C
MUXIN
R FILTER2
0.01 µF1
C
SOURCE
RSOURCE2
CFILTER C
MUXIN
R FILTER2
~
0.01 µF1
~
Interconnect
C
SOURCE
RSOURCE2
CFILTER C
MUXIN
R FILTER2
0.01 µF1
C
SOURCE
RSOURCE2
RMUXOUT
CMUXOUT
CPCB
CFILTER C
MUXIN
R FILTER2
RSOURCE2
0.01 µF
CSAMP
CIN =
CP + CSAMP
~
CSOURCE
CP
1
CFILTER C
MUXIN
R FILTER2
~
C
SOURCE
RSOURCE2
0.01 µF1
CFILTER C
MUXIN
R FILTER2
~
CSOURCE
RSOURCE2
0.01 µF1
CFILTER C
MUXIN
R FILTER2
~
0.01 µF1
C
SOURCE
~
RSOURCE2
C
SOURCE
CFILTER C MUXIN
R FILTER2
0.01 µF1
CFILTER
CP
CSAMP
CPCB
QADC64E EXT MUX EX
1 Typical Value
2 RFILTER typically 10KW–20KW
Figure 13-53. External Multiplexing of Analog Signal Sources
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QADC64E Legacy Mode Operation
13.7.5.2
Settling Time for the External Circuit
The values for RSRC, RF and CF in the external circuitry determine the length of time required to charge
CF to the source voltage level (VSRC). At time t = 0, VSRC changes in Figure 13-52 while S1 is open,
disconnecting the internal circuitry from the external circuitry. Assume that the initial voltage across CF is
zero. As CF charges, the voltage across it is determined by the following equation, where t is the total
charge time:
⎛
⎞
–t
⎛
⎜ ----------------------------------------------------------⎟ ⎞
⎜(R + R
⎟⎟
⎜
)C
⎝
F
SRC F⎠ ⎟
⎜
V CF = V SRC ⎜ 1 – e
⎟
⎜
⎟
⎜
⎟
⎝
⎠
Eqn. 13-1
As t approaches infinity, VCF will equal VSRC. (This assumes no internal leakage.) With 10-bit resolution,
1/2 of a count is equal to 1/2048 full-scale value. Assuming worst case (VSRC = full scale), Table 13-24
shows the required time for CF to charge to within 1/2 of a count of the actual source voltage during 10-bit
conversions. Table 13-24 is based on the RC network in Figure 13-52.
NOTE
The following times are completely independent of the A/D converter
architecture (assuming the QADC64E is not affecting the charging).
Table 13-24. External Circuit Settling Time to 1/2 LSB (10-Bit Conversions)
Filter Capacitor
(CF)
Source Resistance (RF + RSRC)
100 Ω
1 kΩ
10 kΩ
100 kΩ
1 µF
760 µs
7.6 ms
76 ms
760 ms
.1 µF
76 µs
760 µs
7.6 ms
76 ms
.01 µF
7.6 µs
76 µs
760 µs
7.6 ms
.001 µF
760 ns
7.6 µs
76 µs
760 µs
100 pF
76 ns
760 ns
7.6 µs
76 µs
The external circuit described in Table 13-24 is a low-pass filter. A user interested in measuring an AC
component of the external signal must take the characteristics of this filter into account.
13.7.5.3
Error Resulting from Leakage
A series resistor limits the current to a signal, therefore input leakage acting through a large source
impedance can degrade A/D accuracy. The maximum input leakage current is specified in Appendix F,
“Electrical Characteristics.” Input leakage is greater at higher operating temperatures. In the temperature
range from 125° C to 50° C, the leakage current is halved for every 8 – 12° C reduction in temperature.
Assuming VRH – VRL = 5.12 V, one count (assuming 10-bit resolution) corresponds to 5 mV of input
voltage. A typical input leakage of 200 nA acting through 10 kΩ of external series resistance results in an
error of 0.4 count (2.0 mV). If the source impedance is 100 kΩ and a typical leakage of 100 nA is present,
an error of two counts (10 mV) is introduced.
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QADC64E Legacy Mode Operation
In addition to internal junction leakage, external leakage (e.g., if external clamping diodes are used) and
charge sharing effects with internal capacitors also contribute to the total leakage current. Table 13-25
illustrates the effect of different levels of total leakage on accuracy for different values of source
impedance. The error is listed in terms of 10-bit counts.
CAUTION
Leakage from the part below 200 nA is obtainable only within a limited
temperature range.
Table 13-25. Error Resulting from Input Leakage (IOFF)
Source
Impedance
13.7.5.4
Leakage Value (10-bit Conversions)
100 nA
200 nA
500 nA
1000 nA
1 kΩ
—
—
0.1 counts
0.2 counts
10 kΩ
0.2 counts
0.4 counts
1 counts
2 counts
100 kΩ
2 counts
4 count
10 counts
20 counts
Accommodating Positive/Negative Stress Conditions
Positive or negative stress refers to conditions which exceed nominally defined operating limits. Examples
include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the
suggested supply/reference ranges) or causing currents into or out of the signal which exceed normal
limits. QADC64E specific considerations are voltages greater than VDDA, VRH or less than VSSA applied to
an analog input which cause excessive currents into or out of the input. Refer to Appendix F, “Electrical
Characteristics,” to for more information on exact magnitudes.
Either stress condition can potentially disrupt conversion results on neighboring inputs. Parasitic devices,
associated with CMOS processes, can cause an immediate disruptive influence on neighboring signals.
Common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal
tied to substrate (VSSI/VSSA ground). Under stress conditions, current injected on an adjacent signal can
cause errors on the selected channel by developing a voltage drop across the selected channel’s
impedances.
Figure 13-54 shows an active parasitic bipolar NPN transistor when an input signal is subjected to negative
stress conditions. Figure 13-55 shows positive stress conditions can activate a similar PNP transistor.
VSTRESS
+
I
RSTRESS INJN ANn Signal Under
Stress
10K
RSELECTED IIN
Parasitic
Device
ANn+1
VIN
Adjacent
signal
QADC64E PAR
Figure 13-54. Input Signal Subjected to Negative Stress
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QADC64E Legacy Mode Operation
VSTRESS
+
I
RSTRESS INJP ANn Signal Under
Stress
10K
RSELECTED IIN
VDDA
PARASITIC
DEVICE
ANn+1
VIN
Adjacent
signal
QADC64E PAR
Figure 13-55. Input Signal Subjected to Positive Stress
The current into the signal (IINJN or IINJP) under negative or positive stress is determined by the following
equations:
where:
– ( V STRESS – V BE )
I INJN = -----------------------------------------------------R STRESS
Eqn. 13-2
V STRESS – V EB – V DDA
I INJP = ---------------------------------------------------------------------R STRESS
Eqn. 13-3
VSTRESS = Adjustable voltage source
VEB = Parasitic PNP emitter/base voltage
(refer to VNEGCLAMP in Appendix F, “Electrical Characteristics”)
VBE = Parasitic NPN base/emitter voltage
(refer to VNEGCLAMP in Appendix F, “Electrical Characteristics”)
RSTRESS = Source impedance
(10-kΩ resistor in Figure 13-54 and Figure 13-55 on stressed channel)
RSELECTED = Source impedance on channel selected for conversion
The current into (IIN) the neighboring signal is determined by the KN (current coupling ratio) of the
parasitic bipolar transistor (KN 0 the resulting frequency of QCLK is calculated using the following
formula:
fQCLK = fSYSCLK / (PRESCALER + 1)
The QADC64E requires that fSYSCLK be at least twice fQCLK. Therefore if the value in the PRESCALER
field is set to Zero, the resulting QCLK frequency is calculated to be:
fQCLK = fSYSCLK / 2
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Freescale Semiconductor
14-49
QADC64E Enhanced Mode Operation
Table 14-22. QADC64E Clock Programmability
Control Register 0 Information
14.4.6
Input Sample Time (IST) =0
Example
Number
Frequency
PRESCALER
QCLK
(MHz)
Conversion Time
(µs)
1
20 MHz
0x09
2.0
7.0
2
40 MHz
0x13
2.0
7.0
3
56 MHz
0x1B
2.0
7.0
Periodic/Interval Timer
The on-chip periodic/interval timer can be used to generate trigger events at a programmable interval,
initiating execution of queue 1 and/or queue 2. The periodic/interval timer stays reset under the following
conditions:
• Both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval
timer
• IMB3 system reset or the master reset is asserted
• Stop mode is selected
• Freeze mode is selected
NOTE
Interval timer single-scan mode does not use the periodic/interval timer
until the single-scan enable bit is set.
The following two conditions will cause a pulsed reset of the periodic/interval timer during use:
• A queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue
2 is already using the timer
• A queue 2 operating mode change to a mode which uses the periodic/interval timer, provided queue
1 is not in a mode which uses the periodic/interval timer
• Roll over of the timer
During the low power stop mode, the periodic timer is held in reset. Since low power stop mode causes
QACR1 and QACR2 to be reset to zero, a valid periodic or interval timer mode must be written after stop
mode is exited to release the timer from reset.
When the IMB3 internal FREEZE line is asserted and a periodic or interval timer mode is selected, the
timer counter is reset after the conversion in progress completes. When the periodic or interval timer mode
has been enabled (the timer is counting), but a trigger event has not been issued, the freeze mode takes
effect immediately, and the timer is held in reset. When the internal FREEZE line is negated, the timer
counter starts counting from the beginning. Refer to Section 14.4.7, “Configuration and Control Using the
IMB3 Interface” for more information.
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
14.4.7
Configuration and Control Using the IMB3 Interface
The QADC64E module communicates with other microcontroller modules via the IMB3. The QADC64E
bus interface unit (BIU) coordinates IMB3 activity with internal QADC64E bus activity. This section
describes the operation of the BIU, IMB3 read/write accesses to QADC64E memory locations, module
configuration, and general-purpose I/O operation.
14.4.7.1
QADC64E Bus Interface Unit
The BIU is designed to act as a slave device on the IMB3. The BIU has the following functions: to respond
with the appropriate bus cycle termination, and to supply IMB3 interface timing to all internal module
signals.
BIU components consist of
• IMB3 buffers
• Address match and module select logic
• The BIU state machine
• Clock prescaler logic
• Data bus routing logic
• Interface to the internal module data bus
NOTE
Normal accesses from the IMB3 to the QADC64E require two clocks.
However, if the CPU tries to access table locations while the QADC64E is
accessing them, the QADC64E produces IMB3 wait states. From one to
four IMB3 wait states may be inserted by the QADC64E in the process of
reading and writing.
14.4.7.2
QADC64E Bus Accessing
The QADC64E supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses. Coherency of
results read (ensuring that all results read were taken consecutively in one scan) is not guaranteed. For
example, if a read of two consecutive 16-bit locations in a result area is made, the QADC64E could change
one 16-bit location in the result area between the bus cycles. There is no holding register for the second
16-bit location. All read and write accesses that require more than one 16-bit access to complete occur as
two or more independent bus cycles. Depending on bus master protocol, these accesses could include
misaligned and 32-bit accesses.
Figure 14-24 shows the three bus cycles which are implemented by the QADC64E. The following
paragraphs describe how the three types of accesses are used, including misaligned 16-bit and 32-bit
accesses.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
14-51
QADC64E Enhanced Mode Operation
W
Intermodule Bus
QADC Location
R
W
R
Byte 0
Byte 1
Byte 0
Byte 1
8-bit Access of an Even Address (ISIZ = 01, A0 = 0)
W
Intermodule Bus
QADC Location
R
W
R
Byte 0
Byte 1
Byte 0
Byte 1
8-bit Access of an Odd Address (ISIZ = 01, A0 = 1; OR ISIZ = 10, A0 = 1)
W
Intermodule Bus
QADC Location
R
W
R
BYTE 0
BYTE 1
BYTE 0
BYTE 1
16-Bit Aligned Access (ISIZ = 10, A0 = 0)
QADC64E Bus CYC ACC
Figure 14-24. Bus Cycle Accesses
Byte access to an even address of a QADC64E location is shown in the top illustration of Figure 14-24. In
the case of write cycles, byte 1 of the register is not disturbed. In the case of a read cycle, the QADC64E
provides both byte 0 and byte 1.
Byte access to an odd address of a QADC64E location is shown in the center illustration of Figure 14-24.
In the case of write cycles, byte 0 of the register is not disturbed. In the case of read cycles, the QADC64E
provides both byte 0 and byte 1.
16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest illustration of
Figure 14-24. The full 16 bits of data is written to and read from the QADC64E location with each access.
16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit QADC64E
locations is accessed. The first bus cycle is treated by the QADC64E as an 8-bit read or write of an odd
address. The second cycle is an 8-bit read or write of an even address. The QADC64E address space is
organized into 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides
the lower half of one QADC64E location, and the upper half of the following QADC64E location.
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
32-bit accesses to an even address require two bus cycles to complete the access, and two full 16-bit
QADC64E locations are accessed. The first bus cycle reads or writes the addressed 16-bit QADC64E
location and the second cycle reads or writes the following 16-bit location.
32-bit accesses to an odd address require three bus cycles. Portions of three different QADC64E locations
are accessed. The first bus cycle is treated by the QADC64E as an 8-bit access of an odd address, the
second cycle is a 16-bit aligned access, and the third cycle is an 8-bit access of an even address. The
QADC64E address space is organized into 16-bit even address locations, so a 32-bit read or write of an
odd address provides the lower half of one QADC64E location, the full 16-bit content of the following
QADC64E location, and the upper half of the third QADC64E location.
14.5
Trigger and Queue Interaction Examples
This section contains examples describing queue priority and conversion timing schemes.
14.5.1
Queue Priority Schemes
Since there are two conversion command queues and only one A/D converter, there is a priority scheme
to determine which conversion is to occur. Each queue has a variety of trigger events that are intended to
initiate conversions, and they can occur asynchronously in relation to each other and other conversions in
progress. For example, a queue can be idle awaiting a trigger event, a trigger event can have occurred but
the first conversion has not started, a conversion can be in progress, a pause condition can exist awaiting
another trigger event to continue the queue, and so on.
The following paragraphs and figures outline the prioritizing criteria used to determine which conversion
occurs in each overlap situation.
NOTE
The situations in Figure 14-25 through Figure 14-43 are labeled S1 through
S19. In each diagram, time is shown increasing from left to right. The
execution of queue 1 and queue 2 (Q1 and Q2) is shown as a string of
rectangles representing the execution time of each CCW in the queue. In
most of the situations, there are four CCWs (labeled C1 to C4) in both queue
1 and queue 2. In some of the situations, CCW C2 is presumed to have the
pause bit set, to show the similarities of pause and end-of-queue as
terminations of queue execution.
Trigger events are described in Table 14-23.
Table 14-23. Trigger Events
Trigger
Events
T1
Events that trigger queue 1 execution (external trigger, software
initiated single-scan enable bit, or completion of the previous
continuous loop)
T2
Events that trigger queue 2 execution (external trigger, software
initiated single-scan enable bit, timer period/interval expired, or
completion of the previous continuous loop)
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Freescale Semiconductor
14-53
QADC64E Enhanced Mode Operation
When a trigger event causes a CCW execution in progress to be aborted, the aborted conversion is shown
as a ragged end of a shortened CCW rectangle.
The situation diagrams also show when key status bits are set. Table 14-24 describes the status bits.
Table 14-24. Status Bits
Bit
Function
CF Flag
Set when the end of the queue is reached
PF Flag
Set when a queue completes execution up through a pause bit
Trigger Overrun
Error (TOR)
Set when a new trigger event occurs before the queue is finished
serving the previous trigger event
Below the queue execution flows are three sets of blocks that show the status information that is made
available to the software. The first two rows of status blocks show the condition of each queue as:
• Idle
• Active
• Pause
• Suspended (queue 2 only)
• Trigger pending
The third row of status blocks shows the 4-bit QS status register field that encodes the condition of the two
queues. Two transition status cases, QS = 0011 and QS = 0111, are not shown because they exist only very
briefly between stable status conditions.
The first three examples in Figure 14-25 through Figure 14-27 (S1, S2, and S3) show what happens when
a new trigger event is recognized before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1 (Figure 14-25), one trigger event is being recognized on each queue while that queue is still
working on the previously recognized trigger event. The trigger overrun error status bit is set, and
otherwise, the premature trigger event is ignored. A trigger event which occurs before the servicing of the
previous trigger event is through does not disturb the queue execution in progress.
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14-54
Freescale Semiconductor
QADC64E Enhanced Mode Operation
T1
T1
C1
Q1:
C2
C3
C4
TOR1
T2
CF1
Q2:
T2
C1
C2
C3
TOR2
IDLE
Q1
IDLE
0000
QS
CF2
IDLE
ACTIVE
Q2
C4
IDLE
ACTIVE
1000
0000
0000
0010
QADC S1
Figure 14-25. CCW Priority Situation 1
In situation S2 (Figure 14-25), more than one trigger event is recognized before servicing of a previous
trigger event is complete, the trigger overrun bit is again set, but otherwise, the additional trigger events
are ignored. After the queue is complete, the first newly detected trigger event causes queue execution to
begin again. When the trigger event rate is high, a new trigger event can be seen very soon after completion
of the previous queue, leaving software little time to retrieve the previous results. Also, when trigger events
are occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all.
T1
Q1:
T1
C1
T1
C2
T1
C3
T1
C4
TOR1 TOR1 TOR1
C1
C2
C3
CF1
C4
T2
CF1
Q2:
C1
T2
T2
C2
C3
TOR2 TOR2
Q1
IDLE
ACTIVE
1000
1000
CF2
IDLE
ACTIVE
IDLE
Q2
QS
IDLE
C4
0000
ACTIVE
IDLE
0010
0000
QADC S2
Figure 14-26. CCW Priority Situation 2
Situation S3 (Figure 14-26) shows that when the pause feature is in use, the trigger overrun error status bit
is set the same way, and that queue execution continues unchanged.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
14-55
QADC64E Enhanced Mode Operation
T1
Q1:
T1
C1
T1
C2
TOR1
C3
PF1
T2
Q2:
T2
C1
IDLE
IDLE
Q2
QS
T2
PF2
C4
TOR2
PAUSE
0101
CF2
IDLE
ACTIVE
0110
0100
T2
C3
ACTIVE
1000
0000
CF1
C2
PAUSE
ACTIVE
C4
TOR1
TOR2
Q1
T1
ACTIVE
IDLE
0010
0000
0001
1001
QADC S3
Figure 14-27. CCW Priority Situation 3
The next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is
actively being serviced.
Situation S4 (Figure 14-28) shows that a queue 2 trigger event that is recognized while queue 1 is active
is saved, and as soon as queue 1 is finished, queue 2 servicing begins.
T1
Q1:
C1
C2
C3
C4
CF1
T2
C1
C2
C3
C4
Q2:
CF2
Q1
IDLE
IDLE
Q2
QS
0000
IDLE
ACTIVE
1000
TRIGGERED
ACTIVE
IDLE
1011
0010
0000
QADC S4
Figure 14-28. CCW Priority Situation 4
Situation S5 (Figure 14-29) shows that when multiple queue 2 trigger events are detected while queue 1 is
busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. Situation S5 also shows
that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in
use in either queue.
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
T1
T1
Q1:
C1
C2
T2 T2
C3
T2 T2
PF1
Q2:
C1
IDLE
IDLE
Q2
QS
0000
1000
C3
ACTIVE
1011
0110
CF2
ACTIVE
ACTIVE
PAUSE
TRIG
C4
TOR2
PF2
ACTIVE
CF1
C2
TOR2
Q1
C4
IDLE
TRIG
PAUSE
ACTIVE
IDLE
0010
0000
0101 1001 1011
QADC S5
Figure 14-29. CCW Priority Situation 5
The remaining situations, S6 through S11, show the impact of a queue 1 trigger event occurring during
queue 2 execution. Queue 1 is higher in priority the conversion taking place in queue 2 is aborted, so that
there is not a variable latency time in responding to queue 1 trigger events.
In situation S6 (Figure 14-30), the conversion initiated by the second CCW in queue 2 is aborted just
before the conversion is complete, so that queue 1 execution can begin. Queue 2 is considered suspended.
After queue 1 is finished, queue 2 starts over with the first CCW, when the RES (resume) control bit is set
to 0. Situation S7 (Figure 14-31) shows that when pause operation is not in use with queue 2, queue 2
suspension works the same way.
T1
Q1:
T1
C1
C2
C3
C4
RESUME=0
T2
PF1
CF1
Q2:
C1
C1
C2
C2
C3
C4
CF2
Q1
IDLE
PAUSE
ACTIVE
IDLE
Q2
QS
ACTIVE
0000
1000
0100
0110
ACTIVE
ACTIVE
SUSPEND
1010
IDLE
ACTIVE
0010
IDLE
0000
QADC S6
Figure 14-30. CCW Priority Situation 6
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Freescale Semiconductor
14-57
QADC64E Enhanced Mode Operation
T1
Q1:
T1
C1
C2
T2
Q2:
C3
PF1
C1
C2
C4
T2
C1
CF1
C3
C2
C3
C4
CF2
PF2
IDLE
Q1
ACTIVE
Q2
IDLE
ACTIVE
QS
0000
0010
PAUSE
SUSPEND
ACTIVE
IDLE
ACTIVE
PAUSE ACT SUSPEND
0110
1010
RESUME=0
1010
0101 0110
ACTIVE
IDLE
0010
0000
QADC S7
Figure 14-31. CCW Priority Situation 7
Situations S8 and S9 (Figure 14-32 and Figure 14-33) repeat the same two situations with the resume bit
set to a one. When the RES bit is set, following suspension, queue 2 resumes execution with the aborted
CCW, not the first CCW in the queue.
T1
Q1:
T1
C1
C2
C3
C4
T2
PF1
Q2:
RESUME=1
CF1
C1
C2
C2
C3
C4
CF2
Q1
Q2
QS
IDLE
PAUSE
ACTIVE
IDLE
0000
ACTIVE
1000
0100
0110
ACTIVE
ACTIVE
SUSPEND
1010
IDLE
ACTIVE
IDLE
0010
0000
QADC S8
Figure 14-32. CCW Priority Situation 8
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
T1
Q1:
T1
C1
C2
T2
Q2:
C3
PF1
C1
C1
C2
C4
T2
CF1
C4
C3
C2
C4
CF2
PF2
ACTIVE
IDLE
Q1
Q2
IDLE
ACTIVE
QS
0000
0010
ACT PAUSE
0110 0101
1010
IDLE
ACTIVE
PAUSE
SUSPEND
RESUME=1
ACTIVE
SUSPEND
ACT
IDLE
0110
1010
0010
0000
QADC S9
Figure 14-33. CCW Priority Situation 9
Situations S10 and S11 (Figure 14-34 and Figure 14-35) show that when an additional trigger event is
detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue
2 were being executed when a new trigger event occurs. Trigger overrun on queue 2 thus permits the
software to know that queue 1 is taking up so much QADC64E time that queue 2 trigger events are being
lost.
T1
Q1:
T2
Q2:
T1
ACTIVE
C1
C2
T2
C1
ACTIVE
C3
C4
PF1
T2
C1
C2
C2
TOR2
IDLE
Q1
ACTIVE
Q2
IDLE
ACTIVE
QS
0000
0010
SUSPEND
1010
T2
0110
1010
RESUME=0
CF2
IDLE
ACTIVE
PAUSE ACT SUSPEND
0101
C4
TOR2
PAUSE
0110
C3
C3
PF2
ACTIVE
CF1
ACTIVE
IDLE
0010
0000
QADC S10
Figure 14-34. CCW Priority Situation 10
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
14-59
QADC64E Enhanced Mode Operation
T1
T1
C1
Q1:
T2
Q2:
C2
T2
C1
PF1
C2
IDLE
IDLE
ACTIVE
QS
0000
0010
C3
RESUME=1
C4
CF2
TOR2
IDLE
ACTIVE
ACT PAUSE ACTIVE
0110 0101
1010
CF1
C4
PAUSE
SUSPEND
C4
T2
PF2
ACTIVE
Q2
T2
C2
TOR2
Q1
C3
0110
SUSPEND
1010
ACT
IDLE
0010
0000
QADC S11
Figure 14-35. CCW Priority Situation 11
The above situations cover normal overlap conditions that arise with asynchronous trigger events on the
two queues. An additional conflict to consider is that the freeze condition can arise while the QADC64E
is actively executing CCWs. The conventional use for the freeze mode is for software/hardware
debugging. When the CPU background debug mode is enabled and a breakpoint occurs, the freeze signal
is issued, which can cause peripheral modules to stop operation. When freeze is detected, the QADC64E
completes the conversion in progress, unlike queue 1 suspending queue 2. After the freeze condition is
removed, the QADC64E continues queue execution with the next CCW in sequence.
Trigger events that occur during freeze are not captured. When a trigger event is pending for queue 2 before
freeze begins, that trigger event is remembered when the freeze is passed. Similarly, when freeze occurs
while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished.
Situations 12 through 19 (Figure 14-36 to Figure 14-43) show examples of all of the freeze situations.
FREEZE
T1
Q1:
C1
C2
C3
C4
CF1
QADC S12
Figure 14-36. CCW Freeze Situation 12
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
FREEZE
T2
Q2:
C1
C2
C3
C4
QADC S13
CF2
Figure 14-37. CCW Freeze Situation 13
(TRIGGERS IGNORED)
FREEZE
T1
T1 T1
C1
Q1:
C2
C3
C4
QADC S14
T2 T2
CF1
Figure 14-38. CCW Freeze Situation 14
(TRIGGERS IGNORED)
FREEZE
T2
Q2:
T2 T2
C1
C2
C3
C4
T1 T1
QADC S15
CF2
Figure 14-39. CCW Freeze Situation 15
(TRIGGERS IGNORED)
FREEZE
T1
Q1:
T1
C1
T1
C2
C3
PF1
C4
CF1
QADC S16
Figure 14-40. CCW Freeze Situation 16
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Freescale Semiconductor
14-61
QADC64E Enhanced Mode Operation
(TRIGGERS IGNORED)
FREEZE
T2
T2
Q2:
C1
T2
C2
C3
PF2
C4
CF2
QADC S17
Figure 14-41. CCW Freeze Situation 17
FREEZE
T1
Q1:
C1
C2
C3
C4
T2
CF1
(TRIGGER CAPTURED, RESPONSE DELAYED AFTER FREEZE)
Q2:
C1
C2
C3
C4
CF2
QADC S18
Figure 14-42. CCW Freeze Situation 18
FREEZE
T1
Q1:
C1
C2
C3
C4
T2
Q2:
CF1
C1
C2
C3
C4
C4
CF2
QADC S19
Figure 14-43. CCW Freeze Situation 19
14.5.2
Conversion Timing Schemes
This section contains some conversion timing examples. Example 1 below shows the timing for basic
conversions where the following is assumed:
• Q1 begins with CCW0 and ends with CCW3
• CCW0 has pause bit set
• CCW1 does not have pause bit set
• External trigger rise-edge for Q1
• CCW4 = BQ2 and Q2 is disabled
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QADC64E Enhanced Mode Operation
•
Q1 RES shows relative result register updates
Conversion time is >= 14 QCLKS
Time between triggers
QCLK
Trig1
EOC
QS
CWP
CWPQ1
0
4
LAST
8
4
8
CCW1
CCW0
LAST
CCW0
CCW2
CCW1
R0
Q1 RES
R1
Figure 14-44. External Trigger Mode (Positive Edge) Timing with Pause
Recall QS = 0 => Queues disabled; QS = 8 => Q1 active, Q2 disabled; QS= 4 => Q1 paused, Q2 disabled.
A time separator was provided between the triggers and end of conversion (EOC). The relationship to
QCLK displayed is not guaranteed.
CWPQ1 or CWPQ2 typically lag CWP and only match CWP when the associated queue is inactive.
Another way to view CWPQ1(2) is that these registers update when EOC triggers the result register to be
written.
When the pause bit is set (CCW0), please note that CWP does not increment until triggered. When the
pause is not set (CCW1), the CWP increments with EOC.
The conversion results Q1 RES(x) show the result associated with CCW(x). So that R0 represents the
result associated with CCW0.
Example 2 below shows the timing for conversions in gated mode single-scan with the
same assumptions as example 1 except:
• No pause bits set in any CCW
• External trigger gated single-scan mode for Q1
• Single-scan bit is set
When the gate closes and opens again the conversions start with the first CCW in Q1.
When the gate closes the active conversion completes before the queue goes idle.
When Q1 completes both the CF1 bit sets and the SSE bit clears.
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Freescale Semiconductor
14-63
QADC64E Enhanced Mode Operation
Trig1
(gate)
EOC
QS
CWP
CWPQ1
Q1 RES
SSE
8
0
LAST
0
CCW0
LAST
LAST
8
CCW1
CCW0
0
CCW1
CCW2
CCW3
CCW0
CCW1
CCW0
CCW1
CCW2
CCW3
R0
R1
R0
R1
R2
R3
Software must set SSE
CF1
PF1
Software must clear PF1
Figure 14-45. Gated Mode, Single-Scan Timing
Example 3 below shows the timing for conversions in gated continuous-scan mode with the same
assumptions in the amended definition for the PF bit in this mode to reflect the condition that a gate closing
occurred before the queue completed is a proposal under consideration at this time as example 2.
NOTE
At the end of Q1,the completion flag CF1 sets and the queue restarts. Also,
note that if the queue starts a second time and completes, the trigger overrun
flag TOR1 sets.
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
Trig1
(gate)
EOC
8
0
QS
LAST
CCW0
CCW1
CCW2
CCW3
CCW0
CCW3
CCW0
CWPQ1
LAST
CCW0
CCW1
CCW2
CCW3
CCW2
CCW3
Q1 RES
XX
CWP
R0
R1
R2
R3
R2
R3
CF1
TOR1
Q restart
Q restart
Figure 14-46. Gated Mode, Continuous Scan Timing
14.6
QADC64E Integration Requirements
The QADC64E requires accurate, noise-free input signals for proper operation. This section discusses the
design of external circuitry to maximize QADC64E performance.
The QADC64E uses the external signals shown in Figure 14-1. There are 16 channel signals that can also
be used as general-purpose digital input/output signals. With external multiplexing MPC561/MPC563 can
support 41 analog inputs. In addition, there are three analog reference signals and two analog submodule
power signals, shared by each QADC64E module.
14.6.1
Port Digital Input/Output Signals
The sixteen port signals can be used as analog inputs, or as a bidirectional 16-bit digital input/output port.
Port A signals are referred to as PQA[7:0] when used as a bidirectional 8-bit digital input/output port.
These eight signals may be used for general-purpose digital input signals or push-pull digital output
signals. Port B signals are referred to as PQB[7:0] and operate the same as Port A.
Port A and B signals are connected to a digital input synchronizer during reads and may be used as general
purpose digital inputs when the applied voltages meet high voltage input (VIH) and low voltage input (VIL)
requirements. Refer to Appendix F, “Electrical Characteristics,” for more information on voltage
requirements.
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QADC64E Enhanced Mode Operation
Each port A or B signal is configured as an input or output by programming the port data direction register
(DDRQA or DDRQB). The digital input signal states are read by the software in the upper half of the port
data register when the port data direction register specifies that the signals are inputs. The digital data in
the port data register is driven onto the port A or B signals when the corresponding bit in the port data
direction register specifies output. Refer to Appendix B, “Internal Memory Map” for more information.
Since the outputs are configured as push-pull drivers, external pull-up provisions are not necessary when
the output is used to drive another integrated circuit.
14.6.2
External Trigger Input Signals
The QADC64E uses two external trigger signals (ETRIG[2:1]). Each of the two input external trigger
signals is associated with one of the scan queues, queue 1 or queue 2 The assignment of ETRIG[2:1] to a
queue is made in the QACR0 register by the TRG bit. When TRG=0, ETRIG1 triggers queue 1 and
ETRIG2 triggers queue 2. When TRG=1, ETRIG1 triggers queue 2 and ETRIG2 triggers queue 1.
14.6.3
Analog Power Signals
VDDA and VSSA signals supply power to the analog subsystems of the QADC64E module. Dedicated
power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the
digital power supply. Refer to Appendix F, “Electrical Characteristics,” for more information.
The analog supply signals (VDDA and VSSA) define the limits of the analog reference voltages (VRH and
VRL) and of the analog multiplexer inputs. Figure 14-47 is a diagram of the analog input circuitry.
VDDA
VRH
SAMPLE
AMP
S/H
RC DAC
Comparator
16 CHANNELS
CP
VSSA
VRL
QADC64E 16CH SAMPLE AMP
Figure 14-47. Equivalent Analog Input Circuitry
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QADC64E Enhanced Mode Operation
Since the sample amplifier is powered by VDDA and VSSA, it can accurately transfer input signal levels up
to but not exceeding VDDA and down to but not below VSSA. If the input signal is outside of this range, the
output from the sample amplifier is clipped.
In addition, VRH and VRL must be within the range defined by VDDA and VSSA. As long as VRH is less than
or equal to VDDA and VRL is greater than or equal to VSSA and the sample amplifier has accurately
transferred the input signal, resolution is ratiometric within the limits defined by VRL and VRH. If VRH is
greater than VDDA, the sample amplifier can never transfer a full-scale value. If VRL is less than VSSA, the
sample amplifier can never transfer a zero value.
Figure 14-48 shows the results of reference voltages outside the range defined by VDDA and VSSA. At the
top of the input signal range, VDDA is 10 mV lower than VRH. This results in a maximum obtainable 10-bit
conversion value of 0x3FE. At the bottom of the signal range, VSSA is 15 mV higher than VRL, resulting in
a minimum obtainable 10-bit conversion value of three.
3FF
10-Bit Result (Hexadecimal)
3FE
3FD
3FC
3FB
3FA
8
7
6
5
4
3
2
1
0
.010
.020
.030
5.100 5.110
5.120
Input in Volts (VRH = 5.12 V, VRL = 0 V)
5.130
QADC64E Clipping
Figure 14-48. Errors Resulting from Clipping
14.6.3.1
Analog Supply Filtering and Grounding
Two important factors influencing performance in analog integrated circuits are supply filtering and
grounding. Generally, digital circuits use bypass capacitors on every VDD/VSS signal pair. This applies to
analog sub-modules also. The distribution of power and ground is equally important.
MPC561/MPC563 Reference Manual, Rev. 1.2
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14-67
QADC64E Enhanced Mode Operation
Analog supplies should be isolated from digital supplies as much as possible. This necessity stems from
the higher performance requirements often associated with analog circuits. Therefore, deriving an analog
supply from a local digital supply is not recommended. However, if for economic reasons digital and
analog power are derived from a common regulator, filtering of the analog power is recommended in
addition to the bypassing of the supplies already mentioned.
NOTE
An RC low pass filter could be used to isolate the digital and analog supplies
when generated by a common regulator. If multiple high precision analog
circuits are locally employed (i.e., two A/D converters), the analog supplies
should be isolated from each other as sharing supplies introduces the
potential for interference between analog circuits.
Grounding is the most important factor influencing analog circuit performance in mixed signal systems (or
in stand-alone analog systems). Close attention must be paid not to introduce additional sources of noise
into the analog circuitry. Common sources of noise include ground loops, inductive coupling, and
combining digital and analog grounds together inappropriately.
The problem of how and when to combine digital and analog grounds arises from the large transients
which the digital ground must handle. If the digital ground is not able to handle the large transients, the
current from the large transients can return to ground through the analog ground. It is the excess current
overflowing into the analog ground which causes performance degradation by developing a differential
voltage between the true analog ground and the microcontroller’s ground signal. The end result is that the
ground observed by the analog circuit is no longer true ground and often ends in skewed results.
Two similar approaches designed to improve or eliminate the problems associated with grounding excess
transient currents involve star-point ground systems. One approach is to star-point the different grounds at
the power supply origin, thus keeping the ground isolated. Refer to Figure 14-49.
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
Digital Power Supply
Analog Power Supply
QADC64E
PGND
+5V
VDDA
+5V
VSSA
AGND
VRL
VRH
+5V
VSS
VDD
PCB
Figure 14-49. Star-Ground at the Point of Power Supply Origin
Another approach is to star-point the different grounds near the analog ground signal on the
microcontroller by using small traces for connecting the non-analog grounds to the analog ground. The
small traces are meant only to accommodate DC differences, not AC transients.
NOTE
This star-point scheme still requires adequate grounding for digital and
analog subsystems in addition to the star-point ground.
Other suggestions for PCB layout in which the QADC64E is employed include:
• Analog ground must be low impedance to all analog ground points in the circuit.
• Bypass capacitors should be as close to the power signals as possible.
• The analog ground should be isolated from the digital ground. This can be done by cutting a
separate ground plane for the analog ground.
• Non-minimum traces should be utilized for connecting bypass capacitors and filters to their
corresponding ground/power points.
• Distance for trace runs should be minimized where possible.
14.6.4
Analog Reference Signals
VRH and VRL are the dedicated input signals for the high and low reference voltages. Separating the
reference inputs from the power supply signals allows for additional external filtering, which increases
reference voltage precision and stability, and subsequently contributes to a higher degree of conversion
accuracy.
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Freescale Semiconductor
14-69
QADC64E Enhanced Mode Operation
The AltRef signal may be selected through the CCW as the high reference for a conversion. This allows
for the ability to “zoom” in on a portion of the convertible range with the full 10 bits. Refer to Table 14-19.
No A/D converter can be more accurate than its analog reference. Any noise in the reference can result in
at least that much error in a conversion. The reference for the QADC64E, supplied by signals VRH, AltRef,
and VRL, should be low-pass filtered from its source to obtain a noise-free, clean signal. In many cases,
simple capacitive bypassing may sufficed. In extreme cases, inductors or ferrite beads may be necessary
if noise or RF energy is present. Series resistance is not advisable since there is an effective DC current
requirement from the reference voltage by the internal resistor string in the RC DAC array. External
resistance may introduce error in this architecture under certain conditions. Any series devices in the filter
network should contain a minimum amount of DC resistance.
14.6.5
Analog Input Signals
Analog inputs should have low AC impedance at the signals. Low AC impedance can be realized by
placing a capacitor with good high frequency characteristics at the input signal of the part. Ideally, that
capacitor should be as large as possible (within the practical range of capacitors that still have good high
frequency characteristics). This capacitor has two effects:
• It helps attenuate any noise that may exist on the input.
• It sources charge during the sample period when the analog signal source is a high-impedance
source.
Series resistance can be used with the capacitor on an input signal to implement a simple RC filter. The
maximum level of filtering at the input signals is application dependent and is based on the bandpass
characteristics required to accurately track the dynamic characteristics of an input. Simple RC filtering at
the signal may be limited by the source impedance of the transducer or circuit supplying the analog signal
to be measured. Refer to Section 14.6.5.3, “Error Resulting from Leakage” for more information. In some
cases, the size of the capacitor at the signal may be very small.
Figure 14-50 is a simplified model of an input channel. Refer to this model in the following discussion of
the interaction between the external circuitry and the circuitry inside the QADC64E.
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
Source
RSRC
External Filter
Internal Circuit Model
S1
RF
S2
S3
AMP
CSAMP
VSRC
CF
VI
CP
VSRC = Source Voltage
RSRC = Source Impedance
RF = Filter Impedance
CF = Filter Capacitor
CP = Internal Parasitic Capacitance
CSAMP= Sample Capacitor
VI = Internal Voltage Source During Sample and Hold
QADC64E Sample AMP Model
Figure 14-50. Electrical Model of an A/D Input Signal
In Figure 14-50, RF, RSRC and CF comprise the external filter circuit. CP is the internal parasitic capacitor.
CSAMP is the capacitor array used to sample and hold the input voltage. VI is an internal voltage source used
to provide charge to CSAMP during sample phase.
The following paragraphs provide a simplified description of the interaction between the QADC64E and
the external circuitry. This circuitry is assumed to be a simple RC low-pass filter passing a signal from a
source to the QADC64E input signal. The following simplifying assumptions are made:
•
•
•
•
The external capacitor is perfect (no leakage, no significant dielectric absorption characteristics,
etc.)
All parasitic capacitance associated with the input signal is included in the value of the external
capacitor
Inductance is ignored
The “on” resistance of the internal switches is 0 Ω and the “off” resistance is infinite
14.6.5.1
Analog Input Considerations
The source impedance of the analog signal to be measured and any intermediate filtering should be
considered whether external multiplexing is used or not. Figure 14-51 shows the connection of eight
typical analog signal sources to one QADC64E analog input signal through a separate multiplexer chip.
Also, an example of an analog signal source connected directly to a QADC64E analog input channel is
displayed.
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Freescale Semiconductor
14-71
QADC64E Enhanced Mode Operation
Analog Signal Source
Filtering and
Interconnect
RSOURCE2
~
R
Typical Mux Chip
(MC54HC4051, MC74HC4051,
MC54HC4052, MC74HC4052,
MC54HC4053, etc.)
Interconnect
QADC64E
2
FILTER
0.01 µF1
CSOURCE
2
RSOURCE
~
R
C
FILTER
FILTER2
CMUXIN
0.01 µF1
CSOURCE
2
RSOURCE
C
R FILTER2FILTER
CMUXIN
~
R
0.01 µF1
CSOURCE
R SOURCE2
~
MUXOUT
C2FILTER
R FILTER
CMUXIN
C
0.01 µF1
CSOURCE
2
RSOURCE
MUXOUT
CFILTER
R FILTER2
C
PCB
C
P
CMUXIN
C
SAMP
CIN =
CP + CSAMP
~
CSOURCE
2
R SOURCE
0.01 µF
1
CFILTER
R FILTER2
CMUXIN
~
CSOURCE
R SOURCE2
0.01 µF1
R
~
CSOURCE
2
RSOURCE
~
CFILTER
2
FILTER
CMUXIN
0.01 µF1
R
C
FILTER
2
FILTER
CMUXIN
0.01 µF1
CSOURCE
C
FILTER
RSOURCE2
C MUXIN
R FILTER2
~
CSOURCE
0.01 µF1
CFILTER
CPCB
CP
CSAMP
QADC64E EXT MUX EX
Figure 14-51. External Multiplexing of Analog Signal Sources
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QADC64E Enhanced Mode Operation
14.6.5.2
Settling Time for the External Circuit
The values for RSRC, RF and CF in the external circuitry determine the length of time required to charge
CF to the source voltage level (VSRC). At time t = 0, VSRC changes in Figure 14-50 while S1 is open,
disconnecting the internal circuitry from the external circuitry. Assume that the initial voltage across CF is
zero. As CF charges, the voltage across it is determined by the following equation, where t is the total
charge time:
As t approaches infinity, VCF will equal VSRC. (This assumes no internal leakage.) With 10-bit resolution,
1/2 of a count is equal to 1/2048 full-scale value. Assuming worst case (VSRC = full scale), Table 14-25
shows the required time for CF to charge to within 1/2 of a count of the actual source voltage during 10-bit
conversions. Table 14-25 is based on the RC network in Figure 14-50.
NOTE
The following times are completely independent of the A/D converter
architecture (assuming the QADC64E is not affecting the charging).
Table 14-25. External Circuit Settling Time to 1/2 LSB (10-Bit Conversions)
Filter Capacitor
(CF)
Source Resistance (RF + RSRC)
100 Ω
1 kΩ
10 kΩ
100 kΩ
1 µF
760 µs
7.6 ms
76 ms
760 ms
.1 µF
76 µs
760 µs
7.6 ms
76 ms
.01 µF
7.6 µs
76 µs
760 µs
7.6 ms
.001 µF
760 ns
7.6 µs
76 µs
760 µs
100 pF
76 ns
760 ns
7.6 µs
76 µs
The external circuit described in Table 14-25 is a low-pass filter. A user interested in measuring an AC
component of the external signal must take the characteristics of this filter into account.
14.6.5.3
Error Resulting from Leakage
A series resistor limits the current to a signal, therefore input leakage acting through a large source
impedance can degrade A/D accuracy. The maximum input leakage current is specified in Appendix F,
“Electrical Characteristics.” Input leakage is greater at higher operating temperatures. In the temperature
range from 125° C to 50° C, the leakage current is halved for every 8 – 12° C reduction in temperature.
Assuming VRH – VRL = 5.12 V, one count (assuming 10-bit resolution) corresponds to 5 mV of input
voltage. A typical input leakage of 200 nA acting through 10 kΩ of external series resistance results in an
error of 0.4 count (2.0 mV). If the source impedance is 100 kΩ and a typical leakage of 100 nA is present,
an error of two counts (10 mV) is introduced.
In addition to internal junction leakage, external leakage (e.g., if external clamping diodes are used) and
charge sharing effects with internal capacitors also contribute to the total leakage current. Table 14-26
illustrates the effect of different levels of total leakage on accuracy for different values of source
impedance. The error is listed in terms of 10-bit counts.
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Freescale Semiconductor
14-73
QADC64E Enhanced Mode Operation
WARNING
Leakage from the part below 200 nA is obtainable only within a limited
temperature range.
Table 14-26. Error Resulting From Input Leakage (IOFF)
Leakage Value (10-bit Conversions)
Source
Impedance
14.6.5.4
100 nA
200 nA
500 nA
1000 nA
1 kΩ
—
—
0.1 counts
0.2 counts
10 kΩ
0.2 counts
0.4 counts
1 counts
2 counts
100 kΩ
2 counts
4 count
10 counts
20 counts
Accommodating Positive/Negative Stress Conditions
Positive or negative stress refers to conditions which exceed nominally defined operating limits. Examples
include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the
suggested supply/reference ranges) or causing currents into or out of the signal which exceed normal
limits. QADC64E specific considerations are voltages greater than VDDA, VRH or less than VSSA applied to
an analog input which cause excessive currents into or out of the input. Refer to Appendix F, “Electrical
Characteristics,” to for more information on exact magnitudes.
Either stress condition can potentially disrupt conversion results on neighboring inputs. Parasitic devices,
associated with CMOS processes, can cause an immediate disruptive influence on neighboring signals.
Common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal
tied to substrate (VSSI/VSSA ground). Under stress conditions, current injected on an adjacent signal can
cause errors on the selected channel by developing a voltage drop across the selected channel’s
impedances.
Figure 14-52 shows an active parasitic bipolar NPN transistor when an input signal is subjected to negative
stress conditions. Figure 14-53 shows positive stress conditions can activate a similar PNP transistor.
VSTRESS
RSTRESS
+
IINJN
10K
RSELECTED IIN
ANn Signal Under
Stress
PARASITIC
DEVICE
ANn+1
Adjacent
Signal
VIN
QADC64E PAR
Figure 14-52. Input Signal Subjected to Negative Stress
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Freescale Semiconductor
QADC64E Enhanced Mode Operation
VSTRESS
RSTRESS IINJP
+
10K
RSELECTED IIN
ANn
Signal Under
Stress
VDDA
PARASITIC
DEVICE
ANn+1
Adjacent
Signal
VIN
QADC64E PAR
Figure 14-53. Input Signal Subjected to Positive Stress
The current into the signal (IINJN or IINJP) under negative or positive stress is determined by the following
equations:
where:
– ( V STRESS – V BE )
I INJN = -----------------------------------------------------R STRESS
Eqn. 14-1
V STRESS – V EB – V DDA
I INJP = ---------------------------------------------------------------------R STRESS
Eqn. 14-2
VSTRESS = Adjustable voltage source
VEB = Parasitic PNP emitter/base voltage
(refer to VNEGCLAMP in Appendix F, “Electrical Characteristics”)
VBE = Parasitic NPN base/emitter voltage
(refer to VNEGCLAMP in Appendix F, “Electrical Characteristics”))
RSTRESS = Source impedance
(10-kΩ resistor in Figure 14-52 and Figure 14-53 on stressed channel)
RSELECTED = Source impedance on channel selected for conversion
The current into (IIN) the neighboring signal is determined by the KN (current coupling ratio) of the
parasitic bipolar transistor (KN 127 OR RX Error > 127) AND (TX Error < 255)
128 Occurences of 11 consecutive recessive bits,
Tx Error and Rx Error are reset to 0.
TX Error > 255
Bus Off
Figure 16-6. CAN Controller State Diagram
16.3.5
Time Stamp
The value of the free-running 16-bit timer is sampled at the beginning of the identifier field on the CAN
bus. For a message being received, the time stamp is stored in the time stamp entry of the receive message
buffer at the time the message is written into that buffer. For a message being transmitted, the time stamp
entry is written into the transmit message buffer once the transmission has completed successfully.
The free-running timer can optionally be reset upon the reception of a frame into message buffer 0. This
feature allows network time synchronization to be performed.
16.4
TouCAN Operation
The basic operation of the TouCAN can be divided into four areas:
• Reset
• Initialization of the module
• Transmit message handling
• Receive message handling
Example sequences for performing each of these processes is given in the following paragraphs.
16.4.1
TouCAN Reset
The TouCAN can be reset in two ways:
• Hard reset of the module via SRESET.
• Soft reset of the module, using the SOFTRST bit in the module configuration register
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Freescale Semiconductor
CAN 2.0B Controller Module
Following the negation of reset, the TouCAN is not synchronized with the CAN bus, and the HALT, FRZ,
and FRZACK bits in the module configuration register are set. In this state, the TouCAN does not initiate
frame transmissions or receive any frames from the CAN bus. The contents of the message buffers are not
changed following reset.
Any configuration change or initialization requires that the TouCAN be frozen by either the assertion of
the HALT bit in the module configuration register or by reset.
16.4.2
TouCAN Initialization
Initialization of the TouCAN includes the initial configuration of the message buffers and configuration of
the CAN communication parameters following a reset, as well as any reconfiguration which may be
required during operation. The following is a general initialization sequence for the TouCAN:
1. Initialize all operation modes
a) Initialize the transmit and receive pin modes in CANCTRL0
b) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW in CANCTRL1 and
CANCTRL2
c) Select the S-clock rate by programming the PRESDIV register
d) Select the internal arbitration mode (LBUF bit in CANCTRL1)
2. Initialize message buffers
a) The control/status word of all message buffers must be written either as an active or inactive
message buffer.
b) All other entries in each message buffer should be initialized as required
3. Initialize mask registers for acceptance mask as required
4. Initialize TouCAN interrupt handler
a) Initialize the interrupt configuration register (CANICR) with a specific request level
b) Set the required mask bits in the IMASK register (for all message buffer interrupts), in
CANCTRL0 (for bus off and error interrupts), and in CANMCR for the WAKE interrupt
5. Negate the HALT bit in the module configuration register. At this point, the TouCAN attempts to
synchronize with the CAN bus
NOTE
In both the transmit and receive processes, the first action in preparing a
message buffer must be to deactivate the buffer by setting its code field to
the proper value. This step is mandatory to ensure data coherency.
16.4.3
Transmit Process
The transmit process includes preparation of a message buffer for transmission, as well as the internal steps
performed by the TouCAN to decide which message to transmit. This involves loading the message and
ID to be transmitted into a message buffer and then activating that buffer as an active transmit buffer. Once
this is done, the TouCAN performs all additional steps necessary to transmit the message onto the CAN
bus.
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Freescale Semiconductor
16-13
CAN 2.0B Controller Module
The user should prepare or change a message buffer for transmission by executing the following steps.
1. Write the control/status word to hold the transmit buffer inactive (code = 0b1000)
2. Write the ID_HIGH and ID_LOW words
3. Write the data bytes
4. Write the control/status word (active Tx code, Tx length)
NOTE
Steps 1 and 4 are mandatory to ensure data coherency.
Once an active transmit code is written to a transmit message buffer, that buffer begins participating in an
internal arbitration process as soon as the receiver senses that the CAN bus is free, or at the inter-frame
space. If there are multiple messages awaiting transmission, this internal arbitration process selects the
message buffer from which the next frame is transmitted.
When this process is over and a message buffer is selected for transmission, the frame from that message
buffer is transferred to the serial message buffer for transmission.
The TouCAN transmits no more than eight data bytes, even if the transmit length contains a value greater
than eight.
At the end of a successful transmission, the value of the free-running timer (which was captured at the
beginning of the identifier field on the CAN bus), is written into the time stamp field in the message buffer.
The code field in the control/status word of the message buffer is updated and a status flag is set in the
IFLAG register.
16.4.3.1
Transmit Message Buffer Deactivation
Any write access to the control/status word of a transmit message buffer during the process of selecting a
message buffer for transmission immediately deactivates that message buffer, removing it from the
transmission process.
If the transmit message buffer is deactivated while a message is being transferred from it to a serial
message buffer, the message is not transmitted.
If the transmit message buffer is deactivated after the message is transferred to the serial message buffer,
the message is transmitted, but no interrupt is requested, and the transmit code is not updated.
If a message buffer containing the lowest ID is deactivated while that message is undergoing the internal
arbitration process to determine which message should be sent, then that message may not be transmitted.
16.4.3.2
Reception of Transmitted Frames
The TouCAN receives a frame it has transmitted if an empty message buffer with a matching identifier
exists.
16.4.4
Receive Process
During the receive process, the following events occur:
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Freescale Semiconductor
CAN 2.0B Controller Module
•
•
•
The user configures the message buffers for reception
The TouCAN transfers received messages from the serial message buffers to the receive message
buffers with matching IDs
The user retrieves these messages
The user should prepare or change a message buffer for frame reception by executing the following steps.
1. Write the control/status word to hold the receive buffer inactive (code = 0b0000)
2. Write the ID_HIGH and ID_LOW words
3. Write the control/status word to mark the receive message buffer as active and empty
NOTE
Steps 1 and 3 are mandatory for data coherency.
Once these steps are performed, the message buffer functions as an active receive buffer and participates
in the internal matching process, which takes place every time the TouCAN receives an error-free frame.
In this process, all active receive buffers compare their ID value to the newly received one. If a match is
detected, the following actions occur:
1. The frame is transferred to the first (lowest entry) matching receive message buffer
2. The value of the free-running timer (captured at the beginning of the identifier field on the CAN
bus) is written into the time stamp field in the message buffer
3. The ID field, data field, and Rx length field are stored
4. The code field is updated
5. The status flag is set in the IFLAG register
The user should read a received frame from its message buffer in the following order:
1. Control/status word (mandatory, as it activates the internal lock for this buffer)
2. ID (optional, since it is needed only if a mask was used)
3. Data field word(s)
4. Free-running timer (optional, as it releases the internal lock)
If the free running timer is not read, that message buffer remains locked until the read process starts for
another message buffer. Only a single message buffer is locked at a time. When a received message is read,
the only mandatory read operation is that of the control/status word. This ensures data coherency.
If the BUSY bit is set in the message buffer code, the CPU should defer accessing that buffer until this bit
is negated. Refer to Table 16-2.
NOTE
The user should check the status of a message buffer by reading the status
flag in the IFLAG register and not by reading the control/status word code
field for that message buffer. This prevents the buffer from being locked
inadvertently.
Because the received identifier field is always stored in the matching receive message buffer, the contents
of the identifier field in a receive message buffer may change if one or more of the ID bits are masked.
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CAN 2.0B Controller Module
16.4.4.1
Receive Message Buffer Deactivation
Any write access to the control/status word of a receive message buffer during the process of selecting a
message buffer for reception immediately deactivates that message buffer, removing it from the reception
process.
If a receive message buffer is deactivated while a message is being transferred into it, the transfer is halted
and no interrupt is requested. If this occurs, that receive message buffer may contain mixed data from two
different frames.
The CPU should not write data into a receive message buffer. If this occurs while a message is being
transferred from a serial message buffer, the control/status word will reflect a full or overrun condition, but
no interrupt is requested.
16.4.4.2
Locking and Releasing Message Buffers
The lock/release/busy mechanism is designed to guarantee data coherency during the receive process. The
following examples demonstrate how the lock/release/busy mechanism affects TouCAN operation:
1. Reading a control/status word of a message buffer triggers a lock for that message buffer. A new
received message frame which matches the message buffer cannot be written into this message
buffer while it is locked.
2. To release a locked message buffer, the CPU either locks another message buffer by reading its
control/status word or globally releases any locked message buffer by reading the free-running
timer.
3. If a receive frame with a matching ID is received during the time the message buffer is locked, the
receive frame is not immediately transferred into that message buffer, but remains in the serial
message buffer. There is no indication when this occurs.
4. When a locked message buffer is released, if a frame with a matching identifier exists within the
serial message buffer, then this frame is transferred to the matching message buffer.
5. If two or more receive frames with matching IDs are received while a message buffer with a
matching ID is locked, the last received frame with that ID is kept within the serial message buffer,
while all preceding ones are lost. There is no indication when this occurs.
6. If the control/status word of a receive message buffer is read while a frame is being transferred
from a serial message buffer, the BUSY code is indicated. The user should wait until this code is
cleared before continuing to read from the message buffer to ensure data coherency. In this
situation, the read of the control/status word does not lock the message buffer.
Polling the control/status word of a receive message buffer can lock it, preventing a message from being
transferred into that buffer. If the control/status word of a receive message buffer is read, it should be
followed by a read of the control/status word of another buffer, or by a read of the free-running timer, to
ensure that the locked buffer is unlocked.
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CAN 2.0B Controller Module
16.4.5
Remote Frames
The remote frame is a message frame that is transmitted to request a data frame. The TouCAN can be
configured to transmit a data frame automatically in response to a remote frame, or to transmit a remote
frame and then wait for the responding data frame to be received.
To transmit a remote frame, a message buffer is initialized as a transmit message buffer with the RTR bit
set to one. Once this remote frame is transmitted successfully, the transmit message buffer automatically
becomes a receive message buffer, with the same ID as the remote frame that was transmitted.
When the TouCAN receives a remote frame, it compares the remote frame ID to the IDs of all transmit
message buffers programmed with a code of 1010. If there is an exact matching ID, the data frame in that
message buffer is transmitted. If the RTR bit in the matching transmit message buffer is set, the TouCAN
transmits a remote frame as a response.
A received remote frame is not stored in a receive message buffer. It is only used to trigger the automatic
transmission of a frame in response. The mask registers are not used in remote frame ID matching. All ID
bits (except RTR) of the incoming received frame must match for the remote frame to trigger a response
transmission.
16.4.6
Overload Frames
The TouCAN does not initiate overload frame transmissions unless it detects the following conditions on
the CAN bus:
• A dominant bit is the first or second bit of intermission
• A dominant bit is the seventh (last) bit of the end-of-frame (EOF) field in receive frames
• A dominant bit is the eighth (last) bit of the error frame delimiter or overload frame delimiter
16.5
Special Operating Modes
The TouCAN module has three special operating modes:
• Debug mode
• Low-power stop mode
• Auto power save mode
16.5.1
Debug Mode
Debug mode is entered when the FRZ1 bit in CANMCR is set and one of the following events occurs:
• The HALT bit in the CANMCR is set; or
• The IMB3 FREEZE line is asserted
Once entry into debug mode is requested, the TouCAN waits until an intermission or idle condition exists
on the CAN bus, or until the TouCAN enters the error passive or bus off state. Once one of these conditions
exists, the TouCAN waits for the completion of all internal activity. Once this happens, the following
events occur:
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CAN 2.0B Controller Module
•
•
•
•
•
The TouCAN stops transmitting or receiving frames
The prescaler is disabled, thus halting all CAN bus communication
The TouCAN ignores its Rx signals and drives its Tx signals as recessive
The TouCAN loses synchronization with the CAN bus and the NOTRDY and FRZACK bits in
CANMCR are set
The CPU is allowed to read and write the error counter registers
After engaging one of the mechanisms to place the TouCAN in debug mode, the FRZACK bit must be set
before accessing any other registers in the TouCAN; otherwise unpredictable operation may occur.
To exit debug mode, the IMB3 FREEZE line must be negated or the HALT bit in CANMCR must be
cleared.
Once debug mode is exited, the TouCAN resynchronizes with the CAN bus by waiting for 11 consecutive
recessive bits before beginning to participate in CAN bus communication.
16.5.2
Low-Power Stop Mode
Before entering low-power stop mode, the TouCAN waits for the CAN bus to be in an idle state, or for the
third bit of intermission to be recessive. The TouCAN then waits for the completion of all internal activity
(except in the CAN bus interface) to be complete. Then the following events occur:
• The TouCAN shuts down its clocks, stopping most internal circuits, thus achieving maximum
power savings
• The bus interface unit continues to operate, allowing the CPU to access the module configuration
register
• The TouCAN ignores its Rx signals and drives its Tx signals as recessive
• The TouCAN loses synchronization with the CAN bus, and the STOPACK and NOTRDY bits in
the module configuration register are set
To exit low-power stop mode:
• Reset the TouCAN either by asserting one of the IMB3 reset lines or by asserting the SOFTRST
bit CANMCR
• Clear the STOP bit in CANMCR
• The TouCAN module can optionally exit low-power stop mode via the self wake mechanism. If
the SELFWAKE bit in CANMCR was set at the time the TouCAN entered stop mode, then upon
detection of a recessive to dominant transition on the CAN bus, the TouCAN clears the STOP bit
in CANMCR and its clocks begin running.
When the TouCAN is in low-power stop mode, a recessive to dominant transition on the CAN bus causes
the WAKEINT bit in the error and status register (ESTAT) to be set. This event generates an interrupt if
the WAKEMSK bit in CANMCR is set.
Consider the following notes regarding low-power stop mode:
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CAN 2.0B Controller Module
•
•
•
•
•
•
•
•
•
•
When the self wake mechanism is activated, the TouCAN tries to receive the frame that woke it
up. (It assumes that the dominant bit detected is a start-of-frame bit.) It will not arbitrate for the
CAN bus at this time.
If the STOP bit is set while the TouCAN is in the bus off state, then the TouCAN enters low-power
stop mode and stops counting recessive bit times. The count continues when STOP is cleared.
To place the TouCAN in low-power stop mode with the self wake mechanism engaged, write to
CANMCR with both STOP and SELFWAKE set, and then wait for the TouCAN to set the
STOPACK bit.
To take the TouCAN out of low-power stop mode when the self wake mechanism is enabled, write
to CANMCR with both STOP and SELFWAKE clear, and then wait for the TouCAN to clear the
STOPACK bit.
The SELFWAKE bit should not be set after the TouCAN has already entered low-power stop
mode.
If both STOP and SELFWAKE are set and a recessive to dominant edge immediately occurs on the
CAN bus, the TouCAN may never set the STOPACK bit, and the STOP bit will be cleared.
To prevent old frames from being sent when the TouCAN awakes from low-power stop mode via
the self wake mechanism, disable all transmit sources, including transmit buffers configured for
remote request responses, before placing the TouCAN in low-power stop mode.
If the TouCAN is in debug mode when the STOP bit is set, the TouCAN assumes that debug mode
should be exited. As a result, it tries to synchronize with the CAN bus, and only then does it await
the conditions required for entry into low-power stop mode.
Unlike other modules, the TouCAN does not come out of reset in low-power stop mode. The basic
TouCAN initialization procedure should be executed before placing the module in low-power stop
mode. (Refer to Section 16.4.2, “TouCAN Initialization.”)
If the TouCAN is in low-power stop mode with the self wake mechanism engaged and is operating
with a single system clock per time quantum, there can be extreme cases in which the TouCAN
would wake-up on a recessive to dominant edge which may not conform to the CAN protocol.
TouCAN synchronization is shifted one time quantum from the wake-up event. This shift lasts until
the next recessive-to-dominant edge, which resynchronizes the TouCAN to be in conformance
with the CAN protocol. The same holds true when the TouCAN is in auto power save mode and
awakens on a recessive to dominant edge.
16.5.3
Auto Power Save Mode
Auto power save mode enables normal operation with optimized power savings. Once the auto power save
(APS) bit in CANMCR is set, the TouCAN looks for a set of conditions in which there is no need for the
clocks to be running. If these conditions are met, the TouCAN stops its clocks, thus saving power. The
following conditions activate auto power save mode:
• No Rx/Tx frame in progress
• No transfer of Rx/Tx frames to and from a serial message buffer, and no Tx frame awaiting
transmission in any message buffer
• No CPU access to the TouCAN module
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CAN 2.0B Controller Module
•
The TouCAN is not in debug mode, low-power stop mode, or the bus off state
While its clocks are stopped, if the TouCAN senses that any one of the aforementioned conditions is no
longer true, it restarts its clocks. The TouCAN then continues to monitor these conditions and stops or
restarts its clocks accordingly.
16.6
Interrupts
The TouCAN can generate one interrupt level to be passed to the CPU. This level is programmed into the
priority level bits in the interrupt configuration register (CANICR). This value determines which interrupt
signal is driven onto the bus when an interrupt is requested.
Each one of the 16 message buffers can be an interrupt source, if its corresponding IMASK bit is set. There
is no distinction between transmit and receive interrupts for a particular buffer. Each of the buffers is
assigned a bit in the IFLAG register. An IFLAG bit is set when the corresponding buffer completes a
successful transmission/reception. An IFLAG bit is cleared when the CPU reads IFLAG while the
associated bit is set, and then writes it back as zero (and no new event of the same type occurs between the
read and the write actions).
The other three interrupt sources (bus off, error and wake up) act in the same way, and have flag bits
located in the error and status register (ESTAT). The bus off and error interrupt mask bits (BOFFMSK and
ERRMSK) are located in CANCTRL0, and the wake up interrupt mask bit (WAKEMSK) is located in the
module configuration register. Refer to Section 16.7, “Programming Model,” for more information on
these registers.
The TouCAN module is capable of generating one of the 32 possible interrupt levels on the IMB3. The 32
interrupt levels are time multiplexed on the IMB3 IRQ[0:7] lines. All interrupt sources place their asserted
level on a time multiplexed bus during four different time slots, with eight levels communicated per slot.
The ILBS[0:1] signals indicate which group of eight are being driven on the interrupt request lines.
Table 16-9. Interrupt Levels
ILBS[0:1]
Levels
00
0:7
01
8:15
10
16:23
11
24:31
The level that the TouCAN will drive onto internal IRQ[7:0] signals is programmed in the three Interrupt
Request Level (IRL) bits located in the interrupt configuration register. The two ILBS bits in the ICR
register determine on which slot the TouCAN should drive its interrupt signal. Under the control of ILBS,
each interrupt request level is driven during the time multiplexed bus during one of four different time
slots, with eight levels communicated per time slot. No hardware priority is assigned to interrupts.
Furthermore, if more than one source on a module requests an interrupt at the same level, the system
software must assign a priority to each source requesting at that level. Figure 16-7 displays the interrupt
levels on IRQ with ILBS.
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CAN 2.0B Controller Module
IMB3 CLOCK
ILBS [1:0]
00
IMB3 IRQ [7:0]
01
10
11
00
01
IRQ
7:0
IRQ
15:8
IRQ
23:16
IRQ
31:24
IRQ
7:0
10
11
Figure 16-7. Interrupt Levels on IRQ with ILBS
16.7
Programming Model
Table 16-10 shows the TouCAN address map. The lowercase “x” appended to each register name
represents “A”, “B” or “C” for the TouCAN_A, TouCAN_B, or TouCAN_C module, respectively. Refer
to Figure 1-4 to locate each TouCAN module in the MPC561/MPC563 address map.
The column labeled “Access” indicates the privilege level at which the CPU must be operating to access
the register. A designation of “S” indicates that supervisor mode is required. A designation of “S/U”
indicates that the register can be programmed for either supervisor mode access or unrestricted access.
The address space for each TouCAN module is split, with 128 bytes starting at the base address, and an
extra 256 bytes starting at the base address +128. The upper 256 are fully used for the message buffer
structures. Of the lower 128 bytes, some are not used. Registers with bits marked as “reserved” should
always be written as logic 0.
Typically, the TouCAN control registers are programmed during system initialization, before the TouCAN
becomes synchronized with the CAN bus. The configuration registers can be changed after
synchronization by halting the TouCAN module. This is done by setting the HALT bit in the TouCAN
module configuration register (CANMCR). The TouCAN responds by asserting CANMCR[NOTRDY].
Additionally, the control registers can be modified while the MCU is in background debug mode.
NOTE
The TouCAN has no hard-wired protection against invalid bit/field
programming within its registers. Specifically, no protection is provided if
the programming does not meet CAN protocol requirements.
Table 16-10. TouCAN Register Map
Access
Address
MSB
LSB
0
15
S
0x30 7080(A)
0x30 7480(B)
0x30 7880(C)
TouCAN Module Configuration Register (CANMCR_x)
See Table 16-11 for bit descriptions.
S
0x30 7082(A)
0x30 7482(B)
0x30 7882(C)
TouCAN Test Register (CANTCR_x)
.
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CAN 2.0B Controller Module
Table 16-10. TouCAN Register Map (continued)
Access
MSB
Address
LSB
0
15
S
0x30 7084(A)
0x30 7484(B)
0x30 7884(C)
TouCAN Interrupt Register (CANICR_x)
See Table 16-12 for bit descriptions.
S/U
0x30 7086(A)
0x30 7486(B)
0x30 7886(C)
Control Register 0 (CANCTRL0_x) Control Register 1 (CANCTRL1_x)
See Table 16-13 for bit descriptions. See Table 16-16 for bit descriptions.
S/U
0x30 7088(A)
0x30 7488(B)
0x30 7888(C)
Control and Prescaler
Control Register 2 (CANCTRL2_x)
Divider Register (PRESDIV_x)
See Table 16-18 for bit descriptions.
See Table 16-17 for bit descriptions.
S/U
0x30 708A(A)
0x30 748A(B)
0x30 788A(C)
Free-Running Timer Register (TIMER_x)
See Table 16-19 for bit descriptions.
—
0x30 708C – 0x30 708E(A)
0x30 748C – 0x30 748E(B)
0x30 788C – 0x30 788E(C)
Reserved
S/U
0x30 7090(A)
0x30 7490(B)
0x30 7890(C)
Receive Global Mask – High (RXGMSKHI_x)
See Table 16-20 for bit descriptions.
S/U
0x30 7092(A)
0x30 7492(B)
0x30 7892(C)
Receive Global Mask – Low (RXGMSKLO_x)
See Table 16-20 for bit descriptions.
S/U
0x30 7094(A)
0x30 7494(B)
0x30 7894(C)
Receive Buffer 14 Mask – High (RX14MSKHI_x)
See Section 16.7.10, “Receive Buffer 14 Mask Registers (RX14MSKHI,
RX14MSKLO),” for bit descriptions.
S/U
0x30 7096(A)
0x30 7496(B)
0x30 7896(C)
Receive Buffer 14 Mask – Low (RX14MSKLO_x)
See Section 16.7.10, “Receive Buffer 14 Mask Registers (RX14MSKHI,
RX14MSKLO),” for bit descriptions.
S/U
0x30 7098(A)
0x30 7498(B)
0x30 7898(C)
Receive Buffer 15 Mask – High (RX15MSKHI_x)
See Section 16.7.11, “Receive Buffer 15 Mask Registers (RX15MSKHI,
RX15MSKLO),” for bit descriptions.
S/U
0x30 709A(A)
0x30 749A(B)
0x30 789A(C)
Receive Buffer 15 Mask – Low (RX15MSKLO_x)
See Section 16.7.11, “Receive Buffer 15 Mask Registers (RX15MSKHI,
RX15MSKLO),” for bit descriptions.
—
0x30 709C – 0x30 709E(A)
0x30 749C– 0x30 749E(B)
0x30 789C – 0x30 789E(C)
Reserved
S/U
0x30 70A0(A)
0x30 74A0(B)
0x30 78A0(C)
Error and Status Register (ESTAT_x)
See Table 16-23 for bit descriptions.
S/U
0x30 70A2(A)
0x30 74A2(B)
0x30 78A2(C)
Interrupt Masks (IMASK_x)
See Table 16-26 for bit descriptions.
S/U
0x30 70A4(A)
0x30 74A4(B)
0x30 78A4(C)
Interrupt Flags (IFLAG_x)
See Table 16-27 for bit descriptions.
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CAN 2.0B Controller Module
Table 16-10. TouCAN Register Map (continued)
Access
MSB
Address
LSB
0
15
S/U
0x30 70A6(A)
0x30 74A6(B)
0x30 78A6(C)
Receive Error Counter (RXECTR_x) Transmit Error Counter (TXECTR_x)
See Table 16-28 for bit descriptions. See Table 16-28 for bit descriptions
S/U
0x30 7100 — 0x30 710F(A)
0x30 7500 — 0x30 750F(B)
0x30 7900 — 0x30 790F(C)
MBUFF01
TouCAN X Message Buffer 0.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 7110 — 0x30 711F(A)
0x30 7510 — 0x30 751F(B)
0x30 7910 — 0x30 791F(C)
MBUFF1 1
TouCAN X Message Buffer 1.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 7120 — 0x30 712F(A)
0x30 7520 — 0x30 752F(B)
0x30 7920 — 0x30 792F(C)
MBUFF2 1
TouCAN X Message Buffer 2.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 7130 — 0x30 713F(A)
0x30 7530 — 0x30 753F(B)
0x30 7930 — 0x30 793F(C)
MBUFF3 1
TouCAN X Message Buffer 3.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 7140 — 0x30 714F(A)
0x30 7540 — 0x30 754F(B)
0x30 7940 — 0x30 794F(C)
MBUFF4 1
TouCAN X Message Buffer 4.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 7150 — 0x30 715F(A)
0x30 7550 — 0x30 755F(B)
0x30 7950 — 0x30 795F(C)
MBUFF5 1
TouCAN X Message Buffer 5.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 7160 — 0x30 716F(A)
0x30 7560 — 0x30 756F(B)
0x30 7960 — 0x30 796F(C)
MBUFF6 1
TouCAN X Message Buffer 6.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x307170 — 0x30717F(A)
0x30 7570 — 0x30 757F(B)
0x30 7970 — 0x30 797F(C)
MBUFF7 1
TouCAN X Message Buffer 7.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 7180 — 0x30 718F(A)
0x30 7580 — 0x30 758F(B)
0x30 7980 — 0x30 798F(C)
MBUFF8 1
TouCAN X Message Buffer 8.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 7190 — 0x30 719F(A)
0x30 7590 — 0x30 759F(B)
0x30 7990 — 0x30 799F(C)
MBUFF9 1
TouCAN X Message Buffer 9.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 71A0 — 0x30 71AF(A)
0x30 75A0 — 0x30 75AF(B)
0x30 79A0 — 0x30 79AF(C)
MBUFF10 1
TouCAN X Message Buffer 10.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 71B0 — 0x30 71BF(A)
0x30 75B0 — 0x30 75BF(B)
0x30 79B0 — 0x30 79BF(C)
MBUFF11 1
TouCAN X Message Buffer 11.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 71C0 — 0x30 71CF(A)
0x30 75C0 — 0x30 75CF(B)
0x30 79C0 — 0x30 79CF(C)
MBUFF12 1
TouCAN X Message Buffer 12.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 71D0 — 0x30 71DF(A)
0x30 75D0 — 0x30 75DF(B)
0x30 79D0 — 0x30 79DF(C)
MBUFF13 1
TouCAN X Message Buffer 13.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
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CAN 2.0B Controller Module
Table 16-10. TouCAN Register Map (continued)
Access
MSB
Address
LSB
0
1
15
S/U
0x30 71E0 — 0x30 71EF(A)
0x30 75E0 — 0x30 75EF(B)
0x30 79E0 — 0x30 79EF(C)
MBUFF14 1
TouCAN X Message Buffer 14.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
S/U
0x30 71F0 — 0x30 71FF(A)
0x30 75F0 — 0x30 75FF(B)
0x30 79F0 — 0x30 79FF(C)
MBUFF15 1
TouCAN X Message Buffer 15.
See Figure 16-3 and Figure 16-4 for message buffer definitions.
The last word of each of the MBUFF arrays (address 0x....E) is reserved and may cause an RCPU exception if read.
TouCAN_A, B, and C Addresses:
0x30 7100, 0x30 7500 , 0x30 7900
0x30 7102, 0x30 7502 , 0x30 7902
0x30 7104, 0x30 7504 , 0x30 7904
Control/Status
ID High
ID Low
Message Buffer 0
0x30 7106, 0x30 7506 , 0x30 7906
8-byte Data Field
0x30 710D, 0x30 750D , 0x30 790D
0x30 710E, 0x30 750E, 0x30 790E
Reserved
0x30 7110, 0x30 7510 , 0x30 7910
Message Buffers 1 – 15
, 0x30 79FF
0x30 71FF, 0x30 75FF
TouCAN Message Buffer Map
Figure 16-8. TouCAN Message Buffer Memory Map
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CAN 2.0B Controller Module
16.7.1
TouCAN Module Configuration Register (CANMCR)
MSB
LSB
0
1
2
Field STOP FRZ
—
3
4
5
6
7
8
9
HALT NOT WAKE SOFT FRZ SUPV SELF
RDY MSK RST ACK
WAKE
10
11
APS
STOP
ACK
12
13
14
15
—
0101_1001_1000_0000
SRESET
Addr
0x30 7080 (CANMCR_A); 0x30 7480 (CANMCR_B); 0x30 7880 (CANMCR_C)
Figure 16-9. TouCAN Module Configuration Register (CANMCR)
Table 16-11. CANMCR Bit Descriptions
Bits
Name
Description
0
STOP
Low-power stop mode enable. The STOP bit may only be set by the CPU. It may be cleared
either by the CPU or by the TouCAN, if the SELFWAKE bit is set.
Before asserting the STOP Mode, the CPU should disable all interrupts in the TOUCAN,
otherwise it may be interrupted while in STOP mode upon a non wake-up condition.
WAKE-INT can still be enabled by setting WAKEMSK.
0 Enable TouCAN clocks
1 Disable TouCAN clocks
1
FRZ
FREEZE assertion response. When FRZ = 1, the TouCAN can enter debug mode when the
IMB3 FREEZE line is asserted or the HALT bit is set. Clearing this bit field causes the
TouCAN to exit debug mode. Refer to Section 16.5.1, “Debug Mode” for more information.
0 TouCAN ignores the IMB3 FREEZE signal and the HALT bit in the module configuration
register.
1 TouCAN module enabled to enter debug mode.
2
—
3
HALT
Halt TouCAN S-Clock. Setting the HALT bit has the same effect as assertion of the IMB3
FREEZE signal on the TouCAN without requiring that FREEZE be asserted. This bit is set to
one after reset. It should be cleared after initializing the message buffers and control
registers. TouCAN message buffer receive and transmit functions are inactive until this bit is
cleared.
When HALT is set, write access to certain registers and bits that are normally read-only is
allowed.
0 The TouCAN operates normally
1 TouCAN enters debug mode if FRZ = 1
4
NOTRDY
TouCAN not ready. This bit indicates that the TouCAN is either in low-power stop mode or
debug mode. This bit is read-only and is set only when the TouCAN enters low-power stop
mode or debug mode. It is cleared once the TouCAN exits either mode, either by
synchronization to the CAN bus or by the self wake mechanism.
0 TouCAN has exited low-power stop mode or debug mode.
1 TouCAN is in low-power stop mode or debug mode.
5
WAKEMSK
Reserved
Wakeup interrupt mask. The WAKEMSK bit enables wake-up interrupt requests.
0 Wake up interrupt is disabled
1 Wake up interrupt is enabled
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-25
CAN 2.0B Controller Module
Table 16-11. CANMCR Bit Descriptions (continued)
Bits
Name
Description
6
SOFTRST
Soft reset. When this bit is asserted, the TouCAN resets its internal state machines
(sequencer, error counters, error flags, and timer) and the host interface registers
(CANMCR, CANICR, CANTCR, IMASK, and IFLAG).
The configuration registers that control the interface with the CAN bus are not changed
(CANCTRL[0:2] and PRESDIV). Message buffers and receive message masks are also not
changed. This allows SOFTRST to be used as a debug feature while the system is running.
Setting SOFTRST also clears the STOP bit in CANMCR.
After setting SOFTRST, allow one complete bus cycle to elapse for the internal TouCAN
circuitry to completely reset before executing another access to CANMCR.
The TouCAN clears this bit once the internal reset cycle is completed.
0 Soft reset cycle completed
1 Soft reset cycle initiated
7
FRZACK
TouCAN disable. When the TouCAN enters debug mode, it sets the FRZACK bit. This bit
should be polled to determine if the TouCAN has entered debug mode. When debug mode
is exited, this bit is negated once the TouCAN prescaler is enabled. This is a read-only bit.
0 The TouCAN has exited debug mode and the prescaler is enabled
1 The TouCAN has entered debug mode, and the prescaler is disabled
8
SUPV
Supervisor/user data space. The SUPV bit places the TouCAN registers in either supervisor
or user data space.
0 Registers with access controlled by the SUPV bit are accessible in either user or
supervisor privilege mode
1 Registers with access controlled by the SUPV bit are restricted to supervisor mode
9
SELFWAKE
Self wake enable. This bit allows the TouCAN to wake up when bus activity is detected after
the STOP bit is set. If this bit is set when the TouCAN enters low-power stop mode, the
TouCAN will monitor the bus for a recessive to dominant transition. If a recessive to dominant
transition is detected, the TouCAN immediately clears the STOP bit and restarts its clocks.
If a write to CANMCR with SELFWAKE set occurs at the same time a recessive-to-dominant
edge appears on the CAN bus, the bit will not be set, and the module clocks will not stop.
The user should verify that this bit has been set by reading CANMCR. Refer to
Section 16.5.2, “Low-Power Stop Mode” for more information on entry into and exit from
low-power stop mode.
0 Self wake disabled
1 Self wake enabled
10
APS
Auto power save. The APS bit allows the TouCAN to automatically shut off its clocks to save
power when it has no process to execute, and to automatically restart these clocks when it
has a task to execute without any CPU intervention.
0 Auto power save mode disabled; clocks run normally
1 Auto power save mode enabled; clocks stop and restart as needed
11
STOPACK
Stop acknowledge. When the TouCAN is placed in low-power stop mode and shuts down its
clocks, it sets the STOPACK bit. This bit should be polled to determine if the TouCAN has
entered low-power stop mode. When the TouCAN exits low-power stop mode, the STOPACK
bit is cleared once the TouCAN’s clocks are running.
0 The TouCAN is not in low-power stop mode and its clocks are running
1 The TouCAN has entered low-power stop mode and its clocks are stopped
12:15
—
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TouCAN
implementations that use hardware interrupt arbitration.
MPC561/MPC563 Reference Manual, Rev. 1.2
16-26
Freescale Semiconductor
CAN 2.0B Controller Module
16.7.2
TouCAN Test Configuration Register
CANTCR — TouCAN Test Configuration Register0x30 7082, 0x30 7482, 0x30 7882
This register is used for factory test only.
16.7.3
TouCAN Interrupt Configuration Register (CANICR)
MSB
LSB
0
1
Field
2
3
4
5
—
6
7
8
IRL
SRESET
9
10
11
12
ILBS
14
15
—
0000_0000_00
Addr
13
00_1111
0x30 7084 (CANICR_A); 0x30 7484 (CANICR_B); 0x30 7884 (CANICR_C)
Figure 16-10. TouCAN Interrupt Configuration Register (CANICR)
Table 16-12. CANICR Bit Descriptions
Bits
Name
0:4
—
Reserved
5:7
IRL
Interrupt request level. When the TouCAN generates an interrupt request, this field
determines which of the interrupt request signals is asserted.
8:9
ILBS
10:15
—
16.7.4
Description
Interrupt level byte select. This field selects one of four time-multiplexed slots during which
the interrupt request is asserted. The ILBS and IRL fields together select one of 32 effective
interrupt levels.
00 Levels 0 to7
01 Levels 8 to 15
10 Levels 16 to 23
11 Levels 24 to 31
Reserved
Control Register 0 (CANCTRL0)
MSB
0
LSB
1
2
Field BOFFMSK ERRMSK
SRESET
Addr
3
—
4
5
RXMODE
6
7
8
TXMODE
9
10
11
12
13
14
15
CANCTRL1
0000_0000_0000_0000
0x30 7086 (CANCTRL0_A); 0x30 7486 (CANCTRL0_B); 0x30 7886 (CANCTRL0_C)
Figure 16-11. Control Register 0 (CANCTRL0)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-27
CAN 2.0B Controller Module
Table 16-13. CANCTRL0 Bit Descriptions
Bits
Name
Description
0
BOFFMSK
Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt.
0 Bus off interrupt disabled
1 Bus off interrupt enabled
1
ERRMSK
Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt.
0 Error interrupt disabled
1 Error interrupt enabled
2:3
—
4:5
RXMODE
Receive signal configuration control. These bits control the configuration of the CNRX0
signals. Refer to Table 16-14.
6:7
TXMODE
Transmit signal configuration control. This bit field controls the configuration of the CNTX0
signals. Refer to Table 16-15.
8:15
CANCTRL1
Reserved
See Table 16-16 and Section 16.7.5, “Control Register 1 (CANCTRL1).”
Table 16-14. Rx MODE[1:0] Configuration
Signal
RX1
RX0
X
0
0 CNRX0 signal is interpreted as a dominant bit
1 CNRX0 signal is interpreted as a recessive bit
X
1
0 CNRX0 signal is interpreted as a recessive bit
1 CNRX0 signal is interpreted as a dominant bit
CNRX0
Receive Signal Configuration
Table 16-15. Transmit Signal Configuration
TXMODE[1:0]
1
2
16.7.5
TransmitSignal Configuration
00
Full CMOS1; positive polarity (CNTX0 = 0 is a dominant level)
01
Full CMOS1; negative polarity (CNTX0 = 1 is a dominant level)
1X
Open drain2; positive polarity
Full CMOS drive indicates that both dominant and recessive levels are driven by the chip.
Open drain drive indicates that only a dominant level is driven by the chip. During a recessive
level, the CNTX0 signal is disabled (three stated), and the electrical level is achieved by external
pull-up/pull-down devices. The assertion of both Tx mode bits causes the polarity inversion to be
cancelled (open drain mode forces the polarity to be positive).
Control Register 1 (CANCTRL1)
MSB
0
Field
SRESET
Addr
LSB
1
2
3
4
CANCTRL0
5
6
7
8
9
SAMP
—
10
11
TSYNC LBUF
12
—
13
14
15
PROPSEG
0000_0000_0000_0000
0x30 7086 (CANCTRL1_A); 0x30 7486 (CANCTRL1_B); 0x30 7886 (CANCTRL1_C)
Figure 16-12. Control Register 1 (CANCTRL1)
MPC561/MPC563 Reference Manual, Rev. 1.2
16-28
Freescale Semiconductor
CAN 2.0B Controller Module
Table 16-16. CANCTRL1 Bit Descriptions
Bits
Name
0:7
CANCTRL0
8
SAMP
9
—
10
TSYNC
11
LBUF
12
—
13:15
PROPSEG
16.7.6
Description
See Table 16-13
Sampling mode. The SAMP bit determines whether the TouCAN module will sample each
received bit one time or three times to determine its value.
0 One sample, taken at the end of phase buffer segment one, is used to determine the value
of the received bit.
1 Three samples are used to determine the value of the received bit. The samples are taken
at the normal sample point and at the two preceding periods of the S-clock.
Reserved
Timer synchronize mode. The TSYNC bit enables the mechanism that resets the
free-running timer each time a message is received in message buffer zero. This feature
provides the means to synchronize multiple TouCAN stations with a special “SYNC”
message (global network time).
0 Timer synchronization disabled.
1 Timer synchronization enabled.
Note: there can be a bit clock skew of four to five counts between different TouCAN modules
that are using this feature on the same network.
Lowest buffer transmitted first. The LBUF bit defines the transmit-first scheme.
0 Message buffer with lowest ID is transmitted first.
1 Lowest numbered buffer is transmitted first.
Reserved
Propagation segment time. PROPSEG defines the length of the propagation segment in the
bit time. The valid programmed values are zero to seven. The propagation segment time is
calculated as follows:
Propagation Segment Time = (PROPSEG + 1) Time Quanta
where
1 Time Quantum = 1 Serial Clock (S-Clock) Period
Prescaler Divide Register (PRESDIV)
MSB
0
Field
SRESET
Addr
LSB
1
2
3
4
5
6
7
8
9
10
PRESDIV
11
12
13
14
15
CANCTRL2
0000_0000_0000_0000
0x30 7088 (PRESDIV_A); 0x30 7488 (PRESDIV_B); 0x30 7888 (PRESDIV_C)
Figure 16-13. Prescaler Divide Register
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-29
CAN 2.0B Controller Module
Table 16-17. PRESDIV Bit Descriptions
Bits
Name
Description
0:7
PRESDIV
Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency
and the serial clock (S-clock). The S-clock is determined by the following calculation:
f SYS
S-clock = -----------------------------------Eqn. 16-1
PRESDIV + 1
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same
frequency as the system clock. The valid programmed values are 0 through 255.
8:15
16.7.7
CANCTRL2
See Table 16-18.
Control Register 2 (CANCTRL2)
MSB
0
LSB
1
Field
2
3
4
PRESDIV
SRESET
5
6
7
8
9
10
RJW
11
PSEG1
12
13
14
15
PSEG2
0000_0000_0000_0000
Addr
0x30 7088 (CANCTRL2_A); 0x30 7488 (CANCTRL2_B); 0x30 7888 (CANCTRL2_C)
Figure 16-14. Control Register 2 (CANCTRL2)
Table 16-18. CANCTRL2 Bit Descriptions
Bits
Name
Description
0:7
PRESDIV
8:9
RJW
Resynchronization jump width. The RJW field defines the maximum number of time quanta
a bit time may be changed during resynchronization. The valid programmed values are zero
through three.
The resynchronization jump width is calculated as follows:
Resynchronizaton Jump Width = (RJW + 1) Time Quanta
10:12
PSEG1
PSEG1[2:0] — Phase buffer segment 1. The PSEG1 field defines the length of phase buffer
segment one in the bit time. The valid programmed values are zero through seven.
The length of phase buffer segment 1 is calculated as follows:
Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta
13:15
PSEG2
PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer
segment two in the bit time. The valid programmed values are zero through seven.
The length of phase buffer segment two is calculated as follows:
Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta
See Table 16-17.
MPC561/MPC563 Reference Manual, Rev. 1.2
16-30
Freescale Semiconductor
CAN 2.0B Controller Module
16.7.8
Free Running Timer (TIMER)
MSB
LSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
15
TIMER
SRESET
0000_0000_0000_0000
Addr
0x30 708A (TIMER_A); 0x30 748A (TIMER_B); 0x30 788A (TIMER_C)
Figure 16-15. Free Running Timer Register (TIMER)
Table 16-19. TIMER Bit Descriptions
Bits
Name
Description
0:15
TIMER
The free running timer counter can be read and written by the CPU. The timer starts from
zero after reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the TouCAN bit-clock. During a message, it increments by one for
each bit that is received or transmitted. When there is no message on the bus, it increments
at the nominal bit rate.
The timer value is captured at the beginning of the identifier field of any frame on the CAN
bus. The captured value is written into the “time stamp” entry in a message buffer after a
successful reception or transmission of a message.
16.7.9
Receive Global Mask Registers (RXGMSKHI, RXGMSKLO)
MSB
0
1
2
3
4
5
6
7
8
9
10
Field MID MID MID MID MID MID MID MID MID MID MID
28
27
26
25
24
23
22
21
20
19
18
SRESET
1
Addr
1
1
1
1
1
1
1
1
1
1
11
12
0
1
0
1
13
14
15
MID MID MID
17 16 15
1
1
1
0x30 7090 (RxGMSKHI_A); 0x30 7490 (RxGMSKHI_B); 0x30 7890 (RxGMSKHI_C);
0x30 7092 (RxGMSKLO_A); 0x30 7492 (RxGMSKLO_B); 0x30 7892 (RxGMSKLO_C)
LSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Field MID MID MID MID MID MID MID MID MID MID MID MID MID MID MID
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
31
0
0
Figure 16-16. Receive Global Mask Register: High (RXGMSKHI), Low (RXGMSKLO)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-31
CAN 2.0B Controller Module
Table 16-20. RXGMSKHI, RXGMSKLO Bit Descriptions
Bits
Name
Description
0:31
MIDx
The receive global mask registers use four bytes. The mask bits are applied to all
receive-identifiers, excluding receive-buffers 14 and 15, which have their own specific mask
registers.
Base ID mask bits MID[28:18] are used to mask standard or extended format frames.
Extended ID bits MID[17:0] are used to mask only extended format frames.
The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
message buffer ID field. However, remote request frames (RTR = 1) once received, are never
stored into the message buffers. RTR mask bit locations in the mask registers (bits 11 and
31) are always zero, regardless of any write to these bits.
The IDE bit of a received frame is always compared to determine if the message contains a
standard or extended identifier. Its location in the mask registers (bit 12) is always one,
regardless of any write to this bit.
16.7.10 Receive Buffer 14 Mask Registers (RX14MSKHI, RX14MSKLO)
The receive buffer 14 mask registers have the same structure as the receive global mask registers and are
used to mask buffer 14.
MSB
0
1
2
3
4
5
6
7
8
9
10
Field MID2 MID2 MID2 MID2 MID2 MID2 MID2 MID2 MID2 MID1 MID1
8
7
6
5
4
3
2
1
0
9
8
SRESET
1
Addr
1
1
1
1
1
1
1
1
1
1
11
12
0
1
0
1
13
14
15
MID MID MID
17
16
15
1
1
1
0x30 7094 (Rx14MSKHI_A); 0x30 7494 (Rx14MSKHI_B); 0x30 7894 (Rx14MSKHI_C);
0x30 7096 (Rx14MSKLO_A); 0x30 7496 (Rx14MSKLO_B); 0x30 7896 (Rx14MSKLO_C)
LSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Field MID1 MID1 MID1 MID1 MID1 MID9 MID8 MID7 MID6 MID5 MID4 MID3 MID2 MID MID
4
3
2
1
0
1
0
SRESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
31
0
0
Figure 16-17. Receive Buffer 14 Mask Registers: High (RX14MSKHI), Low (RX14MSKLO)
Table 16-21. RX14MSKHI, RX14MSKLO Field Descriptions
Bits
Name
Description
0:31
MIDx
The receive buffer 14 mask registers use 4 bytes.
Base ID mask bits MID[28:18] are used to mask standard or extended format frames.
Extended ID bits MID[17:0] are used to mask only extended format frames.
The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
message buffer ID field. However, remote request frames (RTR = 1) once received, are never
stored into the message buffers. RTR mask bit locations in the mask registers (bits 11 and
31) are always zero, regardless of any write to these bits.
The IDE bit of a received frame is always compared to determine if the message contains a
standard or extended identifier. Its location in the mask registers (bit 12) is always one,
regardless of any write to this bit.
MPC561/MPC563 Reference Manual, Rev. 1.2
16-32
Freescale Semiconductor
CAN 2.0B Controller Module
16.7.11 Receive Buffer 15 Mask Registers (RX15MSKHI, RX15MSKLO)
The receive buffer 15 mask registers have the same structure as the receive global mask registers and are
used to mask buffer 15.
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
0
1
0
1
Field MID MID MID MID MID MID MID MID MID MID MID
28
27
26
25
24
23
22
21
20
19
18
1
SRESET
Addr
1
1
1
1
1
1
1
1
1
1
13
14
15
MID MID MID
17 16 15
1
1
1
0x30 7098 (Rx15MSKHI_A); 0x30 7498 (Rx15MSKHI_B); 0x30 7898 (Rx14MSKHI_C);
0x30 709A (Rx14MSKLO_A); 0x30 749A (Rx14MSKLO_B); 0x30 789A (Rx14MSKLO_C)
LSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field MID MID MID MID MID MID MID MID MID MID MID MID MID MID MID
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
SRESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
Figure 16-18. Receive Buffer 15 Mask Registers: High (RX15MSKHI), Low (RX15MSKLO)
Table 16-22. RX15MSKHI, RX15MSKLO Field Descriptions
Bits
Name
Description
0:31
MIDx
The receive buffer 14 mask registers use 4 bytes.
Base ID mask bits MID[28:18] are used to mask standard or extended format frames.
Extended ID bits MID[17:0] are used to mask only extended format frames.
The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
message buffer ID field. However, remote request frames (RTR = 1) once received, are never
stored into the message buffers. RTR mask bit locations in the mask registers (bits 11 and
31) are always zero, regardless of any write to these bits.
The IDE bit of a received frame is always compared to determine if the message contains a
standard or extended identifier. Its location in the mask registers (bit 12) is always one,
regardless of any write to this bit.
16.7.12 Error and Status Register (ESTAT)
MSB
0
Field
LSB
1
BIT
ERR
2
3
4
5
6
7
8
9
10
ACK CRC FORM STUFF TX
RX IDLE TX/RX
ERR ERR ERR
ERR WARN WARN
SRESET
Addr
11
FCS
12
—
13
14
15
BOFF ERR WAKE
INT
INT
INT
0000_0000_0000_0000
0x30 70A0 (ESTAT_A); 0x30 74A0 (ESTAT_B); 0x30 78A0 (ESTAT_C)
Figure 16-19. Error and Status Register (ESTAT)
This register reflects various error conditions, general status, and has the enable bits for three of the
TouCAN interrupt sources. The reported error conditions are those which have occurred since the last time
the register was read. A read clears these bits to zero.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-33
CAN 2.0B Controller Module
Table 16-23. ESTAT Bit Descriptions
Bits
Name
Description
0:1
BITERR
Transmit bit error. The BITERR[1:0] field is used to indicate when a transmit bit error occurs.
Refer to Table 16-24.
NOTE: The transmit bit error field is not modified during the arbitration field or the ACK slot
bit time of a message, or by a transmitter that detects dominant bits while sending a passive
error frame.
2
ACKERR
Acknowledge error. The ACKERR bit indicates whether an acknowledgment has been
correctly received for a transmitted message.
0 No ACK error was detected since the last read of this register
1 An ACK error was detected since the last read of this register
3
CRCERR
Cyclic redundancy check error. The CRCERR bit indicates whether or not the CRC of the
last transmitted or received message was valid.
0 No CRC error was detected since the last read of this register
1 A CRC error was detected since the last read of this register
4
FORMERR
Message format error. The FORMERR bit indicates whether or not the message format of
the last transmitted or received message was correct.
0 No format error was detected since the last read of this register
1 A format error was detected since the last read of this register
5
STUFFERR
Bit stuff error. The STUFFERR bit indicates whether or not the bit stuffing that occurred in
the last transmitted or received message was correct.
0 No bit stuffing error was detected since the last read of this register
1 A bit stuffing error was detected since the last read of this register
6
TXWARN
Transmit error status flag. The TXWARN status flag reflects the status of the TouCAN
transmit error counter.
0 Transmit error counter < 96
1 Transmit error counter ≥ 96
7
RXWARN
Receiver error status flag. The RXWARN status flag reflects the status of the TouCAN
receive error counter.
0 Receive error counter < 96
1 Receive error counter ≥ 96
8
IDLE
9
TX/RX
Transmit/receive status. The TX/RX bit indicates when the TouCAN module is transmitting or
receiving a message. TX/RX has no meaning when IDLE = 1.
0 The TouCAN is receiving a message if IDLE = 0
1 The TouCAN is transmitting a message if IDLE = 0
10:11
FCS
Fault confinement state. The FCS[1:0] field describes the state of the TouCAN. Refer to
Table 16-25.
If the SOFTRST bit in CANMCR is asserted while the TouCAN is in the bus off state, the error
and status register is reset, including FCS[1:0]. However, as soon as the TouCAN exits reset,
FCS[1:0] bits will again reflect the bus off state. Refer to Section 16.3.4, “Error Counters” for
more information on entry into and exit from the various fault confinement states.
12
—
Idle status. The IDLE bit indicates when there is activity on the CAN bus.
0 The CAN bus is not idle
1 The CAN bus is idle
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
16-34
Freescale Semiconductor
CAN 2.0B Controller Module
Table 16-23. ESTAT Bit Descriptions (continued)
Bits
Name
Description
13
BOFFINT
Bus off interrupt. The BOFFINT bit is used to request an interrupt when the TouCAN enters
the bus off state.
0 No bus off interrupt requested
1 When the TouCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in
CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after
reset.
14
ERRINT
Error Interrupt. The ERRINT bit is used to request an interrupt when the TouCAN detects a
transmit or receive error.
0 No error interrupt request
1 If an event which causes one of the error bits in the error and status register to be set
occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt
request is generated.
To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect.
15
WAKEINT
Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the
TouCAN module is in low-power stop mode.
0 No wake interrupt requested
1 When the TouCAN is in low-power stop mode and a recessive to dominant transition is
detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an
interrupt request is generated.
Table 16-24. Transmit Bit Error Status
BITERR[1:0]
00
Bit Error Status
No transmit bit error
01
At least one bit sent as dominant was received as recessive
10
At least one bit sent as recessive was received as dominant
11
Not used
Table 16-25. Fault Confinement State Encoding
FCS[1:0]
Bus State
00
Error active
01
Error passive
1X
Bus off
16.7.13 Interrupt Mask Register (IMASK)
MSB
0
LSB
1
Field
SRESET
Addr
2
3
4
5
6
7
8
9
10
IMASKH
11
12
13
14
15
IMASKL
0000_0000_0000_0000
0x30 70A2 (IMASK_A); 0x30 74A2 (IMASK_B); 0x30 78A2 (IMASK_C)
Figure 16-20. Interrupt Mask Register (IMASK)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-35
CAN 2.0B Controller Module
Table 16-26. IMASK Bit Descriptions
Bits
Name
Description
0:7,
8:15
IMASKH,
IMASKL
IMASK contains two 8-bit fields, IMASKH and IMASKL. IMASK can be accessed with a 16-bit
read or write, and IMASKH and IMASKL can be accessed with byte reads or writes.
IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which
buffers will generate interrupts after successful transmission/reception. Setting a bit in
IMASK enables interrupt requests for the corresponding message buffer.
16.7.14 Interrupt Flag Register (IFLAG)
MSB
0
LSB
1
2
Field
3
4
5
6
7
8
9
10
IFLAGH
11
12
13
14
15
IFLAGL
SRESET
0000_0000_0000_0000
Addr
0x30 70A4 (IFLAG_A); 0x30 74A4 (IFLAG_B); 0x30 78A4 (IFLAG_C)
Figure 16-21. Interrupt Flag Register (IFLAG)
Table 16-27. IFLAG Bit Descriptions
Bits
Name
Description
0:7,
8:15
IFLAGH,
IFLAGL
IFLAG contains two 8-bit fields, IFLAGH and IFLAGL. IFLAG can be accessed with a 16-bit
read or write, and IFLAGH and IFLAGL can be accessed with byte reads or writes.
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets
the corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request
will be generated.
To clear an interrupt flag, first read the flag as a one, and then write it as a zero. Should a
new flag setting event occur between the time that the CPU reads the flag as a one and
writes the flag as a zero, the flag is not cleared. This register can be written to zeros only.
16.7.15 Error Counters (RXECTR, TXECTR)
MSB
0
LSB
1
2
Field
4
5
6
7
8
9
10
RXECTR
SRESET
Addr
3
11
12
13
14
15
TXECTR
0000_0000_0000_0000
0x30 70A6 (RxECTR_A/TxECTR_A); 0x30 74A6 (RxECTR_B/TxECTR_B); 0x30 78A6
(TxECTR_C/TxECTR_C)
Figure 16-22. Receive Error Counter (RXECTR), Transmit Error Counter (TXECTR)
Table 16-28. RXECTR, TXECTR Bit Descriptions
Bits
Name
0:7,
8:15
RXECTR,
TXECTR
Description
Both counters are read only, except when the TouCAN is in test or debug mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
16-36
Freescale Semiconductor
CAN 2.0B Controller Module
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-37
CAN 2.0B Controller Module
MPC561/MPC563 Reference Manual, Rev. 1.2
16-38
Freescale Semiconductor
Chapter 17
Modular Input/Output Subsystem (MIOS14)
The modular I/O system (MIOS) consists of a library of flexible I/O and timer functions including I/O port,
counters, input capture, output compare, pulse and period measurement, and PWM. Because the MIOS14
is composed of submodules, it is easily configurable for different kinds of applications.
The MIOS14 is composed of the following submodules:
• One MIOS14 bus interface submodule (MBISM)
• One MIOS14 counter prescaler submodule (MCPSM)
• Six MIOS14 modulus counter submodules (MMCSM)
• 10 MIOS14 double action submodules (MDASM)
• 12 MIOS14 pulse-width modulation submodules (MPWMSM)
• One MIOS14 16-bit parallel port I/O submodule (MPIOSM)
• Two interrupt request submodules (MIRSM)
17.1
Block Diagram
Figure 17-1 is a block diagram of the MIOS14.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-1
Modular Input/Output Subsystem (MIOS14)
Channel and
I/O Signals:
MDA12
MDA11
MDA31
MDA30
PWM17
PWM16
MDA14
MDA13
MDA28
MDA27
PWM19
PWM18
Channel and
I/O Signals:
CB7
CB6
CB24
CB23
CB22
CB8
16-Bit Counter Bus Set
MDASM 11
Double Action
MDA11
MDASM12
Double Action
MDA12
MDASM13
Double Action
MDA13
MDASM14
Double Action
MDA14
L
MMCSM8
C Modulus Counter
MDASM15
Double Action
MDA15
L MMCSM22
C Modulus Counter
MDASM 27
Double Action
MDA27
MDASM28
Double Action
MDA28
MDASM29
Double Action
MDA29
MDASM30
Double Action
MDA30
MDASM31
Double Action
MDA31
PWMSM0
PWM
MPWM0
L
MMCSM6
C Modulus Counter
L
MMCSM7
C Modulus Counter
L MMCSM23
C Modulus Counter
L MMCSM24
C Modulus Counter
6xPWMSM
Modular I/O Bus (MIOB)
(To all submodules)
Bus Interface
Unit Submodule
IMB3 Bus
PWMSM5
PWM
MPWM5
MPWMSM16
PWM
MPWM16
6xPWMSM
MIRSM0/1
Interrupt
Submodules
MCPSM
Counter
Prescaler
PWMSM21
PWM
MPWM21
MPIO32B0
MPIOSM32
MPIO32B15
Figure 17-1. MPC561/MPC563 MIOS14 Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
17-2
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
17.2
MIOS14 Key Features
The basic features of the MIOS14 are as follows:
• Modular architecture at the silicon implementation level
• Disable capability in each submodule to allow power saving when its function is not needed
• Six 16-bit counter buses to allow action submodules to use counter data
• When not used for timing functions, every channel signal can be used as a port signal: I/O, output
only or input only, depending on the channel function.
• Submodules’ signal status bits reflect the status of the signal
• MIOS14 counter prescaler submodule (MCPSM):
— Centralized counter clock generator
— Programmable 4-bit modulus down-counter
— Wide range of possible division ratios: 2 through 16
— Count inhibit under software control
• MIOS14 modulus counter submodule (MMCSM):
— Programmable 16-bit modulus up-counter with built-in programmable 8-bit prescaler clocked
by MCPSM output.
— Maximum increment frequency of the counter:
– Clocked by the internal MCPSM output: fSYS / 2
– Clocked by the external signal: fSYS / 4
— Flag setting and possible interrupt generation on overflow of the up-counter
— Time counter on internal clock with interrupt capability after a pre-determined time
— Optional signal usable as an external event counter (pulse accumulator) with overflow and
interrupt capability after a pre-determined number of external events.
— Usable as a regular free-running up-counter
— Capable of driving a dedicated 16-bit counter bus to provide timing information to action
submodules (the value driven is the contents of the 16-bit up-counter register)
— Optional signal to externally force a load to the counter with modulus value
• MIOS14 double action submodule (MDASM):
— Versatile 16-bit dual action unit allowing two events to occur before software intervention is
required
— Six software selectable modes allowing the MDASM to perform pulse width and period
measurements, PWM generation, single input capture and output compare operations as well
as port functions
— Software selection of one of the six possible 16-bit counter buses used for timing operations
— Flag setting and possible interrupt generation after MDASM action completion
— Software selection of output pulse polarity
— Software selection of totem-pole or open-drain output
— Software readable output signal status
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-3
Modular Input/Output Subsystem (MIOS14)
•
•
— Possible use of signal as I/O port when MDASM function is not needed
MIOS14 pulse width modulation submodule (MPWMSM):
— Output pulse width modulated (PWM) signal generation with no software involvement
— Built-in 8-bit programmable prescaler clocked by the MCPSM
— PWM period and pulse width values provided by software:
– Double-buffered for glitch-free period and pulse width changes
– Two-cycle minimum output period/pulse-width increment
(50 ns @ 40 MHz)
– 50% duty-cycle output maximum frequency: 10 MHz
– Up to 16 bits output pulse width resolution
– Wide range of periods:
• 16 bits of resolution: period range from 3.27 ms (with 50-ns steps) to
6.71 s (with 102.4 µs steps)
• Eight bits of resolution: period range from 12.8 µs (with 50-ns steps) to
26.2 ms (with 102.4-µs steps)
– Wide range of frequencies:
• Maximum output frequency at fSYS = 40 MHz with 16 bits of resolution
and divide-by-2 prescaler selection: 305 Hz (3.27 ms)
• Minimum output frequency at fSYS = 40 MHz with 16 bits of resolution
and divide-by-4096 prescaler selection: 0.15 Hz (6.7 s)
• Maximum output frequency at fSYS = 40 MHz with eight bits of
resolution and divide-by-2 prescaler selection: 78125 Hz (12.8 µs)
• Minimum output frequency at fSYS = 40 MHz with 8 bits of resolution
and divide-by-4096 prescaler selection: 38.14 Hz (8.2 ms)
— Programmable duty cycle from 0% to 100%
— Possible interrupt generation after every period
— Software selectable output pulse polarity
— Software readable output signal status
— Possible use of signal as I/O port when PWM function is not needed
MIOS14 16-bit parallel port I/O submodule (MPIOSM):
— Up to 16 parallel I/O signals per MPIOSM
— Uses four 16-bit registers in the address space, one for data and one for direction and two
reserved
— Simple data direction register (DDR) concept for selection of signal direction
17.2.1
Submodule Numbering, Naming, and Addressing
A block is a group of four 16-bit registers. Each of the blocks within the MIOS14 addressing range is
assigned a block number. The first block is located at the base address of the MIOS14. The blocks are
numbered sequentially starting from 0.
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Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Every submodule instantiation is also assigned a number. The number of a given submodule is the block
number of the first block of this submodule.
A submodule is assigned a name made of its acronym followed by its submodule number. For example, if
submodule number 18 were an MPWMSM, it would be named MPWMSM18.
This numbering convention does not apply to the MBISM, the MCPSM, and the MIRSMs. The MBISM
and the MCPSM are unique in the MIOS14 and do not need a number. The MIRSMs are numbered
incrementally starting from zero.
The MIOS14 base address is defined at the chip level and is referred to as the “MIOS14 base address.”
The MIOS14 addressable range is four Kbytes.
The base address of a given implemented submodule within the MIOS14 is the sum of the base address of
the MIOS14 and the submodule number multiplied by eight. Refer to Table 17-1.
This does not apply to the MBISM, the MCPSM and the MIRSMs. For these submodules, refer to the
MIOS14 memory map in Figure 17-2.
17.2.2
Signal Naming Convention
In Figure 17-2, MDASM signals have a prefix MDA, MPWMSM signals have a prefix of MPWM and the
port signals have a prefix of MPIO. The modulus counter clock and load signals are multiplexed with
MDASM signals.
The MIOS14 input and output signal names are composed of five fields according to the following
convention:
• “M”
•
•
• (optional)
• (optional)
The signal prefix and suffix for the different MIOS14 submodules are as follows:
• MMCSM:
— submodule short_prefix: “MC”
— signal attribute suffix: C for the clock signal
— signal attribute suffix: L for the load signal
— For example, an MMCSM placed as submodule number n would have its corresponding input
clock pin named MMCnC and its input load pin named MMCnL. MMC6C is input on MDA11
and MMC22C is input on MDA13. The MMC6L is input on MDA12 and MMC22C is input
on MDA14.
• MDASM:
— submodule short_prefix: “DA”
— signal attribute suffix: none
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-5
Modular Input/Output Subsystem (MIOS14)
•
•
— For example a MDASM placed as submodule number n would have its corresponding channel
I/O signal named MDAn
MPWMSM:
— submodule short_prefix: “PWM”
— signal attribute suffix: none
— For example a MPWMSM placed as submodule number n would have its corresponding
channel I/O signal named MPWMn
MPIOSM:
— submodule short_prefix: “PIO”
— signal attribute suffix: B
— For example a MPIOSM placed as submodule number n would have its corresponding I/O
signals named MPIOnB0 to MPIOnB15 for bit-0 to bit-15, respectively.
In the MIOS14, some signals are multiplexed between submodules using the same signal names for the
inputs and outputs which are connected as shown in Table 17-1.
17.3
MIOS14 Configuration
The complete MIOS14 submodule and signal configuration is shown in Table 17-1.
Table 17-1. MIOS14 Configuration Description
Connected to:
CBA
CBB
CBC
CBD
Output
Signal
Name
Alternate
Signal
Name
PWM, I/O MPWM0
MPWM0
MDI1
0x30
6008
PWM, I/O MPWM1
MPWM1
MDO2
2
0x30
6010
PWM, I/O MPWM2
MPWM2
PPM_TX1
0
3
0x30
6018
PWM, I/O MPWM3
MPWM3
PPM_RX1
4
0
4
0x30
6020
PWM, I/O MPWM4
MPWM4
MDO6/
MPIO32B6
PWMSM
5
0
5
0x30
6028
PWM, I/O MPWM5
MPWM5 MPIO32B7
MMCSM
6
0
6
0x30
6030
MIRS
M
No.
MIRSM
Bit
Position
Base
Address
Offset
0
0
0
0x30
6000
PWMSM
1
0
1
PWMSM
2
0
PWMSM
3
PWMSM
SubModule
Type
Bloc
k
No.
PWMSM
MMCSM
7
BSL0=
0
BSL1=
0
BSL0=
BSL0=
1
BSL0=0
1
BSL1= BSL1=1 BSL1=
1
0
CB6
CB7
0
7
0x30
6038
Signal
Function
Input
Signal
Name
Clock In
MDA11
Load In
MDA12
Clock In
MDA30
MPC561/MPC563 Reference Manual, Rev. 1.2
17-6
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Table 17-1. MIOS14 Configuration Description (continued)
Connected to:
SubModule
Type
MMCSM
Bloc
k
No.
CBA
BSL0=
0
BSL1=
0
CBB
CBC
CBD
BSL0=
BSL0=
1
BSL0=0
1
BSL1= BSL1=1 BSL1=
1
0
8
CB8
MIRS
M
No.
0
MIRSM
Bit
Position
8
Base
Address
Offset
0x30
6040
Signal
Function
Input
Signal
Name
Load In
MDA31
Clock In
MPWM
16
Load In
MPWM
17
Output
Signal
Name
Alternate
Signal
Name
MDO3
Reserve
d
9-10
MDASM
11
CB6
CB22
CB7
CB8
0
11
0x30
6058
Channel
I/O
MDA11
MDA11
MDASM
12
CB6
CB22
CB7
CB8
0
12
0x30
6060
Channel
I/O
MDA12
MDA12
MDASM
13
CB6
CB22
CB23
CB24
0
13
0x30
6068
Channel
I/O
MDA13
MDA13
MDASM
14
CB6
CB22
CB23
CB24
0
14
0x30
6070
Channel
I/O
MDA14
MDA14
MDASM
15
CB6
CB22
CB23
CB24
0
15
0x30
6078
Channel
I/O
MDA15
MDA15
PWMSM
16
1
0
0x30
6080
PWM, I/O
MPWM
16
MPWM
16
PWMSM
17
1
1
0x30
6088
PWM, I/O
MPWM
17
MPWM
17
MDO3
PWMSM
18
1
2
0x30
6090
PWM, I/O
MPWM
18
MPWM
18
MDO6
PWMSM
19
1
3
0x30
6098
PWM, I/O
MPWM
19
MPWM
19
MDO7
PWMSM
20
1
4
0x30
60A0
PWM, I/O
MPWM
20
MPWM
20
MPIO32B8
PWMSM
21
1
5
0x30
60A8
PWM, I/O
MPWM
21
MPWM
21
MPIO32B9
MMCSM
22
1
6
0x30
60B0
Clock In
MDA13
Load In
MDA14
Clock In
MDA27
Load In
MDA28
Clock In
MPWM
18
MMCSM
MMCSM
23
24
CB22
CB23
1
CB24
1
7
8
0x30
60B8
0x30
60C0
MDO6
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-7
Modular Input/Output Subsystem (MIOS14)
Table 17-1. MIOS14 Configuration Description (continued)
Connected to:
SubModule
Type
Bloc
k
No.
CBA
BSL0=
0
BSL1=
0
CBB
CBC
CBD
BSL0=
BSL0=
1
BSL0=0
1
BSL1= BSL1=1 BSL1=
1
0
MIRS
M
No.
MIRSM
Bit
Position
Base
Address
Offset
Signal
Function
Input
Signal
Name
Load In
MPWM
19
Output
Signal
Name
Alternate
Signal
Name
MDO7
Reserve
d
25-2
6
MDASM
27
CB6
CB22
CB23
CB24
1
11
0x30
60D8
Channel
I/O
MDA27
MDA27
MDASM
28
CB6
CB22
CB23
CB24
1
12
0x30
60E0
Channel
I/O
MDA28
MDA28
MDASM
29
CB6
CB22
CB7
CB8
1
13
0x30
60E8
Channel
I/O
MDA29
MDA29
MDASM
30
CB6
CB22
CB7
CB8
1
14
0x30
60F0
Channel
I/O
MDA30
MDA30
MDASM
31
CB6
CB22
CB7
CB8
1
15
0x30
60F8
Channel
I/O
MDA31
MDA31
MPIOS
M
32
0x30
6100
GPIO
MPIO32
B0
MPIO32
B0
VF0
/MDO1
GPIO
MPIO32
B1
MPIO32
B1
VF1
/MCKO
GPIO
MPIO32
B2
MPIO32
B2
VF2
/MSEI
GPIO
MPIO32
B3
MPIO32
B3
VFLS0
/MSEO
GPIO
MPIO32
B4
MPIO32
B4
VFLS1
GPIO
MPIO32
B5
MPIO32
B5
MDO5
GPIO
MPIO32
B6
MPIO32
B6
MPWM4/
MDO6
GPIO
MPIO32
B7
MPIO32
B7
MPWM5
GPIO
MPIO32
B8
MPIO32
B8
MPWM20
GPIO
MPIO32
B9
MPIO32
B9
MPWM21
GPIO
MPIO32
B10
MPIO32
B10
PPM_
TSYNC
GPIO
MPIO32
B11
MPIO32
B11
C_CNRX0
MPC561/MPC563 Reference Manual, Rev. 1.2
17-8
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Table 17-1. MIOS14 Configuration Description (continued)
Connected to:
SubModule
Type
Bloc
k
No.
CBA
BSL0=
0
BSL1=
0
CBB
CBC
CBD
BSL0=
BSL0=
1
BSL0=0
1
BSL1= BSL1=1 BSL1=
1
0
MIRS
M
No.
MIRSM
Bit
Position
Base
Address
Offset
Reserve
d
33255
MBISM
256
Reserve
d
257
MCPSM
258
Reserve
d
259383
MIRSM0
384391
0x30
6C00
MIRSM1
392399
0x30
6C40
Reserve
d
400511
17.3.1
Input
Signal
Name
Output
Signal
Name
Alternate
Signal
Name
GPIO
MPIO32
B12
MPIO32
B12
C_CNTX0
GPIO
MPIO32
B13
MPIO32
B13
PPM_TCL
K
GPIO
MPIO32
B14
MPIO32
B14
PPM_RX0
GPIO
MPIO32
B15
MPIO32
B15
PPM_TX0
Signal
Function
0x30
6800
0x30
6810
MIOS14 Signals
The MIOS14 requires 34 signals: 10 MDASM signals, 8 dedicated MPWMSM signals, 12 dedicated
MPIOSM signals and 4 signals are shared between the MPWMSM and MPIOSM. The required signal
function on shared signals is chosen using the PDMCR2 register in the USIU. The usage of all MIOS14
signals is shown in the block diagram of Figure 17-1 and in the configuration description of Table 17-1.
17.3.2
MIOS14 Bus System
The internal bus system within the MIOS14 is called the modular I/O bus (MIOB). The MIOB makes
communications possible between any submodule and the IMB3 bus master through the MBISM.
The MIOB is divided into three dedicated buses:
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-9
Modular Input/Output Subsystem (MIOS14)
•
•
•
The read/write and control bus
The request bus
The counter bus set
17.3.3
Read/Write and Control Bus
The read/write and control bus (RWCB) allows read and write data transfers to and from any I/O
submodule through the MBISM. It includes signals for data and addresses as well as control signals. The
control signals allow 16-bit simple synchronous single master accesses and supports fast or slow master
accesses.
17.3.4
Request Bus
The request bus (RQB) provides interrupt request signals along with I/O submodule identification and
priority information to the MBISM.
NOTE
Some submodules do not generate interrupts and are therefore independent
of the RQB.
17.3.5
Counter Bus Set
The 16-bit counter bus set (CBS) is a set of six 16-bit counter buses. The CBS makes it possible to transfer
information between submodules. Typically, counter submodules drive the CBS, while action submodules
process the data on these buses. Note, however, that some submodules are self-contained and therefore
independent of the counter bus set.
17.4
MIOS14 Programming Model
The address space of the MIOS14 consist of 4 Kbytes starting at the base address of the module
(0x306000). The overall address map organization is shown in Figure 17-2.
All MIOS14 unimplemented locations within the addressable range, return a logic 0 when accessed. In
addition, the internal TEA (transfer error acknowledge) signal is asserted.
All unused bits within MIOS14 registers return a 0 when accessed.
17.4.1
Bus Error Support
A bus error signal is generated when access to an unimplemented or reserved 16-bit register is attempted,
or when a priviledge violation occurs. A bus error is generated under any of the following conditions:
• Attempted access to unimplemented 16-bit registers within the decoded register block boundary.
• Attempted user access to supervisor registers
• Attempted access to test registers when not in test mode
• Attempted write to read-only registers
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17-10
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
17.4.2
Wait States
The MIOS14 does not generate wait states.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-11
Modular Input/Output Subsystem (MIOS14)
MPWMSM0
MPWMSM1
MPWMSM2
MPWMSM3
MPWMSM4
MPWMSM5
MMCSM6
MMCSM7
MMCSM8
MDASM11
MDASM12
MDASM13
MDASM14
MDASM15
MPWMSM16
MPWMSM17
MPWMSM18
MPWMSM19
MPWMSM20
MPWMSM21
MMCSM22
MMCSM23
MMCSM24
MDASM27
MDASM28
MDASM29
MDASM30
MDASM31
MPIOSM32
Base Address
0x30 6000
Channels
Supervisor/
Unrestricted
Reserved
0x30 6800
0x30 6810
MBISM
MCPSM
Supervisor
Reserved
0x30 6C40
Supervisor
MIRSM0
MIRSM1
Reserved
Submodules
31 to 16
0x30 6FFF
Submodules 15 to 0
MIOS14SR0
0x30 6C00
Reserved
MIOS1ER0
MIOS14RPR0
0x30 6000
0x30 6008
0x30 6010
0x30 6018
0x30 6020
0x30 6028
0x30 6030
0x30 6038
0x30 6040
0x30 6058
0x30 6060
0x30 6068
0x30 6070
0x30 6078
0x30 6080
0x30 6088
0x30 6090
0x30 6098
0x30 60A0
0x30 60A8
0x30 60B0
0x30 60B8
0x30 60C0
0x30 60D8
0x30 60E0
0x30 60E8
0x30 60F0
0x30 60F8
0x30 6100
0x30 6C00
0x30 6C02
0x30 6C04
0x30 6C06
Reserved
MIOS1LVL0
0x30 6C30
Reserved
MIOS14SR1
0x30 6C40
0x30 6C42
Reserved
MIOS14ER1
0x30 6C44
MIOS14RPR1
0x30 6C46
Reserved
MIOS14LVL1
0x30 6C70
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
17-12
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Figure 17-2. MIOS14 Memory Map
17.5
MIOS14 I/O Ports
Each signal of each submodule can be used as an input, output, or I/O port:
Table 17-2. MIOS14 I/O Ports
17.6
Submodule
Number of Pins
per Module
Type
MPIOSM
16
I/O
MMCSM
2
I
MDASM
1
I/O
MPWMSM
1
I/O
MIOS14 Bus Interface Submodule (MBISM)
The MIOS14 bus interface submodule (MBISM) is used as an interface between the MIOB (modular I/O
bus) and the IMB3. It allows the CPU to communicate with the MIOS14 submodules.
17.6.1
MIOS14 Bus Interface (MBISM) Registers
Table 17-3 is the address map for the MBISM submodule.
MSB
0
LSB
1
2
3
4
5
6
7
8
9
10
11
12
0x30 6800
MIOS14 Test and Signal Control Register (MIOS14TPCR)
0x30 6802
MIOS14 Vector Register (MIOS14VECT) -Reserved
0x30 6804
MIOS14 Module-Version Number Register (MIOS14VNR)
0x30 6806
MIOS14 Module Control Register (MIOS14MCR)
0x30 6808
Reserved
0x30 680A
Reserved
0x30 680C
Reserved
0x30 680E
Reserved
13
14
15
Figure 17-3. MBISM Registers
17.6.1.1
MIOS14 Test and Signal Control Register (MIOS14TPCR)
This register is used for MIOS14 factory testing and to control the VF and VFLS Signal usage. Control of
other multiplexed functions is in the PDMCR2 register.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-13
Modular Input/Output Subsystem (MIOS14)
MSB
LSB
0
1
2
3
4
5
6
7
Field TEST
8
9
10
11
12
13
—
SRESET
14
15
VF
VFLS
0000_0000_0000_0000
Addr
0x30 6800
Figure 17-4. Test and Signal Control Register (MIOS14TPCR)
Table 17-3. MIOS14TPCR Bit Descriptions
Bits
Name
0
TEST
1:13
—
Reserved
14
VF
VF Pin Multiplex — This bit controls the function of the VF pins (VF0/MPIO32B0, VF1/MPIO32B1,
VF2/MPIO32B2)
0 = MIOS14 General-Purpose I/O is selected (MPIO32B0, MPIO32B1, MPIO32B2)
1 = VF function is selected (VF[0:2])
15
VFLS
17.6.1.2
Description
Test — This bit is used for MIOS14 factory testing and should always be programmed to a 0.
VFLS Pin Multiplex — This bit controls the function of the VFLS signals (VFLS0/MPIO32B3,
VFLS1/MPIO32B4)
0 = MIOS14 General-Purpose I/O is selected (MPIO32B3, MPIO32B4)
1 = VFLS function is selected (VFLS[0:1])
MIOS14 Vector Register (MIOS14VECT)
This register is reserved and is shown for information purposes only.
MSB
LSB
0
1
2
3
Field
4
5
6
7
8
9
—
10
11
12
13
VECT
SRESET
14
15
—
0000_0000_0000_0000
Addr
0x30 6802
Figure 17-5. Vector Register (MIOS14VECT)
17.6.1.3
MIOS14 Module and Version Number Register (MIOS14VNR)
This read-only register contains the hard-coded values of the module and version number.
MSB
0
Field
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VN1
MN
Reset
Unaffected
Addr
0x30 6804
Figure 17-6. MIOS14 Module/Version Number Register (MIOS14VNR)
1
This field contains the revision level of the MIOS module and may change with different revisions of the device.
MPC561/MPC563 Reference Manual, Rev. 1.2
17-14
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Table 17-4. MIOS14VNR Bit Descriptions
Bits
Name
0:7
MN
Module number = 0x0E on the MPC561/MPC563
8:15
VN
Version number. May change with different revisions of the device.
17.6.1.4
Description
MIOS14 Module Configuration Register (MIOS14MCR)
The MIOS14MCR register is a collection of read/write stop, freeze, reset, and supervisor bits, as well as
interrupt arbitration number bits. These bits are detailed in Table 17-5.
MSB
0
LSB
1
Field STOP RSV
2
3
FRZ
RST
SRESET
4
5
6
—
7
8
9
10
11
SUPV
12
13
14
15
—
0000_0000_0000_0000
Addr
0x30 6806
Figure 17-7. Module Configuration Register (MIOS14MCR)
Table 17-5. MIOS14MCR Bit Descriptions
Bits
Name
Description
0
STOP
Stop enable — The STOP bit, while asserted, activates the MIOB freeze signal regardless of the
state of the IMB3 FREEZE signal. The MIOB freeze signal is further validated in some
submodules with internal freeze enable bits in order for the submodule to be stopped. The
MBISM continues to operate to allow the CPU access to the submodule’s registers. The MIOB
freeze signal remains active until reset or until the STOP bit is written to zero by the CPU (via the
IMB3). The STOP bit is cleared by reset.
0 Allows MIOS14 operation.
1 Selectively stops MIOS14 operation.
1
—
2
FRZ
Freeze enable — The FRZ bit, while asserted, activates the MIOB freeze signal only when the
IMB3 FREEZE signal is active. The MIOB freeze signal is further validated in some submodules
with internal freeze enable bits in order for the submodule to be frozen. The MBISM continues to
operate to allow the CPU access to the submodule’s registers. The MIOB freeze signal remains
active until the FRZ bit is written to zero or the IMB3 FREEZE signal is negated. The FRZ bit is
cleared by reset.
0 Ignores the FREEZE signal on the IMB3, allows MIOS14 operation.
1 Selectively stops MIOS14 operation when the FREEZE signal appears on the IMB3.
3
RST
Module reset — The RST bit is always read as 0 and can be written to 1. When the RST bit is
written to 1 operation of the MIOS14 completely stops and resets all the values in the submodule.
This completely stops the operation of the MIOS14 and reset all the values in the submodules
registers that are affected by reset. This bit provides a way of resetting the complete MIOS14
module regardless of the reset state of the CPU. The RST bit is cleared by reset.
0 Writing a 0 to RST has no effect.
1 Reset the MIOS14 submodules.
4:7
—
Reserved
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-15
Modular Input/Output Subsystem (MIOS14)
Table 17-5. MIOS14MCR Bit Descriptions (continued)
Bits
Name
Description
8
SUPV
Supervisor data space selector — The SUPV bit tells if the address space from 0x30 6000 to
0x30 67FF in the MIOS14 is accessed at the supervisor privilege level (See Figure 17-2). When
cleared, these addresses are accessed at the unrestricted privilege level.
The SUPV bit is cleared by reset.
0 Unrestricted Data Space.
1 Supervisor Data Space.
9:15
—
17.7
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in MIOS14
implementations that use hardware interrupt arbitration. These bits are not used on
MPC561/MPC563.
MIOS14 Counter Prescaler Submodule (MCPSM)
The MIOS14 counter prescaler submodule (MCPSM) divides the MIOS14 clock (fSYS) to generate the
counter clock. It is designed to provide all the submodules with the same division of the main MIOS14
clock (division of fSYS). It uses a 4-bit modulus counter. The clock signal is prescaled by loading the value
of the clock prescaler register into the prescaler counter every time it overflows. This allows all prescaling
factors between 2 and 16. Counting is enabled by asserting MCPSMSCR[PREN]. The counter can be
stopped at any time by negating this bit, thereby stopping all submodules using the output of the MCPSM
(counter clock). A block diagram of the MCPSM is given in Figure 17-8.
The following sections describe the MCPSM in detail.
fSYS
Dec.
CP0
Clock
Prescaler
Register
CP1
4-bit
Decrementer
CP2
Overflow
= 1?
Counter Clock
CP3
Enable
MCPSMSCR
Load
PREN
Figure 17-8. MCPSM Block Diagram
17.7.1
•
MCPSM Features
Centralized counter clock generator
MPC561/MPC563 Reference Manual, Rev. 1.2
17-16
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
•
•
•
Programmable 4-bit modulus down-counter
Wide range of possible division ratios: 2 through 16
Count inhibit under software control
17.7.1.1
MCPSM Signal Functions
The MCPSM has no associated external signals.
17.7.1.2
•
•
•
Modular I/O Bus (MIOB) Interface
The MCPSM is connected to all the signals in the read/write and control bus, to allow data transfer
from and to the MCPSM registers, and to control the MCPSM in the different possible situations.
The MIOS14 counter prescaler submodule does not use any 16-bit counter bus.
The MIOS14 counter prescaler submodule does not use the request bus.
17.7.2
Effect of RESET on MCPSM
When the RESET signal is asserted, all the bits in the MCPSM status and control register are cleared.
NOTE
The MCPSM is still disabled after the RESET signal is negated and
counting must be explicitly enabled by asserting MCPSMSCR[PREN].
17.7.3
MCPSM Registers
The privilege level to access to the MCPSM registers is supervisor only.
17.7.3.1
MCPSM Registers Organization
Table 17-6. MCPSM Register Address Map
Address
Register
0x30 6810
Reserved
0x30 6812
Reserved
0x30 6814
Reserved
0x30 6816
MCPSM Status/Control Register (MCPSMSCR)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-17
Modular Input/Output Subsystem (MIOS14)
17.7.3.2
MCPSM Status/Control Register (MCPSMSCR)
MSB
0
LSB
1
2
3
4
5
6
Field PREN FREN
7
8
9
10
11
12
—
SRESET
13
14
15
PSL3:0
0000_0000_0000_0000
Addr
0x30 6816
Figure 17-9. MCPSM Status/Control Register (MCPSMSCR)
Table 17-7. MCPSMSCR Bit Descriptions
Bits
Name
Description
0
PREN
Prescaler enable bit — This active high read/write control bit enables the MCPSM counter. The
PREN bit is cleared by reset.
0 MCPSM counter disabled.
1 MCPSM counter enabled.
1
FREN
Freeze bit — This active high read/write control bit when set make possible a freeze of the
MCPSM counter if the MIOB freeze line is activated. NOTE: This line is active when
MIOS14MCR[STOP] is set or when MIOS14MCR[FREN] and the IMB3 FREEZE line are set.
When the MCPSM is frozen, it stops counting. Then when the FREN bit is reset or when the
freeze condition on the MIOB is negated, the counter restarts from where it was before freeze.
The FREN bit is cleared by reset.
0 MCPSM counter not frozen.
1 MCPSM counter frozen if MIOB freeze active.
2:11
—
12:15
PSL[3:0]
Reserved
Clock prescaler — This 4-bit read/write data register stores the modulus value for loading into
the clock prescaler. The new value is loaded into the counter on the next time the counter equals
one or when disabled (PREN =0).
Table 17-8. Clock Prescaler Setting
PSL[3:0] Value
Divide Ratio
Hex
Binary
0x0
0b0000
16
0x1
0b0001
No counter clock output
0x2
0b0010
2
0x3
0b0011
3
...
...
...
0xE
0b1110
14
0xF
0b1111
15
NOTE
If the binary value 0b0001 is entered in PSL[3:0], the output signal is stuck
at zero, no clock is output.
MPC561/MPC563 Reference Manual, Rev. 1.2
17-18
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
17.8
MIOS14 Modulus Counter Submodule (MMCSM)
The MMCSM is a versatile counter submodule capable of performing complex counting and timing
functions, including modulus counting, in a wide range of applications. The MMCSM may also be
configured as an event counter, allowing the overflow flag to be set after a predefined number of events
(internal clocks or external events), or as a time source for other submodules.
NOTE
The MMCSM can also operate as a free running counter by loading the
modulus value of zero.
The main components of the MMCSM are an 8-bit prescaler counter, an 8-bit prescaler register, a 16-bit
up-counter register, a 16-bit modulus latch register, counter loading and interrupt flag generation logic.
The contents of the modulus latch register is transferred to the counter under the following three
conditions:
1. When an overflow occurs
2. When an appropriate transition occurs on the external load signal
3. When the program writes to the counter register. In this case, the value is first written into the
modulus register and immediately transferred to the counter.
Software can also write a value to the modulus register for later loading into the counter with one of the
two first criteria.
A software control register selects whether the clock input to the counter is one of the prescaler outputs or
the corresponding input signal. The polarity of the external input signal is also programmable.
The following sections describe the MMCSM in detail. A block diagram of the MMCSM is shown in
Figure 17-10.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-19
Modular Input/Output Subsystem (MIOS14)
16-bit Counter Bus
8-bit Clock
Prescaler
Counter Clock
Clock input
signal (MMCnC)
Edge
Clock Clock Clock
Detect Select Enable
Request Bus
Flag
PINC
CP7 - CP0
8-bit Prescale
Mod.Register
Modulus Load
signal (MMCnL)
FREN
MMCSMCNT
16-bit Up-Counter Reg.
Load
Edge
Detect
PINL
CLS0 CLS1
EDGN
EDGP
Overflow
Load
Control
MMCSMML
16-bit Modulus
Latch Reg.
MIOB
Figure 17-10. MMCSM Block Diagram
0xFFFF
Modulus Value
Two’s Complement
Counter Reload
Figure 17-11. MMCSM Modulus Up-Counter
17.8.1
•
•
•
MMCSM Features
Programmable 16-bit modulus up-counter with a built-in programmable 8-bit prescaler clocked by
MCPSM
Maximum increment frequency of the counter:
— clocked by the internal MCPSM output: fSYS / 2
— clocked by the external signal: fSYS / 4
Flag setting and possible interrupt generation on overflow of the up-counter register
MPC561/MPC563 Reference Manual, Rev. 1.2
17-20
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
•
•
•
•
•
•
Time counter on internal clock with interrupt capability after a pre-determined time
External event counter (pulse accumulator) with overflow and interrupt capability after a
pre-determined number of external events
Usable as a regular free-running up-counter
Capable of driving a dedicated 16-bit counter bus to provide timing information to action
submodules (the value driven is the contents of the 16-bit up-counter register)
Optional signal for counting external events
Optional signal to externally force a load of the modulus counter
17.8.1.1
MMCSM Signal Functions
The MMCSM has two dedicated external signals.
An external modulus load signal (MMCnL) allows the modulus value stored in the modulus latch register
(MMCSMML) to be loaded into the up-counter register (MMCSMCNT) at any time. Both rising and
falling edges of the load signal may be used, according to the EDGEP and EDGEN bit settings in the
MMCSMSCR.
An external event clock signal (MMCnC) can be selected as the clock source for the up-counter register
(MMCSMCNT) by setting the appropriate value in the CLS bit field of the status/control register
(MMCSMSCR). Either rising or falling edge may be used according to the setting of these bits.
When the external clock source is selected, the MMCSM is in the event counter mode. The counter can
simply counts the number of events occurring on the input signal. Alternatively, the MMCSM can be
programmed to generate an interrupt when a predefined number of events have been counted; this is done
by presetting the counter with the two’s complement value of the desired number of events.
17.8.2
MMCSM Prescaler
The built-in prescaler consists of an 8-bit modulus counter, clocked by the MCPSM output. It is loaded
with an 8-bit value every time the counter overflows or whenever the prescaler output is selected as the
clock source. This 8-bit value is stored in the MMCSMSCR[CP]. The prescaler overflow signal is used to
clock the MMCSM up-counter. This allows the MMCSMCNT to be incremented at the MCPSM output
frequency divided by a value between 1 and 256.
17.8.3
•
•
•
Modular I/O Bus (MIOB) Interface
The MMCSM is connected to all the signals in the read/write and control bus, to allow data transfer
from and to the MMCSM registers, and to control the MMCSM in the different possible situations.
The MMCSM drives a dedicated 16-bit counter bus with the value currently in the up-counter
register
The MMCSM uses the request bus to transmit the FLAG line to the interrupt request submodule
(MIRSM). A flag is set when an overflow has occurred in the up-counter register.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-21
Modular Input/Output Subsystem (MIOS14)
17.8.4
Effect of RESET on MMCSM
When the RESET signal is asserted, only the FREN, EDGP, EDGN, and CLS bits in the MMCSMSCR are
cleared. The clock prescaler CP, PINC, and PINL bits in the same register are not cleared.
• The PINC and PINL bits in the MMCSMSCR always reflect the state of the appropriate external
pins.
• The MMCSM is disabled after reset and must be explicitly enabled by selecting a clock source
using the CLS bits.
The MMCSMCNT and the MMCSMML, together with the clock prescaler register bits, must be initialized
by software, because they are undefined after a hardware reset. A modulus value must be written to the
MMCSMCNT (which also writes into the MMCSMML) before the MMCSMSCR is written to. The latter
access initializes the clock prescaler.
17.8.5
MMCSM Registers
The privilege level to access to the MMCSM registers depends on the MIOS14MCR SUPV bit. The
privilege level is unrestricted after SRESET and can be changed to supervisor by software.
17.8.5.1
MMCSM Register Organization
Table 17-9. MMCSM Address Map
Address
Register
MMCSM6
0x30 6030
MMCSM6 Up-Counter Register (MMCSMCNT)
See Table 17-10 for bit descriptions.
0x30 6032
MMCSM6 Modulus Latch Register (MMCSMML)
See Table 17-11 for bit descriptions.
0x30 6034
MMCSM6 Status/Control Register Duplicated (MMCSMSCRD)
See Section 17.8.5.5, “MMCSM Status/Control Register (MMCSMSCR)” for bit descriptions.
0x30 6036
MMCSM6 Status/Control Register (MMCSMSCR).
See Table 17-12 for bit descriptions.
MMCSM7
0x30 6038
MMCSM7 Up-Counter Register (MMCSMCNT)
0x30 603A
MMCSM7 Modulus Latch Register (MMCSMML)
0x30 603C
MMCSM7 Status/Control Register Duplicated (MMCSMSCRD)
0x30 603E
MMCSM7 Status/Control Register (MMCSMSCR)
MMCSM8
0x30 6040
MMCSM8 Up-Counter Register (MMCSMCNT)
0x30 6042
MMCSM8 Modulus Latch Register (MMCSMML)
0x30 6044
MMCSM8 Status/Control Register Duplicated (MMCSMSCRD)
0x30 6046
MMCSM8 Status/Control Register (MMCSMSCR)
MPC561/MPC563 Reference Manual, Rev. 1.2
17-22
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Table 17-9. MMCSM Address Map (continued)
Address
Register
MMCSM22
0x30 60B0
MMCSM22 Up-Counter Register (MMCSMCNT)
0x30 60B2
MMCSM22 Modulus Latch Register (MMCSMML)
0x30 60B4
MMCSM22 Status/Control Register Duplicated (MMCSMSCRD)
0x30 60B6
MMCSM22 Status/Control Register (MMCSMSCR)
MMCSM23
0x30 60B8
MMCSM23 Up-Counter Register (MMCSMCNT)
0x30 60BA
MMCSM23 Modulus Latch Register (MMCSMML)
0x30 60BC
MMCSM23 Status/Control Register Duplicated (MMCSMSCRD)
0x30 60BE
MMCSM23 Status/Control Register (MMCSMSCR)
MMCSM24
0x30 60C0
MMCSM24 Up-Counter Register (MMCSMCNT)
0x30 60C2
MMCSM24 Modulus Latch Register (MMCSMML)
0x30 60C4
MMCSM24 Status/Control Register Duplicated (MMCSMSCRD)
0x30 60C6
MMCSM24 Status/Control Register (MMCSMSCR)
17.8.5.2
MMCSM Up-Counter Register (MMCSMCNT)
MSB
0
LSB
1
Field
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CNT
SRESET
Undefined
Addr
0x30 6030, 0x30 6038, 0x30 6040, 0x30 60B0, 0x30 60B8, 0x30 60C0
Figure 17-12. MMCSM Up-Counter Register (MMCSMCNT)
Table 17-10. MMCSMCNT Bit Descriptions
Bits
Name
0:15
CNT
Description
Counter value — These bits are read/write data bits representing the 16-bit value of the
up-counter. It contains the value that is driven onto the 16-bit counter bus.
Note: Writing to MMCSMCNT simultaneously writes to MMCSMML.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-23
Modular Input/Output Subsystem (MIOS14)
17.8.5.3
MMCSM Modulus Latch Register (MMCSMML)
MSB
LSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
15
ML
SRESET
Undefined
Addr
0x30 6032, 0x30 603A, 0x30 6042, 0x30 60B2, 0x30 60BA, 0x30 60C2
Figure 17-13. MMCSM Modulus Latch Register (MMCSMML)
Table 17-11. MMCSMML Bit Descriptions
Bits
Name
Description
0:15
ML
Modulus latches — These bits are read/write data bits containing the 16-bit modulus value to be
loaded into the up-counter.
The value loaded in this register must be the one’s complement of the desired modulus count.
The up-counter increments from this one’s complement value up to 0xFFFF to get the correct
number of steps before an overflow is generated to reload the modulus value into the up-counter.
17.8.5.4
MMCSM Status/Control Register (MMCSMSCRD)
(Duplicated)
The MMCSMSCRD and the MMCSMSCR are the same registers accessed at two different addresses.
Reading or writing to one of these two addresses has exactly the same effect.
The duplication of the SCR register allows coherent 32-bit accesses when using a RCPU.
WARNING
The user should not write directly to the address of the MMCSMSCRD.
This register’s address may be reserved for future use and should not be
accessed by the software to ensure future software compatibility.
17.8.5.5
MMCSM Status/Control Register (MMCSMSCR)
The status/control register (SCR) is a collection of read-only signal status bits, read/write control bits and
an 8-bit read/write data register, as detailed below.
MSB
0
Field PINC
SRESET
Addr
LSB
1
2
3
4
PINL FREN EDGN EDGP
5
6
CLS
7
8
9
—
10
11
12
13
14
15
CP
Undefined
0x30 6036, 0x30 603E, 0x30 6046, 0x30 60B6, 0x30 60BE, 0x30 60C6
Figure 17-14. MMCSM Status/Control Register (MMCSMSCR)
MPC561/MPC563 Reference Manual, Rev. 1.2
17-24
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Table 17-12. MMCSMSCR Bit Descriptions
Bits
Name
Description
0
PINC
Clock input signal status bit — This read-only status bit reflects the logic state of the clock input
signal MMCnC (MDA11, MDA13, MDA27, MDA30, PWM16, and PWM18).
1
PINL
Modulus load input signal status bit — This read-only status bit reflects the logic state of the
modulus load signal MMCnL (MDA12, MDA14, MDA28, MDA31, PWM17, and PWM19).
2
FREN
Freeze enable — This active high read/write control bit enables the MMCSM to recognize the
MIOB freeze signal.
3
EDGN
Modulus load falling-edge sensitivity — This active high read/write control bit sets falling-edge
sensitivity for the MMCnL signal, such that a high-to-low transition causes a load of the
MMCSMCNT.
4
EDGP
Modulus load rising-edge sensitivity
This active high read/write control bit sets rising-edge sensitivity for the MMCnL signal, such that
a low-to-high transition causes a load of the MMCSMCNT.
See Table 17-13 for details about edge sensitivity.
5:6
CLS
Clock select — These read/write control bits select the clock source for the modulus counter.
Either the rising edge or falling edge of the clock signal on the MMCnC signal may be selected,
as well as, the internal MMCSM prescaler output or disable mode (no clock source). See
Table 17-14 for details about the clock selection.
7
—
Reserved
8:15
CP
Clock prescaler — This 8-bit data field is also accessible as an 8-bit data register. It stores the
two’s complement of the modulus value to be loaded into the built-in 8-bit clock prescaler. The
new value is loaded into the prescaler counter on the next counter overflow, or upon setting the
CLS1 — CLS0 bits for selecting the clock prescaler as the clock source.
Table 17-15 gives the clock divide ratio according to the value of CP.
Table 17-13. MMCSMCNT Edge Sensitivity
EDGN
EDGP
Edge Sensitivity
1
1
MMCSMCNT load on rising and falling edges
1
0
MMCSMCNT load on falling edges
0
1
MMCSMCNT load on rising edges
0
0
None (disabled)
Table 17-14. MMCSMCNT Clock Signal
CLS
Clocking Selected
11
MMCSM clock prescaler
10
Clock signal rising-edge
01
Clock signal falling-edge
00
None (disable)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-25
Modular Input/Output Subsystem (MIOS14)
Table 17-15. Prescaler Values
17.9
Prescaler Value
(CP in Hex)
MIOS14 Prescaler
Clock Divided By
FF
1
FE
2
FD
3
FC
4
FB
5
FA
6
F9
7
F8
8
......
........
02
254 (2^8 -2)
01
255 (2^8 -1)
00
256 (2^8)
MIOS14 Double Action Submodule (MDASM)
The MIOS14 double action submodule (MDASM) is a function included in the MIOS14 library. It is a
versatile 16-bit dual action submodule capable of performing two event operations before software
intervention is required. It can perform two event operations such as PWM generation and measurement,
input capture, output compare, etc.
The MDASM is composed of two timing channels (A and B), an output flip-flop, an input edge detector
and some control logic. All control and status bits are contained in the MDASM status and control register.
The following sections describe the MDASM in detail. A block diagram of the MDASM is shown in
Figure 17-15.
MPC561/MPC563 Reference Manual, Rev. 1.2
17-26
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
4 X 16-bit
Counter buses
Counter Bus Set
Counter bus
select
BSL1 BSL0
16-bit comparator A
FORCA FORCB
WOR
Output
flip-flop
Output
buffer
16-bit Register A
PIN
I/O signal
EDPOL
Edge
detect
16-bit Register B1
Register B
FLAG
16-bit Register B2
16-bit comparator B
MODE3
MODE2
MODE1
MODE0
Request Bus
Control register bits
MIO Bus
Figure 17-15. MDASM Block Diagram
17.9.1
•
•
•
•
•
•
•
MDASM Features
Versatile 16-bit dual action unit allowing up to two events to occur before software intervention is
required
Six software selectable modes allowing the MDASM to perform pulse width and period
measurements, PWM generation, single input capture and output compare operations as well as
port functions
Software selection of one of the four possible 16-bit counter buses used for timing operations
Flag setting and possible interrupt generation after MDASM action completion
Software selection of output pulse polarity
Software selection of totem-pole or open-drain output
Software readable output signal status
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-27
Modular Input/Output Subsystem (MIOS14)
17.9.1.1
MDASM Signal Functions
The MDASM has one dedicated external signal. This signal is used in input or in output depending on the
selected mode. When in input, it allows the MDASM to perform input capture, input pulse width
measurement and input period measurement. When in output, it allows output compare, single shot output
pulse, single output compare and output port bit operations as well as output pulse width modulation.
NOTE
In disable mode, the signal becomes a high impedance input and the input
level on this signal is reflected by the state of the PIN bit in the
MDASMSCR register.
17.9.2
MDASM Description
The MDASM contains two timing channels A and B associated with the same input/output signal. The
dual action submodule is so called because its timing channel configuration allows two events (input
capture or output compare) to occur before software intervention is required.
Six operating modes allow the software to use the MDASM’s input capture and output compare functions
to perform pulse width measurement, period measurement, single pulse generation and continuous pulse
width generation, as well as standard input capture and output compare. The MDASM can also work as a
single I/O signal. See Table 17-16 for details.
Channel A comprises one 16-bit data register and one 16-bit comparator. Channel B also consists of one
16-bit data register and one 16-bit comparator, however, internally, channel B has two data registers B1
and B2, and the operating mode determines which register is accessed by the software:
• In the input modes (IPWM, IPM and IC), registers A and B2 are used to hold the captured values;
in these modes, the B1 register is used as a temporary latch for channel B.
• In the output compare modes (OCB and OCAB), registers A and B2 are used to define the output
pulse; register B1 is not used in these modes.
• In the output pulse width modulation mode (OPWM), registers A and B1 are used as primary
registers and hidden register B2 is used as a double buffer for channel B.
Register contents are always transferred automatically at the correct time so that the minimum pulse
(measurement or generation) is just one 16-bit counter bus count. The A and B data registers are always
read/write registers, accessible via the MIOB.
In the input modes, the edge detect circuitry triggers a capture whenever a rising or falling edge (as defined
by the EDPOL bit) is applied to the input signal. The signal on the input signal is Schmitt triggered and
synchronized with the MIOS14 CLOCK.
In the disable mode (DIS) and in the input modes, the PIN bit reflects the state present on the input signal
(after being Schmitt triggered and synchronized). In the output modes the PIN bit reflects the value present
on the output flip-flop. The output flip-flop is used in output modes to hold the logic level applied to the
output signal.
MPC561/MPC563 Reference Manual, Rev. 1.2
17-28
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
The 16-bit counter bus selector is common to all input and output functions; it connects the MDASM to
one of the four 16-bit counter buses available to that submodule instance and is controlled in software by
the 16-bit counter bus selector bits BSL0 and BSL1 in the MDASMSCR register.
17.9.3
MDASM Modes of Operation
The mode of operation of the MDASM is determined by the mode select bits MODE[0:3] in the
MDASMSCR register (see Table 17-16).
Table 17-16. MDASM Modes of Operation
MODE[0:3]
Mode
Description of Mode
0000
DIS
0001
IPWM
0010
IPM
0011
IC
0100
OCB
Output compare, flag line activated on B compare — Generate leading and trailing edges of an output
pulse.
0101
OCAB
Output compare, flag line activated on A and B compare — Generate leading and trailing edges of an
output pulse.
1xxx
OPWM
Output pulse width modulation — Generate continuous PWM output with 7, 9, 11, 12, 13, 14, 15 or 16
bits of resolution.
Disabled — Input signal is high impedance; PIN gives state of the input signal.
Input pulse width measurement — Capture on the leading edge and the trailing edge of an input pulse.
Input period measurement — Capture two consecutive rising/falling edges.
Input capture — Capture when the designated edge is detected.
To avoid spurious interrupts, and to make sure that the FLAG line is activated according to the newly
selected mode, the following sequence of operations should be adopted when changing mode:
1. Disable MDASM interrupts (by resetting the enable bit in the relevant MIRSM)
2. Change mode (via disable mode)
3. Reset the corresponding FLAG bit in the relevant MIRSM
4. Re-enable MDASM interrupts (if desired)
NOTE
When changing between output modes, it is not necessary to follow this
procedure, as in these modes the FLAG bit merely indicates to the software
that the compare value can be updated. However changing modes without
passing via the disable mode does not guarantee the subsequent
functionality.
17.9.3.1
Disable (DIS) Mode
The disable mode is selected by setting MODE[0:3] to 0b0000.
In this mode, all input capture and output compare functions of the MDASM are disabled and the FLAG
line is maintained inactive, but the input port signal function remains available. The associated signal
becomes a high impedance input and the input level on this signal is reflected by the state of the PIN bit
in the MDASMSCR register. All control bits remain accessible, allowing the software to prepare for future
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-29
Modular Input/Output Subsystem (MIOS14)
mode selection. Data registers A and B are accessible at consecutive addresses. Writing to data register B
stores the same value in registers B1 and B2.
WARNING
When changing modes, it is imperative to go through the DIS mode. Failure
to do this could lead to invalid and unexpected output compare or input
capture results, and to flags being set incorrectly.
17.9.3.2
Input Pulse Width Measurement (IPWM) Mode
IPWM mode is selected by setting MODE[0:3] to 0b0001.
This mode allows the width of a positive or negative pulse to be determined by capturing the leading edge
of the pulse on channel B and the trailing edge of the pulse on channel A; successive captures are done on
consecutive edges of opposite polarity. The edge sensitivity is selected by the EDPOL bit in the
MDASMSCR register.
This mode also allows the software to determine the logic level on the input signal at any time by reading
the PIN bit in the MDASMSCR register.
The channel A input capture function remains disabled until the first leading edge triggers the first input
capture on channel B (refer to Figure 17-16). When this leading edge is detected, the count value of the
16-bit counter bus selected by the BSL[1:0] bits is latched in the 16-bit data register B1; the FLAG line is
not activated. When the next trailing edge is detected, the count value of the 16-bit counter bus is latched
into the 16-bit data register A and, at the same time, the FLAG line is activated and the contents of register
B1 are transferred to register B2.
Reading data register B returns the value in register B2. If subsequent input capture events occur while the
FLAG bit is set in the corresponding MIRSM, data registers A and B will be updated with the latest
captured values and the FLAG line will remain active.
If a 32-bit coherent operation is in progress when the trailing edge is detected, the transfer from B1 to B2
is deferred until the coherent operation is completed. Operation of the MDASM then continues on
channels B and A as previously described.
The input pulse width is calculated by subtracting the value in data register B from the value in data register
A.
Figure 17-16 provides an example of how the MDASM can be used for input pulse width measurement.
MPC561/MPC563 Reference Manual, Rev. 1.2
17-30
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Mode selection; EDPOL = 1 (Channel A capture on falling edge, Channel B capture on rising edge)
Rising
Edge Trigger
Input
signal
Falling
Edge Trigger
Rising
Edge Trigger
Pulse 1
Falling
Edge Trigger
Pulse 2
FLAG reset
by software
FLAG reset
by software
Flag set
0x1400
0x1525
Flag set
FLAG bit
16-bit
0x0500
Counter
Bus
Register A
0xxxxx
0x1100
0x1000
2
1
0xxxxx
Rising
Edge Trigger
0x1100
0x16A0
2
1
0x1100
0x1525
0x1525
0x1400
0x1400
0x16A0
B1 is an internal register, not accessible to software
Register B1
0xxxxx
0x1000
0x1000
3
3
Register B2
0xxxxx
0xxxxx
0x1000
0x1000
Pulse 1 = Reg A- Reg B
= 0x0100
0x1400
0x1400
Pulse 2 = Reg A- Reg B
= 0x0125
Figure 17-16. Input Pulse Width Measurement Example
17.9.3.3
Input Period Measurement (IPM) Mode
IPM mode is selected by setting MODE[0:3] to 0b0010.
This mode allows the period of an input signal to be determined by capturing two consecutive rising edges
or two consecutive falling edges; successive input captures are done on consecutive edges of the same
polarity. The edge sensitivity is defined by the EDPOL bit in the MDASMSCR register.
This mode also allows the software to determine the logic level on the input signal at any time by reading
the PIN bit in the MDASMSCR register (refer to Figure 17-17). When the first edge having the selected
polarity is detected, the 16-bit counter bus value is latched into the 16-bit data register A. Data in register
B1 is transferred to data register B2 and the data in register A is transferred to register B1.
On this first capture the FLAG line is not activated, and the value in register B2 is meaningless. On the
second and subsequent captures, the FLAG line is activated when the data in register A is transferred to
register B1.
When the second edge of the same polarity is detected, the counter bus value is latched into data register
A, the data in register B1 is transferred to data register B2, the FLAG line is activated to signify that the
beginning and end points of a complete period have been captured, and finally the data in register A is
transferred to register B1. This sequence of events is repeated for each subsequent capture. Reading data
register B returns the value in register B2.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-31
Modular Input/Output Subsystem (MIOS14)
If a 32-bit coherent operation is in progress when an edge (except for the first edge) is detected, the transfer
of data from B1 to B2 is deferred until the coherent operation is completed. At any time, the input level
present on the input signal can be read on the PIN bit.
The input pulse period is calculated by subtracting the value in data register B from the value in data
register A.
Figure 17-17 provides an example of how the MDASM can be used for input period measurement.
Mode selection; EDPOL = 0 (Channel A capture on rising edge)
Rising
Edge Trigger
Rising
Edge Trigger
Rising
Edge Trigger
Input signal
Flag set
FLAG reset
by software
FLAG reset
bysoftwa re
Flag set
FLAG bit
16-bit
Counter Bus
0x0500
0x1000
0x1100
1
0xxxxx
0x1000
0x1000
0xxxxx
0xxxxx
2
Register B2
0xxxxx
0x1525
0x1400
3
0x1400
2 Flag set
0x0400
0x16A0
1
1
Register A
0xxxxx
0x1000
0x1000
Internal Register, not accessible to
3 software
Register B1
0x1400
0x1400
0x16A0
3
0x1400
0x16A0
2 Flag set
0x1000
Period = Reg A -Reg B
0x1400
Period = Reg A -Reg B
Figure 17-17. Input Period Measurement Example
17.9.3.4
Input Capture (IC) Mode
IC mode is selected by setting MODE[0:3] to 0b0011.
This mode is identical to the input period measurement mode (IPM) described above, with the exception
that the FLAG line is also activated at the occurrence of the first detected edge of the selected polarity. In
this mode the MDASM functions as a standard input capture function. In this case the value latched in
channel B can be ignored. Figure 17-18 provides an example of how the MDASM can be used for input
capture.
MPC561/MPC563 Reference Manual, Rev. 1.2
17-32
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Mode selection; EDPOL = 0 (Channel A capture on rising edge)
Rising
Edge Trigger
Rising
Edge Trigger
Rising
Edge Trigger
Input signal
FLAG reset
by software
Flag set
Flag set
FLAG reset
by software
FLAG reset
by software
Flag set
FLAG bit
16-bit
Counter Bus
0x0500
0x1000
0x1100
0x1400
0x1525
0x16A0
Register A
0xxxxx
0x1000
Internal Register, not accessible to software
0x1000
0x1400
0x1400
0x16A0
Register B1
0xxxxx
0x1000
0x1000
0x1400
0x1400
0x16A0
Register B2
(Ignored)
0xxxxx
0xxxxx
0xxxxx
0x1000
0x1000
0x1400
Figure 17-18. MDASM Input Capture Example
17.9.3.5
Output Compare (OCB and OCAB) Modes
Output compare mode (either OCA or OCB) is selected by setting MODE[0:3] to 0b010x. The MODE0
controls the activation criteria for the FLAG line, (i.e., when a compare occurs only on channel B or when
a compare occurs on either channel).
This mode allows the MDASM to perform four different output functions:
• Single-shot output pulse (two edges), with FLAG line activated on the second edge
• Single-shot output pulse (two edges), with FLAG line activated on both edges
• Single-shot output transition (one edge)
• Output port signal, with output compare function disabled
In this mode the leading and trailing edges of variable width output pulses are generated by calculated
output compare events occurring on channels A and B, respectively. OC mode may also be used to perform
a single output compare function, or may be used as an output port bit.
In this mode, channel B is accessed via register B2. A write to register B2 writes the same value to register
B1 even though the contents of B1 are not used in this mode. Both channels work together to generate one
‘single shot’ output pulse signal. Channel A defines the leading edge of the output pulse, while channel B
defines the trailing edge of the pulse. FLAG line activation can be done when a match occurs on channel
B only or when a compare occurs on either channel (as defined by the MODE0 in the MDASMSCR
register).
When this mode is first selected, (i.e., coming from disable mode, both comparators are disabled). Each
comparator is enabled by writing to its data register; it remains enabled until the next successful
comparison is made on that channel, whereupon it is disabled. The values stored in registers A and B are
compared with the count value on the selected 16-bit counter bus when their corresponding comparators
are enabled.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-33
Modular Input/Output Subsystem (MIOS14)
The output flip-flop is set when a match occurs on channel A. The output flip-flop is reset when a match
occurs on channel B. The polarity of the output signal is selected by the EDPOL bit. The output flip-flop
level can be obtained at any time by reading the PIN bit.
If subsequent enabled output compares occur on channels A and B, the output pulses continue to be output,
regardless of the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-flop to the level
corresponding to a comparison on channel A or B, respectively.
NOTE
The FLAG line is not affected by these ‘force’ operations.
Totem pole or open-drain output circuit configurations can be selected using the WOR bit in the
MDASMSCR register.
NOTE
If both channels are loaded with the same value, the output flip-flop
provides a logic zero level output and the flag bit is still set on the match.
NOTE
16-bit counter bus compare only occurs when the 16-bit counter bus is
updated.
17.9.3.5.1
Single Shot Output Pulse Operation
The single shot output pulse operation is selected by writing the leading edge value of the desired pulse to
data register A and the trailing edge value to data register B. A single pulse will be output at the desired
time, thereby disabling the comparators until new values are written to the data registers. To generate a
single shot output pulse, the OCB mode should be used to only generate a flag on the B match.
In this mode, registers A and B2 are accessible to the user software (at consecutive addresses).
Figure 17-19 provides an example of how the MDASM can be used to generate a single output pulse.
MPC561/MPC563 Reference Manual, Rev. 1.2
17-34
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
Mode selection; MODE0 = 0
A Event
B Event
Output signal
Reoccurrences of the timer count do not
trigger the output pulse unless r egisters
A and B have been written again.
FLAG reset
by software
FLAG bit
16-bit
0x0500
Counter Bus
Write to A and B
0x1000
0x1100
0x0000
0x1000
0x1100
Register A
0x1000
0x1000
Internal Register, not accessible to software
0x1000
0x1000
0x1000
0x1000
Register B1
0xxxxx
0xxxxx
0xxxxx
0xxxxx
0xxxxx
0xxxxx
Register B2
0x1100
0x1100
0x1100
0x1100
0x1100
0x1100
Figure 17-19. Single Shot Output Pulse Example
17.9.3.5.2
Single Output Compare Operation
The single output compare operation is selected by writing to only one of the two data registers (A or B),
thus enabling only one of the comparators. Following the first successful match on the enabled channel,
the output level is fixed and remains at the same level indefinitely with no further software intervention
being required. To generate a single output compare, the OCAB mode should be used to generate a flag on
both the A and the B match.
NOTE
In this mode, registers A and B2 are accessible to the user software (at
consecutive addresses).
Figure 17-20 provides an example of how the MDASM can be used to perform a single output compare.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-35
Modular Input/Output Subsystem (MIOS14)
Mode selection; MODE0 = 1
A Event
Output signal
F LAG reset
by software
B Event
Reoccurences of the timer count do
not trigger a response unless registers
A or B have been written again.
FLAG reset
by software
FLAG bit
16-bit
Counter Bus
0x0500
Write to A
0x1000
0x1100
0x1000
Write to B
0x1100
0x1000
Register A
0x1000
0x1000
Internal Register, not accessible to software
0x1000
0x1000
0x1000
0x1000
Register B1
0xxxxx
0xxxxx
0xxxxx
0xxxxx
0xxxxx
0xxxxx
Register B2
0xxxxx
0xxxxx
0xxxxx
0x1100
0x1100
0x1100
Figure 17-20. Single Shot Output Transition Example
17.9.3.5.3
Output Port Bit Operation
The output port bit operation is selected by leaving both channels disabled, (i.e., by writing to neither
register A nor B). The EDPOL bit alone controls the output value. The same result can be achieved by
keeping EDPOL at zero and using the FORCA and FORCB bits to obtain the desired output level.
17.9.3.6
Output Pulse Width Modulation (OPWM) Mode
OPWM mode is selected by setting MODE[0:3] to 1xxx. The MODE[1:3] bits allow some of the
comparator bits to be masked.
This mode allows pulse width modulated output waveforms to be generated, with eight selectable
frequencies. Frequencies are only relevant as such if the counter bus is driven by a counter as a time
reference. Both channels (A and B) are used to generate one PWM output signal on the MDASM signal.
Channel B is accessed via register B1. Register B2 is not accessible. Channels A and B define respectively
the leading and trailing edges of the PWM output pulse. The value in register B1 is transferred to register
B2 each time a match occurs on either channel A or B.
NOTE
A FORCA or FORCB does not cause a transfer from B1 to B2.
The value loaded in register A is compared with the value on the 16-bit counter bus each time the counter
bus is updated. When a match on A occurs, the FLAG line is activated and the output flip-flop is set. The
value loaded in register B2 is compared with the value on the 16-bit counter bus each time the counter bus
is updated. When a match occurs on B, the output flip-flop is reset.
MPC561/MPC563 Reference Manual, Rev. 1.2
17-36
Freescale Semiconductor
Modular Input/Output Subsystem (MIOS14)
NOTE
If both channels are loaded with the same value, when a simultaneous match
on A and B occurs, the submodule behaves as if a simple match on B had
occurred except for the FLAG line which is activated. The output flip-flop
is reset and the value in register B1 is transferred to register B2 on the match.
The polarity of the PWM output signal is selected by the EDPOL bit. The output flip-flop level can be
obtained at any time by reading the PIN bit.
If subsequent compares occur on channels A and B, the PWM pulses continue to be output, regardless of
the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-flop to the level
corresponding to a comparison on A or B respectively. Note that the FLAG line is not activated by the
FORCA and FORCB operations.
WARNING
Data registers A and B must be loaded with the values needed to produce
the desired PWM output pulse.
NOTE
16-bit counter bus compare only occurs when the 16-bit counter bus is
updated.
Figure 17-21 provides an example of how the MDASM can be used for pulse width modulation.
EDPOL = 0
A Compare
B Compare
Output signal
A Compare
Flag reset
by software
B Compare
Flag reset
by software
FLAG bit
0x1000
16-bit Counter Bus
Write 0x1000 to A
Write 0x1800 to B1
0x1100
0x1800
0x0000
0x1000
0x1700
Write to B1
Write to B1
Register A
0x1000
0x1000
0x1000
0x1000
0x1000
0x1000
Register B1
0x1800
0x1500
0x1500
0x1700
0x1700
0x1700
0x1500
0x1500
0x1700
0x1700
Register B2
0x1800
0x1800
Internal Register, not accessible to software
Figure 17-21. MDASM Output Pulse Width Modulation Example
To generate PWM output pulses of different frequencies, the 16-bit comparator can have some of its bits
masked. This is controlled by bits MODE2, MODE1and MODE0. The frequency of the PWM output
(fPWM) is given by the following equation (assuming the MDASM is connected to a 16-bit counter bus
used as time reference and fSYS is the frequency of the MIOS14 CLOCK):
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-37
Modular Input/Output Subsystem (MIOS14)
fPWM =
fSYS
NMCPSM • NCOUNTER • NMDASM
where:
• NMCPSM is the overall MCPSM clock divide ratio (2, 3, 4,...,16).
• NCOUNTER is the divide ratio of the prescaler of the counter (used as a time reference) that drives
the 16-bit counter bus.
• NMDASM is the maximum count reachable by the counter when using n bits of resolution (this
count is equal to 2n).
A few examples of frequencies and resolutions that can be obtained are shown in Table 17-17.
Table 17-17. MDASM PWM Example Output Frequencies/Resolutions at fSYS = 40 MHz
1
Resolution
(bits)
NMCPSM
NCOUNTER
NMDASM
PWM output frequency (Hz)1
16
16
256
65536
0.15
16
2
1
65536
305.17
15
16
256
32768
0.29
15
2
1
32768
610.35
14
16
256
16384
0.59
14
2
1
16384
1 220.70
13
16
256
8192
1.19
13
2
1
8192
2 441.41
12
16
256
4096
2.38
12
2
1
4096
4 882.81
11
16
256
2048
4.77
11
2
1
2048
9 765.63
9
16
256
512
19.07
9
2
1
512
39 062.50
7
16
256
128
76.29
7
2
1
128
156 250
This information is valid only if the MDASM is connected to an MMCSM operating as a free-running
counter.
When using 16 bits of resolution on the comparator (MODE[2:0] = 0b000), the output can vary from a 0%
duty cycle up to a duty cycle of 65535/65536. In this case it is not possible to have a 100% duty cycle. In
cases where 16-bit resolution is not needed, it is possible to have a duty cycle ranging from 0% to 100%.
Setting bit 15 of the value stored in register B to one results in the output being ‘always set’. Clearing bit
15 (to zero) allows normal comparisons to occur and the normal output waveform is obtained. Changes to
and from the 100% duty cycle are done synchronously on an A or B match, as are all other width changes.
MPC561/MPC563 Reference Manual, Rev. 1.2
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Modular Input/Output Subsystem (MIOS14)
In the OPWM mode, the WOR bit selects whether the output is totem pole driven or open-drain.
17.9.4
•
•
•
Modular I/O Bus (MIOB) Interface
The MDASM is connected to all the signals in the read/write and control bus, to allow data transfer
from and to the MDASM registers, and to control the MDASM in the different possible situations.
The MDASM is connected to four 16-bit counter buses available to that submodule instance, so
that the MDASM can select by software which one to use.
The MDASM uses the request bus to transmit the FLAG line to the interrupt request submodule
(MIRSM).
17.9.5
Effect of RESET on MDASM
When the reset signal is asserted, the MDASM registers are reset according to the values specified in
Section 17.9.6, “MDASM Registers.”
17.9.6
MDASM Registers
The privilege level to access the MDASM registers depends on the MIOS14MCR[SUPV]. The privilege
level is unrestricted after reset and can be changed to supervisor by software.
17.9.6.1
MDASM Registers Organization
The MDASM register map comprises four 16-bit register locations. As shown in below, the register block
contains four MDASM registers. Note that the MDASMSCRD is the duplication of the MDASMSCR.
This is done to allow 32-bit aligned accesses.
WARNING
The user should not write directly to the address of the MDASMSCRD. This
register’s address may be reserved for future use and should not be accessed
by the software to ensure future software compatibility.
All unused bits return zero when read by the software. All register addresses in this section are specified
as offsets from the base address of the MDASM.
Table 17-18. MDASM Address Map
Address
Register
MDASM11
0x30 6058
MDASM11 Data A Register (MDASMAR)
See Section 17.9.6.2, “MDASM Data A (MDASMAR) Register” for bit
descriptions.
0x30 605A
MDASM11 Data B Register (MDASMBR)
See Section 17.9.6.3, “MDASM Data B (MDASMBR) Register” for bit
descriptions.
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Modular Input/Output Subsystem (MIOS14)
Table 17-18. MDASM Address Map (continued)
Address
Register
0x30 605C
MDASM11 Status/Control Register Duplicated (MDASMSCRD)
See Table 17-21 for bit descriptions.
0x30 605E
MDASM11 Status/Control Register (MDASMSCR)
See Table 17-21 for bit descriptions.
MDASM12
0x30 6060
MDASM12 Data A Register (MDASMAR)
0x30 6062
MDASM12 Data B Register (MDASMBR)
0x30 6064
MDASM12 Status/Control Register Duplicated (MDASMSCRD)
0x30 6066
MDASM12 Status/Control Register (MDASMSCR)
MDASM13
0x30 6068
MDASM13 Data A Register (MDASMAR)
0x30 606A
MDASM13 Data B Register (MDASMBR)
0x30 606C
MDASM13 Status/Control Register Duplicated (MDASMSCRD)
0x30 606E
MDASM13 Status/Control Register (MDASMSCR)
MDASM14
0x30 6070
MDASM14 Data A Register (MDASMAR)
0x30 6072
MDASM14 Data B Register (MDASMBR)
0x30 6074
MDASM14 Status/Control Register Duplicated (MDASMSCRD)
0x30 6076
MDASM14 Status/Control Register (MDASMSCR)
MDASM15
0x30 6078
MDASM15 Data A Register (MDASMAR)
0x30 607A
MDASM15 Data B Register (MDASMBR)
0x30 607C
MDASM15 Status/Control Register Duplicated (MDASMSCRD)
0x30 607E
MDASM15 Status/Control Register (MDASMSCR)
MDASM27
0x30 60D8
MDASM27 Data A Register (MDASMAR)
0x30 60DA
MDASM27 Data B Register (MDASMBR)
0x30 60DC MDASM27 Status/Control Register Duplicated (MDASMSCRD)
0x30 60DE
MDASM27 Status/Control Register (MDASMSCR)
MDASM28
0x30 60E0
MDASM28 Data A Register (MDASMAR)
0x30 60E2
MDASM28 Data B Register (MDASMBR)
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Modular Input/Output Subsystem (MIOS14)
Table 17-18. MDASM Address Map (continued)
Address
Register
0x30 60E4
MDASM28 Status/Control Register Duplicated (MDASMSCRD)
0x30 60E6
MDASM28 Status/Control Register (MDASMSCR)
MDASM29
0x30 60E8
MDASM29 Data A Register (MDASMAR)
0x30 60EA
MDASM29 Data B Register (MDASMBR)
0x30 60EC
MDASM29 Status/Control Register Duplicated (MDASMSCRD)
0x30 60EE
MDASM29 Status/Control Register (MDASMSCR)
MDASM30
0x30 60F0
MDASM30 Data A Register (MDASMAR)
0x30 60F2
MDASM30 Data B Register (MDASMBR)
0x30 60F4
MDASM30 Status/Control Register Duplicated (MDASMSCRD)
0x30 60F6
MDASM30 Status/Control Register (MDASMSCR)
MDASM31
17.9.6.2
0x30 60F8
MDASM31 Data A Register (MDASMAR)
0x30 60FA
MDASM31 Data B Register (MDASMBR)
0x30 60FC
MDASM31 Status/Control Register Duplicated (MDASMSCRD)
0x30 60FE
MDASM31 Status/Control Register (MDASMSCR)
MDASM Data A (MDASMAR) Register
MSB
0
LSB
1
Field
SRESET
Addr
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AR
Undefined
0x30 6058, 0x30 6060, 0x30 6068, 0x30 6070, 0x30 6078,
0x30 60D8, 0x30 60E0, 0x30 60E8, 0x30 60F0, 0x30 60F8
Figure 17-22. MDASM Data A Register (MDASMAR)
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Modular Input/Output Subsystem (MIOS14)
Table 17-19. MDASMAR Bit Descriptions
Bits
Name
Description
0:15
AR
MDASMAR is the data register associated with channel A; its use varies with the different modes of
operation:
DIS mode: MDASMAR can be accessed to prepare a value for a subsequent mode selection.
IPWM mode: MDASMAR contains the captured value corresponding to the trailing edge of the measured
pulse.
IPM and IC modes: MDASMAR contains the captured value corresponding to the most recently detected
dedicated edge (rising or falling edge).
OCB and OCAB modes: MDASMAR is loaded with the value corresponding to the leading edge of the
pulse to be generated. Writing to MDASMAR in the OCB and OCAB modes also enables the
corresponding channel A comparator until the next successful comparison.
OPWM mode: MDASMAR is loaded with the value corresponding to the leading edge of the PWM pulse
to be generated.
NOTE: In IC, IPM, or IPWM mode, when a read to register A or B occurs at the same time as a counter
bus capture into that register and the counter bus is changing value, then the counter bus capture to that
register is delayed.
17.9.6.3
MDASM Data B (MDASMBR) Register
MSB
0
Field
SRESET
Addr
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BR
Undefined
0x30 605A, 0x30 6062, 0x30 606A, 0x30 6072, 0x30 607A,
0x30 60DA, 0x30 60E2, 0x30 60EA, 0x30 60F2, 0x30 60FA
Figure 17-23. MDASM DataB Register (MDASMBR)
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Modular Input/Output Subsystem (MIOS14)
Table 17-20. MDASMBR Bit Descriptions
Bits
Nam
e
0:15
BR
17.9.6.4
Description
MDASMBR is the data register associated with channel B; its use varies with the different modes of
operation.
Writing to register B always writes to B1 and, depending on the mode selected, sometimes to B2. Reading
register B either reads B1 or B2 depending on the mode selected.
In the DIS mode, MDASMBR can be accessed to prepare a value for a subsequent mode selection. In this
mode, register B1 is accessed in order to prepare a value for the OPWM mode. Unused register B2 is hidden
and cannot be read, but is written with the same value when register B1 is written.
In the IPWM mode, MDASMBR contains the captured value corresponding to the leading edge of the
measured pulse. In this mode, register B2 is accessed; buffer register B1 is hidden and is not readable.
In the IPM and IC modes, MDASMBR contains the captured value corresponding to the previously dedicated
edge (rising or falling edge). In this mode, register B2 is accessed; buffer register B1 is hidden and is not
readable.
In the OCB and OCAB modes, MDASMBR is loaded with the value corresponding to the trailing edge of the
pulse to be generated. Writing to MDASMBR in the OCB and OCAB modes also enables the corresponding
channel B comparator until the next successful comparison. In this mode, register B2 is accessed; buffer
register B1 is hidden and is not readable.
In the OPWM mode, MDASMBR is loaded with the value corresponding to the trailing edge of the PWM pulse
to be generated. In this mode, register B1 is accessed; buffer register B2 is hidden and cannot be accessed.
NOTE: In IC, IPM, or IPWM mode, when a read to register A or B occurs at the same time as a counter bus
capture into that register and the counter bus is changing value, then the counter bus capture to that register
is delayed.
MDASM Status/Control Register (MDASMSCRD) (Duplicated)
The MDASMSCRD and the MDASMSCR are the same registers accessed at two different addresses.
Reading or writing to one of these two addresses has exactly the same effect.
WARNING
The user should not write directly to the address of the MDASMSCRD. This
register’s address may be reserved for future use and should not be accessed
by the software to ensure future software compatibility.
The duplication of the SCR register allows coherent 32-bit accesses when using an RCPU.
17.9.6.5
MDASM Status/Control Register (MDASMSCR)
The status and control register gathers a read only bit reflecting the status of the MDASM signal as well
as read/write bits related to its control and configuration.
The signal input status bit reflects the status of the corresponding signal when in input mode. When in
output mode, the PIN bit only reflects the status of the output flip-flop.
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Modular Input/Output Subsystem (MIOS14)
MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
15
Field PIN WOR FREN
SRESET
Addr
LSB
—
—
EDPOL FORCA FORCB
—
BSL
—
MODE
000_0000_0000_0000
0x30 605E, 0x30 6066, 0x30 606E, 0x30 6076, 0x30 607E, 0x30 60DE, 0x30 60E6, 0x30 60EE,
0x30 60F6, 0x30 60FE
Figure 17-24. MDASM Status/Control Register (MDASMSCR)
Table 17-21. MDASMSCR Bit Descriptions
Bits
Name
Description
0
PIN
1
WOR
Wired-OR bit — In the DIS, IPWM, IPM and IC modes, the WOR bit is not used; reading this bit
returns the value that was previously written.
In the OCB, OCAB and OPWM modes, the WOR bit selects whether the output buffer is
configured for open-drain or totem pole operation. When open-drain mode is selected, the
EDPOL bit is not used; writing to EDPOL will have no effect on the output voltage.
1 Output buffer is open-drain.
0 Output buffer is totem pole.
The WOR bit is cleared by reset.
2
FREN
Freeze enable bit — This active high read/write control bit enables the MDASM to recognize the
MIOB freeze signal.
1 = The MDASM is frozen if the MIOB freeze line is active.
0 = The MDASM is not frozen even if the MIOB freeze line is active.
The FREN is cleared by reset.
3
—
4
EDPOL
Polarity bit — In the DIS mode, this bit is not used; reading it returns the last value written.
In the IPWM mode, this bit is used to select the capture edge sensitivity of channels A and B.
1 Channel A captures on a falling edge. Channel B captures on a rising edge.
0 Channel A captures on a rising edge. Channel B captures on a falling edge.
In the IPM and IC modes, the EDPOL bit is used to select the input capture edge sensitivity of
channel A.
1 Channel A captures on a falling edge.
0 Channel A captures on a rising edge.
In the OCB, OCAB and OPWM modes, the EDPOL bit is used to select the voltage level on the
output signal. If open-drain mode is selected via the WOR bit, the EDPOL bit is disabled and
writing to it will have no effect on the output voltage.
1 The complement of the output flip-flop logic level appears on the output signal: a match on
channel A resets the output signal; a match on channel B sets the output signal.
0 The output flip-flop logic level appears on the output signal: a match on channel A sets the
output signal, a match on channel B resets the output signal.
The EDPOL bit is cleared by reset.
5
FORCA
Force A bit — In the OCB, OCAB and OPWM modes, the FORCA bit allows the software to force
the output flip-flop to behave as if a successful comparison had occurred on channel A (except
that the FLAG line is not activated). Writing a one to FORCA sets the output flip-flop; writing a
zero to it has no effect.
In the DIS, IPWM, IPM and IC modes, the FORCA bit is not used and writing to it has no effect.
FORCA is cleared by reset and is always read as zero.
Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop.
Pin Input Status — The pin input status bit reflects the status of the corresponding bit.
Reserved
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Modular Input/Output Subsystem (MIOS14)
Table 17-21. MDASMSCR Bit Descriptions (continued)
Bits
Name
Description
6
FORCB
Force B bit — In the OCB, OCAB and OPWM modes, the FORCB bit allows the software to force
the output flip-flop to behave as if a successful comparison had occurred on channel B (except
that the FLAG line is not activated). Writing a one to FORCB resets the output flip-flop; writing a
zero to it has no effect.
In the DIS, IPWM, IPM and IC modes, the FORCB bit is not used and writing to it has no effect.
FORCB is cleared by reset and is always read as zero.
Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop.
7:8
—
9:10
BSL
11
—
12:15
MODE
Reserved
Bus select bits — These bits are used to select which of the six 16-bit counter buses is used by
the MDASM. Each MDASM instance has four possible counter buses that may be connected.
See Table 17-23 for more information.
NOTE: Unconnected counter buses inputs are grounded.
Reserved
Mode select bits — The four mode select bits select the mode of operation of the MDASM. To
avoid spurious interrupts, it is recommended that MDASM interrupts are disabled before
changing the operating mode.
The mode select bits are cleared by reset.
NOTE: The reserved modes should not be set; if these modes are set, the MDASM behavior is
undefined.
Table 17-22. MDASM Mode Selects
MDASM Control Register Bits
Bits of
Resolution
Counter
Bus Bits
Ignored
0000
—
—
DIS – Disabled
0001
16
—
IPWM – Input pulse width measurement
0010
16
—
IPM – Input period measurement
0011
16
—
IC – Input capture
0100
16
—
OCB – Output compare, flag on B compare
0101
16
—
OCAB – Output compare, flag on A and B compare
0110
—
—
Reserved
0111
—
—
Reserved
1000
16
—
OPWM – Output pulse width modulation
1001
15
0
OPWM – Output pulse width modulation
1010
14
0,1
OPWM – Output pulse width modulation
1011
13
0-2
OPWM – Output pulse width modulation
1100
12
0-3
OPWM – Output pulse width modulation
1101
11
0-4
OPWM – Output pulse width modulation
MODE
MDASM Mode of Operation
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Modular Input/Output Subsystem (MIOS14)
Table 17-22. MDASM Mode Selects (continued)
MDASM Control Register Bits
Bits of
Resolution
Counter
Bus Bits
Ignored
1110
9
0-6
OPWM – Output pulse width modulation
1111
7
0-8
OPWM – Output pulse width modulation
MODE
MDASM Mode of Operation
Table 17-23. MDASM Counter Bus Selection
Connected to:
SubModule
Type
Block
Number
MDASM
CBA
CBB
CBC
CBD
BSL0=0
BSL1=0
BSL0=1
BSL1=0
BSL0=0
BSL1=1
BSL0=1
BSL1=1
11
CB6
CB22
CB7
CB8
MDASM
12
CB6
CB22
CB7
CB8
MDASM
13
CB6
CB22
CB23
CB24
MDASM
14
CB6
CB22
CB23
CB24
MDASM
15
CB6
CB22
CB23
CB24
MDASM
27
CB6
CB22
CB23
CB24
MDASM
28
CB6
CB22
CB23
CB24
MDASM
29
CB6
CB22
CB7
CB8
MDASM
30
CB6
CB22
CB7
CB8
MDASM
31
CB6
CB22
CB7
CB8
17.10 MIOS14 Pulse Width Modulation Submodule (MPWMSM)
The MIOS14 pulse width modulation submodule (MPWMSM) is a function included in the MIOS14
library. It allows pulse width modulated signals to be generated over a wide range of frequencies,
independently of other MIOS14 output signals and with no software intervention. The output pulse width
can vary from 0% to 100%. The minimum pulse width is twice the minimum MIOS14 CLOCK period
(i.e., the minimum pulse width is 50 ns when fSYS is 40 MHz). The MWPMSM can run in a
double-buffered mode, to avoid spurious update.
The following sections describe the MPWMSM in detail. A block diagram of the MPWMSM is shown in
Figure 17-25.
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Modular Input/Output Subsystem (MIOS14)
PS7 - PS0
Counter
Clock
8- bit Prescaler
FREN
(Ncount)
EN
TRSP
16-bit Down Counter
MPWMCNTR
= 0x0001
16-bit
SC
– Read/write address (write address) -> RWAD
– Read/write (1 to indicate a write access) -> RW
– Word size (32 bits, 16 bits, 8 bits) -> SZ
– Write data (write data) -> WD
– Privilege (user data/instruction, supervisor data/instruction) -> PRV
– Map select (select memory map, 0b0 or 0b1) -> MAP
0 = Normal memory access
1 = Secondary memory map (SPR)
– Access Count (0 to indicate single access) -> CNT
3. After completion of the write operation, the device ready for upload/download public message
(TCODE=16) is transmitted to the tool indicating that the device is ready for next access.
4. The SC bit is cleared to indicate that the write access is complete.
24.10.2.2 Block Write Operation
For a block write access to memory-mapped locations, the following sequence of operations need to be
performed via the auxiliary port:
1. The tool confirms that the device is ready before transmitting download request public message
(TCODE = 18).
2. The download request public message contains:
a) TCODE(18)
b) Access opcode 0xF which signals that subsequent data needs to be stored in the RWA register.
c) Configure the RWA register fields as follows
– Start/complete (1 to indicate start access) -> SC
– Read/write address (starting write address of block) -> RWAD
– Read/write (1 to indicate a write access) -> RW
– Word size (32 bits, 16 bits, 8 bits) -> SZ
– Write data (write data) -> WD
– Privilege (user data/instruction, supervisor data/instruction) -> PRV
– Map select (select memory map 0b0) -> MAP
– Access count (non zero number to indicate size of block access) -> CNT
3. After completion of this write operation, the device ready for upload/download public message
(TCODE = 16) is transmitted to the tool indicating that the device is ready for next access.
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READI Module
4. The specified address (stored in RWAD field) is incremented to the next word size and the number
in the CNT field is decremented. The SC field is not cleared.
5. The tool transmits the next upload/download information public message (TCODE = 19).
6. The upload/download information public message contains:
a) TCODE(19)
b) Write data (write data -> UDI)
7. After the completion of this write operation, the device ready for upload/download public message
(TCODE = 16) is transmitted to the tool indicating that the device is ready for next access.
8. The specified address (in RWAD field) is incremented to the next word size and the number in the
CNT field is decremented. The SC field is not cleared.
9. Steps 5 through 8 are repeated until the count value in the CNT field of RWA register equals zero.
The SC bit is cleared to indicate end of the block write access.
NOTE
For downloading write data to the device for block write operation, the
download request public message (TCODE = 18) should not be used to
write subsequent data to the UDI register. Data written to the UDI register
(via download request message, TCODE 18) is not used by the device for
any read/write operation.
24.10.3 Read Operation to Memory-Mapped Locations and SPR Registers
24.10.3.1 Single Read Operation
For a single read access to memory-mapped locations and SPR registers, the following sequence of
operations need to be performed via the auxiliary port:
1. The tool confirms that the device is ready before transmitting download request public message
(TCODE = 18).
2. The download request public message contains:
a) TCODE(18)
b) Access opcode 0xF which signals that subsequent data needs to be stored in the RWA register.
c) Configure the RWA fields as follows:
– Start/complete (1 to indicate start access) -> SC
– Read/write address (read address) -> RWAD
– Read/write (0 to indicate a read access) -> RW
– Word size (32 bits, 16 bits, 8 bits) -> SZ
– Write data (0xXXXXXXXX-> WD [don’t care])
– Privilege (user data/instruction, supervisor data/instruction) > PRV
– Map select (select memory map, 00 or 01) -> MAP
– Access count (0 to indicate single access) -> CNT
3. Data read from the specified address is stored in the UDI register.
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READI Module
4. Once the read access is completed, the upload/download information public message (TCODE =
19) is transmitted to the tool along with the data read from the UDI register. This message also
indicates that the device is ready for next access.
5. The SC field in the RWA register is cleared.
24.10.3.2 Block Read Operation
For a block read access to memory-mapped locations and SPR registers, the following sequence of
operations need to be performed via the auxiliary port:
1. The tool confirms that the device is ready before transmitting download request public message
(TCODE = 18).
2. The download request public message contains:
a) TCODE(18)
b) Access opcode 0xF which signals that subsequent data needs to be stored in the RWA register.
c) Configure the RWA fields as follows:
– Start/complete (1 to indicate start access) -> SC
– Read/write address (starting read address of block) -> RWAD
– Read/write (0 to indicate a read access) -> RW
– Word size (32 bits, 16 bits, 8 bits) -> SZ
– Write data (0xXXXXXXXX-> WD [don’t care])
– Privilege (user data/instruction, supervisor data/instruction) > PRV
– Map select (select memory map 0b0) -> MAP
– Access count (non-zero number to indicate block access) -> CNT
3. Data read from the specified address is stored in the UDI register.
4. After the completion of this read operation, the upload/download information public message
(TCODE=19) is transmitted to the tool along with the data read from the UDI register. This
message also indicates that the device is ready to perform the next read operation.
5. The specified address (in RWAD field) is incremented to the next word size and the number in the
CNT field is decremented. The SC field is not cleared.
6. The data read from the new address is stored in the UDI register.
7. Steps 4 through 7 are repeated until the count value in the CNT field of RWA register equals zero.
The SC bit is cleared to indicate end of the block read access.
24.10.4 Read/Write Access to Internal READI Registers
24.10.4.1 Write Operation
For a write access to internal READI registers, the following sequence of operations need to be performed
via the auxiliary port:
1. The tool confirms that the device is ready before transmitting download request public message
(TCODE = 18).
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READI Module
2. The download request public message contains:
a) TCODE(18)
b) Access opcode, which specifies the register where data needs to be written, (e.g., access opcode
0x14 indicates that DTA1 register is the target register).
c) Data to be written to the register.
3. After the data has been written to the targeted register, the device ready for upload/download public
message (TCODE = 16) is transmitted to the tool indicating that the device is ready for next access.
24.10.4.2 Read Operation
For a read access to internal READI registers, the following sequence of operations need to be performed
via the auxiliary port:
1. The tool confirms that the device is ready before transmitting upload request public message
(TCODE = 17).
2. The upload request public message contains:
a) TCODE(17)
b) Access opcode, which specifies the register where data needs to be read from, (for example,
access opcode 0x14 indicates that DTA1 register is the target register).
3. The upload/download information public message (TCODE=19) is transmitted to the tool along
with the data read from the targeted register indicating that the device is ready for next access.
24.10.5 Error Handling
The READI module handles the various error conditions in the manner shown in the following sections.
24.10.5.1 Access Alignment
The READI module will force address alignment based on the word size field (SZ) value. If the SZ field
indicates word (32-bit) access, the least significant two bits of the read/write address field (RWAD) are
ignored. If the SZ field indicates half-word (16-bit) access, the least significant bit of the read/write address
field (RWAD) is ignored.
24.10.5.2 L-Bus Address Error
An address error occurs on the L-bus when the address phase of a cycle is not completed normally. This
could occur because of address not being valid or the address map not being valid. In such cases:
1. The access is terminated without retrying.
2. The SC bit of the RWA is reset. Block accesses do not continue.
3. The error message (TCODE = 8) is transmitted (error code 0b00011). Refer to Table 24-20.
24.10.5.3 L-Bus Data Error
L-bus data error is signalled due to:
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•
•
•
L-bus data phase error.
U-bus address phase error (for a L-bus to U-bus cycle).
U-bus data phase error (for a L-bus to U-bus cycle).
L-bus data error conditions are signalled along with the transfer acknowledge for the access. L-bus data
error conditions may occur because of privilege violations, access to protected memory, etc. In such cases,
for a read access, the ERR bit of the UDI is set, and the DV bit in the UDI is reset at the termination of the
access. For a write access, an error public message (TCODE = 8) is transmitted (error code 0b00011).
24.10.6 Exception Sequences
The following cases are defined for sequences of the read/write protocol that differ from those described
in the above sections:
1. If the SC bit is set to start READI read/write accesses, without valid values in the RWAD, then an
L-bus address error may occur, which is handled as described above.
2. If a block access is in progress with all the cycles not yet completed, and the RWA is written to
again, (with or without modifications), then the block access is terminated at the boundary of the
nearest completed access. The resulting data is discarded and not written to the UDI. If a new
access has been programmed in the RWA register, then that access will start once the controller has
recovered.
3. When a block access is in progress with all the cycles not yet completed, writing the SC bit to 0 in
RWA register will terminate the block access and device will send out device ready for
upload/download message.
4. If a any type (single/block) of access is in progress with the cycles not yet completed, and system
reset occurs, the device will send out an error message. The access will be terminated and the SC
bit will be reset. Refer to Table 24-20.
5. If any type of (single/block) of access is requested while system is in reset, the device will send out
an error message. The access will not be started and the SC bit will be reset.
24.10.7 Secure Mode
For details refer to Section 24.2.2, “Security.”
24.10.8 Error Messages
24.10.8.1 Read/Write Access Error
An error message is sent out when an L-bus access error or data error on a write access occurs. The error
code within the error message indicates that an L-bus address or L-bus data error occurred. For other error
handling, see Section 24.10.5, “Error Handling.” For a list of error codes, refer to Table 24-20.
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The error message has the following format:
[5 bits]
[6 bits]
TCODE (8)
Error Code (0b00011)
Length = 11 bits
Figure 24-60. Error Message (Read/Write Access Error) Format
24.10.8.2 Invalid Message
An error message is sent out when an invalid message is received by READI. The error code within the
error message indicates that an invalid TCODE was detected in the auxiliary input messages by the signal
input formatter. Refer to Table 24-20.
The error message has the following format:
[5 bits]
[6 bits]
TCODE (8)
Error Code (0b00100)
Length = 11 bits
Figure 24-61. Error Message (Invalid Message) Format
NOTE
If the TCODE is valid, then READI will expect that the correct number of packets have been received and
no further checking will be performed. If the number of packets received by READI is not correct, READI
response is not deterministic.
24.10.8.3 Invalid Access Opcode
An error message is sent out when an invalid access opcode is received by READI. The error code within
the error message indicates that an invalid access opcode was detected in the auxiliary input messages by
the signal input formatter. Refer to Table 24-20.
The error message has the following format:
[6 bits]
TCODE (8)
[5 bits]
Error Code (0b00101)
Length = 11 bits
Figure 24-62. Error Message (Invalid Access Opcode) Format
24.10.9 Faster Read/Write Accesses with Default Attributes
Read/write access throughput may be increased by taking advantage of the default settings of the RWA
register, and truncating the least significant zero bits of the download request message. For example, to
read a word from the default memory map, with default attributes, a download request message that selects
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the RWA register, and transmits the SC, RWAD, RW fields only is sufficient. This message will contain
41 bits instead of the 94 bits for writing the full contents of the RWA register. See Table 24-11 and
Section 24.6.4, “Partial Register Updates,” for RWAR and partial register update details respectively.
NOTE
The last data bit transmitted in the download request message (TCODE 18)
will always be the MSB of the register referenced by the opcode (SC field
in the case of the RWA register).
24.10.10 Throughput and Latency
Throughput analysis has been performed for various read/write access cases such as single write, block
write, single byte read, single word read, block byte read, block word read accesses to memory-mapped
locations. Data is presented for the two cases when the RWA register is written partially and completely.
24.10.10.1 Assumptions for Throughput Analysis
•
•
•
•
•
•
•
•
All accesses are single read accesses only.
MCKI running at 28 MHz.
MCKO running at 56 MHz.
56-MHz internal operation.
Five clock internal L-bus access (read)
Output signals always free (not in middle of transmission) when requested.
One idle clock between read messages.
No delay from tool in responding — tool keeps up with READI port.
Table 24-31. Throughput Comparison for FPM and RPM MDO/MDI Configurations
Reduced Port Mode
2 MDO / 1 MDI pins
Full Port Mode
8 MDO / 2 MDI pins
Access Type
Full RWAR
Update
Partial RWAR
Update
Full RWAR
Update
Partial RWAR
Update
Single Write Access to memory-mapped
location – Word and Byte access
(In Million Messages Per Second)
0.28
0.35
0.53
0.65
Single Read Access to memory-mapped
location – Word access
(In Million Messages Per Second)
0.25
0.51
0.52
1.05
Single Read Access to memory-mapped
location – Byte access
(In Million Messages Per Second)
0.27
0.56
0.53
1.05
9
9
17
17
Block Write Access to memory-mapped
locations – 64-Kbyte block (Word and Byte) write
access
(In 64-Kbyte Block Writes Per Second)
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Table 24-31. Throughput Comparison for FPM and RPM MDO/MDI Configurations
Reduced Port Mode
2 MDO / 1 MDI pins
Full Port Mode
8 MDO / 2 MDI pins
Access Type
Full RWAR
Update
Partial RWAR
Update
Full RWAR
Update
Partial RWAR
Update
Block Read Access to memory-mapped
locations – 64-Kbyte block (Word) read access
(In 64-Kbyte Block Writes Per Second)
32
32
77
77
Block Read Access to memory-mapped
locations – 64-Kbyte block (Byte) read access
(In 64-Kbyte Block Writes Per Second)
61
61
95
95
24.11 Read/Write Timing Diagrams
MSEI
MSEO
MDI
Upload/Download
Information Message
TCODE 19
Download Request
Message
TCODE 18
MDO
Device Ready
for Upload/
Download
TCODE 16
Device Ready
for Upload/
Download
TCODE 16
Figure 24-63. Block Write Access
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MSEI
MSEO
MDI
Download Request
Message
TCODE 18
Upload/Download
Information Message
TCODE 19
MDO
Upload/Download
Information Message
TCODE 19
Figure 24-64. Block Read Access
MCKO
MSEO
MDO[7:0]
00010000
TCODE = 16 (0x10)
00000000
00000000
Don’t care data
(idle clock)
Figure 24-65. Device Ready for Upload/Download Request Message
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MCKI
MSEI
MDI[1:0]
01
00
01
11
11
00
00
00
Don’t care data
(idle clock)
TCODE = 17 (0x11)
Access Opcode = 15 (RWA register) (0xE)
Figure 24-66. Upload Request Message
MCKI
MSEI
MDI[1:0]
10
00
01
10
10
00
00
00
TCODE = 18 (0x12)
Access Opcode = 10 (DC register) (0xA)
Data written to DC register:
EC = 0b00
00
01
00
00
Don’t care data
(idle clock)
TM = 0b100
DPA = 0b0
DME = 0b0
DOR = 0b0
Figure 24-67. Download Request Message
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MCKO
MSEO
MDO[7:0]
01010011
00010110
TCODE = 19 (0x13)
DV =1
ERR = 0
Data Read = 0x3C16 (16 bit read access)
00111100
00000000
Don’t care data
(idle clock)
Figure 24-68. Upload/Download Information Message
MCKO
MSEO
MDO[7:0]
01001000
00000000
00000001
TCODE = 8
Error Code = 0b00101 (Invalid Access Opcode)
Don’t care data
(idle clock)
Figure 24-69. Error Message (Invalid Access Opcode)
24.12 Watchpoint Support
This section details the watchpoint support features of the READI module.
The READI module provides watchpoint messaging via the auxiliary port, as defined by the IEEE-ISTO
5001-1999.
READI is not compliant with all the breakpoint/watchpoint requirements defined in the IEEE-ISTO 5001
standard. Watchpoint trigger and breakpoint/watchpoint control registers are not implemented.
Watchpoint setting via READI can only be done using the BDM protocol.
24.12.1 Watchpoint Messaging
The READI module provides watchpoint messaging using IEEE-ISTO 5001-1999 defined public
messages. The watchpoint status signals from the RCPU are snooped, and when watchpoints occur, a
message is sent to the signal output formatter to be messaged out (the general message queue is bypassed
to prevent watchpoint messages from being cancelled in the event of a queue overflow). The watchpoint
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message has the second highest priority. Refer to Section 24.7.3, “Message Priority,” for further details on
message priorities. The watchpoint message contains the watchpoint code which indicates all the unique
watchpoints have occurred since the last watchpoint message. If duplicate watchpoints occur before the
watchpoint message is sent out, a watchpoint overrun message is generated. The watchpoint source field
will indicate which watchpoints occurred.
The watchpoint message has the following format:
[6 bits]
[6 bits]
TCODE (15)
Watchpoint Source
Length = 12 bits
Figure 24-70. Watchpoint Message Format
24.12.1.1 Watchpoint Source Field
The watchpoint source field is outlined in Table 24-32.
Table 24-32. Watchpoint Source
Watchpoint Source
Description
0bXXXXX1
First L-bus watchpoint (LW0)
0bXXXX1X
Second L-bus watchpoint (LW1)
0bXXX1XX
First I-bus watchpoint (IW0)
0bXX1XXX
Second I-bus watchpoint (IW1)
0bX1XXXX
Third I-bus watchpoint (IW2)
0b1XXXXX
Fourth I-bus watchpoint (IW3)
24.12.2 Watchpoint Overrun Error Message
A watchpoint overrun error occurs when the same watchpoint occurs multiple times before the first
occurrence of that watchpoint has been messaged out. The watchpoint message (which has information of
all the watchpoints that occurred prior to the detection of the same watchpoint occurring multiple times)
will be sent before the error message can be sent.
The overrun error causes further watchpoint occurrences to be ignored, until the error message has been
sent. The error code within the error message indicates that a watchpoint overrun error has occurred. Refer
to Table 24-20.
The error message has the following format:
[6 bits]
[5 bits]
TCODE (8)
Error Code (0b00110)
Length = 11 bits
Figure 24-71. Error Message (Watchpoint Overrun) Format
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24.12.3 Synchronization
Upon occurrence of a watchpoint, the next program and data trace message will be a synchronization
message (provided program and data trace are enabled).
24.12.4 Watchpoint Timing Diagrams
MCKO
MSEO
MDO[7:0]
01001111
00001100
00000000
Don’t care data
(idle clock)
TCODE = 15 (0xE)
Watchpoint Source = 0b110001
This indicates that First L-bus watchpoint (LWO), Third I-bus watchpoint (IW2),
and Fourth I-bus watchpoint (IW3) have occurred.
Figure 24-72. Watchpoint Message
MCKO
MSEO
MDO[7:0]
10001000
00000001
TCODE = 8
Error Code = 0b00110 (Watchpoint Overrun)
00000000
Don’t care data
(idle clock)
Figure 24-73. Error Message (Watchpoint Overrun)
24.13 Ownership Trace
This section details the ownership trace support features of the READI module.
Ownership trace provides a macroscopic view, such as task flow reconstruction, when debugging software
written in a high level (or object-oriented) language. It offers the highest level of abstraction for tracking
operating system software execution. This is especially useful when the developer is not interested in
debugging at lower levels.
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24.13.1 Ownership Trace Messaging
Ownership trace information is messaged via the auxiliary port using an ownership trace message (OTM).
The ownership trace register (OT), which can be accessed via auxiliary port, is updated by the operating
system software to provide task/process ID information. When new information is updated in the register
by the embedded processor, it is messaged out via the auxiliary port, allowing development tools to trace
ownership flow.
Ownership trace information is messaged out in the following format:
[32 bits]
[6 bits]
TCODE (2)
Task/Process ID Tag
Length = 38 bits
Figure 24-74. Ownership Trace Message Format
24.13.2 Queue Overflow Ownership Trace Error Message
A program/data/ownership trace overrun error occurs when a trace message cannot be queued due to the
queue being full, provided ownership trace is enabled.
The overrun error causes the message queue to be flushed, and a error message to be queued. The error
code within the error message indicates that a program/data/ownership trace overrun error has occurred.
Refer to Table 24-20.
The error message has the following format:
[6 bits]
TCODE (8)
[5 bits]
Error Code (0b0 0000,
0b0 0001, 0b0 0010,
0b0 0111)
Length = 11 bits
Figure 24-75. Error Message Format
24.13.2.1 OTM Flow
Ownership trace messages are generated when the operating system (privileged supervisor task) writes to
the memory-mapped ownership trace register.
The following flow describes the OTM process.
1. The OT register is a memory-mapped register, whose address is located in the UBA. The OT
register address can be read from the UBA register by the IEEE-ISTO 5001 tool.
2. Only privileged writes (byte/half word or word) initiated by the RCPU to the OT register that
terminate normally are valid. The data value (word) written into the register is formed into the
ownership trace message that is queued to be transmitted.
3. OT register reads and non-privileged OT register writes, or writes initiated by any source other than
the RCPU, do not cause ownership trace messages to be transmitted by the READI module.
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24.13.2.2 OTM Queueing
READI implements a queue 32 messages deep for program trace, data trace, and ownership trace
messages. Messages that enter the queue are transmitted via the output auxiliary port in the order in which
they are queued.
NOTE
If multiple trace messages need to be queued at the same time, ownership
trace messages will have the lowest priority.
24.13.3 OTM Timing Diagrams
MCKO
MSEO
01000010 11001000 01010000 11011001
MDO[7:0]
00100001 00000000
Don’t care data
(idle clock)
TCODE = 2
Task/Process ID Tag = 0x87654321
Figure 24-76. Ownership Trace Message
MCKO
MSEO
MDO[7:0]
11001000
00000001
TCODE = 8
Error Code = 0b00111 (Program/Data/Ownership trace overrun)
00000000
Don’t care data
(idle clock)
Figure 24-77. Error Message (Program/Data/Ownership Trace Overrun)
24.14 RCPU Development Access
This section details the RCPU development access support features of the READI module.
The READI development port provides a full duplex serial interface for accessing existing RCPU user
register and development features including BDM (background debug mode).
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RCPU development access can be achieved either via the READI signals or the BDM signals on the MCU.
The access method is determined during READI module configuration. Figure 24-78 shows how READI
and BDM signals are multiplexed for RCPU development access.
When the READI module is configured for RCPU development access, IEEE-ISTO 5001 compliant
vendor-defined messages are used for transmission of data in and out of the MCU.
NOTE
On the MPC561/MPC563 the BDM signals are shared with the READI
signals. Therefore BDM access is limited to access via the Nexus
vendor-defined development support messages.
READI
DSCK
DSDI
DSDO
RCPU development Mux Control
Debug
JTAG
..
.
..
.
TCK / DSCK / MCKI
BDM
TDO / DSDO / MDO0 signals
TDI / DSDI / MDI0
USIU
RCPU
Development
Access
Multiplexer
Figure 24-78. RCPU Development Access Multiplexing between READI and BDM Signals
24.14.1 RCPU Development Access Messaging
The following RCPU development access messages are used for handshaking between the device and the
tool — DSDI data message, DSDO data message, and BDM status message.
24.14.1.1 DSDI Message
The DSDI message is used by the tool to download information to the RCPU.
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The DSDI data field has a 3-bit status header followed by 7 or 32 bits of data/instruction, depending on
the RCPU development port mode.
The DSDI message has the following format:
[6 bits]
[10 or 35 bits]
TCODE (56)
DSDI data
Max Length = 41 bits
Min Length = 16 bits
Figure 24-79. DSDI Message Format
NOTE
When sending in a DSDI data message, the DSDI data should contain the
control and status bits (start, mode, control), followed by the 7 or 32-bit
CPU instruction/data or trap enable, MSB first. See Figure 24-85 for DSDI
data message transmission sequence.
24.14.1.2 DSDO Message
The DSDO message is used by the device to upload information from the RCPU.
The DSDO data field has a 3-bit status header followed by 7 or 32 bits of data/instruction, depending on
the RCPU development port mode.
The three status bits in the DSDO data indicates if the device is ready to receive the next message from the
tool.
The DSDO message has the following format:
[6 bits]
[10 or 35 bits]
TCODE (57)
DSDO data
Max Length = 41 bits
Min Length = 16 bits
Figure 24-80. DSDO Message Format
NOTE
The DSDO data received will contain the control and status bits and data
from the CPU, MSB first. See Figure 24-85 for DSDO data message
transmission sequence.
24.14.1.3 BDM Status Message
BDM status message is generated by the device to let the tool know about the status of debug mode.
BDM status message (with BDM status field equal to 0b1) is sent when the RCPU is in debug mode and
the device is ready to receive debug mode messages.
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BDM status message (with BDM status field equal to 0b0) is sent out when the device exits BDM mode
and RCPU is in normal operating mode.
The BDM status message has the following format:
[1 bit]
[6 bits]
TCODE (58)
BDM Status
Length = 7 bits
Figure 24-81. BDM Status Message Format
24.14.1.4 Error Message (Invalid Message)
An error message is sent out when an invalid message is received by READI. The error code within the
error message indicates that an invalid TCODE was detected in the auxiliary input messages by the signal
input formatter. Refer to Table 24-20.
The error message has the following format:
[5 bits]
[6 bits]
TCODE (8)
Error Code (0b00100)
Length = 11 bits
Figure 24-82. Error Message (Invalid Message) Format
24.14.2 RCPU Development Access Operation
The RCPU development access can be achieved either via the READI signals or the BDM signals.
To enable RCPU development access via the READI signals, the tool has to configure the DC register
during the READI reset (RSTI). Once the READI module takes the control of RCPU development access,
the protocol for transmission of development serial data in (DSDI) and out (DSDO) is performed through
the IEEE-ISTO 5001-1999 compliant vendor-defined messages.
After enabling RCPU development access via the READI signals, the READI module can enable debug
mode and enter debug mode. When debug mode is enabled and entered, READI sends a BDM status
message (BDM status field equal to 0b1) to the development tool indicating that the RCPU has entered
debug mode and is now expecting instructions from the READI signals.
The development tool then uses the DSDI Data Message to send in the serial transmission data to READI.
Data is transmitted to the tool using the DSDO data message.
This process continues until the RCPU exits debug mode and READI sends the BDM status message
(BDM status field equal to 0b0) indicating debug mode exit.
NOTE
Only after the DSDO data message is sent out should another DSDI data
message be sent in.
Synchronous self-clocked mode is selected by READI for RCPU development access. In this mode, the
internal transmission between READI and the USIU is performed at system frequency.
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When the RCPU is in debug mode, program trace is not allowed. If program trace is enabled, a program
trace synchronization message is generated when debug mode exits.
When the RCPU is in debug mode, data trace and R/W access are allowed.
The flow chart in Figure 24-83 shows RCPU development access configuration via READI. The modes
of RCPU development access via READI are described below. Allowed modes are also summarized in
Table 24-8 of Section 24.14.2.4, “RCPU Development Access Flow Diagram.”
24.14.2.1 Enabling RCPU Development Access Via READI Signals
Reset sequencing is done by the tool to initialize the READI signals and registers by asserting RSTI (the
device sends out the device ID message after the RSTI negation). System reset is held by the tool until the
READI module is reset and initialized with desired RCPU development access setting.
NOTE
The READI module will ignore any incoming DSDI data messages when
the module is not configured for RCPU development access.
24.14.2.2 Entering Background Debug Mode (BDM) Via READI Signals
There are three ways to enter debug mode (provided debug mode has been enabled):
1. Enter debug mode (halted state) out-of-system reset through READI module configuration. This is
displayed in Figure 24-84.
2. Enter debug mode by downloading breakpoint instructions through RCPU development access
when in non-debug (running) mode.
3. Enter debug mode if an exception or interrupt occurs.
When entering debug mode following an exception/breakpoint, the RCPU signals VFLS[0:1] are equal to
0b11. This causes READI to send a BDM status message to the tool indicating that the RCPU has entered
debug mode and is now expecting instructions from the READI signals.
Debug mode enabling through READI and entering debug mode out of system reset is done by setting the
following bits in the DC register (DME=0b1, DOR=0b1) during system reset. Debug mode entry causes
RCPU to halt.
24.14.2.3 Non-Debug Mode Access of RCPU Development Access
The RCPU development access can be also be used while the RCPU is not halted (in debug mode). This
feature is used to send in breakpoints or synchronization events to the RCPU. Please refer to Chapter 23,
“Development Support” for further details.
Non-debug mode access of RCPU development can be achieved by configuring the READI module to take
control of RCPU development access during module configuration of the DC register (DME=0b0,
DOR=0bx).
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24.14.2.4 RCPU Development Access Flow Diagram
Figure 24-83 has flow diagram describing how the RCPU development access can be achieved via READI
signals.
*A* (@ subsequent READI reset)
Tool Asserts and Negates RSTI
Device sends DID message
BDM CONFIGURATION OUT-OF-RESET
*B* (@ subsequent RCPU reset)
Tool sends Download Request Message and configures
READI module (assign DPA, DME & DOR, etc.)
Tools Negates HRESET 16 clocks after receiving Device Ready
(DPA, DME, DOR, etc. bits locked)
(Debug Mode not enabled) No
(No Debug out-of-reset) No
DSDI=1
(synch.self-clk mode)
GENERIC RCPU DEVELOPMENT PROTOCOL
Tool Asserts HRESET
DME=1
?
Yes (Debug Mode enabled)
DOR=1
?
DSDI=1 (sync. self-clk mode)
DSCK=0 within 8 clocks of SRESET
negation to NOT enter debug mode
BDM
Entry?
Tool sends DSDI Message
Yes (Debug out-of-reset)
DSDI=1 (sync. self-clk mode)
DSCK=1 until 16 clocks after SRESET
negation to enter debug mode
Yes
No
Device sends Debug Mode Status
Message
“BDM entry” (status bit = 1)
Device sends DSDO Message
*(exit loop via READI reset (*A*)
or system reset (*B*))
*(exit loop via
READI reset
(*A*) or via
system reset
(*B*))
Tool sends DSDI Message
Device sends DSDO Message
BDM
Exit?
Yes
No
Device sends Debug Mode
Status Message
“BDM exit” (status bit = 0)
DEBUG MODE NOT ENALBED
(DME=0)
DEBUG MODE ENABLED
(DME=1)
Figure 24-83. RCPU Development Access Flow Diagram
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24.14.3 Throughput
The tool can send a DSDI data message into device upon the receipt of a DSDO data message as soon as
the tool decodes the first two status bits of the DSDO data message just received and confirms valid data
from the RCPU.
An example throughput analysis is performed with the following assumptions:
• READI configuration of RCPU development access and debug mode is already entered through
READI
• The module is configured for reduced port mode
• MCKI running at 28 MHz
• MCKO running at 56 MHz
• 56-MHz internal operation
• READI auxiliary input and output signals are free (not in middle of transmission)
• No delay from tool in responding — tool keeps up with READI port
• Tool reads the complete DSDO data message before shifting in DSDI data message
• 10 clocks estimated to format and encode/decode DSDI data and DSDO data messages within
READI
The DSDI data message is 41 bits (six bits of TCODE and 35 bits of DSDI data.). It takes 41 clocks (41
bits / 1 MDI signals) to shift in the DSDI data message. It is estimated that READI will take approximately
10 clocks to decode the DSDI data message. After the message has been decoded, READI will take 35
clocks to serially shift in the 35 bits of DSDI data to the RCPU development port. Hence, it takes a total
of 86 clocks (41 + 10 + 35) to decode and shift in DSDI data from the tool to the RCPU development port.
At 28 MHz, it translates to 3079 ns (35.8 x 81) to decode and shift in DSDI data to RCPU development port
As DSDI bits are shifted into the RCPU development register, DSDO bits are shifted out from the same
RCPU development register (DPDR) and these are captured by READI.
It is estimated that READI will take approximately 10 clocks to encode the DSDO data. The DSDO
message is 41 bits (6 bits of TCODE and 35 bits of DSDO data). It will take 21 clocks (41 bits / 2 MDO
signals) for READI to transmit this message. Hence, it will take a total of 31 clocks (10 + 21) to encode
the DSDO data message and shift out the DSDO data message to the tool.
At 56 MHz, it will take 552 ns (17.8 x 31) to encode and shift out DSDO data to the tool.
Thus, it will take 3631 ns (3079 + 552) for one complete DSDI data and DSDO data messaging cycle.
24.14.4 Development Access Timing Diagrams
Figure 24-84 shows the timing diagram of RCPU development access and entering debug mode
out-of-system reset through READI.
MPC561/MPC563 Reference Manual, Rev. 1.2
24-82
Freescale Semiconductor
READI Module
HRESET
(Tool drives)
SRESET is negated by the MCU
after some internal system clocks delay.
Tool negates
3
HRESET at least 16
system clocks after
receiving device
ready msg
SRESET
(USIU drives)
RSTI
(Tool drives)
4 BDM is set based on READI
module configuration
and BDM Entry msg is
sent out when VFLS[0:1]=11.
Device sends
out Dev ID
1
msg after
negation of RSTI
MSEI
DC reg
Config Msg
(BDM)
TC = 18
MDI
DSDI
Message
TC = 56
2 DC reg. config
msg (BDM)
sent after DevID
msg received
by tool
5 DSDI msg
sent after.
BDM msg
DSDI
Message
TC = 56
msg can be
7 DSDI
sent to device after
TCODE and two
status bits in the
DSDO msg indicate
it is ready.
MSEO
MDO
BDM
ENTRY
Message
TC = 58
Device
Ready
Message
TC = 16
Dev ID
Message
TC = 1
6
DSDO msg
sent out
DSDO
Message
TC = 57
DSDO
Message
TC = 57
BDM
EXIT
Message
TC = 58
Figure 24-84. RCPU Development Access Timing Diagram — Debug Mode Entry Out-of-Reset
Figure 24-85 shows the transmission sequence of DSDI/DSDO data messages.
1
TCODE (6 bits)
MSB
2
HEADER (3 bits)
LSB MSB
3
DATA (7 or 32 bits)
LSB MSB
LSB
Figure 24-85. Transmission Sequence of DSDx Data Messages
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
24-83
READI Module
DSDI message fields of the development port access message are explained in Table 24-33.
.
Table 24-33. Development Port Access: DSDI Field
Header
Data
Instruction / Data (32 Bits)
Start
Mode
Function
Control
Bits 0:6
Bits 7:31
1
0
0
CPU Instruction
Transfer Instruction
to CPU
1
0
1
CPU Data
Transfer Data
to CPU
1
1
0
Trap enable
Does not exist
Transfer data to
Trap Enable
Control Register
1
1
1
0011111
Does not exist
Negate breakpoint requests
to the CPU.
1
1
1
0
Does not exist
NOP
DSDO message fields of the development port access message are explained in Table 24-34.
Table 24-34. Development Port Access: DSDO Field
Header
Ready
1
2
Data
Status [0:1]
(0)
0
0
(0)
0
1
(0)
1
0
(0)
1
1
Bit 0
Bit 1
Data
Freeze
status1
Download
Procedure
in
progress2
Function
Bits 2:31 or 2:6 —
(Depending on Input Mode)
Valid Data from CPU
1’s
Sequencing Error
1’s
CPU Interrupt
1’s
Null
The “Freeze” status is set to (1) when the CPU is in debug mode and to (0) otherwise.
The “Download Procedure in progress” status is asserted (0) when Debug port in the Download procedure and is
negated (1) otherwise.
MPC561/MPC563 Reference Manual, Rev. 1.2
24-84
Freescale Semiconductor
READI Module
MCKO
MSEO
MDO[7:0]
00001000
00000000
00000001
TCODE = 8
Error Code = 0b00100 (Invalid Message)
Don’t care data
(idle clock)
Figure 24-86. Error Message (Invalid Message)
MCKI
MSEI
MDI[1:0]
00
10
11
11
11
10
TCODE = 56 (0x38)
Header = (Start=1, Mode=1, Control=1)
Data = 0b1011111 (Assert Non Maskable Breakpoint)
11
11
00
Don’t care data
(idle clock)
Figure 24-87. DSDI Data Message (Assert Non-Maskable Breakpoint)
MCKI
MSEI
MDI[1:0]
00 10 11 01 00 01 10 01 00 00 00 00 00 00 00 00 00 11 00 01 00 00
TCODE = 56 (0x38)
Header = (Start=1, Mode=0, Control=0)
Data = 0x4C000064 (rfi Instruction)
Don’t care data
(idle clock)
Figure 24-88. DSDI Data Message (CPU Instruction — rfi)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
24-85
READI Module
MCKO
MSEO
00111001 11111110
MDO[7:0]
00000001 10101010 01011110
00000001 00000000
TCODE = 57 (0x39)
Header = (Start=0, Mode=0, Control=0)
Data = FF00AAF5 (CPU Data Out)
Don’t care data
(idle clock)
Figure 24-89. DSDO Data Message (CPU Data Out)
24.15 Power Management
This section details the power management features of the READI module.
The READI module is a development interface, and is not expected to function under normal
(non-development) conditions. Therefore power management is required to reduce and minimize power
consumption during normal operation of the part.
24.15.1 Functional Description
The following are the candidates for power management:
Table 24-35. Power Management Mechanism Overview
Feature
Power Saving Mechanism
If EVTI is negated at negation of RSTI, the READI module will be
disabled. No trace output will be provided, and output auxiliary port
will be three-stated.
Disabled Mode
Sleep, Deep-Sleep and
Low Power-Down Mode
All outputs will be held static.
Output auxiliary signals will be three-stated.
READI Reset (RSTI)
24.15.2 Low Power Modes
When the MCU is in sleep, deep-sleep, or low power-down mode, all internal clocks on the MCU are shut
down, including the MCKO. The MSEO signal will be held negated.
Low power mode entry for the MCU will be held off until the READI module has transmitted all existing
messages (in the queues and transmit buffers). During this time, input messages from the development tool
are ignored.
Upon restoration of clocks in normal mode, program and data traces will be synchronized, if enabled.
MPC561/MPC563 Reference Manual, Rev. 1.2
24-86
Freescale Semiconductor
Chapter 25
IEEE 1149.1-Compliant Interface (JTAG)
The chip design includes user-accessible test logic that is compatible with the IEEE 1149.1-1994 Standard
Test Access Port and Boundary Scan Architecture. The implementation supports circuit-board test
strategies based on this standard. An overview of the pins requirement on JTAG is shown in Figure 25-1.
bsc
...........
bsc
TDI
MPC561/MPC563
.......
TRST
bsc
...........
bsc
...........
...........
TAP
TMS
JCOMP / RSTI
TDO
bsc
TCK
...........
...........
......
bsc
bsc
Figure 25-1. Pin Requirement on JTAG
25.1
IEEE 1149.1 Test Access Port
The MPC561/MPC563 provides a dedicated user-accessible test access port (TAP) that is compatible with
the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture in all but two areas listed
below. Problems associated with testing high density circuit boards have led to development of this
proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test
Action Group (JTAG). The MPC561/MPC563 implementation supports circuit-board test strategies based
on this standard.
IEEE1149.1 Compatibility Exceptions:
• The MPC561/MPC563 enters JTAG mode by going through a standard device reset sequence with
the JCOMP signal asserted high during PORESET negation. Once JTAG has been entered, the
MPC561/MPC563 remains in JTAG mode until another reset sequence is applied to exit JTAG
mode, or the device is powered down.
• The JTAG output port, TDO, is configured with a weak pull-up until reset negates or the driver is
disabled.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-1
IEEE 1149.1-Compliant Interface (JTAG)
The TAP consists of five dedicated signal pins, a 16-state TAP controller, and two test data registers. A
boundary scan register links all device signal pins into a single shift register. The test logic implemented
utilizes static logic design. The MPC561/MPC563 implementation provides the capability to:
1. Perform boundary scan operations to test circuit-board electrical continuity.
2. Bypass the MPC561/MPC563 for a given circuit-board test by effectively reducing the boundary
scan register to a single cell.
3. Sample the MPC561/MPC563 system pins during operation and transparently shift out the result
in the boundary scan register.
4. Disable the output drive to pins during circuit-board testing.
NOTE
Certain precautions must be observed to ensure that the IEEE 1149-like test
logic does not interfere with nontest operation. JCOMP must be low prior to
PORESET assertion after low power mode exits, otherwise an unknown
state will occur.
25.1.1
Overview
An overview of the MPC561/MPC563 scan chain implementation is shown in Figure 25-2. The
MPC561/MPC563 implementation includes a TAP controller, a 4-bit instruction register, and two test
registers (a one-bit bypass register and a 427-bit (MPC563) or 423-bit (MPC561) boundary scan register).
This implementation includes a dedicated TAP consisting of the following signals:
• TCK — a test clock input to synchronize the test logic. (with an internal pull-down resistor)
• TMS — a test mode select input (with an internal pullup resistor) that is sampled on the rising edge
of TCK to sequence the TAP controller’s state machine.
• TDI — a test data input (with an internal pullup resistor) that is sampled on the rising edge of TCK.
• TDO — a three-state test data output that is actively driven in the shift-IR and shift-DR controller
states. TDO changes on the falling edge of TCK. (This pin also has a weak pull-up that is active
when output drivers are disabled, except during a HI-Z instruction).
• TRST — an asynchronous reset with an internal pull-up resistor that provides initialization of the
TAP controller and other logic required by the standard. This input is multiplexed with the
PORESET signal.
• JCOMP — JTAG Compliancy – This signal provides JTAG IEEE1149.1 compatibility and selects
between normal operation (low) and JTAG test mode (high).
NOTE
JTAG mode does not provide access to the internal MPC561/MPC563
circuitry. It allows access only to the input or output pad (periphery)
circuitry.
MPC561/MPC563 Reference Manual, Rev. 1.2
25-2
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Boundary scan register
M
U
X
TDI
Bypass
Instruction apply & decode register
3
2
1
0
4-bit Instruction register
M
U
X
TRST
JCOMP / RSTI
TMS
TCK
PORESET / TRST
TDO
TAP Controller
Figure 25-2. Test Logic Block Diagram
25.1.2
Entering JTAG Mode
To enable JTAG on reset for board test JCOMP/RSTI must be high on PORESET rising edge as shown in
Figure 25-3.
NOTE
JTAG puts all output pins in fast slew rate mode. Enough current cannot be
supplied to allow all the pins to be switched simultaneously, so this should
be avoided.
PORESET
JCOMP/RSTI
Configuration
JTAG
JTAG ON
JTAG off/READI Config
T
Figure 25-3. JTAG Mode Selection
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-3
IEEE 1149.1-Compliant Interface (JTAG)
25.1.2.1
TAP Controller
The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is
a synchronous state machine that controls the operation of the JTAG logic. The state machine is shown in
Figure 25-4. The value shown adjacent to each arc represents the value of the TMS signal sampled on the
rising edge of the TCK signal.
TEST LOGIC
RESET
1
0
RUN-TEST/IDLE
1
SELECT-DR_SCAN
0
1
SELECT-IR_SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
1
SHIFT-IR
0
1
0
EXIT1-DR
EXIT2-DR
PAUSE-IR
0
1
0
1
UPDATE-DR
0
0
EXIT2-IR
1
1
1
0
PAUSE-DR
0
0
EXIT1-IR
0
1
1
UPDATE-IR
1
0
Figure 25-4. TAP Controller State Machine
25.1.2.2
Boundary Scan Register
The MPC561/MPC563 scan chain implementation has a 427-bit (MPC563) or 423-bit (MPC561)
boundary scan register. This register contains bits for most device signals, clock pins and associated
control signals. The XTAL, EXTAL and XFC pins are associated with analog signals and are not included
in the boundary scan register. The PORESET, HRESET, and SRESET pins are also excluded from the
boundary scan register.
MPC561/MPC563 Reference Manual, Rev. 1.2
25-4
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
The 520-bit boundary scan register can be connected between TDI and TDO by selecting the EXTEST or
SAMPLE/PRELOAD instructions. This register is used to capturing signal pin data on the input pins,
forcing fixed values on the output signal pins, and selecting the direction and drive characteristics (a logic
value or high impedance) of the bidirectional and three-state signal pins.
The key to using the boundary scan register is knowing the boundary scan bit order and the pins that are
associated with them. Table 25-1 shows the bit order starting from the TDO output and going to the TDI
input.
Table 25-1 displays boundary scan bit definitions for the MPC561 and Table 25-2 displays boundary scan
bit definitions for the MPC563.
Table 25-1. MPC561 Boundary Scan Bit Definition
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
0
BC_2
*
controlr
0
1
BC_7
B_CNRX0
bidir
0
2
BC_2
*
internal
1
3
BC_2
B_CNTX0
output2
1
4
BC_2
*
controlr
0
5
BC_7
B_TPUCH0
bidir
0
6
BC_2
*
controlr
0
7
BC_7
B_TPUCH1
bidir
0
8
BC_2
*
controlr
0
9
BC_7
B_TPUCH2
bidir
0
10
BC_2
*
controlr
0
11
BC_7
B_TPUCH3
bidir
0
12
BC_2
*
controlr
0
13
BC_7
B_TPUCH4
bidir
0
14
BC_2
*
controlr
0
15
BC_7
B_TPUCH5
bidir
0
16
BC_2
*
controlr
0
17
BC_7
B_TPUCH6
bidir
0
18
BC_2
*
controlr
0
19
BC_7
B_TPUCH7
bidir
0
20
BC_2
*
controlr
0
21
BC_7
B_TPUCH8
bidir
0
22
BC_2
*
controlr
0
23
BC_7
B_TPUCH9
bidir
0
24
BC_2
*
controlr
0
25
BC_7
B_TPUCH10
bidir
0
0
0
Z
Pin
Function
Pad
Type
IO
5vfa
O
5vfa
4
0
Z
IO
5vsa
6
0
Z
IO
5vsa
8
0
Z
IO
5vsa
10
0
Z
IO
5vsa
12
0
Z
IO
5vsa
14
0
Z
IO
5vsa
16
0
Z
IO
5vsa
18
0
Z
IO
5vsa
20
0
Z
IO
5vsa
22
0
Z
IO
5vsa
24
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-5
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
26
BC_2
*
controlr
0
27
BC_7
B_TPUCH11
bidir
0
28
BC_2
*
controlr
0
29
BC_7
B_TPUCH12
bidir
0
30
BC_2
*
controlr
0
31
BC_7
B_TPUCH13
bidir
0
32
BC_2
*
controlr
0
33
BC_7
B_TPUCH14
bidir
0
34
BC_2
*
controlr
0
35
BC_7
B_TPUCH15
bidir
0
36
BC_2
*
controlr
0
37
BC_7
B_T2CLK_PCS4
bidir
0
38
BC_2
*
controlr
0
39
BC_7
A_T2CLK_PCS5
bidir
0
40
BC_2
*
controlr
0
41
BC_7
A_TPUCH0
bidir
0
42
BC_2
*
controlr
0
43
BC_7
A_TPUCH1
bidir
0
44
BC_2
*
controlr
0
45
BC_7
A_TPUCH2
bidir
0
46
BC_2
*
controlr
0
47
BC_7
A_TPUCH3
bidir
0
48
BC_2
*
controlr
0
49
BC_7
A_TPUCH4
bidir
0
50
BC_2
*
controlr
0
51
BC_7
A_TPUCH5
bidir
0
52
BC_2
*
controlr
0
53
BC_7
A_TPUCH6
bidir
0
54
BC_2
*
controlr
0
55
BC_7
A_TPUCH7
bidir
0
56
BC_2
*
controlr
0
57
BC_7
A_TPUCH8
bidir
0
58
BC_2
*
controlr
0
59
BC_7
A_TPUCH9
bidir
0
60
BC_2
*
controlr
0
61
BC_7
A_TPUCH10
bidir
0
Pin
Function
Pad
Type
26
0
Z
IO
5vsa
28
0
Z
IO
5vsa
30
0
Z
IO
5vsa
32
0
Z
IO
5vsa
34
0
Z
IO
5vsa
36
0
Z
IO
5vfa
38
0
Z
IO
5vfa
40
0
Z
IO
5vsa
42
0
Z
IO
5vsa
44
0
Z
IO
5vsa
46
0
Z
IO
5vsa
48
0
Z
IO
5vsa
50
0
Z
IO
5vsa
52
0
Z
IO
5vsa
54
0
Z
IO
5vsa
56
0
Z
IO
5vsa
58
0
Z
IO
5vsa
60
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
25-6
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
62
BC_2
*
controlr
0
63
BC_7
A_TPUCH11
bidir
0
64
BC_2
*
controlr
0
65
BC_7
A_TPUCH12
bidir
0
66
BC_2
*
controlr
0
67
BC_7
A_TPUCH13
bidir
0
68
BC_2
*
controlr
0
69
BC_7
A_TPUCH14
bidir
0
70
BC_2
*
controlr
0
71
BC_7
A_TPUCH15
bidir
0
72
BC_2
*
controlr
0
73
BC_7
A_AN0_ANW_PQB0
bidir
0
74
BC_2
*
controlr
0
75
BC_7
A_AN1_ANX_PQB1
bidir
0
76
BC_2
*
controlr
0
77
BC_7
A_AN2_ANY_PQB2
bidir
0
78
BC_2
*
controlr
0
79
BC_7
A_AN3_ANZ_PQB3
bidir
0
80
BC_2
*
controlr
0
81
BC_7
A_AN48_PQB4
bidir
0
82
BC_2
*
controlr
0
83
BC_7
A_AN49_PQB5
bidir
0
84
BC_2
*
controlr
0
85
BC_7
A_AN50_PQB6
bidir
0
86
BC_2
*
controlr
0
87
BC_7
A_AN51_PQB7
bidir
0
88
BC_2
*
controlr
0
89
BC_7
A_AN52_MA0_PQA0
bidir
0
90
BC_2
*
controlr
0
91
BC_7
A_AN53_MA1_PQA1
bidir
0
92
BC_2
*
controlr
0
93
BC_7
A_AN54_MA2_PQA2
bidir
0
94
BC_2
*
controlr
0
95
BC_7
A_AN55_PQA3
bidir
0
96
BC_2
*
controlr
0
97
BC_7
A_AN56_PQA4
bidir
0
Pin
Function
Pad
Type
62
0
Z
IO
5vsa
64
0
Z
IO
5vsa
66
0
Z
IO
5vsa
68
0
Z
IO
5vsa
70
0
Z
IO
5vsa
72
0
Z
IO
5vsa
74
0
Z
IO
5vsa
76
0
Z
IO
5vsa
78
0
Z
IO
5vsa
80
0
Z
IO
5vsa
82
0
Z
IO
5vsa
84
0
Z
IO
5vsa
86
0
Z
IO
5vsa
88
0
Z
IO
5vsa
90
0
Z
IO
5vsa
92
0
Z
IO
5vsa
94
0
Z
IO
5vsa
96
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-7
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
98
BC_2
*
controlr
0
99
BC_7
A_AN57_PQA5
bidir
0
100
BC_2
*
controlr
0
101
BC_7
A_AN58_PQA6
bidir
0
102
BC_2
*
controlr
0
103
BC_7
A_AN59_PQA7
bidir
0
104
BC_2
*
controlr
0
105
BC_7
B_AN0_ANW_PQB0
bidir
0
106
BC_2
*
controlr
0
107
BC_7
B_AN1_ANX_PQB1
bidir
0
108
BC_2
*
controlr
0
109
BC_7
B_AN2_ANY_PQB2
bidir
0
110
BC_2
*
controlr
0
111
BC_7
B_AN3_ANZ_PQB3
bidir
0
112
BC_2
*
controlr
0
113
BC_7
B_AN48_PQB4
bidir
0
114
BC_2
*
controlr
0
115
BC_7
B_AN49_PQB5
bidir
0
116
BC_2
*
controlr
0
117
BC_7
B_AN50_PQB6
bidir
0
118
BC_2
*
controlr
0
119
BC_7
B_AN51_PQB7
bidir
0
120
BC_2
*
controlr
0
121
BC_7
B_AN52_MA0_PQA0
bidir
0
122
BC_2
*
controlr
0
123
BC_7
B_AN53_MA1_PQA1
bidir
0
124
BC_2
*
controlr
0
125
BC_7
B_AN54_MA2_PQA2
bidir
0
126
BC_2
*
controlr
0
127
BC_7
B_AN55_PQA3
bidir
0
128
BC_2
*
controlr
0
129
BC_7
B_AN56_PQA4
bidir
0
130
BC_2
*
controlr
0
131
BC_7
B_AN57_PQA5
bidir
0
132
BC_2
*
controlr
0
133
BC_7
B_AN58_PQA6
bidir
0
Pin
Function
Pad
Type
98
0
Z
IO
5vsa
100
0
Z
IO
5vsa
102
0
Z
IO
5vsa
104
0
Z
IO
5vsa
106
0
Z
IO
5vsa
108
0
Z
IO
5vsa
110
0
Z
IO
5vsa
112
0
Z
IO
5vsa
114
0
Z
IO
5vsa
116
0
Z
IO
5vsa
118
0
Z
IO
5vsa
120
0
Z
IO
5vsa
122
0
Z
IO
5vsa
124
0
Z
IO
5vsa
126
0
Z
IO
5vsa
128
0
Z
IO
5vsa
130
0
Z
IO
5vsa
132
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
25-8
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
134
BC_2
*
controlr
0
135
BC_7
B_AN59_PQA7
bidir
0
136
BC_2
*
controlr
0
137
BC_7
ETRIG2_PCS7
bidir
0
138
BC_2
*
controlr
0
139
BC_7
ETRIG1_PCS6
bidir
0
140
BC_2
*
controlr
0
141
BC_7
MDA11
bidir
0
142
BC_2
*
controlr
0
143
BC_7
MDA12
bidir
0
144
BC_2
*
controlr
0
145
BC_7
MDA13
bidir
0
146
BC_2
*
controlr
0
147
BC_7
MDA14
bidir
0
148
BC_2
*
controlr
0
149
BC_7
MDA15
bidir
0
150
BC_2
*
controlr
0
151
BC_7
MDA27
bidir
0
152
BC_2
*
controlr
0
153
BC_7
MDA28
bidir
0
154
BC_2
*
controlr
0
155
BC_7
MDA29
bidir
0
156
BC_2
*
controlr
0
157
BC_7
MDA30
bidir
0
158
BC_2
*
controlr
0
159
BC_7
MDA31
bidir
0
160
BC_2
*
controlr
0
161
BC_7
MPWM0_MDI1
bidir
0
162
BC_2
*
controlr
0
163
BC_7
MPWM1_MDO2
bidir
0
164
BC_2
*
controlr
0
165
BC_7
MPWM2_PPM_TX1
bidir
0
166
BC_2
*
controlr
0
167
BC_7
MPWM3_PPM_RX1
bidir
0
168
BC_2
*
controlr
0
169
BC_7
MPWM16
bidir
0
Pin
Function
Pad
Type
134
0
Z
IO
5vsa
136
0
Z
IO
5vfa
138
0
Z
IO
5vfa
140
0
Z
IO
5vsa
142
0
Z
IO
5vsa
144
0
Z
IO
5vsa
146
0
Z
IO
5vsa
148
0
Z
IO
5vsa
150
0
Z
IO
5vsa
152
0
Z
IO
5vsa
154
0
Z
IO
5vsa
156
0
Z
IO
5vsa
158
0
Z
IO
5vsa
160
0
Z
IO
26v5vs
162
0
Z
IO
26v5vs
164
0
Z
IO
26v5vs
166
0
Z
IO
26v5vs
168
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-9
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
170
BC_2
*
controlr
0
171
BC_7
MPWM17_MDO3
bidir
0
172
BC_2
*
controlr
0
173
BC_7
MPWM18_MDO6
bidir
0
174
BC_2
*
controlr
0
175
BC_7
MPWM19_MDO7
bidir
0
176
BC_2
*
controlr
0
177
BC_7
MPIO32B5_MDO5
bidir
0
178
BC_2
*
controlr
0
179
BC_7
MPIO32B6_MPWM4_MDO6
bidir
0
180
BC_2
*
controlr
0
181
BC_7
MPIO32B7_MPWM5
bidir
0
182
BC_2
*
controlr
0
183
BC_7
MPIO32B8_MPWM20
bidir
0
184
BC_2
*
controlr
0
185
BC_7
MPIO32B9_MPWM21
bidir
0
186
BC_2
*
controlr
0
187
BC_7
MPIO32B10_PPM_TSYNC
bidir
0
188
BC_2
*
controlr
0
189
BC_7
MPIO32B11_C_CNRX0
bidir
0
190
BC_2
*
controlr
0
191
BC_7
MPIO32B12_C_CNTX0
bidir
0
192
BC_2
*
controlr
0
193
BC_7
MPIO32B13_PPM_TCLK
bidir
0
194
BC_2
*
controlr
0
195
BC_7
MPIO32B14_PPM_RX0
bidir
0
196
BC_2
*
controlr
0
197
BC_7
MPIO32B15_PPM_TX0
bidir
0
198
BC_2
*
controlr
0
199
BC_7
VF0_MPIO32B0_MDO1
bidir
0
200
BC_2
*
controlr
0
201
BC_7
VF1_MPIO32B1_MCKO
bidir
0
202
BC_2
*
controlr
0
203
BC_7
VF2_MPIO32B2_MSEI_B
bidir
0
204
BC_2
*
controlr
0
Pin
Function
Pad
Type
170
0
Z
IO
26v5vs
172
0
Z
IO
26v5vs
174
0
Z
IO
26v5vs
176
0
Z
IO
26v5vs
178
0
Z
IO
26v5vs
180
0
Z
IO
5vsa
182
0
Z
IO
5vsa
184
0
Z
IO
5vsa
186
0
Z
IO
26v5vs
188
0
Z
IO
5vfa
190
0
Z
IO
5vfa
192
0
Z
IO
26v5vs
194
0
Z
IO
26v5vs
196
0
Z
IO
26v5vs
198
0
Z
IO
26v5vs
200
0
Z
IO
26v5vs
202
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
25-10
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Cell
Type
205
BC_7
VFLS0_MPIO32B3_MSEO_
B
bidir
0
206
BC_2
*
controlr
0
207
BC_7
VFLS1_MPIO32B4
bidir
0
208
BC_2
*
internal
1
209
BC_2
A_CNTX0
output2
1
210
BC_2
*
internal
0
211
BC_4
A_CNRX0
input
X
212
BC_2
*
controlr
0
213
BC_7
PCS0_SS_B_QGPIO0
bidir
0
214
BC_2
*
controlr
0
215
BC_7
PCS1_QGPIO1
bidir
0
216
BC_2
*
controlr
0
217
BC_7
PCS2_QGPIO2
bidir
0
218
BC_2
*
controlr
0
219
BC_7
PCS3_QGPIO3
bidir
0
220
BC_2
*
controlr
0
221
BC_7
MISO_QGPIO4
bidir
0
222
BC_2
*
controlr
0
223
BC_7
MOSI_QGPIO5
bidir
0
224
BC_2
*
controlr
0
225
BC_7
SCK_QGPIO6
bidir
0
226
BC_2
*
internal
0
227
BC_4
ECK
input
X
228
BC_2
*
internal
1
229
BC_2
TXD1_QGPO1
output2
1
230
BC_2
*
internal
1
231
BC_2
TXD2_QGPO2_C_CNTX0
output2
232
BC_4
RXD1_QGPI1
233
BC_4
234
Pin/Port Name
BSDL
Function
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Pin
Function
Pad
Type
204
0
Z
IO
26v5vs
206
0
Z
IO
26v5vs
I
5vfa
O
5vfa
212
0
Z
IO
5vfa
214
0
Z
IO
5vfa
216
0
Z
IO
5vfa
218
0
Z
IO
5vfa
220
0
Z
IO
5vh
222
0
Z
IO
5vh
224
0
Z
IO
5vh
I
5vfa
O
5vfa
1
O
5vfa
input
X
I
5vido
RXD2_QGPI2_C_CNRX0
input
X
I
5vido
BC_2
*
internal
1
235
BC_2
ENGCLK_BUCLK
output2
1
O
buff
236
BC_2
*
internal
1
237
BC_2
CLKOUT
output2
1
O
26vf
238
BC_4
EXTCLK
input
X
I
extclk
239
BC_2
*
controlr
0
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-11
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
240
BC_7
SRESET_B
bidir
0
241
BC_2
*
controlr
0
242
BC_7
HRESET_B
bidir
0
243
BC_2
*
controlr
0
244
BC_7
RSTCONF_B_TEXP
bidir
0
245
BC_2
*
controlr
0
246
BC_7
IRQ7_B_MODCK3
bidir
0
247
BC_2
*
controlr
0
248
BC_7
IRQ6_B_MODCK2
bidir
0
249
BC_2
*
controlr
0
250
BC_7
IRQ5_B_SGPIOC5_MODCK
1
bidir
0
251
BC_2
*
controlr
0
252
BC_7
DATA_SGPIOD16
bidir
0
253
BC_2
*
controlr
0
254
BC_7
DATA_SGPIOD17
bidir
0
255
BC_2
*
controlr
0
256
BC_7
DATA_SGPIOD18
bidir
0
257
BC_2
*
controlr
0
258
BC_7
DATA_SGPIOD14
bidir
0
259
BC_2
*
controlr
0
260
BC_7
DATA_SGPIOD15
bidir
0
261
BC_2
*
controlr
0
262
BC_7
DATA_SGPIOD19
bidir
0
263
BC_2
*
controlr
0
264
BC_7
DATA_SGPIOD20
bidir
0
265
BC_2
*
controlr
0
266
BC_7
DATA_SGPIOD12
bidir
0
267
BC_2
*
controlr
0
268
BC_7
DATA_SGPIOD13
bidir
0
269
BC_2
*
controlr
0
270
BC_7
DATA_SGPIOD21
bidir
0
271
BC_2
*
controlr
0
272
BC_7
DATA_SGPIOD10
bidir
0
273
BC_2
*
controlr
0
274
BC_7
DATA_SGPIOD11
bidir
0
Pin
Function
Pad
Type
239
0
Z
IO
26vc
241
0
Z
IO
26vc
243
0
Z
IO
26v
245
0
Z
IO
26v
247
0
Z
IO
26v
249
0
Z
IO
26v
251
0
Z
IO
26v5vs
253
0
Z
IO
26v5vs
255
0
Z
IO
26v5vs
257
0
Z
IO
26v5vs
259
0
Z
IO
26v5vs
261
0
Z
IO
26v5vs
263
0
Z
IO
26v5vs
265
0
Z
IO
26v5vs
267
0
Z
IO
26v5vs
269
0
Z
IO
26v5vs
271
0
Z
IO
26v5vs
273
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
25-12
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
275
BC_2
*
controlr
0
276
BC_7
DATA_SGPIOD22
bidir
0
277
BC_2
*
controlr
0
278
BC_7
DATA_SGPIOD23
bidir
0
279
BC_2
*
controlr
0
280
BC_7
DATA_SGPIOD8
bidir
0
281
BC_2
*
controlr
0
282
BC_7
DATA_SGPIOD9
bidir
0
283
BC_2
*
controlr
0
284
BC_7
DATA_SGPIOD24
bidir
0
285
BC_2
*
controlr
0
286
BC_7
DATA_SGPIOD25
bidir
0
287
BC_2
*
controlr
0
288
BC_7
DATA_SGPIOD6
bidir
0
289
BC_2
*
controlr
0
290
BC_7
DATA_SGPIOD7
bidir
0
291
BC_2
*
controlr
0
292
BC_7
DATA_SGPIOD26
bidir
0
293
BC_2
*
controlr
0
294
BC_7
DATA_SGPIOD27
bidir
0
295
BC_2
*
controlr
0
296
BC_7
DATA_SGPIOD4
bidir
0
297
BC_2
*
controlr
0
298
BC_7
DATA_SGPIOD5
bidir
0
299
BC_2
*
controlr
0
300
BC_7
DATA_SGPIOD28
bidir
0
301
BC_2
*
controlr
0
302
BC_7
DATA_SGPIOD29
bidir
0
303
BC_2
*
controlr
0
304
BC_7
DATA_SGPIOD2
bidir
0
305
BC_2
*
controlr
0
306
BC_7
DATA_SGPIOD3
bidir
0
307
BC_2
*
controlr
0
308
BC_7
DATA_SGPIOD30
bidir
0
309
BC_2
*
controlr
0
310
BC_7
DATA_SGPIOD0
bidir
0
Pin
Function
Pad
Type
275
0
Z
IO
26v5vs
277
0
Z
IO
26v5vs
279
0
Z
IO
26v5vs
281
0
Z
IO
26v5vs
283
0
Z
IO
26v5vs
285
0
Z
IO
26v5vs
287
0
Z
IO
26v5vs
289
0
Z
IO
26v5vs
291
0
Z
IO
26v5vs
293
0
Z
IO
26v5vs
295
0
Z
IO
26v5vs
297
0
Z
IO
26v5vs
299
0
Z
IO
26v5vs
301
0
Z
IO
26v5vs
303
0
Z
IO
26v5vs
305
0
Z
IO
26v5vs
307
0
Z
IO
26v5vs
309
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-13
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
311
BC_2
*
controlr
0
312
BC_7
DATA_SGPIOD1
bidir
0
313
BC_2
*
controlr
0
314
BC_7
DATA_SGPIOD31
bidir
0
315
BC_2
*
controlr
0
316
BC_7
ADDR_SGPIOA29
bidir
0
317
BC_2
*
controlr
0
318
BC_7
ADDR_SGPIOA25
bidir
0
319
BC_2
*
controlr
0
320
BC_7
ADDR_SGPIOA26
bidir
0
321
BC_2
*
controlr
0
322
BC_7
ADDR_SGPIOA27
bidir
0
323
BC_2
*
controlr
0
324
BC_7
ADDR_SGPIOA28
bidir
0
325
BC_2
*
controlr
0
326
BC_7
ADDR_SGPIOA24
bidir
0
327
BC_2
*
controlr
0
328
BC_7
ADDR_SGPIOA23
bidir
0
329
BC_2
*
controlr
0
330
BC_7
ADDR_SGPIOA22
bidir
0
331
BC_2
*
controlr
0
332
BC_7
ADDR_SGPIOA30
bidir
0
333
BC_2
*
controlr
0
334
BC_7
ADDR_SGPIOA21
bidir
0
335
BC_2
*
controlr
0
336
BC_7
ADDR_SGPIOA20
bidir
0
337
BC_2
*
controlr
0
338
BC_7
ADDR_SGPIOA8
bidir
0
339
BC_2
*
controlr
0
340
BC_7
ADDR_SGPIOA31
bidir
0
341
BC_2
*
controlr
0
342
BC_7
ADDR_SGPIOA19
bidir
0
343
BC_2
*
controlr
0
344
BC_7
ADDR_SGPIOA18
bidir
0
345
BC_2
*
controlr
0
346
BC_7
ADDR_SGPIOA9
bidir
0
Pin
Function
Pad
Type
311
0
Z
IO
26v5vs
313
0
Z
IO
26v5vs
315
0
Z
IO
26v5vs
317
0
Z
IO
26v5vs
319
0
Z
IO
26v5vs
321
0
Z
IO
26v5vs
323
0
Z
IO
26v5vs
325
0
Z
IO
26v5vs
327
0
Z
IO
26v5vs
329
0
Z
IO
26v5vs
331
0
Z
IO
26v5vs
333
0
Z
IO
26v5vs
335
0
Z
IO
26v5vs
337
0
Z
IO
26v5vs
339
0
Z
IO
26v5vs
341
0
Z
IO
26v5vs
343
0
Z
IO
26v5vs
345
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
25-14
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
347
BC_2
*
controlr
0
348
BC_7
ADDR_SGPIOA17
bidir
0
349
BC_2
*
controlr
0
350
BC_7
ADDR_SGPIOA16
bidir
0
351
BC_2
*
controlr
0
352
BC_7
ADDR_SGPIOA10
bidir
0
353
BC_2
*
controlr
0
354
BC_7
ADDR_SGPIOA15
bidir
0
355
BC_2
*
controlr
0
356
BC_7
ADDR_SGPIOA14
bidir
0
357
BC_2
*
controlr
0
358
BC_7
ADDR_SGPIOA13
bidir
0
359
BC_2
*
controlr
0
360
BC_7
ADDR_SGPIOA11
bidir
0
361
BC_2
*
controlr
0
362
BC_7
ADDR_SGPIOA12
bidir
0
363
BC_2
*
controlr
0
364
BC_7
BI_B_STS_B
bidir
0
365
BC_2
*
controlr
0
366
BC_7
BURST_B
bidir
0
367
BC_2
*
controlr
0
368
BC_7
BDIP_B
bidir
0
369
BC_2
*
controlr
0
370
BC_7
TA_B
bidir
0
371
BC_2
*
controlr
0
372
BC_7
TS_B
bidir
0
373
BC_2
*
controlr
0
374
BC_7
TSIZ1
bidir
0
375
BC_2
*
controlr
0
376
BC_7
TSIZ0
bidir
0
377
BC_2
*
controlr
0
378
BC_7
TEA_B
bidir
0
379
BC_2
*
internal
1
380
BC_2
OE_B
output2
1
381
BC_2
*
controlr
0
382
BC_7
RD_WR_B
bidir
0
Pin
Function
Pad
Type
347
0
Z
IO
26v5vs
349
0
Z
IO
26v5vs
351
0
Z
IO
26v5vs
353
0
Z
IO
26v5vs
355
0
Z
IO
26v5vs
357
0
Z
IO
26v5vs
359
0
Z
IO
26v5vs
361
0
Z
IO
26v5vs
363
0
Z
IO
26v
365
0
Z
IO
26v
367
0
Z
IO
26v
369
0
Z
IO
26v
371
0
Z
IO
26v
373
0
Z
IO
26v
375
0
Z
IO
26v
377
0
Z
IO
26v
O
26v
IO
26v
381
0
Z
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-15
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
383
BC_2
*
internal
1
384
BC_2
CS3_B
output2
1
385
BC_2
*
internal
1
386
BC_2
CS2_B
output2
1
387
BC_2
*
internal
1
388
BC_2
CS1_B
output2
1
389
BC_2
*
internal
1
390
BC_2
CS0_B
output2
1
391
BC_2
*
internal
1
392
BC_2
WE_B_AT3
output2
1
393
BC_2
*
internal
1
394
BC_2
WE_B_AT2
output2
1
395
BC_2
*
internal
1
396
BC_2
WE_B_AT1
output2
1
397
BC_2
*
internal
1
398
BC_2
WE_B_AT0
output2
1
399
BC_2
*
controlr
0
400
BC_7
BR_B_VF1_IWP2
bidir
0
401
BC_2
*
controlr
0
402
BC_7
BG_B_VF0_LWP1
bidir
0
403
BC_2
*
controlr
0
404
BC_7
BB_B_VF2_IWP3
bidir
0
405
BC_2
*
controlr
0
406
BC_7
SGPIOC7_IRQOUT_B_LWP
0
bidir
0
407
BC_2
*
controlr
0
408
BC_7
IRQ1_B_RSV_B_SGPIOC1
bidir
0
409
BC_2
*
controlr
0
410
BC_7
IRQ0_B_SGPIOC0_MDO4
bidir
0
411
BC_2
*
controlr
0
412
BC_7
IRQ2_B_CR_B_SGPIOC2_
MDO5_MTS_B
bidir
0
413
BC_2
*
controlr
0
414
BC_7
IRQ4_B_AT2_SGPIOC4
bidir
0
415
BC_2
*
controlr
0
416
BC_7
IRQ3_B_KR_B_RETRY_B_
SGPIOC3
bidir
0
Pin
Function
Pad
Type
O
26v
O
26v
O
26v
O
26v
O
26v
O
26v
O
26v
O
26v
399
0
Z
IO
26v
401
0
Z
IO
26v
403
0
Z
IO
26v
405
0
Z
IO
26v5vs
407
0
Z
IO
26v5vs
409
0
Z
IO
26v
411
0
Z
IO
26v5vs
413
0
Z
IO
26v5vs
415
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
25-16
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-1. MPC561 Boundary Scan Bit Definition (continued)
Safe Contro
Disable Disable
Valu
l
Value
Result
e
Cell
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
417
BC_2
*
internal
1
418
BC_2
IWP0_VFLS0
output2
1
419
BC_2
*
internal
1
420
BC_2
IWP1_VFLS1
output2
1
421
BC_2
*
controlr
0
422
BC_7
SGPIOC6_FRZ_PTR_B
bidir
0
421
0
Z
Pin
Function
Pad
Type
O
26v
O
26v
IO
26v5vs
Pin
Functio
n
Pad
Type
IO
5vfa
O
5vfa
Table 25-2. MPC563 Boundary Scan Bit Definition
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
0
BC_2
*
controlr
0
1
BC_7
B_CNRX0
bidir
0
2
BC_2
*
internal
1
3
BC_2
B_CNTX0
output2
1
4
BC_2
*
controlr
0
5
BC_7
B_TPUCH0
bidir
0
6
BC_2
*
controlr
0
7
BC_7
B_TPUCH1
bidir
0
8
BC_2
*
controlr
0
9
BC_7
B_TPUCH2
bidir
0
10
BC_2
*
controlr
0
11
BC_7
B_TPUCH3
bidir
0
12
BC_2
*
controlr
0
13
BC_7
B_TPUCH4
bidir
0
14
BC_2
*
controlr
0
15
BC_7
B_TPUCH5
bidir
0
16
BC_2
*
controlr
0
17
BC_7
B_TPUCH6
bidir
0
18
BC_2
*
controlr
0
19
BC_7
B_TPUCH7
bidir
0
20
BC_2
*
controlr
0
21
BC_7
B_TPUCH8
bidir
0
22
BC_2
*
controlr
0
23
BC_7
B_TPUCH9
bidir
0
24
BC_2
*
controlr
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
0
0
Z
4
0
Z
IO
5vsa
6
0
Z
IO
5vsa
8
0
Z
IO
5vsa
10
0
Z
IO
5vsa
12
0
Z
IO
5vsa
14
0
Z
IO
5vsa
16
0
Z
IO
5vsa
18
0
Z
IO
5vsa
20
0
Z
IO
5vsa
22
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-17
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
25
BC_7
B_TPUCH10
bidir
0
26
BC_2
*
controlr
0
27
BC_7
B_TPUCH11
bidir
0
28
BC_2
*
controlr
0
29
BC_7
B_TPUCH12
bidir
0
30
BC_2
*
controlr
0
31
BC_7
B_TPUCH13
bidir
0
32
BC_2
*
controlr
0
33
BC_7
B_TPUCH14
bidir
0
34
BC_2
*
controlr
0
35
BC_7
B_TPUCH15
bidir
0
36
BC_2
*
controlr
0
37
BC_7
B_T2CLK_PCS4
bidir
0
38
BC_2
*
controlr
0
39
BC_7
A_T2CLK_PCS5
bidir
0
40
BC_2
*
controlr
0
41
BC_7
A_TPUCH0
bidir
0
42
BC_2
*
controlr
0
43
BC_7
A_TPUCH1
bidir
0
44
BC_2
*
controlr
0
45
BC_7
A_TPUCH2
bidir
0
46
BC_2
*
controlr
0
47
BC_7
A_TPUCH3
bidir
0
48
BC_2
*
controlr
0
49
BC_7
A_TPUCH4
bidir
0
50
BC_2
*
controlr
0
51
BC_7
A_TPUCH5
bidir
0
52
BC_2
*
controlr
0
53
BC_7
A_TPUCH6
bidir
0
54
BC_2
*
controlr
0
55
BC_7
A_TPUCH7
bidir
0
56
BC_2
*
controlr
0
57
BC_7
A_TPUCH8
bidir
0
58
BC_2
*
controlr
0
59
BC_7
A_TPUCH9
bidir
0
60
BC_2
*
controlr
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
24
0
Z
IO
5vsa
26
0
Z
IO
5vsa
28
0
Z
IO
5vsa
30
0
Z
IO
5vsa
32
0
Z
IO
5vsa
34
0
Z
IO
5vsa
36
0
Z
IO
5vfa
38
0
Z
IO
5vfa
40
0
Z
IO
5vsa
42
0
Z
IO
5vsa
44
0
Z
IO
5vsa
46
0
Z
IO
5vsa
48
0
Z
IO
5vsa
50
0
Z
IO
5vsa
52
0
Z
IO
5vsa
54
0
Z
IO
5vsa
56
0
Z
IO
5vsa
58
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
25-18
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
61
BC_7
A_TPUCH10
bidir
0
62
BC_2
*
controlr
0
63
BC_7
A_TPUCH11
bidir
0
64
BC_2
*
controlr
0
65
BC_7
A_TPUCH12
bidir
0
66
BC_2
*
controlr
0
67
BC_7
A_TPUCH13
bidir
0
68
BC_2
*
controlr
0
69
BC_7
A_TPUCH14
bidir
0
70
BC_2
*
controlr
0
71
BC_7
A_TPUCH15
bidir
0
72
BC_2
*
controlr
0
73
BC_7
A_AN0_ANW_PQB0
bidir
0
74
BC_2
*
controlr
0
75
BC_7
A_AN1_ANX_PQB1
bidir
0
76
BC_2
*
controlr
0
77
BC_7
A_AN2_ANY_PQB2
bidir
0
78
BC_2
*
controlr
0
79
BC_7
A_AN3_ANZ_PQB3
bidir
0
80
BC_2
*
controlr
0
81
BC_7
A_AN48_PQB4
bidir
0
82
BC_2
*
controlr
0
83
BC_7
A_AN49_PQB5
bidir
0
84
BC_2
*
controlr
0
85
BC_7
A_AN50_PQB6
bidir
0
86
BC_2
*
controlr
0
87
BC_7
A_AN51_PQB7
bidir
0
88
BC_2
*
controlr
0
89
BC_7
A_AN52_MA0_PQA0
bidir
0
90
BC_2
*
controlr
0
91
BC_7
A_AN53_MA1_PQA1
bidir
0
92
BC_2
*
controlr
0
93
BC_7
A_AN54_MA2_PQA2
bidir
0
94
BC_2
*
controlr
0
95
BC_7
A_AN55_PQA3
bidir
0
96
BC_2
*
controlr
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
60
0
Z
IO
5vsa
62
0
Z
IO
5vsa
64
0
Z
IO
5vsa
66
0
Z
IO
5vsa
68
0
Z
IO
5vsa
70
0
Z
IO
5vsa
72
0
Z
IO
5vsa
74
0
Z
IO
5vsa
76
0
Z
IO
5vsa
78
0
Z
IO
5vsa
80
0
Z
IO
5vsa
82
0
Z
IO
5vsa
84
0
Z
IO
5vsa
86
0
Z
IO
5vsa
88
0
Z
IO
5vsa
90
0
Z
IO
5vsa
92
0
Z
IO
5vsa
94
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-19
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
97
BC_7
A_AN56_PQA4
bidir
0
98
BC_2
*
controlr
0
99
BC_7
A_AN57_PQA5
bidir
0
100
BC_2
*
controlr
0
101
BC_7
A_AN58_PQA6
bidir
0
102
BC_2
*
controlr
0
103
BC_7
A_AN59_PQA7
bidir
0
104
BC_2
*
controlr
0
105
BC_7
B_AN0_ANW_PQB0
bidir
0
106
BC_2
*
controlr
0
107
BC_7
B_AN1_ANX_PQB1
bidir
0
108
BC_2
*
controlr
0
109
BC_7
B_AN2_ANY_PQB2
bidir
0
110
BC_2
*
controlr
0
111
BC_7
B_AN3_ANZ_PQB3
bidir
0
112
BC_2
*
controlr
0
113
BC_7
B_AN48_PQB4
bidir
0
114
BC_2
*
controlr
0
115
BC_7
B_AN49_PQB5
bidir
0
116
BC_2
*
controlr
0
117
BC_7
B_AN50_PQB6
bidir
0
118
BC_2
*
controlr
0
119
BC_7
B_AN51_PQB7
bidir
0
120
BC_2
*
controlr
0
121
BC_7
B_AN52_MA0_PQA0
bidir
0
122
BC_2
*
controlr
0
123
BC_7
B_AN53_MA1_PQA1
bidir
0
124
BC_2
*
controlr
0
125
BC_7
B_AN54_MA2_PQA2
bidir
0
126
BC_2
*
controlr
0
127
BC_7
B_AN55_PQA3
bidir
0
128
BC_2
*
controlr
0
129
BC_7
B_AN56_PQA4
bidir
0
130
BC_2
*
controlr
0
131
BC_7
B_AN57_PQA5
bidir
0
132
BC_2
*
controlr
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
96
0
Z
IO
5vsa
98
0
Z
IO
5vsa
100
0
Z
IO
5vsa
102
0
Z
IO
5vsa
104
0
Z
IO
5vsa
106
0
Z
IO
5vsa
108
0
Z
IO
5vsa
110
0
Z
IO
5vsa
112
0
Z
IO
5vsa
114
0
Z
IO
5vsa
116
0
Z
IO
5vsa
118
0
Z
IO
5vsa
120
0
Z
IO
5vsa
122
0
Z
IO
5vsa
124
0
Z
IO
5vsa
126
0
Z
IO
5vsa
128
0
Z
IO
5vsa
130
0
Z
IO
5vsa
MPC561/MPC563 Reference Manual, Rev. 1.2
25-20
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
133
BC_7
B_AN58_PQA6
bidir
0
134
BC_2
*
controlr
0
135
BC_7
B_AN59_PQA7
bidir
0
136
BC_2
*
controlr
0
137
BC_7
ETRIG2_PCS7
bidir
0
138
BC_2
*
controlr
0
139
BC_7
ETRIG1_PCS6
bidir
0
140
BC_2
*
controlr
0
141
BC_7
MDA11
bidir
0
142
BC_2
*
controlr
0
143
BC_7
MDA12
bidir
0
144
BC_2
*
controlr
0
145
BC_7
MDA13
bidir
0
146
BC_2
*
controlr
0
147
BC_7
MDA14
bidir
0
148
BC_2
*
controlr
0
149
BC_7
MDA15
bidir
0
150
BC_2
*
controlr
0
151
BC_7
MDA27
bidir
0
152
BC_2
*
controlr
0
153
BC_7
MDA28
bidir
0
154
BC_2
*
controlr
0
155
BC_7
MDA29
bidir
0
156
BC_2
*
controlr
0
157
BC_7
MDA30
bidir
0
158
BC_2
*
controlr
0
159
BC_7
MDA31
bidir
0
160
BC_2
*
controlr
0
161
BC_7
MPWM0_MDI1
bidir
0
162
BC_2
*
controlr
0
163
BC_7
MPWM1_MDO2
bidir
0
164
BC_2
*
controlr
0
165
BC_7
MPWM2_PPM_TX1
bidir
0
166
BC_2
*
controlr
0
167
BC_7
MPWM3_PPM_RX1
bidir
0
168
BC_2
*
controlr
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
132
0
Z
IO
5vsa
134
0
Z
IO
5vsa
136
0
Z
IO
5vfa
138
0
Z
IO
5vfa
140
0
Z
IO
5vsa
142
0
Z
IO
5vsa
144
0
Z
IO
5vsa
146
0
Z
IO
5vsa
148
0
Z
IO
5vsa
150
0
Z
IO
5vsa
152
0
Z
IO
5vsa
154
0
Z
IO
5vsa
156
0
Z
IO
5vsa
158
0
Z
IO
5vsa
160
0
Z
IO
26v5vs
162
0
Z
IO
26v5vs
164
0
Z
IO
26v5vs
166
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-21
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
169
BC_7
MPWM16
bidir
0
170
BC_2
*
controlr
0
171
BC_7
MPWM17_MDO3
bidir
0
172
BC_2
*
controlr
0
173
BC_7
MPWM18_MDO6
bidir
0
174
BC_2
*
controlr
0
175
BC_7
MPWM19_MDO7
bidir
0
176
BC_2
*
controlr
0
177
BC_7
MPIO32B5_MDO5
bidir
0
178
BC_2
*
controlr
0
179
BC_7
MPIO32B6_MPWM4_MDO6
bidir
0
180
BC_2
*
controlr
0
181
BC_7
MPIO32B7_MPWM5
bidir
0
182
BC_2
*
controlr
0
183
BC_7
MPIO32B8_MPWM20
bidir
0
184
BC_2
*
controlr
0
185
BC_7
MPIO32B9_MPWM21
bidir
0
186
BC_2
*
controlr
0
187
BC_7
MPIO32B10_PPM_TSYNC
bidir
0
188
BC_2
*
controlr
0
189
BC_7
MPIO32B11_C_CNRX0
bidir
0
190
BC_2
*
controlr
0
191
BC_7
MPIO32B12_C_CNTX0
bidir
0
192
BC_2
*
controlr
0
193
BC_7
MPIO32B13_PPM_TCLK
bidir
0
194
BC_2
*
controlr
0
195
BC_7
MPIO32B14_PPM_RX0
bidir
0
196
BC_2
*
controlr
0
197
BC_7
MPIO32B15_PPM_TX0
bidir
0
198
BC_2
*
controlr
0
199
BC_7
VF0_MPIO32B0_MDO1
bidir
0
200
BC_2
*
controlr
0
201
BC_7
VF1_MPIO32B1_MCKO
bidir
0
202
BC_2
*
controlr
0
203
BC_7
VF2_MPIO32B2_MSEI_B
bidir
0
204
BC_2
*
controlr
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
168
0
Z
IO
5vsa
170
0
Z
IO
26v5vs
172
0
Z
IO
26v5vs
174
0
Z
IO
26v5vs
176
0
Z
IO
26v5vs
178
0
Z
IO
26v5vs
180
0
Z
IO
5vsa
182
0
Z
IO
5vsa
184
0
Z
IO
5vsa
186
0
Z
IO
26v5vs
188
0
Z
IO
5vfa
190
0
Z
IO
5vfa
192
0
Z
IO
26v5vs
194
0
Z
IO
26v5vs
196
0
Z
IO
26v5vs
198
0
Z
IO
26v5vs
200
0
Z
IO
26v5vs
202
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
25-22
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
BSDL
Function
Safe
Value
205
BC_7
VFLS0_MPIO32B3_MSEO_
B
bidir
0
206
BC_2
*
controlr
0
207
BC_7
VFLS1_MPIO32B4
bidir
0
208
BC_2
*
internal
1
209
BC_2
A_CNTX0
output2
1
210
BC_2
*
internal
0
211
BC_4
A_CNRX0
input
X
212
BC_2
*
controlr
0
213
BC_7
PCS0_SS_B_QGPIO0
bidir
0
214
BC_2
*
controlr
0
215
BC_7
PCS1_QGPIO1
bidir
0
216
BC_2
*
controlr
0
217
BC_7
PCS2_QGPIO2
bidir
0
218
BC_2
*
controlr
0
219
BC_7
PCS3_QGPIO3
bidir
0
220
BC_2
*
controlr
0
221
BC_7
MISO_QGPIO4
bidir
0
222
BC_2
*
controlr
0
223
BC_7
MOSI_QGPIO5
bidir
0
224
BC_2
*
controlr
0
225
BC_7
SCK_QGPIO6
bidir
0
226
BC_2
*
internal
0
227
BC_4
ECK
input
X
228
BC_2
*
internal
1
229
BC_2
TXD1_QGPO1
output2
1
230
BC_2
*
internal
1
231
BC_2
TXD2_QGPO2_C_CNTX0
output2
232
BC_4
RXD1_QGPI1
233
BC_4
234
Pin/Port Name
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
204
0
Z
IO
26v5vs
206
0
Z
IO
26v5vs
O
5vfa
I
5vfa
212
0
Z
IO
5vfa
214
0
Z
IO
5vh
216
0
Z
IO
5vh
218
0
Z
IO
5vh
220
0
Z
IO
5vh
222
0
Z
IO
5vh
224
0
Z
IO
5vh
I
vfa
O
vfa
1
O
vfa
input
X
I
5vido
RXD2_QGPI2_C_CNRX0
input
X
I
5vido
BC_2
*
internal
0
235
BC_4
B0EPEE
input
X
236
BC_2
*
internal
0
237
BC_4
EPEE
input
X
238
BC_2
*
internal
1
239
BC_2
ENGCLK_BUCLK
output2
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-23
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
1
O
26vf
input
X
I
extclk
*
controlr
0
BC_7
SRESET_B
bidir
0
245
BC_2
*
controlr
0
246
BC_7
HRESET_B
bidir
0
247
BC_2
*
controlr
0
248
BC_7
RSTCONF_B_TEXP
bidir
0
249
BC_2
*
controlr
0
250
BC_7
IRQ7_B_MODCK3
bidir
0
251
BC_2
*
controlr
0
252
BC_7
IRQ6_B_MODCK2
bidir
0
253
BC_2
*
controlr
0
254
BC_7
IRQ5_B_SGPIOC5_MODCK
1
bidir
0
255
BC_2
*
controlr
0
256
BC_7
DATA_SGPIOD16
bidir
0
257
BC_2
*
controlr
0
258
BC_7
DATA_SGPIOD17
bidir
0
259
BC_2
*
controlr
0
260
BC_7
DATA_SGPIOD18
bidir
0
261
BC_2
*
controlr
0
262
BC_7
DATA_SGPIOD14
bidir
0
263
BC_2
*
controlr
0
264
BC_7
DATA_SGPIOD15
bidir
0
265
BC_2
*
controlr
0
266
BC_7
DATA_SGPIOD19
bidir
0
267
BC_2
*
controlr
0
268
BC_7
DATA_SGPIOD20
bidir
0
269
BC_2
*
controlr
0
270
BC_7
DATA_SGPIOD12
bidir
0
271
BC_2
*
controlr
0
272
BC_7
DATA_SGPIOD13
bidir
0
273
BC_2
*
controlr
0
274
BC_7
DATA_SGPIOD21
bidir
0
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
240
BC_2
*
internal
1
241
BC_2
CLKOUT
output2
242
BC_4
EXTCLK
243
BC_2
244
243
0
Z
IO
26vc
245
0
Z
IO
26vc
247
0
Z
IO
26v
249
0
Z
IO
26v
251
0
Z
IO
26v
253
0
Z
IO
26v
255
0
Z
IO
26v5vs
257
0
Z
IO
26v5vs
259
0
Z
IO
26v5vs
261
0
Z
IO
26v5vs
263
0
Z
IO
26v5vs
265
0
Z
IO
26v5vs
267
0
Z
IO
26v5vs
269
0
Z
IO
26v5vs
271
0
Z
IO
26v5vs
273
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
25-24
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
275
BC_2
*
controlr
0
276
BC_7
DATA_SGPIOD10
bidir
0
277
BC_2
*
controlr
0
278
BC_7
DATA_SGPIOD11
bidir
0
279
BC_2
*
controlr
0
280
BC_7
DATA_SGPIOD22
bidir
0
281
BC_2
*
controlr
0
282
BC_7
DATA_SGPIOD23
bidir
0
283
BC_2
*
controlr
0
284
BC_7
DATA_SGPIOD8
bidir
0
285
BC_2
*
controlr
0
286
BC_7
DATA_SGPIOD9
bidir
0
287
BC_2
*
controlr
0
288
BC_7
DATA_SGPIOD24
bidir
0
289
BC_2
*
controlr
0
290
BC_7
DATA_SGPIOD25
bidir
0
291
BC_2
*
controlr
0
292
BC_7
DATA_SGPIOD6
bidir
0
293
BC_2
*
controlr
0
294
BC_7
DATA_SGPIOD7
bidir
0
295
BC_2
*
controlr
0
296
BC_7
DATA_SGPIOD26
bidir
0
297
BC_2
*
controlr
0
298
BC_7
DATA_SGPIOD27
bidir
0
299
BC_2
*
controlr
0
300
BC_7
DATA_SGPIOD4
bidir
0
301
BC_2
*
controlr
0
302
BC_7
DATA_SGPIOD5
bidir
0
303
BC_2
*
controlr
0
304
BC_7
DATA_SGPIOD28
bidir
0
305
BC_2
*
controlr
0
306
BC_7
DATA_SGPIOD29
bidir
0
307
BC_2
*
controlr
0
308
BC_7
DATA_SGPIOD2
bidir
0
309
BC_2
*
controlr
0
310
BC_7
DATA_SGPIOD3
bidir
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
275
0
Z
IO
26v5vs
277
0
Z
IO
26v5vs
279
0
Z
IO
26v5vs
281
0
Z
IO
26v5vs
283
0
Z
IO
26v5vs
285
0
Z
IO
26v5vs
287
0
Z
IO
26v5vs
289
0
Z
IO
26v5vs
291
0
Z
IO
26v5vs
293
0
Z
IO
26v5vs
295
0
Z
IO
26v5vs
297
0
Z
IO
26v5vs
299
0
Z
IO
26v5vs
301
0
Z
IO
26v5vs
303
0
Z
IO
26v5vs
305
0
Z
IO
26v5vs
307
0
Z
IO
26v5vs
309
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-25
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
311
BC_2
*
controlr
0
312
BC_7
DATA_SGPIOD30
bidir
0
313
BC_2
*
controlr
0
314
BC_7
DATA_SGPIOD0
bidir
0
315
BC_2
*
controlr
0
316
BC_7
DATA_SGPIOD1
bidir
0
317
BC_2
*
controlr
0
318
BC_7
DATA_SGPIOD31
bidir
0
319
BC_2
*
controlr
0
320
BC_7
ADDR_SGPIOA29
bidir
0
321
BC_2
*
controlr
0
322
BC_7
ADDR_SGPIOA25
bidir
0
323
BC_2
*
controlr
0
324
BC_7
ADDR_SGPIOA26
bidir
0
325
BC_2
*
controlr
0
326
BC_7
ADDR_SGPIOA27
bidir
0
327
BC_2
*
controlr
0
328
BC_7
ADDR_SGPIOA28
bidir
0
329
BC_2
*
controlr
0
330
BC_7
ADDR_SGPIOA24
bidir
0
331
BC_2
*
controlr
0
332
BC_7
ADDR_SGPIOA23
bidir
0
333
BC_2
*
controlr
0
334
BC_7
ADDR_SGPIOA22
bidir
0
335
BC_2
*
controlr
0
336
BC_7
ADDR_SGPIOA30
bidir
0
337
BC_2
*
controlr
0
338
BC_7
ADDR_SGPIOA21
bidir
0
339
BC_2
*
controlr
0
340
BC_7
ADDR_SGPIOA20
bidir
0
341
BC_2
*
controlr
0
342
BC_7
ADDR_SGPIOA8
bidir
0
343
BC_2
*
controlr
0
344
BC_7
ADDR_SGPIOA31
bidir
0
345
BC_2
*
controlr
0
346
BC_7
ADDR_SGPIOA19
bidir
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
311
0
Z
IO
26v5vs
313
0
Z
IO
26v5vs
315
0
Z
IO
26v5vs
317
0
Z
IO
26v5vs
319
0
Z
IO
26v5vs
321
0
Z
IO
26v5vs
323
0
Z
IO
26v5vs
325
0
Z
IO
26v5vs
327
0
Z
IO
26v5vs
329
0
Z
IO
26v5vs
331
0
Z
IO
26v5vs
333
0
Z
IO
26v5vs
335
0
Z
IO
26v5vs
337
0
Z
IO
26v5vs
339
0
Z
IO
26v5vs
341
0
Z
IO
26v5vs
343
0
Z
IO
26v5vs
345
0
Z
IO
26v5vs
MPC561/MPC563 Reference Manual, Rev. 1.2
25-26
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
347
BC_2
*
controlr
0
348
BC_7
ADDR_SGPIOA18
bidir
0
349
BC_2
*
controlr
0
350
BC_7
ADDR_SGPIOA9
bidir
0
351
BC_2
*
controlr
0
352
BC_7
ADDR_SGPIOA17
bidir
0
353
BC_2
*
controlr
0
354
BC_7
ADDR_SGPIOA16
bidir
0
355
BC_2
*
controlr
0
356
BC_7
ADDR_SGPIOA10
bidir
0
357
BC_2
*
controlr
0
358
BC_7
ADDR_SGPIOA15
bidir
0
359
BC_2
*
controlr
0
360
BC_7
ADDR_SGPIOA14
bidir
0
361
BC_2
*
controlr
0
362
BC_7
ADDR_SGPIOA13
bidir
0
363
BC_2
*
controlr
0
364
BC_7
ADDR_SGPIOA11
bidir
0
365
BC_2
*
controlr
0
366
BC_7
ADDR_SGPIOA12
bidir
0
367
BC_2
*
controlr
0
368
BC_7
BI_B_STS_B
bidir
0
369
BC_2
*
controlr
0
370
BC_7
BURST_B
bidir
0
371
BC_2
*
controlr
0
372
BC_7
BDIP_B
bidir
0
373
BC_2
*
controlr
0
374
BC_7
TA_B
bidir
0
375
BC_2
*
controlr
0
376
BC_7
TS_B
bidir
0
377
BC_2
*
controlr
0
378
BC_7
TSIZ1
bidir
0
379
BC_2
*
controlr
0
380
BC_7
TSIZ0
bidir
0
381
BC_2
*
controlr
0
382
BC_7
TEA_B
bidir
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
347
0
Z
IO
26v5vs
349
0
Z
IO
26v5vs
351
0
Z
IO
26v5vs
353
0
Z
IO
26v5vs
355
0
Z
IO
26v5vs
357
0
Z
IO
26v5vs
359
0
Z
IO
26v5vs
361
0
Z
IO
26v5vs
363
0
Z
IO
26v5vs
365
0
Z
IO
26v5vs
367
0
Z
IO
26v
369
0
Z
IO
26v
371
0
Z
IO
26v
373
0
Z
IO
26v
375
0
Z
IO
26v
377
0
Z
IO
26v
379
0
Z
IO
26v
381
0
Z
IO
26v
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
25-27
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
383
BC_2
*
internal
1
384
BC_2
OE_B
output2
1
385
BC_2
*
controlr
0
386
BC_7
RD_WR_B
bidir
0
387
BC_2
*
internal
1
388
BC_2
CS3_B
output2
1
389
BC_2
*
internal
1
390
BC_2
CS2_B
output2
1
391
BC_2
*
internal
1
392
BC_2
CS1_B
output2
1
393
BC_2
*
internal
1
394
BC_2
CS0_B
output2
1
395
BC_2
*
internal
1
396
BC_2
WE_B_AT3
output2
1
397
BC_2
*
internal
1
398
BC_2
WE_B_AT2
output2
1
399
BC_2
*
internal
1
400
BC_2
WE_B_AT1
output2
1
401
BC_2
*
internal
1
402
BC_2
WE_B_AT0
output2
1
403
BC_2
*
controlr
0
404
BC_7
BR_B_VF1_IWP2
bidir
0
405
BC_2
*
controlr
0
406
BC_7
BG_B_VF0_LWP1
bidir
0
407
BC_2
*
controlr
0
408
BC_7
BB_B_VF2_IWP3
bidir
0
409
BC_2
*
controlr
0
410
BC_7
SGPIOC7_IRQOUT_B_LWP
0
bidir
0
411
BC_2
*
controlr
0
412
BC_7
IRQ1_B_RSV_B_SGPIOC1
bidir
0
413
BC_2
*
controlr
0
414
BC_7
IRQ0_B_SGPIOC0_MDO4
bidir
0
415
BC_2
*
controlr
0
416
BC_7
IRQ2_B_CR_B_SGPIOC2_|
MDO5_MTS_B
bidir
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
385
0
Z
Pin
Functio
n
Pad
Type
O
26v
IO
26v
O
26v
O
26v
O
26v
O
26v
O
26v
O
26v
O
26v
O
26v
403
0
Z
IO
26v
405
0
Z
IO
26v
407
0
Z
IO
26v
409
0
Z
IO
26v
411
0
Z
IO
26v5vs
413
0
Z
IO
26v5vs
415
0
Z
IO
26v
MPC561/MPC563 Reference Manual, Rev. 1.2
25-28
Freescale Semiconductor
IEEE 1149.1-Compliant Interface (JTAG)
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
BSDL
Bit
Cell
Type
Pin/Port Name
BSDL
Function
Safe
Value
417
BC_2
*
controlr
0
418
BC_7
IRQ4_B_AT2_SGPIOC4
bidir
0
419
BC_2
*
controlr
0
420
BC_7
IRQ3_B_KR_B_RETRY_B_
SGPIOC3
bidir
0
421
BC_2
*
internal
1
422
BC_2
IWP0_VFLS0
output2
1
423
BC_2
*
internal
1
424
BC_2
IWP1_VFLS1
output2
1
425
BC_2
*
controlr
0
426
BC_7
SGPIOC6_FRZ_PTR_B
bidir
0
Contro
Disabl
Disable
l
e
Value
Cell
Result
Pin
Functio
n
Pad
Type
417
0
Z
IO
26v5vs
419
0
Z
IO
26v5vs
O
26v
O
26v
IO
26v5vs
425
0
Z
1.Bi-state outputs (Pin Function = O) such as mdo_2, and mdo_3, are incorporated with general I/O pads hard-wired to keep
output enable always on in system mode. The JTAG Control cell, indicated by the next lower bsdl bit in the chain, is configured
as an “internal” only cell to be held at a “1” value (always driving out) during JTAG testing.
2. Some input-only cells made with generic I/O pads are configured with “internal” control cells to keep them always in input mode,
such as epee, b0epee, and input pins that may be attached to analog references. Other input-only cells are configured as
bidirectional for JTAG testing, to give the board-level ATPG tools the flexability to use the pad as an input or output, depending
on the network of other devices that the pin is connected too. If it is desired to restrict these pins to only act as receivers during
JTAG mode, then these JTAG bsdl entries can be converted as shown in the example below:
3. This description allows ATPG tools to use a pin as a driver or receiver:
188
BC_2
*
controlr
0
189
BC_7
irq6_b_modck2
bidir
0
188
0
Z
I
26v
I
26v
4. A modification to restrict ATPG tools to use a functional input-only pin as an input receiver only:.
188
BC_2
*
internal
0
189
BC_4
irq6_b_modck2
input
X
5. The PORESET, HRESET, and SRESET pins are not part of the JTAG boundary scan chain. These pins are used in the reset
configuration to enter JTAG. Board-level connections to them will not be testable with the EXTEST and CLAMP instructions.
They do respond to the HI-Z JTAG instruction for parametric testing purposes.6.
6. The XTAL, EXTAL, and XFC pins are associated with analog signals and are excluded from the boundary scan chain.
7. The READI module reset pin, rsti_b, (bsdl pin 517) is in the JTAG boundary scan chain, but must be kept at a “0” level during
JTAG testing, (except for Hi-Z testing), due to system interactions. It is classified as a “linkage” pin, and its data and control
cells are configured to advise ATPG tools to drive a “0” value in during JTAG testing.
8. Pad type naming conventions:
•26 V – 2.6 V
•5 V – 5 V
•s – slow
•f – fast
•h – high drive
•a – analog input
•i – input only
•d – has direct connection to the pad (may be used for module test)
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IEEE 1149.1-Compliant Interface (JTAG)
•r – resized cell instance
9. Column Descriptions:
•Columns 1 through 8 are entries from the boundary-scan description from the BSDL file. The columns and formats for each
of these entries are defined in the IEEE Std. 1149.1b-1994 Supplement to the IEEE Std. 1149.1-1990, IEEE Standard Test
Access Port and Boundary-Scan Architecture document. Descriptions of these columns are described below:
•Column 1: Defines the bit’s ordinal position in the boundary scan register. The shift register cell nearest TDO (i.e., first to be
shifted in) is defined as bit 0; the last bit to be shifted in is 519.
•Column 2: References one of the three standard JTAG Cell Types (BC_4, BC_2, and BC_7) that are used for this JTAG cell
in the MPC561/MPC563. See the IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
document for further description of these standard cell types.
•Column 3: Lists the pin name (also called the PortID) for all pin-related cells. For JTAG control cells or data cells that have
been designated as “internal”, an asterisk, is shown in this column.
•Column 4: Lists the BSDL pin function.
•Column 5: The “safe bit” column specifies the value that should be loaded into the capture (and update) flip-flop of a given
cell when board-level test generation software might otherwise choose a value randomly.
•Column 6: The “control cell” column identifies the cell number of the control cell that is associated with this data cell, and can
disable its output.
•Column 7: The “disable value” column gives the value that must be scanned into the control cell identified by the previous
“control cell” (column 6) to disable the port named by the relevant portID.
•Column 8: The “disable result” column identifies a given signal value of the PortID if that signal can be disabled. The values
shown specifies the condition of the driver of that signal when it is disabled.
•Column 9: The “pin function” column indicates the normal system pin directionality. (– Input Only Pin, O – Output Only Pin,
I/O – Bidirectional I/O pin)
•Column 10: The pad type column describes relevant characteristics about each pad type. See the Pad Type Keys in Note 5
above.
25.1.3
Instruction Register
The MPC561/MPC563 JTAG implementation includes the public instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS), and also supports the CLAMP instruction. One additional public
instruction (HI-Z) provides the capability for disabling all device output drivers. The MPC561/MPC563
includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs.
Data is transferred from the shift register to the parallel outputs during the update-IR controller state. The
four bits are used to decode the five unique instructions listed in.
Table 25-3. Instruction Decoding
Code
1
B3
B2
B1
B01
Instruction
0
0
0
0
EXTEST
0
0
0
1
SAMPLE/PRELOAD
0
X
1
X
BYPASS
0
1
0
0
HI-Z
0
1
0
1
CLAMP and BYPASS
B0 (LSB) is shifted first
The parallel output of the instruction register is reset to all ones in the test-logic-reset controller state.
NOTE
This preset state is equivalent to the BYPASS instruction.
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During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with
the CLAMP command code.
25.1.3.1
EXTEST
The external test (EXTEST) instruction selects the 520-bit boundary scan register. EXTEST also asserts
internal reset for the MPC561/MPC563 system logic to force a predictable beginning internal state while
performing external boundary scan operations.
By using the TAP, the register is capable of:
a) scanning user-defined values into the output buffers
b) capturing values presented to input pins
c) controlling the output drive of three-state output or bidirectional pins
25.1.3.2
SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction initializes the boundary scan register output cells prior to selection
of EXTEST. This initialization ensures that known data will appear on the outputs when entering the
EXTEST instruction. The SAMPLE/PRELOAD instruction also provides a means to obtain a snapshot of
system data and control signals.
NOTE
Since there is no internal synchronization between the scan chain clock
(TCK) and the system clock (CLKOUT), there must be provision of some
form of external synchronization to achieve meaningful results.
25.1.3.3
BYPASS
The BYPASS instruction selects the single-bit bypass register as shown in Figure 25-5. This creates a shift
register path from TDI to the bypass register and, finally, to TDO, circumventing the 520-bit boundary
scan register. This instruction is used to enhance test efficiency when a component other than the
MPC561/MPC563 becomes the device under test.
SHIFT DR
0
FROM TDI
G1
1
TO TDO
D
Mux
C
1
CLOCK DR
Figure 25-5. Bypass Register
When the bypass register is selected by the current instruction, the shift register stage is set to a logic zero
on the rising edge of TCK in the capture-DR controller state. Therefore, the first bit to be shifted out after
selecting the bypass register will always be a logic zero.
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25.1.3.4
CLAMP
The CLAMP instruction selects the single-bit bypass register as shown in Figure 25-5, and the state of all
signals driven from system output pins is completely defined by the data previously shifted into the
boundary scan register (for example, using the SAMPLE/PRELOAD instruction).
25.1.4
HI-Z
The HI-Z instruction is provided as a manufacturer’s optional public instruction to prevent having to
backdrive the output pins during circuit-board testing. When HI-Z is invoked, all output drivers, including
the two-state drivers, are turned off (i.e., high impedance). The instruction selects the bypass register.
25.2
MPC561/MPC563 Restrictions
The control afforded by the output enable signals using the boundary scan register and the EXTEST
instruction requires a compatible circuit-board test environment to avoid device-destructive
configurations. The user must avoid situations in which the MPC561/MPC563 output drivers are enabled
into actively driven networks.
The MPC561/MPC563 features a low-power stop mode. The interaction of the scan chain interface with
low-power stop mode is as follows:
1. The TAP controller must be in the test-logic-reset state to either enter or remain in the low-power
stop mode. Leaving the TAP controller in the test-logic-reset state negates the ability to achieve
low-power, but does not otherwise affect device functionality.
2. The TCK input is not blocked in low-power stop mode. To consume minimal power, the TCK input
should be externally connected to VDD or ground.
3. The TMS pin includes an on-chip pull-up resistor. In low-power stop mode, this pin should remain
either unconnected or connected to VDD to achieve minimal power consumption. Note that for
proper reset of the scan chain test logic, the best approach is to pull JCOMP low at power-on reset
(PORESET).
4. JCOMP must be low prior to PORESET assertion after low power mode exits otherwise an
unknown state will occur.
25.2.1
Non-Scan Chain Operation
In non-scan chain operation, there are two constraints. First, the TCK input does not include an internal
pull-up resistor and should not be left unconnected to preclude mid-level inputs. The second constraint is
to ensure that the scan chain test logic is kept transparent to the system logic by forcing TAP into the
test-logic-reset controller state, using either of two methods. Connecting pin JCOMP to logic 0 (or one of
the reset pins), or TMS must be sampled as a logic one for five consecutive TCK rising edges. If then TMS
either remains unconnected or is connected to VDD, then the TAP controller cannot leave the
test-logic-reset state, regardless of the state of TCK.
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25.2.2
BSDL Description
The BSDL file for the MPC561/MPC563 can be found on the Freescale web site.
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Appendix A
MPC562/MPC564 Compression Features
The MPC562/MPC564 contains a number of code compression features not found in the
MPC561/MPC563 that function from the burst buffer controller module (BBC) module of the device.
The BBC’s instruction code decompressor unit (ICDU) is responsible for on-line (previously compressed)
instruction code decompression in the decompression on mode. The ICDU contains a 2-Kbyte RAM
(DECRAM) that is used for decompressor vocabulary table storage when compression is enabled or as
general-purpose memory on the U-bus when compression is disabled.
NOTE
The code compression features of the MPC562/MPC564 are different than
the code compression of the MPC556.
A.1
ICDU Key Features
The following are instruction code decompression unit key features:
• Instruction code on-line decompression is based on an “instruction class” algorithm.
• There is no need for address translation between compressed and non-compressed address spaces
— ICDU provides the “next instruction address” to the RCPU.
• In most cases, instruction decompression takes one clock.
• Code decompression is pipelined:
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
• Two operation modes are available: decompression on and decompression off. Switches between
compressed and non-compressed user application software is possible.
• Adaptive vocabularies scheme is supported; each user application can have its own optimum
vocabularies.
A.2
Class-Based Compression Model Main Principles
The operational model used by the MPC562/MPC564 is explained in the sections below.
A.2.1
•
•
•
Compression Model Features
Implemented for MPC56x architecture
Up to 50% instruction code size reduction
No need for address translation tables
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A-1
MPC562/MPC564 Compression Features
•
•
•
•
•
•
•
•
No changes in the CPU architecture
A compressor tool performs compression off-line in software using instruction class-based
algorithms optimized for the MPC56x instruction set
Decompression is done at run-time by special hardware
Optimized for cache-less systems:
— Highly effective in system solutions for a low-cache hit ratio environment and for systems with
fast embedded program memory
— Deterministic program execution
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Switches between compressed and non-compressed user application sections is possible. (A
compressed subroutine can call a non-compressed one and be called from non-compressed portions
of the user application)
Adaptive vocabularies, generated for a particular application
Compressed address space is up to 1 Gbyte
Branch displacement from its target:
— Conditional branch displacement is up to 4 Kbytes
— Unconditional branch displacement is up to 4 Mbytes
NOTE
Branch displacement is hardware limited. The compiler can enlarge the
branch scope by creating branch chains.
A.2.2
Model Limitations
No address arithmetic is allowed for instruction space because the address map changes during
compression and no software tool can identify address arithmetic structures in the code. Address
arithmetic for data tables is permitted since data space is not compressed. Only instruction space is
compressed.
A.2.3
Instruction Class-Based Compression Algorithm
The code compression algorithm is based on creating optimal vocabularies of frequently appearing RCPU
RISC instructions or instruction halves and replacing these instructions with pointers to the vocabularies.
The system contains several sets of vocabularies for different groups of instructions. These groups are
referred to as classes.
Every instruction belongs to exactly one class. Compression of the instructions in a class may be in one of
the following modes. Refer to Figure A-1.
1. Compression of the whole instruction into one vocabulary pointer
2. Compression of each half of the instruction into a different vocabulary
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MPC562/MPC564 Compression Features
3. Compression of one of the instruction’s halves into a vocabulary pointer and bypass of the other
half. A bypassed field is one for which non-compressed data (16-bit halfword or 32-bit word) is
placed in the compressed code. After compression is defined, the non-compressed data field is
defined in the class.
4. Bypass of the whole instruction. No compression is permitted.
Uncompressed Instruction
Compressed Instruction
1.
1.
2.
2.
3.
3.
OR
4.
4.
Legend
Uncompressed or Bypassed Code
Compressed Code
Class Identifier
Figure A-1. Instruction Compression Alternatives
A 4-bit class identifier is added to the beginning of each compressed instruction to supply class
identification during decompression. Compressed and bypass field lengths may vary. (A fully bypassed
instruction, including its 4-bit class identifier, is 36 bits.)
The compressed instruction is guaranteed to start on an even bit. Thus, four bits are needed to find the
starting location of the instruction inside a memory word. The instruction address in decompression on
mode consists of a 28-bit word address (1 Gbyte of address space) and a 4-bit instruction pointer (IP). See
Figure A-2.
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MPC562/MPC564 Compression Features
27
Compressed
Instruction
Adddress
Base Address
31
IP
x
Memory
Layout
x+4
x+8
2*IP Bits
x+c
– Compressed Instruction
Figure A-2. Addressing Instructions with Compressed Address
A.2.4
Compressed Address Generation with Direct Branches
During the compression process, compressed instructions change their location in the memory and are not
word aligned. Displacement fields in the direct branch instructions have to be updated by the compression
tool to make compressed instruction addressing possible. Four LSB bits of the displacement immediate
field (LI or BD) in the compressed direct branch instructions are used for bit addressing in the 32-bit
memory word. The remaining bits of the fields are used in the branch target calculation of the base address
(word address). The RCPU branch unit copies the bit pointer into the IP field of issued compressed branch
target address. The branch compressed target base address is calculated according the direct branch
addressing mode.
If a branch has absolute addressing mode, the branch target base address is calculated as a sign extension
of the base address portion of the LI (or BD) field.
If a branch has relative addressing mode, the branch target base address is calculated as a sum of the base
address of the branch and sign extended base address portion of the branch LI (or BD) field.
Figure A-3 illustrates direct branch target address generation in “Decompression On” mode. The base
address for the unconditional branch has 20 bits This yields an unconditional branch displacement limit of
4 Mbytes. The word pointer for the conditional branch has 10 bits. This yields a conditional branch
displacement limit of 4 Kbytes.
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MPC562/MPC564 Compression Features
AA
Word Pointer (LI)
0
6
30 31
Unconditional immediate branch instruction BEFORE compression mapping
4-bit
Pointer
26
Word Pointer
0
6
AA
30 31
Unconditional immediate branch instruction AFTER compression mapping (I-form)
Sign
Extension
Word Pointer
27
0
8
Sign extended Base address generation for unconditional branches
OR
AA
W o rd P o in te r (BD )
0
16
30 31
Conditional immediate branch instruction BEFORE compression mapping
Word Pointer
4-biit
Pointer
26
16
0
Conditional immediate branch instruction AFTER compression mapping (B-form)
Sign Extension
AA
30 31
Word Pointer
27
0
18
Sign extended Base address generation for conditional branches
Si gn Extended Base Addres s
Base address of the branc h
+
AA=0
OR
A A=1
Word Pointer - Base Address
0
Bit pointer from
i nstruction
4-bit
Pointer
28
31
Branch target compressed address
Figure A-3. Compressed Target Address Generation by Direct Branches
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A-5
MPC562/MPC564 Compression Features
When a change of flow occurs, the RCPU issues the new address in compression format. The address
extractor unit of the BBC extracts the base address to instruction memory. When the compressed memory
word is brought to the BBC from the memory, the ICDU uses the IP field of the RCPU-issued address to
decompress the instruction. The BBC provides compressed addresses of the decompressed and next
instructions to the RCPU together with the decompressed instruction.
Shortened word pointer fields of direct branches in compressed mode imply some limitations on compilers
that implement the PowerPC ISA architecture. They should generate binaries, with limited direct branch
displacements to make the compression possible.
If a conditional branch target, generated by a compiler, must be farther than the compression mode
limitation of 4 Kbytes, the compiler may generate a sequence of a conditional branch with opposite
condition to skip the following unconditional branch to the original target.
If the unconditional branch range is still not big enough, the compiler can use branch chains or indirect
branches.
A.2.5
Compressed Address Generation—Indirect Branches
The indirect branch destination address is copied without any change from one of the following RCPU
registers:
• LR
• CTR
• SRR0
See the RCPU User’s Manual for more details.
These registers should contain (or be loaded by) the 32-bit compressed address of existing compressed
instructions to be used for correct branching.
The LR register is automatically updated by the correct value of the “next” instruction compressed address
during subroutine calls by using the ‘L’ - form of branch instructions (like bl or bcl).
The SRR0 register is updated by the correct return compressed address when exceptions are taken by the
RCPU, thus the rfi instruction obtains the correct return address from an exception handler.
A.2.6
Compressed Address Generation—Exceptions
Upon an exception, the RCPU core issues a regular 0xFFF00X00 or 0x00000X00 exception vector as
specified in the PowerPC ISA architecture. The compressed exception routines (or branches to them)
should start (reside) at the same location in memory as noncompressed ones. The BBC ICDU passes the
vectors unchanged to the MCU internal bus and provides corresponding compressed address to the RCPU
together with the first exception handler instruction opcode.
This scheme allows use of the BBC exception relocation feature regardless of the MCU operational mode.
The RESET routine vector is relocated differently in decompression on and in decompression off modes.
This feature may be used by a software code compression tool to guarantee that a vocabulary table
initialization routine is always executed before application code is running.
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MPC562/MPC564 Compression Features
A.2.7
•
•
•
•
•
•
•
•
•
•
Class Code Compression Algorithm Rules
Compressed instruction length may vary between 6 and 36 bits and is even.
A compressed instruction can begin at any even location in a memory word.
An instruction source may be compressed as a single 32-bit segment or as two independent 16-bit
segments.
Possible partitions of an instruction for compression are:
– One 32-bit bypass segment
– One 32-bit compressed segment
– One 16-bit compressed segment and one 16-bit bypass segment
– Two 16-bit compressed segments
A bypass field is always the second field of the two possible. Length of a bypass field can be zero,
10, 15, 16 or 32 bits.
The class prefix in a compressed instruction is 4 bits long and covers up to 16 classes.
The vocabulary table pointer of each field may be 2 to 9 bits long.
Vocabulary table pointers are reversed in the code. This means the pointer’s LSB will be the first
bit.
In a class with a single segment of full compression, data is fetched from both memories.
Every vocabulary table in the DECRAM is 16 bytes (8 entries) aligned (3 LSBs zeroed).
A.2.8
Bypass Field Compression Rules
The bypass field can be either a full bypass, (i.e., the whole segment from the un-compressed instruction
appears as is in the compressed instruction), or it can be represented in one of several compression
encoding formats. These formats are hard-wired in the decompression module.
A.2.8.1
Branch Right Segment Compression #1
For the MPC562/MPC564, a 15-bit bypass is used to indicate that the AA bit of a branch instruction should
be inserted with a value of zero. The decompression process is performed as shown in Figure A-4.
0
13 14
16
29 30 31
15-bit Compressed
Bypass Field
Decompressed
Right Segment
0
LK
Figure A-4. Branch Right Segment Compression #1
This bypass is coded by a value of “13” (0xD) in the TP2LEN field of the DCCR register.
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MPC562/MPC564 Compression Features
A.2.8.2
Branch Right Segment Compression #2
Also created for branch instructions on the MPC562/MPC564, a bypass of 10 bits indicates that the AA
bit should be inserted with a value of zero and that the 5-bit word offset should be extended to 10 bits. The
decompression process is performed as shown in Figure A-5.
0
8
4 5
1
9
10-bit Compressed Bypass Field
16
Decompressed
Right Segment
21 22
w
o r
d
o
f
f
s
e
25 26
t
29 30 31
IP
0
LK
Figure A-5. Branch Right Segment Compression #2
This bypass is coded by a value of “12” (0xC) in the TP2LEN field of the DCCR register.
A.2.8.3
Right Segment Zero Length Compression Bypass
This MPC562/MPC564 bypass type indicates that no bypass data exists in the compressed instruction. The
bypassed segment is16 zero bits.
This bypass is coded by a value of “11” (0xB) in the TP2LEN field of the DCCR register.
A.2.9
Instruction Class Structures and Programming
The four possible compression layouts of an instruction and their attributes are listed in this section. See
Section A.4, “Decompressor Class Configuration Registers (DCCR0-15),” for the instruction class
attributes and more programming details.
A.2.9.1
Global Bypass
This MPC562/MPC564 instruction is not compressed at all.
Uncompressed Instruction
MSB
32-bit segment – to be bypassed
Compressed Instruction
0000
32-bit bypass data
Figure A-6. Global Bypass Instruction Layout
This class does not have a configuration register. Its prefix is hard-wired to ‘0000’ and no other attributes
are needed.
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A.2.9.2
Single Segment Full Compression – CLASS_1
This MPC562/MPC564 instruction is compressed into a single segment. The vocabulary table pointer
points to an offset in tables of all RAMs (DECRAMs).
Uncompressed Instruction
MSB
32-bit segment – to be compressed
Compressed Instruction
4-bit class
2-to 9-bit TP1
Figure A-7. CLASS_1 Instruction Layout
The definition of the class includes:
• TP1 length = 2-9
• TP2 length = 0
• TP1 base address, TP2 base address = the two tables’ base addresses for RAM #1 and RAM #2,
respectively.
• AS, DS=0
Data brought from RAM#1 is the 16 MSBs of the decompressed instruction and data brought from
RAM#2 is the 16 LSBs of the decompressed instruction.
A.2.9.3
Twin Segment Full Compression – CLASS_2
This MPC562/MPC564 instruction is divided into two segments. Each segment is compressed and mapped
into a different vocabulary. The vocabularies reside in different RAMs. Proper programming can swap the
vocabularies’ locations.
Uncompressed Instruction
MSB
16-bit segment #1 – to be compressed
16-bit segment #2 – to be compressed
Compressed Instruction
Alternative #1 (CLASS_2a)
4-bit class
2- to 9-bit TP1 for segment #1
2- to 9-bit TP2 for segment #2
Alternative #2 (CLASS_2b)
4-bit class
2- to 9-bit TP1 for segment #2
2- to 9-bit TP2 for segment #1
Figure A-8. CLASS_2 Instruction Layout
The definition of the class includes:
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MPC562/MPC564 Compression Features
•
•
•
•
TP1 length=2-9
TP2 length=2-9
AS=0
For alternative #1:
— TP1 base address = base address of segment #1 vocabulary in RAM #1
— TP2 base address = base address of segment #2 vocabulary in RAM #2
— DS=0
For alternative #2:
— TP1 base address = base address of segment #2 vocabulary in RAM #1
— TP2 base address = base address of segment #1 vocabulary in RAM #2
— DS=1
•
Alternatives #1 and #2 are referred to as CLASS_2a and CLASS_2b respectively.
A.2.9.4
Left Segment Compression and Right Segment Bypass – CLASS_3
For the MPC562/MPC564, the instruction is divided into two segments. The left segment is compressed
and mapped into a vocabulary. The vocabulary location is programmable. The right segment is either fully
bypassed by a 16-bit field or by a shorter field which is decompressed according to fixed rules.
.
Uncompressed Instruction
MSB
16-bit segment #1 – to be compressed
16-bit segment #2 – to be bypassed
Compressed Instruction
4-bit class
2- to 9-bit TP1 for segment #1
0-, 10-, 15- or 16-bit bypass for segment #2
Figure A-9. CLASS_3 Instruction Layout
The definition of the class includes
• TP1 length=2-9
• TP2 length=0xB, 0xC, 0xD, or 0xE indicating a 0, 10, 15 or 16 bit bypass, respectively.
• TP1 base address = base address of segment #1 vocabulary in RAM #1, if it exists there.
• TP2 base address = base address of segment #1 vocabulary in RAM #2, if it exists there.
• DS=0
• AS=0 or 1 directing access to the vocabulary in RAM #1 or RAM #2, respectively.
When the vocabulary is located in RAM #1, the class will be referred to as CLASS_3a and when the
vocabulary is located in RAM #2, the class will be referred to as CLASS_3b.
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MPC562/MPC564 Compression Features
A.2.9.5
Left Segment Bypass and Right Segment Compression—CLASS_4
This MPC562/MPC564 instruction is divided into two segments. The left segment is either fully bypassed
by a 16-bit field or by a shorter field which is decompressed according to fixed rules. The right segment
is compressed and mapped into a vocabulary. The vocabulary location is programmable. The compressed
fields must be swapped in the compressed instruction order to follow the rule that bypass appears only in
the second field of a compressed instruction.
.
Uncompressed Instruction
MSB
16-bit segment #1 – to be bypassed
16-bit segment #2 – to be compressed
Compressed Instruction
4-bit class
2- to 9-bit TP1 for segment #2
0-, 10-, 15- or 16-bit bypass for segment #1
Figure A-10. CLASS_4 Instruction Layout
The definition of the class includes:
• TP1 length=2-9
• TP2 length=0xB, 0xC, 0xD, or 0xE indicating a 0, 10, 15 or 16 bit bypass, respectively.
• TP1 base address = base address of segment #1 vocabulary in RAM #1, if it exists there
• TP2 base address = base address of segment #1 vocabulary in RAM #2, if it exists there
• DS=1
• AS=0 or 1 directing access to the vocabulary in RAM #1 or RAM #2, respectively.
When the vocabulary is located in RAM #1, the class is referred to as CLASS_4band when the vocabulary
is located in RAM #2, the class is referred to as CLASS_4a. Refer to Table A-4.
A.2.10
Instruction Layout Programming Summary
Table A-4 summarizes the programming for all possible compressed instruction layouts.
The un-compressed instruction of two half-words are referred as H1 & H2. The compressed instruction
can be built out of: (1) X1 field – representing a vocabulary pointer for encoding of either H1 or H1+H2;
(2) X2 field – representing a vocabulary pointer for encoding of H2; and (3) BP – representing a bypass
field.
Vocabularies V1 and V2 refer to the 16 MSB and 16 LSB of the uncompressed instruction, respectively.
A.2.11
Compression Process
The compression process is implemented by the following steps. See Figure A-11.
• User code compilation/linking
• Vocabulary and class generation
• User application code compression by a software compression tool
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A-11
MPC562/MPC564 Compression Features
The vocabulary and class configurations are generated by profiling the static code, based on the instruction
class algorithm.
The code compression can be created by using either default or specific application vocabularies,
generated at the previous step. In case of default vocabularies, the generation step can be omitted, but
compression efficiency is reduced.
The compression tool replaces regular PowerPC ISA instructions with a compressed representation that
contains fewer bits. The tool also updates offset fields in direct branch instructions to include a compressed
format offset (four bits of IP and word offset). Thus, maximum branch offsets in decompression on mode
are reduced. The RCPU uses the word offset for direct branch target address computation. The RCPU
provides the instruction pointer portion of the branch offset field to the decompression unit as it is
represented in the branch instruction.
Program
Executable
Non-compressed
Program
Executable
Compressed
Compiler/
Compressor
Tool
Linker
Classes
Generator
Classes
Vocabulary
Vocabulary
Generator
Vocabulary
Generation Tool
Figure A-11. Code Compression Process
A.2.12
•
•
•
•
•
Decompression
The instruction code is stored in the memory in the compressed format
The vocabularies are stored in a dedicated ICDU RAM (DECRAM)
The class configuration is stored in a dedicated ICDU register (DCCR)
The decompression is done on-line by the dedicated decompressor unit
Decompression flow is as follows: (See Figure A-12)
— RCPU provides to the BBC a 2-bit aligned change of flow (COF) address
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MPC562/MPC564 Compression Features
— The ICDU:
– Converts the COF address to a word-aligned physical address to access the memory
– Fetches the compressed instruction code from the memory, decompresses it and delivers
non-compressed instruction code, together with the bit-aligned next instruction address, to
the RCPU.
Compressed
Instructions
Memory
Decompressor
Bit-Aligned COF
Address
COF Word Aligned
Physical Address
MPC500
Vocabulary
Noncompressed
Instruction Code
Embedded
CPU
Compressed
Instruction
Code
Classes (DCCR)
Registers
Compressed Space
“Next Instruction”
Address
ICDU
Figure A-12. Code Decompression Process
A.2.13
Compression Environment Initialization
In order to commence the execution of the compressed code, the DECRAM and the class information (in
the DCCR registers) must be programmed. The data to be programmed is supplied by the compressor tool
and the vocabulary generator. There are two initialization scenarios:
1. Wake up in decompression off mode — If the chip wakes up with decompression disabled, the
initialization routine can be executed at any time before entering decompression on mode. After
the compression environment is initialized, the operational mode would be changed to
decompression on.
2. Wake up in decompression on mode — If the chip wakes up in decompression on mode, it has to
process compressed instructions without the vocabularies and class parameters. Thus, all
instructions executed until the end of the initialization routine should be compressed in the global
bypass format. DECRAM loading is an essential part of this intialization routine. After DECRAM
loading, efficient compressed code may be used.
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MPC562/MPC564 Compression Features
A.2.14
Compression/Non-Compression Mode Switch
The MPC562/MPC564 allows the option to switch between compressed and non-compressed code on the
fly. There are two ways to switch between the modes, as shown in Section A.2.14.1, “Compression
Definition for Exception Handlers,” and Section A.2.14.2, “Running Mixed Code.”
A.2.14.1
Compression Definition for Exception Handlers
The MPC562/MPC564 can wake up upon reset with all the exception handlers defined to be compressed
(or not), so when any exception occurs or completes, the hardware switches to the appropriate mode
without software intervention.
A.2.14.2
Running Mixed Code
If the compression mode is enabled on the MPC562/MPC564, the software can switch between
compressed and non-compressed code by setting (or clearing) the compression mode bit in the RCPU
MSR register. This is done by setting/clearing bit 29 in the RCPU SRR1 register (SRR1 gets loaded into
the MSR register when the rfi instruction is executed. Bit 29 is the DCMPEN bit of the MSR). The next
step is to load SRR0 with a target address in compressed/non-compressed format and then executing an rfi
instruction. Following is a suggested routine to execute the switch in both directions (must be run in
supervisor mode when RCPU MSR[PR] bit is cleared):
# R30 contains destination address in appropriate format
.set turn_on_compression_bit_mask, 4
.set turn_off_compression_bit_mask, 0xfffb
mfmsr
r31
# to go to compressed code
ori
r31,r31,turn_on_compression_bit_mask
# or alternative to go to uncompressed code:
andi.
r31,r31,turn_off_compression_bit_mask
mtspr
NRI,r0 # Disable external interrupts
mtspr
SRR1,r31
mtspr
SRR0,r30 # destination address load
rfi
# branch and modify MSR
NOTE
When BBCMCR[EN_COMP] (bit 21) is set, modification of
MSR[DCMPEN] (bit 29) by mtmsr instruction is strictly forbidden. It may
cause the machine to hang until reset.
A.3
A.3.1
Operation Modes
Instruction Fetch
The MPC562/MPC564 provides two instruction fetch modes: decompression off and decompression on.
The operational modes are defined by RCPU MSR[DCMPEN] bit. If the bit is set, the mode is
decompression on. Otherwise, it is in decompression off.
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MPC562/MPC564 Compression Features
A.3.1.1
Decompression Off Mode
Refer to Section 4.2.1.1, “Decompression Off Mode” for an explanation of decompression off.
A.3.1.2
Decompression On Mode
In this mode, the MPC562/MPC564’s RCPU sends the two-bit aligned change of flow (COF) address to
the BBC. The BIU transfers the word portion of the address to the U-bus. The BBC continues to pre-fetch
the data from the consequent memory addresses regardless of whether the RCPU requests them in order
to supply data to the ICDU.
In the MPC562/MPC564, the data coming from the instruction memory is not provided directly to the
RCPU, but loaded into the ICDU for decompression. Decompressed instruction code together with “next
instruction address” are provided to the RCPU whenever it requires another instruction fetch.
All addresses issued by the BIU to the U-bus are transferred in parallel to the IMPU. The IMPU compares
the address of the access to its region programming. If any protection violation is detected by the IMPU,
the current U-bus access is aborted by the BIU and an instruction storage protection error exception is
signaled to the RCPU.
Show cycle and program trace access attributes accompanying the COF RCPU access only are forwarded
by the BIU along with the U-bus access. Additional information about the IP of the compressed instruction
address is provided on the U-bus data bus. Refer below to Section A.3.1.2.1, “Show Cycles in
Decompression On Mode,” for more details.
In this mode the MPC562/MPC564’s ICDU DECRAM is used as a decompressor vocabulary storage and
may not be used as a general purpose RAM.
A.3.1.2.1
Show Cycles in Decompression On Mode
In the MPC562/MPC564’s decompression on mode, the instruction address consists of an instruction base
address and four bits of the instruction bit pointer. In order to provide the capability to show full instruction
address, including instruction bit pointer on the external bus, show cycle information is presented not only
on the address bus, but also on some bits of the data bus:
• ADDR[0:29] – show the value of the base address of compressed instruction (word pointer into the
memory)
• DATA[0] – shows in which mode the MPC562/MPC564 is operating
— 0 = decompression off mode
— 1 = decompression on mode
• DATA[1:4] – represent an instruction bit pointer within the word.
Instruction show cycle bus transactions have the following characteristics (see Figure 9-41):
• One clock cycle
• Address phase only; in decompression on mode part of the compressed address is driven on data
lines together with address lines. The external bus interface adds one clock delay between a read
cycle and such show cycle.
• STS assertion only (no TA assertion)
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MPC562/MPC564 Compression Features
NOTE
The BBCMCR[DECOMP_SC_EN] bit determines if the data portion
(DATA[0:4]) of the instruction show cycle is driven or not, regardless of
decompression mode (BBCMCR[EN_COMP] bit)
A.3.2
Vocabulary Table Storage Operation
The MPC562/MPC564 uses DECRAM for decompressor vocabulary tables (VT1 and VT2) storage in
decompression on mode. The ICDU utilizes DECRAM as two separately accessed 1-Kbyte RAM arrays
(16 bits wide) that are accessed via internal ICDU buses. The VTs should be loaded before the
decompression process starts. In order to allow decompression, the DECRAM must be disabled for the
U-bus accesses after VTs and decompressor class configuration registers (DCCRs) are initialized.
A.3.3
READI Compression
Setting BBCMCR[DECOMP_SC_EN] when decompression is enabled allows READI to track the
compressed code (see Chapter 24, “READI Module”). BBCMCR[DECOMP_SC_EN] should not be set
if there is no intention to use compressed code, as it will degrade U-bus performance. The show cycle may
be delayed by one clock by the USIU if the show cycle occurs after an external device read cycle. Refer
to Section 24.6.5.2, “Compressed Code Mode Guidelines.”
The ICTRL register must be programmed such that a show cycle will be performed for all changes in the
program flow (ISCTL field = 0b01), or the PTM bit must be set and ISCTL must be set to a value other
than 0b11. (See Table A-2.)
A.3.3.1
I-Bus Support Control Register (ICTRL)
MSB
0
Field
1
2
3
CTA
4
5
6
CTB
7
8
9
CTC
Reset
10
11
CTD
12
13
IWP0
14
15
IWP1
0000_0000_0000_0000
LSB
16
17
Field IWP2
18
19
IWP3
20
21
22
23
24
25
26
27
28
29
30
31
SIWP0 SIWP1 SIWP2 SIWP3 DIWP0 DIWP1 DIWP2 DIWP3 IFM ISCT_SER1
EN
EN
EN
EN
EN
EN
EN
EN
Reset
0000_0000_0000_0000
Addr
SPR 158
Figure A-13. I-Bus Support Control Register (ICTRL)
1
Changing the instruction show cycle programming starts to take effect only from the second instruction after the
actual mtspr to ICTRL.
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MPC562/MPC564 Compression Features
Table A-1. ICTRL Bit Descriptions
Function
Bits
Mnemonic
Description
Non-compressed mode
0xx = not active (reset value)
100 = equal
101 = less than
110 = greater than
111 = not equal
Compressed Mode1
0:2
CTA
Compare type of comparator A
3:5
CTB
Compare type of comparator B
6:8
CTC
Compare type of comparator C
9:11
CTD
Compare type of comparator D
12:13
IWP0
I-bus 1st watchpoint
programming
0x = not active (reset value)
10 = match from comparator A
11 = match from comparators (A&B)
14:15
W1
I-bus 2nd watchpoint
programming
0x = not active (reset value)
10 = match from comparator B
11 = match from comparators (A | B)
16:17
IWP2
I-bus 3rd watchpoint
programming
0x = not active (reset value)
10 = match from comparator C
11 = match from comparators (C&D)
18:19
IWP3
I-bus 4th watchpoint
programming
0x = not active (reset value)
10 = match from comparator D
11 = match from comparators (C | D)
0x = not active (reset value)
10 = match from comparator D
11 = match from comparators (C | D)
20
SIWP0EN
21
SIWP1EN
22
SIWP2EN
Software trap enable selection of
the 3rd I-bus watchpoint
23
SIWP3EN
Software trap enable selection of
the 4th I-bus watchpoint
24
DIWP0EN
Development port trap enable
selection of the 1st I-bus
watchpoint (read only bit)
25
DIWP1EN
Development port trap enable
selection of the 2nd I-bus
watchpoint (read only bit)
26
DIWP2EN
Development port trap enable
selection of the 3rd I-bus
watchpoint (read only bit)
27
DIWP3EN
Development port trap enable
selection of the 4th I-bus
watchpoint (read only bit)
Software trap enable selection of 0 = trap disabled (reset
the 1st I-bus watchpoint
value)
1 = trap enabled
Software trap enable selection of
the 2nd I-bus watchpoint
0 = trap disabled (reset
value)
1 = trap enabled
1xx = not active
000 = equal (reset value)
001 = less than
010 = greater than
011 = not equal
0 = trap disabled (reset
value)
1 = trap enabled
0 = trap disabled (reset
value)
1 = trap enabled
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MPC562/MPC564 Compression Features
Table A-1. ICTRL Bit Descriptions (continued)
Function
Bits
1
Mnemonic
28
IFM
29:31
ISCT_SER
Description
Non-compressed mode
Compressed Mode1
Ignore first match, only for I-bus
breakpoints
0 = Do not ignore first match,
used for “go to x” (reset
value)
1 = Ignore first match (used
for “continue”)
0 = Do not ignore first match,
used for “go to x” (reset
value)
1 = Ignore first match (used
for “continue”)
RCPU serialize control and
Instruction fetch show cycle
These bits control
serialization and instruction
fetch show cycles. See
Table A-2 for the bit
definitions.
NOTE: Changing the
instruction show cycle
programming starts to take
effect only from the second
instruction after the actual
mtspr to ICTRL.
These bits control
serialization and instruction
fetch show cycles. See
Table A-2 for the bit
definitions.
NOTE: Changing the
instruction show cycle
programming starts to take
effect only from the second
instruction after the actual
mtspr to ICTRL.
MPC562/MPC564 only.
Table A-2. ISCT_SER Bit Descriptions
Serialize
Control
(SER)
Instruction
Fetch
(ISCTL)
0
00
RCPU is fully serialized and show cycles will be performed for all fetched instructions (reset
value)
0
01
RCPU is fully serialized and show cycles will be performed for all changes in the program flow
0
10
RCPU is fully serialized and show cycles will be performed for all indirect changes in the
program flow
0
11
RCPU is fully serialized and no show cycles will be performed for fetched instructions
1
00
Illegal. This mode should not be selected.
1
01
RCPU is not serialized (normal mode) and show cycles will be performed for all changes in
the program flow
1
10
RCPU is not serialized (normal mode) and show cycles will be performed for all indirect
changes in the program flow
1
11
RCPU is not serialized (normal mode) and no show cycles will be performed for fetched
instructions
A.4
Functions Selected
Decompressor Class Configuration Registers (DCCR0-15)
The DCCR fields are programmed to achieve maximum flexibility in the vocabulary tables placement into
the two DECRAM banks under constraints, implied by hardware, which are:
• A bypass field must always be in the second field of the compressed instruction
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MPC562/MPC564 Compression Features
•
When fetching 32 bits of decompressed instruction from the DECRAM, each 16 bits will be read
from different RAM banks.
The DCCR registers should be programmed with data supplied by the code compression tool, in order to
be correlated with the compressed code.
,
MSB
0
Field
1
2
3
4
TP1LEN
5
6
7
8
9
10
TP2LEN
11
12
13
14
TP1BA
Reset
15
TP2BA
Unaffected
Addr DCCR01 0x2F + A000
DCCR1 0x2F + A004
DCCR2 0x2F + A008
DCCR3 0x2F + A00C
DCCR4
DCCR5
DCCR6
DCCR7
0x2F + A010
0x2F + A014
0x2F + A018
0x2F + A01C
DCCR8 0x2F + A020
DCCR9 0x2F + A024
DCCR10 0x2F + A028
DCCR11 0x2F + A02C
DCCR12
DCCR13
DCCR14
DCCR15
0x2F + A030
0x2F + A034
0x2F + A038
0x2F + A03C
LSB
16
17
Field
Reset
18
19
20
TP2BA
Unaffected
0
21
22
23
AS
DS
24
25
26
Unaffected
27
28
29
30
31
—
0000_0000
Figure A-14. Decompressor Class Configuration Registers1 (DCCRx)
1. The DCCR0 register is hard coded for the “bypass decompressor class.” Write accesses do not affect the DCCR0 register. The
DCCR0 register will always return 0x0000 0000 when read.
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MPC562/MPC564 Compression Features
Table A-3. DCCR0-DCCR15 Field Descriptions
Bits
Name
Description
0:3
TP1LEN
Length and Type of Table Pointer 1. This field’s value defines the length of the field that contains
a pointer to the first vocabulary table allocated for the class.
0x0 Empty field
0x1 Reserved
0x2 TP1 length is 2 bits
0x3 TP1 length is 3 bits
0x4 TP1 length is 4 bits
0x5 TP1 length is 5 bits
0x6 TP1 length is 6 bits
0x7 TP1 length is 7 bits
0x8 TP1 length is 8 bits
0x9 TP1 length is 9 bits
0xA to 0xFReserved
4:7
TP2LEN
Length and Type of Table Pointer 2. This field’s value defines the length of the field that contains
either a pointer to the second vocabulary table allocated for the class or a bypass field.
0x0 Empty field
0x1 Reserved
0x2 TP2 length is 2 bits
0x3 TP2 length is 3 bits
0x4 TP2 length is 4 bits
0x5 TP2 length is 5 bits
0x6 TP2 length is 6 bits
0x7 TP2 length is 7 bits
0x8 TP2 length is 8 bits
0x9 TP2 length is 9 bits
0xA Reserved
0xB TP2 field is a 0 bit compact bypass field
0xC TP2 field is a 10 bits compact bypass field
0xD TP2 field is a 15 bits compact bypass field
0xE TP2 field is a 16 bits bypass field
0xF Reserved.
8:14
TP1BA
Base address for vocabulary table in RAM Bank 1. This field specifies the base page address
of the class’ vocabulary table that resides in RAM Bank 1.
15:21
TP2BA
Base address for vocabulary table in RAM Bank 2. This field specifies the base page address
of the class’ vocabulary table that resides in RAM Bank 2.
22
AS
Address Swap specification
0 Address swap operation will not be performed for the class.
1 Address swap operation will be performed for the class
For further details concerning AS operation refer to Table A-4.
23
DS
Data swap specification
0 Data swap operation will not be performed for the class.
1 Data swap operation will be performed for the class.
For further details concerning DS operation refer to Table A-4.
24:31
—
Reserved
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MPC562/MPC564 Compression Features
Table A-4. Instruction Layout Encoding
Configuration
TP1
Configu
Points
ration
to RAM
Code
#
TP2BA Points
to
AS DS
RAM # Vocab. RAM # Vocab.
CLASS
1
Twin Segments Full
Compression
CLASS
2a
Twin Segments Full
Compression With
Swapped Vocabularies
(Vocabulary In RAM #2
For MSB Segment)
CLASS
2b
Left Segment
Compression, Right
Segment Bypassed,
Vocabulary In RAM #1
CLASS
3a
1
1
V1
—
—
0
Left Segment
Compression, Right
Segment Bypassed,
Vocabulary In RAM #2
CLASS
3b
2
—
—
2
V1
1
Left Segment Bypassed,
Right Segment
Compression,
Vocabulary In RAM #1
CLASS
4b
1
1
V2
—
—
0
Left Segment Bypassed,
Right Segment
Compression,
Vocabulary In RAM #2
CLASS
4a
2
—
—
2
V2
1
2
—
TP1BA Points
to
Single Segment Full
Compression
1
1 and 2
TP2
Points
to RAM
#
1
V1
2
V1
1
2
1
V2
V2
—
V2
2
V1
—
Compressed
Instruction
Layout
—
X11
0
X1 X2
1
X2 X1
X1 BP2
0
Bypass
X1 BP2
X2 BP2
1
X2 BP2
X1, X2 - pointers to vocabularies
BP - the bypassed data
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MPC562/MPC564 Compression Features
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Appendix B
Internal Memory Map
This appendix includes the following memory maps:
•
Table B-1. SPR (Special Purpose Registers)
•
Table B-2. UC3F Flash Array
•
Table B-3. DECRAM SRAM Array
•
Table B-4. BBC (Burst Buffer Controller Module)
•
Table B-5. USIU (Unified System Interface Unit)
•
Table B-6. CDR3 Flash Control Registers EEPROM (UC3F)
•
Table B-7. DPTRAM Control Registers
•
Table B-8. DPTRAM Memory Arrays
•
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B)
•
Table B-10. QADC64E A and B (Queued Analog-to-Digital Converter)
•
Table B-11. QSMCM (Queued Serial Multi-Channel Module)
•
Table B-12. Peripheral Pin Multiplexing (PPM) Module
•
Table B-13. MIOS14 (Modular Input/Output Subsystem)
•
Table B-14. TouCAN A, B and C (CAN 2.0B Controller)
•
Table B-15. UIMB (U-Bus to IMB Bus Interface)
•
Table B-16. CALRAM Control Registers
•
Table B-17. CALRAM Array
•
Table B-18. READI Module Registers
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-1
Internal Memory Map
Memory map tables use the notation shown below:
Notations Used in the Access Column
Notations Used in the Reset Column
S = Supervisor access only
— (em dash) = Untouched
U = User access
S = SRESET
T = Test access
H = HRESET
M = Module Reset
POR = Power-On Reset
U = Unchanged
X = Unknown
R = RSTI
In each table, the codes in the Reset column indicate which reset affects register values.
Table B-1. SPR (Special Purpose Registers)
Address
Access
Symbol
CR
U
CR
FPSCR
U
FPSCR
MSR
S
SPR 1
Register
Size
Reset
Condition State Register
See Section 3.7.4 for bit descriptions.
32
—
Floating-Point Status and Control Register
See Table 3-5 for bit descriptions.
32
—
MSR
Machine State Register
See Table 3-11 for bit descriptions.
32
—
U
XER
Integer Exception Register
See Table 3-10 for bit descriptions.
32
—
SPR 8
U
LR
Link Register
See Section 3.7.6 for bit descriptions.
32
—
SPR 9
U
CTR
Count Register
See Section 3.7.7 for bit descriptions.
32
—
SPR 18
S
DSISR
DAE/Source Instruction Service Register
See Section 3.9.2 for bit descriptions.
32
—
SPR 19
S
DAR
Data Address Register
See Section 3.9.3 for bit descriptions.
32
—
SPR 22
S
DEC
Decrementer Register
See Section 3.9.5 for more information.
32
POR
SPR 26
S
SRR0
Machine Status Save/Restore Register 0
See Section 3.9.6 for bit descriptions.
32
—
SPR 27
S
SRR1
Machine Status Save/Restore Register1
See Section 3.9.7 for bit descriptions.
32
—
SPR 80
S
EIE
External Interrupt Enable
See Section 3.9.10.1 for bit descriptions.
32
—
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Freescale Semiconductor
Internal Memory Map
Table B-1. SPR (Special Purpose Registers) (continued)
Address
Access
Symbol
SPR 81
S
EID
SPR 82
S
NRI
SPR 144 —
SPR 147
—
Register
Size
Reset
External Interrupt Disable
See Section 3.9.10.1 for bit descriptions.
32
—
Non-Recoverable Interrupt Register
See Section 3.9.10.1 for bit descriptions.
32
—
32
H
CMPA — CMPD Comparator A-D Value Register
See Table 23-17 for bit descriptions.
SPR 148
D, S
ECR
Exception Cause Register
See Table 23-18 for bit descriptions.
32
—
SPR 149
D, S
DER
Debug Enable Register
See Table 23-19 for bit descriptions.
32
—
SPR 150
D, S
COUNTA
Breakpoint Counter A Value and Control
Register
See Table 23-20 for bit descriptions.
32
—
SPR 151
D, S
COUNTB
Breakpoint Counter B Value and Control
Register
See Table 23-21 for bit descriptions.
32
—
SPR 152 —
SPR 153
—
CMPE — CMPF Comparator E-F Value Register
See Table 23-22 for bit descriptions.
32
—
SPR 154 —
SPR 155
—
CMPG — CMPH Comparator G-H Value Register
See Table 23-23 for bit descriptions.
32
—
SPR 156
D, S
LCTRL1
L-bus Support Control Register 1
See Table 23-24 for bit descriptions.
32
S
SPR 157
D, S
LCTRL2
L-bus Support Control Register 2
See Table 23-25 for bit descriptions.
32
S
SPR 158
D, S
ICTRL
I-bus Support Control Register
See Table 23-26 for bit descriptions.
32
S
SPR 159
D, S
BAR
Breakpoint Address Register
See Table 23-28 for bit descriptions.
32
—
SPR 268, 269
U
TBL/TBU
Time Base (Read Only) Register
See Section 6.2.2.4.2 for bit descriptions.
32
—
SPR 272 —
SPR 275
S
SPRG0 —
SPRG3
General Special-Purpose Registers 0-3
See Table 3-13 for bit descriptions.
32
—
SPR 284, 285
S
TBL/TBU
Time Base (Write Only) Register
See Section 6.2.2.4.2 for bit descriptions.
32
—
SPR 287
S
PVR
Processor Version Register
See Table 3-14 for bit descriptions.
32
—
SPR 1022
S
FPECR
Floating-Point Exception Cause Register
See Table 3-16 for bit descriptions.
32
S
SPR 528
S
MI_GRA
MI Global Region Attribute Register
See Table 4-8 for bit descriptions.
32
—
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-3
Internal Memory Map
Table B-1. SPR (Special Purpose Registers) (continued)
Address
Access
Symbol
SPR 529
S
EIBADR
SPR 536
S
SPR 560
Register
Size
Reset
External Interrupt Relocation Table Base
Address Register
See Table 4-9 for bit descriptions.
32
—
L2U_GRA
L2U Global Region Attribute Register
See Table 11-10 for bit descriptions.
32
—
S
BBCMCR
BBC Module Configuration Register
See Table 4-4 for bit descriptions.
32
H
SPR 568
S
L2U_MCR
L2U Module Configuration Register
See Table 11-7 for bit descriptions.
32
—
SPR 630
S
DPDR
Development Port Data Register
See Section 23.4.6 for bit descriptions.
32
—
SPR 638
S
IMMR
Internal Memory Mapping Register
See Table 6-12 for bit descriptions.
32
H
SPR 784 –
787
S
MI_RBAx
MI Region x Base Address Register
See Table 4-5 for bit descriptions.
32
—
SPR 792 –
795
S
L2U_RBAx
L2U Region x Base Address Register
See Table 11-8 for bit descriptions.
32
—
SPR 816 –
819
S
MI_RAx
MI Region x Attribute Register
See Table 4-6 for bit descriptions.
32
—
SPR 824 –
827
S
L2U_RAx
L2U Region x Attribute Register
See Table 11-9 for bit descriptions.
32
—
Table B-2. UC3F Flash Array
Address
Access
Symbol
0x00 0000 —
0x07 FFFF
U,S
UC3F
Register
UC3F Flash Array
Size
Reset
32
—
Size
Reset
32
—
Size
Reset
Table B-3. DECRAM SRAM Array
Address
Access
Symbol
0x2F 8000 —
0x2F 87FF
U,S
DECRAM
Register
DECRAM SRAM
Table B-4. BBC (Burst Buffer Controller Module)
Address
Access
Symbol
Register
0x2F A000
S (read only)1
DCCR0
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A004
S
DCCR1
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
MPC561/MPC563 Reference Manual, Rev. 1.2
B-4
Freescale Semiconductor
Internal Memory Map
Table B-4. BBC (Burst Buffer Controller Module) (continued)
Address
Access
Symbol
0x2F A008
S
DCCR2
0x2F A00C
S
0x2F A010
Size
Reset
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
DCCR3
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
S
DCCR4
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A014
S
DCCR5
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A018
S
DCCR6
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A01C
S
DCCR7
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A020
S
DCCR8
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A024
S
DCCR9
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A028
S
DCCR10
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A02C
S
DCCR11
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A030
S
DCCR12
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A034
S
DCCR13
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A038
S
DCCR14
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
0x2F A03C
S
DCCR15
Decompressor Class Configuration Register
See Table A-3 for bit descriptions.
32
—
Size
Reset
1
Register
Always reads 0x0000 0000.
Table B-5. USIU (Unified System Interface Unit)
Address
Access
Symbol
Register
0x2F C000
U1
SIUMCR
SIU Module Configuration Register
See Table 6-7 for bit descriptions.
32
H
0x2F C004
U2
SYPCR
System Protection Control Register
See Table 6-15 for bit descriptions.
32
H
0x2F C008
—
—
Reserved
—
—
0x2F C00E
U,
write only
SWSR
Software Service Register
See Table 6-16 for bit descriptions.
16
S
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Freescale Semiconductor
B-5
Internal Memory Map
Table B-5. USIU (Unified System Interface Unit) (continued)
Address
Access
Symbol
0x2F C010
U
SIPEND
0x2F C014
U
SIMASK
0x2F C018
U
0x2F C01C
Register
Size
Reset
Interrupt Pending Register
See Section 6.2.2.2.1 for bit descriptions.
32
S
Interrupt Mask Register
SIMASK is a 32-bit read/write register. Each bit
in the register corresponds to an interrupt
request bit in the SIPEND register.
32
S
SIEL
Interrupt Edge Level Mask.
See Section 6.2.2.2.7 for bit descriptions.
32
H
U,
read only
SIVEC
Interrupt Vector.
See Section 6.2.2.2.8 for bit descriptions.
32
—
0x2F C020
U
TESR
Transfer Error Status Register
See Table 6-17 for bit descriptions.
32
S
0x2F C024
U
SGPIODT1
USIU General-Purpose I/O Data Register 1
See Table 6-23 for bit descriptions.
32
H
0x2F C028
U
SGPIODT2
USIU General-Purpose I/O Data Register 2
See Table 6-24 for bit descriptions.
32
H
0x2F C02C
U
SGPIOCR
USIU General-Purpose I/O Control Register
See Table 6-25 for bit descriptions.
32
H
0x2F C030
U
EMCR
External Master Mode Control Register
See Table 6-13 for bit descriptions.
32
H
0x2F C038
U
PDMCR2
Pads Module Configuration Register 2
See Table 2-6 for bit descriptions.
32
H
0x2F C03C
U
PDMCR
Pads Module Configuration Register
See Table 2-5 for bit descriptions.
32
H
0x2F C040 —
0x2F C044
U
SIPEND2 —
SIPEND3
Interrupt Pending Registers 2 and 3
See Section 6.2.2.2.1 for bit descriptions.
32
S
0x2F C048 —
0x2F C04C
U
SIMASK2 —
SIMASK3
Interrupt Mask Register and Interrupt Mask
Registers 2 and 3
See Section 6.2.2.2.9 for bit descriptions.
32
S
0x2F C050 —
0x2F C054
U
32
S
0x2F C0FC —
0x2F C0FF
—
—
—
SISR2 — SISR3 SISR2 and SISR3 Registers
See Section 6.2.2.2.9 for bit descriptions.
—
Reserved
Memory Controller Registers
0x2F C100
U
BR0
Base Register 0.
See Table 10-8 for bit descriptions.
32
H
0x2F C104
U
OR0
Option Register 0.
See Table 10-10 for bit descriptions.
32
H
0x2F C108
U
BR1
Base Register 1.
See Table 10-8 for bit descriptions.
32
H
MPC561/MPC563 Reference Manual, Rev. 1.2
B-6
Freescale Semiconductor
Internal Memory Map
Table B-5. USIU (Unified System Interface Unit) (continued)
Address
Access
Symbol
0x2F C10C
U
OR1
0x2F C110
U
0x2F C114
Register
Size
Reset
Option Register 1.
See Table 10-10 for bit descriptions.
32
H
BR2
Base Register 2.
See Table 10-8 for bit descriptions.
32
H
U
OR2
Option Register 2.
See Table 10-10 for bit descriptions.
32
H
0x2F C118
U
BR3
Base Register 3.
See Table 10-8 for bit descriptions.
32
H
0x2F C11C
U
OR3
Option Register 3.
See Table 10-10 for bit descriptions.
32
H
0x2F C120 –
0x2F C13C
—
—
Reserved
—
—
0x2F C140
U
DMBR
Dual-Mapping Base Register.
See Table 10-11 for bit descriptions.
32
H
0x2F C144
U
DMOR
Dual-Mapping Option Register.
See Table 10-12 for bit descriptions.
32
H
0x2F C148 –
0x2F C174
—
—
Reserved
—
—
0x2F C178
U
MSTAT
Memory Status.
See Table 10-7 for bit descriptions.
16
H
System Integration Timers
0x2F C200
U3
TBSCR
Time Base Status and Control.
See Table 6-18 for bit descriptions.
16
H
0x2F C204
U3
TBREF0
Time Base Reference 0.
See Section 6.2.2.4.3 for bit descriptions.
32
U
0x2F C208
U3
TBREF1
Time Base Reference 1.
See Section 6.2.2.4.3 for bit descriptions.
32
U
0x2F C20C –
0x2F C21C
—
—
Reserved
—
—
0x2F C220
U4
RTCSC
Real-Time Clock Status and Control.
See Table 6-19 for bit descriptions.
16
H
0x2F C224
U4
RTC
Real-Time Clock.
See Section 6.2.2.4.6 for bit descriptions.
32
U
0x2F C228
T4
RTSEC
Real-Time Alarm Seconds. Reserved
32
—
0x2F C22C
U4
RTCAL
Real-Time Alarm.
See Section 6.2.2.4.7 for bit descriptions.
32
U
0x2F C230 –
0x2F C23C
—
—
Reserved
—
—
0x2F C240
U3
PISCR
PIT Status and Control.
See Table 6-20 for bit descriptions.
16
H
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-7
Internal Memory Map
Table B-5. USIU (Unified System Interface Unit) (continued)
Address
Access
Symbol
0x2F C244
U3
PITC
0x2F C248
U,
read only
PITR
—
—
0x2F C24C –
0x2F C27C
Register
Size
Reset
PIT Count.
See Table 6-21 for bit descriptions.
32
(half reserved)
U
PIT Register.
See Table 6-22 for bit descriptions.
32
(half reserved)
U
—
—
System Clock Control Register.
See Table 8-9 for bit descriptions.
32
H
PLL Low Power and Reset Control Register.
See Table 8-11 for bit descriptions.
32
H
Reserved
Clocks and Reset
0x2F C280
U2
SCCR
0x2F C284
U3,5,6
PLPRCR
0x2F C288
U3
RSR
Reset Status Register.
See Table 7-3 for bit descriptions.
16
POR
0x2F C28C
U
COLIR
Change of Lock Interrupt Register.
See Table 8-12 for bit descriptions.
16
U
0x2F C290
U
VSRMCR
IRAMSTBY Control Register.
See Table 8-13 for bit descriptions.
16
U
0x2F C294 –
0x2F C2FC
—
—
Reserved
—
—
System Integration Timer Keys
0x2F C300
U
TBSCRK
Time Base Status and Control Key.
See Table 8-8 for bit descriptions.
32
POR
0x2F C304
U
TBREF0K
Time Base Reference 0 Key.
See Table 8-8 for bit descriptions.
32
POR
0x2F C308
U
TBREF1K
Time Base Reference 1 Key.
See Table 8-8 for bit descriptions.
32
POR
0x2F C30C
U
TBK
Time Base and Decrementer Key.
See Table 8-8 for bit descriptions.
32
POR
0x2F C310 –
0x2F C31C
—
—
Reserved
—
—
0x2F C320
U
RTCSCK
Real-Time Clock Status and Control Key.
See Table 8-8 for bit descriptions.
32
POR
0x2F C324
U
RTCK
Real-Time Clock Key.
See Table 8-8 for bit descriptions.
32
POR
0x2F C328
U
RTSECK
Real-Time Alarm Seconds Key.
See Table 8-8 for bit descriptions.
32
POR
0x2F C32C
U
RTCALK
Real-Time Alarm Key.
See Table 8-8 for bit descriptions.
32
POR
0x2F C330 –
0x2F C33C
—
—
Reserved
—
—
MPC561/MPC563 Reference Manual, Rev. 1.2
B-8
Freescale Semiconductor
Internal Memory Map
Table B-5. USIU (Unified System Interface Unit) (continued)
Address
Access
Symbol
0x2F C340
U
PISCRIK
0x2F C344
U
PITCK
0x2F C348 –
0x2F C37C
—
—
Register
Size
Reset
PIT Status and Control Key.
See Table 8-8 for bit descriptions.
32
POR
PIT Count Key.
See Table 8-8 for bit descriptions.
32
POR
Reserved
—
—
System Clock Control Key.
See Table 8-8 for bit descriptions.
32
POR
PLL Low-Power and Reset Control Register Key.
See Table 8-8 for bit descriptions.
32
POR
Reset Status Register Key.
See Table 8-8 for bit descriptions.
32
POR
Reserved
—
—
32
S
Clocks and Reset Keys
0x2F C380
U
SCCRK
0x2F C384
U
PLPRCRK
0x2F C388
U
RSRK
0x2F C38C –
0x2F C3F8
—
—
Test Register
0x2F C3FC
1
2
3
4
5
6
S
SIUTST
SIU Test Register
Entire register is locked if bit 15 (DLK) is set.
Write once after power on reset (POR).
Must use the key register to unlock if it has been locked by a key register, see Section 8.8.3.2, “Keep-Alive Power Registers
Lock Mechanism.”
Locked after Power on Reset (POR). A write of 0x55CCAA33 must performed to the key register to unlock. See
Section 8.8.3.2, “Keep-Alive Power Registers Lock Mechanism.”
Can have bits 0:11 (MF bits) write-protected by setting bit 4 (MFPDL) in the SCCR register to 1. Bit 21 (CSRC) and bits 22:23
(LPM) can be locked by setting bit 5 (LPML) of the SCCR register to 1.
Bit 24 (CSR) is write-once after soft reset.
Table B-6. CDR3 Flash Control Registers EEPROM (UC3F)1
Address
Access
Symbol
Register
Size
Reset
C3F EEPROM Configuration Register.
See Table 21-3 for bit descriptions.
32
POR, H
C3F EEPROM Extended Configuration Register.
See Table 21-4 for bit descriptions.
32
POR, H
C3F EEPROM High Voltage Control Register.
See Table 21-5 for bit descriptions.
32
POR, H
C3F
0x2F C800
S
UC3FMCR
0x2F C804
S
UC3FMCRE
0x2F C808
S
UC3FCTL
1
Available on the MPC563/MPC564 only,
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-9
Internal Memory Map
Table B-7. DPTRAM Control Registers
Address
Access
Symbol
Register
Size
Reset
DPTRAM Control
0x30 0000
U, S1
DPTMCR
DPTRAM Module Configuration Register.
See Table 20-2 for bit descriptions.
16
S
0x30 0002
S
DPTTCR
Test Configuration Register.
16
S
0x30 0004
S
RAMBAR
RAM Array Base Address Register.
See Table 20-3 for bit descriptions.
16
S
0x30 0006
S
MISRH
Multiple Input Signature Register High.
16
S
0x30 0008
S
MISRL
Multiple Input Signature Register Low.
16
S
0x30 000A
S
MISCNT
MISC Counter Register.
16
S
1
Access to the DPTRAM array through the IMB3 bus is disabled once bit 5 (EMU) of either TPUMCR_A or TPUMCR_B
is set.
Table B-8. DPTRAM Memory Arrays
Address
Access
Symbol
0x30 2000 —
0x30 37FF
U, S1
DPTRAM
1
Register
DPTRAM Memory Array
Size
Reset
16
—
Access to the DPTRAM array through the IMB3 bus is disabled once bit 5 (EMU) of either TPUMCR_A or TPUMCR_B
is set.
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B)
Address
Access
Symbol
Register
Size
Reset
16 only
S, M
TPU3_A Test Configuration Register.
16
S, M
TPU3_A
(Note: Bit descriptions apply to TPU3_B as well)
0x30 4000
S1
TPUMCR_A
0x30 4002
T
TCR_A
0x30 4004
T
DSCR_A
TPU3_A Development Support Control Register.
See Table 19-8 for bit descriptions.
162
S, M
0x30 4006
T
DSSR_A
TPU3_A Development Support Status Register.
See Table 19-9 for bit descriptions.
162
S, M
0x30 4008
S
TICR_A
TPU3_A Interrupt Configuration Register.
See Table 19-10 for bit descriptions.
162
S, M
0x30 400A
S
CIER_A
TPU3_A Channel Interrupt Enable Register.
See Table 19-11 for bit descriptions.
162
S, M
0x30 400C
S
CFSR0_A
TPU3_A Channel Function Selection Register 0.
See Table 19-12 for bit descriptions.
162
S, M
TPU3_A Module Configuration Register.
See Table 19-7 for bit descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
B-10
Freescale Semiconductor
Internal Memory Map
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B) (continued)
Address
Access
Symbol
Register
Size
Reset
0x30 400E
S
CFSR1_A
TPU3_A Channel Function Selection Register 1.
See Table 19-12 for bit descriptions.
162
S, M
0x30 4010
S
CFSR2_A
TPU3_A Channel Function Selection Register 2.
See Table 19-12 for bit descriptions.
162
S, M
0x30 4012
S
CFSR3_A
TPU3_A Channel Function Selection Register 3.
See Table 19-12 for bit descriptions.
162
S, M
0x30 4014
S/U3
HSQR0_A
TPU3_A Host Sequence Register 0.
See Table 19-13 for bit descriptions.
162
S, M
0x30 4016
S/U3
HSQR1_A
TPU3_A Host Sequence Register 1.
See Table 19-13 for bit descriptions.
162
S, M
0x30 4018
S/U3
HSRR0_A
TPU3_A Host Service Request Register 0.
See Table 19-14 for bit descriptions.
162
S, M
0x30 401A
S/U3
HSRR1_A
TPU3_A Host Service Request Register 1.
See Table 19-14 for bit descriptions.
162
S, M
0x30 401C
S
CPR0_A
TPU3_A Channel Priority Register 0.
See Table 19-15 for bit descriptions.
162
S, M
0x30 401E
S
CPR1_A
TPU3_A Channel Priority Register 1.
See Table 19-15 for bit descriptions.
162
S, M
0x30 4020
S
CISR_A
TPU3_A Channel Interrupt Status Register.
See Table 19-17 for bit descriptions.
16
S, M
0x30 4022
T
LR_A
TPU3_A Link Register4
162
S, M
0x30 4024
T
SGLR_A
TPU3_A Service Grant Latch Register4
162
S, M
0x30 4026
T
DCNR_A
TPU3_A Decoded Channel Number Register4
162
S, M
0x30 4028
S5
TPUMCR2_A
TPU3_A Module Configuration Register 2.
See Table 19-18 for bit descriptions.
162
S, M
0x30 402A
S
TPUMCR3_A
TPU3_A Module Configuration Register 3.
See Table 19-21 for bit descriptions.
162
S, M
0x30 402C
T
ISDR_A
TPU3_A Internal Scan Data Register
16, 322
—
0x30 402E
T
ISCR_A
TPU3_A Internal Scan Control Register
16, 322
—
0x30 4100 –
0x30 410F
S/U3
—
TPU3_A Channel 0 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 4110 –
0x30 411F
S/U3
—
TPU3_A Channel 1 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 4120 –
0x30 412F
S/U3
—
TPU3_A Channel 2 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 4130 –
0x30 413F
S/U3
—
TPU3_A Channel 3 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 4140 –
0x30 414F
S/U3
—
TPU3_A Channel 4 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-11
Internal Memory Map
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B) (continued)
Address
Access
Symbol
0x30 4150 –
0x30 415F
S/U3
—
0x30 4160 –
0x30 416F
S/U3
0x30 4170 –
0x30 417F
Register
Size
Reset
TPU3_A Channel 5 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
—
TPU3_A Channel 6 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
S/U3
—
TPU3_A Channel 7 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 4180 –
0x30 418F
S/U3
—
TPU3_A Channel 8 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 4190 –
0x30 419F
S/U3
—
TPU3_A Channel 9 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 41A0 –
0x30 41AF
S/U3
—
TPU3_A Channel 10 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 41B0 –
0x30 41BF
S/U3
—
TPU3_A Channel 11 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 41C0 –
0x30 41CF
S/U3
—
TPU3_A Channel 11 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 41D0 –
0x30 41DF
S/U3
—
TPU3_A Channel 11 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 41E0 –
0x30 41EF
S/U3
—
TPU3_A Channel 14 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
0x30 41F0 –
0x30 41FF
S/U3
—
TPU3_A Channel 15 Parameter Registers.
See Section 19.4.15 for more information.
16, 322
—
16 only
S, M
TPU3_B Test Configuration Register
16
S, M
TPU3_B Development Support Control Register
162
S, M
S, M
TPU3_B
0x30 44001
S1
TPUMCR_B
0x30 4402
T
TCR_B
0x30 4404
T
DSCR_B
TPU3_B Module Configuration Register
0x30 4406
T
DSSR_B
TPU3_B Development Support Status Register
162
0x30 4408
S
TICR_B
TPU3_B Interrupt Configuration Register
162
S, M
TPU3_B Channel Interrupt Enable Register
162
S, M
TPU3_B Channel Function Selection Register 0
162
S, M
S, M
0x30 440A
S
CIER_B
0x30 440C
S
CFSR0_B
0x30 440E
S
CFSR1_B
TPU3_B Channel Function Selection Register 1
162
0x30 4410
S
CFSR2_B
TPU3_B Channel Function Selection Register 2
162
S, M
S, M
0x30 4412
S
CFSR3_B
TPU3_B Channel Function Selection Register 3
162
0x30 4414
S/U3
HSQR0_B
TPU3_B Host Sequence Register 0
162
S, M
0x30 4416
S/U3
HSQR1_B
TPU3_B Host Sequence Register 1
162
S, M
0x30 4418
S/U3
HSRR0_B
TPU3_B Host Service Request Register 0
162
S, M
0x30 441A
S/U3
TPU3_B Host Service Request Register 1
162
S, M
HSRR1_B
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
Internal Memory Map
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B) (continued)
Address
Access
Symbol
0x30 441C
S
CPR0_B
0x30 441E
S
0x30 4420
Register
Size
Reset
TPU3_B Channel Priority Register 0
162
S, M
CPR1_B
TPU3_B Channel Priority Register 1
162
S, M
S
CISR_B
TPU3_B Channel Interrupt Status Register
16
S, M
0x30 4422
T
LR_B
TPU3_B Link Register
162
S, M
0x30 4424
T
SGLR_B
TPU3_B Service Grant Latch Register
162
S, M
0x30 4426
T
DCNR_B
TPU3_B Decoded Channel Number Register
162
S, M
0x30 4428
S4
TPUMCR2_B
TPU3_B Module Configuration Register 2
162
S, M
0x30 442A
S
TPUMCR3_B
TPU3_B Module Configuration Register 3
16, 322
S, M
0x30 442C
T
ISDR_B
TPU3_B Internal Scan Data Register
16, 322
—
0x30 442E
T
ISCR_B
TPU3_B Internal Scan Control Register
16, 322
—
0x30 4500 –
0x30 450F
S/U3
—
TPU3_B Channel 0 Parameter Registers
16, 322
—
0x30 4510 –
0x30 451F
S/U3
—
TPU3_B Channel 1 Parameter Registers
16, 322
—
0x30 4520 –
0x30 452F
S/U3
—
TPU3_B Channel 2 Parameter Registers
16, 322
—
0x30 4530 –
0x30 453F
S/U3
—
TPU3_B Channel 3 Parameter Registers
16, 322
—
0x30 4540 –
0x30 454F
S/U3
—
TPU3_B Channel 4 Parameter Registers
16, 322
—
0x30 4550 –
0x30 455F
S/U3
—
TPU3_B Channel 5 Parameter Registers
16, 322
—
0x30 4560 –
0x30 456F
S/U3
—
TPU3_B Channel 6 Parameter Registers
16, 322
—
0x30 4570 –
0x30 457F
S/U3
—
TPU3_B Channel 7 Parameter Registers
16, 322
—
0x30 4580 –
0x30 458F
S/U3
—
TPU3_B Channel 8 Parameter Registers
16, 322
—
0x30 4590 –
0x30 459F
S/U3
—
TPU3_B Channel 9 Parameter Registers
16, 322
—
0x30 45A0 –
0x30 45AF
S/U3
—
TPU3_B Channel 10 Parameter Registers
16, 322
—
0x30 45B0 –
0x30 45BF
S/U3
—
TPU3_B Channel 11 Parameter Registers
16, 322
—
0x30 45C0 –
0x30 45CF
S/U3
—
TPU3_B Channel 11 Parameter Registers
16, 322
—
0x30 45D0 –
0x30 45DF
S/U3
—
TPU3_B Channel 11 Parameter Registers
16, 322
—
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-13
Internal Memory Map
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B) (continued)
Address
Access
Symbol
0x30 45E0 –
0x30 45EF
S/U3
—
0x30 45F0 –
0x30 45FF
S/U3
—
1
2
3
4
5
Register
Size
Reset
TPU3_B Channel 14 Parameter Registers
16, 322
—
TPU3_B Channel 15 Parameter Registers
162
—
Bit 10 (TPU3) and bit 11 (T2CSL) are write-once. Bits 1:2 (TCR1P) and bits 3:4 (TCR2P) are write-once if PWOD is
not set in the TPUMCR3 register. This register cannot be accessed with a 32-bit read. It can only be accessed with an
8- or 16-bit read.
Some TPU registers can only be read or written with 16- or 32-bit accesses. 8-bit accesses are not allowed.
S/U = Supervisor accessible only if SUPV = 1 or unrestricted if SUPV = 0. Unrestricted registers allow both user and
supervisor access. The SUPV bit is in the TPUMCR register.
TPU code development (Debug) register
Bits 9:10 (ETBANK), 14 (T2CF), and 15 (DTPU) are write-once.
Table B-10. QADC64E A and B (Queued Analog-to-Digital Converter)
Address
Access
Symbol
Register
Size
Reset
16
S
QADC64 Test Register.
16
S
Interrupt Register.
See Section 13.2.2 and Section 14.3.2 for bit
descriptions.
16
S
QADC_A
(Note: Bit descriptions apply to QADC_B as well)
0x30 4800
S
QADC64MCR_A QADC64 Module Configuration Register.
See Table 13-5 and Table 14-5 for bit
descriptions.
0x30 4802
S
QADC64TST
0x30 4804
S
QADC64INT_A
0x30 4806
S/U
PORTQA_A/
PORTQB_A
Port A and Port B Data.
See Table 1-9 and Table 14-8 for bit
descriptions.
16
U
0x30 4808
S/U
DDRQA_A/
DDRQB_A
Port A Data and Port B Direction Register.
See Section 13.3.4 and Section 14.3.4 for
more information.
16
S
0x30 480A
S/U
QACR0_A
QADC64 Control Register 0.
See Table 13-9 and Table 14-9 for bit
descriptions.
16
S
0x30 480C
S/U1
QACR1_A
QADC64 Control Register 1.
See Table 13-10 and Table 14-11 for bit
descriptions.
16
S
0x30 480E
S/U1
QACR2_A
QADC64 Control Register 2.
See Table 13-12 and Table 14-13 for bit
descriptions.
16
S
0x30 4810
S/U
QASR0_A
QADC64 Status Register 0.
See Table 13-14 and Table 14-15 for bit
descriptions.
16
S
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Freescale Semiconductor
Internal Memory Map
Table B-10. QADC64E A and B (Queued Analog-to-Digital Converter) (continued)
Address
Access
Symbol
S/U
QASR1_A
0x30 4814 –
0x30 49FE
—
—
0x30 4A00 –
0x30 4A7E
S/U
CCW_A
0x30 4A80 –
0x30 4AFE
S/U
0x30 4B00 –
0x30 4B7E
0x30 4B80 –
0x30 4BFE
0x30 4812
Register
Size
Reset
QADC64 Status Register 1.
See Table 13-17 and Table 14-18 for bit
descriptions.
16
S
Reserved
—
—
Conversion Command Word Table.
See Table 13-18 and Table 14-19 for bit
descriptions.
16
U
RJURR_A
Result Word Table
Right-Justified, Unsigned Result Register.
See Section 13.3.10 and Section 14.3.10 for
bit descriptions.
16
X
S/U
LJSRR_A
Result Word Table
Left-Justified, Signed Result Register.
See Section 13.3.10 and Section 14.3.10 for
bit descriptions.
16
X
S/U
LJURR_A
Result Word Table
Left-Justified, Unsigned Result Register.
See Section 13.3.10 and Section 14.3.10 for
bit descriptions.
16
X
QADC_B
0x30 4C00
S
QADC64MCR_B QADC64 Module Configuration Register
16
S
0x30 4C02
T
QADC64TEST_ QADC64 Test Register
B
16
—
0x30 4C04
S
QADC64INT_B
Interrupt Register
16
S
0x30 4C06
S/U
PORTQA_B/
PORTQB_B
Port A and Port B Data
16
U
0x30 4C08
S/U
DDRQA_B/
DDRQB_B
Port A Data and Port B Direction Register
16
S
0x30 4C0A
S/U
QACR0_B
QADC64 Control Register 0
16
S
0x30 4C0C
S/U1
QACR1_B
QADC64 Control Register 1
16
S
0x30 4C0E
S/U1
QACR2_B
QADC64 Control Register 2
16
S
0x30 4C10
S/U
QASR0_B
QADC64 Status Register 0
16
S
0x30 4C12
S/U
QASR1_B
QADC64 Status Register 1
16
S
0x30 4C14 –
0x30 4DFE
—
—
Reserved
—
—
0x30 4E00 –
0x30 4E7E
S/U
CCW_B
Conversion Command Word Table
16
U
0x30 4E80 –
0x30 4EFE
S/U
RJURR_B
Result Word Table.
Right-Justified, Unsigned Result Register.
16
X
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-15
Internal Memory Map
Table B-10. QADC64E A and B (Queued Analog-to-Digital Converter) (continued)
Address
Access
Symbol
0x30 4F00 –
0x30 4F7E
S/U
LJSRR_B
0x30 4F80 –
0x30 4FFE
S/U
LJURR_B
1
Register
Size
Reset
Result Word Table.
Left-Justified, Signed Result Register.
16
X
Result Word Table.
Left-Justified, Unsigned Result Register.
16
X
Size
Reset
QSMCM Module Configuration Register.
See Table 15-4 for bit descriptions.
16
S
QSMCM Test Register
16
S
Bit 3 (SSEx) is readable in test mode only.
Table B-11. QSMCM (Queued Serial Multi-Channel Module)
Address
Access
Symbol
Register
QSMCM
0x30 5000
S
QSMCMMCR
0x30 5002
T
QTEST
0x30 5004
S
QDSCI_IL
Dual SCI Interrupt Level.
See Table 15-5 for bit descriptions.
16
S
0x30 5006
S
QSPI_IL
Queued SPI Interrupt Level.
See Table 15-6 for bit descriptions.
16
S
0x30 5008
S/U
SCC1R0
SCI1 Control Register 1.
See Table 15-24 for bit descriptions.
16
S
0x30 500A
S/U
SCC1R1
SCI1 Control Register 1.
See Table 15-25 for bit descriptions.
16
S
0x30 500C
S/U
SC1SR
SCI1 Status Register.
See Table 15-26 for bit descriptions.
16
S
0x30 500E
S/U
SC1DR
SCI1 Data Register.
See Table 15-27 for bit descriptions.
16
S
—
—
Reserved
—
—
0x30 5014
S/U
PORTQS
QSMCM Port QS Data Register.
See Section 15.5.2 for bit descriptions.
16
S
0x30 5016
S/U
PQSPAR/
DDRQST
QSMCM Port QS PIn Assignment Register/
QSMCM Port QS Data Direction Register.
See Section 15.5.2 for bit descriptions.
16
S
0x30 5018
S/U
SPCR0
QSPI Control Register 0.
See Table 15-13 for bit descriptions.
16
S
0x30 501A
S/U
SPCR1
QSPI Control Register 1.
See Table 15-15 for bit descriptions.
16
S
0x30 501C
S/U
SPCR2
QSPI Control Register 2.
See Table 15-16 for bit descriptions.
16
S
0x30 501E
S/U
SPCR3
QSPI Control Register 3.
See Table 15-17 for bit descriptions.
8
S
0x30 5010 —
0x30 5012
MPC561/MPC563 Reference Manual, Rev. 1.2
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Freescale Semiconductor
Internal Memory Map
Table B-11. QSMCM (Queued Serial Multi-Channel Module) (continued)
Address
Access
Symbol
0x30 501F
S/U
SPSR
0x30 5020
S/U
0x30 5022
Size
Reset
QSPI Status Register 3.
See Table 15-18 for bit descriptions.
8
S
SCC2R0
SCI2 Control Register 0.
See Table 15-24 for bit descriptions.
16
S
S/U
SCC2R1
SCI2 Control Register 1.
See Table 15-25 for bit descriptions.
16
S
0x30 5024
S/U
SC2SR
SCI2 Status Register.
See Table 15-26 for bit descriptions.
16
S
0x30 5026
S/U
SC2DR
SCI2 Data Register.
See Table 15-27 for bit descriptions.
16
S
0x30 5028
S/U1
QSCI1CR
QSCI1 Control Register.
See Table 15-32 for bit descriptions.
16
S
0x30 502A
S/U2
QSCI1SR
QSCI1 Status Register.
See Table 15-33 for bit descriptions.
16
S
0x30 502C –
0x30 504A
S/U
SCTQ
Transmit Queue Locations
16
S
0x30 504C –
0x30 506A
S/U
SCRQ
Receive Queue Locations
16
S
0x30 506C –
0x30 513F
—
—
Reserved
—
—
0x30 5140 –
0x30 517F
S/U
RECRAM
Receive Data RAM
16
S
0x30 5180 –
0x30 51BF
S/U
TRAN.RAM
Transmit Data RAM
16
S
0x30 51C0 –
0x30 51DF
S/U
COMD.RAM
Command RAM
16
S
1
2
Register
Bits 0–3 writeable only in test mode, otherwise read only.
Bits 3–11 writeable only in test mode, otherwise read only.
Table B-12. Peripheral Pin Multiplexing (PPM) Module
Address
Access
Symbol
0x30 5C00
S/U
PPMMCR
0x30 5C04
S/U
0x30 5C06
0x30 5C08
Register
Size
Reset
PPM Module Configuration Register
See Table 18-2 for bit descriptions.
16
S
PPMPCR
PPM Contol Register
See Table 18-3 for bit descriptions.
16
S
S/U
TX_CONFIG_1
Transmit Configuration Register 1
See Table 18-6 for channel settings.
16
S
S/U
TX_CONFIG_2
Transmit Configuration Register 2
See Table 18-6 for channel settings.
16
S
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-17
Internal Memory Map
Table B-12. Peripheral Pin Multiplexing (PPM) Module (continued)
Address
Access
Symbol
0x30 5C0E
S/U
RX_CONFIG_1
0x30 5C10
S/U
RX_CONFIG_2
0x30 5C16
S/U
0x30 5C1A
Register
Size
Reset
Receive Configuration Register 1
See Table 18-6 for channel settings.
16
S
Receive Configuration Register 2
See Table 18-6 for channel settings.
16
S
RX_DATA
Receive Data Register
See Section 18.4.5 for bit descriptions.
16
S
S/U
RX_SHIFTER
Receive Shift Register
See Section 18.4.6 for bit descriptions.
16
S
0x30 5C1E
S/U
TX_DATA
Transmit Data Register
See Section 18.4.7 for bit descriptions.
16
S
0x30 5C22
S/U
GPDO
General-Purpose Data Out
See Section 18.4.8 for bit descriptions.
16
S
0x30 5C24
S/U
GPDI
General-Purpose Data In
See Section 18.4.9 for bit descriptions.
16
S
0x30 5C26
S/U
SHORT_REG
Short Register
See Table 18-7 for bit descriptions.
16
S
0x30 5C28
S/U
SHORT_CH_REG
Short Channels Register
See Table 18-10 for bit descriptions.
16
S
0x30 5C2A
S/U
SCALE_TCLK_REG Scale Transmit Clock Register
See Table 18-13 for bit descriptions.
16
S
Table B-13. MIOS14 (Modular Input/Output Subsystem)
Address
Access
Symbol
Register
Size
Reset
MPWMSM0 (MIOS Pulse Width Modulation Submodule 0)
0x30 6000
S/U
MPWMPERR
MPWMSM0 Period Register.
See Table 17-26 for bit descriptions.
16
S1
0x30 6002
S/U
MPWMPULR
MPWMSM0 Pulse Width Register.
See Table 17-27 for bit descriptions.
16
S
0x30 6004
S/U
MPWMCNTR
MPWMSM0 Counter Register.
See Table 17-28 for bit descriptions.
16
S
0x30 6006
S/U
MPWMSCR
MPWMSM0 Status/Control Register.
See Table 17-29 for bit descriptions.
16
S
MPWMSM1 (MIOS Pulse Width Modulation Submodule 1)
0x30 6008
S/U
MPWMPERR
MPWMSM1 Period Register.
See Table 17-26 for bit descriptions.
16
S
0x30 600A
S/U
MPWMPULR
MPWMSM1 Pulse Width Register.
See Table 17-27 for bit descriptions.
16
S
0x30 600C
S/U
MPWMCNTR
MPWMSM1 Counter Register.
See Table 17-28 for bit descriptions.
16
S
MPC561/MPC563 Reference Manual, Rev. 1.2
B-18
Freescale Semiconductor
Internal Memory Map
Table B-13. MIOS14 (Modular Input/Output Subsystem) (continued)
Address
0x30 600E
Access
Symbol
S/U
MPWMSCR
Register
MPWMSM1 Status/Control Register.
See Table 17-29 for bit descriptions.
Size
Reset
16
S
MPWMSM2 (MIOS Pulse Width Modulation Submodule 2)
0x30 6010
S/U
MPWMPERR
MPWMSM2 Period Register.
See Table 17-26 for bit descriptions.
16
S
0x30 6012
S/U
MPWMPULR
MPWMSM2 Pulse Width Register.
See Table 17-27 for bit descriptions.
16
S
0x30 6014
S/U
MPWMCNTR
MPWMSM2 Counter Register.
See Table 17-28 for bit descriptions.
16
S
0x30 6016
S/U
MPWMSCR
MPWMSM2 Status/Control Register.
See Table 17-29 for bit descriptions.
16
S
MPWMSM3 (MIOS Pulse Width Modulation Submodule 3)
0x30 6018
S/U
MPWMPERR
MPWMSM3 Period Register.
See Table 17-26 for bit descriptions.
16
S
0x30 601A
S/U
MPWMPULR
MPWMSM3 Pulse Width Register.
See Table 17-27 for bit descriptions.
16
S
0x30 601C
S/U
MPWMCNTR
MPWMSM3 Counter Register.
See Table 17-28 for bit descriptions.
16
S
0x30 601E
S/U
MPWMSCR
MPWMSM3 Status/Control Register.
See Table 17-29 for bit descriptions.
16
S
MPWMSM4 (MIOS Pulse Width Modulation Submodule 4)
0x30 6020
S/U
MPWMPERR
MPWMSM4 Period Register.
See Table 17-26 for bit descriptions.
16
S
0x30 6022
S/U
MPWMPULR
MPWMSM4 Pulse Width Register.
See Table 17-27 for bit descriptions.
16
S
0x30 6024
S/U
MPWMCNTR
MPWMSM4 Counter Register.
See Table 17-28 for bit descriptions.
16
S
0x30 6026
S/U
MPWMSCR
MPWMSM4 Status/Control Register.
See Table 17-29 for bit descriptions.
16
S
MPWMSM5 (MIOS Pulse Width Modulation Submodule 5)
0x30 6028
S/U
MPWMPERR
MPWMSM5 Period Register.
See Table 17-26 for bit descriptions.
16
S
0x30 602A
S/U
MPWMPULR
MPWMSM5 Pulse Width Register.
See Table 17-27 for bit descriptions.
16
S
0x30 602C
S/U
MPWMCNTR
MPWMSM5 Counter Register.
See Table 17-28 for bit descriptions.
16
S
0x30 602E
S/U
MPWMSCR
MPWMSM5 Status/Control Register.
See Table 17-29 for bit descriptions.
16
S
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-19
Internal Memory Map
Table B-13. MIOS14 (Modular Input/Output Subsystem) (continued)
Address
Access
Symbol
Register
Size
Reset
MMCSM6 (MIOS Modulus Counter Submodule 6)
0x30 6030
S/U
MMCSMCNT
MMCSM6 Up-Counter Register.
See Table 17-10 for bit descriptions.
16
X
0x30 6032
S/U
MMCSMML
MMCSM6 Modulus Latch Register.
See Table 17-11 for bit descriptions.
16
S
0x30 6034
S/U
MMCSMSCRD
MMCSM6 Status/Control Register.
See Table 17-12 for bit descriptions.
16
S
0x30 6036
S/U
MMCSMSCR
MMCSM6 Status/Control Register.
See Table 17-12 for bit descriptions.
16
S
MMCSM7 (MIOS Modulus Counter Submodule 7)
0x30 6038
S/U
MMCSMCNT
MMCSM7 Up-Counter Register.
See Table 17-10 for bit descriptions.
16
X
0x30 603A
S/U
MMCSMML
MMCSM7 Modulus Latch Register.
See Table 17-11 for bit descriptions.
16
S
0x30 603E
S/U
MMCSMSCR
MMCSM7 Status/Control Register.
See Table 17-12 for bit descriptions.
16
S
MMCSM8 (MIOS Modulus Counter Submodule 8)
0x30 6040
S/U
MMCSMCNT
MMCSM8 Up-Counter Register.
See Table 17-10 for bit descriptions.
16
X
0x30 6042
S/U
MMCSMML
MMCSM8 Modulus Latch Register.
See Table 17-11 for bit descriptions.
16
S
0x30 6046
S/U
MMCSMSCR
MMCSM8 Status/Control Register.
See Table 17-12 for bit descriptions.
16
S
MDASM11 (MIOS Double Action Submodule 11)
0x30 6058
S/U
MDASMAR
MDASM11 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 605A
S/U
MDASMBR
MDASM11 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 605A
S/U
MDASMSCR
MDASM11 Status/Control Register.
See Table 17-21 for bit descriptions.
16
S
MDASM12 (MIOS Double Action Submodule 12)
0x30 6060
S/U
MDASMAR
MDASM12 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 6062
S/U
MDASMBR
MDASM12 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 6064
S/U
MDASMSCRD
MDASM12 DataA Register.
See Table 17-19 for bit descriptions.
16
S
MPC561/MPC563 Reference Manual, Rev. 1.2
B-20
Freescale Semiconductor
Internal Memory Map
Table B-13. MIOS14 (Modular Input/Output Subsystem) (continued)
Address
0x30 6066
Access
Symbol
S/U
MDASMSCR
Register
MDASM Status/Control Register.
See Table 17-21 for bit descriptions.
Size
Reset
16
S
MDASM13 (MIOS Double Action Submodule 13)
0x30 6068
S/U
MDASMAR
MDASM13 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 606A
S/U
MDASMBR
MDASM13 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 606E
S/U
MDASMSCR
MDASM13 Status/Control Register.
See Table 17-21 for bit descriptions.
16
S
MDASM14 (MIOS Double Action Submodule 14)
0x30 6070
S/U
MDASMAR
MDASM14 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 6072
S/U
MDASMBR
MDASM14 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 6076
S/U
MDASMSCR
MDASM14 Status/Control Register.
See Table 17-21 for bit descriptions.
16
S
MDASM (MIOS Double Action Submodule 15)
0x30 6078
S/U
MDASMAR
MDASM15 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 607A
S/U
MDASMBR
MDASM15 DataA Register.
See Table 17-19 for bit descriptions.
16
S
0x30 607E
S/U
MDASMSCR
MDASM15 Status/Control Register.
See Table 17-21 for bit descriptions.
16
S
MPWMSM16 (MIOS Pulse Width Modulation Submodule 16)
0x30 6080
S/U
MPWMPERR
MPWMSM16 Period Register.
See Table 17-26 for bit descriptions.
16
S
0x30 6082
S/U
MPWMPULR
MPWMSM16 Pulse Width Register.
See Table 17-27 for bit descriptions.
16
S
0x30 6084
S/U
MPWMCNTR
MPWMSM16 Counter Register.
See Table 17-28 for bit descriptions.
16
S
0x30 6086
S/U
MPWMSCR
MPWMSM16 Status/Control Register.
See Table 17-29 for bit descriptions.
16
S
MPWMSM17 (MIOS Pulse Width Modulation Submodule 17)
0x30 6088
S/U
MPWMPERR
MPWMSM17 Period Register.
See Table 17-26 for bit
descriptions.
16
S
0x30 608A
S/U
MPWMPULR
MPWMSM17 Pulse Width Register.
See Table 17-27 for bit
descriptions.
16
S
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-21
Internal Memory Map
Table B-13. MIOS14 (Modular Input/Output Subsystem) (continued)
Address
Access
Symbol
0x30 608C
S/U
MPWMCNTR
0x30 608E
S/U
MPWMSCR
Register
Size
Reset
MPWMSM17 Counter Register.
See Table 17-28 for bit
descriptions.
16
S
MPWMSM17 Status/Control Register.
See Table 17-29 for bit
descriptions.
16
S
MPWMSM18 (MIOS Pulse Width Modulation Submodule 18)
0x30 6090
S/U
MPWMPERR
MPWMSM18 Period Register.
See Table 17-26 for bit
descriptions.
16
S
0x30 6092
S/U
MPWMPULR
MPWMSM18 Pulse Width Register.
See Table 17-27 for bit
descriptions.
16
S
0x30 6094
S/U
MPWMCNTR
MPWMSM18 Counter Register.
See Table 17-28 for bit
descriptions.
16
S
0x30 6096
S/U
MPWMSCR
MPWMSM18 Status/Control Register.
See Table 17-29 for bit
descriptions.
16
S
MPWMSM19 (MIOS Pulse Width Modulation Submodule 19)
0x30 6098
S/U
MPWMPERR
MPWMSM19 Period Register.
See Table 17-26 for bit
descriptions.
16
S
0x30 609A
S/U
MPWMPULR
MPWMSM19 Pulse Width Register.
See Table 17-27 for bit
descriptions.
16
S
0x30 609C
S/U
MPWMCNTR
MPWMSM19 Counter Register.
See Table 17-28 for bit
descriptions.
16
S
0x30 609E
S/U
MPWMSCR
MPWMSM19 Status/Control Register.
See Table 17-29 for bit
descriptions.
16
S
MPWMSM20 (MIOS Pulse Width Modulation Submodule 20)
0x30 60A0
S/U
MPWMPERR
MPWMSM20 Period Register.
See Table 17-26 for bit
descriptions.
16
S
0x30 60A2
S/U
MPWMPULR
MPWMSM20 Pulse Width Register.
See Table 17-27 for bit
descriptions.
16
S
0x30 60A4
S/U
MPWMCNTR
MPWMSM20 Counter Register.
See Table 17-28 for bit
descriptions.
16
S
MPC561/MPC563 Reference Manual, Rev. 1.2
B-22
Freescale Semiconductor
Internal Memory Map
Table B-13. MIOS14 (Modular Input/Output Subsystem) (continued)
Address
0x30 60A6
Access
Symbol
S/U
MPWMSCR
Register
MPWMSM20 Status/Control Register.
See Table 17-29 for bit
descriptions.
Size
Reset
16
S
MPWMSM21 (MIOS Pulse Width Modulation Submodule 21)
0x30 60A8
S/U
MPWMPERR
MPWMSM21 Period Register.
See Table 17-26 for bit
descriptions.
16
S
0x30 60AA
S/U
MPWMPULR
MPWMSM21 Pulse Width Register.
See Table 17-27 for bit
descriptions.
16
S
0x30 60AC
S/U
MPWMCNTR
MPWMSM21 Counter Register.
See Table 17-28 for bit
descriptions.
16
S
0x30 60AE
S/U
MPWMSCR
MPWMSM21 Status/Control Register.
See Table 17-29 for bit
descriptions.
16
S
MMCSM22 Up-Counter Register.
See Table 17-10 for bit
descriptions.
16
X
MMCSM22 (MIOS Modulus Counter Submodule 22)
0x30 60B0
S/U
MMCSMCNT
0x30 60B2
S/U
MMCSMML
MMCSM22 Modulus Latch Register.
See Table 17-11 for bit
descriptions.
16
S
0x30 60B6
S/U
MMCSMSCR
MMCSM22 Status/Control Register.
See Table 17-12 for bit
descriptions.
16
S
MMCSM23 Up-Counter Register.
See Table 17-10 for bit
descriptions.
16
X
MMCSM23 (MIOS Modulus Counter Submodule 23)
0x30 60B8
S/U
MMCSMCNT
0x30 60BA
S/U
MMCSMML
MMCSM23 Modulus Latch Register.
See Table 17-11 for bit
descriptions.
16
S
0x30 60BE
S/U
MMCSMSCR
MMCSM23 Status/Control Register.
See Table 17-12 for bit
descriptions.
16
S
16
X
MMCSM24 (MIOS Modulus Counter Submodule 24)
0x30 60C0
S/U
MMCSMCNT
MMCSM24 Up-Counter Register.
See Table 17-10 for bit
descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-23
Internal Memory Map
Table B-13. MIOS14 (Modular Input/Output Subsystem) (continued)
Address
Access
Symbol
0x30 60C2
S/U
MMCSMML
0x30 60C6
S/U
MMCSMSCR
Register
Size
Reset
MMCSM24 Modulus Latch Register.
See Table 17-11 for bit
descriptions.
16
S
MMCSM24 Status/Control Register.
See Table 17-12 for bit
descriptions.
16
S
MDASM27 (MIOS Double Action Submodule 27)
0x30 60D8
S/U
MDASMAR
MDASM27 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
0x30 60DA
S/U
MDASMBR
MDASM27 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
0x30 60DE
S/U
MDASMSCR
MDASM27 Status/Control Register.
See Table 17-21 for bit
descriptions.
16
S
MDASM28 (MIOS Double Action Submodule 28)
0x30 60E0
S/U
MDASMAR
MDASM28 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
0x30 60E2
S/U
MDASMBR
MDASM28 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
0x30 60E6
S/U
MDASMSCR
MDASM28 Status/Control Register.
See Table 17-21 for bit
descriptions.
16
S
MDASM29 (MIOS Double Action Submodule 29)
0x30 60E8
S/U
MDASMAR
MDASM29 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
0x30 60EA
S/U
MDASMBR
MDASM29 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
0x30 60EE
S/U
MDASMSCR
MDASM29 Status/Control Register.
See Table 17-21 for bit
descriptions.
16
S
16
S
MDASM30 (MIOS Double Action Submodule 30)
0x30 60F0
S/U
MDASMAR
MDASM30 DataA Register.
See Table 17-19 for bit
descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
B-24
Freescale Semiconductor
Internal Memory Map
Table B-13. MIOS14 (Modular Input/Output Subsystem) (continued)
Address
Access
Symbol
0x30 6F2
S/U
MDASMBR
0x30 60F6
S/U
MDASMSCR
Register
Size
Reset
MDASM30 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
MDASM30 Status/Control Register.
See Table 17-21 for bit
descriptions.
16
S
MDASM31 (MIOS Double Action Submodule 31)
0x30 60F8
S/U
MDASMAR
MDASM31 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
0x30 60FA
S/U
MDASMBR
MDASM31 DataA Register.
See Table 17-19 for bit
descriptions.
16
S
0x30 60FE
S/U
MDASMSCR
MDASM31 Status/Control Register.
See Table 17-21 for bit
descriptions.
16
S
MPIOSM (MIOS 16-bit Parallel Port I/O Submodule)
0x30 6100
S/U
MPIOSMDR
MPIOSM Data Register.
See Table 17-33 for bit
descriptions.
16
S
0x30 6102
S/U
MPIOSMDDR
MPIOSM Data Direction Register.
See Table 17-34 for bit
descriptions.
16
S
MBISM (MIOS Bus Interface Submodule)
0x30 6800
S/U
MIOS14TPCR
MIOS14 Test and Pin Control Register.
See Table 17-3 for bit descriptions.
16
X
0x30 6802
S/U
MIOS14VECT
MIOS14 Vector Register.
See Table 17-2 for bit descriptions.
16
X
0x30 6804
S/U
MIOS14VNR
MIOS14 Vector Register.
See Section 17.6.1.3 for bit descriptions.
16
S
0x30 6806
S/U
MIOS14MCR
MIOS14 Module Configuration Register.
See Table 17-5 for bit descriptions.
16
X
16
X
16
X
MCPSM (MIOS Status/Control Submodule)
0x30 6816
S/U
MCPSMSCR
MCPSM Status/Control Register.
See Table 17-7 for bit descriptions.
MIRSM0 (MIOS Interrupt Status Submodule 0)
0x30 6C00
S/U
MIOS14SR0
MIOS14 Interrupt Status Register.
See Table 17-35 for bit
descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-25
Internal Memory Map
Table B-13. MIOS14 (Modular Input/Output Subsystem) (continued)
Address
Access
Symbol
0x30 6C04
S/U
MIOS14ER0
0x30 6C06
S/U
MIOS14RPR0
Register
Size
Reset
MIOS14 Interrupt Enable Register.
See Table 17-36 for bit
descriptions.
16
X
MIOS14 Request Pending Register.See
Table 17-37 for bit descriptions.
16
S
MIRSM1 (MIOS Interrupt Request Submodule 1)
0x30 6C40
S/U
MIOS14SR1
MIOS14 Interrupt Status Register.
See Table 17-38 for bit
descriptions.
16
X
0x30 6C44
S/U
MIOSER1
MIOS14 Interrupt Enable Register.
See Table 17-39 for bit
descriptions.
16
X
0x30 6C46
S/U
MIOS14RPR1
MIOS14 Request Pending Register.
See Table 17-40 for bit
descriptions.
16
X
MBISM0 (MIOS Interrupt Request Submodule 0)
0x30 6C30
S/U
MIOS14LVL0
MIOS14 Interrupt Level 0 Register.
See Table 17-42 for bit
descriptions.
16
S
0x30 6C70
S/U
MIOS14LVL1
MIOS14 Interrupt Level 1 Register.
See Table 17-43 for bit descriptions.
16
X
Size
Reset
1
Only bits WEN, TEST, STB, and WIP affected by reset.
Table B-14. TouCAN A, B and C (CAN 2.0B Controller)
Address
Access
Symbol
Register
TouCAN_A
(Note: Bit descriptions apply to TouCAN_B and TouCAN_C as well)
0x30 7080
S
CANMCR_A
TouCAN_A Module Configuration Register.
See Table 16-11 for bit descriptions.
16
S
0x30 7082
T
CANTCR_A
TouCAN_A Test Register
16
S
0x30 7084
S
CANICR_A
TouCAN_A Interrupt Configuration Register.
See Table 16-12 for bit descriptions.
16
S
0x30 7086
S/U
CANCTRL0_A/
CANCTRL1_A
TouCAN_A Control Register 0/
TouCAN_A Control Register 1.
See Table 16-13 and Table 16-16 for bit
descriptions.
16
S
0x30 7088
S/U
PRESDIV_A/
CTRL2_A
TouCAN_A Control and Prescaler Divider
Register/TouCAN_A Control Register 2.
See Table 16-17 and Table 16-18 for bit
descriptions.
16
S
MPC561/MPC563 Reference Manual, Rev. 1.2
B-26
Freescale Semiconductor
Internal Memory Map
Table B-14. TouCAN A, B and C (CAN 2.0B Controller) (continued)
Address
Access
Symbol
Size
Reset
S/U
TIMER_A
TouCAN_A Free-Running Timer Register.
See Table 16-19 for bit descriptions.
16
S
—
—
Reserved
—
—
0x30 7090
S/U
RXGMSKHI_A
TouCAN_A Receive Global Mask High.
See Table 16-20 for bit descriptions.
32
S
0x30 7092
S/U
RXGMSKLO_A
TouCAN_A Receive Global Mask Low.
See Table 16-20 for bit descriptions.
32
S
0x30 7094
S/U
RX14MSKHI_A
TouCAN_A Receive Buffer 14 Mask High.
See Table 16-21 for bit descriptions.
32
S
0x30 7096
S/U
RX14MSKLO_A TouCAN_A Receive Buffer 14 Mask Low.
See Table 16-21 for bit descriptions.
32
S
0x30 7098
S/U
RX15MSKHI_A
TouCAN_A Receive Buffer 15 Mask High.
See Table 16-22 for bit descriptions.
32
S
0x30 709A
S/U
RX15MSKLO_A TouCAN_A Receive Buffer 15 Mask Low.
See Table 16-22 for bit descriptions.
32
S
Reserved
—
—
0x30 708A
0x30 708C —
0x30 708E
0x30 709C —
0x30 709E
Register
—
—
0x30 70A0
S/U
ESTAT_A
TouCAN_A Error and Status Register.
See Table 16-23 for bit descriptions.
16
S
0x30 70A2
S/U
IMASK_A
TouCAN_A Interrupt Masks.
See Table 16-26 for bit descriptions.
16
S
0x30 70A4
S/U
IFLAG_A
TouCAN_A Interrupt Flags.
See Table 16-27 for bit descriptions.
16
S
0x30 70A6
S/U
RxECTR_A/
TxECTR_A
TouCAN_A Receive Error Counter/
TouCAN_A Transmit Error Counter.
See Table 16-28 for bit descriptions.
16
S
0x30 7100 —
0x30 710F
S/U
MBUFF0_A1
TouCAN_A Message Buffer 02
—
U
0x30 7110 —
0x30 711F
S/U
MBUFF1_A1
TouCAN_A Message Buffer 12
—
U
0x30 7120 —
0x30 712F
S/U
MBUFF2_A1
TouCAN_A Message Buffer 22
—
U
0x30 7130 —
0x30 713F
S/U
MBUFF3_A1
TouCAN_A Message Buffer 32
—
U
0x30 7140 —
0x30 714F
S/U
MBUFF4_A1
TouCAN_A Message Buffer 42
—
U
0x30 7150 —
0x30 715F
S/U
MBUFF5_A1
TouCAN_A Message Buffer 52
—
U
0x30 7160 —
0x30 716F
S/U
MBUFF6_A1
TouCAN_A Message Buffer 62
—
U
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-27
Internal Memory Map
Table B-14. TouCAN A, B and C (CAN 2.0B Controller) (continued)
Address
Access
Symbol
0x307170 —
0x30717F
S/U
MBUFF7_A1
0x30 7180 —
0x30 718F
S/U
0x30 7190 —
0x30 719F
Register
Size
Reset
TouCAN_A Message Buffer 72
—
U
MBUFF8_A1
TouCAN_A Message Buffer 82
—
U
S/U
MBUFF9_A1
TouCAN_A Message Buffer 92
—
U
0x30 71A0 —
0x30 71AF
S/U
MBUFF10_A1
TouCAN_A Message Buffer 102
—
U
0x30 71B0 —
0x30 71BF
S/U
MBUFF11_A1
TouCAN_A Message Buffer 112
—
U
0x30 71C0 —
0x30 71CF
S/U
MBUFF12_A1
TouCAN_A Message Buffer 122
—
U
0x30 71D0 —
0x30 71DF
S/U
MBUFF13_A1
TouCAN_A Message Buffer 132
—
U
0x30 71E0 —
0x30 71EF
S/U
MBUFF14_A1
TouCAN_A Message Buffer 142
—
U
0x30 71F0 —
0x30 71FF
S/U
MBUFF15_A1
TouCAN_A Message Buffer 152
—
U
TouCAN_B
0x30 7480
S
CANMCR_B
TouCAN_B Module Configuration Register
16
S
0x30 7482
T
CANTCR_B
TouCAN_B Test Register
16
S
0x30 7484
S
CANICR_B
TouCAN_B Interrupt Configuration Register
16
S
0x30 7486
S/U
CANCTRL0_B/
CANCTRL1_B
TouCAN_B Control Register 0/
TouCAN_B Control Register 1
16
S
0x30 7488
S/U
PRESDIV_B/
CTRL2_B
TouCAN_B Control and Prescaler Divider
Register/TouCAN_B Control Register 2
16
S
0x30 748A
S/U
TIMER_B
TouCAN_B Free-Running Timer Register
—
—
0x30 7490
S/U
0x30 7492
0x30 748C —
0x30 748E
S
Reserved
—
—
RXGMSKHI_B
TouCAN_B Receive Global Mask High
32
S
S/U
RXGMSKLO_B
TouCAN_B Receive Global Mask Low
32
S
0x30 7494
S/U
RX14MSKHI_B
TouCAN_B Receive Buffer 14 Mask High
32
S
0x30 7496
S/U
RX14MSKLO_B TouCAN_B Receive Buffer 14 Mask Low
3
S
0x30 7498
S/U
RX15MSKHI_B
TouCAN_B Receive Buffer 15 Mask High
32
S
0x30 749A
S/U
RX15MSKLO_B TouCAN_B Receive Buffer 15 Mask Low
32
S
Reserved
—
—
TouCAN_B Error and Status Register
16
S
0x30 749C —
0x30 749E
0x30 74A0
—
—
S/U
ESTAT_B
MPC561/MPC563 Reference Manual, Rev. 1.2
B-28
Freescale Semiconductor
Internal Memory Map
Table B-14. TouCAN A, B and C (CAN 2.0B Controller) (continued)
Address
Access
Symbol
0x30 74A2
S/U
IMASK_B
0x30 74A4
S/U
IFLAG_B
0x30 74A6
S/U
0x30 7500 —
0x30 750F
Register
Size
Reset
TouCAN_B Interrupt Masks
16
S
TouCAN_B Interrupt Flags
16
S
RXECTR_B/
TXECTR_B
TouCAN_B Receive Error Counter/
TouCAN_B Transmit Error Counter
16
S
S/U
MBUFF0_B1
TouCAN_B Message Buffer 0.
—
U
0x30 7510 —
0x30 751F
S/U
MBUFF1_B1
TouCAN_B Message Buffer 1.
—
U
0x30 7520 —
0x30 752F
S/U
MBUFF2_B1
TouCAN_B Message Buffer 2.
—
U
0x30 7530 —
0x30 753F
S/U
MBUFF3_B1
TouCAN_B Message Buffer 3.
—
U
0x30 7540 —
0x30 754F
S/U
MBUFF4_B1
TouCAN_B Message Buffer 4.
—
U
0x30 7550 —
0x30 755F
S/U
MBUFF5_B1
TouCAN_B Message Buffer 5.
—
U
0x30 7560 —
0x30 756F
S/U
MBUFF6_B1
TouCAN_B Message Buffer 6.
—
U
0x30 7570 —
0x30 757F
S/U
MBUFF7_B1
TouCAN_B Message Buffer 7.
—
U
0x30 7580 —
0x30 758F
S/U
MBUFF8_B1
TouCAN_B Message Buffer 8.
—
U
0x30 7590 —
0x30 759F
S/U
MBUFF9_B1
TouCAN_B Message Buffer 9.
—
U
0x30 75A0 —
0x30 75AF
S/U
MBUFF10_B1
TouCAN_B Message Buffer 10.
—
U
0x30 75B0 —
0x30 75BF
S/U
MBUFF11_B1
TouCAN_B Message Buffer 11.
—
U
0x30 75C0 —
0x30 75CF
S/U
MBUFF12_B1
TouCAN_B Message Buffer 12.
—
U
0x30 75D0 —
0x30 75DF
S/U
MBUFF13_B1
TouCAN_B Message Buffer 13.
—
U
0x30 75E0 —
0x30 75EF
S/U
MBUFF14_B1
TouCAN_B Message Buffer 14.
—
U
0x30 75F0 —
0x30 75FF
S/U
MBUFF15_B1
TouCAN_B Message Buffer 15.
—
U
TouCAN_C
0x30 7880
S
CANMCR_C
TouCAN_C Module Configuration Register
16
S
0x30 7882
T
CANTCR_C
TouCAN_C Test Register
16
S
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-29
Internal Memory Map
Table B-14. TouCAN A, B and C (CAN 2.0B Controller) (continued)
Address
Access
Symbol
0x30 7884
S
CANICR_C
0x30 7886
S/U
CANCTRL0_C/
CANCTRL1_C
0x30 7888
S/U
0x30 788A
Size
Reset
TouCAN_C Interrupt Configuration Register
16
S
TouCAN_C Control Register 0/
TouCAN_C Control Register 1
16
S
PRESDIV_C/
CTRL2_C
TouCAN_C Control and Prescaler Divider
Register/
TouCAN_C Control Register 2
16
S
S/U
TIMER_C
TouCAN_C Free-Running Timer Register
—
—
0x30 7890
S/U
0x30 7892
0x30 788C —
0x30 788E
Register
S
Reserved
—
—
RXGMSKHI_C
TouCAN_C Receive Global Mask High
32
S
S/U
RXGMSKLO_C
TouCAN_C Receive Global Mask Low
32
S
0x30 7894
S/U
RX14MSKHI_C
TouCAN_C Receive Buffer 14 Mask High
32
S
0x30 7896
S/U
RX14MSKLO_C TouCAN_C Receive Buffer 14 Mask Low
32
S
0x30 7898
S/U
RX15MSKHI_C
TouCAN_C Receive Buffer 15 Mask High
32
S
0x30 789A
S/U
RX15MSKLO_C TouCAN_C Receive Buffer 15 Mask Low
32
S
Reserved
—
—
0x30 789C —
0x30 789E
—
—
0x30 78A0
S/U
ESTAT_C
TouCAN_C Error and Status Register
16
S
0x30 78A2
S/U
IMASK_C
TouCAN_C Interrupt Masks
16
S
0x30 78A4
S/U
IFLAG_C
TouCAN_C Interrupt Flags
16
S
0x30 78A6
S/U
RXECTR_C/
TXECTR_C
TouCAN_C Receive Error Counter/
TouCAN_C Transmit Error Counter
16
S
0x30 7900 —
0x30 790F
S/U
MBUFF0_C1
TouCAN_C Message Buffer 0.
—
U
0x30 7910 —
0x30 791F
S/U
MBUFF1_C1
TouCAN_B Message Buffer 1.
—
U
0x30 7920 —
0x30 792F
S/U
MBUFF2_C1
TouCAN_C Message Buffer 2.
—
U
0x30 7930 —
0x30 793F
S/U
MBUFF3_C1
TouCAN_C Message Buffer 3.
—
U
0x30 7940 —
0x30 794F
S/U
MBUFF4_C1
TouCAN_C Message Buffer 4.
—
U
0x30 7950 —
0x30 795F
S/U
MBUFF5_C1
TouCAN_C Message Buffer 5.
—
U
0x30 7960 —
0x30 796F
S/U
MBUFF6_C1
TouCAN_C Message Buffer 6.
—
U
0x30 7970 —
0x30 797F
S/U
MBUFF7_C1
TouCAN_C Message Buffer 7.
—
U
MPC561/MPC563 Reference Manual, Rev. 1.2
B-30
Freescale Semiconductor
Internal Memory Map
Table B-14. TouCAN A, B and C (CAN 2.0B Controller) (continued)
Address
Access
Symbol
0x30 7980 —
0x30 798F
S/U
MBUFF8_C1
0x30 7990 —
0x30 799F
S/U
0x30 79A0 —
0x30 79AF
Size
Reset
TouCAN_C Message Buffer 8.
—
U
MBUFF9_C1
TouCAN_C Message Buffer 9.
—
U
S/U
MBUFF10_C1
TouCAN_C Message Buffer 10.
—
U
0x30 79B0 —
0x30 79BF
S/U
MBUFF11_C1
TouCAN_C Message Buffer 11.
—
U
0x30 79C0 —
0x30 79CF
S/U
MBUFF12_C1
TouCAN_C Message Buffer 12.
—
U
0x30 79D0 —
0x30 79DF
S/U
MBUFF13_C1
TouCAN_C Message Buffer 13.
—
U
0x30 79E0 —
0x30 79EF
S/U
MBUFF14_C1
TouCAN_C Message Buffer 14.
—
U
0x30 79F0 —
0x30 79FF
S/U
MBUFF15_C1
TouCAN_C Message Buffer 15.
—
U
1
2
Register
The last word of each of the MBUFF arrays (address 0x....E) is reserved and may cause a RCPU exception if read.
See Table 16-3 and Table 16-4 for message buffer definitions.
Table B-15. UIMB (U-Bus to IMB Bus Interface)
Address
Access
Symbol
0x30 7F80
S1
UMCR
0x30 7F84 —
0x30 7F8C
—
—
0x30 7F90
S/T
UTSTCREG
0x30 7F94 —
0x30 7F9C
—
—
0x30 7FA0
S
UIPEND
1
Register
Size
Reset
UIMB Module Configuration Register.
See Table 12-6 for bit descriptions.
32
H
Reserved
32
H
UIMB Test Control Register.
Reserved
32
H
Reserved
32
H
Pending Interrupt Request Register.
See Section 12.5.3 and Table 12-7 for bit
descriptions.
32
H
S = Supervisor mode only, T = Test mode only
Table B-16. CALRAM Control Registers
Address
Access
Symbol
Register
Size
Reset
32
S
CALRAM
0x38 0000
S
CRAMMCR
CALRAMModule Configuration Register.
See Table 22-3 for bit descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-31
Internal Memory Map
Table B-16. CALRAM Control Registers (continued)
Address
0x38 0004
Access
Symbol
S
CRAMTST
Register
CALRAM Test Register.
Size
Reset
32
S
Register1
32
S
0x38 0008
S
CRAM_RBA0
CALRAM Region Base Address
0x38 000C
S
CRAM_RBA1
CALRAM Region Base Address Register1
32
S
CRAM_RBA2
Register1
32
S
1
32
S
0x38 0010
S
CALRAM Region Base Address
0x38 0014
S
CRAM_RBA3
CALRAM Region Base Address Register
0x38 0018
S
CRAM_RBA4
CALRAM Region Base Address Register1
32
S
CRAM_RBA5
CALRAM Region Base Address Register
1
32
S
1
32
S
0x38 001C
S
0x38 0020
S
CRAM_RBA6
CALRAM Region Base Address Register
0x38 0024
S
CRAM_RBA7
CALRAM Region Base Address Register1
32
S
0x38 0028
S
CRAM_OLVCR
CALRAM Overlay Configuration Register.See
Table 22-7 for bit descriptions.
32
S
0x38 002C
S2
READI_OTR
READI Ownership Trace Register.
See Section 24.6.1.1, “User-Mapped Register
(OTR),” for more information.
32
H
1
2
See Section 22.5.2, “CALRAM Region Base Address Registers (CRAM_RBAx),” for more information.
This register is write only.
Table B-17. CALRAM Array
Address
Access
Symbol
Register
Size
Reset
32 Kbytes
—
Size
Reset
CALRAM
0x3F 8000 —
0x3F FFFF
U,S
CRAM
CALRAM Array
Table B-18. READI Module Registers
Address
Access
Symbol
Register
0x08
Read Only
READI_DID
Device ID Register
See Table 24-6 for bit descriptions.
32
R
0x0A
Read Only
READI_DC
Development Control Register
See Table 24-7 for bit descriptions.
8
R
0x0B
Read/Write
READI_MC
Mode Control Register1
See Table 24-9 for bit descriptions.
8
R
0x0D
Read Only
READI_UBA
User Base Address Register
See Table 24-10 for bit descriptions.
32
R
0x0F
Read/Write
READI_RWA
Read/Write Access Register
See Table 24-11 for bit descriptions.
80
R
0x10
Read/Write
READI_UDI
Upload/Download Information Register
See Table 24-12 for bit descriptions.
34
R
MPC561/MPC563 Reference Manual, Rev. 1.2
B-32
Freescale Semiconductor
Internal Memory Map
Table B-18. READI Module Registers
1
Address
Access
Symbol
0x14
Read/Write
READI_DTA1
0x15
Read/Write
READI_DTA2
Register
Size
Reset
Data Trace Attributes Register 1
See Table 24-15 for bit descriptions.
48
R
Data Trace Attributes Register 2
See Table 24-15 for bit descriptions.
48
R
Not available on all revisions. Refer to the device errata for the version of silicon in use.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
B-33
Internal Memory Map
MPC561/MPC563 Reference Manual, Rev. 1.2
B-34
Freescale Semiconductor
Appendix C
Clock and Board Guidelines
The MPC561/MPC563 built-in PLL, oscillator, and other analog and sensitive circuits require that the
board design follow special layout guidelines to ensure proper operation of the chip clocks. This appendix
describes how the clock supplies and external components should be connected in a system. These
guidelines must be fulfilled to reduce switching noise which is generated on internal and external buses
during operation. Any noise injected into the sensitive clock and PLL logic reduces clock performance.
The USIU maintains a PLL loss-of-lock warning indication that can be used to determine the clock
stability in the MPC561/MPC563.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
C-1
Clock and Board Guidelines
C.1
MPC56x Device Power Distribution
Board
MPC56x Device
VDD (external 2.6 V)
100 nF3
Keyed
VDD 2.6 V
(Main Supply)1
VSS (external GND)
NVDDL (external 2.6 V)
100 nF
1 nF
1 µF
VSS (internal GND)
100 nF
VDDF5 (external 2.6 V)
DECRAM
(Decompression off)
Instruction Fetch->
cmf
new page
Load/Store -> IMB
U
ICD
U
ICD
U
U
C,U
2
U
L
U
IMB
6
IMB
Instruction Fetch->
cmf
new page
Load/Store -> IMB
C
U
U
6
U
L
U
IMB
6
IMB
External Bus-> cmf
new page
E
External Bus-> IMB
E
U
5
U
L
L
U
U
E
IMB
7
IMB
Load/Store->
DECRAM
L
U
E
U
U
L
MPC561/MPC563 Reference Manual, Rev. 1.2
E-2
Freescale Semiconductor
Memory Access Timing
Table E-2. Instruction Timing Examples for Different Buses (continued)
Note: L = L-bus, U = U-bus, E = E-bus, C = CMF (Flash), IMB = intermodule bus, DC = DECRAM
Number of Clocks
Access
Total
1
Instruction Fetch->
cmf
2 consecutive
accesses and
External Bus-> cmf
2
3
4
5
6
7
8
9
10
11
12
13
C,U
2
U
C
—3
—
—
—
—
—
—
—
U
11
U
E
Retr
y
E4
U
8
U
E
1
N is the number of read cycle clocks from external address valid until external data valid. In the case of zero wait states,
N = 2.
2 Core instruction fetch data bus is usually the U-bus
3 8 clocks are dedicated for external accesses, and internal accesses are denied.
4 Assuming the external master immediately retries
Note: Shaded areas = address phase ; Non-shaded areas = data phase
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
E-3
Memory Access Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
E-4
Freescale Semiconductor
Appendix F
Electrical Characteristics
This appendix contains detailed information on power considerations, DC/AC electrical characteristics,
and AC timing characteristics of the MPC561/MPC563. The MPC561/MPC563 is designed to operate at
40 MHz, or optionally at 56 or 66 MHz. Refer to Appendix G, “66-MHz Electrical Characteristics,” for
more information.
)
Table F-1. Absolute Maximum Ratings (VSS = 0V)
Rating
1
2
3
4
5
2.6-V Supply Voltage1
Flash Supply
Flash Core
Voltage3,4
Voltage1, 4
Oscillator, keep-alive Reg. Supply
SRAM Supply
Voltage1
Symbol
Min. Value
Max. Value
Unit
VDDL
-0.3
3.02
V
VFLASH
-0.3
5.6
V
VDDF
-0.3
3.0
V
KAPWR
-0.3
3.0
V
-0.3
3.0
V
-0.3
3.0
V
Voltage1,5
IRAMSTBY
6
Clock Synthesizer Supply Voltage1
7
N.A.
—
—
—
—
8
QADC Supply Voltage6
VDDA
-0.3
5.6
V
9
5-V Supply Voltage
VDDH
-0.3
5.6
V
V
Voltages7,8
VDDSYN
10
DC Input
VIN
VSS-0.3
5.69
11
Reference VRH, with reference to VRL
VRH
-0.3
5.6
V
12
Reference ALTREF, with reference to VRL
VARH
-0.3
5.6
V
13
VSS Differential Voltage
VSS – VSSA
-0.1
0.1
V
15
VREF Differential Voltage
VRH – VRL
-5.6
5.6
V
16
VRL to VSSA Differential Voltage
VRL – VSSA
-0.3
0.3
V
17
Maximum Input Current per pin 10, 11, 12
IMA
-2513
2513
mA
18
QADC Maximum Input Current per Pin
IMAX
-2513
2513
mA
19
Operating Temperature Range – Ambient
(Packaged), M temperature range.
TA
-40
(TL)
+125
(TH)
°C
19a Operating Temperature Range – Ambient
(Packaged), C temperature range.
TA
-40
(TL)
+85
(TH)
°C
TSB
-40
(TL)
+135
(TH)
°C
TJ
-40
+150
°C
TSTG
-55
+150
°C
TSDR
—
235
°C
MSL
—
3
—
20
Operating Temperature Range – Solder Ball
(Packaged any perimeter solder ball)14
21
Junction Temperature Range
22
Storage Temperature Range
23
24
Maximum Solder Temperature
Moisture Sensitivity
Level16
15
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-1
Electrical Characteristics
1
For internal digital supply of VDDL = 2.6-V typical.
2.6 volt supply pins can withstand up to 3.6 volts for acumulative time of 24 hours over the lifetime of the device.
3
During operation the value of VFLASH must be 5.0 V ±5%
4
These power supplies are available on MPC563 and MPC564 only.
5
Maximum average current into the IRAMSTBY pin must be < 1.75mA.
6
VDDA=5.0 V ±5%.
7
All 2.6-V input-only pins are 5-V tolerant.
8
Note that long term reliability may be compromised if 2.6-V output drivers drive a node which has been previously
pulled to >3.1 V by an external component. HRESET and SRESET are fully 5-V compatible.
9
6.35 V on 5-V only pins (all QADC, all TPU, all QSMCM and the following MIOS pins: MDA[11:15], MDA[27:31],
MPWM16, MPIO32B[7:9]/MPWM[20:21], MPIO32B11/C_CNRX0, MPIO32B12/C_CNTX0 ). Internal structures hold
the input voltage below this maximum voltage on all of these pins, except the QSMCM RXD1/QPI1 and
RXD2/QPI2/C_CNRX0 pins, if the maximum injection current specification is met (1 mA for all pins; exception: 3 mA
on QADC pins) and VDDH is within Operating Voltage specifications (see specification 43 in Table F-4). Exception:
The RXD1/QGPI1 and RXD2/GPI2 pins do not have clamp diodes to VDDH. Voltage must be limited to less than 6.5
volts on these 2 pins to prevent damage.
10
Maximum continuous current on I/O pins provided the overall power dissipation is below the power dissipation of the
package. Proper operation is not guaranteed at this condition.
11 Condition applies to one pin at a time.
12 Transitions within the limit do not affect device reliability or cause permanent damage. Exceeding limit may cause
permanent conversion error on stressed channels and on unstressed channels.
13 Maximum transient current per ISO7637.
14 Maximum operating temperature on any solder ball in outer four rows of solder balls on the package. These rows are
referred to as “Perimeter Balls” to distinguish them from the balls in the center of the package.
15 Solder profile per CDF-AEC-Q100, current revision.
16 Moisture sensitivity per JEDEC test method J-STD-020-A (April 1999).
2
Functional operating conditions are given in Section F.5, “DC Electrical Characteristics.” Absolute
maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress
beyond those listed may affect device reliability or cause permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).
NOTE
Negative current flows out of the pin and positive current flows into the pin.
F.1
Package
The MPC561/MPC563 is available in packaged form. The package is a 388-ball PBGA having a 1.0 mm
ball pitch, Freescale case outline 1164-01 (See Figure F-64 and Figure F-65).
F.2
F.2.1
EMI Characteristics
Reference Documents
The document referenced for the EMC testing of MPC561/MPC563 is SAE J1752/3 Issued 1995-03
MPC561/MPC563 Reference Manual, Rev. 1.2
F-2
Freescale Semiconductor
Electrical Characteristics
F.2.2
Definitions and Acronyms
EMC – Electromagnetic Compatibility
EMI – Electromagnetic Interference
TEM cell – Transverse Electromagnetic Mode cell
F.2.3
EMI Testing Specifications
1.
2.
3.
4.
5.
6.
Scan range: 150 KHz – 1000 MHz
Operating Frequency: 56 MHz
Operating Voltages: 2.6 V, 5.0 V
Max spikes: TBD dBuV
I/O port waveforms: Per J1752/3
Temperature: 25 °C
F.3
Thermal Characteristics
Table F-2. Thermal Characteristics
Characteristic
Symbol
Value
Unit
RθJA
47.31,2,3
°C/W
RθJMA
29.43,4,5
°C/W
BGA Package Thermal Resistance,
Junction to Board
RθJB
21.2 3,6
°C/W
BGA Package Thermal Resistance,
Junction to Case (top)
RθJT
7.03,7
°C/W
BGA Package Thermal Resistance,
Junction to Package Top, Natural Convection
ΨJT
1.68
°C/W
BGA Package Thermal Resistance,
Junction to Ambient – Natural Convection
BGA Package Thermal Resistance,
Junction to Ambient – Four layer (2s2p) board, natural
convection
1
2
3
4
5
6
7
8
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
the board thermal resistance.
Per SEMI G38-87 and JESD51-2 with the board horizontal.
These values are the mean + 3 standard deviations of characterized data.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
the board thermal resistance.
Per JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board (Four layer (2s2p) board, natural convection).
Indicates the thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per EIA/JESD51-2.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-3
Electrical Characteristics
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
TJ = TA + (RθJA x PD)
where:
TA = ambient temperature (°C)
RθJA = package junction to ambient resistance (°C/W)
PD = power dissipation in package
The junction to ambient thermal resistance is an industry standard value which provides a quick and easy
estimation of thermal performance. Unfortunately, the answer is only an estimate; test cases have
demonstrated that errors of a factor of two are possible. As a result, more detailed thermal characterization
is supplied.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal
resistance and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction to ambient thermal resistance (°C/W)
RθJC = junction to case thermal resistance (°C/W)
RθJA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced. The user controls the thermal environment to change the
case to ambient thermal resistance, RθCA. For instance, the air flow can be changed around the device, add
a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation
on the printed circuit board surrounding the device. This description is most useful for ceramic packages
with heat sinks where about 90% of the heat flow is through the case to the heat sink to ambient. For most
packages, a better model is required.
The simplest thermal model of a package which has demonstrated reasonable accuracy (about 20 percent)
is a two resistor model consisting of a junction to board and a junction to case thermal resistance. The
junction to case covers the situation where a heat sink will be used or where a substantial amount of heat
is dissipated from the top of the package. The junction to board thermal resistance describes the thermal
performance when most of the heat is conducted to the printed circuit board. It has been observed that the
thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the
board. temperature.
If the board temperature is known, an estimate of the junction temperature in the environment can be made
using the following equation:
TJ = TB + (RθJB x PD)
where:
TB = board temperature (°C)
RθJB = package junction to board resistance (°C/W)
PD = power dissipation in package (Ω)
MPC561/MPC563 Reference Manual, Rev. 1.2
F-4
Freescale Semiconductor
Electrical Characteristics
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction to board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two-resistor model can be used with the thermal simulation of the application (2), or a more accurate and
complex model of the package can be used in the thermal simulation. Consultation on the creation of the
complex model is available.
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT x PD)
where:
TT = thermocouple temperature on top of package (°C)
ΨJT = thermal characterization parameter
PD = power dissipation in package
The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC
using a 40 gauge type-T thermocouple epoxied to the top center of the package case. The thermocouple
should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is
placed over the thermocouple junction and over about one mm of wire extending from the junction. The
thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling
effects of the thermocouple wire.
F.3.1
Thermal References
The website for Semiconductor Equipment and Materials International is www.semi.org and their global
headquarters address is: 3081 Zanker Road, San Jose CA, 95134; 1-408-943-6900.
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents on
the WEB at www.global.ihs.com or 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance
and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp.
212-220.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-5
Electrical Characteristics
F.4
ESD Protection
Table F-3. ESD Protection
Characteristics
Symbol
Value
Units
2000
V
R1
1500
Ω
C
100
pF
200
V
R1
0
Ω
C
200
pF
Number of pulses per pin
Positive pulses (MM)
Negative pulses (MM)
Positive pulses (HBM)
Negative pulses (HBM)
—
—
—
—
3
3
1
1
Interval of Pulses
—
1
ESD for Human Body Model (HBM)1
HBM Circuit Description
ESD for Machine Model (MM)
MM Circuit Description
2
—
S
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
MPC561/MPC563 Reference Manual, Rev. 1.2
F-6
Freescale Semiconductor
Electrical Characteristics
F.5
DC Electrical Characteristics
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH)
Table F-4. DC Electrical Characteristics
Characteristic
1
1
2.6-V only Input High Voltage
except DATA[0:31] and EXTCLK
1a
2.6-V Input High Voltage
EXTCLK
2
DATA[0:31] Precharge Voltage 2
DATA[0:31] Precharge Voltage (Predischarge circuit
enabled)3
3
5-V Input only High Voltage 4
4
5-V Input High Voltage (QADC PQA, PQB)
5
MUXed 2.6-V/ 5-V pins
(GPIO muxed with Addr and Data)
2.6-V Input High Voltage Addr., Data
5-V Input High Voltage (GPIO)
Symbol
Min
Max
Unit
VIH2.6
2.0
VDDH + 0.3
V
VIHC
1.6
VDDH + 0.3
V
3.1
5.25
V
VDATAPC
VDATAPC5
VIH5
0.7 * VDDH
VDDH + 0.3
V
VIHA5
0.7 * VDDH
(VDDA |
VDDH) + 0.35
V
VIH2.6M
VIH5M
2.0
0.7 * VDDH
VDDH + 0.3
VDDH + 0.3
V
V
6
2.6-V Input Low Voltage
Except EXTCLK
VIL2.6
VSS – 0.3
0.8
V
7
2.6-V Input Low Voltage
EXTCLK
VIL2.6C
VSS – 0.3
0.4
V
8
5-V Input Low Voltage
VIL5
VSS – 0.3
0.48 * VDDH
V
9
5-V Input Low Voltage (QADC PQA, PQB)
VILA5
VSSA – 0.3
0.48 * VDDH
V
10
MUXed 2.6-V/ 5-V pins (GPIO muxed with Addr, Data)
2.6-V Input Low Voltage (Addr., Data)
5-V Input Low Voltage (GPIO)
VIL2.6M
VIL5M
VSS – 0.3
VSS – 0.3
0.8
0.48 * VDDH
V
11
QADC Analog Input Voltage6
Note: Assumes VDDA ≥ VDDH
VINDC
VSSH – 0.3
VDDH + 0.3
V
12
2.6-V Weak Pull-up/down Current
pull-up @ 0 to VIL2.6, pull-down @ VIH2.6 to VDD
IACT2.6V
20
130
µA
13
5-V Weak Pull-up/down Current6
pull-up @ 0 to VIL5, pull-down @ VIH5 to VDDH
IACT5V
20
130
µA
14
2.6-V Input Leakage Current6
pull-up/down inactive – measured @rails
IINACT2.6V
—
2.5
µA
15
5V Input Leakage Current6,7
pull-up/down inactive – measured @rails
IINACT5V
—
2.5
µA
16
QADC64 Input Current, Channel Off 8
PQA,
PQB
IOFF
-200
-200
200
200
nA
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-7
Electrical Characteristics
Table F-4. DC Electrical Characteristics (continued)
Characteristic
17
2.6-V Output High Voltage VDD = VDDL
2.6-V Output High Voltage (IOH = -1mA)
2.6-V Output High Voltage (IOH = -2mA)
Symbol
Min
VOH2.6
VOH2.6A
2.3
2.1
Max
Unit
—
V
18
5-V Output High Voltage VDD = VDDH (IOH= -2mA)
All 5-V only outputs except TPU.
VOH5
VDDH – 0.7
—
V
19
5-V Output High Voltage VDD = VDDH (IOH= -5mA)
For TPU pins Only
VOHTP5
VDDH – 0.65
—
V
20
MUXed 2.6-V/ 5-V pins (GPIO MUXed with Addr, Data)
2.6-V Output High Voltage (IOH = -1mA)
2.6-V Output High Voltage (IOH = -2mA)
5-V Output High Voltage (IOH = -2mA)
—
V
VOH2.6M
VOH2.6MA
VOH5M
2.3
2.1
VDDH – 0.7
VOL2.6
—
0.5
V
VOL5
—
0.45
V
VOLTP5
—
21
2.6-V Output Low voltage VDD = VDDL (IOL = 3.2mA)
22
5-V Output Low voltage VDD = VDDH (IOL = 2mA)
All 5-V only outputs except TPU
23
5-V Output Low voltage VDD = VDDH -TPU pins Only
IOL = 2mA
IOL = 10mA
24
MUXed 2.6-V/ 5-V pins (GPIO MUXed with Addr, Data)
2.6-V Output Low Voltage (IOL = 3.2mA)
5-V Output Low Voltage (IOL = 2mA)
V
VOL2.6M
VOL5M
0.5
0.45
25
Output Low Current (@ VOL2.6= 0.4 V)
IOL2.6
2.0
27
CLKOUT Load Capacitance – SCCR COM & CQDS
COM[0:1]= 0b01, CQDS = 0b1
COM[0:1]= 0b01 CQDS = 0b0
COM[0:1]= 0b00 CQDS = 0bx
CCLK
—
29
Capacitance for Input, Output, and Bidirectional Pins:
Vin = 0 V, f = 1 MHz (except QADC)
CIN
—
30
Load Capacitance for bus pins only 9
COM[0:1] of SCCR = 0b11
COM[0:1] of SCCR = 0b10
CL
—
31
Total Input Capacitance
PQA Not Sampling
PQB Not Sampling
V
0.45
1.0
—
mA
25
50
90
pF
pF
pF
7
pF
pF
25
50
pF
CIN
—
—
15
15
VH
0.5
—
IDDL
—
120
KAPWR (Crystal Frequency: 20 MHz)
IDDKAP
—
5
KAPWR (Crystal Frequency: 4 MHz)
IDDKAP
—
2
32
Hysteresis (Only IRQ, TPU, MIOS, GPIO, QADC (Digital
inputs) and HRESET, SRESET, PORESET) 10
33
Operating Current (2.6-V supplies) @ 40 MHz11,12
VDD/QVDDL/NVDDL
IRAMSTBY
IDDSRAM
VDDSYN
14
VDDF (Read, program, or erase)
VDDFSTOP16
VDDFDISABLED
16
50 x
10-3
V
1.7513
IDDSYN
—
2
IDDF
—
35
IDDFSTOP
—
10
IDDFDISB
—
100
mA
µA
MPC561/MPC563 Reference Manual, Rev. 1.2
F-8
Freescale Semiconductor
Electrical Characteristics
Table F-4. DC Electrical Characteristics (continued)
Characteristic
34
Symbol
Operating Current (5-V supplies)@ 40 MHz
VDDH
VDDA15
VFLASHF5 (Program or Erase)
VFLASHF5READ
VFLASHF5 (Stopped)
12
Operating Current (2.6-V supplies)@ 56
—
Unit
mA
20
5
1016
3
1
SIDDF5D
—
100
IDDL
—
210
IDDKAP
—
5
µA
MHz12
VDD/QVDDL/NVDDL
KAPWR (Crystal Frequency: 20 MHz)
KAPWR (Crystal Frequency: 4 MHz)
IDDKAP
—
2
IDDSRAM
50 x 10-3
1.7513
IDDSYN
—
2
IDDF
—
35
VDDFSTOP
IDDFSTOP
—
10
VDDFDISABLED
IDDFDISB
—
100
µA
20
5.0
1016
4
1
100
mA
mA
mA
mA
mA
µA
10
µA
110
15
8
mA
mA
mA
IRAMSTBY
VDDSYN (Crystal Frequency: 20 MHz)
VDDF (Read, program, or erase)16
36
Max
IDDH5
IDDA
IDDF5
IDDF5R
SIDDF5
VFLASHF5 (Disabled)
35
Min
Operating Current (5-V supplies)@ 56
VDDH
VDDA15
VFLASHF5 (Program or Erase)
VFLASHF5READ
VFLASHF5 (Stopped)
VFLASHF5 (Disabled)
MHz12, 15
—
IDDH5
IDDA
IDDF5
IDDF5R
SIDDF5
SIDDF5D
37
QADC64 Low Power Stop Mode (VDDA)
38
Low Power Current (QVDDL+ NVDDI+ VDD) @56 MHz
DOZE, Active PLL and Active Clocks
SLEEP, Active PLL with Clocks off
DEEP SLEEP, PLL and Clocks off
16Operating
39
NVDDL, QVDDL,VDD, VDDF
40
VFLASH Flash Operating/Programming Voltage16
IDDA
Voltage
41
Oscillator, Keep-Alive Registers Operating Voltage
42
N.A.
43
44
mA
17,18
—
—
IDDDZ
IDDSLP
IDDDPSLP
NVDDL, QVDDL,
VDD, VDDF
2.5
2.7
V
VFLASH
4.75
5.25
V
KAPWR
VDD - 0.2 V VDD
+ 0.2 V19
V
—
—
—
—
VDDH Operating Voltage
VDDH
4.75
5.25
V
QADC Operating Voltage
VDDA
4.75
5.25
V
45
Clock Synthesizer Operating Voltage
46
N.A.
Difference18
VDDSYN
—
47
VSS Differential Voltage
48
QADC64 Reference Voltage Low20
High20
49
QADC64 Reference Voltage
50
QADC64 VREF Differential Voltage
51
QADC64 Reference Supply Current, DC
QADC64 Reference Supply Current, Transient
52
QADC64 ALT Reference Voltage21
VDD – 0.2 V VDD
—
+ 0.2 V19
V
—
—
VSS – VSSA
-100
100
mV
VRL
VSSA
VSSA + 0.1
V
VRH
3.0
VDDA
V
VRH – VRL
3.0
5.25
V
IREF
IREFT
—
—
500
4.0
µA
mA
VARH
1.0
.75 * VDDA
V
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-9
Electrical Characteristics
Table F-4. DC Electrical Characteristics (continued)
Characteristic
53
Standby Supply Current
KAPWR only (4 MHz Crystal)
KAPWR only (20 MHz Crystal)
Measured @ 2.7 V
Symbol
Min
Max
Unit
2.0
5
mΑ
mΑ
—
ISBKAPWR4
ISBKAPWR20
53a IRAMSTBY Regulator Current Data Retention 17
Specified VDD applied (VDD, VDDH = VSS)
ISTBY
50 x 10-3
1.75
mA
53b IRAMSTBY Regulator Voltage for Data Retention17,22
(power-down mode) Specified VDD applied
(VDD, VDDH = VSS)21
VSTBY
1.35
1.95
V
mA
54
DC Injection Current per Pin GPIO, TPU, MIOS, QSMCM,
EPEE and 5 V pins 6, 23, 24
IIC5
-1.0
1.0
55
DC Injection Current per Pin 2.6 V 6, 24, 25, 26
IIC26
-1.0
1.0
mA
56
QADC64 Disruptive Input Current 24,27
INA
-3
3
mA
57
Power Dissipation – 56 MHz
40 MHz
PD
1.12
0.8
W
W
1
This characteristic is for 2.6-V output and 5-V input friendly pins.
VDATAPC is the maximum voltage the data pins can have been precharged to by an external device when the
MPC561/MPC563 data pins turn on as outputs. The 3.1-V maximum for VDATAPC is to allow the data pins to be driven
from an external memory running at a higher voltage. Note that if the data pins are precharged to higher than VDDL,
then the 50-pF maximum load characteristic must be observed.
3 The predischarge circuit is enabled by setting the PREDIS_EN bit to a “1” in the PDMCR2 register. VDATAPC is the
maximum voltage the data pins can have been precharged to by an external device when the MPC561/MPC563 data
pins turn on as outputs. The 5.25-V maximum for VDATAPC is to allow the data pins to be driven from an external
memory running at a higher voltage. Note that if the data pins are precharged to higher than VDDL, then the maximum
load characteristic must match the data bus drive setting and the data bus can withstand up to 3.6 volts for a cumulative
time of 24 hours over the lifetime of the device.
4 This characteristic is for 5-V output and 5-V input pins.
5 0.3V > V
DDA or VDDH, whichever is greater.
6 Within this range, no significant injection will be seen. See QADC64 Disruptive Input Current (I
NA).
7 During reset all 2.6V and 2.6V/5V pads will leak up to 10µA to QVDDL if the pad has a voltage > QVDDL.
8 Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each
8 to 12 °C, in the ambient temperature range of 50 to 125 °C.
9
All bus pins support two drive strengths capabilities, 25 pF and 50 pF. Current drive is less at the 25-pF
capacitive load. Both modes achieve 40-MHz (or, optionally, 56-MHz) timing.
10 Only IRQ, TPU, MIOS, GPIO, QADC (when digital inputs) and RESET pins have hysteresis, thus there is no hysteresis
specification on all other pins
11 Values to be characterized. Current consumption values will be updated as information becomes available. Initial
values are only estimates based on predicted capacitive differences between CDR1 and CDR3 as well as actual CDR1
measurements.
12 All power consumption specifications assume 50-pF loads and running a typical application. The power consumption
of some modules could go up if they are exercised heavier, but the power consumption of other modules would
decrease.
13
This value depends on the R value set by the user. Refer to Appendix C, “Clock and Board Guidelines.”
14 These power supplies are available on the MPC563 and MPC564 only.
15 Current measured at maximum system clock frequency with QADC active.
16
Transient currents can reach 50mA.
17 KAPWR and IRAMSTBY can be powered-up prior to any other supply or at the same time as the other 2.6 V supplies.
IRAMSTBY must lead or coincide with VDD; however it can lag KAPWR.
2
MPC561/MPC563 Reference Manual, Rev. 1.2
F-10
Freescale Semiconductor
Electrical Characteristics
18
This parameter is periodically sampled rather than 100% tested
Up to 0.5 V during power up/down.
20
To obtain full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA
21 When using the QADC in legacy mode it is recommended to connect this pin to 2.6V or 3.3V, however it can be
connected to 0V or 5V without damage to the device.
22
A resistor must be placed in series with the IRAMSTBY power supply. Refer to Appendix C, “Clock and Board
Guidelines.”
23
All injection current is transferred to the VDDH. An external load is required to dissipate this current to maintain the
power supply within the specified voltage range.
24
Absolute maximum voltage ratings for each pin (see Table F-1) must also be met during this condition.
25
Total injection current for all I/O pins on the chip must not exceed 20 mA (sustained current). Exceeding this limit can
cause disruption of normal operation.
26
Current refers to two QADC64 modules operating simultaneously.
27
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs
greater than VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the
presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.
19
F.6
Oscillator and PLL Electrical Characteristics
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH)
Table F-5. Oscillator and PLL
Characteristic
1
Symbol
Min
Typica
l
Oscillator Startup time (for typical crystal capacitive load)
4-MHz crystal
OSCstart4
20-MHz crystal
OSCstart20
TLOCK
Max
Unit
10
10
ms
ms
10001
Input
Clocks
2
PLL Lock Time
3
PLL Operating Range2
FVCOOUT
30
112
MHz
4
Crystal Operating Range, MODCK=0b010,0b110
MODCK[1:3] = 0b001, 0b011, 0b100, 0b101, 0b111
FCRYSTAL
3
15
5
25
MHz
MHz
5
PLL Jitter
PLL Jitter (averaged over 10 µs)
FJIT
FJIT10
-1%
-0.3%
+1%
+0.3%
—
6
Limp Mode Clock Out Frequency
—
33
173
MHz
7
Oscillator Bias Current (XTAL)
4 MHz
20 MHz
IBIAS
—
| 1.5 |
| 0.8 |
| 4.0 |
mA
mA
8
Oscillator Drive (XTAL)
IOSC
7
—
mA
9
Oscillator Bias Resistor
ROSC
0.5
3
MΩ
11
1
1
Assumes stable power and oscillator.
FVCOOUT is 2x the system frequency.
3
Estimated value, real values to be characterized and updated.
2
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-11
Electrical Characteristics
F.7
Flash Electrical Characteristics
The characteristics found in this section apply only to the MPC563.
Note: (VDDF = 2.6 V ± 0.1 V, VFLASH = 5.0 V ± 0.25 V, TA = TL to TH, TB = TL to TH)
Table F-6. Array Program and Erase Characteristics
Value
Symbol
Meaning
Minimum
Maximum
3
12
s
13
60
s
15
20
µs
Block Erase Time2
TERASE
2
TERASEM
Module Erase Time
TPROG
Word Programming Time
Units
Typical1
3,4
1
Typical program and erase times assume nominal supply values and 25 °C.
Erase time specification does not include pre-programming operation
3 Word size is 32 bits.
4 The maximum hardware programming time of the entire Flash (not including the shadow row) is 20 µs x (512 Kbytes
/ 4 bytes per word), or 131,072 words, (no software overhead).
2
Note: (VDDF = 2.6 V ± 0.1 V, VFLASH = 5.0 V ± 0.25 V, TA = TL to TH, TB = TL to TH)
Table F-7. CENSOR Cell Program and Erase Characteristics
Value
Symbol
Meaning
Units
Minimum
1
2
Typical1
Maximum
TCLEAR
CENSOR Bit Clear Time2
13
60
s
TSET
CENSOR Bit Set Time
115
250
µs
Typical set and clear times assume nominal supply values and 25 °C.
Clear time specification does not include pre-set operation.
Table F-8. Flash Module Life
Symbol
Array P/E
Cycles1
CENSOR Set/Clear
Cycles2
Meaning
Maximum number of Program/Erase cycles per block to guarantee
data retention.
Minimum number of Program/Erase cycles per bit before failure.
Array and CENSOR Data Minimum data retention at an average of 85 °C junction temperature.
Retention
Minimum data retention at an average of 125 °C junction temperature.
Value
1,000
100
Min 15 years3
Min 10 years3
1
A Program/Erase cycle is defined as switching the bits from 1 to 0 to 1.
A CENSOR Set/Clear cycle is defined as switching the bits from 1 to 0 to 1.
3
Maximum total time @ 150 °C junction temperature ≤ 1 year.
2
MPC561/MPC563 Reference Manual, Rev. 1.2
F-12
Freescale Semiconductor
Electrical Characteristics
F.8
Power-Up/Down Sequencing
The supply symbols used in this section are described in Table F-9.
.
Table F-9. Power Supply Pin Groups
Symbol
Types of Power Pins
VDDH
Supply to the 5-V pads for output driver (VDDH)
(High Voltage Supply Group)
Supply to the analog (QADC64E) circuitry (VDDA)
High voltage supply to the flash module (VFLASH)1
VDDL
(Low Voltage Supply Pins)
Supply to low voltage pad drivers (QVDDL, NVDDL)
Supply to all low voltage internal logic (VDD)
Supply to low voltage flash circuitry (VDDF)1
Supply to system PLL
VDDKA
(Low Voltage Keep-Alive
Supply Pins2
1
2
Supply to IRAMSTBY
Supply to oscillator and other circuitry for keep-alive functions (KAPWR).
These power supplies are only available on the MPC563 and MPC564.
Any supply in the VDDKA group can be powered with the VDDL if the function which it supplies is not
required during “Keep-alive.”
There are two power-up/down options. Choosing which one is required for an application will depend
upon circuitry connected to 2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Power-up/down
option A is required if 2.6-V compliant pins and dual 2.6-V/5-V compliant pins are connected to the 5-V
supply with a pull-up resistor or driven by 5-V logic during power-up/down. In applications for which this
scenario is not true the power-up/down option B may be implemented. Option B is less stringent and easier
to ensure over a variety of applications.
Refer to Table 2-1 for a list of 2.6 V and dual 2.6V/5 V compliant pins.
The power consumption during power-up/down sequencing will stay below the operating power
consumption specifications when following these guidelines.
NOTE:
The VDDH ramp voltage should be kept below 50V/ms and the VDDL ramp
rate less that 25V/ms.
F.8.1
Power-Up/Down Option A
The Option A power-up sequence (excluding VDDKA) is
1. VDDH ≤ VDDL + 3.1 V (VDDH cannot lead VDDL by more than 3.1 V)
2. VDDH ≥ VDDL - 0.5 V (VDDH cannot lag VDDL by more than 0.5 V)
The first step in the sequence is required is due to gate-to-drain stress limits for transistors in the pads of
2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Damage can occur if gate-to-drain voltage
potential is greater than 3.1 V. This is only a concern at power-up/down. The second step in the sequence
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-13
Electrical Characteristics
is required is due to ESD diodes in the pad logic for dual 2.6-V/5-V compliant pins and 2.6-V pins. The
diodes are forward biased when VDDL is greater than VDDH and will start to conduct current.
Figure F-1 illustrates the power-up sequence if no keep-alive supply is required. Figure F-2 illustrates the
power-up sequence if a keep-alive supply is required. The keep-alive supply should be powered-up at the
same instant or before both the high voltage and low voltage supplies are powered-up.
VDDH
3.1-V lead
VDDL
0.5-V lag
VDDH cannot lead VDDL by more than 3.1 V
VDDH cannot lag VDDL by more than 0.5 V
Figure F-1. Option A Power-Up Sequence Without Keep-Alive Supply
VDDH
3.1-V lead
VDDL
VDDKA
0.5-V lag
VDDH cannot lead VDDL by more than 3.1 V
VDDH cannot lag VDDL by more than 0.5 V
Figure F-2. Option A Power-Up Sequence With Keep-Alive Supply
The option A power-down sequence (excluding VDDKA) is
1. VDDH ≤ VDDL + 3.1 V (VDDH cannot lag VDDL by more than 3.1 V)
2. VDDH ≥ VDDL - 0.5 V (VDDH cannot lead VDDL by more than 0.5 V)
Figure F-3 illustrates the power-down sequence if no keep-alive supply is required.
MPC561/MPC563 Reference Manual, Rev. 1.2
F-14
Freescale Semiconductor
Electrical Characteristics
VDDH
VDDL
3.1-V Max
0.5-V Max
Ramp down rates may differ
with load, so care should be taken
maintain VDDH with respect to VDDL.
VDDH cannot lag VDDL by more than 3.1 V.
VDDH ≥ VDDL - 0.5 V (VDDH cannot lead VDDL by more than 0.5 V.)
Figure F-3. Option A Power-Down Sequence Without Keep-Alive Supply
Figure F-4 illustrates the power-down sequence if a keep-alive supply is required.
VDDH
VDDL
VDDKA
0.5-V Max
3.1-V Max
Ramp down rates may
differ with load.
VDDH cannot lag VDDL by more than 3.1 V.
VDDH ≥ VDDL - 0.5 V (VDDH cannot lead VDDL by more than 0.5 V.)
Figure F-4. Option A Power-Down Sequence With Keep-Alive Supply
F.8.2
Power-Up/Down Option B
A less stringent power-up sequence may be implemented if 2.6-V compliant pins and dual 2.6-V/5-V
compliant pins are NOT connected to the 5-V supply with a pull-up resistor or driven by 5-V logic during
power-up/down.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-15
Electrical Characteristics
The option B power-up sequence (excluding VDDKA) is:
1. VDDH > VDDL - 0.5 V (VDDH cannot lag VDDL by more than 0.5 V)
Thus the VDDH supply group can be fully powered-up prior to power-up of the VDDL supply group, with
no adverse affects to the device.
The requirement that VDDH cannot lag VDDL by more than 0.5 V is due to ESD diodes in the pad logic for
dual 2.6-V/5-V compliant pins and 2.6-V pins. The diodes are forward biased when VDDL is greater than
VDDH and will start to conduct current.
Figure F-5 illustrates the power-up sequence if no keep-alive supply is required. Figure F-6 illustrates the
power-up sequence if a keep-alive supply is required. The keep-alive supply should be powered-up at the
same time or before both the high voltage and low voltage supplies are powered-up.
VDDH
VDDL
0.5-V lag
VDDH cannot lag VDDL by more than 0.5 V
Figure F-5. Option B Power-Up Sequence Without Keep-Alive Supply
VDDH
VDDL
VDDKA
0.5-V lag
VDDH cannot lag VDDL by more than 0.5 V
Figure F-6. Option B Power-Up Sequence With Keep-Alive Supply
The option B power-down sequence (excluding VDDKA) is:
1. The VDDL supply group can be fully powered-down prior to power-down of the VDDH supply
group, with no adverse affects to the device.
MPC561/MPC563 Reference Manual, Rev. 1.2
F-16
Freescale Semiconductor
Electrical Characteristics
For power-down, the low voltage supply should come down before the high voltage supply, although with
varying loads, the high voltage may actually get ahead.
Figure F-7 illustrates the power-down sequence if no keep-alive supply is required. Figure F-8 illustrates
the power-down sequence if a keep-alive supply is required.
VDDH
VDDH ≤ 5.25V
VDDL
0.5-V lag
Ramp down rates may
differ with load.
VDDH cannot lead VDDL by more than 0.5V
Figure F-7. Option B Power-Down Sequence Without Keep-Alive Supply
VDDH
VDDL
VDDKAP
0.5-V lag
Ramp down rates may
differ with load.
VDDH cannot lead VDDL by more than 0.5V
Figure F-8. Option B Power-Down Sequence with Keep-Alive Supply
F.9
F.9.1
Issues Regarding Power Sequence
Application of PORESET or HRESET
When VDDH is rising and VDDL is at 0.0 V, as VDDH reaches 1.6 V, all 5 V drivers are tristated. Before
VDDH reaches 1.6V, all 5 V outputs are unknown. If VDDL is rising and VDDH is at least 3.1V greater than
VDDL, then the 5 V drivers can come out of tristate when VDDL reaches 1.1V, and the 2.6 V drivers can
start driving when VDDL reaches 0.5 V. For these reasons, the PORESET or HRESET signal must be
asserted during power-up before VDDL is above 0.5 V.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-17
Electrical Characteristics
If the PORESET or HRESET signal is not asserted before this condition, there is a possibility of disturbing
the programmed state of the flash. In addition, the state of the pads are indeterminant until PORESET or
HRESET propagates through the device to initialize all circuitry.
F.9.2
Keep-Alive RAM
PORESET or HRESET must be asserted during power-down prior to any supply dropping out of specified
operating conditions.
An additional constraint is placed on PORESET assertion since it is an asynchronous input. To assure that
the assertion of PORESET does not potentially cause stores to keep-alive RAM to be corrupted (store
single or store multiple) or non-coherent (store multiple), either of the following solutions is
recommended:
• Assert HRESET at least 0.5 µs prior to when PORESET is asserted.
• Assert IRQ0 (non-maskable interrupt) at least 0.5 µs prior to when PORESET is asserted. The
service routine for IRQ0 should not perform any writes to keep-alive RAM.
The amount of delay that should be added to PORESET assertion is dependent upon the frequency of
operation and the maximum number of store multiples executed that are required to be coherent. If store
multiples of more than 28 registers are needed and if the frequency of operation is lower that 56 MHz, the
delay added to PORESET assertion will need to be greater than 0.5 µs. In addition, if KAPWR features
are being used, PORESET should not be driven low while the VDDH and VDDL supplies are off.
F.10
AC Timing
Figure F-9 displays generic examples of MPC561/MPC563 timing. Specific timing diagrams are shown
in Figure F-10 through Figure F-36.
MPC561/MPC563 Reference Manual, Rev. 1.2
F-18
Freescale Semiconductor
Electrical Characteristics
CLKOUT
VDD/2
VDD/2
VDD/2
A
B
5-V OUTPUTS
VOH
VOL
VOH
VOL
A
B
5-V OUTPUTS
VOH
VOH
VOL
VOL
A
B
VDD/2
ADDR/DATA/CTRL
A
B
ADDR/DATA/CTRL OUTPUTS
VDD/2
C
VIH
VIL
5-V INPUTS
D
VIH
VIL
C
VIH
VIL
5-V INPUTS
C
ADDR/DATA/CTRL
D
VIH
VIL
D
VDD/2
VDD/2
C
ADDR/DATA/CTRL INPUTS
VDD/2
A. Maximum Output Delay Specification
B. Minimum Output Hold Time
D
VDDVDD/2
C. Minimum input Setup Time Specification
D. Minimum input Hold Time Specification
Figure F-9. Generic Timing Examples
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-19
Electrical Characteristics
Table F-10. Bus Operation Timing
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
56 MHz1
40 MHz
Unit
Characteristic
Min
1
CLKOUT Period (TC)
1a
ENGCLK Frequency
5 V – EECLK = 01
2. 6 V – EECLK = 00
Max
25
Min
Max
17.86
ns
MHz
10
20
10
28
2
Clock pulse width low
12.5 –2%
12.5 + 2%
8.93 –2%
8.93 + 2%
ns
3
Clock pulse width high
12.5 – 2%
12.5 + 2%
8.93 – 2%
8.93 + 2%
ns
4
CLKOUT rise time
ABUS/DBUS rise time
3.5
3.0
3.5
3.0
ns
5
CLKOUT fall time
ABUS/DBUS fall time
3.5
3.0
3.5
3.0
ns
6
Circuit Parameter
7
CLKOUT to Signal Invalid
(Hold Time)
ADDR[8:31]
RD/WR
BURST
D[0:31]
7a
7b
7c
7
CLKOUT to Signal Invalid:
(Hold Time)
TSIZ[0:1]
RSV
AT[0:3]
BDIP
PTR
RETRY
CLKOUT to Signal Invalid
(Hold Time)2
BR
BG
FRZ
VFLS[0:1]
VF[0:2]
IWP(0:2]
LWP[0:1]
STS3
Slave mode CLKOUT to
Signal Invalid
D[0:31]
5
ns
3.5
3.5
ns
3.5
3.5
ns
3.5
3.5
ns
3.5
3.5
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
F-20
Freescale Semiconductor
Electrical Characteristics
Table F-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
56 MHz1
40 MHz
Unit
Characteristic
8
Min
Max
Min
Max
6.25
14
4.5
11
ns
CLKOUT to Signal Valid
TSIZ[0:1]
RSV
AT[0:3]
BDIP
PTR
RETRY
6.25
13
4.5
9.5
ns
CLKOUT to Signal Valid2
BR
BG
VFLS[0:1]
VF[0:2]
IWP[0:2]
FRZ
LWP[0:1]
STS valid.
6.25
14
4.5
10.5
ns
14
11
ns
16
16
ns
CLKOUT to Signal Valid
ADDR[8:31]
RD/WR
BURST
D[0:31]4
8a
8b
8c
Slave Mode CLKOUT to
Signal Valid
D[0:31]
8d
CLKOUT to Data
Pre-discharge time
8e
CLKOUT to Data
Pre-discharge start
9
CLKOUT to High Z
ADDR[8:31]
RD/WR
BURST
D[0:31]
TSIZ[0:1]
RSV
AT[0:3]
PTR
RETRY
3
10
CLKOUT to TS, BB assertion
10a
CLKOUT to TA, BI assertion
(when driven by the
Memory Controller)
3
ns
6.25
13
4.5
9.5
ns
7.25
14
5.5
10.5
ns
8.5
ns
8.5
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-21
Electrical Characteristics
Table F-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
56 MHz1
40 MHz
Unit
Characteristic
Min
10b
CLKOUT to RETRY assertion
(when driven by the
Memory Controller)
Max
Min
10
Max
10
ns
11
CLKOUT to TS, BB negation
7.25
14
5.5
10.5
ns
11a
CLKOUT to TA, BI negation
(when driven by the
Memory Controller)
2
11
2
11
ns
CLKOUT to RETRY negation
(when driven by the
Memory Controller)
2
11
2
11
ns
6.25
20
4.5
16
ns
11b
12
CLKOUT to TS, BB High Z
12a
CLKOUT to TA, BI High Z
(when driven by the
Memory Controller)
15
15
ns
13
CLKOUT to TEA assertion
8.5
8.5
ns
14
CLKOUT to TEA High Z
15
15
ns
15
Input Valid to CLKOUT
(Setup Time)
TA
TEA
BI3
12
8.5
ns
Input Valid to CLKOUT
(Setup Time)
KR
CR
RETRY
10
7.25
ns
Input Valid to CLKOUT
(Setup Time)
BB
BG
BR2
8
6.5
ns
2
2
ns
15a
15b
16
CLKOUT to Signal Invalid
(Hold Time)
TA
TEA
BI
BB
BG
BR2, 3
MPC561/MPC563 Reference Manual, Rev. 1.2
F-22
Freescale Semiconductor
Electrical Characteristics
Table F-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
56 MHz1
40 MHz
Unit
Characteristic
Min
16a
17
17b
18
19
19a
19b
19c
20
Max
Min
Max
CLKOUT to Signal Invalid
(Hold Time)
RETRY
KR
CR
2
2
ns
Signal Valid to CLKOUT
Rising Edge (Setup Time)
D[0:31]4
6
6
ns
3
3
2
2
Signal Valid to CLKOUT
Rising Edge (Short Setup
Time, SST = 1)
D[0:31]4
CLKOUT Rising Edge to Signal
Invalid (Hold Time)
D[0:31]4
CLKOUT Rising Edge to CS
asserted
-GPCM- ACS = 00
7.25
CLKOUT Falling Edge to CS
asserted
-GPCM- ACS = 10, TRLX = 0
or 1
CLKOUT Falling Edge to CS
asserted
-GPCM- ACS = 11, TRLX = 0
or 1
CLKOUT Falling Edge to CS
asserted
-GPCM- ACS = 11, TRLX = 0,
EBDF = 1
CLKOUT Rising Edge to CS
negated
-GPCM- Read Access
or Write access when CSNT =
0 or write access when CSNT =
1 and ACS = 00
15
6.5
8
ns
11.5
ns
6
ns
6.25
14
5.5
10.5
ns
6.25
17
6.69
12.69
ns
1
8
1
7
ns
21
ADDR[8:31] to CS asserted
-GPCM- ACS = 10, TRLX = 0
0.75
1
ns
21a
ADDR[8:31] to CS asserted
-GPCM- ACS = 11, TRLX = 0
8
6
ns
22
CLKOUT Rising Edge to
OE, WE[0:3]/BE[0:3]
asserted
1
8
1
6
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-23
Electrical Characteristics
Table F-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
56 MHz1
40 MHz
Unit
Characteristic
Min
Max
Min
Max
8
1
6
23
CLKOUT Rising Edge to OE n
egated
1
24
ADDR[8:31] to CS asserted
-GPCM- ACS = 10, TRLX = 1
23
16.42
ns
24a
ADDR[8:31] to CS asserted
-GPCM- ACS = 11, TRLX = 1
28
20
ns
25
CLKOUT Rising Edge to
WE[0:3]/BE[0:3] negated
-GPCM-write access CSNT =
‘0‘
25a
25b
25c
25d
26
26a
CLKOUT Falling Edge to
WE[0:3]/BE[0:3] negated
-GPCM-write access
TRLX = ‘0’ or ‘1’, CSNT = ‘1,
EBDF = 0’.
CLKOUT Falling Edge to CS
negated
-GPCM-write access
TRLX = ‘0’ or ‘1’, CSNT = ‘1’,
ACS = ‘10’ or ACS=’11’,
EBDF = 0
CLKOUT Falling Edge to
WE[0:3]/BE[0:3] negated
-GPCM-write access
TRLX = ‘0’, CSNT = ‘1,
EBDF = 1’.
CLKOUT Falling Edge to CS
negated
-GPCM-write access
TRLX = ‘0’, CSNT = ‘1’,
ACS = ‘10’ or ACS=’11’,
EBDF = 1
WE[0:3]/BE[0:3] negated to
D[0:31] High Z
-GPCM- write access, CSNT =
‘0’
WE[0:3]/BE[0:3] negated to
D[0:31] High Z
-GPCM- write access,
TRLX = ‘0’, CSNT = ‘1’,
EBDF = 0
7.5
ns
6
ns
6.25
14
5.5
10.5
ns
6.25
14
5.5
10.5
ns
6.25
17
5.5
12.69
ns
6.25
17
6.25
17
ns
3
2.25
ns
8
5.71
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
F-24
Freescale Semiconductor
Electrical Characteristics
Table F-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
56 MHz1
40 MHz
Unit
Characteristic
Min
26b
26c
26d
26e
26f
26g
26h
26i
27
CS negated to D[0:31], High Z
-GPCM- write access,
ACS = ‘00’,
TRLX = ‘0’ & CSNT = ‘0’
Max
Min
Max
3
2.25
ns
CS negated to D[0:31], High Z
-GPCM- write access,
TRLX = ‘0’, CSNT = ‘1’,
ACS = ‘10’ or ACS=’11’,
EBDF = 0
8
5.71
ns
WE[0:3]/BE[0:3] negated to
D[0:31] High Z
-GPCM- write access,
TRLX = ‘1’, CSNT = ‘1’,
EBDF = 0
28
20
ns
CS negated to D[0:31] High Z
-GPCM- write access,
TRLX = ‘1’, CSNT = ‘1’,
ACS = ‘10’ or ACS=’11’,
EBDF = 0
28
20
ns
WE[0:3]/BE[0:3] negated to
D[0:31] HighZ
-GPCM- write access,
TRLX = ‘0’, CSNT = ‘1’,
EBDF = 1
5
3.75
ns
CS negated to D[0:31] High Z
-GPCM- write access,
TRLX = ‘0’, CSNT = ‘1’,
ACS = ‘10’ or ACS=‘11’,
EBDF = 1
5
3.75
ns
WE[0:3]/BE[0:3] negated to
D[0:31] High Z
-GPCM- write access,
TRLX = ‘1’, CSNT = ‘1’,
EBDF = 1
24
17.25
ns
CS negated to D[0:31] High Z
-GPCM- write access,
TRLX = ‘1’, CSNT = ‘1’,
ACS = ‘10’ or ACS=’11’,
EBDF = 1
24
17.25
ns
CS, WE[0:3]/BE[0:3] negated
to ADDR[8:31] invalid -GPCMwrite access5
0.75
1
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-25
Electrical Characteristics
Table F-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
56 MHz1
40 MHz
Unit
Characteristic
Min
27a
Max
Min
Max
WE[0:3]/BE[0:3] negated to
ADDR[8:31]
Invalid -GPCM- write access,
TRLX=‘0’, CSNT = ‘1’.
8
5.71
ns
28
20
ns
4
3
ns
24
17.25
ns
9
6
ns
5
5
ns
CS negated to ADDR[8:31]
Invalid -GPCM- write
access, TRLX=’0’, CSNT = ‘1’,
ACS = 10,ACS = =‘11’,
EBDF = 0
27b
WE[0:3]/BE[0:3] negated to
ADDR[8:31]
Invalid -GPCM- write access,
TRLX=’1’, CSNT = '1’.
CS negated to ADDR[8:31]
Invalid -GPCM- write
access, TRLX=’1’, CSNT = '1’,
ACS = 10,ACS = =’11’,
EBDF = 0
27c
WE[0:3]/BE[0:3] negated to
ADDR[8:31] invalid
-GPCM- write access,
TRLX=’0’, CSNT = '1’.
CS negated to ADDR[8:31]
Invalid -GPCM- write access,
TRLX=’0’, CSNT = '1’,
ACS = 10,ACS = =’11’,
EBDF = 1
27d
WE[0:3]/BE[0:3] negated to
ADDR[8:31]
Invalid -GPCM- write access,
TRLX=’1’, CSNT = '1’.
CS negated to ADDR[8:31]
Invalid -GPCM- write access,
TRLX=’1’, CSNT = '1’,
ACS = 10,ACS = =’11’,
EBDF = 1
28
28a
ADDR[8:31], TSIZ[0:1],
RD/WR, BURST, valid to
CLKOUT Rising Edge. (Slave
mode Setup Time)
Slave Mode
D[0:31] valid to CLKOUT
Rising Edge
MPC561/MPC563 Reference Manual, Rev. 1.2
F-26
Freescale Semiconductor
Electrical Characteristics
Table F-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
56 MHz1
40 MHz
Unit
Characteristic
Min
1
2
3
4
5
Max
Min
Max
29
TS valid to CLKOUT Rising
Edge (Setup Time)
7
5
ns
30
CLKOUT Rising Edge to TS
Valid (Hold Time).
5
5
ns
56-MHz operation is available as an option. Some parts (without the 56-MHz option) will operate at a
maximum frequency of 40 MHz.
The timing for BR output is relevant when the MPC561/MPC563 is
selected to work with external bus arbiter. The timing for BG output is relevant when the
MPC561/MPC563 is selected to work with internal bus arbiter.
The setup times required for TA, TEA, and BI are relevant only when they are supplied by the external
device (and not the memory controller).
The maximum value of spec 8 for DATA[0:31] pins must be extended by 1.1 ns if the pins have been
precharged to greater than VDDL. This is the case if an external slave device on the bus is running at
the max. value of VDATAPC. This is currently specified at 3.1 V. The 1.1 ns addition to spec 8 reflects
the expected timing degradation for 3.1 V.
The timing 27 refers to CS when ACS = ‘00’ and to WE[0:3]/BE[0:3] when CSNT = ‘0’.
NOTE
The D[0:31] input timings 17 and 18 refer to the rising edge of the CLKOUT
in which the TA input signal is asserted.
CLKOUT
4
3
2
5
1
Figure F-10. CLKOUT Pin Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-27
Electrical Characteristics
CLKOUT
8
9
7
OUTPUT
SIGNALS
8a
9
7a
OUTPUT
SIGNALS
8b
7b
OUTPUT
SIGNALS
Figure F-11. Synchronous Output Signals Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
F-28
Freescale Semiconductor
Electrical Characteristics
CLKOUT
TS
8e
DATA
5.25V
< 3.1V
2.6V
0V
8d
sp8e: clkout to predischarge drivers enabled
sp8d: clkout to data below 3.1V
Figure F-12. Predischarge Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-29
Electrical Characteristics
CLKOUT
12
10
11
TS, BB
12a
10a
11a
TA, BI
13
14
TEA
Figure F-13. Synchronous Active Pull-Up And Open Drain
Outputs Signals Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
F-30
Freescale Semiconductor
Electrical Characteristics
CLKOUT
15
16
TA, BI
15a
16a
TEA, KR,
RETRY, CR
15b
16
BB, BG, BR
Figure F-14. Synchronous Input Signals Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-31
Electrical Characteristics
CLKOUT
15a
16
TA
17
18
DATA[0:31]
Figure F-15. Input Data Timing In Normal Case
MPC561/MPC563 Reference Manual, Rev. 1.2
F-32
Freescale Semiconductor
Electrical Characteristics
CLKOUT
10
11
TS
8
ADDR[8:31]
19
20
CSx
22
23
OE
25
WE[0:3]/BE[0:3]
17
DATA[0:31]
18
Figure F-16. External Bus Read Timing (GPCM Controlled – ACS = ‘00’)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-33
Electrical Characteristics
CLKOUT
10
11
TS
8
ADDR[8:31]
19a
20
CSx
OE
21
23
22
17
DATA[0:31]
18
Figure F-17. External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’)
MPC561/MPC563 Reference Manual, Rev. 1.2
F-34
Freescale Semiconductor
Electrical Characteristics
CLKOUT
10
11
TS
8
ADDR[8:31]
19b
CSx
20
19c
21a
OE
23
22
17
DATA[0:31]
18
Figure F-18. External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-35
Electrical Characteristics
CLKOUT
10
11
TS
8
ADDR[8:31]
19a
20
CSx
24
OE
23
24a
19b
19c
17
DATA[0:31]
18
Figure F-19. External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’)
CLKOUT
10
TS
11
9
8
ADDR[8:31]
Figure F-20. Address Show Cycle Bus Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
F-36
Freescale Semiconductor
Electrical Characteristics
CLKOUT
10
11
TS
8
27
ADDR[8:31]
CSx
WE[0:3]/BE[0:3]
8
DATA[0:31]
9
Figure F-21. Address and Data Show Cycle Bus Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-37
Electrical Characteristics
CLKOUT
10
11
TS
8
27
ADDR[8:31]
19
20
CSx
26b
22
25
WE[0:3]/BE[0:3]
23
OE
26
8
DATA[0:31]
9
Figure F-22. External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’)
MPC561/MPC563 Reference Manual, Rev. 1.2
F-38
Freescale Semiconductor
Electrical Characteristics
CLKOUT
10
11
TS
27c
8
27a
19
20
ADDR[8:31]
CSx
25b
25d
22
26c 26g
WE[0:3]/BE[0:3]
23
26a 26g
OE
25a
25c
8
D[0:31]
9
Figure F-23. External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-39
Electrical Characteristics
CLKOUT
10
11
TS
27d 27b
8
ADDR[8:31]
19
20
CSx
25b
25d
22
26i 26e
WE[0:3]/BE[0:3]
23
26h 26d
OE
26b
25a
25c
8
DATA[0:31]
9
Figure F-24. External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’)
MPC561/MPC563 Reference Manual, Rev. 1.2
F-40
Freescale Semiconductor
Electrical Characteristics
CLKOUT
30
29
TS
28
ADDR[8:31],
TSIZ[0:1],
RD/WR,
BURST,
BDIP
12a
10a
11a
TA,
BI
13
14
TEA
8
DATA[0:31]
9
10b
11b
RETRY
Figure F-25. External Master Read From Internal Registers Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-41
Electrical Characteristics
CLKOUT
30
29
TS
28
ADDR[8:31],
TSIZ[0:1],
RD/WR,
BURST
12a
10a
11a
TA,
BI
13
14
TEA,
28a
DATA[0:31]
18
10b
RETRY
11b
Figure F-26. External Master Write To Internal Registers Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
F-42
Freescale Semiconductor
Electrical Characteristics
Table F-11. Interrupt Timing
Note: (TA = TL to TH)
40 MHz
56 MHz
Characteristic
Unit
Min
Max
Min
Max
33
IRQx Pulse width Low
TC
TC
ns
34
IRQx Pulse width High; Between Level IRQ
TC
TC
ns
35
IRQx Edge to Edge time
4 * TC
4 * TC
ns
IRQx
35
34
33
Level IRQ
Edge IRQ
Figure F-27. Interrupt Detection Timing for External Edge Sensitive Lines
F.10.1
Debug Port Timing
Table F-12. Debug Port Timing
Note: (TA = TL to TH)
40 MHz
56 MHz
Characteristic
Unit
Min
Max
Min
Max
36
DSCK Cycle Time
50
—
37.4
—
ns
37
DSCK Clock Pulse Width
25
—
18.7
—
ns
38
DSCK Rise and Fall Times
0
7
0
7
ns
39
DSDI Input Data Setup Time
15
—
15
—
ns
40
DSDI Data Hold Time
5
—
5
—
ns
41
DSCK low to DSDO Data Valid
0
18
0
18
ns
42
DSCK low to DSDO Invalid
0
—
0
—
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-43
Electrical Characteristics
DSCK
36
37
37
36
38
38
Figure F-28. Debug Port Clock Input Timing
DSCK
39
40
DSDI
41
42
DSDO
Figure F-29. Debug Port Timings
MPC561/MPC563 Reference Manual, Rev. 1.2
F-44
Freescale Semiconductor
Electrical Characteristics
F.11
READI Electrical Characteristics
The AC electrical characteristics (56 MHz) are described in the following tables and figures
Table F-13. READI AC Electrical Characteristics
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH 50 pF load unless noted otherwise)
Number
Characteristic
Min
Max
Unit
17.9
—
ns
1
MCKO Cycle Time (Tco)
2
MCKO Duty Cycle
40
60
%
3
Output Rise and Fall Times
0
3
ns
4
MCKO low to MDO Data Valid
-1.79
3.58
ns
5
MCKI Cycle Time (Tci)
35.6
—
ns
6
MCKI Duty Cycle
40
60
%
7
Input Rise and Fall Times
0
3
ns
8
MDI, EVTI, MSEI Setup Time
7.12
—
ns
9
MDI Hold TIme
3.56
—
ns
10
RSTI Pulse Width
71.6
—
ns
11
MCKO low to MSEO Valid
-1.79
3.58
ns
12
EVTI Pulse Width
71.6
—
ns
13
EVTI to RSTI Setup
(at reset only)
(4.0) x TC
—
ns
14
EVTI to RSTI Hold
(at reset only)
(4.0) x TC
—
ns
MCKI
8
MDI, EVTI,MSEI
9
Input Data Valid
Figure F-30. Auxiliary Port Data Input Timing Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-45
Electrical Characteristics
MCKO
MDO, MSEO
4
11
Output Data Valid
Figure F-31. Auxiliary Port Data Output Timing Diagram
MDO and MSEO data is held valid until the next MCKO low transition.
When RSTI is asserted, EVTI is used to enable or disable the auxiliary port. Because MCKO probably is
not active at this point, the timing must be based on the system clock. Since the system clock is not realized
on the connector, its value must be known by the tool.
RSTI
13
14
EVTI
Figure F-32. Enable Auxiliary From RSTI
RSTI
13
14
EVTI
Figure F-33. Disable Auxiliary From RSTI
MPC561/MPC563 Reference Manual, Rev. 1.2
F-46
Freescale Semiconductor
Electrical Characteristics
F.12
RESET Timing
Table F-14. RESET Timing
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH)
40 MHz
Characteristic
56 MHz
Expression
Unit
Min
Max
Min
Max
43
CLKOUT to HRESET high
impedance
20
20
ns
44
CLKOUT to SRESET high
impedance
20
20
ns
45
RSTCONF pulse width
46
17 * TC
425
302
ns
Configuration Data to HRESET
rising edge Setup Time
15 * TC + TCC
382
272
ns
47
Configuration Data to RSTCONF
rising edge set up time
15 * TC + TCC
382
272
ns
48
Configuration Data hold time after
RSTCONF negation
0
0
ns
49
Configuration Data hold time after
HRESET negation
0
0
ns
49a
RSTCONF hold time after HRESET
negation1
50
35
50
HRESET and RSTCONF asserted to
Data out drive
25
25
ns
51
RSTCONF negated to Data out high
impedance
25
25
ns
52
CLKOUT of last rising edge before
chip tristates HRESET to Data out
high impedance
25
25
ns
53
DSDI, DSCK set up
75
55
ns
54
DSDI, DSCK hold time
0
0
ns
55
SRESET negated to CLKOUT
rising edge for DSDI and DSCK
sample
200
142
ns
55a
HRESET, SRESET, PORESET
pulse width 2
100
100
ns
3 * TC
8 * TC
Weak pull-ups and pull-downs used for Reset timing will comply with the 130 µA mode select current
outlined in Table F.5 on page F-7 The system requires two clocks of hold time on
RSTCONF/TEXP after negation of HRESET. The simplest way to insure meeting this requirement in
systems that require the use of the TEXP function, is to connect RSTCONF/TEXP to SRESET.
2 HRESET, SRESET and PORESET have a glitch detector to ensure that spikes less than 20 ns are rejected.
The internal HRESET, SRESET and PORESET will assert only if these signals are
asserted for more than 100 ns
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-47
Electrical Characteristics
HRESET
45
49a
RSTCONF
49
46
48
DATA[0:31] (IN)
47
Figure F-34. Reset Timing – Configuration from Data Bus
MPC561/MPC563 Reference Manual, Rev. 1.2
F-48
Freescale Semiconductor
Electrical Characteristics
CLKOUT
43
55a
HRESET
RSTCONF
51
50
52
DATA[0:31] (OUT)
(Weak)
Figure F-35. Reset Timing – Data Bus Weak Drive During Configuration
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-49
Electrical Characteristics
CLKOUT
44
55
SRESET
53
53
54
54
DSCK, DSDI
Figure F-36. Reset Timing – Debug Port Configuration
F.13
IEEE 1149.1 Electrical Characteristics
Table F-15. JTAG Timing
Note: (TA = TL to TH)
10 MHz1
Characteristic
Min
Max
Unit
56
TCK Cycle Time1 (JTAG clock)
100
—
ns
57
TCK Clock Pulse Width Measured at VDD/2
50
—
ns
58
TCK Rise and Fall Times
0
10
ns
59
TMS, TDI Data Setup Time
5
ns
60
TMS, TDI Data Hold Time
25
ns
61
TCK Low to TDO Data Valid
62
TCK Low to TDO Data Invalid
63
TCK Low to TDO High Impedance
20
ns
66
TCK Falling Edge to Output Valid
50
ns
67
TCK Falling Edge to Output Valid out of High Impedance
50
ns
68
TCK Falling Edge to Output High Impedance
50
ns
69
Boundary Scan Input Valid to TCK Rising Edge
50
ns
70
TCK Rising Edge to Boundary Scan Input Invalid
50
ns
20
0
ns
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
F-50
Freescale Semiconductor
Electrical Characteristics
1
JTAG timing (TCK) is only tested at 10 MHz. TCK is the operating clock of the MPC561/MPC563 in JTAG mode.
TCK
57
56
57
58
Figure F-37. JTAG Test Clock Input Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-51
Electrical Characteristics
TCK
59
60
TMS, TDI
61
63
62
TDO
Figure F-38. JTAG Test Access Port Timing Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
F-52
Freescale Semiconductor
Electrical Characteristics
TCK
66
68
OUTPUT
SIGNALS
67
OUTPUT
SIGNALS
70
69
OUTPUT
SIGNALS
Figure F-39. Boundary Scan (JTAG) Timing Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
F-53
Electrical Characteristics
F.14
QADC64E Electrical Characteristics
Table F-16. QADC64E Conversion Characteristics
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH)
Num
Parameter
97
QADC Clock (QCLK) Frequency1
98
Conversion Cycles2
Legacy mode: QADCMCR[FLIP] = 0
Enhanced mode: QADCMCR[FLIP] = 1
99
Symbol
Min
Max
Units
FQCLK
0.5
3.0
MHz
CC
CC
12
14
28
20
QCLK cycles
QCLK cycles
14
µs
µs
10
µs
µs
Conversion Time
FQCLK = 2.0 MHz1
Legacy mode: QADCMCR[FLIP] = 0
Min = CCW[IST] =0b00, CCW[BYP] = 0
Max = CCW[IST] =0b11, CCW[BYP] = 1
6.0
TCONV
Enhanced mode: QADCMCR[FLIP] = 1
Min = CCW[IST] =0b0
Max = CCW[IST] =0b1
5
6
7
µs
Resolution3
—
5
—
mV
Absolute (total unadjusted) error4, 5, 6, 7
FQCLK = 2.0MHz3, 2 clock input sample time
AE
-2
2
Counts
-7.8
3.5
mV
mΑ
mA
102
8, 9, 10, 11
Absolute (total unadjusted) error
FQCLK = 2.0MHz3, 2 clock input sample time
AEALT
104
DC Disruptive Input Injection Current12, 13, 14, 15, 16
IINJ17
IINJ18
-319
-1
3
1
105
Current Coupling Ratio20
PQA
PQB
K
—
—
8x10 -5
8x10 -5
107a
4
10
101
107
3
—
Stop Mode Recovery Time
106
2
TSR
100
102a
1
7.0
Incremental error due to injection current
All channels have same 10KΩ < Rs 3.1 V by an external component. HRESET and SRESET are fully 5-V compatible.
9 6.35 V on 5-V only pins (all QADC, all TPU, all QSMCM and the following MIOS pins: MDA[11:15], MDA[27:31],
MPWM16, MPIO32B[7:9]/MPWM[20:21], MPIO32B11/C_CNRX0, MPIO32B12/C_CNTX0 ). Internal structures hold
the input voltage below this maximum voltage on all of these pins, except the QSMCM RXD1/QPI1 and
RXD2/QPI2/C_CNRX0 pins, if the maximum injection current specification is met (1 mA for all pins; exception: 3 mA
on QADC pins) and VDDH is within Operating Voltage specifications (see specification 43 in Table G-4). Exception:
The RXD1/QGPI1 and RXD2/GPI2 pins do not have clamp diodes to VDDH. Voltage must be limited to less than 6.5
volts on these 2 pins to prevent damage.
10 Maximum continuous current on I/O pins provided the overall power dissipation is below the power dissipation of the
package. Proper operation is not guaranteed at this condition.
11 Condition applies to one pin at a time.
12 Transitions within the limit do not affect device reliability or cause permanent damage. Exceeding limit may cause
permanent conversion error on stressed channels and on unstressed channels.
13 Maximum transient current per ISO7637.
14
Maximum operating temperature on any solder ball in outer four rows of solder balls on the package. These rows are
referred to as “Perimeter Balls” to distinguish them from the balls in the center of the package.
15
Solder profile per CDF-AEC-Q100, current revision.
16 Moisture sensitivity per JEDEC test method J-STD-020-A (April 1999).
2
Functional operating conditions are given in Section G.6, “DC Electrical Characteristics.” Absolute
maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress
beyond those listed may affect device reliability or cause permanent damage to the device.
MPC561/MPC563 Reference Manual, Rev. 1.2
G-2
Freescale Semiconductor
66-MHz Electrical Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).
NOTE
Negative current flows out of the pin and positive current flows into the pin.
G.2
Package
The MPC561/MPC563 is available in packaged form. The package is a 388-ball PBGA having a 1.0 mm
ball pitch, Freescale case outline 1164-01 (See Figure G-63 and Figure G-64).
G.3
G.3.1
EMI Characteristics
Reference Documents
The document referenced for the EMC testing of MPC561/MPC563 is SAE J1752/3 Issued 1995-03
G.3.2
Definitions and Acronyms
EMC – Electromagnetic Compatibility
EMI – Electromagnetic Interference
TEM cell – Transverse Electromagnetic Mode cell
G.3.3
1.
2.
3.
4.
5.
6.
G.4
EMI Testing Specifications
Scan range: 150 KHz – 1000 MHz
Operating Frequency: 66 MHz
Operating Voltages: 2.6 V, 5.0 V
Max spikes: TBD dBuV
I/O port waveforms: Per J1752/3
Temperature: 25 °C
Thermal Characteristics
Table G-2. Thermal Characteristics
Characteristic
BGA Package Thermal Resistance,
Junction to Ambient – Natural Convection
BGA Package Thermal Resistance,
Junction to Ambient – Four layer (2s2p) board, natural
convection
Symbol
Value
Unit
RθJA
47.31,2,3
°C/W
RθJMA
29.43,4,5
°C/W
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-3
66-MHz Electrical Characteristics
Table G-2. Thermal Characteristics (continued)
Characteristic
Symbol
Value
Unit
BGA Package Thermal Resistance,
Junction to Board
RθJB
21.2 3,6
°C/W
BGA Package Thermal Resistance,
Junction to Case (top)
RθJT
7.03,7
°C/W
BGA Package Thermal Resistance,
Junction to Package Top, Natural Convection
ΨJT
1.68
°C/W
1
2
3
4
5
6
7
8
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
the board thermal resistance.
Per SEMI G38-87 and JESD51-2 with the board horizontal.
These values are the mean + 3 standard deviations of characterized data.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
the board thermal resistance.
Per JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board (Four layer (2s2p) board, natural convection).
Indicates the thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per EIA/JESD51-2.
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
TJ = TA + (RθJA x PD)
where:
TA = ambient temperature (°C)
RθJA = package junction to ambient resistance (°C/W)
PD = power dissipation in package
The junction to ambient thermal resistance is an industry standard value which provides a quick and easy
estimation of thermal performance. Unfortunately, the answer is only an estimate; test cases have
demonstrated that errors of a factor of two are possible. As a result, more detailed thermal characterization
is supplied.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal
resistance and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction to ambient thermal resistance (°C/W)
RθJC = junction to case thermal resistance (°C/W)
RθJA = case to ambient thermal resistance (°C/W)
MPC561/MPC563 Reference Manual, Rev. 1.2
G-4
Freescale Semiconductor
66-MHz Electrical Characteristics
RθJC is device related and cannot be influenced. The user controls the thermal environment to change the
case to ambient thermal resistance, RθCA. For instance, the air flow can be changed around the device, add
a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation
on the printed circuit board surrounding the device. This description is most useful for ceramic packages
with heat sinks where about 90% of the heat flow is through the case to the heat sink to ambient. For most
packages, a better model is required.
The simplest thermal model of a package which has demonstrated reasonable accuracy (about 20 percent)
is a two resistor model consisting of a junction to board and a junction to case thermal resistance. The
junction to case covers the situation where a heat sink will be used or where a substantial amount of heat
is dissipated from the top of the package. The junction to board thermal resistance describes the thermal
performance when most of the heat is conducted to the printed circuit board. It has been observed that the
thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the
board. temperature.
If the board temperature is known, an estimate of the junction temperature in the environment can be made
using the following equation:
TJ = TB + (RθJB x PD)
where:
TB = board temperature (°C)
RθJB = package junction to board resistance (°C/W)
PD = power dissipation in package (Ω)
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction to board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two-resistor model can be used with the thermal simulation of the application (2), or a more accurate and
complex model of the package can be used in the thermal simulation. Consultation on the creation of the
complex model is available.
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT x PD)
where:
TT = thermocouple temperature on top of package (°C)
ΨJT = thermal characterization parameter
PD = power dissipation in package
The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC
using a 40 gauge type-T thermocouple epoxied to the top center of the package case. The thermocouple
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-5
66-MHz Electrical Characteristics
should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is
placed over the thermocouple junction and over about one mm of wire extending from the junction. The
thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling
effects of the thermocouple wire.
G.4.1
Thermal References
The website for Semiconductor Equipment and Materials International is www.semi.org and their global
headquarters address is: 3081 Zanker Road, San Jose CA, 95134; 1-408-943-6900.
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents on
the WEB at www.global.ihs.com or 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance
and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp.
212-220.
G.5
ESD Protection
Table G-3. ESD Protection
Characteristics
Symbol
Value
Units
2000
V
R1
1500
Ω
C
100
pF
200
V
R1
0
Ω
C
200
pF
Number of pulses per pin2
Positive pulses (MM)
Negative pulses (MM)
Positive pulses (HBM)
Negative pulses (HBM)
—
—
—
—
3
3
1
1
Interval of Pulses
—
1
ESD for Human Body Model (HBM)1
HBM Circuit Description
ESD for Machine Model (MM)
MM Circuit Description
—
S
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
MPC561/MPC563 Reference Manual, Rev. 1.2
G-6
Freescale Semiconductor
66-MHz Electrical Characteristics
G.6
DC Electrical Characteristics
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH)
Table G-4. DC Electrical Characteristics
Characteristic
1
1
2.6-V only Input High Voltage
except DATA[0:31] and EXTCLK
1a
2.6-V Input High Voltage
EXTCLK
2
N.A.
2
3
5-V Input only High Voltage
4
5-V Input High Voltage (QADC PQA, PQB)
5
MUXed 2.6-V/ 5-V pins
(GPIO muxed with Addr and Data)
2.6-V Input High Voltage Addr., Data
5-V Input High Voltage (GPIO)
Symbol
Min
Max
Unit
VIH2.6
2.0
VDDH + 0.3
V
VIHC
1.6
VDDH + 0.3
V
—
—
—
—
VIH5
0.7 * VDDH
VDDH + 0.3
V
VIHA5
0.7 * VDDH
(VDDA |
VDDH) + 0.33
V
VIH2.6M
VIH5M
2.0
0.7 * VDDH
VDDH + 0.3
VDDH + 0.3
V
V
6
2.6-V Input Low Voltage
Except EXTCLK
VIL2.6
VSS – 0.3
0.8
V
7
2.6-V Input Low Voltage
EXTCLK
VIL2.6C
VSS – 0.3
0.4
V
8
5-V Input Low Voltage
9
5-V Input Low Voltage (QADC PQA, PQB)
10
MUXed 2.6-V/ 5-V pins (GPIO muxed with Addr, Data)
2.6-V Input Low Voltage (Addr., Data)
5-V Input Low Voltage (GPIO)
VIL5
VSS – 0.3
0.48 * VDDH
V
VILA5
VSSA – 0.3
0.48 * VDDH
V
VIL2.6M
VIL5M
VSS – 0.3
VSS – 0.3
0.8
0.48 * VDDH
V
11
QADC Analog Input Voltage4
Note: Assumes VDDA ≥ VDDH
VINDC
VSSH – 0.3
VDDH + 0.3
V
12
2.6-V Weak Pull-up/down Current
pull-up @ 0 to VIL2.6, pull-down @ VIH2.6 to VDD
IACT2.6V
20
130
µA
13
5-V Weak Pull-up/down Current4
pull-up @ 0 to VIL5, pull-down @ VIH5 to VDDH
IACT5V
20
130
µA
14
2.6-V Input Leakage Current4
pull-up/down inactive – measured @rails
IINACT2.6V
—
2.5
µA
15
5V Input Leakage Current4,5
pull-up/down inactive – measured @rails
IINACT5V
—
2.5
µA
16
QADC64 Input Current, Channel Off 6
PQA,
PQB
IOFF
-200
-200
200
200
nA
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-7
66-MHz Electrical Characteristics
Table G-4. DC Electrical Characteristics (continued)
Characteristic
17
2.6-V Output High Voltage VDD = VDDL
2.6-V Output High Voltage (IOH = -1mA)
2.6-V Output High Voltage (IOH = -2mA)
Symbol
Min
VOH2.6
VOH2.6A
2.3
2.1
Max
Unit
—
V
18
5-V Output High Voltage VDD = VDDH (IOH= -2mA)
All 5-V only outputs except TPU.
VOH5
VDDH – 0.7
—
V
19
5-V Output High Voltage VDD = VDDH (IOH= -5mA)
For TPU pins Only
VOHTP5
VDDH – 0.65
—
V
20
MUXed 2.6-V/ 5-V pins (GPIO MUXed with Addr, Data)
2.6-V Output High Voltage (IOH = -1mA)
2.6-V Output High Voltage (IOH = -2mA)
5-V Output High Voltage (IOH = -2mA)
—
V
VOH2.6M
VOH2.6MA
VOH5M
2.3
2.1
VDDH – 0.7
VOL2.6
—
0.5
V
VOL5
—
0.45
V
VOLTP5
—
21
2.6-V Output Low voltage VDD = VDDL (IOL = 3.2mA)
22
5-V Output Low voltage VDD = VDDH (IOL = 2mA)
All 5-V only outputs except TPU
23
5-V Output Low voltage VDD = VDDH -TPU pins Only
IOL = 2mA
IOL = 10mA
24
MUXed 2.6-V/ 5-V pins (GPIO MUXed with Addr, Data)
2.6-V Output Low Voltage (IOL = 3.2mA)
5-V Output Low Voltage (IOL = 2mA)
V
VOL2.6M
VOL5M
0.5
0.45
25
Output Low Current (@ VOL2.6= 0.4 V)
IOL2.6
2.0
27
CLKOUT Load Capacitance – SCCR COM & CQDS
COM[0:1]= 0b01, CQDS = 0b1
COM[0:1]= 0b01 CQDS = 0b0
COM[0:1]= 0b00 CQDS = 0bx
CCLK
—
29
Capacitance for Input, Output, and Bidirectional Pins:
Vin = 0 V, f = 1 MHz (except QADC)
CIN
—
30
Load Capacitance for bus pins only 7
COM[0:1] of SCCR = 0b11
COM[0:1] of SCCR = 0b10
CL
—
31
Total Input Capacitance
PQA Not Sampling
PQB Not Sampling
V
0.45
1.0
—
mA
25
50
90
pF
pF
pF
7
pF
pF
25
50
pF
CIN
—
—
15
15
32
Hysteresis (Only IRQ, TPU, MIOS, GPIO, QADC (Digital
inputs) and HRESET, SRESET, PORESET) 8
VH
0.5
—
V
33
N.A. (see Appendix F, “Electrical Characteristics”)
—
—
—
—
34
N.A. (see Appendix F, “Electrical Characteristics”)
—
—
—
—
35
N.A. (see Appendix F, “Electrical Characteristics”)
—
—
—
—
IDDL
—
250
IDDKAP
—
5
35a Operating Current (2.6-V supplies)@ 66 MHz10
VDD/QVDDL/NVDDL
KAPWR (Crystal Frequency: 20 MHz)
KAPWR (Crystal Frequency: 4 MHz)
IDDKAP
—
2
IDDSRAM
50 x 10-3
1.7511
IDDSYN
—
2
IDDF
—
35
VDDFSTOP
IDDFSTOP
—
10
VDDFDISABLED
IDDFDISB
—
100
IRAMSTBY
VDDSYN (Crystal Frequency: 20 MHz)
VDDF (Read, program, or erase)9
mA
µA
MPC561/MPC563 Reference Manual, Rev. 1.2
G-8
Freescale Semiconductor
66-MHz Electrical Characteristics
Table G-4. DC Electrical Characteristics (continued)
Characteristic
36
Symbol
Min
Max
Unit
—
—
—
—
VDDH
IDDH5
—
20
mA
VDDA11
IDDA
—
5
mA
VFLASHF5 (Program or Erase)
IDDF5
—
109
mA
VFLASHF5READ
IDDF5R
—
5
mA
VFLASHF5 (Stopped)
SIDDF5
—
1
mA
VFLASHF5 (Disabled)
SIDDF5D
—
100
µA
IDDA
—
10
µA
130
18
9.5
mA
mA
mA
2.5
2.7
V
4.75
5.25
V
N.A. (see Appendix F, “Electrical Characteristics”)
36a Operating Current (5-V supplies)@ 66 MHz10, 11
1
37
QADC64 Low Power Stop Mode (VDDA)
38
Low Power Current (QVDDL+ NVDDI+ VDD) @ 66 MHz
DOZE, Active PLL and Active Clocks
SLEEP, Active PLL with Clocks off
DEEP SLEEP, PLL and Clocks off
—
IDDDZ
IDDSLP
IDDDPSLP
39
NVDDL, QVDDL,VDD, VDDF 9Operating Voltage
40
VFLASH Flash Operating/Programming Voltage9
VFLASH
41
Oscillator, Keep-Alive Registers Operating Voltage10,11
KAPWR
42
N.A.
43
VDDH Operating Voltage
44
QADC Operating Voltage
45
Clock Synthesizer Operating Voltage Difference11
46
N.A.
47
VSS Differential Voltage
48
49
NVDDL, QVDDL,
VDD, VDDF
—
VDDH
VDDA
VDDSYN
VDD - 0.2 V VDD + 0.2 V12
—
—
V
—
4.75
5.25
V
4.75
5.25
V
VDD – 0.2 V VDD + 0.2 V12
V
—
—
—
—
VSS – VSSA
-100
100
mV
QADC64 Reference Voltage Low13
VRL
VSSA
VSSA + 0.1
V
QADC64 Reference Voltage High13
VRH
3.0
VDDA
V
50
QADC64 VREF Differential Voltage
VRH – VRL
3.0
5.25
V
51
QADC64 Reference Supply Current, DC
QADC64 Reference Supply Current, Transient
—
—
500
4.0
µA
mA
52
QADC64 ALT Reference Voltage14
IREF
IREFT
VARH
1.0
.75 * VDDA
V
53
Standby Supply Current
KAPWR only (4 MHz Crystal)
KAPWR only (20 MHz Crystal)
Measured @ 2.7 V
2.0
5
mΑ
mΑ
—
ISBKAPWR4
ISBKAPWR20
53a IRAMSTBY Regulator Current Data Retention 10
Specified VDD applied (VDD, VDDH = VSS)
ISTBY
50 x 10-3
1.75
mA
53b IRAMSTBY Regulator Voltage for Data Retention10,15
(power-down mode) Specified VDD applied
(VDD, VDDH = VSS)14
VSTBY
1.35
1.95
V
mA
54
DC Injection Current per Pin GPIO, TPU, MIOS, QSMCM,
EPEE and 5 V pins 4, 16, 17
IIC5
-1.0
1.0
55
DC Injection Current per Pin 2.6 V 4, 17, 18, 19
IIC26
-1.0
1.0
mA
56
QADC64 Disruptive Input Current 17, 20
INA
-3
3
mA
57
Power Dissipation – 66 MHz
PD
1.32
W
This characteristic is for 2.6-V output and 5-V input friendly pins.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-9
66-MHz Electrical Characteristics
2
This characteristic is for 5-V output and 5-V input pins.
0.3V > VDDA or VDDH, whichever is greater.
4
Within this range, no significant injection will be seen. See QADC64 Disruptive Input Current (I NA).
5
During reset all 2.6V and 2.6V/5V pads will leak up to 10µA to QVDDL if the pad has a voltage > QVDDL.
6 Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each
8 to 12 °C, in the ambient temperature range of 50 to 125 °C.
7 All bus pins support two drive strengths capabilities, 25 pF and 50 pF. Current drive is less at the 25-pF
capacitive load. Both modes achieve 66-MHz timing.
8
Only IRQ, TPU, MIOS, GPIO, QADC (when digital inputs) and RESET pins have hysteresis, thus there is no hysteresis
specification on all other pins
9
Transient currents can reach 50mA.
10
KAPWR and IRAMSTBY can be powered-up prior to any other supply or at the same time as the other 2.6 V supplies.
IRAMSTBY must lead or coincide with VDD; however it can lag KAPWR.
11
This parameter is periodically sampled rather than 100% tested
12
Up to 0.5 V during power up/down.
13 To obtain full-range results, V
SSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA
14 When using the QADC in legacy mode it is recommended to connect this pin to 2.6V or 3.3V, however it can be
connected to 0V or 5V without damage to the device.
15 A resistor must be placed in series with the IRAMSTBY power supply. Refer to Appendix C, “Clock and Board
Guidelines.”
16 All injection current is transferred to the V
DDH. An external load is required to dissipate this current to maintain the
power supply within the specified voltage range.
17 Absolute maximum voltage ratings for each pin (see Table G-1) must also be met during this condition.
18 Total injection current for all I/O pins on the chip must not exceed 20 mA (sustained current). Exceeding this limit can
cause disruption of normal operation.
19 Current refers to two QADC64 modules operating simultaneously.
20 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs
greater than VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the
presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.
3
G.7
Oscillator and PLL Electrical Characteristics
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH)
Table G-5. Oscillator and PLL
1
Characteristic
Symbol
Oscillator Startup time (for typical crystal capacitive load)
4-MHz crystal
20-MHz crystal
Min
Typica
l
Max
Unit
OSCstart4
OSCstart20
10
10
ms
ms
TLOCK
10001
Input
Clocks
2
PLL Lock Time
3
PLL Operating Range2
FVCOOUT
30
132
MHz
4
Crystal Operating Range, MODCK=0b010,0b110
MODCK[1:3] = 0b001, 0b011, 0b100, 0b101, 0b111
FCRYSTAL
3
15
5
25
MHz
MHz
5
PLL Jitter
PLL Jitter (averaged over 10 µs)
FJIT
FJIT10
-1%
-0.3%
+1%
+0.3%
—
6
Limp Mode Clock Out Frequency
—
33
173
MHz
7
Oscillator Bias Current (XTAL)
4 MHz
20 MHz
| 0.8 |
| 4.0 |
mA
mA
11
IBIAS
—
| 1.5 |
MPC561/MPC563 Reference Manual, Rev. 1.2
G-10
Freescale Semiconductor
66-MHz Electrical Characteristics
Table G-5. Oscillator and PLL (continued)
Characteristic
Symbol
Min
8
Oscillator Drive (XTAL)
IOSC
7
9
Oscillator Bias Resistor
ROSC
0.5
Typica
l
Max
1
Unit
—
mA
3
MΩ
1
Assumes stable power and oscillator.
FVCOOUT is 2x the system frequency.
3
Estimated value, real values to be characterized and updated.
2
G.8
Flash Electrical Characteristics
The characteristics found in this section apply only to the MPC563.
NOTE
Flash programming should be restricted to 56 MHz.
Flash read operations are unaffected by this condition.
Note: (VDDF = 2.6 V ± 0.1 V, VFLASH = 5.0 V ± 0.25 V, TA = TL to TH, TB = TL to TH)
Table G-6. Array Program and Erase Characteristics
Value
Symbol
Meaning
Minimum
TERASE
TERASEM
TPROG
Maximum
3
12
s
13
60
s
15
20
µs
Block Erase Time2
Module Erase
Time2
Word Programming
Units
Typical1
Time3,4
1
Typical program and erase times assume nominal supply values and 25 °C.
Erase time specification does not include pre-programming operation
3
Word size is 32 bits.
4 The maximum hardware programming time of the entire Flash (not including the shadow row) is 20 µs x (512 Kbytes
/ 4 bytes per word), or 131,072 words, (no software overhead).
2
Note: (VDDF = 2.6 V ± 0.1 V, VFLASH = 5.0 V ± 0.25 V, TA = TL to TH, TB = TL to TH)
Table G-7. CENSOR Cell Program and Erase Characteristics
Value
Symbol
Meaning
Minimum
1
2
Units
Typical1
Maximum
TCLEAR
CENSOR Bit Clear Time2
13
60
s
TSET
CENSOR Bit Set Time
115
250
µs
Typical set and clear times assume nominal supply values and 25 °C.
Clear time specification does not include pre-set operation.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-11
66-MHz Electrical Characteristics
Table G-8. Flash Module Life
Symbol
Array P/E
Cycles1
CENSOR Set/Clear
Cycles2
Meaning
Value
Maximum number of Program/Erase cycles per block to guarantee
data retention.
Minimum number of Program/Erase cycles per bit before failure.
Array and CENSOR Data Minimum data retention at an average of 85 °C junction temperature.
Retention
Minimum data retention at an average of 125 °C junction temperature.
1,000
100
Min 15 years3
Min 10 years3
1
A Program/Erase cycle is defined as switching the bits from 1 to 0 to 1.
A CENSOR Set/Clear cycle is defined as switching the bits from 1 to 0 to 1.
3
Maximum total time @ 150 °C junction temperature ≤ 1 year.
2
G.9
Power-Up/Down Sequencing
The supply symbols used in this section are described in Table G-9.
.
Table G-9. Power Supply Pin Groups
Symbol
VDDH
(High Voltage Supply Group)
Types of Power Pins
Supply to the 5-V pads for output driver (VDDH)
Supply to the analog (QADC64E) circuitry (VDDA)
High voltage supply to the Flash module (VFLASH)1
VDDL
(Low Voltage Supply Pins)
Supply to low voltage pad drivers (QVDDL, NVDDL)
Supply to all low voltage internal logic (VDD)
Supply to low voltage Flash circuitry (VDDF)1
Supply to system PLL
VDDKA
(Low Voltage Keep-Alive
Supply Pins2
1
2
Supply to IRAMSTBY
Supply to oscillator and other circuitry for keep-alive functions (KAPWR).
These power supplies are only available on the MPC563 and MPC564.
Any supply in the VDDKA group can be powered with the VDDL if the function which it supplies is not required during
“Keep-alive.”
MPC561/MPC563 Reference Manual, Rev. 1.2
G-12
Freescale Semiconductor
66-MHz Electrical Characteristics
There are two power-up/down options. Choosing which one is required for an application will depend
upon circuitry connected to 2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Power-up/down
option A is required if 2.6-V compliant pins and dual 2.6-V/5-V compliant pins are connected to the 5-V
supply with a pull-up resistor or driven by 5-V logic during power-up/down. In applications for which this
scenario is not true the power-up/down option B may be implemented. Option B is less stringent and easier
to ensure over a variety of applications.
Refer to Table 2-1 for a list of 2.6 V and dual 2.6V/5 V compliant pins.
The power consumption during power-up/down sequencing will stay below the operating power
consumption specifications when following these guidelines.
NOTE:
The VDDH ramp voltage should be kept below 50V/ms and the VDDL ramp
rate less that 25V/ms.
G.9.1
Power-Up/Down Option A
The Option A power-up sequence (excluding VDDKA) is
1. VDDH ≤ VDDL + 3.1 V (VDDH cannot lead VDDL by more than 3.1 V)
2. VDDH ≥ VDDL - 0.5 V (VDDH cannot lag VDDL by more than 0.5 V)
The first step in the sequence is required is due to gate-to-drain stress limits for transistors in the pads of
2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Damage can occur if gate-to-drain voltage
potential is greater than 3.1 V. This is only a concern at power-up/down. The second step in the sequence
is required is due to ESD diodes in the pad logic for dual 2.6-V/5-V compliant pins and 2.6-V pins. The
diodes are forward biased when VDDL is greater than VDDH and will start to conduct current.
Figure G-1 illustrates the power-up sequence if no keep-alive supply is required. Figure G-2 illustrates the
power-up sequence if a keep-alive supply is required. The keep-alive supply should be powered-up at the
same instant or before both the high voltage and low voltage supplies are powered-up.
VDDH
3.1-V lead
VDDL
0.5-V lag
VDDH cannot lead VDDL by more than 3.1 V
VDDH cannot lag VDDL by more than 0.5 V
Figure G-1. Option A Power-Up Sequence Without Keep-Alive Supply
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-13
66-MHz Electrical Characteristics
VDDH
3.1-V lead
VDDL
VDDKA
0.5-V lag
VDDH cannot lead VDDL by more than 3.1 V
VDDH cannot lag VDDL by more than 0.5 V
Figure G-2. Option A Power-Up Sequence With Keep-Alive Supply
The option A power-down sequence (excluding VDDKA) is
1. VDDH ≤ VDDL + 3.1 V (VDDH cannot lag VDDL by more than 3.1 V)
2. VDDH ≥ VDDL - 0.5 V (VDDH cannot lead VDDL by more than 0.5 V)
Figure G-3 illustrates the power-down sequence if no keep-alive supply is required.
VDDH
VDDL
3.1-V Max
0.5-V Max
Ramp down rates may differ
with load, so care should be taken
maintain VDDH with respect to VDDL.
VDDH cannot lag VDDL by more than 3.1 V.
VDDH ≥ VDDL - 0.5 V (VDDH cannot lead VDDL by more than 0.5 V.)
Figure G-3. Option A Power-Down Sequence Without Keep-Alive Supply
MPC561/MPC563 Reference Manual, Rev. 1.2
G-14
Freescale Semiconductor
66-MHz Electrical Characteristics
Figure G-4 illustrates the power-down sequence if a keep-alive supply is required.
VDDH
VDDL
VDDKA
0.5-V Max
3.1-V Max
Ramp down rates may
differ with load.
VDDH cannot lag VDDL by more than 3.1 V.
VDDH ≥ VDDL - 0.5 V (VDDH cannot lead VDDL by more than 0.5 V.)
Figure G-4. Option A Power-Down Sequence With Keep-Alive Supply
G.9.2
Power-Up/Down Option B
A less stringent power-up sequence may be implemented if 2.6-V compliant pins and dual 2.6-V/5-V
compliant pins are NOT connected to the 5-V supply with a pull-up resistor or driven by 5-V logic during
power-up/down.
The option B power-up sequence (excluding VDDKA) is:
1. VDDH > VDDL - 0.5 V (VDDH cannot lag VDDL by more than 0.5 V)
Thus the VDDH supply group can be fully powered-up prior to power-up of the VDDL supply group, with
no adverse affects to the device.
The requirement that VDDH cannot lag VDDL by more than 0.5 V is due to ESD diodes in the pad logic for
dual 2.6-V/5-V compliant pins and 2.6-V pins. The diodes are forward biased when VDDL is greater than
VDDH and will start to conduct current.
Figure G-5 illustrates the power-up sequence if no keep-alive supply is required. Figure G-6 illustrates the
power-up sequence if a keep-alive supply is required. The keep-alive supply should be powered-up at the
same time or before both the high voltage and low voltage supplies are powered-up.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-15
66-MHz Electrical Characteristics
VDDH
VDDL
0.5-V lag
VDDH cannot lag VDDL by more than 0.5 V
Figure G-5. Option B Power-Up Sequence Without Keep-Alive Supply
VDDH
VDDL
VDDKA
0.5-V lag
VDDH cannot lag VDDL by more than 0.5 V
Figure G-6. Option B Power-Up Sequence With Keep-Alive Supply
The option B power-down sequence (excluding VDDKA) is:
1. The VDDL supply group can be fully powered-down prior to power-down of the VDDH supply
group, with no adverse affects to the device.
For power-down, the low voltage supply should come down before the high voltage supply, although with
varying loads, the high voltage may actually get ahead.
Figure G-7 illustrates the power-down sequence if no keep-alive supply is required. Figure G-8 illustrates
the power-down sequence if a keep-alive supply is required.
MPC561/MPC563 Reference Manual, Rev. 1.2
G-16
Freescale Semiconductor
66-MHz Electrical Characteristics
VDDH
VDDH ≤ 5.25V
VDDL
0.5-V lag
VDDH cannot lead VDDL by more than 0.5V
Ramp down rates may
differ with load.
Figure G-7. Option B Power-Down Sequence Without Keep-Alive Supply
VDDH
VDDL
VDDKAP
0.5-V lag
Ramp down rates may
differ with load.
VDDH cannot lead VDDL by more than 0.5V
Figure G-8. Option B Power-Down Sequence with Keep-Alive Supply
G.10 Issues Regarding Power Sequence
G.10.1
Application of PORESET or HRESET
When VDDH is rising and VDDL is at 0.0 V, as VDDH reaches 1.6 V, all 5 V drivers are tristated. Before
VDDH reaches 1.6V, all 5 V outputs are unknown. If VDDL is rising and VDDH is at least 3.1V greater than
VDDL, then the 5 V drivers can come out of tristate when VDDL reaches 1.1V, and the 2.6 V drivers can
start driving when VDDL reaches 0.5 V. For these reasons, the PORESET or HRESET signal must be
asserted during power-up before VDDL is above 0.5 V.
If the PORESET or HRESET signal is not asserted before this condition, there is a possibility of disturbing
the programmed state of the flash. In addition, the state of the pads are indeterminant until PORESET or
HRESET propagates through the device to initialize all circuitry.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-17
66-MHz Electrical Characteristics
G.10.2
Keep-Alive RAM
PORESET or HRESET must be asserted during power-down prior to any supply dropping out of specified
operating conditions.
An additional constraint is placed on PORESET assertion since it is an asynchronous input. To assure that
the assertion of PORESET does not potentially cause stores to keep-alive RAM to be corrupted (store
single or store multiple) or non-coherent (store multiple), either of the following solutions is
recommended:
• Assert HRESET at least 0.5 µs prior to when PORESET is asserted.
• Assert IRQ0 (non-maskable interrupt) at least 0.5 µs prior to when PORESET is asserted. The
service routine for IRQ0 should not perform any writes to keep-alive RAM.
The amount of delay that should be added to PORESET assertion is dependent upon the frequency of
operation and the maximum number of store multiples executed that are required to be coherent. If store
multiples of more than 28 registers are needed and if the frequency of operation is lower that 66 MHz, the
delay added to PORESET assertion will need to be greater than 0.5 µs. In addition, if KAPWR features
are being used, PORESET should not be driven low while the VDDH and VDDL supplies are off.
G.11 AC Timing
Figure G-9 displays generic examples of MPC561/MPC563 timing. Specific timing diagrams are shown
in Figure G-10 through Figure G-35.
MPC561/MPC563 Reference Manual, Rev. 1.2
G-18
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
VDD/2
VDD/2
VDD/2
A
B
5-V OUTPUTS
VOH
VOL
VOH
VOL
A
B
5-V OUTPUTS
VOH
VOH
VOL
VOL
A
B
VDD/2
ADDR/DATA/CTRL
A
B
ADDR/DATA/CTRL OUTPUTS
VDD/2
C
VIH
VIL
5-V INPUTS
D
VIH
VIL
C
VIH
VIL
5-V INPUTS
C
ADDR/DATA/CTRL
D
VIH
VIL
D
VDD/2
VDD/2
C
ADDR/DATA/CTRL INPUTS
VDD/2
A. Maximum Output Delay Specification
B. Minimum Output Hold Time
D
VDDVDD/2
C. Minimum input Setup Time Specification
D. Minimum input Hold Time Specification
Figure G-9. Generic Timing Examples
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-19
66-MHz Electrical Characteristics
Table G-10. Bus Operation Timing
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
66 MHz
Characteristic
Min
Max
—
1
CLKOUT Period (TC)
15.15
1a
ENGCLK Frequency
5 V – EECLK = 01
2. 6 V – EECLK = 00
—
10
33
Uni
t
ns
MH
z
2
Clock pulse width low
7.575 –2% 7.575 + 2%
ns
3
Clock pulse width high
7.575 – 2% 7.575 + 2%
ns
4
CLKOUT rise time
ABUS/DBUS rise time
—
3.5
3.0
ns
5
CLKOUT fall time
ABUS/DBUS fall time
—
3.5
3.0
ns
6
N.A.
—
—
—
7
CLKOUT to Signal Invalid
(Hold Time)
ADDR[8:31]
RD/WR
BURST
D[0:31]
1.8
—
ns
2.0
—
ns
2.15
—
ns
Slave mode CLKOUT to
Signal Invalid
D[0:31]
1.8
—
ns
CLKOUT to Signal Valid
ADDR[8:31]
RD/WR
BURST
D[0:31]3
5.95
9.8
ns
7a
7b
7c
8
CLKOUT to Signal Invalid:
(Hold Time)
TSIZ[0:1]
RSV
AT[0:3]
BDIP
PTR
RETRY
CLKOUT to Signal Invalid
(Hold Time)1
BR
BG
FRZ
VFLS[0:1]
VF[0:2]
IWP(0:2]
LWP[0:1]
STS2
MPC561/MPC563 Reference Manual, Rev. 1.2
G-20
Freescale Semiconductor
66-MHz Electrical Characteristics
Table G-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
66 MHz
Characteristic
8a
8b
Uni
t
Min
Max
CLKOUT to Signal Valid
TSIZ[0:1]
RSV
AT[0:3]
BDIP
PTR
RETRY
4.65
8.3
ns
CLKOUT to Signal Valid1
BR
BG
VFLS[0:1]
VF[0:2]
IWP[0:2]
FRZ
LWP[0:1]
STS valid.
4.55
8.75
ns
8c
Slave Mode CLKOUT to Signal Valid
D[0:31]
—
8.3
ns
8d
CLKOUT to Data Pre-discharge time4
—
—
ns
8e
CLKOUT to Data Pre-discharge
start4
—
—
ns
9
CLKOUT to High Z
ADDR[8:31]
RD/WR
BURST
D[0:31]
TSIZ[0:1]
RSV
AT[0:3]
PTR
RETRY
5.95
9.8
ns
3.33
7.9
ns
10
CLKOUT to TS, BB assertion
10a
CLKOUT to TA, BI assertion
(when driven by the Memory Controller)
—
7.85
ns
10b
CLKOUT to RETRY assertion
(when driven by the Memory Controller)
—
6.4
ns
11
CLKOUT to TS, BB negation
2.78
5.95
ns
11a
CLKOUT to TA, BI negation
(when driven by the Memory Controller)
0.28
2.8
ns
11b
CLKOUT to RETRY negation
(when driven by the Memory Controller)
0
11
ns
12
CLKOUT to TS, BB High Z
3.85
13.6
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-21
66-MHz Electrical Characteristics
Table G-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
66 MHz
Characteristic
Min
Max
Uni
t
12a
CLKOUT to TA, BI High Z
(when driven by the Memory Controller)
—
12.75
ns
13
CLKOUT to TEA assertion
—
5.85
ns
14
CLKOUT to TEA High Z
—
12.75
ns
15
Input Valid to CLKOUT
(Setup Time)
TA
TEA
BI2
6.35
—
ns
Input Valid to CLKOUT
(Setup Time)
KR
CR
RETRY
6.6
—
ns
Input Valid to CLKOUT
(Setup Time)
BB
BG
BR1
5.46
—
ns
1
—
ns
1
—
ns
4
—
ns
3
—
ns
15a
15b
16
16a
17
CLKOUT to Signal Invalid
(Hold Time)
TA
TEA
BI
BB
BG
BR1, 2
CLKOUT to Signal Invalid
(Hold Time)
RETRY
KR
CR
Signal Valid to CLKOUT Rising Edge (Setup Time)
D[0:31]3
17b
Signal Valid to CLKOUT Rising Edge (Short Setup Time, SST = 1)
D[0:31]3
18
CLKOUT Rising Edge to Signal Invalid (Hold Time)
D[0:31]3
0.5
—
ns
19
CLKOUT Rising Edge to CS asserted
-GPCM- ACS = 00
6.1
9.75
ns
19a
CLKOUT Falling Edge to CS asserted
-GPCM- ACS = 10, TRLX = 0 or 1
—
4.25
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
G-22
Freescale Semiconductor
66-MHz Electrical Characteristics
Table G-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
66 MHz
Characteristic
19b
CLKOUT Falling Edge to CS asserted
-GPCM- ACS = 11, TRLX = 0 or 1
19c
CLKOUT Falling Edge to CS asserted
-GPCM- ACS = 11, TRLX = 0, EBDF = 1
20
CLKOUT Rising Edge to CS negated
-GPCM- Read Access or Write access when CSNT = 0 or write access
when CSNT = 1 and ACS = 00
Uni
t
Min
Max
4
9
ns
6.69
12.69
ns
1.55
4.85
ns
21
ADDR[8:31] to CS asserted
-GPCM- ACS = 10, TRLX = 0
1.2
—
ns
21a
ADDR[8:31] to CS asserted
-GPCM- ACS = 11, TRLX = 0
5.1
—
ns
22
CLKOUT Rising Edge to OE, WE[0:3]/BE[0:3] asserted
1
5.45
ns
23
CLKOUT Rising Edge to OE negated
1.45
5.06
ns
24
ADDR[8:31] to CS asserted
-GPCM- ACS = 10, TRLX = 1
13.95
—
ns
24a
ADDR[8:31] to CS asserted
-GPCM- ACS = 11, TRLX = 1
17
—
ns
25
CLKOUT Rising Edge to WE[0:3]/BE[0:3] negated
-GPCM-write access CSNT = ‘0‘
—
4.75
ns
25a
CLKOUT Falling Edge to WE[0:3]/BE[0:3] negated
-GPCM-write access
TRLX = ‘0’ or ‘1’, CSNT = ‘1, EBDF = 0’.
4.5
9.5
ns
CLKOUT Falling Edge to CS negated
-GPCM-write access
TRLX = ‘0’ or ‘1’, CSNT = ‘1’, ACS = ‘10’ or ACS=’11’, EBDF = 0
4.5
9.5
ns
CLKOUT Falling Edge to WE[0:3]/BE[0:3] negated
-GPCM-write access
TRLX = ‘0’, CSNT = ‘1, EBDF = 1’.
5.5
12.69
ns
CLKOUT Falling Edge to CS negated
-GPCM-write access
TRLX = ‘0’, CSNT = ‘1’, ACS = ‘10’ or ACS=’11’, EBDF = 1
6.25
17
ns
25b
25c
25d
26
WE[0:3]/BE[0:3] negated to D[0:31] High Z
-GPCM- write access, CSNT = ‘0’
1.95
—
ns
26a
WE[0:3]/BE[0:3] negated to D[0:31] High Z
-GPCM- write access, TRLX = ‘0’, CSNT = ‘1’, EBDF = 0
4.85
—
ns
26b
CS negated to D[0:31], High Z
-GPCM- write access, ACS = ‘00’, TRLX = ‘0’ & CSNT = ‘0’
1.95
—
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-23
66-MHz Electrical Characteristics
Table G-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
66 MHz
Characteristic
26c
CS negated to D[0:31], High Z
-GPCM- write access, TRLX = ‘0’, CSNT = ‘1’, ACS = ‘10’ or ACS=’11’,
EBDF = 0
26d
WE[0:3]/BE[0:3] negated to D[0:31] High Z
-GPCM- write access, TRLX = ‘1’, CSNT = ‘1’, EBDF = 0
26e
CS negated to D[0:31] High Z
-GPCM- write access, TRLX = ‘1’, CSNT = ‘1’, ACS = ‘10’ or ACS=’11’,
EBDF = 0
26f
WE[0:3]/BE[0:3] negated to D[0:31] HighZ
-GPCM- write access, TRLX = ‘0’, CSNT = ‘1’, EBDF = 1
26g
CS negated to D[0:31] High Z
-GPCM- write access, TRLX = ‘0’, CSNT = ‘1’, ACS = ‘10’ or ACS=‘11’,
EBDF = 1
26h
WE[0:3]/BE[0:3] negated to D[0:31] High Z
-GPCM- write access, TRLX = ‘1’, CSNT = ‘1’, EBDF = 1
26i
CS negated to D[0:31] High Z
-GPCM- write access, TRLX = ‘1’, CSNT = ‘1’, ACS = ‘10’ or ACS=’11’,
EBDF = 1
27
CS, WE[0:3]/BE[0:3] negated to ADDR[8:31] invalid -GPCM- write
access5
27a
WE[0:3]/BE[0:3] negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=‘0’, CSNT = ‘1’.
Uni
t
Min
Max
4.85
—
ns
17
—
ns
17
—
ns
3.2
—
ns
3.2
—
ns
14.65
—
ns
14.65
—
ns
1.2
—
ns
4.85
—
ns
17
—
ns
2.55
—
ns
CS negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’0’, CSNT = ‘1’, ACS = 10,ACS = =‘11’,
EBDF = 0
27b
WE[0:3]/BE[0:3] negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’1’, CSNT = '1’.
CS negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’1’, CSNT = '1’, ACS = 10,ACS = =’11’,
EBDF = 0
27c
WE[0:3]/BE[0:3] negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’0’, CSNT = '1’.
CS negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’0’, CSNT = '1’, ACS = 10,ACS = =’11’,
EBDF = 1
MPC561/MPC563 Reference Manual, Rev. 1.2
G-24
Freescale Semiconductor
66-MHz Electrical Characteristics
Table G-10. Bus Operation Timing (continued)
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH, 50 pF load unless noted otherwise)
66 MHz
Characteristic
27d
Uni
t
Min
Max
14.65
—
ns
WE[0:3]/BE[0:3] negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’1’, CSNT = '1’.
CS negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’1’, CSNT = '1’, ACS = 10,ACS = =’11’,
EBDF = 1
1
2
3
4
5
28
ADDR[8:31], TSIZ[0:1], RD/WR, BURST, valid to CLKOUT Rising
Edge. (Slave mode Setup Time)
3.5
—
ns
28a
Slave Mode D[0:31] valid to CLKOUT Rising Edge
3.7
—
ns
29
TS valid to CLKOUT Rising Edge (Setup Time)
2
—
ns
30
CLKOUT Rising Edge to TS Valid (Hold Time).
3.6
—
ns
The timing for BR output is relevant when the deviceMPC561/MPC563 is selected to work with external bus
arbiter. The timing for BG output is relevant when the MPC561/MPC563 is selected to work with internal bus
arbiter.
The setup times required for TA, TEA, and BI are relevant only when they are supplied by the external device
(and not the memory controller).
The maximum value of spec 8 for DATA[0:31] pins must be extended by 1.1 ns if the pins have been precharged
to greater than VDDL. This is the case if an external slave device on the bus is running at the max. value of
VDATAPC. This is currently specified at 3.1 V. The 1.1 ns addition to spec 8 reflects the expected timing
degradation for 3.1 V.
The device may be used without limitation in conjuction with 2.6 V external memories. Pre-discharge function
is not available for 66-MHz operation.
The timing 27 refers to CS when ACS = ‘00’ and to WE[0:3]/BE[0:3] when CSNT = ‘0’.
NOTE
The D[0:31] input timings 17 and 18 refer to the rising edge of the CLKOUT
in which the TA input signal is asserted.
CLKOUT
4
3
2
5
1
Figure G-10. CLKOUT Pin Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-25
66-MHz Electrical Characteristics
CLKOUT
8
9
7
OUTPUT
SIGNALS
8a
9
7a
OUTPUT
SIGNALS
8b
7b
OUTPUT
SIGNALS
Figure G-11. Synchronous Output Signals Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
G-26
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
12
10
11
TS, BB
12a
10a
11a
TA, BI
13
14
TEA
Figure G-12. Synchronous Active Pull-Up And Open Drain Outputs Signals Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-27
66-MHz Electrical Characteristics
CLKOUT
15
16
TA, BI
15a
16a
TEA, KR,
RETRY, CR
15b
16
BB, BG, BR
Figure G-13. Synchronous Input Signals Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
G-28
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
15a
16
TA
17
18
DATA[0:31]
Figure G-14. Input Data Timing In Normal Case
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-29
66-MHz Electrical Characteristics
CLKOUT
10
11
TS
8
ADDR[8:31]
19
20
CSx
22
23
OE
25
WE[0:3]/BE[0:3]
17
DATA[0:31]
18
Figure G-15. External Bus Read Timing (GPCM Controlled – ACS = ‘00’)
MPC561/MPC563 Reference Manual, Rev. 1.2
G-30
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
10
11
TS
8
ADDR[8:31]
19a
20
CSx
21
OE
23
22
17
DATA[0:31]
18
Figure G-16. External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-31
66-MHz Electrical Characteristics
CLKOUT
10
11
TS
8
ADDR[8:31]
19b
CSx
20
19c
21a
OE
23
22
17
DATA[0:31]
18
Figure G-17. External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’)
MPC561/MPC563 Reference Manual, Rev. 1.2
G-32
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
10
11
TS
8
ADDR[8:31]
19a
20
CSx
24
OE
23
24a
19b
19c
17
DATA[0:31]
18
Figure G-18. External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-33
66-MHz Electrical Characteristics
CLKOUT
10
TS
11
9
8
ADDR[8:31]
Figure G-19. Address Show Cycle Bus Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
G-34
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
10
11
TS
8
27
ADDR[8:31]
CSx
WE[0:3]/BE[0:3]
8
DATA[0:31]
9
Figure G-20. Address and Data Show Cycle Bus Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-35
66-MHz Electrical Characteristics
CLKOUT
10
11
TS
8
27
ADDR[8:31]
19
20
CSx
26b
22
25
WE[0:3]/BE[0:3]
23
OE
26
8
DATA[0:31]
9
Figure G-21. External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’)
MPC561/MPC563 Reference Manual, Rev. 1.2
G-36
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
10
11
TS
27c
8
27a
19
20
ADDR[8:31]
CSx
25b
25d
22
26c 26g
WE[0:3]/BE[0:3]
23
26a 26g
OE
25a
25c
8
D[0:31]
9
Figure G-22. External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-37
66-MHz Electrical Characteristics
CLKOUT
10
11
TS
27d 27b
8
ADDR[8:31]
19
20
CSx
25b
25d
22
26i 26e
WE[0:3]/BE[0:3]
23
26h 26d
OE
26b
25a
25c
8
DATA[0:31]
9
Figure G-23. External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’)
MPC561/MPC563 Reference Manual, Rev. 1.2
G-38
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
30
29
TS
28
ADDR[8:31],
TSIZ[0:1],
RD/WR,
BURST,
BDIP
12a
10a
11a
TA,
BI
13
14
TEA
8
DATA[0:31]
9
10b
11b
RETRY
Figure G-24. External Master Read From Internal Registers Timing
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-39
66-MHz Electrical Characteristics
CLKOUT
30
29
TS
28
ADDR[8:31],
TSIZ[0:1],
RD/WR,
BURST
12a
10a
11a
TA,
BI
13
14
TEA,
28a
DATA[0:31]
18
10b
11b
RETRY
Figure G-25. External Master Write To Internal Registers Timing
Table G-11. Interrupt Timing
Note: (TA = TL to TH)
66 MHz
Characteristic
Unit
Min
Max
33
IRQx Pulse width Low
TC
—
ns
34
IRQx Pulse width High; Between Level IRQ
TC
—
ns
35
IRQx Edge to Edge time
4 * TC
—
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
G-40
Freescale Semiconductor
66-MHz Electrical Characteristics
IRQx
35
34
33
Level IRQ
Edge IRQ
Figure G-26. Interrupt Detection Timing for External Edge Sensitive Lines
G.11.1
Debug Port Timing
Table G-12. Debug Port Timing
Note: (TA = TL to TH)
66 MHz
Characteristic
Unit
Min
Max
36
DSCK Cycle Time
30.30
—
ns
37
DSCK Clock Pulse Width
15.15
—
ns
38
DSCK Rise and Fall Times
0
7
ns
39
DSDI Input Data Setup Time
15
—
ns
40
DSDI Data Hold Time
5
—
ns
41
DSCK low to DSDO Data Valid
0
18
ns
42
DSCK low to DSDO Invalid
0
—
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-41
66-MHz Electrical Characteristics
DSCK
36
37
37
36
38
38
Figure G-27. Debug Port Clock Input Timing
DSCK
39
40
DSDI
41
42
DSDO
Figure G-28. Debug Port Timings
MPC561/MPC563 Reference Manual, Rev. 1.2
G-42
Freescale Semiconductor
66-MHz Electrical Characteristics
G.12 READI Electrical Characteristics
The AC electrical characteristics (56 MHz) are described in the following tables and figures
Table G-13. READI AC Electrical Characteristics
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH 50 pF load unless noted otherwise)
Number
Characteristic
Min
Max
Unit
17.9
—
ns
1
MCKO Cycle Time (Tco)
2
MCKO Duty Cycle
40
60
%
3
Output Rise and Fall Times
0
3
ns
4
MCKO low to MDO Data Valid
-1.79
3.58
ns
5
MCKI Cycle Time (Tci)
35.6
—
ns
6
MCKI Duty Cycle
40
60
%
7
Input Rise and Fall Times
0
3
ns
8
MDI, EVTI, MSEI Setup Time
7.12
—
ns
9
MDI Hold TIme
3.56
—
ns
10
RSTI Pulse Width
71.6
—
ns
11
MCKO low to MSEO Valid
-1.79
3.58
ns
12
EVTI Pulse Width
71.6
—
ns
13
EVTI to RSTI Setup
(at reset only)
(4.0) x TC
—
ns
14
EVTI to RSTI Hold
(at reset only)
(4.0) x TC
—
ns
MCKI
8
9
Input Data Valid
MDI, EVTI,MSEI
Figure G-29. Auxiliary Port Data Input Timing Diagram
MCKO
MDO, MSEO
4
11
Output Data Valid
Figure G-30. Auxiliary Port Data Output Timing Diagram
MDO and MSEO data is held valid until the next MCKO low transition.
When RSTI is asserted, EVTI is used to enable or disable the auxiliary port. Because MCKO probably is
not active at this point, the timing must be based on the system clock. Since the system clock is not realized
on the connector, its value must be known by the tool.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-43
66-MHz Electrical Characteristics
RSTI
14
13
EVTI
Figure G-31. Enable Auxiliary From RSTI
RSTI
13
14
EVTI
Figure G-32. Disable Auxiliary From RSTI
G.13 RESET Timing
Table G-14. RESET Timing
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH)
66 MHz
Characteristic
Unit
Min
Max
43
CLKOUT to HRESET high impedance
—
20
ns
44
CLKOUT to SRESET high impedance
—
20
ns
45
RSTCONF pulse width
257
—
ns
46
Configuration Data to HRESET rising edge Setup Time
231
—
ns
47
Configuration Data to RSTCONF rising edge set up time
231
—
ns
48
Configuration Data hold time after RSTCONF negation
0
—
ns
49
Configuration Data hold time after HRESET negation
0
—
ns
24
—
1
49a
RSTCONF hold time after HRESET negation
50
HRESET and RSTCONF asserted to Data out drive
25
—
ns
51
RSTCONF negated to Data out high impedance
25
—
ns
52
CLKOUT of last rising edge before chip tristates HRESET to Data out high impedance
25
—
ns
53
DSDI, DSCK set up
46
—
ns
54
DSDI, DSCK hold time
0
—
ns
55
SRESET negated to CLKOUT rising edge for DSDI and DSCK sample
121
—
ns
55a
HRESET, SRESET, PORESET pulse width 2
100
—
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
G-44
Freescale Semiconductor
66-MHz Electrical Characteristics
Weak pull-ups and pull-downs used for Reset timing will comply with the 130 µA mode select current outlined in
Table G.6 on page G-7 The system requires two clocks of hold time on
RSTCONF/TEXP after negation of HRESET. The simplest way to insure meeting this requirement in systems that
require the use of the TEXP function, is to connect RSTCONF/TEXP to SRESET.
2
HRESET, SRESET and PORESET have a glitch detector to ensure that spikes less than 20 ns are rejected. The internal
HRESET, SRESET and PORESET will assert only if these signals are
asserted for more than 100 ns
1
HRESET
45
49a
RSTCONF
49
46
48
DATA[0:31] (IN)
47
Figure G-33. Reset Timing – Configuration from Data Bus
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-45
66-MHz Electrical Characteristics
CLKOUT
43
55a
HRESET
RSTCONF
51
50
52
DATA[0:31] (OUT)
(Weak)
Figure G-34. Reset Timing – Data Bus Weak Drive During Configuration
MPC561/MPC563 Reference Manual, Rev. 1.2
G-46
Freescale Semiconductor
66-MHz Electrical Characteristics
CLKOUT
44
55
SRESET
53
53
54
54
DSCK, DSDI
Figure G-35. Reset Timing – Debug Port Configuration
G.14 IEEE 1149.1 Electrical Characteristics
Table G-15. JTAG Timing
Note: (TA = TL to TH)
10 MHz1
Characteristic
Min
Max
Unit
56
TCK Cycle Time1 (JTAG clock)
100
—
ns
57
TCK Clock Pulse Width Measured at VDD/2
50
—
ns
58
TCK Rise and Fall Times
0
10
ns
59
TMS, TDI Data Setup Time
5
ns
60
TMS, TDI Data Hold Time
25
ns
61
TCK Low to TDO Data Valid
62
TCK Low to TDO Data Invalid
63
TCK Low to TDO High Impedance
20
ns
66
TCK Falling Edge to Output Valid
50
ns
67
TCK Falling Edge to Output Valid out of High Impedance
50
ns
68
TCK Falling Edge to Output High Impedance
50
ns
69
Boundary Scan Input Valid to TCK Rising Edge
50
ns
70
TCK Rising Edge to Boundary Scan Input Invalid
50
ns
20
0
ns
ns
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-47
66-MHz Electrical Characteristics
1
JTAG timing (TCK) is only tested at 10 MHz. TCK is the operating clock of the MPC561/MPC563 in JTAG mode.
TCK
57
56
57
58
Figure G-36. JTAG Test Clock Input Timing
TCK
59
60
TMS, TDI
61
63
62
TDO
Figure G-37. JTAG Test Access Port Timing Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
G-48
Freescale Semiconductor
66-MHz Electrical Characteristics
TCK
66
68
OUTPUT
SIGNALS
67
OUTPUT
SIGNALS
70
69
OUTPUT
SIGNALS
Figure G-38. Boundary Scan (JTAG) Timing Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-49
66-MHz Electrical Characteristics
G.15 QADC64E Electrical Characteristics
Table G-16. QADC64E Conversion Characteristics
Note: (VDD = 2.6 V ± 0.1 V, VDDH = 5.0 V ± 0.25 V, TA = TL to TH)
Num
Parameter
97
QADC Clock (QCLK) Frequency1
98
Conversion Cycles2
Legacy mode: QADCMCR[FLIP] = 0
Enhanced mode: QADCMCR[FLIP] = 1
99
Symbol
Min
Max
Units
FQCLK
0.5
3.0
MHz
CC
CC
12
14
28
20
QCLK cycles
QCLK cycles
14
µs
µs
10
µs
µs
Conversion Time
FQCLK = 2.0 MHz1
Legacy mode: QADCMCR[FLIP] = 0
Min = CCW[IST] =0b00, CCW[BYP] = 0
Max = CCW[IST] =0b11, CCW[BYP] = 1
6.0
TCONV
Enhanced mode: QADCMCR[FLIP] = 1
Min = CCW[IST] =0b0
Max = CCW[IST] =0b1
5
6
7
µs
Resolution3
—
5
—
mV
Absolute (total unadjusted) error4, 5, 6, 7
FQCLK = 2.0MHz3, 2 clock input sample time
AE
-2
2
Counts
-7.8
3.5
mV
mΑ
mA
102
8, 9, 10, 11
Absolute (total unadjusted) error
FQCLK = 2.0MHz3, 2 clock input sample time
AEALT
104
DC Disruptive Input Injection Current12, 13, 14, 15, 16
IINJ17
IINJ18
-319
-1
3
1
105
Current Coupling Ratio20
PQA
PQB
K
—
—
8x10 -5
8x10 -5
107a
4
10
101
107
3
—
Stop Mode Recovery Time
106
2
TSR
100
102a
1
7.0
Incremental error due to injection current
All channels have same 10KΩ < Rs
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