NXP Semiconductors
User Guide
Document Number: MPC5748GLCEVBUG
Rev. 0, 05/2016
MPC5748G Low Cost EVB User Guide
© 2016 NXP B.V.
Contents
1.
INTRODUCTION.............................................................................................................................................................. 3
2.
LCEVB FEATURES.......................................................................................................................................................... 3
2.1.
Differences to the Customer EVB ..................................................................................................................................... 4
3.
CONFIGURATION OVERVIEW ..................................................................................................................................... 6
4.
INITIAL SETUP ................................................................................................................................................................ 7
4.1.
Power Supply Configuration.............................................................................................................................................. 7
4.1.1.
Power Input Connector ................................................................................................................................................. 7
4.1.2.
Power Switch ................................................................................................................................................................ 7
4.1.3.
Power Status LED ......................................................................................................................................................... 8
4.1.4.
MCU and Peripheral Voltage Configuration ................................................................................................................ 8
4.2.
Reset Control (SW3) .......................................................................................................................................................... 8
4.2.1.
Reset LEDs ................................................................................................................................................................... 9
4.3.
MCU Clock Configuration .............................................................................................................................................. 10
4.4.
Debug Connector (P1) ..................................................................................................................................................... 10
4.4.1.
Debug Connector Pinout ............................................................................................................................................. 10
5.
COMMUNICATIONS & MEMORY INTERFACES: .................................................................................................... 11
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
6.
CAN Interfaces (P2, P3) .................................................................................................................................................. 11
LIN Interfaces (P6, P7) .................................................................................................................................................... 12
USB RS232 Serial Interface (P11) .................................................................................................................................. 12
USB HOST Interface (P4) ............................................................................................................................................... 12
Ethernet Interface (P5) ..................................................................................................................................................... 13
FlexRay (P8, P9, P10)...................................................................................................................................................... 13
USER INTERFACE (I/O) ................................................................................................................................................ 14
6.1.
6.2.
6.3.
6.4.
6.5.
GPIO Matrix .................................................................................................................................................................... 14
User Switches (SW4, SW5) ............................................................................................................................................. 15
Hex Encoded Switch (SW1) ............................................................................................................................................ 15
User LED’s (DS1, DS2, DS3, DS4) ................................................................................................................................ 16
ADC Input Potentiometer (RVAR, RV1) ........................................................................................................................ 16
7.
MCU PORT PIN LCEVB FUNCTIONS ......................................................................................................................... 17
8.
APPENDIX ...................................................................................................................................................................... 18
MPC5748G Low Cost EVB User Guide, Rev. 0, 05/2016
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1. Introduction
This user guide details the setup and configuration of the NXP MPC5748G Low Cost Evaluation Board
(hereafter referred to as the LCEVB). The LCEVB is intended to provide a mechanism for easy
evaluation of the MPC5748G family of microcontrollers, and to facilitate basic hardware and software
development.
Note that the LCEVB has a limited feature set compared to the main MPC574xG customer EVB and is
intended for evaluation purposes. Customers moving to serious development activities are recommended
to purchase the fully functional customer EVB which also has device specific daughter cards.
The LCEVB is intended for bench / laboratory use and has been designed using normal temperature
specified components (+70° C).
This product contains components that may be damaged by electrostatic discharge. Observe precautions
for handling electrostatic sensitive devices when using the LCEVB.
The user guide is intended to be read alongside the respective MCU documentation available at
www.nxp.com and includes:
Reference Manuals
Product Data Sheets
Application notes
Device Errata
2. LCEVB Features
The LCEVB provides the following key features:
Single 5 V DC external power supply input with on-board 3.3 V regulator. Power is supplied via
a 2.1 mm barrel style power jack.
Simple jumperless configuration (enhanced configuration is possible via 0 Ohm Resistors and
optional jumpers if required).
Master power switch and regulator status LED.
USB Serial interface.
2 x High Speed CAN transceiver routed to 3-way headers.
2 x LIN interfaces routed to 3-way headers.
Main clock supplied from on board crystal.
User reset switch with reset status LED’s.
Ethernet PHY and RJ45 socket (configured for MII mode).
USB Type A Host interface.
2 x FlexRay interfaces with standard 2-pin connectors.
14-pin JTAG connector.
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4 user LED’s wired to MCU ports.
2 user pushbutton switches wired to MCU ports.
Hexadecimal encoded switch wired to 4 MCU ports.
Simple potentiometer connected to analogue input channel.
2.1. Differences to the Customer EVB
Note that the GPIO pins used for peripherals on the LCEVB are the same as those used on the customer
EVB. This ensures maximum code compatibility between the 2 boards, making it easy to migrate from
one board to the other
Table 1. Customer EVB vs LCEVB features
Customer EVB
LCEVB
Custom MCU Daughtercards for
Soldered 176QFP MPC5748G
multiple devices (socketed)
Power Supply
External 12 V
External 5 V (Caution)
On Board Regulators (and LED’s)
5 V, 3.3 V, 1.25 V (combination of
3.3 V Switching Regulator
Linear and /or Switching regulators)
Master Power Switch
Yes
Yes
Reset Control
Reset button with MCU and External
Reset button with MCU and External
Reset LED’s
Reset LED’s
USB FTDI Serial Interface
Yes
Yes
CAN Physical Interfaces
2 (routed to 0.1” headers)
2 (routed to 0.1” headers)
LIN Physical Interfaces
2 (routed to Molex headers)
2 (routed to 0.1” headers)
FlexRay Physical Interfaces
2 (routed to 0.1” headers)
2 (routed to 0.1” headers)
Ethernet Physical Interface
1 (MII and RMII Support)
1 (MII only mode)
USB Physical Interface
2 (USB Host and OTG)
1 (USB Host)
MLB Daughtercard Connector
Yes
No
SAI Audio / TWRPI Connectors
Yes
No
SDHC Connector
Full Size SDHC Socket
No
Fast External Osc (FXOSC)
Daughtercard Crystal * and
40 MHz Crystal
SMA input connector
Slow External Osc (SXOSC)
Daughtercard Crystal *
32.768 KHz Crystal
CLKOUT signals available
Yes (GPIO Matrix)
Yes (Standalone pads)
User LEDS
4
4
User Pushbutton Switches
4
2
Hex Encoded Switch
Yes
Yes
Test Potentiometer for ADC
Yes
Yes
GPIO Matrix
All Available Pins not otherwise used
Selection of Pins available from 5
for peripherals
GPIO Ports
Debug
14 Pin JTAG and 50 pin Nexus
14 Pin JTAG
Configuration
Highly configurable via jumper shunts
Fixed (limited configuration via 0 ohm
resistors)
Feature
MCU Support
* Daughtercard crystals are typically 40 MHz for FXOSC and 32.768 KHz for SXOSC but may vary
between daughtercards.
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LCEVB Features
The figure below shows the customer EVB (left) next to the LCEVB(right).
Figure 1. Customer and LCEVB side by side
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3. Configuration Overview
Out of the box, there is no configuration required for the LCEVB to function. Unlike the customer EVB,
the LCEVB is primarily designed for a single mode of operation with no requirement for user
configuration. If you wish to have a more flexible configuration the recommendation is that the fully
configurable customer EVB is purchased.
There are however some jumper footprints and zero ohm resistors populated in positions that would
normally have jumper headers fitted (for example on the MCU power supply lines and tracking to the
peripheral interfaces). If required these can be de-soldered to modify functionality. Any such
modification is done at the full risk of the user and no support or warranty repairs will be provided for a
board that has been modified. Modifications should only be attempted by appropriately trained
personnel using the correct equipment and Personal Protective Apparel
The diagram below gives an overview of the functional blocks of the LCEVB
Figure 2. EVB Functional Blocks
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Initial Setup
4. Initial Setup
This section details the power, reset, clocks, and debug configuration which is the minimum
configuration needed in order to power ON the LCEVB.
4.1. Power Supply Configuration
The Power supply
section is located in
the bottom left corner
of the LCEVB
The LCEVB requires an external power supply voltage of 5 V DC, minimum 1 A. There is a single 3.3
V switching regulator on the LCEVB providing MCU and peripheral power.
CAUTION
Connecting a power supply with a voltage greater than 5 V will result
in irrecoverable board damage. Check the power supply voltage
before connecting the plug to the LCEVB.
4.1.1. Power Input Connector
Power is supplied to the LCEVB via a 2.1 mm connector from the wall-plug mains adapter as shown
below. Note – if a replacement or alternative adapter is used, care must be taken to ensure the 2.1 mm
plug uses the correct polarisation as shown below:
Figure 3. 2.1 mm Power Connector
4.1.2. Power Switch
Slide switch SW2 can be used to isolate the power supply input from the EVB voltage regulators if
required.
Moving the slide switch to the right (away from the power connector) will turn the EVB ON.
Moving the slide switch to the left (towards the power connector) will turn the EVB OFF.
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4.1.3. Power Status LED
When power is applied to the LCEVB, two green LED’s adjacent to the regulator and power connector
show the presence of the supply voltages as follows:
LED DS5 – Indicates that the 5.0 V supply voltage is present
LED DS6 – Indicates that the 3.3 V switching regulator is functioning
If no LED’s are illuminated when power is supplied to the LCEVB and the power switch is in the “ON”
position, the power adapter may be faulty or there may be a fault with the LCEVB. If only one LED is
illuminated there may be a short in that power supply rail – check there is nothing shorting on the EVB.
If you continue to have problems, contact NXP for support.
CAUTION
In the event of a short on the regulator output (in which case one of the
LED’s would be off or dimly illuminated), the regulator and/or the shorted
component will likely be hot.
4.1.4. MCU and Peripheral Voltage Configuration
The following MCU supply rails are connected to the 3.3 V switching regulator:
VDD_HV_ADC0
VDD_HV_ADC1
VDD_HV_ADC1_REF
VDD_HV_A
VDD_HV_B
VDD_HV_FLA
External Ballast Transistor Supply
Similarly all of the peripheral interfaces (or the I/O power in the peripheral interface) are supplied from
3.3 V as is the reset circuitry and the voltage sense wire on the JTAG connector.
4.2. Reset Control (SW3)
The reset circuitry is
located in the bottom left
quarter of the LCEVB next
to the power switch
connector
The MCU has a single bi-directional open drain Reset pin. Rather than connect multiple devices to the
reset pin directly, a reset-in and reset-out buffering scheme has been implemented on the LCEVB as
shown in Figure 4. The reset “in” from the reset switch (SW3) and the debug connectors are logically
OR’d together using an AND gate and then connected to the buffer to provide an open-drain output.
The “reset-out” circuitry provides a buffered reset signal that can be used to drive any circuitry requiring
a reset control from the MCU.
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Initial Setup
This scheme is not required if it is guaranteed that anything driving the reset pin has an open drain drive
and that there is no significant output load on the MCU reset pin.
Figure 4. EVB Reset Control
4.2.1. Reset LEDs
As can be seen above, there are two reset LED’s that can be used to identify the source / cause of a reset:
RED LED DS8 (titled “MCU”) will illuminate if:
The MCU issues a reset (in this condition ONLY this LED will be illuminated and LED DS1
will be off)
There is a target reset (ie from the reset switch or from the debugger in which case LED DS1
will be ON)
YELLOW LED DS7 (titled “EXT”) will illuminate when an external hardware device issues a reset to
the MCU:
The reset switch is pressed
There is a reset being driven from one of the debug connectors
LED DS7 (Yellow)
OFF
OFF
LED DS8 (Red)
OFF
ON
ON
OFF
ON
ON
Table 2. Reset LED Decoding
Description
No Reset being issued from MCU or external logic
MCU has issued a reset
External reset issued from switch or debug BUT not being issued to MCU
(check R137 has not been removed)
External reset issued from reset switch or debug and has been issued to MCU.
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4.3. MCU Clock Configuration
There is an external 40MHz crystal connected to the MCU Fast External Oscillator (FXOSC) pins
EXTAL and XTAL.
There is also a 32.768 crystal connected to the MCU Slow External Oscillator (SXOSC) pins
OSC32K_EXTAL and OSC32K_XTAL. This can be used for accurate time keeping.
There are 2 pads PG6 and PG7 (located just below the MCU) on the LCEVB to facilitate measurement
of the CLKOUT1 and CLKOUT0 signals.
Note – there is no external clock input on the LCEVB
4.4. Debug Connector (P1)
The JTAG debug
connectors is located
in the top left corner
of the LCEVB
The LCEVB has a single 14-pin keyed JTAG connector for connection to an external debugger.
Before attaching or removing the debug cable from the LCEVB remove power from the EVB to prevent
damage to the LCEVB or debug hardware.
4.4.1. Debug Connector Pinout
The following tables list the pinout for the JTAG connector used on the LCEVB
Pin No
1
3
5
7
9
11
13
Function
TDI
TDO
TCLK
EVTI
RESET
VREF
RDY
Table 3. 14-Pin JTAG Debug Connector Pinout
Connection
Pin No
Function
PC0
2
GND
PC1
4
GND
PH9
6
GND
PL8
8
N/C
JTAG-RSTx
10
TMS
PER_HVA
12
GND
--14
JCOMP
Connection
GND
GND
GND
--PH10
GND
10K Pulldown
TDI, TDO and TMS have 10K pullup resistors on the LCEVB. TCLK has a 10K pulldown (R147) to
facilitate STANDBY exit without any additional code (at the sacrifice of slightly higher STANDBY
current), however this can be changed to a pullup if required by removing R147 and fitting the resistor
on R56.
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Communications & Memory Interfaces:
Table 4. JTAG Pins Pull State (from MPC5748G Reference Manual)
5. Communications & Memory Interfaces:
This section details the communication interface and storage peripherals that are implemented on the
LCEVB.
5.1. CAN Interfaces (P2, P3)
The CAN circuitry is
located on the top
right edge of the
LCEVB
The LCEVB incorporates two identical CAN interface circuits connected to MCU CAN0 and CAN1
using MC33901 transceivers. Both transceivers are configured for high speed operation by pulling pin 8
to GND via a 4.7 KOhm resistor. There are test points to allow the Select pin to be driven high if
desired. The MC33901 is pin compatible with other CAN transceivers supporting full CAN FD data
rates.
For flexibility, the CAN transceiver I/O is connected to a 0.1” header (P2 for CAN0 / P3 for CAN1)
rather than using non-standard DB9 connectors. The pinout of these headers is shown below.
1
H
L
GND
Figure 5. CAN Physical Interface Connectors
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The LIN Physical
interface circuits are
located on the right
edge of the LCEVB
5.2. LIN Interfaces (P6, P7)
The LCEVB incorporates two LIN transceiver circuits connected to MCU LIN0 and LIN1, using an
NXP MC33662 transceiver. The MPC5748G LIN0 supports both master and slave modes whereas LIN1
only supports master mode.
On the LCEVB, the LIN0 transceiver is configured as slave mode by default. Master mode operation is
possible by either populating a zero ohm resistor (R143) or buy fitting a jumper header (J2) – see the
schematics for details. The LIN0 transceiver is hard wired for master mode.
To save on board space and cost, both LIN transceivers are connected to 0.1” pitch 3x1 headers as
shown below rather than the usual LIN Molex header.
1
GND Vsup
Lin
Figure 6. LIN Physical Interface Connector
Note that in order for the LIN transceiver to function, external 12v must be supplied via pin 2 of the
connector
5.3. USB RS232 Serial Interface (P11)
The USB RS232
interface is on the
left hand edge of the
board (USB Type B
socket)
The LCEVB incorporates a USB RS232 serial interface providing RS232 connectivity via a direct USB
connection between the PC and the EVB. The circuit contains an FTDI FT2232D USB to Serial
interface which should automatically install the drivers for two additional COM ports on your PC. Note
that only one of these ports is used so you will need to try both (usually the higher numbered COM port
is the active one). For more information on the USB drivers and general fault finding, consult the FTDI
website at http://www.ftdichip.com/
The MCU LIN2 signals are routed to the FTDI transceiver (UART TX and RX). No handshaking
signals are implemented and no board configuration is required.
5.4. USB HOST Interface (P4)
The USB Host
interface is on the
top left corner of the
LCEVB on the left
side
The LCEVB includes a Type A (Host) USB interface, routed to a USB type A female connector. The
USB circuit contains a USB83340 transceiver with a MIC2026-1YM USB power switch. There is no
hardware user configuration required to use the USB circuit.
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Communications & Memory Interfaces:
5.5. Ethernet Interface (P5)
The Ethernet
interface is mid-way
along the top edge
of the LCEVB
The EVB incorporates a single DP83848c Ethernet transceiver with the circuitry configured for MII
mode. The transceiver is connected to a pulse J1011F21PNL RJ45 connector which includes a built-in
isolation transformer. There is no hardware configuration needed.
If you require RMII mode or access to both Ethernet ports on the MPC5748G, please purchase the
MPC5748G customer EVB and appropriate daughter cards.
Note that the MCU Ethernet signals are all in the VDD_HV_B domain. The Ethernet PHY will only
function with 3.3 V I/O so if you have made any modifications to the EVB power domain configuration
(via the zero ohm resistors), you need to ensure the VDD_HV_B domain is at 3.3 V before attempting to
use the Ethernet module. If VDD_HV_B is set to 5 V, the signals routed to the Ethernet PHY (see the
EVB schematics) must be left as tristate to prevent damage to the transceiver.
5.6. FlexRay (P8, P9, P10)
The FlexRay
interfaces are midway
down the left hand
edge of the LCEVB
The LCEVB incorporates two FlexRay TJA1080TS/N interfaces connected to MCU FlexRay channels
A and B and routed to two Molex 1.25 mm pitch PicoBlade shrouded headers (standard on many NXP
EVB’s). There is no hardware configuration required to use FlexRay.
Note that the LCEVB is supplied with a 40 MHz crystal by default. If FlexRay is configured to use the
external clock source, then the crystal should be left at 40 MHz.
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6. User Interface (I/O)
This section details the user I/O available on the LCEVB and includes the GPIO matrix, switches,
LED’s and the ADC variable resistor.
The GPIO matrix is
on the right hand
edge of the LCEVB
6.1. GPIO Matrix
A sub-set of available GPIO pins (available pins being those not already routed to LCEVB peripherals)
are available at the GPIO matrix as detailed below. The matrix provides an easy to follow, intuitive,
space saving grid of 0.1” header through-hole pads. Users can solder wires, fit headers or simply insert a
scope probe into the respective pad.
To use the matrix, simply read the port letter from the top or bottom row of text then the pad number
from the columns on the left or right of the matrix. For example, the 1st pad available on Port B is PB5
as outlined below.
Figure 7. GPIO Matrix
If a pad is populated in the matrix, it means this is available for exclusive use as GPIO. The exception to
this are the port pins detailed below which are also shared with switches or user LED’s (shaded red in
the matrix diagram above).
PD0, PD1, PD2, PD3 – HEX Encoder Switch
PA1, PA2
– User pushbutton Switches
If you require access to all of the available GPIO pads, the customer EVB and daughtercard provides
this additional functionality.
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User Interface (I/O)
6.2. User Switches (SW4, SW5)
The user pushbutton
switches are in the
bottom right corner
of the LCEVB
There are two active high (pulled low, driven to 3.3 V) pushbutton switches on the LCEVB connected
directly to MCU GPIO ports. No configuration is required to use the switches.
SW4 is connected to port PA1 (which is also the NMI pin) and SW5 is connected to port PA2
NOTE
The MCU ports used on the user pushbutton switches are also routed to
the GPIO matrix.
6.3. Hex Encoded Switch (SW1)
The hex encoder
switch is located to
the left of the GPIO
Matrix
There is a single hex encoded 16 position rotary switch on the LCEVB. This outputs a binary encoded
hex value (active high) on four MCU ports (Port D[0..3]).
Position
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
HEX_SW4
(PD3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 5. Hex Encoder Switch (SW2)
HEX_SW3
HEX_SW2
(PD2)
(PD1)
0
0
0
0
0
1
0
1
0
1
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
HEX_SW1
(PD0)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Note that POSN 0 will ensure that no voltage is applied to the pads. This allows the pads to be used as
normal GPIO (with 10K pulldown) and accessed at the respective pads on the GPIO matrix area.
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6.4. User LED’s (DS1, DS2, DS3, DS4)
The user LED’s are
above the user
switches in the lower
right corner
There are four active low user LED’s, DS1 to DS4, connected directly to 4 MCU ports (PG[2..5]) as
shown below. No configuration is required to use the LED’s.
Table 6. Use LED’s (DS1, DS2, DS3 and DS4)
User LED
MCU Pin
DS1
PG2
DS2
PG3
DS3
PG4
DS4
PG5
6.5.
ADC Input Potentiometer (RVAR, RV1)
The ADC Pot is
above the hex
switch to the left of
the GPIO matrix
There is a small variable resistor RV1 on the LCEVB which routes a voltage between 0v and 3.3 V to
MCU pin PB4. This is useful for quick ADC testing. Test point RVAR can be used to probe the voltage
with a voltmeter.
Note that this circuit provides a very rough way to evaluate the ADC. There is a small current limiting
series resistor network to limit the injection current to around 4.4 mA.
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MCU Port Pin LCEVB Functions
7. MCU Port Pin LCEVB Functions
The table below shows what each MCU pin is used for on the LCEVB.
No
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Port A
GPIO
GPIO 2
GPIO 2
Ethernet
GPIO
GPIO
GPIO
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
GPIO
GPIO
GPIO
GPIO
Port B
CAN0
CAN0
LIN0
LIN0
ADC Pot
GPIO
GPIO
GPIO
EXTAL32
XTAL32
SAI Audio
GPIO
GPIO
GPIO
GPIO
GPIO
No
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Port I
GPIO
GPIO
GPIO
GPIO
USB1
USB1
GPIO
USB1
GPIO
Port J
-----------
Table 7. LCEVB 176QFP Port Pin Functions
Port C
Port D
Port E
Port F
JTAG
GPIO 3
--GPIO
JTAG
GPIO 3
--GPIO
USB1
GPIO 3
FlexRay A
GPIO
USB1
GPIO 3
FlexRay A
GPIO
FlexRay B
GPIO
FlexRay B
GPIO
FlexRay A
GPIO
FlexRay B
GPIO
LIN1
GPIO
--GPIO
LIN1
GPIO
--GPIO
RS232
GPIO
--GPIO
RS232
GPIO
--GPIO
CAN1
GPIO
--GPIO
CAN1
--GPIO
FlexRay
GPIO
Ethernet
GPIO
FlexRay
GPIO
Ethernet
GPIO
FlexRay
GPIO
USB1
Ethernet
FlexRay
GPIO
USB1
Ethernet
Port G
Ethernet
Ethernet
GPIO 4,
GPIO 4
GPIO 4
GPIO 4
GPIO
GPIO
----USB1
USB1
Ethernet
Ethernet
USB1
USB1
Port H
Ethernet
Ethernet
Ethernet
------------JTAG
JTAG
USB1
USB1
-------
Key:
---
Pin not bonded out on 176QFP package
Pin not accessible on LCEVB
Ethernet
GPIO
GPIO
GPIO
GPIO
2
Shared with user switches
3
Shared with Hex Encoder Switch
4
Shared with user LED’s
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8. Appendix
The MPC5748G LCEVB schematics, Rev B are shown below.
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5
4
3
2
1
MPC5748G Low Cost Evaluation Board (MPC5748G-LCEVB)
Table Of Contents:
D
Power - Main input and 3.3V regulator
Power - MCU Power
Power - MCU Decoupling
Reset and JTAG
Clocks
MCU GPIO 1
MCU GPIO 2
Comms1 - CAN and LIN
Comms 2 - FTDI RS232 Interface
Comms 3 - USB Host Interface (device footprints only)
Comms 4 - Ethernet (MII Mode)
Comms 5 - FlexRay
User - Switches, LED's and Potentiometer
User - GPIO Pin Matrix
C
Sheet 2
Sheet 3
Sheet 4
Sheet 5
Sheet 6
Sheet 7
Sheet 8
Sheet 9
Sheet 10
Sheet 11
Sheet 12
Sheet 13
Sheet 14
Sheet 15
Revision Information
Rev Date
x1
14 Apr 2015
x2
08 May 2015
x3
18 May 2015
x4
19 May 2015
x5
26 May 2015
x6
27 May 2015
x7
29 May 2015
x8
31 May 2015
x9
01 Jun 2015
x10 01 Jun 2015
A
11 Jun 2015
AX1 29 Sep 2015
AX2
AX3
AX4
AX5
B
26 Oct 2015
29 Oct 2015
09 Dec 2015
20 Jan 2016
12 Feb 2016
Designer
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Andrew MacDonald
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Alasdair Robertson
Comments
Start of capture, Working version (256BGA)
Changed to 176 QFP Package and changed periperhal Matrix
Changes required for initial placement
Tidy Up, Replaced some "hard to source" components
Renumber and Back Annoted from Layout
Correction to GND on 3v3 Regulator circuit
Correction to CAN Test points
Few refdes changes after layout tweaks
Correction to user LED Refdes after re-number
DNP Jumpers. 0 Ohm resistors added accross LIN jumpers
Prototype Manufacture Release
Prodn Build changes (LIN0 default to Slave, LIN1 Master only)
PN Changed to MPC5748G-LCEVB
Change to JTAG Pulls to meet latest RM Spec
Changed RV1 current limit resistor. SW4 / SW5 refdes swap
Pull DOWN on TCLK to mitigate against STANDBY exit issue.
Updated NXP Logos
Updated NXP Logos
D
C
Caution:
These schematics are provided for reference purposes only.
As such,NXP does not make any warranty, implied or otherwise, as to the
suitability of circuit design or component selection (type or value) used in
these schematics for hardware design using the NXP Calypso family of
Microprocessors. Customers using any part of these schematics as a
basis for hardware design, do so at their own risk and NXP does not
assume any liability for such a hardware design.
B
B
3 Different test points used in design:
TPVx - Through Hole Pad small
TPHx - Through Hile Pad Large (for standard 0.1" header).
Also used on IO Matrix (IOMx)
TPX
- Surface Mount Wire Loop
Notes:
-
A
All components and board processes are to be ROHS compliant
All small capacitors are 0402 unless otherwise stated
All resistors are 0603 5% 0.1w unless otherwise stated. All zero ohm links are 0603
All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated
All jumpers are denoted Jx. Jumpers are 2mm pitch
Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2.
2 Pin jumpers generally have the "source" on pin 1.
- All switches are denoted SWx
- All test points (SMT wire loop style) are denoted TPx
- Test point Vias (just through hole pads) are denoted TPVx
Automotive Microcontroller Applications
East Kilbride, Scotland
NXP General Business Use
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A
Freescale AISG Applications, East Kilbride
Designer:
Signals (ports) have not been routed via busses as this makes it harder to determine where each signal goes.
A. Robertson
Drawn by:
User notes are given throughtout the schematics.
A. Robertson
Specific PCB LAYOUT notes are detailed in ITALICS
Approved:
5
A. Robertson
4
3
Drawing Title:
2
MPC5748G-LCEVB
Page Title:
Index and Title Page
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
1
of
15
5
4
3
2
1
Power Input and Linear Voltage Regulators
Power Supply Input
SW2
1
4
Jumpers can be fitted to
facilitate power measurements
5V0_SR
2.1mm Barrel
P12 Connector
1
2
3
3V3_SR
5
5V-IN
C26
0.1UF
D4
B340A
DNP
1
2
MCU_3V3
2
MCU_5V0
MCU_3V3
3
MCU_5V0
3
HDR 1X2
R48
0
5v0
R142
560
A
GND
C21
10UF
10V
D
J3
Main Power In
(SR = Swithing Reg)
1
C
D
Power Control
(Power Switch)
3
2
5V0_SR
J4
DNP
1
DS5
C
A
HDR 1X2
R49
0
LED GREEN
GND
5V0_SR 3V3_SR
3.3v Switching Regulator
PER_HVA
R47
0
R45
0
DNP
5V0_SR
PER_HVB
U10
8
1
3
C22
10UF
10V
2
9
VIN
PG
EN
SW
MODE
VOS
GND
FB
6
7
R138
1
L3
3V3_SR
178K
2
1.0uH
R46
0
R44
0
1
C
5
C
DNP
C23
22UF
10V
4
EP
R43
270
3v3
TPS62082
DS6
C
A
LED GREEN
GND
Inoput Voltage 5V, Output 3.3V at 700mA. Ripple 1.4mV, Approx 90% efficient
B
B
GND Test Points,
Top Side
GND15
GND16
1
1
1
1
1
GND1 GND2 GND3 GND4
1
Test and reference points
GND Test Points,
underside of board
GND
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
Page Title:
Power Input and Linear Voltage Regulators
5
4
3
2
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
2
of
15
5
4
3
Calypso MCU Power Connections
2
Power Supply Contraints:
Default Configuration:
- If
also
- If
must
- ALL MCU supply voltages are set to 3.3V
(ADC0, ADC1, VDD_HV_A, VDD_HV_B, VDD_HV_C,
VBallast)
- VDD_HV_FLA = External 3.3V supplied (jumper
fitted)
VDD_HV_A is driven from 3.3V, VDD_HV_FLA must
be supplied from 3.3V
VDD_HV_A is driven from 5V, the VDD_HV_FLA pin
be disconnected from 3.3V
- Don't attempt to over drive an analogue pad to 5V
when the digital VDD_HV_x supply is set to 3.3V.
This will trigger the ESD protectrion on that pad.
For example if VDD_HV_A is set to 3.3V and the
analogue supplies are set to 5V, you cannot drive 5V
into a pad in the VDD_HV_A domain
D
1
The analogue pins can only be driven to the
same voltage as the VDD_HV_x domain they are
situated in (ie max 3.3V) so makes sense for
the analogue supply and reference to be 3.3V
D
MCU_3V3
2 MCU_3V3
MCU_5V0
R98
0
R112 0
R103 0
DNP
R99
0
R111 0
DNP
0
DNP
DNP
R122 0
R124 0
Q50
MJD31CT4
B_CAP
1
HVFLA_CAP
HVB_CAP
HVA_CAP
R139
0
1
ADC1_CAP
ADC1REF_CAP
R102 0
ADC0_CAP
Individual MCU
supply control
R114 0
DNP
C
C_CAP
E_CAP
LVDEC_CAP
R101 0
R97
4
5v0
C
R100 0
3
3v3
LV_CAP
2 MCU_5V0
30
31
54
110
152
VDD_LP_DEC
VDD_LV_31
VDD_LV_54
VDD_LV_110
VDD_LV_152
32
VRC_CTRL
Flash
B
1.25v Core & External Ballast
109
EP
Central Pad for heat
dissipation & GND
177
VSS_LV_109
VSS_HV_VPP
Power Pins
26
97
7
28
55
57
86
123
150
VSS_HV_7
VSS_HV_28
VSS_HV_55
VSS_HV_57
VSS_HV_86
VSS_HV_123
VSS_HV_150
VSS_HV_ADC1
Package 2of3
VSS_HV_ADC0
VDD_HV_FLA
Calypso 6M 176QFP
Analogue
89
27
124
VDD_HV_B_124
6
59
85
151
VDD_HV_A_6
VDD_HV_A_59
VDD_HV_A_85
VDD_HV_A_151
98
99
VDD_HV_ADC1_REF
B
VDD_HV_ADC1
U20B
VDD_HV_ADC0
90
TPH2
PPC5748GSK0MKU6
1
R123 0
GND
GND
GND
TPH3
GND
Automotive Microcontroller
Applications
East Kilbride, Scotland
GND
A
Drawing Title:
MPC5748G-LCEVB
- The scheme shown has the analogue and digital grounds connected to the same plane
- This results in better ADC performance than using an analogue grond plane with single entry
point (or ferrite) to digital ground plane.
5
4
A
NXP General Business Use
Notes on signal Grounds:
3
Page Title:
Calypso MCU Power
2
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27899
Rev
B
PDF: SPF-27899
Sheet
1
3
of
15
5
4
3
2
1
Calypso MCU Decoupling and bulk storage
Flash
ADC
ADC0_CAP
ADC1_CAP
ADC1REF_CAP
Capacitor Types:
HVFLA_CAP
4700pF
0.1uF
0.68uF
1uF
2.2uF
D
C94
1uF
C93
0.1UF
GND
C97
1uF
C96
0.1UF
C95
1uF
GND
C118
2.2UF
GND
-
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
X7R,
X7R,
X7R,
X7R,
X7R,
50V
16V
16V
10V
10V
10%
10%
10%
10%
10%
0402
0402 (Kemet
0805 (Murata
0603 Low ESR
0603 Low ESR
C0402C104K4RAC)
GCM219R71C684KA37)
(Taiyo Yuden LMK107B7105KA-T)
(Taiyo Yuden LMK107B7225KA-TR)
D
GND
Place small Caps as close as possible to MCU pins
VDD_HVA
VDD_HVB
HVA_CAP
HVB_CAP
C112
2.2UF
C
C109
0.1UF
C120
0.1UF
C92
0.1UF
C100
0.1UF
C99
C
0.1UF
GND
GND
One 0.1uF cap per VDD_HV_x pin. Place as close as possible to pin
Ballast Transistor
VDD_LV
LP Internal Reg Cap
LV_CAP
B_CAP
C110
0.68uF
(low
ESR)
B
C111
0.68uF
(low
ESR)
C27
0.68uF
(low
ESR)
C108
0.1UF
C116
0.1UF
C98
0.1UF
C113
0.1UF
C_CAP
C119
4700pF
VDD_LV (1.25V) Decoupling. Place one of the 0.1uF caps close to each VDD_LV
pin. Place the 0.68uF caps on each side of the package such that there is
no cap on the side with the ballast transistor
(For regulator stability the total capacitance should be around 2.2uF).
GND
E_CAP
LVDEC_CAP
C122
2.2UF
C117
1uF
B
GND
GND
Place close to transistor
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
Page Title:
Calypso MCU Decoupling
5
4
3
2
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27899
Rev
B
PDF: SPF-27899
Sheet
1
4
of
15
5
4
3
2
1
Reset and External Clock In
Reset is in the
VDD_HVA domain.
Reset Input / Output
PER_HVA
PORST
PER_HVA
D
Connect an external LVI to pad
when supplying external 1.25V so
that PORST is asserted until
exterbal 1.25V supply is at
threshold and stable
3V3_SR
R37
10.0K
D
TPH1
R140
270
R135
10.0K
R134
10.0K
GND
JTAG-RSTx
JTAG-RSTx
1
RST-SWITCHx
2
7
SYSTEM-RSTx
3
MR
RESET
GND
4
Reset Switch
1
1
C
2
C121
0.1UF
GND
B3WN-6002
GND
PORSTx
7
R137 0
RST-INx
MCU-RSTx
5,7
Bi Directional reset
line to/from MCU
MCU-RSTx
Tri-State Buffered
RESET signal to
reset the MCU
Buffered RESET-out
2
SW3
R136
10.0K
RST
4
VCC
GND
SN74LVC2G08DCT
(1.65 to 5.5v operation)
PORSTx
GND
U11
U12A
VCC
C
5
TARGET
RESET
LED
8
Reset from
Debugger
DS7
YELLOW LED
1
(0603
C24
0.1UF 50V)
1
A
(0603
C25
0.1UF 50V)
ADM6315-26D2ARTZR7
(2.5 to 5v operation)
Active reset drive (high / low)
for any periperhals that need to
be reset when MCU is in reset
TPV5
C
3V3_SR
(0603
50V)
DS8
R141 270
Note:
A
C
GND
The Reset pad on Calypso is in the VDD_HV_A domain which can be run from either 3.3V or 5V
(selected by the VDD_HV_A and PER_HVA jumpers)
LED RED
(MCU RESET)
U12B
To maintian brightness on the LED's irrespective of the voltage setting, the LED's are
powered from constant 3.3V, grounded via the reset line.
5
3
RST-OUTx
12
RST-OUTx
6
SN74LVC2G08DCT
JTAG Standard 14-pin Connector
PER_HVA
B
B
R58
10.0K
7
7
7
PC0
PC1
PH9
PC0
PC1
PH9
R57
10.0K
R56
10.0K
DNP
R52
10.0K
(TDI)
(TDO)
(TCLK)
(EVTI)
(RESET)
(VREF)
(RDY)
DBUG-RSTx
5
5,7
JTAG-RSTx
JTAG-RSTx
(buffered
reset TO MCU)
MCU-RSTx
MCU-RSTx
(bidirectional
MCU reset)
R55
0
R54
0
ONCE Connector
P1
TDI
TDO
TCLK
EVTI
R147
10.0K
1
3
5
7
9
11
13
2
4
6
8
10
12
14
CON_2X7
(GND)
(GND)
(GND)
(N/C)
(TMS)
PH10
(GND)
JCOMP
R53
10.0K
Note TCLK needs to be pulled down to allow exit from STANDBY in some corner cases
DNP
Optional
Config
Automotive Microcontroller
Applications
East Kilbride, Scotland
GND
GND
A
7
PH10
PH10
A
NXP General Business Use
TMS
Drawing Title:
MPC5748G-LCEVB
Page Title:
5
4
3
2
Reset Circuitry & External Clock In
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
5
of
15
5
4
3
2
1
Clocks
D
D
Oscillators
PB9
C18
PB9
(EXTAL32)
PB8
Y3
32.768KHZ
1
R42
1.0M
DNP
7
12PF
2
7
PB8
(XTAL32)
C20
FC-255 32.7680K-A3
(Load Capacitance 7pF)
12PF
GND
C
MCU-EXTAL
C19
MCU-EXTAL
C
12PF
1
7
7
MCU-XTAL
MCU-XTAL
Y2
40.0MHZ
2
R41
1.0M
DNP
C17
NX8045GB-40.000M-STD-CSJ-1 XTAL
(Optimised for Automotive, 8pF Load capacitance)
12PF
GND
B
B
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
Page Title:
5
4
3
2
Clocks
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27899
Rev
B
PDF: SPF-27899
Sheet
1
6
of
15
5
4
3
2
1
Calypso GPIO 1 of 2
U20A
D
15
(WKPU2 / NMI0)
14,15
(WKPU3)
14,15
12
15
Key to text colours:
15
Purple - Comms Physical Interfaces
15
Orange - Other Peripherals and I/O
12
Blue
- Debug (JTAG & Nexus)
12
Black
- Clock, Reset and Control
12
RED
- I/O Matrix and other functions (eg LED)
12
Green
- I/O Matrix (dedicated)
12
15
15
15
PA 12..15 has SPI
15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
(GPIO)
(SW1 & GPIO**)
(SW2 & GPIO)
(MII_RXCLK)
(GPIO)
(GPIO)
(GPIO)
(MII_RXD2)
(RMII_RXD1)
(RMII_RXD0)
(MII_COL)
(RMII_RXER)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
9
9
9
9
14
15
15
15
6
6
15
15
15
15
15
15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
(CAN0_TX)
(CAN0_RX)
(LIN0_TX)
(LIN0_RX)
(ADC_POT)
(GPIO)
(GPIO)
(GPIO)
(XTAL32)
(EXTAL32)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
39
40
176
1
88
91
92
93
61
60
62
96
101
103
105
107
5
5
11
11
13
13
9
9
10
10
9
9
13
13
13
13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
(TDI)
(TDO)
(USB1_CLK)
(USB1_DIR)
(FR_B_TX_EN)
(FR_A_TX)
(LIN1_TX)
(LIN1_RX)
(RS232_TX)
(RS232_RX)
(CAN1_TX)
(CAN1_RX)
(FR_DBG0)
(FR_DBG1)
(FR_DBG2)
(FR_DBG3)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
154
149
145
144
159
158
44
45
175
2
36
35
173
174
3
4
14,15
14,15
14,15
14,15
15
15
15
15
15
15
15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
(HEX1 &
(HEX2 &
(HEX3 &
(HEX4 &
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
77
78
79
80
81
82
83
84
87
94
95
15
15
15
15
PD12
PD13
PD14
PD15
(GPIO)
(GPIO)
(GPIO)
(GPIO)
PD12
PD13
PD14
PD15
100
102
104
106
C
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
24
19
17
114
51
146
147
128
129
130
131
132
53
52
50
48
B
PD has ADC0 and ADC1
A
GPIO)
GPIO)
GPIO)
GPIO)
5
5
MCU-RSTx
PORSTx
MCU-RSTx
PORSTx
6
6
MCU-XTAL
MCU-EXTAL
MCU-XTAL
MCU-EXTAL
29
153
56
58
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
Calypso 176QFP
Package 1of3 GPIO Pins1
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PD12
PD13
PD14
PD15
18
20
156
157
160
161
167
168
21
22
23
25
133
127
136
137
PE2
PE3
PE4
PE5
(FR_A_TX_EN)
(FR_A_RX)
(FR_B_TX)
(FR_B_RX)
PE12
PE13
PE14
PE15
(MII_CRS)
(MII_RXD3)
(USB1_D2)
(USB1_D3)
63
64
65
66
67
68
69
70
42
41
46
47
43
49
126
125
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(RMII_MDIO)
(RMII_RXDV)
122
121
16
15
14
13
38
37
34
33
138
139
116
115
134
135
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
(RMII_MDC)
(RMII_TXCLK)
(LED1 & GPIO)
(LED2 & GPIO)
(LED3 & GPIO)
(LED4 & GPIO)
(CLKOUT1 GPIO)
(CLKOUT0 GPIO)
PG10
PG11
PG12
PG13
PG14
PG15
(USB1_D4)
(USB1_D5)
(MII_TXD2)
(MII_TXD3)
(USB1_D0)
(USB1_D1)
117
118
119
120
162
163
164
165
166
155
148
140
141
9
10
8
PH0
PH1
PH2
(RMII_TXD1)
(RMII_TXD0)
(RMII_TXEN)
PH9
PH10
PH11
PH12
(TCK)
(TMS)
(USB1_D6)
(USB1_D7)
PE2
PE3
PE4
PE5
13
13
13
13
PE12
PE13
PE14
PE15
12
12
11
11
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
12
12
PG0
PG1
PG2
PG3
PG4
PG5
12
12
14
14
14
14
PG10
PG11
PG12
PG13
PG14
PG15
11
11
12
12
11
11
PH0
PH1
PH2
12
12
12
PH9
PH10
PH11
PH12
5
5
11
11
D
C
(eMIOS
(eMIOS
(eMIOS
(eMIOS
E1UC_11_H)
E1UC_12_H)
E1UC_13_H)
E1UC_14_H)
1
PG6
1
PG7
B
RESET
PORST
Automotive Microcontroller
Applications
East Kilbride, Scotland
XTAL
EXTAL
A
NXP General Business Use
Drawing Title:
PPC5748GSK0MKU6
Page Title:
5
4
3
2
MPC5748G-LCEVB
Calypso GPIO 1of2
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27899
Rev
B
PDF: SPF-27899
Sheet
1
7
of
15
5
4
3
2
1
Calypso GPIO 2 of 2
U20C
Key to text colours:
D
Purple
Orange
Blue
Black
RED
Green
-
Comms Physical Interfaces
Other Peripherals and I/O
Debug (JTAG & Nexus)
Clock, Reset and Control
I/O Matrix and other functions (eg LED)
I/O Matrix (dedicated)
15
15
15
15
11
11
15
11
15
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(USB1_STP)
(USB1_NXT)
(GPIO)
(USB1_RST)
12
15
15
15
15
PI11
PI12
PI13
PI14
PI15
(ENET_RST)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
172
171
170
169
143
142
11
12
108
PI11
PI12
PI13
PI14
PI15
111
112
113
76
75
74
73
72
71
5
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
Calypso 176QFP
Package 3of3 GPIO Pins2
D
PI11
PI12
PI13
PI14
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
C
C
B
B
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
Page Title:
PPC5748GSK0MKU6
5
4
3
2
MPC5748G-LCEVB
Calypso GPIO 2of2
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27899
Rev
B
PDF: SPF-27899
Sheet
1
8
of
15
5
4
CAN & LIN Physical
3
CAN0 Physical Interface
VDD
2
PER_HVA
5V0_SR
- 5.0V input supply for CAN transceiver (4.5 to 5.5V)
VI/O - determines the signal level on MCU TX and RX pins
and can range from 2.8 to 5.5V
C60
0.1UF
C59
2.2UF
10V
STB - High for Standby mode, pulled low for normal mode.
C53
0.1UF
C52
2.2UF
10V
(0603
50V)
(0603
50V)
CAN termination resistor
footprint. Place on
underside of PCB
(CAN0_TX)
(CAN0_RX)
R64
R63
0
0
R51
CAN0_TX
1
CAN0_RX
4
TXD
R1
CANH
STB
TPV16
CANL
7
CAN0-CANH
6
CAN0-CANL
D
120
DNP
P2
1
2
3
HDR_1X3
GND
MC33901WEF
2
GND
All CAN and LIN signals are
in power domain VDD_HV_A.
5
RXD
8
4.70K CAN0-S
GND
VIO
PB0
PB1
VDD
PB0
PB1
U1
GND
GND
3
D
7
7
1
GND
- 5.0V input supply for CAN transceiver (4.5 to 5.5V)
C58
0.1UF
C57
2.2UF
10V
(0603
50V)
STB - High for Standby mode, pulled low for normal mode.
GND
7
7
PC10
PC11
PC10
PC11
(CAN1_TX)
(CAN1_RX)
R62
R59
0
0
R50
U2
CAN1_TX
1
CAN1_RX
4
4.70K CAN1-S
8
TXD
R2
CANH
STB
CANL
TPV15
C
GND
RXD
7
6
120
DNP
CAN1-CANH
P3
1
2
3
CAN1-CANL
HDR_1X3
GND
MC33901WEF
2
GND
(0603
50V)
VIO
C
CAN termination resistor
footprint. Place on
underside of PCB
C51
0.1UF
C50
2.2UF
10V
3
VI/O - determines the signal level on MCU TX and RX pins
and can range from 2.8 to 5.5V
5
VDD
PER_HVA
5V0_SR
VDD
CAN1 Physical Interface
GND
All interfaces will work at
3.3V or 5.0V (PER_HVA)
GND
Master Mode Pullup Enable
R143
DNP
J2
1
Configired as SLAVE by default
(Lin0 Supports Master and Slave)
PER_HVA
B
7
7
PB3
PB2
PB3
PB2
(LIN0_RX)
(LIN0_TX)
R74
R75
0
0
LIN0-RX
(Enable)
(Wake)
LIN0-TX
U6
1
2
3
4
RXD
EN
WAKE
TXD
INH
VSUP
LIN
GND
8
7
6
5
MC33662BLEF
GND
0
DNP
2
C
D51
HDR 1X2
GND
C70
0.1UF
C69
2.2UF
10V
(0603
50V)
(LEF = 20K Baud)
EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A
WAKE = GND ensures no spurious wakeups
D50
A
GF1A
C
A
GF1A
R18
2.0K
R17
2.0K
LIN0-VSUP
LIN0-LIN
Battery
Reverse
polarity &
Pulse
Protection
VSUP2
HDR_1X3
B
P7
1
2
3
1
LIN0 Physical Interface
Total current
through resistors
(LIN Bus at GND)
= 12mA (0.144W)
GND
3 pin
header
(NOT
Molex)
Each resistor spec
= 0.1W (0.2W total)
GND
MC33662LEF LIN transceiver is newer version of 33661 offering:
-
Full LIN compliance (33661 no longer compliant)
Improved ESD protection on LIN pin up to 15KV
Improved ESD on Wake and VSUP Pins
Other EMC and performance improvements
See freescale.com for more details
LIN1 Physical Interface
Master Mode Pullup Enable
PER_HVA
7
7
A
PC7
PC6
PC7
PC6
(LIN1_RX)
(LIN1_TX)
R60
R61
0
0
LIN1-RX
(Enable)
(Wake)
LIN1-TX
(TXD_0)
GND
R144
U3
1
2
3
4
RXD
EN
WAKE
TXD
INH
VSUP
LIN
GND
MC33662BLEF
(LEF = 20K Baud)
D52
A
0
C
D53
8
7
6
5
GND
C56
0.1UF
C55
2.2UF
10V
(0603
50V)
EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A
WAKE = GND ensures no spurious wakeups
GF1A
C
A
GF1A
Battery
Reverse
polarity &
Pulse
Protection
R6
2.0K
R7
2.0K
LIN1-VSUP
LIN1-LIN
Total current
through resistors
(LIN Bus at GND)
= 12mA (0.144W)
VSUP1
HDR_1X3
P6
4
3
A
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
GND
3 pin
header
(NOT
Molex)
Each resistor spec
= 0.1W (0.2W total)
GND
5
Automotive Microcontroller
Applications
East Kilbride, Scotland
1
2
3
1
Configired as MASTER by default
(Lin1 only supports Master mode)
2
Page Title:
CAN and LIN
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
9
of
15
5
4
3
2
1
USB RS232 (serial) Interface
- Self Powered mode. No power is taken from USB
- Device efaults to Dual serial (RS232) mode ie RS232 on both A and B
- Configurable I/O voltage on CHA / CHB via VDDIOA/B
5V0_SR
PER_HVA
D3
BGX50A
D1
D2
D4
D3
C105 (0603
0.1UF 50V)
R119
470
4
R38 27
USB_RN
USB_RP
C115
0.1UF
(0603
50V)
(0603
50V)
5V0_SR
GND
1.0M
X1
6 MHZ
2
R127
10.0K
CLK_XTIN_6M
43
CLK_XTOUT_6M
44
C103
0.1UF
C104
0.1UF
(0603
50V)
(0603
50V)
GND
48
1
2
GND
R118 10.0K
47
31
USBDP
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
SI/WUA
RSTOUT#
RESET#
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
XTIN
XTOUT
EECS
EESK
EEDATA
TEST
GND
VCCIOB
14
3
42
VCC2
USBDM
R36
GND
5
4
1
4
1
R39
4.70K
47PF 47PF
DNP DNP
GND
R34
1.5K
C106
USB_TYPE_B
8
7
R35 27
C107
C101
0.1UF
BCBUS0
BCBUS1
BCBUS2
BCBUS3
SI/WUB
GND1
GND2
GND3
GND4
USB_N
USB_P
3
3
2
S2
2
3
4
1
S1
VCCIOA
P11
3V3OUT
VCC1
6
GND
46
U9
GND
-D
+D
G
V
C102
2.2UF
10V
C114
0.033UF
3
2
C
D
5V0_SR
AVCC
FTDI interface will
work at 3.3V or 5.0V
(PER_HVA)
1
D
FTDI USB Serial Interface
AGND
All Signals are in
power domain
VDD_HV_A.
PWREN#
FT2232D
9
18
25
34
45
B
24
23
22
21
20
19
17
16
FTDI Pin 40 (TXD)
is Output from
FTDI Device,
connect to MCU RXD
15
13
12
11
10
Send Immediate / Wakeup
Disabled for CHA
PER_HVA
40
39
38
37
36
35
33
32
FTDI_TXD
FTDI_RXD
30
29
28
27
26
Send Immediate / Wakeup
Disabled for CHB
PER_HVA
C
FTDI Pin 39 (RXD)
is Input to FTDI
device, connect to
MCU TXD
R126 10.0K
R116
R115
0
0
(MCU_LIN2RX)
(MCU_LIN2TX)
PC9
PC8
PC9
PC8
7
7
5V0_SR
R125 10.0K
41
R117 10.0K
DNP
Disable Receiver when
in USB suspend mode
B
GND
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
Page Title:
USB RS232 Interface
5
4
3
2
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
10
of
15
5
4
3
2
1
USB (Type A Host and Type AB OTG)
3V3_SR
C3
0.1UF
C5
0.1UF
GND
7
7
7
7
7
7
7
7
PG14
PG15
PE14
PE15
PG10
PG11
PH11
PH12
7
8
8
7
PC3
PI4
PI5
PC2
8
PI7
(USB1_DO)
(USB1_D1)
(USB1_D2)
(USB1_D3)
(USB1_D4)
(USB1_D5)
(USB1_D6)
(USB1_D7)
PC3
PI4
PI5
PC2
R65
(USB1_DIR)
31
(USB1_STP)
29
(USB1_NXT)
2
USB1_CLK 1
30
PI7
(USB1_RST Active Low)
R3
10.0K
C64
2
33PF Y50
24MHZ
C
3
4
5
6
7
9
10
13
PG14
PG15
PE14
PE15
PG10
PG11
PH11
PH12
R71
10
27
A_XO 25
A_XI 26
16
15
33PF
C63
1
3V3_SR
R70
1.0M
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
VBUS
DM
DP
ID
VDD3V3_20
VDD1V8_28
VDD1V8_30
SPK_R
SPK_L
Crystals are
FOXSDLF/240F-20
(20pF Load
Capacitance)
GND
Adobe Acrobat
Document
USB Host, Type A
(Available on all packages)
D
GND
REFSEL0
REFSEL1
REFSEL2
RESET
XO
REFCLK/XI
C2
10UF
3V3_SR
CPEN
DIR
STP
NXT
CLKOUT
General Layout Note. Recommendation is to keep all
tracks between MCU and USB PHI less than 3" See
additional SMSC Layout guidelines PDF to the right
(0603
50V)
VBAT_5V
U50
21
32
(0603
50V)
(Layout Note: Place Series
Termination resistor close
to USB IC)
VDDIO
The USB
interface
only supports
3.3V
operation.
All I/O
signals must
be 3.3V. If
VDD_HVA is
set to 5V,
USB MCU pads
must be left
as tri-state
with no
pullups.
C6
10UF
33
D
5V0_SR
PAD_GND
USB Signals
are in
power
domain
VDD_HV_A
RBIAS
8
11
14
17
USB_A_EN
22
USB_A_VBUS
19
18
23
(1/10W 0603)
USB_A_DM
USB_A_DP
(ID=GND for HOST mode)
20
USB_A_VDD3.3
28
30
USB_TYPE_A_FEMALE
(Layout Note: Route DP and DM with
90 Ohm Differential Pair. Keep
tracks as short as possible)
(Select 60MHz CLKOUT
with 24MHz XTAL)
P4
S1
R73
20K
L50 26OHM
C54
C67
100UF 1.0UF
1
2
(16V (16V (0402
TANT) TANT) 50v)
C66
+
+
C68
10UF
1000pF
(35V
TANT)
(20K for HOST)
C1
1000pF
USB_A_5V
USB_A_DM
USB_A_DP
D-
D+
G
A1
A2
A3
A4
+
GND
V
S2
C78
1000pf
(1210
2KV)
R81
100
GND
(50V
0402)
USB_A_VDD1.8
GND
GND
GND
24
C
NC
R72
8.06K
1%
12
C4
1uF
(10V
0603
low
ESR)
USB83340
GND
GND
C65
1uF
(10V
0603
low
ESR)
GND
Layout Note:
Place caps &
resistor as
close to
device as
possible
GND
5V0_SR
U5
C76
0.1UF
C77
10UF
USB_A_EN
1
4
(0603
50V)
7
6
B
GND
USB Power Switch
ENA
ENB
FLGA
FLGB
IN
OUTA
GND
OUTB
2
FLG_A
TPV12
3
FLG_B
TPV13
8
USB_A_PWR
5
B
MIC2026-1YM
GND
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
Page Title:
5
4
3
2
USB Type A / Type AB
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
11
of
15
5
4
3
2
1
Ethernet (Configured for MII Mode)
All Ethernet Signals are in power
domain VDD_HV_B
1
Layout Note - Place Caps
and Resistors close to PHI
7
7
PG0
PF14
PG0
PF14
R109
R32
50
R31
R30
R29
R28
R24
R26
R27
R25
R22
50
50
50
50
50
50
50
50
50
(+MII)
(+MII)
(RMII)
(RMII)
(RMII)
(RMII)
(+MII)
(RMII)
(+MII)
RXD3
RXD2
RXD1
RXD0
RXDV
RXER
COL
CRS
RXCLK
46
45
44
43
39
41
42
40
38
(RMII)
(RMII)
MDC
(MDIO)
31
30
50
MCU Output
Resistors Next
to MCU on
daughtercard
PHI Output
Place Next to
PHI
Series Termination Resistors:
50 Ohms as per TI spec. Place
resistors as close to driving
source as possible. Termination
recommended for ALL MII signals
29
7
20
21
10/100 single phy
GND
RSVDPU1
RSVDPU2
6
5
4
3
2
1
25MHZ_OUT
TXD3_SNIMODE
TXD2
TXD1
TXD0
TXEN
TXCLK
dp83848c
TDP
TDN
RDP
RDN
RXD3_PHYAD3
RXD2_PHYAD2
RXD1_PHYAD1 LEDACTCOL_ANEN
RXD0_PHYAD1
LEDLINK_AN0
RXDV_MIIMODE LEDSPEED_AN1
RXER_MDIXEN
COL_PHYAD0
PFBOUT
CRS/CRS_DV/LED_CFG
RXCLK
PFBIN1
PFBIN2
MDC
MDIO
RESET
PWRDN_INT
RBIAS
25
TDP
TDN
14
13
RDP
RDN
28
26
27
LED_Y
LED_G
23
PFBOUT
B
8
RST-OUTx
PI11
R82
RST-OUTx
50
R83
PI11
C10
0.1UF
R14
49.9
1%
TPV17
17
16
GND
0
3V3_SR
Pulse J1011F21PNL
(Includes built in
transformer)
P5
RJ45-8
(0603
50V)
1
2
3
4
5
6
7
8
GND
3V3_SR
R15
49.9
1%
GND
R16
49.9
1%
18
37
C11
0.1UF
C8
0.1UF
C7
0.1UF
(0603
50V)
(0603
50V)
(0603
50V)
TD+
TDGND1
CT_3
GND_4
GND_5
CT_6
RD+
GND2
RD-
CG1
CG2
C
GND
R5
270
R4
270
3V3_SR
GND
3V3_SR
GND
24
Place Caps close
to connector
RBIAS
R10
4.87K
GND
5
3V3_SR
R13
49.9
1%
GC
GA
C
TXD3
TXD2
TXD1
TXD0
TXEN
TXCLK
(+MII)
(+MII)
(RMII)
(RMII)
(RMII)
(RMII)
X1
X2
(0603
50V)
11
12
PE13
PA7
PA8
PA9
PF15
PA11
PA10
PE12
PA3
50
50
50
50
50
CLKIN_X1 34
33
X2
(0603
50V)
D
YA
YC
7
7
7
7
7
7
7
7
7
PE13
PA7
PA8
PA9
PF15
PA11
PA10
PE12
PA3
R104
R105
R106
R107
R108
(RMII)
(+MII)
C79
0.1UF
9
10
PG13
PG12
PH0
PH1
PH2
PG1
U8
22
GND
0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
R23
32
48
Y1
25MHZ
C14
PG13
PG12
PH0
PH1
PH2
PG1
(0603
50V)
R11
2.2K
5%
C81
0.1UF
8
9
10
11
12
GND
R12
2.2K
5%
AVDD33
2
33PF
C71
10UF
(Bulk
Storage)
IOVDD33_1
IOVDD33_2
33PF
1
(MII Clock)
C73
0.1UF
AGND_1
AGND_2
DGND
IOGND_1
IOGND_2
C15
7
7
7
7
7
7
3V3_SR
L51
120OHM
2
19
15
36
35
47
D
3V3_SR
The Ethernet interface only supports
3.3V operation. All I/O signals must
be 3.3V. If VDD_HVA is set to 5V,
Ethernet MCU pads must be left as
tri-state with no pullups.
C72
0.1UF
C74
0.1UF
C75
+
C80
0.1UF
(0603
50V)
(0603
50V)
10UF
(TANT)
(0603
50V)
Layout Note:
Place 0.1uF cap close to each pin.
10uF TANT as close to pin 23 as
possible as shown in diagram below
taken from TI device specificaiton
B
DNP
3V3_SR
R84
10.0K
PFBIN1
Reset Control:
- Reset from MCU Reset Out (will reset with MCU)
- Reset from GPIO. Allows MCU to reset PHY as well as hold PHY in reset
while reset config data can be driven onto pins to change mode etc.
PFBIN2
PFBOUT
GND
Boot Configuration (using PHY internal Pulls)
R110
- Auto Negotiation Enable (All speeds / duplex supported)
(AN_EN, AN0 and AN1 all Internal PullUP)
- Operating Mode (MII)
(SNI_Mode Internal PullDown, MII_Mode control via PF15)
- LED Configuraiton (Mode1)
(LED_CFG Internal PullUp)
- MDIX Enable (Auto MDIX Enabled)
(MDIX_EN Internal PullUP)
PF15
(MII_MODE)
2.2K 5%
GND
Configured for MII Mode
3V3_SR
MDIO Pullup
R113
1.5K
PF14
Automotive Microcontroller
Applications
East Kilbride, Scotland
- Physical Address (set to 0b00001)
(PHYAD[0] Internal PullUp, PHYAD[1..4] Internal PullDown)
A
A
NXP General Business Use
Layout Note:
Drawing Title:
MII Mode resistor and the MDIP ullup resistor should be placed as close as possible to the
PF15 / PF14 tracks to reduce the effect of a stub on the transmission line.
Page Title:
MPC5748G-LCEVB
Ethernet
5
4
3
2
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
12
of
15
5
4
3
2
1
FlexRAY Physical Interface
All Signals are in
power domain VDD_HV_A.
D
Decoupling Caps for BOTH IC's. Place next to power pins.
Note on VBAT:
- Operational range is 6.5v to 60V
- Undervoltage detection is max 4.5v
FlexRAY interface will
work at 3.3V or 5.0V
(PER_HVA)
7
7
PC12
PC14
PC12
PC14
(FR_DBG0)
(FR_DBG2)
FlexRAY
debug
connector
P9
1
2 (FR_DBG1)
3
4 (FR_DBG3)
PC15
PC13
FRBATB
PER_HVA
5V0_SR
D
C89
10UF
PER_HVA
DNP
7
7
FRBATA
On EVB this is supplied from 5v, In theory this
should be to battery with 60uS delay between
applying Vbat and I/O voltages. If necessary,
12V can be externally supplied by removing the
resistor and connecting pad to 12v
5V0_SR
PC15
PC13
C88
10UF
C87
10UF
C86
10UF
FRBATA
R21
0
C85
0.1UF
C84
0.1UF
C83
0.1UF
C82
0.1UF
(0603
50V)
(0603
50V)
(0603
50V)
(0603
50V)
FRB2
VBAT
VBUF
VCC
VIO
PC5
PE2
PE3
(FR_A_TX)
(FR_A_TX_EN)
(FR_A_RX)
R120
R90
R89
0
0
0
FRA-JTXD
FRA-JTXEN
FRA-JRXD
U7
GND
11
10
PER_HVA
BGE: Bus Guardian Enable. Pull
high to enable transmitter
R88
R87
R121
R91
STBN: Standby Input. Pull High
for non standby mode
C
10.0K
10.0K
10.0K
10.0K
FRA-BGE
FRA-STBN
FRA-EN
5
6
8
9
3
FRA-WAKE 15
EN: Enable Input. PUll high to
enable
TRXD0
TRXD1
TXD
TXEN
BGE
STBN
EN
WAKE
RXD
ERRN
RXEN
FlexRAY A
18
17
7
13
12
FRA-INH2
FRA-INH1
FRA-BP
1
FRA-BM
4
FRA-ERRN
FRA-RXEN
R33
47.0
1%
TPV9
TPV7
L2
2
FRA-DATA-A
3
FRA-DATA-B
DLW43SH
TPV1
TPV4
C16
10PF
C91
4700PF
(50V 0805)
R19
47.0
1%
P10
1
2
(0603)
C12
GND
10PF
Crimped lead - 279-9522
Receptacle housing - 279-9156
C
(0603)
Bus voltage +/- 12V (VBAT = 12v)
Components spec'd for 12V operation
GND
PER_HVA
5V0_SR
FlexRAY B
FRBATB
FRB1
(FR_B_TX)
(FR_B_TX_EN)
(FR_B_RX)
R85
R79
R78
0
0
0
FRB-JTXD
FRB-JTXEN
FRB-JRXD
B
U4
GND
11
10
PER_HVA
R77
R76
R86
R80
10.0K
10.0K
10.0K
10.0K
FRB-BGE
FRB-STBN
FRB-EN
5
6
8
9
3
FRB-WAKE 15
TRXD0
TRXD1
TXD
TXEN
BGE
STBN
EN
WAKE
16
GND
INH2
INH1
BP
BM
GND
PE4
PC4
PE5
0
4
19
20
14
R9
VIO
VCC
VBUF
VBAT
PE4
PC4
PE5
1
2
TJA1080TS/N
16
GND
7
7
7
INH2
INH1
BP
BM
GND
PC5
PE2
PE3
VIO
VCC
VBUF
VBAT
7
7
7
4
19
20
14
GND
RXD
ERRN
RXEN
1
2
18
17
7
13
12
FRB-INH2
FRB-INH1
FRB-BP
1
FRB-BM
4
FRB-ERRN
FRB-RXEN
R20
47.0
1%
TPV8
TPV6
L1
2
FRB-DATA-A
3
FRB-DATA-B
DLW43SH
TPV2
TPV3
R8
47.0
1%
C13
10PF
C90
4700PF
(50V 0805)
B
P8
(0603)
1
2
C9
GND
10PF
Crimped lead - 279-9522
Receptacle housing - 279-9156
(0603)
TJA1080TS/N
Bus voltage +/- 12V (VBAT = 12v)
Components spec'd for 12V operation
GND
MODE
Normal
Rec Only
Go to Sleep
Sleep
EN
1
0
1
0
STBN
1
1
0
0
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
Page Title:
5
4
3
2
FlexRAY Physical Interface
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
13
of
15
5
4
3
2
1
User Peripheralls (Led's, Switches and ADC Pot)
Switches are hard wired to 3.3V rather than 5V so it's not possible to drive 5V into a 3.3V pad (which would cause damage)
Similarly, the LED's are active low with 3.3v supply so can be safely coupled to pads on either 3.3V or 5V domains
The ADC input is limited to 3.3V, again to prevent driving 5V into a 3.3V pad which would cause damage
User LED's (Active Low)
PG[2..5] share eMIOS1
UC[11..14] with PWM
functionality
ADC Input Pot and Test Point
DS1
C
A
C
(USR_LED1)
(USR_LED2)
(USR_LED3)
(USR_LED4)
270
R133
270
3V3_SR
A
3
1
2
PG2
PG3
PG4
PG5
PG2
PG3
PG4
PG5
R129
RV1 2K
DS2
7
7
7
7
D
3V3_SR
DS3
C
A
DS4
C
A
R131
270
R130
270
RVAR
Current limit resistors to ensure
injection spec of 5mA is not
exceeded
GND
R40
1
D
1.5K
PB4
PB4
(ADC1_P[0])
7
R146 1.5K
LED's are SMD (1206) Yellow
Note that LED2 and LED4 (PG3 and PG5) can be
controlled in LPU_RUN mode (and also have pad
keepers in LPU_STANDBY)
Hex Encoded Switch (Active High)
C
3V3_SR
C
SW1
R92
C
B C D
E
A
F
9
8
1
7
6 5 3 2
4
0
100
1
(HEX_SW1)
PD0
2
(HEX_SW2)
PD1
4
(HEX_SW3)
PD2
8
(HEX_SW4)
PD3
PD0
7,15
PD1
7,15
PD2
7,15
PD3
7,15
DRS4016
R93
R94
R95
R96
10.0K
10.0K
10.0K
10.0K
GND
User Pushbutton Switches (Active High)
B
3V3_SR
Note - PA1 is
also the NMI pin!
SW4
1
2
1
2
SW5
(PB_SW1)
(PB_SW2)
(eMIOS H / X)
(eMIOS G / X)
R132
R128
10.0K
10.0K
B
PA1
PA2
PA1
PA2
7,15
7,15
OMRON B3WN-6002 Pushbutton Switch
GND
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
Page Title:
5
4
3
2
MPC5748G-LCEVB
User Peripherals
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
14
of
15
5
4
PD[0..3] shared with
Hex Switch
C
B
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD12
PD13
PD14
PD15
7
7
7
7
7
7
7
7
7
7
7
7
7
7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
8
8
8
8
8
8
8
8
8
8
PI0
PI1
PI2
PI3
PI6
PI8
PI12
PI13
PI14
PI15
PB5
PB6
PB7
PB10
PB11
PB12
PB13
PB14
PB15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD12
PD13
PD14
PD15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PI0
PI1
PI2
PI3
PI6
PI8
PI12
PI13
PI14
PI15
PORTB
1
PA4
IOM4
1
PA5
IOM19
1
PA6
IOM20
1
PB5
IOM21
1
PB6
IOM22
1
PB7
IOM23
1
PB10
IOM39
1
PB11
IOM40
1
PB12
IOM41
1
PB13
IOM42
1
PB14
IOM43
1
PB15
IOM56
1
PA12
IOM36
1
PA13
IOM37
1
PA14
IOM38
1
PA15
IOM55
TPH4
GND
PORTD
PortF
1
PD0
IOM5
1
PD1
IOM6
1
PD2
IOM7
1
PD3
IOM8
1
PD4
IOM9
1
PD5
IOM24
1
PD6
IOM25
1
PD7
IOM26
1
PD8
IOM27
1
PD9
IOM28
1
PD10
IOM44
1
PF0
IOM10
1
PF1
IOM11
1
PF2
IOM12
1
PF3
IOM13
1
PF4
IOM14
1
PF5
IOM29
1
PF6
IOM30
1
PF7
IOM31
1
PF8
IOM32
1
PF9
IOM33
1
PF10
IOM48
1
PF11
IOM49
1
PF12
IOM50
1
PF13
IOM51
1
1
PD12
IOM45
1
PD13
IOM46
1
PD14
IOM47
1
PD15
IOM57
PortI
D
1
PI0
IOM15
1
PI1
IOM16
1
PI2
IOM17
1
PI3
IOM18
1
PI6
IOM34
1
PI8
IOM35
C
1
PI12
IOM52
1
PI13
IOM53
1
PI14
IOM54
1
PI15
IOM58
TPH5
TPH6
TPH7
TPH8
1
7,14
7,14
7,14
7,14
7
7
7
7
7
7
7
7
7
7
7
PB5
PB6
PB7
PB10
PB11
PB12
PB13
PB14
PB15
PORTA
1
PA0
IOM1
1
PA1
IOM2
1
PA2
IOM3
1
7
7
7
7
7
7
7
7
7
PA0
PA1
PA2
PA4
PA5
PA6
PA12
PA13
PA14
PA15
1
D
PA0
PA1
PA2
PA4
PA5
PA6
PA12
PA13
PA14
PA15
2
1
7
7,14
7,14
7
7
7
7
7
7
7
PA[1,2] shared with
user switches
3
All pads are DNP (Do Not Populate) 0.1" pitch headers placed on a 0.1" grid
1
GPIO Pin Matrix
5 GND Pads (one at bottom of each colum)
B
Layout Notes:
Pads must be placed in a 5 (W) x 16(H) matrix pattern, 2.54 mm pitch
- one column for each port
- 16 tall (1 row for each port number from 0 to 15).
- GND pad at bottom of each colum
- After production, pads should be through hole (not solder filled)
Automotive Microcontroller
Applications
East Kilbride, Scotland
A
A
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
Page Title:
GPIO Pin Matrix
5
4
3
2
Size
B
Document Number
Date:
Friday, February 12, 2016
SCH-27897
Rev
B
PDF: SPF-27897
Sheet
1
15
of
15
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© 2016 NXP B.V.
Document Number: MPC5748GLCEVBUG
Rev. 0
05/2016
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