MPC7410VS450NE

Freescale Semiconductor MPC7410EC Rev. 6.1, 11/2007 Technical Data MPC7410 RISC Microprocessor Hardware Specifications The MPC7410 is a PowerPC™ reduced instruction set computing (RISC) microprocessor. This document describes pertinent electrical and physical characteristics of the MPC7410. For functional characteristics of the processor, refer to the MPC7410 RISC Microprocessor User’s Manual. To locate any published errata or updates for this document, refer to the web site at http://www.freescale.com. 1 Overview The MPC7410 is the second implementation of the fourth generation (G4) microprocessors from Freescale. The MPC7410 implements the full PowerPC 32-bit architecture and is targeted at both computing and embedded systems applications. Some comments on the MPC7410 with respect to the MPC750: • • • The MPC7410 adds an implementation of the new AltiVec™ technology instruction set. The MPC7410 includes significant improvements in memory subsystem (MSS) bandwidth and offers an optional, high-bandwidth MPX bus interface. The MPC7410 adds full hardware-based multiprocessing capability, including a five-state cache coherency protocol (four MESI states plus a fifth state for shared intervention). © Freescale Semiconductor, Inc., 2005, 2007. All rights reserved. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical and Thermal Characteristics . . . . . . . . . . . . 7 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 29 System Design Information . . . . . . . . . . . . . . . . . . . 34 Document Revision History . . . . . . . . . . . . . . . . . . . 48 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 53 Features • • • • The MPC7410 is implemented in a next generation process technology for core frequency improvement. The MPC7410 floating-point unit has been improved to make latency equal for double- and single-precision operations involving multiplication. The completion queue has been extended to eight slots. There are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms, or the branch unit. The MPC750 four-stage pipeline model is unchanged (fetch, decode/dispatch, execute, complete/writeback). Some comments on the MPC7410 with respect to the MPC7400: • • • The MPC7410 adds configurable direct-mapped SRAM capability to the L2 cache interface. The MPC7410 adds 32-bit interface support to the L2 cache interface. The MPC7410 implements a 19th L2 address pin (L2ASPARE on the MPC7400) in order to support additional address range. The MPC7410 removes support for 3.3-V I/O on the L2 cache interface. Figure 1 shows a block diagram of the MPC7410. 2 Features This section summarizes features of the MPC7410 implementation of the PowerPC architecture. Major features of the MPC7410 are as follows: • • Branch processing unit — Four instructions fetched per clock — One branch processed per cycle (plus resolving two speculations) — Up to one speculative stream in execution, one additional speculative stream in fetch — 512-entry branch history table (BHT) for dynamic prediction — 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay slots Dispatch unit — Full hardware detection of dependencies (resolved in the execution units) — Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU) — Serialization control (predispatch, postdispatch, execution serialization) MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 2 Freescale Semiconductor Freescale Semiconductor Completion Queue (8-Entry) Completion Unit VSCR Vector ALU Vector Permute Unit 19-Bit L2 Address Bus 64- or 32-Bit L2 Data Bus Ability to Complete Up to Two Instructions Per Clock Integer Unit 2 Reservation Station + CTR LR 32-Bit Address Bus 64-Bit Data Bus L2PMCR L2 Castout IBAT Array DBAT Array Reservation Station (2-Entry) 128-Entry DTLB SRs (Original) Data MMU 128-Entry ITLB SRs (Shadow) Instruction MMU 32-Kbyte I Cache Instruction Instruction Reload Buffer Reload Table Memory Subsystem Data Reload Data Reload Buffer Table 64-Bit 6 Rename Buffers FPSCR FPSCR + x ÷ FloatingPoint Unit Reservation Station 32-Kbyte Tags D Cache Tags 128-Bit (4 Instructions) FPR File Completed L1 Stores Operations 64-Bit Load/Store Unit + (EA Calculation) Load Fold 32-Bit Finished Queue Stores Vector Touch Queue 6 Rename Buffers GPR File PA EA Bus Interface Unit Data L2 Miss Transaction Queue 32-Bit System Register Unit Reservation Station 64-Bit (2 Instructions) Dispatch Unit BHT (512-Entry) Branch Processing Unit BTIC (64-Entry) L2 Controller L2 Data L2 Tags Transaction Queue L2CR 32-Bit + x ÷ Integer Unit 1 Reservation Station Instruction Queue (6-Word) 128-Bit 6 Rename Buffers VR File 128-Bit VSIU VCIU VFPU Reservation Station 2 Instructions Reservation Station • • • • • • Additional Features Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor Fetcher Instruction Unit Features Figure 1. MPC7410 Block Diagram MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 3 Features • • • • • • • Decode — Register file access — Forwarding control — Partial instruction decode Completion — Eight-entry completion buffer — Instruction tracking and peak completion of two instructions per cycle — Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization, and all instruction flow changes Fixed point units (FXUs) that share 32 GPRs for integer operands — Fixed point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical — Fixed point unit 2 (FXU2)—shift, rotate, arithmetic, logical — Single-cycle arithmetic, shifts, rotates, logical — Multiply and divide support (multi-cycle) — Early out multiply Three-stage floating-point unit and a 32-entry FPR file — Support for IEEE Std 754™ single- and double-precision floating-point arithmetic — Three-cycle latency, one-cycle throughput (single- or double-precision) — Hardware support for divide — Hardware support for denormalized numbers — Time deterministic non-IEEE mode System unit — Executes CR logical instructions and miscellaneous system instructions — Special register transfer instructions AltiVec unit — Full 128-bit data paths — Two dispatchable units: vector permute unit and vector ALU unit. — Contains its own 32-entry, 128-bit vector register file (VRF) with 6 renames — The vector ALU unit is further subdivided into the vector simple integer unit (VSIU), the vector complex integer unit (VCIU), and the vector floating-point unit (VFPU). — Fully pipelined Load/store unit — One-cycle load or store cache access (byte, half word, word, double word) — Two-cycle load latency with 1-cycle throughput — Effective address generation — Hits under misses (multiple outstanding misses) — Single-cycle unaligned access within double-word boundary — Alignment, zero padding, sign extend for integer register file — Floating-point internal format conversion (alignment, normalization) — Sequencing for load/store multiples and string operations MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 4 Freescale Semiconductor Features • • • • — Store gathering — Executes the cache and TLB instructions — Big- and little-endian byte addressing supported — Misaligned little-endian supported — Supports FXU, FPU, and AltiVec load/store traffic — Complete support for all four architecture AltiVec DST streams Level 1 (L1) cache structure — 32 Kbyte, 32-byte line, eight-way set-associative instruction cache (iL1) — 32 Kbyte, 32-byte line, eight-way set-associative data cache (dL1) — Single-cycle cache access — Pseudo least-recently-used (LRU) replacement — Data cache supports AltiVec LRU and transient instructions algorithm — Copy-back or write-through data cache (on a page-per-page basis) — Supports all PowerPC memory coherency modes — Nonblocking instruction and data cache — Separate copy of data cache tags for efficient snooping — No snooping of instruction cache except for ICBI instruction Level 2 (L2) cache interface — Internal L2 cache controller and tags; external data SRAMs — 512-Kbyte, 1-Mbyte, and 2-Mbyte two-way set-associative L2 cache support — Copy-back or write-through data cache (on a page basis, or for all L2) — 32-byte (512-Kbyte), 64-byte (1-Mbyte), or 128-byte (2-Mbyte) sectored line size — Supports pipelined (register-register) synchronous BurstRAMs and pipelined (register-register) late write synchronous BurstRAMs — Supports direct-mapped mode for 256 Kbytes, 512 Kbytes, 1 Mbyte, or 2 Mbytes of SRAM (either all, half, or none of L2 SRAM must be configured as direct-mapped) — Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported — 64-bit data bus which also supports 32-bit bus mode — Selectable interface voltages of 1.8 and 2.5 V Memory management unit — 128-entry, two-way set-associative instruction TLB — 128-entry, two-way set-associative data TLB — Hardware reload for TLBs — Four instruction BATs and four data BATs — Virtual memory support for up to 4 hexabytes (252) of virtual memory — Real memory support for up to 4 gigabytes (232) of physical memory — Snooped and invalidated for TLBI instructions Efficient data flow — All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128 bits wide — dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 5 Features — — — — — • • • • L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s. Up to eight outstanding, out-of-order, cache misses between dL1 and L2/bus Up to seven outstanding, out-of-order transactions on the bus Load folding to fold new dL1 misses into older, outstanding load and store misses to the same line Store miss merging for multiple store misses to the same line. Only coherency action taken (that is, address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed). — Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1 — Separate additional queues for efficient buffering of outbound data (castouts, write throughs, and so on) from dL1 and L2 Bus interface — MPX bus extension to 60x processor interface — Mode-compatible with 60x processor interface — 32-bit address bus — 64-bit data bus — Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x supported — Selectable interface voltages of 1.8, 2.5, and 3.3 V Power management — Low-power design with thermal requirements very similar to MPC740 and MPC750 — Low-voltage processor core — Selectable interface voltages can reduce power in output buffers — Three static power saving modes: doze, nap, and sleep — Dynamic power management Testability — LSSD scan design — IEEE Std 1149.1™ JTAG interface — Array built-in self test (ABIST)—factory test only — Redundancy on L1 data arrays and L2 tag arrays Reliability and serviceability — Parity checking on 60x and L2 cache buses MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 6 Freescale Semiconductor General Parameters 3 General Parameters The following list provides a summary of the general parameters of the MPC7410: Technology Die size Transistor count Logic design Packages 0.18 µm CMOS, six-layer metal 6.32 mm × 8.26 mm (52 mm2) 10.5 million Fully static Surface mount 360 ceramic ball grid array (CBGA) Surface mount 360 high coefficient of thermal expansion ceramic ball grid array (HCTE_CBGA) Surface mount 360 high coefficient of thermal expansion ceramic ball grid array with lead free C5 spheres (HCTE_CBGA Lead Free C5 Spheres) Surface mount 360 high coefficient of thermal expansion ceramic land grid array (HCTE_LGA) Core power supply 1.8 V ± 100 mV DC (nominal; see Table 3 for recommended operating conditions) I/O power supply 1.8 V ± 100 mV DC or 2.5 V ± 100 mV 3.3 V ± 165 mV (system bus only) (input thresholds are configuration pin selectable) 4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7410. 4.1 DC Electrical Characteristics The tables in this section describe the MPC7410 DC electrical characteristics. Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings 1 Characteristic Symbol Maximum Value Unit Notes Core supply voltage VDD –0.3 to 2.1 V 4 PLL supply voltage AVDD –0.3 to 2.1 V 4 L2AVDD –0.3 to 2.1 V 4 OVDD –0.3 to 3.6 V 3, 6 L2OVDD –0.3 to 2.8 V 3 Processor bus Vin –0.3 to OVDD + 0.2 V V 2, 5 L2 bus Vin –0.3 to L2OVDD + 0.2 V V 2, 5 JTAG signals Vin –0.3 to OVDD + 0.2 V V — Tstg –55 to 150 °C — L2 DLL supply voltage Processor bus supply voltage L2 bus supply voltage Input voltage Storage temperature range MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 7 Electrical and Thermal Characteristics Table 1. Absolute Maximum Ratings 1 (continued) Characteristic Rework temperature Symbol Maximum Value Unit Notes Trwk 260 °C — Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: V in must not exceed OVDD or L2OVDD by more than 0.2 V at any time including during power-on reset. 3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0 V at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4 V at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD and have a maximum value OVDD of –0.3 to 2.8 V. Figure 2 shows the allowable undershoot and overshoot voltage for the MPC7410. (L2)OV DD + 20% (L2)OVDD + 5% (L2)OVDD VIH VIL GND GND – 0.3 V GND – 0.7 V Not to Exceed 10% of tSYSCLK (OVDD) or tL2CLK (L2OV DD) Figure 2. Overshoot/Undershoot Voltage The MPC7410 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The MPC7410 core voltage must always be provided at nominal voltage (see Table 3 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 2. Voltage must be provided to the L2OVDD power pins even if the interface is not used. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins BVSEL and L2VSEL at the negation of the signal HRESET. These signals must remain stable during part operation and cannot change. The output voltage will swing from GND to the maximum voltage applied to the OVDD or L2OVDD power pins. MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 8 Freescale Semiconductor Electrical and Thermal Characteristics Table 2. Input Threshold Voltage Setting BVSEL Signal 3 Processor Bus Input Threshold is Relative to: L2VSEL Signal 3 L2 Bus Input Threshold is Relative to: Notes 0 1.8 V 0 1.8 V 1 HRESET 2.5 V HRESET 2.5 V 1, 2 1 3.3 V 1 2.5 V 1, 4, 5 ¬HRESET 3.3 V ¬HRESET Not Supported 6 Notes: 1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied. 2. To select the 2.5-V threshold option, BVSEL and/or L2VSEL should be tied to HRESET so that the two signals change state together. This is the preferred method for selecting this mode of operation. 3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 Ω should be used. 4. Default voltage setting if left unconnected (internal pulled-up). MPC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3 V OVDD; the default voltage setting if left unconnected is 2.5 V. 5. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD; having BVSEL = 1 selects the 2.5-V threshold. 6. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET. (¬HRESET is the inverse of HRESET.) Table 3 provides the recommended operating conditions for the MPC7410. MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 9 Electrical and Thermal Characteristics Table 3. Recommended Operating Conditions 1 Symbol Recommended Value Unit Notes Core supply voltage VDD 1.8 V ± 100 mV V — PLL supply voltage AVDD 1.8 V ± 100 mV V — L2AVDD 1.8 V ± 100 mV V — BVSEL = 0 OVDD 1.8 V ± 100 mV V — BVSEL = HRESET OVDD 2.5 V ± 100 mV V — BVSEL = ¬HRESET or BVSEL = 1 OVDD 3.3 V ± 165 mV V 2, 3 L2VSEL = 0 L2OVDD 1.8 V ± 100 mV V — L2VSEL = HRESET or L2VSEL = 1 L2OVDD 2.5 V ± 100 mV V — Processor bus and JTAG signals Vin GND to OVDD V — L2 bus Vin GND to L2OVDD V — Tj 0 to 105 °C — Characteristic L2 DLL supply voltage Processor bus supply voltage L2 bus supply voltage Input voltage Die-junction temperature Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD and have a recommended OVDD value of 2.5 V ± 100 mV for BVSEL = 1. 3. M xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET. Table 4 provides the package thermal characteristics for the MPC7410. Table 4. Package Thermal Characteristics Value Characteristic Symbol Unit Notes Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board 20 °C/W 1, 2 14 16 °C/W 1, 2 RθJMA 13 15 °C/W 1, 2 RθJB 9 11 °C/W 3 MPC7410 CBGA MPC7410 HCTE RθJMA 18 Junction-to-ambient thermal resistance, 1m/sec airflow, four-layer (2s2p) board RθJMA Junction-to-ambient thermal resistance, 2m/sec airflow, four-layer (2s2p) board Junction-to-board thermal resistance MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 10 Freescale Semiconductor Electrical and Thermal Characteristics Table 4. Package Thermal Characteristics (continued) Value Characteristic Symbol Junction-to-case thermal resistance RθJC MPC7410 CBGA MPC7410 HCTE < 0.1 < 0.1 Unit Notes °C/W 4 Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-6 with the board horizontal. 3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the active portion of the die and the calculated case temperature at the top of the die. The actual value of R JC is less than 0.1 °C/W. Note: Refer to Section 8.8, “Thermal Management Information,” for details on thermal management. Table 5 provides the DC electrical characteristics for the MPC7410. Table 5. DC Electrical Specifications At recommended operating conditions (see Table 3) Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = L2OVDD/OVDD Nominal Bus Voltage1 Symbol Min Max Unit Notes 1.8 VIH 0.65 × (L2)OVDD (L2)OVDD + 0.2 V 2, 3, 8 2.5 VIH 1.7 (L2)OVDD + 0.2 3.3 VIH 2.0 OVDD + 0.3 1.8 VIL –0.3 0.35 × (L2)OVDD V 8 2.5 VIL –0.3 0.2 × (L2)OVDD 3.3 VIL –0.3 0.8 1.8 CVIH 1.5 OVDD + 0.2 V 2, 8 2.5 CVIH 2.0 OVDD + 0.2 3.3 CVIH 2.4 OVDD + 0.3 1.8 CV IL –0.3 0.2 V 8 2.5 CV IL –0.3 0.4 3.3 CV IL –0.3 0.4 1.8 Iin — 20 µA 2.5 Iin — 35 2, 3, 6, 7 3.3 Iin — 70 MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 11 Electrical and Thermal Characteristics Table 5. DC Electrical Specifications (continued) At recommended operating conditions (see Table 3) Characteristic High-Z (off-state) leakage current, Vin = L2OVDD/OVDD Output high voltage, IOH = –5 mA Output low voltage, IOL = 5 mA Capacitance, Vin = 0 V, f = 1 MHz Nominal Bus Voltage1 Symbol Min Max Unit Notes 1.8 ITSI — 20 µA 2.5 ITSI — 35 2, 3, 5, 7 3.3 ITSI — 70 1.8 VOH (L2)OVDD – 0.45 — V 8 2.5 VOH 1.7 — 3.3 VOH 2.4 — 1.8 VOL — 0.45 V 8 2.5 VOL — 0.4 3.3 VOL — 0.4 Cin — 6.0 pF 3, 4, 7 Notes: 1. Nominal voltages; see Table 3 for recommended operating conditions. 2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals. 3. Excludes factory test signals. 4. Capacitance is periodically sampled rather than 100% tested. 5. The leakage is measured for nominal OVDD and L2OVDD, or both OVDD and L2OVDD must vary in the same direction (for example, both OVDD and L2OVDD vary by either +5% or –5%). 6. Measured at max OVDD/L2OVDD. 7. Excludes IEEE 1149.1 boundary scan (JTAG) signals. 8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL/VOH/CVIH/CVIL DC limits of 1.8 V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed, there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a SAMPLE instruction, the DC voltage limits will be controlled by the BVSEL/L2VSEL settings during HRESET. Anytime HRESET is not asserted (that is, just asserting TRST), the voltage mode is not known until either EXTEST or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8 V. MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 12 Freescale Semiconductor Electrical and Thermal Characteristics Table 6 provides the power consumption for the MPC7410. Table 6. Power Consumption for MPC7410 Processor (CPU) Frequency 400 MHz 450 MHz Unit Notes 500 MHz Full-On Mode Typical 4.2 4.7 5.3 W 1, 3 Maximum 9.5 10.7 11.9 W 1, 2 4.8 5.3 W 1 1.5 1.65 W 1 1.45 1.6 W 1 Doze Mode Maximum 4.3 Nap Mode Maximum 1.35 Sleep Mode Maximum 1.3 Sleep Mode—PLL and DLL Disabled Typical 600 600 600 mW 1 Maximum 1.1 1.1 1.1 W 1 Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically