Freescale Semiconductor
Technical Data
Document Number: MPC8343EAEC
Rev. 11, 09/2011
MPC8343EA PowerQUICC II Pro
Integrated Host Processor Hardware
Specifications
The MPC8343EA PowerQUICC II Pro is a next generation
PowerQUICC II integrated host processor. The
MPC8343EA contains a processor core built on Power
Architecture® technology with system logic for networking,
storage, and general-purpose embedded applications. For
functional characteristics of the processor, refer to the
MPC8349EA PowerQUICC II Pro Integrated Host
Processor Family Reference Manual.
To locate published errata or updates for this document, refer
to the MPC8343EA product summary page on our website,
as listed on the back cover of this document, or contact your
local Freescale sales office.
© 2006–2011 Freescale Semiconductor, Inc. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 15
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Three-Speed Ethernet, MII Management . 22
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
System Design Information . . . . . . . . . . . . . . . . . . . 73
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 76
Document Revision History . . . . . . . . . . . . . . . . . . . 78
Overview
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8343E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
See Section 22.1, “Part Numbers Fully Addressed by This Document,” for
silicon revision level determination.
1
Overview
This section provides a high-level overview of the device features. Figure 1 shows the major functional
units within the MPC8343EA.
Security
DUART
Dual I2C
Timers
GPIO
High-Speed
USB 2.0
e300 Core
Interrupt
Controller
10/100/1000
Ethernet
32KB
D-Cache
10/100/1000
Ethernet
32KB
I-Cache
Local Bus
PCI
SEQ
DDR
SDRAM
Controller
DMA
Dual
Role
Figure 1. MPC8343EA Block Diagram
Major features of the device are as follows:
• Embedded PowerPC e300 processor core; operates at up to 400 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
• Double data rate, DDR1/DDR2 SDRAM memory controller
— Programmable timing supporting DDR1 and DDR2 SDRAM
— 32- bit data interface, up to 266 MHz data rate
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Overview
•
•
— Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
— DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports
— Full error checking and correction (ECC) support
— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep-mode support for SDRAM self refresh
— Auto refresh
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual controllers designed to comply with IEEE 802.3™, 802.3u™, 820.3x™, 802.3z™,
802.3ac™ standards
— Ethernet physical interfaces:
– 1000 Mbps IEEE Std. 802.3 RGMII, IEEE Std. 802.3z RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
PCI interface
— Designed to comply with PCI Specification Revision 2.3
— Data bus width:
– 32-bit data PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— PCI host bridge capabilities
— PCI agent mode on PCI interface
— PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration supporting five masters on PCI
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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3
Overview
•
•
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
— Internal configuration registers accessible from PCI
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):
— Public key execution unit (PKEU) :
– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard (DES) execution unit (DEU)
– DES and 3DES algorithms
– Two key (K1, K2) or three key (K1, K2, K3) for 3DES
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rijndael symmetric-key cipher
– Key lengths of 128, 192, and 256 bits
– ECB, CBC, CCM, and counter (CTR) modes
— XOR parity generation accelerator for RAID applications
— ARC four execution unit (AFEU)
– Stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units through an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
Universal serial bus (USB) dual role controller
— USB on-the-go mode with both device and host functionality
— Complies with USB specification Rev. 2.0
— Can operate as a stand-alone USB device
– One upstream facing port
– Six programmable USB endpoints
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Overview
•
•
•
•
— Can operate as a stand-alone USB host controller
– USB root hub with one downstream-facing port
– Enhanced host controller interface (EHCI) compatible
– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects for eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
— Three protocol engines on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA pin in core disable mode.
— Unique vector number for each interrupt source
Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded
hardware
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],
DMA_DACK[0:3], DMA_DDONE[0:3]
— All channels accessible to local core and remote PCI masters
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
5
Electrical Characteristics
•
•
•
•
•
•
2
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Serial peripheral interface (SPI) for master or slave
General-purpose parallel I/O (GPIO)
— 39 parallel I/O pins multiplexed on various chip interfaces
System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan
Integrated PCI bus and SDRAM clock generation
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8343EA. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Parameter
Symbol
Max Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.32
V
—
PLL supply voltage
AVDD
–0.3 to 1.32
V
—
DDR and DDR2 DRAM I/O voltage
GVDD
–0.3 to 2.75
–0.3 to 1.98
V
—
Three-speed Ethernet I/O, MII management voltage
LVDD
–0.3 to 3.63
V
—
PCI, local bus, DUART, system control and power management, I2C,
and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
—
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Electrical Characteristics
Table 1. Absolute Maximum Ratings1 (continued)
Parameter
Symbol
Max Value
Unit
Notes
MVIN
–0.3 to (GVDD + 0.3)
V
2, 5
MVREF
–0.3 to (GVDD + 0.3)
V
2, 5
Three-speed Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
4, 5
Local bus, DUART, CLKIN, system control and
power management, I2C, and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
3, 5
PCI
OVIN
–0.3 to (OVDD + 0.3)
V
6
Storage temperature range
TSTG
–55 to 150
°C
—
Input voltage
DDR DRAM signals
DDR DRAM reference
Notes:
1
Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2 Caution: MV must not exceed GV
IN
DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3 Caution: OV must not exceed OV
IN
DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4 Caution: LV must not exceed LV
IN
DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
5 (M,L,O)V and MV
IN
REF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8343EA. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside these
conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Symbol
Recommended
Value
Unit
Notes
Core supply voltage
VDD
1.2 V ± 60 mV
V
1
PLL supply voltage
AVDD
1.2 V ± 60 mV
V
1
DDR and DDR2 DRAM I/O voltage
GVDD
2.5 V ± 125 mV
1.8 V ± 90 mV
V
—
Three-speed Ethernet I/O supply voltage
LVDD1
3.3 V ± 330 mV
2.5 V ± 125 mV
V
—
Three-speed Ethernet I/O supply voltage
LVDD2
3.3 V ± 330 mV
2.5 V ± 125 mV
V
—
Parameter
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
7
Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Parameter
PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
Symbol
Recommended
Value
Unit
Notes
OVDD
3.3 V ± 330 mV
V
—
Note:
GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or
negative direction.
1
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8343EA.
G/L/OVDD + 20%
G/L/OVDD + 5%
VIH
G/L/OVDD
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tinterface1
Note:
1. tinterface refers to the clock period associated with the bus clock interface.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8343EA for the
3.3-V signals, respectively.
11 ns
(Min)
+7.1 V
7.1 V p-to-p
(Min)
Overvoltage
Waveform
0V
4 ns
(Max)
4 ns
(Max)
62.5 ns
+3.6 V
7.1 V p-to-p
(Min)
Undervoltage
Waveform
–3.5 V
Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Output Impedance
(Ω)
Supply
Voltage
Local bus interface utilities signals
40
OVDD = 3.3 V
PCI signals (not including PCI output clocks)
25
PCI output clocks (including PCI_SYNC_OUT)
40
DDR signal
18
GVDD = 2.5 V
DDR2 signal
18
36 (half-strength mode)
GVDD = 1.8 V
40
LVDD = 2.5/3.3 V
DUART, system control, C, JTAG, USB
40
OVDD = 3.3 V
GPIO signals
40
OVDD = 3.3 V,
LVDD = 2.5/3.3 V
Driver Type
TSEC/10/100 signals
I2
2.2
Power Sequencing
This section details the power sequencing considerations for the MPC8343EA.
2.2.1
Power-Up Sequencing
MPC8343EAdoes not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD,
LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the power
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
9
Power Characteristics
supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of
time that all input and output pins will actively be driven and cause contention and excessive current from
3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the
core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the
power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 4.
Voltage
I/O Voltage (GVDD, LVDD, OVDD)
Core Voltage (VDD, AVDD)
0.7 V
90%
Time
Figure 4. Power Sequencing Example
I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one
another.
3
Power Characteristics
The estimated typical power dissipation for the MPC8343EA device is shown in Table 4.
Table 4. MPC8343EA Power Dissipation1
l
PBGA
Core
Frequency
(MHz)
CSB
Frequency
(MHz)
Typical at TJ = 65
Typical2,3
Maximum4
Unit
266
266
1.3
1.6
1.8
W
133
1.1
1.4
1.6
W
266
1.5
1.9
2.1
W
133
1.4
1.7
1.9
W
200
1.5
1.8
2.0
W
100
1.3
1.7
1.9
W
400
400
1
The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5.
Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark
application.
3 Thermal solutions may need to design to a value higher than typical power based on the end application, T target, and I/O
A
power.
4 Maximum power is based on a voltage of V
DD = 1.2 V, worst case process, a junction temperature of TJ = 105°C, and an
artificial smoke test.
2
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Clock Input Timing
Table 5 shows the estimated typical I/O power dissipation for MPC8343EA.
Table 5. MPC8343EA Typical I/O Power Dissipation
Interface
Parameter
DDR2
GVDD
(1.8 V)
DDR1
GVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V)
Unit
Comments
DDR I/O
65% utilization
2.5 V
Rs = 20 Ω
Rt = 50 Ω
2 pair of clocks
200 MHz, 32 bits
0.31
0.42
—
—
—
W
—
266 MHz, 32 bits
0.35
0.5
—
—
—
W
—
PCI I/O
load = 30 pF
33 MHz, 32 bits
—
—
0.04
—
—
W
—
66 MHz, 32 bits
—
—
0.07
—
—
W
—
Local bus I/O
load = 25 pF
167 MHz, 32 bits
—
—
0.34
—
—
W
—
133 MHz, 32 bits
—
—
0.27
—
—
W
—
83 MHz, 32 bits
—
—
0.17
—
—
W
—
66 MHz, 32 bits
—
—
0.14
—
—
W
—
50 MHz, 32 bits
—
—
0.11
—
—
W
—
MII
—
—
0.01
—
W
GMII or TBI
—
—
0.06
—
W
Multiply by number
of interfaces used.
RGMII or RTBI
—
—
—
0.04
W
12 MHz
—
—
0.01
—
—
W
—
480 MHz
—
—
0.2
—
—
W
—
—
—
0.01
—
—
W
—
TSEC I/O
load = 25 pF
USB
Other I/O
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the device.
4.1
DC Electrical Characteristics
Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8343EA.
Table 6. CLKIN DC Timing Specifications
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
VIH
2.7
OVDD + 0.3
V
Input low voltage
—
VIL
–0.3
0.4
V
0 V ≤ VIN ≤ OVDD
IIN
—
±10
μA
CLKIN input current
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
11
Clock Input Timing
Table 6. CLKIN DC Timing Specifications (continued)
Parameter
Condition
Symbol
Min
Max
Unit
PCI_SYNC_IN input current
0 V ≤ VIN ≤ 0.5 V or
OVDD – 0.5 V ≤ VIN ≤ OVDD
IIN
—
±10
μA
PCI_SYNC_IN input current
0.5 V ≤VIN ≤ OVDD – 0.5 V
IIN
—
±50
μA
4.2
AC Electrical Characteristics
The primary clock source for the MPC8343EA can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
Table 7. CLKIN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
CLKIN/PCI_CLK frequency
fCLKIN
—
—
66
MHz
1, 6
CLKIN/PCI_CLK cycle time
tCLKIN
15
—
—
ns
—
CLKIN/PCI_CLK rise and fall time
tKH, tKL
0.6
1.0
2.3
ns
2
tKHK/tCLKIN
40
—
60
%
3
—
—
—
±150
ps
4, 5
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless
of input frequency.
4.3
TSEC Gigabit Reference Clock Timing
Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
Table 8. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
tG125
—
125
—
MHz
—
EC_GTX_CLK125 cycle time
tG125
—
8
—
ns
—
tG125R/tG125F
—
—
ns
1
EC_GTX_CLK125 rise and fall time
LVDD = 2.5 V
LVDD = 3.3 V
0.75
1.0
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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RESET Initialization
Table 8. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV (continued)
Parameter
Symbol
EC_GTX_CLK125 duty cycle
Min
Typical
45
47
—
Unit
Notes
%
2
ps
2
—
tG125H/tG125
GMII, TBI
1000Base-T for RGMII, RTBI
EC_GTX_CLK125 jitter
Max
55
53
—
—
±150
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD = 3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T
reference clock.
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8343EA.
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8343EA.
Table 9. RESET Pins DC Electrical Characteristics1
Parameter
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
IIN
—
—
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input current
2
Notes:
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
13
RESET Initialization
5.2
RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications of the MPC8343EA.
Table 10. RESET Initialization Timing Specifications
Parameter
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET (input) to activate reset flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock applied to CLKIN when the
MPC8343EA is in PCI host mode
32
—
tCLKIN
2
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the MPC8343EA is in PCI agent mode
32
—
tPCI_SYNC_IN
1
HRESET/SRESET assertion (output)
512
—
tPCI_SYNC_IN
1
HRESET negation to SRESET negation (output)
16
—
tPCI_SYNC_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is
in PCI host mode
4
—
tCLKIN
2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is
in PCI agent mode
4
—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of HRESET
0
—
ns
—
Time for the MPC8343EA to turn off POR configuration signals with respect to the
assertion of HRESET
—
4
ns
3
Time for the MPC8343EA to turn on POR configuration signals with respect to the
negation of HRESET
1
—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 11 lists the PLL and DLL lock times.
Table 11. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs
—
DLL lock times
7680
122,880
csb_clk cycles
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
14
Freescale Semiconductor
DDR and DDR2 SDRAM
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8343EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
The AC electrical specifications are the same for DDR and DRR2 SDRAM.
NOTE
The information in this document is accurate for revision 3.0 silicon and
later. For information on revision 1.1 silicon and earlier versions see the
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware
Specifications. See Section 22.1, “Part Numbers Fully Addressed by This
Document,” for silicon revision level determination.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8343EA when GVDD(typ) = 1.8 V.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.71
1.89
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.125
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.125
V
—
Output leakage current
IOZ
–9.9
9.9
μA
4
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
—
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise
on MVREF cannot exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal
MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
15
DDR and DDR2 SDRAM
Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when
GVDD(typ) = 2.5 V.
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.18
V
—
Output leakage current
IOZ
–9.9
–9.9
μA
4
Output high current (VOUT = 1.95 V)
IOH
–15.2
—
mA
—
Output low current (VOUT = 0.35 V)
IOL
15.2
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
Table 15 provides the DDR capacitance when GVDD(typ) = 2.5 V.
Table 15. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
16
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 16 provides the current draw characteristics for MVREF.
Table 16. Current Draw Characteristics for MVREF
Parameter/Condition
Current draw for MVREF
Symbol
Min
Max
Unit
Note
IMVREF
—
500
μA
1
Note:
1. The voltage regulator for MVREF must supply up to 500 μA current.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF – 0.25
V
—
AC input high voltage
VIH
MVREF + 0.25
—
V
—
Table 18 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.
Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions with GVDD of 2.5 ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF – 0.31
V
—
AC input high voltage
VIH
MVREF + 0.31
—
V
—
Unit
Notes
ps
1, 2
Table 19 provides the input AC timing specifications for the DDR SDRAM interface.
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol
Controller Skew for MDQS—MDQ/MECC/MDM
Min
Max
tCISKEW
400 MHz
–600
600
3
333 MHz
–750
750
—
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
17
DDR and DDR2 SDRAM
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
266 MHz
–750
750
—
200 MHz
–750
750
—
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ± (T/4 – abs (tCISKEW)); where T is the clock period and abs (tCISKEW) is the absolute
value of tCISKEW.
3. This specification applies only to the DDR interface.
Figure 5 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
MCK[n]
MCK[n]
tMCK
MDQS[n]
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 5. DDR Input Timing Diagram
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 shows the DDR and DDR2 output AC timing specifications.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
ADDR/CMD/MODT output setup with respect to MCK
Symbol 1
Min
Max
Unit
Notes
tMCK
7.5
10
ns
2
ns
3
tDDKHAS
400 MHz
1.95
—
333 MHz
2.40
—
266 MHz
3.15
—
200 MHz
4.20
—
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
DDR and DDR2 SDRAM
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol 1
ADDR/CMD/MODT output hold with respect to MCK
tDDKHAX
Min
Max
400 MHz
1.95
—
333 MHz
2.40
—
266 MHz
3.15
—
200 MHz
4.20
—
MCS(n) output setup with respect to MCK
tDDKHCS
400 MHz
1.95
—
333 MHz
2.40
—
266 MHz
3.15
—
200 MHz
4.20
—
MCS(n) output hold with respect to MCK
tDDKHCX
400 MHz
1.95
—
333 MHz
2.40
—
266 MHz
3.15
—
200 MHz
4.20
—
–0.6
0.6
MCK to MDQS Skew
tDDKHMH
MDQ/MECC/MDM output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
400 MHz
700
—
333 MHz
775
—
266 MHz
1100
—
200 MHz
1200
—
MDQ/MECC/MDM output hold with respect to MDQS
tDDKHDX,
tDDKLDX
400 MHz
700
—
333 MHz
900
—
266 MHz
1100
—
200 MHz
1200
—
–0.5 × tMCK – 0.6
–0.5 × tMCK + 0.6
MDQS preamble start
tDDKHMP
Unit
Notes
ns
3
ns
3
ns
3
ns
4
ps
5
ps
5
ns
6
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
19
DDR and DDR2 SDRAM
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
MDQS epilogue end
Symbol 1
Min
Max
Unit
Notes
tDDKHME
–0.6
0.6
ns
6
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from
the rising or falling edge of the reference clock (KH or KL) until the output goes invalid (AX or DX). For example, tDDKHAS
symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are
set up (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes
low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
4. tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the
rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the
DQSS override bits in the TIMING_CFG_2 register and is typically set to the same delay as the clock adjust in the CLK_CNTL
register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value.
See the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual for the timing modifications
enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
Figure 6 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n]
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns
MDQS
tDDKHMH(min) = –0.6 ns
MDQS
Figure 6. Timing Diagram for tDDKHMH
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
20
Freescale Semiconductor
DUART
Figure 7 shows the DDR SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS,tDDKHCS
tDDKHAX,tDDKHCX
ADDR/CMD/MODT
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 7. DDR SDRAM Output Timing Diagram
Figure 8 provides the AC test load for the DDR bus.
Z0 = 50 Ω
Output
GVDD/2
RL = 50 Ω
Figure 8. DDR AC Test Load
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8343EA.
7.1
DUART DC Electrical Characteristics
Table 21 provides the DC electrical characteristics for the DUART interface of the MPC8343EA.
Table 21. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current (0.8 V ≤ VIN ≤ 2 V)
IIN
—
±5
μA
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
21
Ethernet: Three-Speed Ethernet, MII Management
Table 21. DUART DC Electrical Characteristics (continued)
Parameter
Symbol
Min
Max
Unit
High-level output voltage, IOH = –100 μA
VOH
OVDD – 0.2
—
V
Low-level output voltage, IOL = 100 μA
VOL
—
0.2
V
7.2
DUART AC Electrical Specifications
Table 22 provides the AC timing parameters for the DUART interface of the MPC8343EA.
Table 22. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
256
baud
—
Maximum baud rate
> 1,000,000
baud
1
16
—
2
Oversample rate
Notes:
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
8
Ethernet: Three-Speed Ethernet, MII Management
This section provides the AC and DC electrical characteristics for three-speeds (10/100/1000 Mbps) and
MII management.
8.1
Three-Speed Ethernet Controller (TSEC)—MII/RGMII/RTBI
Electrical Characteristics
The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit
media independent interface (RGMII), and reduced ten-bit interface (RTBI) signals except management
data input/output (MDIO) and management data clock (MDC). The MII interface is defined for 3.3 V, and
the RGMII and RTBI interfaces are defined for 2.5 V. The RGMII and RTBI interfaces follow the
Hewlett-Packard Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Device Specification,
Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3,
“Ethernet Management Interface Electrical Characteristics.”
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
8.1.1
TSEC DC Electrical Characteristics
MII, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in
Table 23 and Table 24. The RGMII and RTBI signals in Table 24 are based on a 2.5-V CMOS interface
voltage as defined by JEDEC EIA/JESD8-5.
Table 23. MII DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage 3.3 V
LVDD2
—
2.97
3.63
V
Output high voltage
VOH
IOH = –4.0 mA
LVDD = Min
2.40
LVDD + 0.3
V
Output low voltage
VOL
IOL = 4.0 mA
LVDD = Min
GND
0.50
V
Input high voltage
VIH
—
—
2.0
LVDD + 0.3
V
Input low voltage
VIL
—
—
–0.3
0.90
V
Input high current
IIH
—
40
μA
–600
—
μA
Input low current
VIN1 = LVDD
IIL
VIN
1=
GND
Notes:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
2. MII pins not needed for RGMII or RTBI operation are powered by the OVDD supply.
Table 24. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics
Parameters
Symbol
Conditions
Min
Max
Unit
Supply voltage 2.5 V
LVDD
—
2.37
2.63
V
Output high voltage
VOH
IOH = –1.0 mA
LVDD = Min
2.00
LVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDD = Min
GND – 0.3
0.40
V
Input high voltage
VIH
—
LVDD = Min
1.7
LVDD + 0.3
V
Input low voltage
VIL
—
LVDD = Min
–0.3
0.70
V
Input high current
Input low current
IIH
IIL
VIN
1=
LVDD
—
10
μA
1=
GND
–15
—
μA
VIN
Note:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
23
Ethernet: Three-Speed Ethernet, MII Management
8.2
MII, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for MII, RGMII, and RTBI are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1
MII Transmit AC Timing Specifications
Table 25 provides the MII transmit AC timing specifications.
Table 25. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—
40
—
ns
tMTXH/tMTX
35
—
65
%
tMTKHDX
1
5
15
ns
TX_CLK data clock rise (20%–80%)
tMTXR
1.0
—
4.0
ns
TX_CLK data clock fall (80%–20%)
tMTXF
1.0
—
4.0
ns
Parameter/Condition
TX_CLK duty cycle
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
Note:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing
(MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference
symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of tMTX
represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
Figure 9 shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXH
tMTXF
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 9. MII Transmit AC Timing Diagram
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
8.2.1.2
MII Receive AC Timing Specifications
Table 26 provides the MII receive AC timing specifications.
Table 26. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—
400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—
40
—
ns
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
—
ns
RX_CLK clock rise (20%–80%)
tMRXR
1.0
—
4.0
ns
RX_CLK clock fall time (80%–20%)
tMRXF
1.0
—
4.0
ns
Parameter/Condition
RX_CLK duty cycle
Note:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing
(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to
the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. In general, the clock
reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tMRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
Figure 10 provides the AC test load for TSEC.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 10. TSEC AC Test Load
Figure 11 shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRXF
Valid Data
tMRDVKH
tMRDXKH
Figure 11. MII Receive AC Timing Diagram
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
25
Ethernet: Three-Speed Ethernet, MII Management
8.2.2
RGMII and RTBI AC Timing Specifications
Table 27 presents the RGMII and RTBI AC timing specifications.
Table 27. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Symbol1
Min
Typ
Max
Unit
tSKRGT
–0.5
—
0.5
ns
tSKRGT
1.0
—
2.8
ns
tRGT
7.2
8.0
8.8
ns
tRGTH/tRGT
45
50
55
%
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
—
0.75
ns
Fall time (80%–20%)
tRGTF
—
—
0.75
ns
Parameter/Condition
Data to clock output skew (at transmitter)
2
Data to clock input skew (at receiver)
Clock cycle
duration3
4, 5
Duty cycle for 1000Base-T
Duty cycle for 10BASE-T and 100BASE-TX
3, 5
Notes:
1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For
example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times
follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).
2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added
to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned.
5. Duty cycle reference is LVDD/2.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
26
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Figure 12 shows the RBMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At Transmitter)
tSKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CTL
TXD[8:5]
TXD[3:0] TXD[7:4]
TXD[4]
TXEN
TXD[9]
TXERR
tSKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[3:0] RXD[7:4]
tSKRGT
RX_CTL
RXD[4]
RXDV
RXD[9]
RXERR
tSKRGT
RX_CLK
(At PHY)
Figure 12. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to the MII management interface signals management
data input/output (MDIO) and management data clock (MDC). The electrical characteristics for GMII,
RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller
(TSEC)—MII/RGMII/RTBI Electrical Characteristics.”
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5 or 3.3 V. The DC electrical
characteristics for MDIO and MDC are provided in Table 28 and Table 29.
Table 28. MII Management DC Electrical Characteristics Powered at 2.5 V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (2.5 V)
LVDD
—
2.37
2.63
V
Output high voltage
VOH
IOH = –1.0 mA
LVDD = Min
2.00
LVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDD = Min
GND – 0.3
0.40
V
Input high voltage
VIH
—
LVDD = Min
1.7
—
V
Input low voltage
VIL
—
LVDD = Min
–0.3
0.70
V
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
27
Ethernet: Three-Speed Ethernet, MII Management
Table 28. MII Management DC Electrical Characteristics Powered at 2.5 V (continued)
Parameter
Symbol
Conditions
Min
Max
Unit
Input high current
IIH
VIN1 = LVDD
—
10
μA
Input low current
IIL
VIN = LVDD
–15
—
μA
Note:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
Table 29. MII Management DC Electrical Characteristics Powered at 3.3 V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (3.3 V)
LVDD
—
2.97
3.63
V
Output high voltage
VOH
IOH = –1.0 mA
LVDD = Min
2.10
LVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDD = Min
GND
0.50
V
Input high voltage
VIH
—
2.00
—
V
Input low voltage
VIL
—
—
0.80
V
—
40
μA
–600
—
μA
Input high current
IIH
LVDD = Max
VIN1
Input low current
IIL
LVDD = Max
VIN = 0.5 V
= 2.1 V
Note:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
8.3.2
MII Management AC Electrical Specifications
Table 30 provides the MII management AC timing specifications.
Table 30. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V ± 10% or 2.5 V ± 5%.
Symbol1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—
2.5
—
MHz
2
MDC period
tMDC
—
400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
—
ns
—
MDC to MDIO delay
tMDKHDX
10
—
70
ns
3
MDIO to MDC setup time
tMDDVKH
5
—
—
ns
—
MDIO to MDC hold time
tMDDXKH
0
—
—
ns
—
tMDCR
—
—
10
ns
—
Parameter/Condition
MDC rise time
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Table 30. MII Management AC Timing Specifications (continued)
At recommended operating conditions with LVDD is 3.3 V ± 10% or 2.5 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
tMDHF
—
—
10
ns
—
MDC fall time
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data
timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,
tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)
relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of
333 MHz, the delay is 58 ns).
Figure 13 shows the MII management AC timing diagram.
tMDCR
tMDC
MDC
tMDCF
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 13. MII Management Interface Timing Diagram
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
29
USB
9
USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8343EA.
9.1
USB DC Electrical Characteristics
Table 31 provides the DC electrical characteristics for the USB interface.
Table 31. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—
±5
μA
High-level output voltage, IOH = –100 μA
VOH
OVDD – 0.2
—
V
Low-level output voltage, IOL = 100 μA
VOL
—
0.2
V
9.2
USB AC Electrical Specifications
Table 32 describes the general timing parameters of the USB interface of the MPC8343EA.
Table 32. USB General Timing Parameters (ULPI Mode Only)
Symbol1
Min
Max
Unit
Notes
tUSCK
15
—
ns
2–5
Input setup to USB clock—all inputs
tUSIVKH
4
—
ns
2–5
Input hold to USB clock—all inputs
tUSIXKH
1
—
ns
2–5
USB clock to output valid—all outputs
tUSKHOV
—
7
ns
2–5
Output hold from USB clock—all outputs
tUSKHOX
2
—
ns
2–5
Parameter
USB clock cycle time
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for
the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to USB clock.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
30
Freescale Semiconductor
Local Bus
Figure 14 and Figure 15 provide the AC test load and signals for the USB, respectively.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 14. USB AC Test Load
USB0_CLK/USB1_CLK/DR_CLK
tUSIXKH
tUSIVKH
Input Signals
tUSKHOV
tUSKHOX
Output Signals:
Figure 15. USB Signals
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8343EA.
10.1
Local Bus DC Electrical Characteristics
Table 33 provides the DC electrical characteristics for the local bus interface.
Table 33. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—
±5
μA
High-level output voltage, IOH = –100 μA
VOH
OVDD – 0.2
—
V
Low-level output voltage, IOL = 100 μA
VOL
—
0.2
V
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
31
Local Bus
10.2
Local Bus AC Electrical Specification
Table 34 and Table 35 describe the general timing parameters of the local bus interface of the
MPC8343EA.
Table 34. Local Bus General Timing Parameters—DLL On
Symbol1
Min
Max
Unit
Notes
tLBK
7.5
—
ns
2
Input setup to local bus clock (except LUPWAIT)
tLBIVKH1
1.5
—
ns
3, 4
LUPWAIT input setup to local bus clock
tLBIVKH2
2.2
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
tLBIXKH1
1.0
—
ns
3, 4
LUPWAIT Input hold from local bus clock
tLBIXKH2
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3
—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Local bus clock to LALE rise
tLBKHLR
—
4.5
ns
—
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—
4.5
ns
—
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—
4.5
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—
4.5
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKHOX1
1
—
ns
3
Output hold from local bus clock for LAD/LDP
tLBKHOX2
1
—
ns
3
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—
3.8
ns
8
Parameter
Local bus cycle time
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)
for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one
(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output
(O) going invalid (X) or output hold time.
2. All timings are in reference to the rising edge of LSYNC_IN.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than
the load on the LAD output pins.
6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the
load on the LAD output pins.
7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD
output pins.
8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
32
Freescale Semiconductor
Local Bus
Table 35. Local Bus General Timing Parameters—DLL Bypass9
Symbol1
Min
Max
Unit
Notes
tLBK
15
—
ns
2
Input setup to local bus clock
tLBIVKH
7
—
ns
3, 4
Input hold from local bus clock
tLBIXKH
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3
—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Local bus clock to output valid
tLBKLOV
—
3
ns
3
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—
4
ns
8
Parameter
Local bus cycle time
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)
for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one
(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output
(O) going invalid (X) or output hold time.
2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge
of LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the
load on the LAD output pins.
6. tLBOTOT2 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than
the load on the LAD output pins.the
7. tLBOTOT3 should be used when RCWH[LALE] is not set and when the load on the LALE output pin equals to the load on the
LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.
Figure 16 provides the AC test load for the local bus.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 16. Local Bus C Test Load
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
33
Local Bus
Figure 17 through Figure 22 show the local bus signals.
LSYNC_IN
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE
tLBKHOV
tLBKHOV
tLBKHOZ
tLBKHOX
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV
tLBKHOZ
tLBKHOX
Output (Address) Signal:
LAD[0:31]
tLBOTOT
tLBKHLR
LALE
Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
LCLK[n]
Input Signals:
LAD[0:31]/LDP[0:3]
Input Signal:
LGTA
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE
Output Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH
tLBIVKH
tLBIXKH
tLBIVKH
tLBKLOV
tLBKLOV
tLBKLOV
tLBKHOZ
tLBOTOT
LALE
Figure 18. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
34
Freescale Semiconductor
Local Bus
LSYNC_IN
T1
T3
tLBKHOV1
tLBKHOZ1
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBIVKH2
tLBIXKH2
UPM Mode Input Signal:
LUPWAIT
tLBIVKH1
tLBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV1
tLBKHOZ1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
LCLK
T1
T3
tLBKLOV
tLBKHOZ
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBKLOV
tLBIXKH
tLBKHOZ
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
35
Local Bus
LCLK
T1
T2
T3
T4
tLBKLOV
tLBKHOZ
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBKLOV
tLBIXKH
tLBKHOZ
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
36
Freescale Semiconductor
JTAG
LSYNC_IN
T1
T2
T3
T4
tLBKHOZ1
tLBKHOV1
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH2
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBIXKH1
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ1
tLBKHOV1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)
11 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface
of the MPC8343EA.
11.1
JTAG DC Electrical Characteristics
Table 36 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the
MPC8343EA.
Table 36. JTAG Interface DC Electrical Characteristics
Parameter
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
OVDD – 0.3
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
—
—
±5
μA
VOH
IOH = –8.0 mA
2.4
—
V
Output high voltage
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
37
JTAG
Table 36. JTAG Interface DC Electrical Characteristics (continued)
Parameter
Symbol
Condition
Min
Max
Unit
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
11.2
JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the
MPC8343EA. Table 37 provides the JTAG AC timing specifications as defined in Figure 24 through
Figure 27.
Table 37. JTAG AC Timing Specifications (Independent of CLKIN)1
At recommended operating conditions (see Table 2).
Symbol2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
—
JTAG external clock cycle time
t JTG
30
—
ns
—
tJTKHKL
15
—
ns
—
tJTGR, tJTGF
0
2
ns
—
tTRST
25
—
ns
3
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
4
—
—
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
2
11
11
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
2
—
—
Parameter
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
ns
Input setup times:
Input hold times:
4
ns
4
ns
Valid times:
5
ns
Output hold times:
5
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
38
Freescale Semiconductor
JTAG
Table 37. JTAG AC Timing Specifications (Independent of CLKIN)1 (continued)
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
2
19
9
Unit
Notes
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see Figure 14).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going
to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. In general, the clock reference symbol is
based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
Figure 23 provides the AC test load for TDO and the boundary-scan outputs of the MPC8343EA.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 23. AC Test Load for the JTAG Interface
Figure 24 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTGR
tJTKHKL
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 24. JTAG Clock Input Timing Diagram
Figure 25 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 25. TRST Timing Diagram
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
39
JTAG
Figure 26 provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 26. Boundary-Scan Timing Diagram
Figure 27 provides the test access port timing diagram.
JTAG
External Clock
VM
VM
tJTIVKH
tJTIXKH
Input
Data Valid
TDI, TMS
tJTKLOV
tJTKLOX
TDO
Output Data Valid
tJTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 27. Test Access Port Timing Diagram
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
40
Freescale Semiconductor
I2 C
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8343EA.
12.1
I2C DC Electrical Characteristics
Table 38 provides the DC electrical characteristics for the I2C interface of the MPC8343EA.
Table 38. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7 × OVDD
OVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3 × OVDD
V
—
Low level output voltage
VOL
0
0.2 × OVDD
V
1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1 × CB
250
ns
2
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL
0
50
ns
3
Input current each I/O pin (input voltage is between
0.1 × OVDD and 0.9 × OVDD(max)
II
–10
10
μA
4
Capacitance for each I/O pin
CI
—
10
pF
—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8349EA Integrated Host Processor Family Reference Manual, for information on the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
12.2
I2C AC Electrical Specifications
Table 39 provides the AC timing parameters for the I2C interface of the MPC8343EA. Note that all values
refer to VIH(min) and VIL(max) levels (see Table 38).
Table 39. I2C AC Electrical Specifications
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
—
μs
High period of the SCL clock
tI2CH
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL
0.6
—
μs
Data setup time
tI2DVKH
100
—
ns
Data hold time:CBUS compatible masters
I2C bus devices
tI2DXKL
—
02
—
0.93
μs
Parameter
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
41
I2 C
Table 39. I2C AC Electrical Specifications (continued)
Symbol1
Min
Max
Unit
tI2CF
__
300
ns
Setup time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1 × OVDD
—
V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2 × OVDD
—
V
Parameter
Fall time of both SDA and SCL signals5
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with
respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H)
state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S)
goes invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
3. The maximum tI2DVKH must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
5.)The device does not follow the “I2C-BUS Specifications” version 2.1 regarding the tI2CF AC parameter.
Figure 28 provides the AC test load for the I2C.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 28. I2C AC Test Load
Figure 29 shows the AC timing diagram for the I2C bus.
SDA
tI2CF
tI2DVKH
tI2CL
tI2KHKL
tI2SXKL
tI2CF
tI2CR
SCL
tI2SXKL
S
tI2CH
tI2DXKL
tI2SVKH
Sr
tI2PVKH
P
S
2
Figure 29. I C Bus AC Timing Diagram
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
PCI
13 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8343EA.
13.1
PCI DC Electrical Characteristics
Table 40 provides the DC electrical characteristics for the PCI interface of the MPC8343EA.
Table 40. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
2
OVDD + 0.3
V
Low-level input voltage
VIL
VOUT ≤ VOL (max)
–0.3
0.8
V
Input current
IIN
VIN1= 0 V or VIN = OVDD
—
±5
μA
High-level output voltage
VOH
OVDD = min,
IOH = –100 μA
OVDD – 0.2
—
V
Low-level output voltage
VOL
OVDD = min,
IOL = 100 μA
—
0.2
V
Note:
1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1.
13.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the MPC8343EA. Note that the
PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is
configured as a host or agent device. Table 41 provides the PCI AC timing specifications at 66 MHz.
Table 41. PCI AC Timing Specifications at 66 MHz1
Symbol2
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
6.0
ns
3
Output hold from clock
tPCKHOX
1
—
ns
3
Clock to output high impedance
tPCKHOZ
—
14
ns
3, 4
Input setup to clock
tPCIVKH
3.0
—
ns
3, 5
Parameter
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
43
PCI
Table 41. PCI AC Timing Specifications at 66 MHz1 (continued)
Parameter
Input hold from clock
Symbol2
Min
Max
Unit
Notes
tPCIXKH
0
—
ns
3, 5
Notes:
1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
description of M66EN.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
Table 42 provides the PCI AC timing specifications at 33 MHz.
Table 42. PCI AC Timing Specifications at 33 MHz
Symbol1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
11
ns
2
Output hold from clock
tPCKHOX
2
—
ns
2
Clock to output high impedance
tPCKHOZ
—
14
ns
2, 3
Input setup to clock
tPCIVKH
3.0
—
ns
2, 4
Input hold from clock
tPCIXKH
0
—
ns
2, 4
Parameter
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
Figure 30 provides the AC test load for PCI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 30. PCI AC Test Load
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
44
Freescale Semiconductor
Timers
Figure 31 shows the PCI input AC timing diagram.
CLK
tPCIVKH
tPCIXKH
Input
Figure 31. PCI Input AC Timing Diagram
Figure 32 shows the PCI output AC timing diagram.
CLK
tPCKHOV
tPCKHOX
Output Delay
tPCKHOZ
High-Impedance
Output
Figure 32. PCI Output AC Timing Diagram
14 Timers
This section describes the DC and AC electrical specifications for the timers.
14.1
Timer DC Electrical Characteristics
Table 43 provides the DC electrical characteristics for the MPC8343EA timer pins, including TIN, TOUT,
TGATE, and RTC_CLK.
Table 43. Timer DC Electrical Characteristics
Parameter
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
—
—
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
45
GPIO
14.2
Timer AC Timing Specifications
Table 44 provides the timer input and output AC timing specifications.
Table 44. Timers Input AC Timing Specifications1
Parameter
Symbol2
Min
Unit
tTIWID
20
ns
Timers inputs—minimum pulse width
Notes:
1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.
Timings are measured at the pin.
2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external
synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
15 GPIO
This section describes the DC and AC electrical specifications for the GPIO.
15.1
GPIO DC Electrical Characteristics
Table 45 provides the DC electrical characteristics for the MPC8343EA GPIO.
Table 45. GPIO DC Electrical Characteristics
PArameter
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
—
—
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Symbol2
Min
Unit
tPIWID
20
ns
15.2
GPIO AC Timing Specifications
Table 46 provides the GPIO input and output AC timing specifications.
Table 46. GPIO Input AC Timing Specifications1
Parameter
GPIO inputs—minimum pulse width
Notes:
1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.
Timings are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external
synchronous logic. GPIO inputs must be valid for at least tPIWID ns to ensure proper operation.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
46
Freescale Semiconductor
IPIC
16 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins.
16.1
IPIC DC Electrical Characteristics
Table 47 provides the DC electrical characteristics for the external interrupt pins.
Table 47. IPIC DC Electrical Characteristics1
Parameter
Symbol
Condition
Min
Max
Unit
Notes
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
—
Input low voltage
VIL
—
–0.3
0.8
V
—
Input current
IIN
—
—
±5
μA
—
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
2
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
2
Symbol2
Min
Unit
tPICWID
20
ns
Notes:
1. This table applies for pins IRQ[0:7], IRQ_OUT, and MCP_OUT.
2. IRQ_OUT and MCP_OUT are open-drain pins; thus VOH is not relevant for those pins.
16.2
IPIC AC Timing Specifications
Table 48 provides the IPIC input and output AC timing specifications.
Table 48. IPIC Input AC Timing Specifications1
Parameter
IPIC inputs—minimum pulse width
Notes:
1. Input specifications are measured at the 50 percent level of the IPIC input signals. Timings are measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external
synchronous logic. IPIC inputs must be valid for at least tPICWID ns to ensure proper operation in edge triggered mode.
17 SPI
This section describes the SPI DC and AC electrical specifications.
17.1
SPI DC Electrical Characteristics
Table 49 provides the SPI DC electrical characteristics.
Table 49. SPI DC Electrical Characteristics
Parameter
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
47
SPI
Table 49. SPI DC Electrical Characteristics (continued)
Parameter
Symbol
Condition
Min
Max
Unit
IIN
—
—
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input current
17.2
SPI AC Timing Specifications
Table 50 provides the SPI input and output AC timing specifications.
Table 50. SPI AC Timing Specifications1
Symbol2
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
tNIKHOV
—
6
ns
SPI outputs hold—Master mode (internal clock) delay
tNIKHOX
0.5
—
ns
SPI outputs valid—Slave mode (external clock) delay
tNEKHOV
—
8
ns
SPI outputs hold—Slave mode (external clock) delay
tNEKHOX
2
—
ns
SPI inputs—Master mode (internal clock input setup time
tNIIVKH
4
—
ns
SPI inputs—Master mode (internal clock input hold time
tNIIXKH
0
—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4
—
ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2
—
ns
Parameter
Notes:
1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing
(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Figure 33 provides the AC test load for the SPI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 33. SPI AC Test Load
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Package and Pin Listings
Figure 34 and Figure 35 represent the AC timings from Table 50. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 34 shows the SPI timings in slave mode (external clock).
SPICLK (Input)
Input Signals:
SPIMOSI
(See Note)
tNEIVKH
tNEIXKH
tNEKHOX
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 34. SPI AC Timing in Slave Mode (External Clock) Diagram
Figure 35 shows the SPI timings in master mode (internal clock).
SPICLK (Output)
Input Signals:
SPIMISO
(See Note)
tNIIVKH
Output Signals:
SPIMOSI
(See Note)
tNIIXKH
tNIKHOX
Note: The clock edge is selectable on SPI.
Figure 35. SPI AC Timing in Master Mode (Internal Clock) Diagram
18 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8343EA is available
in a plastic ball grid array (PBGA). See Section 18.1, “Package Parameters for the MPC8343EA PBGA,”
and Section 18.2, “Mechanical Dimensions for the MPC8343EA PBGA.”
18.1
Package Parameters for the MPC8343EA PBGA
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm,
620 plastic ball grid array (PBGA).
Package outline
29 mm × 29 mm
Interconnects
620
Pitch
1.00 mm
Module height (maximum)
2.46 mm
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
49
Package and Pin Listings
Module height (typical)
Module height (minimum)
Solder balls
Ball diameter (typical)
2.23 mm
2.00 mm
62 Sn/36 Pb/2 Ag (ZQ package)
96.5 Sn/3.5Ag (VR package)
0.60 mm
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Package and Pin Listings
18.2
Mechanical Dimensions for the MPC8343EA PBGA
Figure 36 shows the mechanical dimensions and bottom surface nomenclature for the MPC8343EA,
620-PBGA package.
Notes:
1. All dimensions are in millimeters.
2. Dimensioning and tolerancing per ASME Y14. 5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
Figure 36. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8343EA PBGA
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
51
Package and Pin Listings
18.3
Pinout Listings
Table 51 provides the pin-out listing for the MPC8343EA, 620-PBGA package.
Table 51. MPC8343EA (PBGA) Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
PCI
PCI1_INTA/IRQ_OUT
D20
O
OVDD
2
PCI1_RESET_OUT
B21
O
OVDD
—
PCI1_AD[31:0]
E19, D17, A16, A18, B17, B16, D16,
B18, E17, E16, A15, C16, D15, D14,
C14, A12, D12, B11, C11, E12, A10,
C10, A9, E11, E10, B9, B8, D9, A8, C9,
D8, C8
I/O
OVDD
—
PCI1_C/BE[3:0]
A17, A14, A11, B10
I/O
OVDD
—
PCI1_PAR
D13
I/O
OVDD
—
PCI1_FRAME
B14
I/O
OVDD
5
PCI1_TRDY
A13
I/O
OVDD
5
PCI1_IRDY
E13
I/O
OVDD
5
PCI1_STOP
C13
I/O
OVDD
5
PCI1_DEVSEL
B13
I/O
OVDD
5
PCI1_IDSEL
C17
I
OVDD
—
PCI1_SERR
C12
I/O
OVDD
5
PCI1_PERR
B12
I/O
OVDD
5
PCI1_REQ[0]
A21
I/O
OVDD
—
PCI1_REQ[1]/CPCI1_HS_ES
C19
I
OVDD
—
C18, A19, E20
I
OVDD
—
PCI1_GNT0
B20
I/O
OVDD
—
PCI1_GNT1/CPCI1_HS_LED
C20
O
OVDD
—
PCI1_GNT2/CPCI1_HS_ENUM
B19
O
OVDD
—
A20, E18
O
OVDD
—
L26
I
OVDD
—
I/O
GVDD
—
PCI1_REQ[2:4]
PCI1_GNT[3:4]
M66EN
DDR SDRAM Memory Interface
MDQ[0:31]
AC25, AD27, AD25, AH27, AE28, AD26,
AD24, AF27, AF25, AF28, AH24, AG26,
AE25, AG25, AH26, AH25, AG22, AH22,
AE21, AD19, AE22, AF23, AE19, AG20,
AG19, AD17, AE16, AF16, AF18, AG18,
AH17, AH16
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
52
Freescale Semiconductor
Package and Pin Listings
Table 51. MPC8343EA (PBGA) Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
AG13, AE14, AH12, AH10, AE15
I/O
GVDD
—
AH14
I/O
GVDD
—
MECC[6:7]
AE13, AH11
I/O
GVDD
—
MDM[0:3]
AG28, AG24, AF20, AG17
O
GVDD
—
AG12
O
GVDD
—
AE27, AE26, AE20, AH18
I/O
GVDD
—
MDQS[8]
AH13
I/O
GVDD
—
MBA[0:1]
AF10, AF11
O
GVDD
—
MA[0:14]
AF13, AF15, AG16, AD16, AF17, AH20,
AH19, AH21, AD18, AG21, AD13, AF21,
AF22, AE1, AA5
O
GVDD
—
MWE
AD10
O
GVDD
—
MRAS
AF7
O
GVDD
—
MCAS
AG6
O
GVDD
—
AE7, AH7, AH4, AF2
O
GVDD
—
AG23, AH23
O
GVDD
3
MCK[0:3]
AH15, AE24, AE2, AF14
O
GVDD
—
MCK[0:3]
AG15, AD23, AE3, AG14
O
GVDD
—
AG5, AD4, AH6, AF4
O
GVDD
—
MBA[2]
AD22
O
GVDD
—
MDIC0
AG11
I/O
—
9
MDIC1
AF12
I/O
—
9
T4, T5, T1, R2, R3, T2, R1, R4, P1, P2,
P3, P4, N1, N4, N2, N3, M1, M2, M3, N5,
M4, L1, L2, L3, K1, M5, K2, K3, J1, J2,
L5, J3
I/O
OVDD
—
LDP[0]/CKSTOP_OUT
H1
I/O
OVDD
—
LDP[1]/CKSTOP_IN
K5
I/O
OVDD
—
LDP[2]/LCS[4]
H2
I/O
OVDD
—
LDP[3]/LCS[5]
G1
I/O
OVDD
—
LA[27:31]
J4, H3, G2, F1, G3
O
OVDD
—
LCS[0:3]
J5, H4, F2, E1
O
OVDD
—
LWE[0:3]/LSDDQM[0:3]/LBS[0:3]
F3, G4, D1, E2
O
OVDD
—
Signal
MECC[0:4]/MSRCID[0:4]
MECC[5]/MDVAL
MDM[8]
MDQS[0:3]
MCS[0:3]
MCKE[0:1]
MODT[0:3]
Local Bus Controller Interface
LAD[0:31]
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
53
Package and Pin Listings
Table 51. MPC8343EA (PBGA) Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
LBCTL
H5
O
OVDD
—
LALE
E3
O
OVDD
—
LGPL0/LSDA10/cfg_reset_source0
F4
I/O
OVDD
—
LGPL1/LSDWE/cfg_reset_source1
D2
I/O
OVDD
—
LGPL2/LSDRAS/LOE
C1
O
OVDD
—
LGPL3/LSDCAS/cfg_reset_source2
C2
I/O
OVDD
—
LGPL4/LGTA/LUPWAIT/LPBSE
C3
I/O
OVDD
12
LGPL5/cfg_clkin_div
B3
I/O
OVDD
—
LCKE
E4
O
OVDD
—
D4, A3, C4
O
OVDD
—
LSYNC_OUT
U3
O
OVDD
—
LSYNC_IN
Y2
I
OVDD
—
Signal
LCLK[0:2]
General Purpose I/O Timers
GPIO1[0]/DMA_DREQ0/GTM1_TIN1/
GTM2_TIN2
D27
I/O
OVDD
—
GPIO1[1]/DMA_DACK0/GTM1_TGATE1/
GTM2_TGATE2
E26
I/O
OVDD
—
GPIO1[2]/DMA_DDONE0/
GTM1_TOUT1
D28
I/O
OVDD
—
GPIO1[3]/DMA_DREQ1/GTM1_TIN2/
GTM2_TIN1
G25
I/O
OVDD
—
GPIO1[4]/DMA_DACK1/
GTM1_TGATE2/GTM2_TGATE1
J24
I/O
OVDD
—
GPIO1[5]/DMA_DDONE1/
GTM1_TOUT2/GTM2_TOUT1
F26
I/O
OVDD
—
GPIO1[6]/DMA_DREQ2/GTM1_TIN3/
GTM2_TIN4
E27
I/O
OVDD
—
GPIO1[7]/DMA_DACK2/GTM1_TGATE3/
GTM2_TGATE4
E28
I/O
OVDD
—
GPIO1[8]/DMA_DDONE2/
GTM1_TOUT3
H25
I/O
OVDD
—
GPIO1[9]/DMA_DREQ3/GTM1_TIN4/
GTM2_TIN3
F27
I/O
OVDD
—
GPIO1[10]/DMA_DACK3/
GTM1_TGATE4/GTM2_TGATE3
K24
I/O
OVDD
—
GPIO1[11]/DMA_DDONE3/
GTM1_TOUT4/GTM2_TOUT3
G26
I/O
OVDD
—
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
54
Freescale Semiconductor
Package and Pin Listings
Table 51. MPC8343EA (PBGA) Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
USB
DR_D0_ENABLEN
C28
I/O
OVDD
—
DR_D1_SER_TXD
F25
I/O
OVDD
—
DR_D2_VMO_SE0
B28
I/O
OVDD
—
DR_D3_SPEED
C27
I/O
OVDD
—
DR_D4_DP
D26
I/O
OVDD
—
DR_D5_DM
E25
I/O
OVDD
—
DR_D6_SER_RCV
C26
I/O
OVDD
—
DR_D7_DRVVBUS
D25
I/O
OVDD
—
DR_SESS_VLD_NXT
B26
I
OVDD
—
DR_XCVR_SEL_DPPULLUP
E24
I/O
OVDD
—
DR_STP_SUSPEND
A27
O
OVDD
—
DR_RX_ERROR_PWRFAULT
C25
I
OVDD
—
DR_TX_VALID_PCTL0
A26
O
OVDD
—
DR_TX_VALIDH_PCTL1
B25
O
OVDD
—
DR_CLK
A25
I
OVDD
—
Programmable Interrupt Controller
MCP_OUT
E8
O
OVDD
2
IRQ0/MCP_IN/GPIO2[12]
J28
I/O
OVDD
—
K25, J25, H26, L24, G27
I/O
OVDD
—
IRQ[6]/GPIO2[18]/CKSTOP_OUT
G28
I/O
OVDD
—
IRQ[7]/GPIO2[19]/CKSTOP_IN
J26
I/O
OVDD
—
IRQ[1:5]/GPIO2[13:17]
Ethernet Management Interface
EC_MDC
Y24
O
LVDD1
—
EC_MDIO
Y25
I/O
LVDD1
11
I
LVDD1
—
Gigabit Reference Clock
EC_GTX_CLK125
Y26
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_COL/GPIO2[20]
M26
I/O
OVDD
—
TSEC1_CRS/GPIO2[21]
U25
I/O
LVDD1
—
TSEC1_GTX_CLK
V24
O
LVDD1
3
TSEC1_RX_CLK
U26
I
LVDD1
—
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
55
Package and Pin Listings
Table 51. MPC8343EA (PBGA) Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
TSEC1_RX_DV
U24
I
LVDD1
—
TSEC1_RX_ER/GPIO2[26]
L28
I/O
OVDD
—
TSEC1_RXD[3:0]
W26, W24, Y28, Y27
I
LVDD1
—
TSEC1_TX_CLK
N25
I
OVDD
—
TSEC1_TXD[3:0]
V28, V27, V26, W28
O
LVDD1
10
TSEC1_TX_EN
W27
O
LVDD1
—
TSEC1_TX_ER/GPIO2[31]
N24
I/O
OVDD
—
Signal
Three-Speed Ethernet Controller (Gigabit Ethernet 2)
TSEC2_COL/GPIO1[21]
P28
I/O
OVDD
—
TSEC2_CRS/GPIO1[22]
AC28
I/O
LVDD2
—
TSEC2_GTX_CLK
AC27
O
LVDD2
—
TSEC2_RX_CLK
AB25
I
LVDD2
—
TSEC2_RX_DV/GPIO1[23]
AC26
I/O
LVDD2
—
AA25, AA26, AA27, AA28
I/O
LVDD2
—
R25
I/O
OVDD
—
AB26, AB27, AA24, AB28
I/O
LVDD2
—
TSEC2_TX_ER/GPIO1[24]
R27
I/O
OVDD
—
TSEC2_TX_EN/GPIO1[12]
AD28
I/O
LVDD2
3
TSEC2_TX_CLK/GPIO1[30]
R26
I/O
OVDD
—
TSEC2_RXD[3:0]/GPIO1[13:16]
TSEC2_RX_ER/GPIO1[25]
TSEC2_TXD[3:0]/GPIO1[17:20]
DUART
UART_SOUT[1:2]/MSRCID[0:1]/
LSRCID[0:1]
B4, A4
O
OVDD
—
UART_SIN[1:2]/MSRCID[2:3]/
LSRCID[2:3]
D5, C5
I/O
OVDD
—
UART_CTS[1]/MSRCID4/LSRCID4
B5
I/O
OVDD
—
UART_CTS[2]/MDVAL/LDVAL
A5
I/O
OVDD
—
D6, C6
O
OVDD
—
UART_RTS[1:2]
I2C
interface
IIC1_SDA
E5
I/O
OVDD
2
IIC1_SCL
A6
I/O
OVDD
2
IIC2_SDA
B6
I/O
OVDD
2
IIC2_SCL
E7
I/O
OVDD
2
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
56
Freescale Semiconductor
Package and Pin Listings
Table 51. MPC8343EA (PBGA) Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
SPI
SPIMOSI/LCS[6]
D7
I/O
OVDD
—
SPIMISO/LCS[7]
C7
I/O
OVDD
—
SPICLK
B7
I/O
OVDD
—
SPISEL
A7
I
OVDD
—
Y1, W3, W2
O
OVDD
—
PCI_CLK_OUT[3]/LCS[6]
W1
O
OVDD
—
PCI_CLK_OUT[4]/LCS[7]
V3
O
OVDD
—
PCI_SYNC_IN/PCI_CLOCK
U4
I
OVDD
—
PCI_SYNC_OUT
U5
O
OVDD
3
RTC/PIT_CLOCK
E9
I
OVDD
—
CLKIN
W5
I
OVDD
—
Clocks
PCI_CLK_OUT[0:2]
JTAG
TCK
H27
I
OVDD
—
TDI
H28
I
OVDD
4
TDO
M24
O
OVDD
3
TMS
J27
I
OVDD
4
TRST
K26
I
OVDD
4
Test
TEST
F28
I
OVDD
6
TEST_SEL
T3
I
OVDD
7
O
OVDD
—
PMC
K27
QUIESCE
System Control
PORESET
K28
I
OVDD
—
HRESET
M25
I/O
OVDD
1
SRESET
L27
I/O
OVDD
2
I
—
8
Thermal Management
THERM0
B15
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
57
Package and Pin Listings
Table 51. MPC8343EA (PBGA) Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
Power and Ground Signals
AVDD1
C15
Power for e300
PLL (1.2 V)
AVDD1
—
AVDD2
U1
Power for
system PLL
(1.2 V)
AVDD2
—
AVDD3
AF9
Power for DDR
DLL (1.2 V)
—
—
AVDD4
U2
Power for LBIU
DLL (1.2 V)
AVDD4
—
GND
A2, B1, B2, D10, D18, E6, E14, E22, F9,
F12, F15, F18, F21, F24, G5, H6, J23,
L4, L6, L12, L13, L14, L15, L16, L17,
M11, M12, M13, M14, M15, M16, M17,
M18, M23, N11, N12, N13, N14, N15,
N16, N17, N18, P6, P11, P12, P13, P14,
P15, P16, P17, P18, P24, R5, R23, R11,
R12, R13, R14, R15, R16, R17, R18,
T11, T12, T13, T14, T15, T16, T17, T18,
U6, U11, U12, U13, U14, U15, U16,
U17, U18, V12, V13, V14, V15, V16,
V17, V23, V25, W4, Y6, AA23, AB24,
AC5, AC8, AC11, AC14, AC17, AC20,
AD9, AD15, AD21, AE12, AE18, AF3,
AF26
—
—
—
GVDD
U9, V9, W10, W19, Y11, Y12, Y14, Y15,
Y17, Y18, AA6, AB5, AC9, AC12, AC15,
AC18, AC21, AC24, AD6, AD8, AD14,
AD20, AE5, AE11, AE17, AG2, AG27
Power for DDR
DRAM I/O
voltage
(2.5 V)
GVDD
—
LVDD1
U20, W25
Power for three
speed Ethernet
#1 and for
Ethernet
management
interface I/O
(2.5V, 3.3V)
LVDD1
—
LVDD2
V20, Y23
Power for three
speed Ethernet
#2 I/O (2.5 V,
3.3 V)
LVDD2
—
J11, J12, J15, K10, K11, K12, K13, K14,
K15, K16, K17, K18, K19, L10, L11, L18,
L19, M10, M19, N10, N19, P9, P10, P19,
R10, R19, R20, T10, T19, U10, U19,
V10, V11, V18, V19, W11, W12, W13,
W14, W15, W16, W17, W18
Power for core
(1.2 V)
VDD
—
VDD
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
58
Freescale Semiconductor
Package and Pin Listings
Table 51. MPC8343EA (PBGA) Pinout Listing (continued)
Signal
Power
Supply
Notes
PCI, 10/100
Ethernet, and
other standard
(3.3 V)
OVDD
—
AF19
I
DDR
reference
voltage
—
AE10
I
DDR
reference
voltage
—
—
—
—
Package Pin Number
Pin Type
B27, D3, D11, D19, E15, E23, F5, F8,
F11, F14, F17, F20, G24, H23, H24, J6,
J14, J17, J18, K4, L9, L20, L23, L25, M6,
M9, M20, P5, P20, P23, R6, R9, R24,
U23, V4, V6
MVREF1
MVREF2
OVDD
No Connection
NC
A22, A23, A24, B22, B23, B24, C21,
C22, C23, C24, D21, D22, D23, D24,
E21, M27, M28, N26, N27, N28, P25,
P26, P27, R28, T24, T25, T26, T27, T28,
U27, U28, Y3, Y4, Y5, AA1, AA2, AA3,
AA4, AB1, AB2, AB3, AB4, AC1, AC2,
AC3, AC4, AD1, AD2, AD3, AD5, AD7,
AD11, AD12, AE4, AE6, AE8, AE9,
AE23, AF1, AF5, AF6, AF8, AF24, AG1,
AG3, AG4, AG7, AG8, AG9, AG10, AH2,
AH3, AH5, AH8, AH9, V5, V2, V1
Notes:
1. This pin is an open-drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
2. This pin is an open-drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
3. During reset, this output is actively driven rather than three-stated.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.
6. This pin must be always be tied to GND.
7. This pin must always be pulled up to OVDD.
8. Thermal sensitive resistor.
9. It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
resistor.
10.TSEC1_TXD[3] is required an external pull-up resistor. For proper functionality of the device, this pin must be pulled up or
actively driven high during a hard reset. No external pull-down resistors are allowed to be attached to this net.
11. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to LVDD1.
12. For systems that boot from local bus (GPCM)-controlled NOR flash, a pull up on LGPL4 is required.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
59
Clocking
19 Clocking
Figure 37 shows the internal distribution of the clocks.
MPC8343EA
e300 Core
Core PLL
core_clk
csb_clk
System PLL
To DDR
Memory
Controller DDR
Clock
ddr_clk
Div
/2
Clock
Unit lbiu_clk
4
4
/n
MCK[0:3]
MCK[0:3]
DDR
Memory
Device
LCLK[0:2]
To Local Bus
Memory
LBIU
Controller DLL
LSYNC_OUT
Local Bus
Memory
Device
LSYNC_IN
csb_clk to Rest
of the Device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI Clock
Divider
5
PCI_CLK_OUT[0:4]
Figure 37. MPC8343EA Clock Subsystem
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8343EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8343EA to function. When the
device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal
should be tied to GND.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
60
Freescale Semiconductor
Clocking
As shown in Figure 37, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the
csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL),
which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset,
clocking, and initialization in the MPC8349EA Reference Manual for more information on the clock
subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWL[DDRCM])
ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (÷2) to
create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the
same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
lbiu_clk = csb_clk × (1 + RCWL[LBIUCM])
lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create
the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is
controlled by LCCR[CLKDIV].
In addition, some of the internal units may have to be shut off or operate at lower frequency than the
csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped
register after the device exits reset. Table 52 specifies which units have a configurable clock frequency.
Table 52. Configurable Clock Units
Unit
Default Frequency
Options
TSEC1
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
TSEC2, I2C1
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Security core
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
USB DR, USB MPH
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
PCI and DMA complex
csb_clk
Off, csb_clk
All frequency combinations shown in the table below may not be available. Maximum operating
frequencies depend on the part ordered, see Section 22.1, “Part Numbers Fully Addressed by This
Document,” for part ordering details and contact your Freescale Sales Representative or authorized
distributor for more information.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
61
Clocking
Table 53 provides the operating frequencies for the MPC8343EA PBGA under recommended operating
conditions.
Table 53. Operating Frequencies for PBGA
Parameter1
e300 core frequency (core_clk)
266 MHz
333 MHz
400 MHz
200–266
200–333
200–400
Unit
MHz
Coherent system bus frequency (csb_clk)
100–266
MHz
DDR1 memory bus frequency (MCK)2
100–133
MHz
(MCK)3
100–133
MHz
16.67–133
MHz
25–66
MHz
Security core maximum internal operating frequency
133
MHz
USB_DR, USB_MPH maximum internal operating
frequency
133
MHz
DDR2 memory bus frequency
Local bus frequency (LCLKn)4
PCI input frequency (CLKIN or PCI_CLK)
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
2
The DDR data rate is 2× the DDR memory bus frequency.
3 The DDR data rate is 2× the DDR memory bus frequency.
4 The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBIUCM]).
19.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 54 shows the multiplication factor
encodings for the system PLL.
Table 54. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication Factor
0000
× 16
0001
Reserved
0010
×2
0011
×3
0100
×4
0101
×5
0110
×6
0111
×7
1000
×8
1001
×9
1010
× 10
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Freescale Semiconductor
Clocking
Table 54. System PLL Multiplication Factors (continued)
RCWL[SPMF]
System PLL Multiplication Factor
1011
× 11
1100
× 12
1101
× 13
1110
× 14
1111
× 15
As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 55
and Table 56 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
Table 55. CSB Frequency Options for Host Mode
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk :
Input Clock Ratio2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0010
2:1
Low
0011
3:1
Low
0100
4:1
Low
0101
5:1
Low
0110
6:1
Low
0111
Low
133
100
200
100
133
266
125
166
333
100
150
200
7:1
116
175
233
1000
8:1
133
200
266
Low
1001
9:1
150
225
300
Low
1010
10 : 1
166
250
333
Low
1011
11 : 1
183
275
Low
1100
12 : 1
200
300
Low
1101
13 : 1
216
325
Low
1110
14 : 1
233
Low
1111
15 : 1
250
Low
0000
16 : 1
266
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
63
Clocking
Table 55. CSB Frequency Options for Host Mode (continued)
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk :
Input Clock Ratio2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
High
0010
2:1
133
High
0011
3:1
100
200
High
0100
4:1
133
266
High
0101
5:1
166
333
High
0110
6:1
200
High
0111
7:1
233
High
1000
8:1
1
CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.
2
Table 56. CSB Frequency Options for Agent Mode
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk :
Input Clock Ratio2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0010
2:1
Low
0011
3:1
Low
0100
4:1
Low
0101
5:1
Low
0110
6:1
Low
0111
Low
133
100
200
100
133
266
125
166
333
100
150
200
7:1
116
175
233
1000
8:1
133
200
266
Low
1001
9:1
150
225
300
Low
1010
10 : 1
166
250
333
Low
1011
11 : 1
183
275
Low
1100
12 : 1
200
300
Low
1101
13 : 1
216
325
Low
1110
14 : 1
233
Low
1111
15 : 1
250
Low
0000
16 : 1
266
High
0010
4:1
100
133
266
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Clocking
Table 56. CSB Frequency Options for Agent Mode (continued)
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk :
Input Clock Ratio2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
High
0011
6:1
100
150
200
High
0100
8:1
133
200
266
High
0101
10 : 1
166
250
333
High
0110
12 : 1
200
300
High
0111
14 : 1
233
High
1000
16 : 1
266
1
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.
2
19.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 57 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 57 should be considered as reserved.
NOTE
Core VCO frequency = core frequency × VCO divider
VCO divider must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
Table 57. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider1
0–1
2–5
6
nn
0000
n
00
0001
0
1:1
2
01
0001
0
1:1
4
10
0001
0
1:1
8
11
0001
0
1:1
8
00
0001
1
1.5:1
2
01
0001
1
1.5:1
4
10
0001
1
1.5:1
8
11
0001
1
1.5:1
8
PLL bypassed
PLL bypassed
(PLL off, csb_clk clocks core directly) (PLL off, csb_clk clocks core directly)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
65
Clocking
Table 57. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
1
core_clk : csb_clk Ratio
VCO Divider1
0–1
2–5
6
00
0010
0
2:1
2
01
0010
0
2:1
4
10
0010
0
2:1
8
11
0010
0
2:1
8
00
0010
1
2.5:1
2
01
0010
1
2.5:1
4
10
0010
1
2.5:1
8
11
0010
1
2.5:1
8
00
0011
0
3:1
2
01
0011
0
3:1
4
10
0011
0
3:1
8
11
0011
0
3:1
8
Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency
is in the range of 800–1800 MHz.
19.3
Suggested PLL Configurations
Table 58 shows suggested PLL configurations for 33 and 66 MHz input clocks, when CFG_CLKIN_DIV
is low at reset.
Table 58. Suggested PLL Configurations
RCWL
Ref
No.1
SPMF
CORE
PLL
266 MHz Device
Input
Clock
Freq
(MHz)2
CSB
Freq
(MHz)
333 MHz Device
Core
Freq
(MHz)
Input
Clock
Freq
(MHz)2
CSB
Freq
(MHz)
400 MHz Device
Core
Freq
(MHz)
Input
Clock
Freq
(MHz)2
CSB
Freq
(MHz)
Core
Freq
(MHz)
33 MHz CLKIN/PCI_CLK Options
343
0011
1000011
33
100
150
33
100
150
33
100
150
324
0011
0100100
33
100
200
33
100
200
33
100
200
423
0100
0100011
33
133
200
33
133
200
33
133
200
622
0110
0100010
33
200
200
33
200
200
33
200
200
523
0101
0100011
33
166
250
33
166
250
33
166
250
424
0100
0100100
33
133
266
33
133
266
33
133
266
822
1000
0100010
33
266
266
33
266
266
33
266
266
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Clocking
Table 58. Suggested PLL Configurations (continued)
RCWL
Ref
No.1
266 MHz Device
Input
Clock
Freq
(MHz)2
CSB
Freq
(MHz)
333 MHz Device
Core
Freq
(MHz)
400 MHz Device
Input
Clock
Freq
(MHz)2
CSB
Freq
(MHz)
Core
Freq
(MHz)
Input
Clock
Freq
(MHz)2
CSB
Freq
(MHz)
Core
Freq
(MHz)
SPMF
CORE
PLL
326
0011
0100110
—
33
100
300
33
100
300
623
0110
0100011
—
33
200
300
33
200
300
922
1001
0100010
—
33
300
300
33
300
300
425
0100
0100101
—
33
133
333
33
133
333
524
0101
0100100
—
33
166
333
33
166
333
A22
1010
0100010
—
33
333
333
33
333
333
723
0111
0100011
—
—
33
233
350
604
0110
0000100
—
—
33
200
400
624
0110
0100100
—
—
33
200
400
823
1000
0100011
—
—
33
266
400
66 MHz CLKIN/PCI_CLK Options
242
0010
1000010
66
133
133
66
133
133
66
133
133
322
0011
0100010
66
200
200
66
200
200
66
200
200
224
0010
0100100
66
133
266
66
133
266
66
133
266
422
0100
0100010
66
266
266
66
266
266
66
266
266
323
0011
0100011
—
66
200
300
66
200
300
223
0010
0100101
—
66
133
333
66
133
333
522
0101
0100010
—
66
333
333
66
333
333
304
0011
0000100
—
—
66
200
400
324
0011
0100100
—
—
66
200
400
403
0100
0000011
—
—
66
266
400
423
0100
0100011
—
—
66
266
400
1
The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF
and COREPLL settings given in the table.
2 The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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67
Thermal
20 Thermal
This section describes the thermal specifications of the MPC8343EA.
20.1
Thermal Characteristics
.Table 59 provides the package thermal characteristics for the 620 29 × 29 mm PBGA of the MPC8343EA.
Table 59. Package Thermal Characteristics for PBGA
Parameter
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection on single-layer board (1s)
RθJA
21
°C/W
1, 2
Junction-to-ambient natural convection on four-layer board (2s2p)
RθJMA
15
°C/W
1, 3
Junction-to-ambient (at 200 ft/min) on single-layer board (1s)
RθJMA
17
°C/W
1, 3
Junction-to-ambient (at 200 ft/min) on four-layer board (2s2p)
RθJMA
12
°C/W
1, 3
Junction-to-board thermal
RθJB
6
°C/W
4
Junction-to-case thermal
RθJC
5
°C/W
5
Junction-to-package natural convection on top
ψJT
5
°C/W
6
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
20.2
Thermal Management Information
For the following sections, PD = (VDD × IDD) + PI/O where PI/O is the power dissipation of the I/O drivers.
See Table 5 for I/O power dissipation values.
20.2.1
Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA × PD)
where:
TJ = junction temperature (°C)
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Thermal
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Generally, the value obtained on a single-layer board is appropriate for
a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated. Test cases have
demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible.
20.2.2
Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package is approximately the same as the local air temperature near the device. Specifying
the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TA + (RθJA × PD)
where:
TJ = junction temperature (°C)
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
20.2.3
Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, use
the thermal characterization parameter (ΨJT) to determine the junction temperature and a measure of the
temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
TJ = junction temperature (°C)
TT = thermocouple temperature on top of package (°C)
ΨJT = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type
T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
69
Thermal
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
20.2.4
Heat Sinks and Junction-to-Case Thermal Resistance
Some application environments require a heat sink to provide the necessary thermal management of the
device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (°C/W)
RθJC = junction-to-case thermal resistance (°C/W)
RθCA = case-to-ambient thermal resistance (°C/W)
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit
board, or change the thermal dissipation on the printed-circuit board surrounding the device.
The thermal performance of devices with heat sinks has been simulated with a few commercially available
heat sinks. The heat sink choice is determined by the application environment (temperature, air flow,
adjacent component power dissipation) and the physical space available. Because there is not a standard
application environment, a standard heat sink is not required.
Table 60 shows heat sink thermal resistance for PBGA of the MPC8343EA.
f
Table 60. Heat Sink and Thermal Resistance of MPC8343EA (PBGA)
29 × 29 mm PBGA
Heat Sink Assuming Thermal Grease
Air Flow
Thermal Resistance
AAVID 30 × 30 × 9.4 mm pin fin
Natural convection
13.5
AAVID 30 × 30 × 9.4 mm pin fin
1 m/s
9.6
AAVID 30 × 30 × 9.4 mm pin fin
2 m/s
8.8
AAVID 31 × 35 × 23 mm pin fin
Natural convection
11.3
AAVID 31 × 35 × 23 mm pin fin
1 m/s
8.1
AAVID 31 × 35 × 23 mm pin fin
2 m/s
7.5
Wakefield, 53 × 53 × 25 mm pin fin
Natural convection
9.1
Wakefield, 53 × 53 × 25 mm pin fin
1 m/s
7.1
Wakefield, 53 × 53 × 25 mm pin fin
2 m/s
6.5
Natural convection
10.1
MEI, 75 × 85 × 12 no adjacent board, extrusion
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
Thermal
Table 60. Heat Sink and Thermal Resistance of MPC8343EA (PBGA) (continued)
29 × 29 mm PBGA
Heat Sink Assuming Thermal Grease
Air Flow
Thermal Resistance
MEI, 75 × 85 × 12 no adjacent board, extrusion
1 m/s
7.7
MEI, 75 × 85 × 12 no adjacent board, extrusion
2 m/s
6.6
MEI, 75 × 85 × 12 mm, adjacent board, 40 mm side bypass
1 m/s
6.9
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More
detailed thermal models can be made available on request.
Heat sink vendors include the following list:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-thermal.com
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
603-224-9988
408-567-8082
818-842-7277
408-436-8770
800-522-2800
603-635-5102
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
71
Thermal
Interface material vendors include the following:
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01801
Internet: www.chomerics.com
Dow-Corning Corporation
Dow-Corning Electronic Materials
P.O. Box 994
Midland, MI 48686-0997
Internet: www.dowcorning.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
The Bergquist Company
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
20.3
781-935-4850
800-248-2481
888-642-7674
800-347-4572
Heat Sink Attachment
When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip.
The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to
the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the
package from the board. Such peeling forces reduce the solder joint lifetime of the package. The
recommended maximum force on the top of the package is 10 lb force (4.5 kg force). Any adhesive
attachment should attach to painted or plastic surfaces, and its performance should be verified under the
application requirements.
20.3.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimize the size of the clearance to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this
case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
TJ = TC + (RθJC × PD)
where:
TJ = junction temperature (°C)
TC = case temperature of the package (°C)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
System Design Information
RθJC = junction-to-case thermal resistance (°C/W)
PD = power dissipation (W)
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8343EA.
21.1
System Clocking
The MPC8343EA includes two PLLs:
1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The
frequency ratio between the platform and CLKIN is selected using the platform PLL ratio
configuration bits as described in Section 19.1, “System PLL Configuration.”
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in Section 19.2, “Core PLL Configuration.”
21.2
PLL Power Supply Filtering
Each PLL gets power through independent power supply pins (AVDD1, AVDD2, respectively). The AVDD
level should always equal to VDD, and preferably these voltages are derived directly from VDD through a
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide four independent filter circuits as illustrated in Figure 38, one to each of the four AVDD pins.
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
Figure 38 shows the PLL power supply filter circuit.
10 Ω
VDD
AVDD (or L2AVDD)
2.2 µF
2.2 µF
GND
Low ESL Surface Mount Capacitors
Figure 38. PLL Power Supply Filter Circuit
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
73
System Design Information
21.3
Decoupling Recommendations
Due to large address and data buses and high operating frequencies, the MPC8343EA can generate
transient power surges and high frequency noise in its power supply, especially while driving large
capacitive loads. This noise must be prevented from reaching other components in the MPC8343EA
system, and the device itself requires a clean, tightly regulated source of power. Therefore, the system
designer should place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pin of the
device. These capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND
power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under
the device using a standard escape pattern. Others can surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, distribute several bulk storage capacitors around the PCB, feeding the VDD, OVDD, GVDD,
and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also
be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
21.4
Connection Recommendations
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low
inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be
connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of
the MPC8343EA.
21.5
Output Buffer DC Impedance
The MPC8343EA drivers are characterized over process, voltage, and temperature. For all buses, the
driver is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 39). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Freescale Semiconductor
System Design Information
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN) ÷ 2.
OVDD
RN
SW2
Pad
Data
SW1
RP
OGND
Figure 39. Driver Impedance Measurement
Two measurements give the value of this resistance and the strength of the driver current source. First, the
output voltage is measured while driving logic 1 without an external differential termination resistor. The
measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1
with an external precision differential termination resistor of value Rterm. The measured voltage is
V2 = (1 ÷ (1/R1 + 1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1 ÷ V2 – 1).
The drive current is then Isource = V1 ÷ Rsource.
Table 61 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
Table 61. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI Signals
(Not Including PCI
Output Clocks)
PCI Output Clocks
(Including
PCI_SYNC_OUT)
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
42 Target
20 Target
Z0
W
RP
42 Target
25 Target
42 Target
20 Target
Z0
W
Differential
NA
NA
NA
NA
ZDIFF
W
Note: Nominal supply voltages. See Table 1, Tj = 105°C.
21.6
Configuration Pin Multiplexing
The MPC8343EA power-on configuration options can be set through external pull-up or pull-down
resistors of 4.7 kΩ on certain output pins (see the customer-visible configuration pins). These pins are used
as output only pins in normal operation.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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75
Ordering Information
However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched
when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal
function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with
the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed
for the output pins.
21.7
Pull-Up Resistor Requirements
The MPC8343EA requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins,
including I2C pins, and IPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface,
refer to application note AN2931, “PowerQUICC Design Checklist.”
22 Ordering Information
This section presents ordering information for the device discussed in this document, and it shows an
example of how the parts are marked.
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8343E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications
(Document Order No. MPC8343EEC).
22.1
Part Numbers Fully Addressed by This Document
Table 62 shows an analysis of the Freescale part numbering nomenclature for the MPC8343EA. The
individual part numbers correspond to a maximum processor core frequency. Each part number also
contains a revision code that refers to the die mask revision number. For available frequency configuration
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
76
Freescale Semiconductor
Ordering Information
parts including extended temperatures, refer to the device product summary page on our website listed on
the back cover of this document or, contact your local Freescale sales office.
Table 62. Part Numbering Nomenclature
MPC
nnnn
Product
Part
Code Identifier
MPC
e
t
pp
aa
a
r
Encryption
Acceleration
Temperature1
Range
Package2
Processor
Frequency3
Platform
Frequency
Revision
Level
e300 core
speed
AD = 266
AG = 400
D = 266
B = 3.1
8343
Blank = Not
included
E = included
Blank = 0 to 105°C
C = –40 to 105°C ZQ = PBGA
VR = PB Free PBGA
Notes:
1. For temperature range = C, processor frequency is limited to 400 with a platform frequency of 266 and up to with a platform
frequency of 333
2. See Section 18, “Package and Pin Listings,” for more information on available package types.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
Table 63 shows the SVR settings by device and package type.
Table 63. SVR Settings
22.2
Device
Package
SVR (Rev. 3.0)
MPC8343EA
PBGA
8056_0030
MPC8343A
PBGA
8057_0030
Part Marking
Parts are marked as in the example shown in Figure 40.
MPCnnnnetppaaar
core/platform MHZ
ATWLYYWW
CCCCC
*MMMMM
YWWLAZ
PBGA
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
Figure 40. Freescale Part Marking for PBGA Devices
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
77
Document Revision History
23 Document Revision History
This table provides a revision history of this document.
Table 64. Document Revision History
Rev.
Number
Date
Substantive Change(s)
11
09/2011
• In Section 2.2, “Power Sequencing,” added Section 2.2.1, “Power-Up Sequencing” and Figure 4.
• In Table 25, Table 29, and Table 27, removed the GTX_CLK125.
• In Table 30, updated tMDKHDX Max value from 170ns to 70ns.
10
11/2010
• In Table 51, added overbar to LCS[4] and LCS[5] signals. In Table 51 added note for pin LGPL4.
• In Section 21.7, “Pull-Up Resistor Requirements, updated the list of open drain type pins.
9
05/2010
• In Table 25 through Table 26, changed VIL(min) to VIH(max) to (20%–80%).
• Added Table 8, “EC_GTX_CLK125 AC Timing Specifications.”
8
5/2009
• In Section 18.1, “Package Parameters for the MPC8343EA PBGA, changed solder ball for TBGA
and PBGA from 95.5 Sn/0.5 Cu/4 Ag to 96.5 Sn/3.5 Ag.
• In Table 53, added two columns for the DDR1 and DDR2 memory bus frequency.
• In Table 62, footnote 1, changed 667(TBGA) to 533(TBGA). footnote 4, added data rate for DDR1
and DDR2.
7
2/2009
• Added footnote 6 to Table 7.
• In Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only.
• In Table 35, corrected tLBKHOV parameter to tLBKLOV (output data is driven on falling edge of clock
in DLL bypass mode). Similarly, made the same correction to Figure 18, Figure 20, and Figure 21
for output signals.
• Added footnote 10 to Table 51.
• In Table 51, updated note 11 to say the following: “SEC1_TXD[3] is required an external pull-up
resistor. For proper functionality of the device, this pin must be pulled up or actively driven high
during a hard reset. No external pull-down resistors are allowed to be attached to this net.”
• In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.
• In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and
“the four AVDD pins.”
• In Table 62, updated note 1 to say the following: “For temperature range = C, processor frequency
is limited to 400 with a platform frequency of 266.”
6
4/2007
• In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and
added USB to the seventh row.
• In Section 21.7, “Pull-Up Resistor Requirements,“deleted last two paragraphs and after first
paragraph, added a new paragraph.
• Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
5
3/2007
• Page 1, updated first paragraph to reflect PowerQUICC II Pro information.
• In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to tCISKEW
and deleted original note 3; renumbered the remaining notes.
• In Figure 38, “JTAG Interface Connection,” updated with new figure.
• In Figure 38, “JTAG Interface Connection,” updated with new figure.
• In Section 23, “Ordering Information,” replaced first paragraph and added a note.
• In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.
4
12/2006
Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified Tddkhds for 333 MHz
from 900 ps to 775 ps.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
78
Freescale Semiconductor
Document Revision History
Table 64. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
3
11/2006
• Updated note in introduction.
• In the features list in Section 1, “Overview,” updated DDR data rate to show 266 MHz for PBGA
parts for all silicon revisions.
• In Table 57, “Suggested PLL Configurations,” added the following row:
• Ref No: 823, SPMF: 1000, Core PLL: 0100011, 400-MHz Device Input Clock Freq: 33, CSB
Freq: 266, and Core Freq: 400.
• In Section 23, “Ordering Information,” replicated note from document introduction.
2
8/2006
• Changed all references to revision 2.0 silicon to revision 3.0 silicon.
• Changed number of general purpose parallel I/O pins to 39 in Section 1, “Overview.”
• Changed VIH minimum value in Table 35, “JTAG Interface DC Electrical Characteristics,” to
OVDD – 0.3.
• In Table 40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min =
2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”
•
1
4/2006
• Removed Table 20, “Timing Parameters for DDR2-400.”
• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
• Changed Min and Max values for VIH and VIL in Table 40Table 44,“PCI DC Electrical
Characteristics.”
• In Table 58, “MPC8343EA (PBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that
MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.’
• Table 58, “MPC8343EA (PBGA) Pinout Listing,” in row AVDD3 changed power supply from
“AVDD3” to ‘—.’
0
3/2006
Initial public release
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
79
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Document Number: MPC8343EAEC
Rev. 11
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