MPC8347CZQAGDB

Freescale Semiconductor Technical Data Document Number: MPC8347EEC Rev. 11, 02/2009 MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications The MPC8347E PowerQUICC™ II Pro is a next generation PowerQUICC II integrated host processor. The MPC8347E contains a PowerPC™ processor core built on Power Architecture™ technology with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349E PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual. To locate published errata or updates for this document, refer to the MPC8347E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. NOTE The information in this document is accurate for revision 1.1 silicon and earlier. For information on revision 3.0 silicon and later versions (for orderable part numbers ending in A or B), see the MPC8347EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications. See Section 23.1, “Part Numbers Fully Addressed by This Document,” for silicon revision level determination. © Freescale Semiconductor, Inc., 2005–2009. All rights reserved. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ethernet: Three-Speed Ethernet, MII Management . 22 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 55 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 System Design Information . . . . . . . . . . . . . . . . . . . 91 Document Revision History . . . . . . . . . . . . . . . . . . . 95 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 98 Overview 1 Overview This section provides a high-level overview of the MPC8347E features. Figure 1 shows the major functional units within the MPC8347E. Security DUART Dual I2C Timers GPIO High-Speed USB 2.0 Dual Role e300 Core Interrupt Controller 10/100/1000 Ethernet 32KB D-Cache 10/100/1000 Ethernet 32KB I-Cache PCI Local Bus SEQ DDR SDRAM Controller DMA Host Figure 1. MPC8347E Block Diagram Major features of the MPC8347E are as follows: • Embedded PowerPC e300 processor core; operates at up to 667 MHz — High-performance, superscalar processor core — Floating-point, integer, load/store, system register, and branch processing units — 32-Kbyte instruction cache, 32-Kbyte data cache — Lockable portion of L1 cache — Dynamic power management — Software-compatible with the other Freescale processor families that implement Power Architecture technology • Double data rate, DDR SDRAM memory controller — Programmable timing for DDR-1 SDRAM — 32- or 64-bit data interface, up to 333-MHz data rate for TBGA, 266 MHz for PBGA — Four banks of memory, each up to 1 Gbyte — DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports — Full error checking and correction (ECC) support — Page mode support (up to 16 simultaneous open pages) — Contiguous or discontiguous memory mapping — Read-modify-write support — Sleep mode for self-refresh SDRAM — Auto refresh MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 2 Freescale Semiconductor Overview • • • — On-the-fly power management using CKE — Registered DIMM support — 2.5-V SSTL2 compatible I/O Dual three-speed (10/100/1000) Ethernet controllers (TSECs) — Dual controllers designed to comply with IEEE 802.3®, 802.3u®, 820.3x®, 802.3z®, 802.3ac® standards — Ethernet physical interfaces: – 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex – 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex — Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100 programming models — 9.6-Kbyte jumbo frame support — RMON statistics support — Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module — MII management interface for control and status — Programmable CRC generation and checking PCI interface — Designed to comply with PCI Specification Revision 2.2 — Data bus width: – 32-bit data PCI interface operating at up to 66 MHz — PCI 3.3-V compatible — PCI host bridge capabilities — PCI agent mode on PCI interface — PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses and support for delayed read transactions — Posting of processor-to-PCI and PCI-to-memory writes — On-chip arbitration supporting five masters on PCI — Accesses to all PCI address spaces — Parity supported — Selectable hardware-enforced coherency — Address translation units for address mapping between host and peripheral — Dual address cycle for target — Internal configuration registers accessible from PCI Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs): — Public key execution unit (PKEU) : – RSA and Diffie-Hellman algorithms MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 3 Overview • • – Programmable field size up to 2048 bits – Elliptic curve cryptography – F2m and F(p) modes – Programmable field size up to 511 bits — Data encryption standard (DES) execution unit (DEU) – DES and 3DES algorithms – Two key (K1, K2) or three key (K1, K2, K3) for 3DES – ECB and CBC modes for both DES and 3DES — Advanced encryption standard unit (AESU) – Implements the Rijndael symmetric-key cipher – Key lengths of 128, 192, and 256 bits – ECB, CBC, CCM, and counter (CTR) modes — ARC four execution unit (AFEU) – Stream cipher compatible with the RC4 algorithm – 40- to 128-bit programmable key — Message digest execution unit (MDEU) – SHA with 160- or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either algorithm — Random number generator (RNG) — Four crypto-channels, each supporting multi-command descriptor chains – Static and/or dynamic assignment of crypto-execution units through an integrated controller – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes Universal serial bus (USB) dual role controller — USB on-the-go mode with both device and host functionality — Complies with USB specification Rev. 2.0 — Can operate as a stand-alone USB device – One upstream facing port – Six programmable USB endpoints — Can operate as a stand-alone USB host controller – USB root hub with one downstream-facing port – Enhanced host controller interface (EHCI) compatible – High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations — External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI) Universal serial bus (USB) multi-port host controller — Can operate as a stand-alone USB host controller – USB root hub with one or two downstream-facing ports MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 4 Freescale Semiconductor Overview • • • • – Enhanced host controller interface (EHCI) compatible – Complies with USB Specification Rev. 2.0 — High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations — Direct connection to a high-speed device without an external hub — External PHY with serial and low-pin count (ULPI) interfaces Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 133 MHz — Four chip selects support four external slaves — Up to eight-beat burst transfers — 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller — Three protocol engines on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user-programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit) Programmable interrupt controller (PIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for 8 external and 35 internal discrete interrupt sources — Support for 1 external (optional) and 7 internal machine checkstop interrupt sources — Programmable highest priority request — Four groups of interrupts with programmable priority — External and internal interrupts directed to host processor — Redirects interrupts to external INTA pin in core disable mode. — Unique vector number for each interrupt source Dual industry-standard I2C interfaces — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus — System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware DMA controller — Four independent virtual channels — Concurrent execution across multiple channels with programmable bandwidth control — All channels accessible to local core and remote PCI masters — Misaligned transfer capability MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 5 Overview • • • • • • — Data chaining and direct mode — Interrupt on completed segment and chain DUART — Two 4-wire interfaces (RxD, TxD, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D Serial peripheral interface (SPI) for master or slave General-purpose parallel I/O (GPIO) — 52 parallel I/O pins multiplexed on various chip interfaces System timers — Periodic interrupt timer — Real-time clock — Software watchdog timer — Eight general-purpose timers Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan Integrated PCI bus and SDRAM clock generation MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 6 Freescale Semiconductor Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8347E. The MPC8347E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings1 Characteristic Symbol Max Value Unit Core supply voltage VDD –0.3 to 1.32 V PLL supply voltage AVDD –0.3 to 1.32 V DDR DRAM I/O voltage GVDD –0.3 to 3.63 V LVDD –0.3 to 3.63 V OV DD –0.3 to 3.63 V MVIN –0.3 to (GV DD + 0.3) V 2, 5 MVREF –0.3 to (GV DD + 0.3) V 2, 5 Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V 4, 5 Local bus, DUART, CLKIN, system control and power management, I2C, and JTAG signals OVIN –0.3 to (OV DD + 0.3) V 3, 5 PCI OVIN –0.3 to (OV DD + 0.3) V 6 Storage temperature range TSTG –55 to 150 °C Three-speed Ethernet I/O, MII management voltage PCI, local bus, DUART, system control and power management, and JTAG I/O voltage Input voltage I2C, DDR DRAM signals DDR DRAM reference Notes Notes: Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2 Caution: MV must not exceed GV IN DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3 Caution: OV must not exceed OV IN DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4 Caution: LV must not exceed LV IN DD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5 (M,L,O)V and MV IN REF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6 OV on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as IN shown in Figure 3. 1 MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 7 Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8347E. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 2. Recommended Operating Conditions Symbol Recommended Value Unit Notes Core supply voltage VDD 1.2 V ± 60 mV V 1 PLL supply voltage AVDD 1.2 V ± 60 mV V 1 DDR DRAM I/O supply voltage GVDD 2.5 V ± 125 mV V Three-speed Ethernet I/O supply voltage LVDD1 3.3 V ± 330 mV 2.5 V ± 125 mV V Three-speed Ethernet I/O supply voltage LVDD2 3.3 V ± 330 mV 2.5 V ± 125 mV V PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD 3.3 V ± 330 mV V Characteristic Note: GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative direction. 1 Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8347E. G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tinterface1 Note: 1. tinterface refers to the clock period associated with the bus clock interface. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 8 Freescale Semiconductor Electrical Characteristics Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8347E for the 3.3-V signals, respectively. 11 ns (Min) +7.1 V 7.1 V p-to-p (Min) Overvoltage Waveform 4 ns (Max) 0V 4 ns (Max) 62.5 ns +3.6 V Undervoltage Waveform 7.1 V p-to-p (Min) –3.5 V Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Output Drive Capability Output Impedance (Ω) Supply Voltage Local bus interface utilities signals 40 OVDD = 3.3 V PCI signals (not including PCI output clocks) 25 PCI output clocks (including PCI_SYNC_OUT) 40 DDR signal 18 GVDD = 2.5 V TSEC/10/100 signals 40 LVDD = 2.5/3.3 V DUART, system control, I2C, JTAG, USB 40 OVDD = 3.3 V GPIO signals 40 OVDD = 3.3 V, LVDD = 2.5/3.3 V Driver Type 2.2 Power Sequencing MPC8347E does not require the core supply voltage and I/O supply voltages to be applied in any particular order. Note that during the power ramp up, before the power supplies are stable, there may be a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are three-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 9 Power Characteristics 3 Power Characteristics The estimated typical power dissipation for the MPC8347E device is shown in Table 4. Table 4. MPC8347E Power Dissipation1 PBGA Core Frequency (MHz) CSB Frequency (MHz) Typical at TJ = 65 Typical2,3 Maximum4 Unit 266 266 1.3 1.6 1.8 W 133 1.1 1.4 1.6 W 266 1.5 1.9 2.1 W 133 1.4 1.7 1.9 W 200 1.5 1.8 2.0 W 100 1.3 1.7 1.9 W 333 2.0 3.0 3.2 W 166 1.8 2.8 2.9 W 266 2.1 3.0 3.3 W 133 1.9 2.9 3.1 W 300 2.3 3.2 3.5 W 150 2.1 3.0 3.2 W 333 2.4 3.3 3.6 W 166 2.2 3.1 3.4 W 266 2.4 3.3 3.6 W 133 2.2 3.1 3.4 W 400 400 TBGA 333 400 450 500 533 1 The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5. Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of T J = 105°C, and a Dhrystone benchmark application. 3 Thermal solutions may need to design to a value higher than typical power based on the end application, T target, and I/O A power. 4 Maximum power is based on a voltage of VDD = 1.2 V, worst case process, a junction temperature of TJ = 105°C, and an artificial smoke test. 2 MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 10 Freescale Semiconductor Power Characteristics Table 5 shows the estimated typical I/O power dissipation for MPC8347E. Table 5. MPC8347E Typical I/O Power Dissipation Parameter DDR2 GVDD (1.8 V) DDR1 GVDD (2.5 V) OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Unit Comments 200 MHz, 32 bits — 0.42 — — — W — 200 MHz, 64 bits — 0.55 — — — W — 266 MHz, 32 bits — 0.5 — — — W — 266 MHz, 64 bits — 0.66 — — — W — 300 MHz,1 32 bits — 0.54 — — — W — 300 MHz,1 64 bits — 0.7 — — — W — 333 MHz,1 32 bits — 0.58 — — — W — 333 MHz,1 64 bits — 0.76 — — — W — 400 MHz,1 32 bits — — — — — — 400 MHz,1 64 bits — — — — — — 33 MHz, 32 bits — — 0.04 — — W — 66 MHz, 32 bits — — 0.07 — — W — 167 MHz, 32 bits — — 0.34 — — W — 133 MHz, 32 bits — — 0.27 — — W — 83 MHz, 32 bits — — 0.17 — — W — 66 MHz, 32 bits — — 0.14 — — W — 50 MHz, 32 bits — — 0.11 — — W — MII — — — 0.01 — W GMII or TBI — — — 0.06 — W Multiply by number of interfaces used. RGMII or RTBI — — — — 0.04 W 12 MHz — — 0.01 — — W 480 MHz — — 0.2 — — W — — 0.01 — — W Interface DDR I/O 65% utilization 2.5 V Rs = 20 Ω Rt = 50 Ω 2 pair of clocks PCI I/O load = 30 pF Local bus I/O load = 25 pF TSEC I/O load = 25 pF USB Other I/O 1 Multiply by 2 if using 2 ports. — TBGA package only. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 11 Clock Input Timing 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8347E. 4.1 DC Electrical Characteristics Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8347E. Table 6. CLKIN DC Timing Specifications Parameter Condition Symbol Min Max Unit Input high voltage — VIH 2.7 OVDD + 0.3 V Input low voltage — VIL –0.3 0.4 V 0 V ≤ VIN ≤ OVDD IIN — ±10 μA PCI_SYNC_IN input current 0 V ≤ VIN ≤ 0.5 V or OVDD – 0.5 V ≤ VIN ≤ OV DD IIN — ±10 μA PCI_SYNC_IN input current 0.5 V ≤VIN ≤ OVDD – 0.5 V IIN — ±50 μA CLKIN input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8347E can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the MPC8347E. Table 7. CLKIN AC Timing Specifications Parameter/Condition Symbol Min Typical Max Unit Notes CLKIN/PCI_CLK frequency fCLKIN — — 66 MHz 1, 6 CLKIN/PCI_CLK cycle time tCLKIN 15 — — ns — CLKIN/PCI_CLK rise and fall time tKH, tKL 0.6 1.0 2.3 ns 2 tKHK/tCLKIN 40 — 60 % 3 — — — ±150 ps 4, 5 CLKIN/PCI_CLK duty cycle CLKIN/PCI_CLK jitter Notes: 1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be