MPC8535AVTAKG

Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC8535EEC Rev. 7, 07/2015 MPC8535E MPC8535E PowerQUICC III Integrated Processor Hardware Specifications • High-performance, 32-bit e500 core, scaling up to 1.25 GHz, that implements the Power Architecture® technology – 36-bit physical addressing – Double-precision embedded floating point APU using 64-bit operands – Embedded vector and scalar single-precision floating-point APUs using 32- or 64-bit operands – Memory management unit (MMU) • Integrated L1/L2 cache – L1 cache—32-Kbyte data and 32-Kbyte instruction – L2 cache—512-Kbyte (8-way set associative) • DDR2/DDR3 SDRAM memory controller with full ECC support – One 64-bit/32-bit data bus – Up to 250-MHz clock (500-MHz data rate) – Supporting up to 16 Gbytes of main memory – Using ECC, detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble – Invoke a level of system power management by asserting MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode – Both hardware and software options to support battery-backed main memory • Integrated security engine (SEC) optimized to process all the algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP. – XOR engine for parity checking in RAID storage applications • Enhanced Serial peripheral interfaces (eSPI) – Support boot capability from eSPI • Two enhanced three-speed Ethernet controllers (eTSECs) with SGMII support – Three-speed support (10/100/1000 Mbps) – Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and IEEE Std 1588™-compatible controllers MAPBGA–783 29 mm x 29 mm • • • • • • • • • • • • – Support for various Ethernet physical interfaces: GMII, TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII – Support TCP/IP acceleration and QOS features – MAC address recognition and RMON statistics support – Support ARP parsing and generating wake-up events based on the parsing results while in deep sleep mode – Support accepting and storing packets while in deep sleep mode High-speed interfaces (multiplexed) supporting: – Two PCI Express interfaces – PCI Express 1.0a compatible – One x4/x2/x1 PCI Express interface – Two x2/x1 ports – One SGMII interface – One Serial ATA (SATA) controller supports SATA I and SATA I data rates PCI 2.2 compatible PCI controller Two universal serial bus (USB) dual-role controllers comply with USB specification revision 2.0 133-MHz, 32-bit, enhanced local bus (eLBC) with memory controller Enhanced secured digital host controller (eSDHC) used for SD/MMC card interface – Support boot capability from eSDHC Integrated four-channel DMA controller Dual I2C and dual universal asynchronous receiver/transmitter (DUART) support Programmable interrupt controller (PIC) Power management, low standby power – Support Doze, Nap, Sleep, Jog, and Deep Sleep mode – PMC wake on: LAN activity, USB connection or remote wakeup, GPIO, internal timer, or external interrupt event System performance monitor IEEE Std 1149.1™-compatible, JTAG boundary scan 783-pin FC-PBGA package, 29 mm × 29 mm Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2009-2011, 2014-2015 Freescale Semiconductor, Inc. All rights reserved. Table of Contents 1 2 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3 1.1 Pin Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21 2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .31 2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.10 Ethernet Management Interface Electrical Characteristics 60 2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.12 Enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .65 2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .74 2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .76 2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 2.17 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .90 2.21 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 3 4 5 6 7 2.23 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 113 3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.2 Power Supply Design and Sequencing . . . . . . . . . . . 113 3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 114 3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 114 3.5 SerDes Block Power Supply Decoupling Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 115 3.7 Pull-Up and Pull-Down Resistor Requirements . . . . . 115 3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 115 3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 116 3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 117 3.11 Guidelines for High-Speed Interface Termination . . . 119 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.1 Part Numbering Nomenclature . . . . . . . . . . . . . . . . . 121 4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 122 5.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 124 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 125 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 2 Freescale Semiconductor Pin Assignments and Reset States This figure shows the major functional units within the chip. e500 Core 32-Kbyte D-Cache MPC8535E Performance Monitor Timers SD MMC Enhanced Local Bus USB Host/ Device USB Host/ Device ULPI ULPI SEC OpenPIC Gigabit Ethernet w/ IEEE 1588 512-Kbyte L2 Cache 32-Kbyte I-Cache Coherency Module Gigabit Ethernet w/ IEEE 1588 eSPI DUART 2x I2C Power Management 64-bit Async DDR2/DDR3 Queue SDRAM Controller with ECC PCI 32 DMA PCI-e PCI-e SATA SGMII SerDes 4 Lane SerDes Figure 1. Chip Block Diagram 1 Pin Assignments and Reset States NOTE The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails for the eTSEC blocks and to ease the port of existing PowerQUICC III software NOTE The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. See Table 1 for more details. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 3 Pin Assignments and Reset States 1.1 Pin Map See Table 1 for the MPC8535E pinout, which is a subset of the MPC8536E. A 2 3 M N P R GND GND GVDD MDQS [7] MDQ [58] MDQ [59] AVDD_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_ USB1_D USB1_D USB1_ RXD SRDS2 RX_CLK RXD TX_EN RX_DV STP CLK [7] [0] [2] [5] [3] [1] MDQ [44] MDQ [40] MDM [5] MDQS [5] GVDD MDQ [42] MDQ [43] MDQ [35] MDQ [60] MDQ [61] MDM [7] MDQS [7] GND MDM [62] MDQ [63] GND MDQ [45] MDQ [41] MCS [0] GND MDQ [33] GVDD MDQ [38] MDQ [52] GVDD MDM [6] MDQS [6] MDQ [50] MDQ [51] GVDD USB1_ AGND_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D USB1_ OVDD PWRRXD SRDS2 RXD RX_DV GTX_CLK RXD NXT [6] [1] [3] [4] FAULT [1] [0] [3] SD2_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ USB1_ PCTL0/ USB2_D USB2_D GND USB3_D USB3_D PLL_ RXD RXD TXD RXD RX_CLK RXD [1] [0] [0] [1] GPIO[6] [2] [0] [3] [2] [7] TPA MAPAR_ OUT GND NC MA [0] MCK [3] 9 MCK [0] MCK [0] MCS [2] MRAS GND GVDD GVDD MDQ [36] GND MDM [4] GND MODT [0] GVDD MODT [2] NC MA [2] GND GVDD MA [4] MCAS GND MDQ [39] MDQ [53] MDQ [49] GVDD MDQ [37] GVDD MDQS [4] MDQS [4] MDQ [48] MODT [3] MCS [3] MCS [1] MCK [2] MCK [2] MA [13] GVDD MODT [1] NC SEE DETAIL A MCK MCK MA GV DD MA [8] GND MA [7] [1] [5] GVDD MCKE [3] [5] NC GND GND NC MDQS [6] GND SD2_ SD2_ IMP_CAL REF_ _TX CLK SD2_ PLL_ TPD SD2_ REF_ CLK Rsvd S2GND Rsvd S2VDD MDQ [54] GVDD MDQ [55] GND TSEC1_ TXD [1] TSEC3_ RX_ER Rvsd TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD GTX_CLK TX_EN TXD TXD TXD TX_ER [1] [2] [4] [6] GND TVDD GND MA [5] NC MA [14] MA [15] MCKE [2] MCKE [0] GVDD MCKE [1] NC X2GND 11 MA [6] GVDD MECC [3] MA [12] GVDD MECC [2] GVDD MCK [1] MCK [1] GND X2VDD SD2_TX [1] 12 MA [11] MA [9] GND MECC [7] NC MECC [0] GND GVDD TSEC3_ TSEC3_ MSRCID MSRCID UART_ X2GND SD2_TX X2VDD SD2_TX X2GND TXD RXD CTS [0] [2] [1] [0] [7] [7] [1] MAPAR_ ERR MBA [2] MECC [6] MCK [4] VDD_ CORE 14 GND MDQ [27] 15 MDQ [26] 16 MDQ [30] MDQS [3] MDQS [8] GVDD MECC [1] MDQ [31] MDQS [3] MDM [3] MECC [5] GND GVDD GND GVDD MDQ [19] MDQ [23] MDQ [18] GVDD GND GND LCS6/ DMA_ DACK2 LA [28] VDD_ CORE GND LCS [4] LCS5/ DMA_ DREQ2 LA [30] 23 MDQS [0] GVDD 25 MDQ [12] MDQ [5] MDM [0] 26 MDQ [0] MDQ [1] LAD [25] GND GND LAD [27] MDQS [0] [30] LBS[1] BVDD LAD [28] LWE[2]/ LBS[2] LAD [23] LAD [26] MDQ [4] LDP [3] LAD [19] GND GND LAD [22] LAD [18] LAD [16] LSYNC_ IN AVDD_ LSYNC_ LBIU OUT C LAD [24] [29] D LAD [21] GND LAD [15] LCLK [0] LCLK [2] BVDD LAD [14] PCI1_ AD [30] VDD_ PLAT SD1_TX [6] LAD [1] SD1_TX [1] XGND SD1_TX [3] XGND SD1_TX [4] XVDD SD1_TX [6] XGND SD1_TX [2] XGND SD1_TX [5] XVDD SD1_TX [2] XVDD SD1_TX [5] BVDD MDM [1] VDD_ PLAT SENSEVDD_ PLAT XGND LWE[3]/ LBS[3] MDQ [9] GND SD1_TX [4] LAD [31] 22 PCI1_ GNT [1] XVDD GND GVDD SENSEVSS PCI1_ REQ [1] SD1_TX [3] BVDD SEE DETAIL C LAD LWE[1]/ LAD MDQ [6] GND VDD_ CORE XVDD MDQ [7] MDQ [2] CLK_ OUT SD1_TX [1] LGPL0/ LFCLE MDQS [1] GND SENSEVDD_ CORE LGPL4/ LGTA/ LGPL1/ LUPWAIT/ XGND LFALE LPBSE/ LFRB LCS [3] MDQS [1] GND VDD_ CORE VDD_ PLAT VDD_ CORE LGPL5 BVDD MDQ [3] GND MSRCID [3] BVDD GND GVDD GND VDD_ CORE GND VDD_ PLAT LGPL2/ LOE/ LFRE MDQ [14] VDD_ CORE LWE0/ LBS0/ LFWE BVDD LCLK [1] GND LAD [0] LAD [3] LAD [4] LBCTL LAD [7] LALE LDP [0] GND LAD [20] LAD [17] LDP [1] LAD [13] LAD [12] E F G H J LAD [11] XVDD LAD [2] SD1_TX [0] BVDD SD1_TX [0] LAD [5] LAD [6] GND LAD [9] XGND GND VDD_ PLAT GND GND VDD_ PLAT NC SGND SVDD SD1_RX [1] SD1_ IMP_CAL SGND _RX SD1_RX [1] NC SVDD SD1_RX SGND [0] LAD [10] LAD [8] SGND SD1_RX [0] SVDD K L M N P GND VDD_ PLAT GND GND VDD_ PLAT XVDD XGND SVDD Rsvd Rsvd SVDD SGND SD1_RX [3] SVDD SD1_RX [3] SD1_RX [2] SVDD SD1_RX SGND [2] R GND VDD_ CORE LA [27] NC MDQ [15] GND GND LCS [2] 21 VDD_ CORE VDD_ PLAT VDD_ CORE LCS [0] LCS [1] GVDD GND GND MDQ [20] GND VDD_ CORE GND VDD_ TSEC3_ MDVAL MSRCID RXD CORE [1] [6] LCS7/ DMA_ DDONE2 MDQ [16] 20 GND VDD_ CORE LA [29] GND MDQ [17] MDQ [10] B GND MDIC [1] MDIC [0] LGPL3/ LFWP MDQ [11] A GND GVDD LA [31] GND VDD_ CORE GND GND 19 GND GVDD MDQ [21] MDQ [28] MVREF MECC [4] GVDD MDQ [29] LDP [2] MDQ [22] MCK [4] MDM [2] MDQ [24] GND MDQS [2] GND GND MDQS [2] MDQ [25] MDQ [13] MDM [8] GVDD 18 MDQ [8] MDQS [8] VDD_ CORE GND T GND MCP SGND SGND SVDD NC SGND SD1_ PLL_ TPA SD1_ REF_ CLK SD1_ REF_ CLK U AGND_ SRDS XGND SVDD GND UART_ SIN [0] UART_ GND RTS [1] IRQ[10]/ IRQ[9]/ DMA_ OVDD DDRCLK DMA_ DACK[3] DREQ[3] IRQ[11]/ PCI1_GNT OVDD UDE [4]/GPIO DMA_ DDONE[3] [3] USB3_ USB3_D [7] NXT 7 USB3_ DIR USB3_ STP 8 USB2_ PCTL0/ GPIO[8] Rsvd 9 SDHC_ SDHC_ WP/GPIO CMD [5] SDHC_ SDHC_ CD/GPIO DAT [3] [4] 12 PCI1_ REQ [2] SDHC_ SDHC_ DAT CLK [2] 13 PCI1_ GNT [2] IIC2_ SDA SYSCLK 14 IIC2_ SCL 15 GND RTC OVDD PCI1_ AD [26] OVDD PCI1_ IDSEL IRQ [5] AVDD_ HRESET CORE PCI1_ AD [29] PCI1_ AD [27] IRQ_ OUT PCI1_ AD [24] PCI1_ AD [23] IRQ [1] PCI1_ C_BE [3] PCI1_ AD [20] 17 PCI1_ AD [18] CKSTP_ AVDD_ PLAT IN 18 IRQ [3] AVDD_ SRESET DDR 19 OVDD ASLEEP AVDD_ PCI1 20 GND PCI1_ TRDY IIC1_ SCL TRST 21 OVDD PCI1_ SERR IRQ [0] IIC1_ SDA 22 PCI1_ AD [15] GND PCI1_ AD [11] 23 OVDD PCI1_ AD [10] PCI1_ AD [12] 24 25 GND GND XVDD L2_ TSTCLK PCI1_ IRDY PCI1_ AD [16] PCI1_ C_BE [2] PCI1_ FRAME XGND L1_ TSTCLK PCI1_ PERR C_BE [1] [6] [8] PAR XVDD IRQ [2] PCI1_ AD [13] GND PCI1_ AD [14] SGND PCI1_ AD [5] PCI1_ AD [7] PCI1_ AD [9] SGND SD1_RX [4] SVDD SD1_RX SGND [4] SVDD SD1_RX [5] PCI1_ AD [1] PCI1_ AD [4] PCI1_ AD [8] PCI1_ C_BE [0] GND PCI1_ AD [2] PCI1_ AD [3] PCI1_ CLK 26 SD1_RX [7] SVDD POWER_ OVDD EN PCI1_ AD [6] TMS 27 SD1_ SGND IMP_CAL _TX TDO TCK TDI 28 AF AG AH SD1_RX LSSD_ [6] MODE OVDD SD1_RX POWER_ PCI1_ AD [6] OK [0] SGND IRQ [4] 16 CKSTP_ OUT PCI1_ AD [17] PCI1_ PCI1_ DEVSEL STOP 11 SDHC_ SDHC_ DAT DAT [0] [1] PCI1_ REQ [0] SEEIRQDETAIL DPCI1_ PCI1_ IRQ SD1_TX 10 UART_ SIN [1] HRESET_ REQ PCI1_ AD [19] SVDD 6 PCI1_REQ [4]/GPIO [1] PCI1_ AD [21] SVDD USB3_D USB3_D [5] [6] PCI1_ AD [28] OVDD [7] 3 5 PCI1_ AD [22] SD1_TX [7] 2 4 PCI1_ AD [31] SGND NC UART_ RTS [0] 1 USB2_ USB2_D USB2_D USB3_D USB3_ CLK [4] [4] [5] CLK PCI1_ AD [25] GND XVDD TEST_ SEL PCI1_REQ PCI1_GNT [3]/GPIO [3]/GPIO [0] [2] PCI1_ OVDD GNT [0] TRIG_ IRQ GND OUT/READY TRIG_IN [7] /QUIESCE VDD_ PLAT UART_ SOUT [1] USB1_ DIR USB2_D USB2_D USB3_D USB3_D [3] [2] [2] [3] OVDD SEE DETAIL B GND GVDD LVDD DMA_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D SD2_RX DACK[0]/ USB2_D OVDD S2VDD TXD S2GND RXD RXD TXD RXD CLK125 COL [0] [6] [7] GPIO[10] [0] [5] [4] [0] [4] TSEC_ SD2_ TSEC3_ TSEC1_ USB2_ USB2_ USB2_ TVDD LVDD GND 1588_TRIG GND GND S2VDD SD2_RX IMP_CAL TXD RXD NXT STP DIR [0] _RX [2] _IN[1] [6] SDHC_ TSEC_ USB2_ TSEC1_ TSEC1_ TSEC1_ TSEC3_ TSEC3_ TSEC3_ SPI_ SPI_ SD2_RX DAT[4]/SPI NC S2GND PWRTXD RXD TXD TXD TXD 1588_TRIG TXD MOSI CLK [1] FAULT _CS[0] [7] [5] [5] [3] [5] [6] _IN[0] SDHC_ USB2_ SPI_ TSEC3_ TSEC3_ TSEC3_ TSEC_ TSEC1_ TSEC1_ SD2_RX S2GND PCTL1/ NC GND DAT[6]/SPI GND 1588_ RX_ER TXD COL TX_ER CRS [1] GPIO[9] MISO _CS[2] [4] CLK SDHC_ DMA_ SDHC_ DMA_ UART_ TSEC_ TSEC_ EC_ TSEC3_ TSEC3_ 1588_CLK DAT[7]/SPI DREQ[0]/ DAT[5]/SPI OVDD DACK[1]/ SOUT 1588_TRIG NC NC NC MDC CRS TX_CLK _OUT GPIO[11] _CS[3] GPIO[14] _CS[1] _OUT[1] [0] TSEC_ TSEC_ TSEC_ DMA_ UART_ DMA_ DMA_ EC_ SD2_TX MSRCID 1588_PULSE 1588_TRIG 1588_PULSE OVDD DDONE[0]/ DDONE[1]/ DREQ[1]/ X2GND X2VDD GND CTS MDIO GPIO[12] GPIO[13] [4] [0] GPIO[15] _OUT2 _OUT[0] _OUT1 [0] MA [3] GND USB1_ TSEC1_ PCTL1/ TX_CLK GPIO[7] Rvsd 10 28 AH L MCK [3] 27 AG K MDQ [57] 8 24 AF J MDQ [56] 5 17 AE H MBA [1] 13 AD G MDQ [34] MA [10] 7 AC F MDQ [47] MWE 6 AB E MDQ [46] MBA [0] V AA D MDQ [32] 4 U Y C MDQS [5] 1 T W B GVDD SD1_ PLL_ TPD AVDD_ SRDS SGND SD1_RX [5] SVDD SD1_RX [7] V W Y AA AB AC AD AE Figure 2. Chip Pin Map Bottom View MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 4 Freescale Semiconductor Pin Assignments and Reset States A 1 B C D E F G H J K L M N P GVDD MDQS [5] MDQ [32] MDQ [46] MDQ [47] MDQ [34] GND MDQ [56] MDQ [57] GND GVDD MDQS [7] MDQ [58] 2 MDQ [44] MDQ [40] MDM [5] MDQS [5] GVDD MDQ [42] MDQ [43] MDQ [35] MDQ [60] MDQ [61] MDM [7] MDQS [7] GND MDM [62] 3 GND MDQ [45] MDQ [41] MCS [0] GND MDQ [33] GVDD MDQ [38] MDQ [52] GVDD MDM [6] MDQS [6] MDQ [50] MDQ [51] 4 MBA [0] MWE MCS [2] GVDD MDQ [36] GND MDM [4] GND MDQ [39] MDQ [53] MDQ [49] MDQS [6] MDQ [54] MDQ [55] 5 MA [10] MBA [1] MRAS GND MODT [0] GVDD MDQ [37] GVDD MDQS [4] MDQS [4] MDQ [48] GND GVDD GND 6 MAPAR_ OUT NC GND GVDD MODT [2] MODT [3] MCS [3] MCS [1] MCK [2] MCK [2] SD2_ IMP_CAL _TX SD2_ REF_ CLK S2GND SD2_RX [0] 7 GND MA [0] GVDD NC MCAS MA [13] GVDD MODT [1] NC GND SD2_ PLL_ TPD SD2_ REF_ CLK S2VDD SD2_RX [0] 8 MCK [3] MCK [3] MA [2] GND GVDD GND MA [1] MCK [5] MCK [5] GND Rsvd S2GND SD2_RX [1] S2GND 9 MCK [0] MCK [0] GVDD MA [4] MA [8] MA [7] GVDD MCKE [3] NC NC Rsvd S2VDD SD2_RX [1] S2GND 10 MA [3] GND MA [5] NC MA [14] MA [15] MCKE [2] MCKE [0] GVDD MCKE [1] NC X2GND NC NC 11 MA [6] GVDD MECC [3] MA [12] GVDD MECC [2] GVDD MCK [1] MCK [1] GND X2VDD SD2_TX [1] X2GND SD2_TX [0] 12 MA [11] MA [9] GND MECC [7] GND NC MECC [0] GVDD GND GVDD X2GND SD2_TX [1] X2VDD SD2_TX [0] 13 MAPAR_ ERR MBA [2] MECC [6] MDQS [8] MDQS [8] MDM [8] GND MCK [4] MCK [4] VDD_ CORE GND VDD_ CORE GND VDD_ CORE 14 GND MDQ [27] GVDD MECC [1] GVDD MECC [5] MECC [4] GVDD GND GVDD VDD_ CORE GND VDD_ CORE GND DETAIL A Figure 3. Chip Pin Map Detail A MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 5 Pin Assignments and Reset States AA AB AC AD AE MDQ [59] AVDD_ SRDS2 TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D RXD RXD RX_CLK TX_EN RX_DV [0] [2] [3] [1] MDQ [63] AGND_ SRDS2 TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D RXD RXD RX_DV GTX_CLK RXD [1] [3] [4] [6] [1] [0] [3] GVDD SD2_ PLL_ TPA Rvsd S2VDD TSEC3_ RX_ER V Y T Rvsd U W R TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ RXD RXD TXD RXD RXD RX_CLK [2] [0] [3] [2] [7] GND TVDD TSEC1_ TXD [1] GND LVDD TSEC1_ TX_CLK TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD TXD GTX_CLK TX_EN TX_ER [1] [2] [4] [6] USB1_ PCTL0/ GPIO[6] TSEC_ 1588_TRIG _IN[1] USB1_D USB1_D [5] [7] USB2_D USB2_D [0] [1] USB1_ NXT GND AG AH USB1_ STP USB1_ DIR 1 OVDD USB1_ PWRFAULT 2 USB3_D USB3_D [1] [0] 3 USB1_ PCTL1/ GPIO[7] OVDD USB2_D USB2_D USB3_D USB3_D [2] [3] [3] [2] 4 GND USB2_ CLK USB2_D USB2_D USB3_D [4] [4] [5] USB3_ CLK 5 DMA_ DACK[0]/ GPIO[10] USB2_D [7] OVDD USB3_D USB3_D [5] [6] 6 TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D TXD RXD RXD TXD RXD COL [6] CLK125 [0] [5] [4] [0] [4] SD2_ TSEC3_ IMP_CAL TXD _RX [2] USB1_ CLK AF TSEC1_ RXD [6] USB2_ NXT USB2_ STP GND USB2_ DIR USB3_ NXT USB3_D [7] 7 NC TSEC_ TSEC1_ TSEC1_ TSEC1_ TSEC3_ TSEC3_ TSEC3_ 1588_TRIG TXD TXD RXD TXD TXD TXD _IN[0] [7] [5] [5] [3] [5] [6] USB2_ PWRFAULT SPI_ CLK SDHC_ DAT[4]/SPI _CS[0] SPI_ MOSI USB3_ DIR USB3_ STP 8 NC TSEC3_ TSEC3_ TSEC3_ TXD COL TX_ER [4] SPI_ MISO GND Rsvd 9 OVDD DMA_ DACK[1]/ GPIO[11] UART_ SOUT [0] SDHC_ WP/GPIO [5] SDHC_ CMD 10 GND DMA_ DREQ[1]/ GPIO[15] UART_ CTS [0] OVDD SDHC_ DAT [3] SDHC_ CD/GPIO [4] 11 NC TVDD GND GND LVDD USB2_ TSEC_ TSEC1_ TSEC1_ PCTL1/ GND 1588_ RX_ER CRS GPIO[9] CLK TSEC_ SDHC_ SDHC_ TSEC_ DMA_ TSEC3_ TSEC3_ 1588_CLK 1588_TRIG EC_ DAT[7]/SPI DREQ[0]/ DAT[5]/SPI MDC CRS TX_CLK _OUT _OUT[1] _CS[3] GPIO[14] _CS[1] SDHC_ USB2_ DAT[6]/SPI PCTL0/ _CS[2] GPIO[8] TSEC_ TSEC_ TSEC_ X2VDD 1588_PULSE 1588_TRIG 1588_PULSE MSRCID [4] _OUT[0] _OUT2 _OUT1 EC_ MDIO TSEC3_ TSEC3_ MSRCID MSRCID TXD RXD [2] [0] [7] [7] UART_ CTS [1] UART_ SOUT [1] UART_ RTS [0] UART_ SIN [0] UART_ RTS [1] GND UART_ SIN [1] SDHC_ DAT [0] SDHC_ DAT [1] 12 DDRCLK IRQ[10]/ DMA_ DACK[3] IRQ[9]/ DMA_ DREQ[3] PCI1_ REQ [2] SDHC_ CLK SDHC_ DAT [2] 13 PCI1_GNT IRQ[11]/ DMA_ [4]/GPIO DDONE[3] [3] OVDD PCI1_ GNT [2] IIC2_ SDA SYSCLK 14 X2GND DMA_ DMA_ DDONE[0]/ DDONE[1]/ GPIO[12] GPIO[13] GND VDD_ CORE TSEC3_ RXD [6] MDVAL MSRCID [1] GND TEST_ SEL OVDD VDD_ CORE GND VDD_ CORE GND MSRCID [3] MCP GND UDE DETAIL B Figure 4. Chip Pin Map Detail B MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 6 Freescale Semiconductor Pin Assignments and Reset States DETAIL C 15 MDQ [26] MDQ [31] GND GVDD GND GVDD GND MDIC [0] GND MDIC [1] GND VDD_ CORE GND VDD_ CORE 16 MDQ [30] MDQS [3] MDQ [19] MDQ [23] MDQ [18] GND LCS [4] LCS5/ DMA_ DREQ2 LCS6/ DMA_ DACK2 LA [28] VDD_ CORE GND VDD_ CORE GND 17 MDQS [3] MDM [3] GVDD GND MDQS [2] MDQ [22] LA [31] LA [30] GND LA [29] GND VDD_ PLAT GND VDD_ PLAT 18 MDQ [25] MDQ [24] MDQS [2] MDM [2] GVDD MDQ [21] GND LGPL3/ LFWP BVDD LCS [0] LCS7/ DMA_ DDONE2 GND VDD_ PLAT GND 19 MDQ [29] MDQ [28] NC MDQ [17] MDQ [16] MDQ [20] LCS [1] LCS [2] BVDD LGPL5 LA [27] VDD_ PLAT GND VDD_ PLAT 20 MDQ [11] MDQ [10] GND GVDD GND BVDD LGPL2/ LOE/ LFRE LCS [3] LGPL0/ LFCLE LGPL4/ LGTA/ LGPL1/ LUPWAIT/ XGND LFALE LPBSE/ LFRB SD1_TX [1] XVDD 21 MDQ [15] MDQ [14] GVDD MDQ [3] MDQ [7] GND LAD [31] LWE[3]/ LBS[3] BVDD GND LAD [1] XVDD SD1_TX [1] XGND 22 MDQS [1] MDQS [1] MDQ [2] MDQ [6] GVDD LAD [29] LAD [30] LWE[1]/ LBS[1] LWE0/ LBS0/ LFWE LAD [0] LAD [2] SD1_TX [0] XGND SD1_TX [2] 23 MDQ [9] MDM [1] MDQS [0] GND LAD [27] BVDD LAD [28] LWE[2]/ LBS[2] BVDD LAD [3] BVDD SD1_TX [0] XVDD SD1_TX [2] 24 MDQ [8] MDQ [13] GVDD MDQS [0] LAD [24] LAD [23] LAD [26] LCLK [0] LCLK [1] LAD [4] LAD [5] XGND NC SGND 25 MDQ [12] MDQ [5] MDM [0] MDQ [4] LDP [3] LAD [19] GND LCLK [2] LBCTL LAD [7] LAD [6] NC SVDD SD1_RX [1] 26 MDQ [0] MDQ [1] LAD [25] GND LAD [22] LAD [18] LAD [16] BVDD LALE LDP [0] GND SD1_ IMP_CAL _RX SGND SD1_RX [1] 27 GND LDP [2] GND LSYNC_ IN LAD [21] GND LAD [15] LAD [14] GND LAD [11] LAD [9] SVDD SD1_RX [0] SGND 28 MVREF GND AVDD_ LBIU LSYNC_ OUT LAD [20] LAD [17] LDP [1] LAD [13] LAD [12] LAD [10] LAD [8] SGND SD1_RX [0] SVDD A B C D E F G H J K L M N P Figure 5. Chip Pin Map Detail C MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 7 Pin Assignments and Reset States DETAIL D GND VDD_ CORE GND SENSEVDD_ CORE CLK_ OUT VDD_ CORE GND VDD_ CORE SENSEVSS PCI1_ REQ [1] PCI1_ GNT [1] GND VDD_ PLAT GND VDD_ PLAT SENSEVDD_ PLAT VDD_ PLAT GND VDD_ PLAT GND PCI1_ GNT [0] GND VDD_ PLAT GND SD1_TX [3] XVDD SD1_TX [4] XGND SD1_TX [3] XGND SD1_TX [4] XVDD Rsvd XGND PCI1_ AD [31] PCI1_ AD [28] GND PCI1_REQ [4]/GPIO [1] RTC HRESET_ REQ IIC2_ SCL 15 PCI1_ REQ [0] OVDD PCI1_ AD [26] OVDD PCI1_ IDSEL IRQ [5] HRESET AVDD_ CORE 16 PCI1_ AD [30] PCI1_ AD [29] PCI1_ AD [27] IRQ_ OUT PCI1_ AD [24] PCI1_ AD [23] IRQ [1] IRQ [4] CKSTP_ OUT 17 OVDD PCI1_ AD [25] PCI1_ AD [22] OVDD PCI1_ C_BE [3] PCI1_ AD [20] PCI1_ AD [18] CKSTP_ IN AVDD_ PLAT 18 IRQ [7] GND PCI1_ AD [21] PCI1_ AD [19] GND PCI1_ AD [17] IRQ [3] SRESET AVDD_ DDR 19 SD1_TX [6] XVDD L2_ TSTCLK PCI1_ IRDY PCI1_ AD [16] PCI1_ C_BE [2] PCI1_ FRAME OVDD ASLEEP AVDD_ PCI1 20 XVDD SD1_TX [6] XGND L1_ TSTCLK PCI1_ PERR PCI1_ DEVSEL PCI1_ STOP GND PCI1_ TRDY IIC1_ SCL TRST 21 XGND SD1_TX [5] XVDD SD1_TX [7] IRQ [6] IRQ [8] PCI1_ PAR PCI1_ C_BE [1] OVDD PCI1_ SERR IRQ [0] IIC1_ SDA 22 Rsvd XVDD SD1_TX [5] XGND SD1_TX [7] XVDD IRQ [2] PCI1_ AD [13] GND PCI1_ AD [14] PCI1_ AD [15] GND PCI1_ AD [11] 23 SVDD SVDD SGND SGND SVDD SVDD SGND SGND PCI1_ AD [5] PCI1_ AD [7] PCI1_ AD [9] OVDD PCI1_ AD [10] PCI1_ AD [12] 24 SGND SD1_RX [3] SVDD NC SGND SD1_RX [4] SVDD SD1_RX [6] LSSD_ MODE OVDD PCI1_ AD [1] PCI1_ AD [4] PCI1_ AD [8] PCI1_ C_BE [0] 25 SVDD SD1_RX [3] SGND SD1_ PLL_ TPA SVDD SD1_RX [4] SGND SD1_RX POWER_ [6] OK PCI1_ AD [0] GND PCI1_ AD [2] PCI1_ AD [3] PCI1_ CLK 26 SD1_RX [2] SVDD SD1_ REF_ CLK AGND_ SRDS NC SVDD SD1_RX [5] SGND SD1_RX [7] SVDD POWER_ EN OVDD PCI1_ AD [6] TMS 27 SD1_RX [2] SGND SD1_ REF_ CLK SD1_ PLL_ TPD AVDD_ SRDS SGND SD1_RX [5] SVDD SD1_RX [7] SGND SD1_ IMP_CAL _TX TDO TCK TDI 28 R T U V W Y AA AB AC AD AE AF AG AH TRIG_ OUT/READY TRIG_IN /QUIESCE PCI1_REQ PCI1_GNT [3]/GPIO [3]/GPIO [0] [2] Figure 6. Chip Pin Map Detail D MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 8 Freescale Semiconductor Pin Assignments and Reset States This table provides the pin-out listing for the 783 FC-PBGA package. 3 Table 1. Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes PCI PCI1_AD[31:0] Muxed Address / data AB15,Y17,AA17,AC15, AB17,AC16,AA18, AD17,AE17,AB18, AB19,AE18,AC19, AF18,AE19,AC20, AF23,AE23,AC23, AH24,AH23,AG24, AE24,AG25,AD24, AG27,AC24,AF25, AG26,AF26,AE25, AD26 I/O OVDD — PCI1_C_BE[3:0] Command/Byte Enable AD18, AD20,AD22, AH25 I/O OVDD 29 PCI1_PAR Parity AC22 I/O OVDD 29 PCI1_FRAME Frame AE20 I/O OVDD 2,29 PCI1_TRDY Target Ready AF21 I/O OVDD 2,29 PCI1_IRDY Initiator Ready AB20 I/O OVDD 2,29 PCI1_STOP Stop AD21 I/O OVDD 2,29 PCI1_DEVSEL Device Select AC21 I/O OVDD 2,29 PCI1_IDSEL Init Device Select AE16 I OVDD 29 PCI1_PERR Parity Error AB21 I/O OVDD 2,29 PCI1_SERR System Error AF22 I/O OVDD 2,4,29 PCI1_REQ[4:3]/GPIO[1:0] Request AE15,Y15 I OVDD — PCI1_REQ[2:1] Request AF13,W16 I OVDD 29 PCI1_REQ[0] Request AA16 I/O OVDD 29 PCI1_GNT[4:3]/GPIO[3:2] Grant AC14, AA15 O OVDD PCI1_GNT[2:1] Grant AF14,Y16 O OVDD 5,9,25,29 PCI1_GNT[0] Grant W18 I/O OVDD 29 PCI1_CLK PCI Clock AH26 I OVDD 29 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 9 Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes DDR SDRAM Memory Interface MDQ[0:63] Data A26,B26,C22,D21,D25, B25,D22,E21,A24,A23, B20,A20,A25,B24,B21, A21,E19,D19,E16,C16, F19,F18,F17,D16,B18, A18,A15,B14,B19,A19, A16,B15,D1,F3,G1,H2, E4,G5,H3,J4,B2,C3,F2, G2,A2,B3,E1,F1,L5,L4, N3,P3,J3,K4,N4,P4,J1, K1,P1,R1,J2,K2,P2,R2 I/O GVDD — MECC[0:7] Error Correcting Code G12,D14,F11,C11, G14,F14,C13,D12 I/O GVDD — MAPAR_ERR Address Parity Error A13 I GVDD — MAPAR_OUT Address Parity Out A6 O GVDD — MDM[0:8] Data Mask C25,B23,D18,B17,G4, C2,L3,L2,F13 O GVDD — MDQS[0:8] Data Strobe D24,B22,C18,A17,J5, C1,M4,M2,E13 I/O GVDD — MDQS[0:8] Data Strobe C23,A22,E17,B16,K5, D2,M3,N1,D13 I/O GVDD — MA[0:15] Address B7,G8,C8,A10,D9,C10, A11,F9,E9,B12,A5, A12,D11,F7,E10,F10 O GVDD — MBA[0:2] Bank Select A4,B5,B13 O GVDD — MWE Write Enable B4 O GVDD — MRAS Row Address Strobe C5 O GVDD — MCAS Column Address Strobe E7 O GVDD — MCS[0:3] Chip Select D3,H6,C4,G6 O GVDD — MCKE[0:3] Clock Enable H10,K10,G10,H9 O GVDD 11 MCK[0:5] Differential Clock 3 Pairs / DIMM A9,J11,J6,A8,J13,H8 O GVDD — MCK[0:5] Differential Clock 3 Pairs / DIMM B9,H11,K6,B8,H13,J8 O GVDD — MODT[0:3] On Die Termination E5,H7,E6,F6 O GVDD — MDIC[0:1] Calibration H15,K15 I/O GVDD 26 Local Bus Controller Interface MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 10 Freescale Semiconductor Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Name Package Pin Number Pin Type Power Supply Notes LAD[0:31] Muxed data / address K22,L21,L22,K23,K24, L24,L25,K25,L28,L27, K28,K27,J28,H28,H27, G27,G26,F28,F26,F25, E28,E27,E26,F24,E24, C26,G24,E23,G23,F22, G22,G21 I/O BVDD 5,9,29 LDP[0:3] Data parity K26,G28,B27,E25 I/O BVDD 29 LA[27] Burst address L19 O BVDD 5,9,29 LA[28:31] Port address K16,K17,H17,G17 O BVDD 5,7,9,29 LCS[0:4] Chip selects K18,G19,H19,H20,G16 O BVDD 29 LCS5/DMA_DREQ2 Chips selects / DMA Request H16 I/O BVDD 1,29 LCS6/DMA_DACK2 Chips selects / DMA Ack J16 O BVDD 1,29 LCS7/DMA_DDONE2 Chips selects / DMA Done L18 O BVDD 1,29 LWE0/LBS0/LFWE Write enable / Byte select J22 O BVDD 5,9,29 LWE[1:3]/LBS[1:3] Write enable / Byte select H22,H23,H21 O BVDD 5,9,29 LBCTL Buffer control J25 O BVDD 5,8,9,29 LALE Address latch enable J26 O BVDD 5,8,9,29 LGPL0/LFCLE UPM general purpose line 0 / J20 FLash command latch enable O BVDD 5,9,29 LGPL1/LFALE UPM general purpose line 1 / K20 Flash address latch enable O BVDD 5,9,29 LGPL2/LOE/LFRE UPM general purpose line 2 / G20 Output enable/Flash read enable O BVDD 5,8,9,29 LGPL3/LFWP UPM general purpose line 3 / H18 Flash write protect O BVDD 5,9,29 LGPL4/LGTA/LUPWAIT /LPBSE/LFRB UPM general purpose line 4 / L20 Target Ack/Wait/SDRAM parity byte select/Flash Ready-busy I/O BVDD 29, 35 LGPL5 UPM general purpose line 5 / K19 Amux O BVDD 5,9,29 LCLK[0:2] Local bus clock H24,J24,H25 O BVDD 29 LSYNC_IN Synchronization D27 I BVDD 29 LSYNC_OUT Local bus DLL D28 O BVDD 29 O OVDD — Signal DMA DMA_DACK[0:1] /GPIO[10:11] DMA Acknowledge AD6,AE10 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 11 Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes DMA_DREQ[0:1] /GPIO[14:15] DMA Request AB10,AD11 I OVDD — DMA_DDONE[0:1] /GPIO[12:13] DMA Done AA11,AB11 O OVDD — DMA_DREQ[2]/LCS[5] Chips selects / DMA Request H16 I/O BVDD 1,29 DMA_DACK[2]/LCS[6] Chips selects / DMA Ack J16 O BVDD 1,29 DMA_DDONE[2]/LCS[7] Chips selects / DMA Done L18 O BVDD 1,29 DMA_DREQ[3]/IRQ[9] External interrupt/DMA request AE13 I OVDD 1 DMA_DACK[3]/IRQ[10] External interrupt/DMA Ack AD13 I/O OVDD 1 DMA_DDONE[3]/IRQ[11] External interrupt/DMA done AD14 I/O OVDD 1 I/O OVDD — USB Port 1 USB1_D[7:0] USB1 Data bits AF1,AE2,AE1,AD2, AC2,AC1,AB2,AB1 USB1_NXT USB1 Next data AF2 I OVDD — USB1_DIR USB1 Data Direction AH1 I OVDD — USB1_STP USB1 Stop AG1 O OVDD 5,9 USB1_PWRFAULT USB1 bus power fault. AH2 I OVDD — USB1_PCTL0/GPIO[6] USB1 Port control 0 AC3 O OVDD — USB1_PCTL1/GPIO[7] USB1 Port control 1 AC4 O OVDD — USB1_CLK USB1 bus clock AD1 I OVDD — I/O OVDD — USB Port 2 USB2_D[7:0] USB2 Data bits AE6,AC6,AF5,AE5, AF4,AE4,AE3,AD3 USB2_NXT USB2 Next data AC7 I OVDD — USB2_DIR USB2 Data Direction AF7 I OVDD — USB2_STP USB2 Stop AD7 O OVDD 5,9 USB2_PWRFAULT USB2 bus power fault. AC8 I OVDD — USB2_PCTL0/GPIO[8] USB2 Port control 0 AG9 O OVDD — USB2_PCTL1/GPIO[9] USB2 Port control 1 AC9 O OVDD — USB2_CLK USB2 bus clock AD5 I OVDD — — Reserved — AH8 — — — Reserved — AH7,AG6,AH6,AG5, AG4,AH4,AG3,AH3, AG7, AG8, AH9,AH5 — — 27 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 12 Freescale Semiconductor Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes Programmable Interrupt Controller MCP Machine check processor Y14 I OVDD — UDE Unconditional debug event AB14 I OVDD — IRQ[0:8] External interrupts AG22,AF17,AB23, AF19,AG17,AF16, AA22,Y19,AB22 I OVDD — IRQ[9]/DMA_DREQ[3] External interrupt/DMA request AE13 I OVDD 1 IRQ[10]/DMA_DACK[3] External interrupt/DMA Ack AD13 I/O OVDD 1 IRQ[11]/DMA_DDONE[3] External interrupt/DMA done AD14 I/O OVDD 1 IRQ_OUT Interrupt output O OVDD 2,4 AC17 Ethernet Management Interface EC_MDC Management data clock Y10 O OVDD 5,9,22 EC_MDIO Management data In/Out Y11 I/O OVDD — I LVDD 31 Gigabit Reference Clock EC_GTX_CLK125 Reference clock AA6 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_TXD[7:0] Transmit data AA8,AA5,Y8,Y5,W3, W5,W4,W6 O LVDD 5,9,22 TSEC1_TX_EN Transmit Enable W1 O LVDD 23 TSEC1_TX_ER Transmit Error AB5 O LVDD 5,9 TSEC1_TX_CLK Transmit clock In AB4 I LVDD — TSEC1_GTX_CLK Transmit clock Out W2 O LVDD — TSEC1_CRS Carrier sense AA9 I/O LVDD 17 TSEC1_COL Collision detect AB6 I LVDD — TSEC1_RXD[7:0] Receive data AB3,AB7,AB8,Y6,AA2, Y3,Y1,Y2 I LVDD — TSEC1_RX_DV Receive data valid AA1 I LVDD — TSEC1_RX_ER Receive data error Y9 I LVDD — TSEC1_RX_CLK Receive clock AA3 I LVDD — Three-Speed Ethernet Controller (Gigabit Ethernet 3) TSEC3_TXD[7:0] Transmit data T12,V8,U8,V9,T8,T7, T5,T6 O TVDD 5,9,22 TSEC3_TX_EN Transmit Enable V5 O TVDD 23 TSEC3_TX_ER Transmit Error U9 O TVDD 5,9 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 13 Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes TSEC3_TX_CLK Transmit clock In U10 I TVDD — TSEC3_GTX_CLK Transmit clock Out U5 O TVDD — TSEC3_CRS Carrier sense T10 I/O TVDD 17 TSEC3_COL Collision detect T9 I TVDD — TSEC3_RXD[7:0] Receive data U12,U13,U6,V6,V1,U3, U2,V3 I TVDD — TSEC3_RX_DV Receive data valid V2 I TVDD — TSEC3_RX_ER Receive data error T4 I TVDD — TSEC3_RX_CLK Receive clock U1 I TVDD — IEEE 1588 TSEC_1588_CLK Clock In W9 I LVDD 29 TSEC_1588_TRIG_IN[0:1] Trigger In W8,W7 I LVDD 29 TSEC_1588_TRIG_OUT[0:1] Trigger Out U11,W10 O LVDD 5,9,29 TSEC_1588_CLK_OUT Clock Out V10 O LVDD 5,9,29 TSEC_1588_PULSE_OUT1 Pulse Out1 V11 O LVDD 5,9,29 TSEC_1588_PULSE_OUT2 Pulse Out2 T11 O LVDD 5,9,29 eSDHC SDHC_CMD Command line AH10 I/O OVDD 29 SDHC_CD/GPIO[4] Card detection AH11 I OVDD — SDHC_DAT[0:3] Data line AG12,AH12,AH13, AG11 I/O OVDD 29 SDHC_DAT[4:7] / SPI_CS[0:3] 8-bit MMC Data line / SPI chip AE8,AC10,AF9,AA10 select I/O OVDD 29 SDHC_CLK SD/MMC/SDIO clock AG13 I/O OVDD 29 SDHC_WP/GPIO[5] Card write protection AG10 I OVDD 1, 32 eSPI SPI_MOSI Master Out Slave In AF8 I/O OVDD 29 SPI_MISO Master In Slave Out AD9 I OVDD 29 SPI_CLK eSPI clock AD8 I/O OVDD 29 SPI_CS[0:3] / SDHC_DAT[4:7] eSPI chip select / SDHC 8-bit AE8,AC10,AF9,AA10 MMC data I/O OVDD 29 DUART UART_CTS[0:1] Clear to send AE11,Y12 I OVDD 29 UART_RTS[0:1] Ready to send AB12,AD12 O OVDD 29 UART_SIN[0:1] Receive data AC12,AF12 I OVDD 29 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 14 Freescale Semiconductor Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name UART_SOUT[0:1] Transmit data Package Pin Number AF10,AA12 Pin Type Power Supply O OVDD 5,9,22, 10,29 Notes I2C interface IIC1_SCL Serial clock AG21 I/O OVDD 4,21,29 IIC1_SDA Serial data AH22 I/O OVDD 4,21,29 IIC2_SCL Serial clock AH15 I/O OVDD 4,21,29 IIC2_SDA Serial data AG14 I/O OVDD 4,21,29 SerDes1(x4) SD1_TX[7:4] Transmit Data (+) Y23,W21,V23,U21 O XVDD — SD1_TX[7:4] Transmit Data(-) Y22,W20,V22,U20 O XVDD — SD1_RX[7:4] Receive Data(+) AC28,AB26,AA28,Y26 I XVDD — SD1_RX[7:4] Receive Data(–) AC27,AB25,AA27,Y25 I XVDD — Reserved — R21,P23,N21,M23, R20,P22,N20,M22 — — 18 Reserved — T26,R28,P26,N28, T25,R27,P25,N27 — — 33 SD1_PLL_TPD PLL test point Digital V28 O XVDD 18 SD1_REF_CLK PLL Reference clock U28 I XVDD — SD1_REF_CLK PLL Reference clock complement U27 I XVDD — T22 — — 18 T23 — — 18 Reserved — Reserved — SerDes2(x1) SD2_TX[0] Transmit data(+) P11 O X2VDD — SD2_TX[0] Transmit data(-) P12 O X2VDD — SD2_RX[0] Receive data(+) P6 I X2VDD — SD2_RX[0] Receive data(-) P7 I X2VDD — Reserved — M11,M12 — — 18 Reserved — N8, N9 — — 34 SD2_PLL_TPD PLL test point Digital L7 O X2VDD 18 SD2_REF_CLK PLL Reference clock M6 I X2VDD — SD2_REF_CLK PLL Reference clock complement M7 I X2VDD — Reserved — L8 — X2VDD 18 Reserved — L9 — X2VDD 18 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 15 Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes General-Purpose Input/Output GPIO[0:1]/PCI1_REQ[3:4] GPIO/PCI request Y15,AE15 I/O OVDD — GPIO[2:3]/PCI1_GNT[3:4] GPIO/PCI grant AA15,AC14 I/O OVDD — GPIO[4]/SDHC_CD GPIO/SDHC card detection AH11 I/O OVDD — GPIO[5]/SDHC_WP GPIO/SDHC write protection AG10 I/O OVDD 32 GPIO[6]/USB1_PCTL0 GPIO/USB1 PCTL0 AC3 I/O OVDD — GPIO[7]/USB1_PCTL1 GPIO/USB1 PCTL1 AC4 I/O OVDD — GPIO[8]/USB2_PCTL0 GPIO/USB2 PCTL0 AG9 I/O OVDD — GPIO[9]/USB2_PCTL1 GPIO/USB2 PCTL1 AC9 I/O OVDD — GPIO[10:11] /DMA_DACK[0:1] GPIO/DMA Ack AD6,AE10 I/O OVDD — GPIO[12:13] /DMA_DDONE[0:1] GPIO/DMA done AA11,AB11 I/O OVDD — GPIO[14:15] /DMA_DREQ[0:1] GPIO/DMA request AB10,AD11 I/O OVDD — System Control HRESET Hard reset AG16 I OVDD — HRESET_REQ Hard reset - request AG15 O OVDD 22 SRESET Soft reset AG19 I OVDD — CKSTP_IN CheckStop in AG18 I OVDD — CKSTP_OUT CheckStop Output AH17 O OVDD 2,4 Debug TRIG_IN Trigger in W19 I OVDD — TRIG_OUT/READY /QUIESCE Trigger out/Ready/Quiesce V19 O OVDD 22 MSRCID[0:1] Memory debug source port ID W12,W13 O OVDD 6,9 MSRCID[2:4] Memory debug source port ID V12, W14,W11 O OVDD 6,9,22 MDVAL Memory debug data valid V13 O OVDD 6,22 CLK_OUT Clock Out W15 O OVDD 11 Clock RTC Real time clock AF15 I OVDD — SYSCLK System clock / PCI clock AH14 I OVDD — DDRCLK DDR clock AC13 I OVDD 30 JTAG MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 16 Freescale Semiconductor Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes TCK Test clock AG28 I OVDD — TDI Test data in AH28 I OVDD 12 TDO Test data out AF28 O OVDD 11 TMS Test mode select AH27 I OVDD 12 TRST Test reset AH21 I OVDD 12 DFT L1_TSTCLK L1 test clock AA21 I OVDD 19 L2_TSTCLK L2 test clock AA20 I OVDD 19 LSSD_MODE LSSD Mode AC25 I OVDD 19 TEST_SEL Test select AA13 I OVDD 19 Power Management ASLEEP Asleep AG20 O OVDD 9,16,22 POWER_OK Power OK AC26 I OVDD — POWER_EN Power enable AE27 O OVDD — — OVDD — Power and Ground Signals OVDD General I/O supply Y18,AG2,AD4,AB16, AF6,AC18,AB13,AD10, AE14,AD16,AD25, AF27,AE22,AF11, AF20,AF24 LVDD GMAC 1 I/O supply AA7, AA4 Power for TSEC1 interfaces LVDD — TVDD GMAC 3 I/O supply V4,U7 Power for TSEC3 interfaces TVDD — GVDD SSTL2 DDR supply B1,B11,C7,C9,C14, C17,D4,D6,R3,D15,E2, E8,C24,E18,F5,E14, C21,G3,G7,G9,G11, H5,H12,E22,F15,J10, K3,K12,K14,H14,D20, E11,M1,N5 Power for DDR DRAM I/O GVDD — BVDD Local bus I/O supply L23,J18,J23,J19,F20, F23,H26,J21 Power for Local Bus BVDD — SVDD SerDes 1 core logic supply M27,N25,P28,R24, R26,T24,T27,U25, W24,W26,Y24,Y27, AA25,AB28,AD27 — SVDD — MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 17 Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes XVDD SerDes 1 transceiver supply M21,N23,P20,R22,T20, U23,V21,W22,Y20, AA23 — XVDD — S2VDD SerDes 2 core logic supply R6,N7,M9 — S2VDD — X2VDD SerDes 2 transceiver supply R11,N12,L11 — X2VDD — VDD_CORE Core, L2 logic supply P13,U16,L16,M15,N14, R14,P15,N16,M13, U14,T13,L14,T15,R16, K13 — VDD_CORE — VDD_PLAT Platform logic supply T19,T17,V17,U18,R18, N18,M19,P19,P17,M17 — VDD_PLAT — AVDD_CORE CPU PLL supply AH16 — AVDD_CORE 20,28 AVDD_PLAT Platform PLL supply AH18 — AVDD_PLAT 20 AVDD_DDR DDR PLL supply AH19 — AVDD_DDR 20 AVDD_LBIU Local Bus PLL supply C28 — AVDD_LBIU 20 AVDD_PCI1 PCI PLL supply AH20 — AVDD_PCI1 20 AVDD_SRDS SerDes 1 PLL supply W28 — AVDD_SRDS 20 AVDD_SRDS2 SerDes 2 PLL supply T1 — AVDD_SRDS2 20 SENSEVDD_CORE — V15 — VDD_CORE 13 SENSEVDD_PLAT — W17 — VDD_PLAT 13 GND Ground D5,AE7,F4,D26,D23, C12,C15,E20,D8,B10, AF3,E3,J14,K21,F8,A3, F16,E12,E15,D17,L1, F21,H1,G13,G15,G18, C6,A14,A7,G25,H4, C20,J12,J15,J17,F27, M5,J27,K11,L26,K7, K8,T14,V14,M16,M18, P14,N15,N17,N19,N2, P5,P16,P18,M14,R15, R17,R19,T16,T18,L17, U15,U17,U19,V18,C27, Y13,AE26,AA19,AE21, B28,AC11,AD19,AD23, L15,AD15,AG23,AE9, A27,V7,Y7,AC5,U4,Y4, AE12,AB9,AA14,N13, R13,L13 — — — XGND SerDes 1Transceiver pad GND (xpadvss) M20,M24,N22,P21, R23,T21,U22,V20, W23, Y21 — — — MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 18 Freescale Semiconductor Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes SGND SerDes 1 Transceiver core logic GND (xcorevss) M28,N26,P24,P27, R25,T28,U24,U26,V24, W25,Y28,AA24,AA26, AB24,AB27,AD28 — — — X2GND SerDes 2 Transceiver pad GND (xpadvss) R12,M10,N11,L12 — — — S2GND SerDes 2 Transceiver core logic GND (xcorevss) P8,P9,N6,M8 — — — AGND_SRDS SerDes 1 PLL GND V27 — — — AGND_SRDS2 SerDes 2 PLL GND T2 — — — SENSEVSS GND Sensing V16 — — 13 Analog Signals MVREF SSTL2 reference voltage A28 Reference voltage for DDR GVDD/2 — SD1_IMP_CAL_RX Rx impedance calibration M26 — 200Ω (±1%) to GND — SD1_IMP_CAL_TX Tx impedance calibration AE28 — 100Ω (±1%) to GND — SD1_PLL_TPA PLL test point analog V26 — AVDD_SRD S analog 18 SD2_IMP_CAL_RX Rx impedance calibration R7 — 200Ω (±1%) to GND — SD2_IMP_CAL_TX Tx impedance calibration L6 — 100Ω (±1%) to GND — SD2_PLL_TPA PLL test point analog T3 — AVDD_SRD S2 analog 18 Reserved — R4 — — — Reserved — R5 — — — — — — No Connect Pins NC — C19,D7,D10,L10,R10, B6,F12,J7,P10,M25, W27,N24,N10,R8,J9, K9,V25,R9 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 19 Pin Assignments and Reset States Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes Notes: 1. All multiplexed signals may be listed only once and may not re-occur. 2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OVDD. 3. This pin must always be pulled-high. 4. This pin is an open drain signal. 5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 6. Treat these pins as no connects (NC) unless using debug address functionality. 7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See Section 22.2, “CCB/SYSCLK PLL Ratio.” 8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See the Section 22.3, “e500 Core PLL Ratio.” 9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan. 10.For proper state of these signals during reset, UART_SOUT[1] must be pulled down to GND through a resistor. UART_SOUT[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down the value of the net at reset, then a pullup is needed on UART_SOUT[0]. 11.This output is actively driven during reset rather than being three-stated during reset. 12.These JTAG pins have weak internal pull-up P-FETs that are always enabled. 13.These pins are connected to the VDD_CORE/VDD_PLAT/GND planes internally and may be used by the core power supply to improve tracking and regulation. 15. These pins have other manufacturing or debug test functions. It’s recommended to add both pull-up resistor pads to OVDD and pull-down resistor pads to GND on board to support future debug testing when needed. 16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset. 17. This pin is only an output in FIFO mode when used as Rx Flow Control. 18. Do not connect. 19.These must be pulled up (100 Ω- 1 kΩ) to OVDD. 20. Independent supplies derived from board VDD. 21. Recommend a pull-up resistor (1 KΩ) be placed on this pin to OVDD. 22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0], EC_MDC, TSEC1_TXD[3], TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. 23. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 24. General-Purpose POR configuration of user system. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 20 Freescale Semiconductor Electrical Characteristics Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes 25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as “No Connect” or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the address pins are not connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI device connected on the bus. 26. When operating in DDR2 mode, connect MDIC[0] to ground through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor, and connect MDIC[1] to GVDD through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor. When operating in DDR3 mode, connect MDIC[0] to ground through an 20-Ω (full-strength mode) or 40-Ω (half-strength mode) precision 1% resistor, and connect MDIC[1] to GVDD through an 20-Ω (full-strength mode) or 40-Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR IOs. 27. Connect to GND through a pull down 1 kΩ resistor. 28. It must be the same as VDD_CORE 29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when GCR[DEEPSLEEP_Z] =1. 30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E PowerQUICC III Integrated Host Processor Family Reference Manual , Table 4-3 in section 4.2.2 “Clock Signals”, section 4.4.3.2 “DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding DDR controller operation in asynchronous and synchronous modes. 31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND. 32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for SD/MMC card specification. 33. Must connect to XGND. 34. Must connect to X2GND 35. For systems which boot from Local Bus(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is required. 2 Electrical Characteristics 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 21 Electrical Characteristics 2.1.1 Absolute Maximum Ratings This table provides the absolute maximum ratings. Table 2. Absolute Maximum Ratings1 Characteristic Symbol Max Value Core supply voltage VDD_CORE –0.3 to 1.21 V — Platform supply voltage VDD_PLAT –0.3 to 1.1 V — PLL core supply voltage AVDD_CORE –0.3 to 1.21 V — PLL other supply voltage AVDD –0.3 to 1.1 V — Core power supply for SerDes transceivers SVDD, S2VDD –0.3 to 1.1 V — Pad power supply for SerDes transceivers and PCI Express XVDD, X2VDD –0.3 to 1.1 V — GVDD –0.3 to 1.98 V — DDR SDRAM Controller I/O supply voltage DDR2 SDRAM Interface DDR3 SDRAM Interface Three-speed Ethernet I/O Unit Notes –0.3 to 1.65 LVDD (eTSEC1) –0.3 to 3.63 –0.3 to 2.75 V 2 TVDD (eTSEC3) –0.3 to 3.63 –0.3 to 2.75 V 2 PCI, DUART, system control and power management, I2C, USB, eSDHC, eSPI and JTAG I/O voltage, MII management voltage OVDD –0.3 to 3.63 V — Local bus I/O voltage BVDD –0.3 to 3.63 –0.3 to 2.75 –0.3 to 1.98 V — Input voltage MVIN –0.3 to (GVDD + 0.3) V 3 DDR2/DDR3 DRAM reference MVREF –0.3 to (GVDD + 0.3) V — Three-speed Ethernet signals LVIN TVIN –0.3 to (LVDD + 0.3) –0.3 to (TVDD + 0.3) V 3 Local bus signals BVIN –0.3 to (BVDD + 0.3) — — PCI, DUART, SYSCLK, system control and power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 3 TSTG –55 to 150 0C — DDR2/DDR3 DRAM signals Storage temperature range Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect chip reliability or cause permanent damage to the chip. 2. The 3.63-V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V maximum applies. See Section 2.9.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on the recommended operating conditions per protocol. 3. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 7. 2.1.2 Recommended Operating Conditions This table provides the recommended operating conditions for this chip. Note that the values in this table are the recommended and tested operating conditions. Proper chip operation outside these conditions is not guaranteed. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 22 Freescale Semiconductor Electrical Characteristics Table 3. Recommended Operating Conditions Characteristic Symbol Recommended Value Unit Notes Core supply voltage VDD_CORE 1.0 ± 50 mV V — Platform supply voltage VDD_PLAT 1.0 ± 50 mV V — PLL core supply voltage AVDD_CORE 1.0 ± 50 mV V 2 PLL other supply voltage AVDD 1.0 ± 50 mV V 2 Core power supply for SerDes transceivers SVDD 1.0 ± 50 mV V — Pad power supply for SerDes transceivers and PCI Express XVDD 1.0 ± 50 mV V — DDR SDRAM DDR2 SDRAM Interface Controller I/O supply DDR3 SDRAM Interface voltage GVDD 1.8 V ± 90 mV V 3 V 5 1.5 V ± 75 mV LVDD (eTSEC1) 3.3 V ± 165 mV 2.5 V ± 125 mV TVDD (eTSEC3) 3.3 V ± 165 mV 2.5 V ± 125 mV PCI, DUART, system control and power management, I2C, USB, eSDHC, eSPI and JTAG I/O voltage, MII management voltage OVDD 3.3 V ± 165 mV V 4 Local bus I/O voltage BVDD 3.3 V ± 165 mV 2.5 V ± 125 mV 1.8 V ± 90 mV V — MVIN GND to GVDD V 3 MVREF GVDD/2 ± 1% V — Three-speed Ethernet signals LVIN TVIN GND to LVDD GND to TVDD V 5 Local bus signals BVIN GND to BVDD V — PCI, Local bus, DUART, SYSCLK, system control and power management, I2C, and JTAG signals OVIN GND to OVDD V 4 °C 6 Three-speed Ethernet I/O voltage Input voltage DDR2 and DDR3 SDRAM Interface signals DDR2 and DDR3 SDRAM Interface reference Operating Temperature range Commercial TA= 0 (min) to TJ= 90(max) Industrial standard temperature range Extended temperature range TA TJ TA= 0 (min) to TJ= 105 (max) TA= -40 (min) to TJ= 105 (max) Notes: 2. This voltage is the input to the filter discussed in Section 3.2.1, “PLL Power Supply Filtering,” and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter. 3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. Minimum temperature is specified with TA; maximum temperature is specified with TJ. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 23 Electrical Characteristics This figure shows the undershoot and overshoot voltages at the interfaces of the chip. B/G/L/OVDD + 20% B/G/L/OVDD + 5% B/G/L/OVDD VIH GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tCLOCK1 Note: 1. tCLOCK refers to the clock period associated with the respective interface: For I2C and JTAG, tCLOCK references SYSCLK. For DDR, tCLOCK references MCLK. For eTSEC, tCLOCK references EC_GTX_CLK125. For eLBC, tCLOCK references LCLK. For PCI, tCLOCK references PCI1_CLK or SYSCLK. 2. With the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3). Figure 7. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD The core voltage must always be provided at nominal 1.0 V . (See Table 3 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface uses differential receivers referenced by the externally supplied MVREFn signal (nominally set to GVDD/2) as is appropriate for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 24 Freescale Semiconductor Electrical Characteristics 2.1.3 Output Driver Characteristics This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 4. Output Drive Capability Driver Type Local bus interface utilities signals PCI signals Programmable Output Impedance (Ω) Supply Voltage 25 35 BVDD = 3.3 V BVDD = 2.5 V 45(default) 45(default) 125 BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V 25 OVDD = 3.3 V 2 Notes 1 42 (default) DDR2 signal 16 32 (half strength mode) GVDD = 1.8 V 3 DDR3 signal 20 40 (half strength mode) GVDD = 1.5 V 2 TSEC signals 42 LVDD = 2.5/3.3 V — DUART, system control, JTAG 42 OVDD = 3.3 V — I2C 150 OVDD = 3.3 V — Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset. 3. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at Tj = 105°C and at GVDD (min) 2.2 Power Sequencing The chip requires its power rails to be applied in a specific sequence in order to ensure proper chip operation. These requirements are as follows for power up: 1. 2. 3. VDD_PLAT, VDD_CORE (if POWER_EN is not used to control VDD_CORE), AVDD, BVDD, LVDD, OVDD, SVDD,S2VDD, TVDD, XVDD and X2VDD [Wait for POWER_EN to assert], then VDD_CORE (if POWER_EN is used to control VDD_CORE) GVDD All supplies must be at their stable values within 50 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required. From a system standpoint, if any of the I/O power supplies ramp prior to the VDD platform supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the chip. During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 25 Electrical Characteristics 2.3 Power Characteristics The estimated power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III chips is shown in the following table. Table 5. Power Dissipation 5 Core CCB DDR VDD Frequen Frequen Frequen Platfor Power Mode m cy cy cy VDD Core Junction Tempera ture (V) (°C) mean7 Max mean7 Max 105 /90 — 4.1/3.3 — 4.7/3.7 1, 3, 8 — 3.7/2.9 — 4.7/3.7 1, 4, 8 1.5 — 1.5 — 1, 2 1.2 1.9 1.4 1.9 1 Nap (W) 0.8 1.5 1.4 1.9 1 Sleep (W) 0.8 1.5 1.0 1.6 1 (MHz) (MHz) (MHz) (V) Maximum (A) Thermal (W) Typical (W) Doze (W) 600 400 400 1.0 1.0 65 Core Power Platform Power9 Notes Deep Sleep (W) 35 0 0 0.6 1.1 6 Maximum (A) 105 / 90 — 4.5/3.7 — 4.7/3.7 1, 3, 8 — 3.9/3.1 — 4.7/3.7 1, 4, 8 1.7 — 1.5 — 1, 2 1.3 2.1 1.4 1.9 1 Nap (W) 0.8 1.5 1.4 1.9 1 Sleep (W) 0.8 1.5 1.0 1.6 1 Thermal (W) Typical (W) Doze (W) 800 400 400 1.0 1.0 65 Deep Sleep (W) 35 0 0 0.6 1.1 1,6 Maximum (A) 105 / 90 — 4.8/4.0 — 4.7/3.7 1, 3, 8 — 4.1/3.3 — 4.7/3.7 1, 4, 8 1.9 — 1.5 — 1, 2 1.4 2.2 1.4 1.9 1 Nap (W) 0.8 1.6 1.4 1.9 1 Sleep (W) 0.8 1.6 1.0 1.6 1 0 0 0.6 1.1 1, 6 Thermal (W) Typical (W) Doze (W) Deep Sleep (W) 1000 400 400 1.0 1.0 65 35 MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 26 Freescale Semiconductor Electrical Characteristics Table 5. Power Dissipation (continued)5 Core CCB DDR VDD Frequen Frequen Frequen Platfor Power Mode m cy cy cy VDD Core Junction Tempera ture Platform Power9 Notes (MHz) (MHz) (MHz) (V) (V) (°C) mean7 Max mean7 Max 5.3/4.4 — 5.0/4.0 1, 3, 8 500 500 1.0 1.0 105 / 90 — 1250 — 4.4/3.6 — 5.0/4.0 1, 4, 8 65 2.2 Maximum (A) Thermal (W) Core Power Typical (W) 1.7 1 Doze (W) 1.6 2.4 1.5 2.1 1 Nap (W) 0.8 1.6 1.5 2.1 1 Sleep (W) 0.8 1.6 1.1 1.7 1 0 0 0.6 1.2 1, 6 Deep Sleep (W) 35 Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (VDD) and 65°C junction temperature (see Table 3) while running the Dhrystone benchmark. 3. Maximum power is the maximum power measured with the worst process and recommended core and platform voltage (VDD) at maximum operating junction temperature (see Table 3) while running a smoke test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy. 4. Thermal power is the maximum power measured with worst case process and recommended core and platform voltage (VDD) at maximum operating junction temperature (see Table 3) while running the Dhrystone benchmark. 6. Maximum power is the maximum number measured with USB1, eTSEC1, and DDR blocks enabled. The Mean power is the mean power measured with only external interrupts enabled and DDR in self refresh. 7. Mean power is provided for information purposes only and is the mean power consumed by a statistically significant range of devices. 8. Maximum operating junction temperature (see Table 3) for Commercial Tier is 90 0C, for Industrial Tier is 105 0C. 9. Platform power is the power supplied to all the VDD_PLAT pins. See Section 2.23.6.1, “SYSCLK to Platform Frequency Options,” for the full range of CCB frequencies that the chip supports. MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 Freescale Semiconductor 27 Electrical Characteristics 2.4 Input Clocks 2.4.1 System Clock Timing This table provides the system clock (SYSCLK) AC timing specifications for the chip. Table 6. SYSCLK AC Timing Specifications At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV. Parameter/Condition Symbol Min Typical Max Unit Notes SYSCLK frequency fSYSCLK 33 — 133 MHz 1 SYSCLK cycle time tSYSCLK 7.5 — 30 ns — SYSCLK rise and fall time tKH, tKL 0.6 1.0 2.1 ns 2 tKHK/tSYSCLK 40 — 60 % — — — — +/-150 ps 3, 4 SYSCLK duty cycle SYSCLK jitter Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” and Section 2.23.3, “e500 Core PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V. 3. The SYSCLK driver’s closed loop jitter bandwidth should be