Freescale Semiconductor
MPC8555EEC
Rev. 4.2, 1/2008
Technical Data
MPC8555E PowerQUICC™ III
Integrated Communications Processor
Hardware Specification
The MPC8555E integrates a PowerPC™ processor core
built on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8555E is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the MPC8555E
PowerQUICC™ III Integrated Communications Processor
Reference Manual.
To locate any published errata or updates for this document
refer to http://www.freescale.com or contact your Freescale
sales office.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Three-Speed, MII Management . . . . . . . . . . 22
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 56
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
System Design Information . . . . . . . . . . . . . . . . . . . . . 78
Document Revision History . . . . . . . . . . . . . . . . . . . . 85
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 86
Overview
1
Overview
The following section provides a high-level overview of the MPC8555E features. Figure 1 shows the
major functional units within the MPC8555E.
DDR
SDRAM
DDR SDRAM Controller
Security
Engine
I2C Controller
DUART
GPIO
32b
Local Bus Controller
IRQs
Programmable
Interrupt Controller
MIIs/RMIIs
TDMs
I/Os
Serial Interfaces
MPHY
UTOPIA
Time-Slot Assigner
CPM
FCC
FCC
SCC
SCC/USB
SCC
SMC
SMC
SPI
2
I C
e500
Coherency
Module
Serial
DMA
256-Kbyte
L2 Cache/
SRAM
Core Complex
Bus
e500 Core
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
64/32b PCI Controller
OCeaN
ROM
0/32b PCI Controller
I-Memory
DMA Controller
DPRAM
RISC
Engine
10/100/1000 MAC
Parallel I/O
Baud Rate
Generators
10/100/1000 MAC
MII, GMII, TBI,
RTBI, RGMIIs
Timers
CPM
Interrupt
Controller
Figure 1. MPC8555E Block Diagram
1.1
Key Features
The following lists an overview of the MPC8555E feature set.
• Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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Overview
•
•
Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels,
a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:
— Public Key Execution Unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511-bits
— Data Encryption Standard Execution Unit (DEU)
– DES, 3DES
– Two key (K1, K2) or Three Key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced Encryption Standard Unit (AESU)
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and Counter modes
— ARC Four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message Digest Execution Unit (MDEU)
– SHA with 160-bit or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random Number Generator (RNG)
— 4 Crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments: instruction set supports CRC computation and bit
manipulation.
— Internal timer
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
virtual DMA channels for each peripheral controller
— Handles serial protocols and virtual DMA
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3
Overview
•
— Two full-duplex fast communications controllers (FCCs) that support the following protocols:
– ATM protocol through two UTOPIA level 2 interfaces
– IEEE Std 802.3™/Fast Ethernet (10/100)
– HDLC
– Totally transparent operation
— Three full-duplex serial communications controllers (SCCs) support the following protocols:
– High level/synchronous data link control (HDLC/SDLC)
– LocalTalk (HDLC-based local area network protocol)
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART (1x clock mode)
– Binary synchronous communication (BISYNC)
– Totally transparent operation
– QMC support, providing 64 channels per SCC using only one physical TDM interface
— Universal serial bus (USB) controller that is full/low-speed compliant (multiplexed on an SCC)
– USB host mode
– Supports USB slave mode
— Serial peripheral interface (SPI) support for master or slave
— I2C bus controller
— Two serial management controllers (SMCs) supporting:
– UART
– Transparent
– General-circuit interfaces (GCI)
— Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight
time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following
TDM formats:
– T1/CEPT lines
– T3/E3
– Pulse code modulation (PCM) highway interface
– ISDN primary rate
– Freescale interchip digital link (IDL)
– General circuit interface (GCI)
— User-defined interfaces
— Eight independent baud rate generators (BRGs)
— Four general-purpose 16-bit timers or two 32-bit timers
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
256 Kbytes of on-chip memory
— Can act as a 256-Kbyte level-2 cache
— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays
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Overview
—
—
—
—
—
•
•
•
Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
Full ECC support on 64-bit boundary in both cache and SRAM modes
SRAM operation supports relocation and is byte-accessible
Cache mode supports instruction caching, data caching, or both
External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines
– Individual line locks set and cleared through Book E instructions or by externally mastered
transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI
– Four inbound windows
– Four outbound windows plus default translation for PCI
DDR memory controller
— Programmable timing supporting first generation DDR SDRAM
— 64-bit data interface, up to MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Sleep mode support for self refresh DDR SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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Overview
•
•
•
•
•
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
— Four global high resolution timers/counters that can generate interrupts
— Supports additional internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
Two I2C controllers (one is contained within the CPM, the other is a stand-alone controller which
is not part of the CPM)
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the stand-alone I2C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I2C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (RXD, TXD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Two Three-speed (10/100/1000)Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers
— Support for Ethernet physical interfaces:
– 10/100/1000 Mbps IEEE 802.3 GMII
– 10/100 Mbps IEEE 802.3 MII
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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Overview
•
•
– 10 Mbps IEEE 802.3 MII
– 1000 Mbps IEEE 802.3z TBI
– 10/100/1000 Mbps RGMII/RTBI
— Full- and half-duplex support
— Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— 2-Kbyte internal transmit and receive FIFOs
— MII management interface for control and status
— Programmable CRC generation and checking
OCeaN switch fabric
— Three-port crossbar packet switch
— Reorders packets from a source based on priorities
— Reorders packets to bypass blocked packets
— Implements starvation avoidance algorithms
— Supports packets with payloads of up to 256 bytes
Integrated DMA controller
— Four-channel controller
— All channels accessible by both local and remote masters
— Extended DMA functions (advanced chaining and striding capability)
•
— Support for scatter and gather transfers
— Misaligned transfer capability
— Interrupt on completed segment, link, list, and error
— Supports transfers to or from any local memory or I/O port
— Selectable hardware-enforced coherency (snoop/no-snoop)
— Ability to start and flow control each DMA channel from external 3-pin interface
— Ability to launch DMA from single write transaction
PCI Controllers
— PCI 2.2 compatible
— One 64-bit or two 32-bit PCI ports supported at 16 to 66 MHz
— Host and agent mode support, 64-bit PCI port can be host or agent, if two 32-bit ports, only one
can be an agent
— 64-bit dual address cycle (DAC) support
— Supports PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses
— Supports posting of processor-to-PCI and PCI-to-memory writes
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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Electrical Characteristics
•
•
— PCI 3.3-V compatible
— Selectable hardware-enforced coherency
— Selectable clock source (SYSCLK or independent PCI_CLK)
Power management
— Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O
— Supports power save modes: doze, nap, and sleep
— Employs dynamic power management
— Selectable clock source (sysclk or independent PCI_CLK)
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter specific events
— Supports 64 reference events that can be counted on any of the 8 counters
— Supports duration and quantity threshold counting
•
•
•
2
— Burstiness feature that permits counting of burst events with a programmable time between
bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE Std 1149.1™-compatible, JTAG boundary scan
783 FC-PBGA package
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8555E. The MPC8555E is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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Freescale Semiconductor
Electrical Characteristics
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings 1
Characteristic
Symbol
Max Value
Unit
Core supply voltage
VDD
–0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
PLL supply voltage
AV DD
–0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
DDR DRAM I/O voltage
GVDD
–0.3 to 3.63
V
Three-speed Ethernet I/O, MII management voltage
LVDD
–0.3 to 3.63
–0.3 to 2.75
V
CPM, PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
3
Input voltage
MV IN
–0.3 to (GVDD + 0.3)
V
2, 5
MV REF
–0.3 to (GVDD + 0.3)
V
2, 5
Three-speed Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
4, 5
CPM, Local bus, DUART,
SYSCLK, system control and
power management, I2C, and
JTAG signals
OV IN
–0.3 to (OVDD + 0.3)1
V
5
PCI
OV IN
–0.3 to (OVDD + 0.3)
V
6
TSTG
–55 to 150
°C
DDR DRAM signals
DDR DRAM reference
Storage temperature range
Notes
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GV DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LV DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. OV IN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.
2.1.2
Power Sequencing
The MPC8555Erequires its power rails to be applied in a specific sequence in order to ensure proper device
operation. These requirements are as follows for power up:
1. VDD, AVDDn
2. GVDD, LVDD, OVDD (I/O supplies)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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9
Electrical Characteristics
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value
before the voltage rails on the current step reach ten percent of theirs.
NOTE
If the items on line 2 must precede items on line 1, please ensure that the
delay does not exceed 500 ms and the power sequence is not done greater
than once per day in production environment.
NOTE
From a system standpoint, if the I/O power supplies ramp prior to the VDD
core supply, the I/Os on the MPC8555E may drive a logic one or zero during
power-up.
2.1.3
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8555E. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value
Unit
Core supply voltage
VDD
1.2 V ± 60 mV
1.3 V± 50 mV (for 1 GHz only)
V
PLL supply voltage
AVDD
1.2 V ± 60 mV
1.3 V ± 50 mV (for 1 GHz only)
V
DDR DRAM I/O voltage
GV DD
2.5 V ± 125 mV
V
Three-speed Ethernet I/O voltage
LVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
V
PCI, local bus, DUART, system control and power management,
I2C, and JTAG I/O voltage
OV DD
3.3 V ± 165 mV
V
Input voltage
MVIN
GND to GVDD
V
MVREF
GND to GVDD
V
Three-speed Ethernet signals
LVIN
GND to LVDD
V
PCI, local bus, DUART,
SYSCLK, system control and
power management, I2C, and
JTAG signals
OVIN
GND to OV DD
V
Tj
0 to 105
°C
DDR DRAM signals
DDR DRAM reference
Die-junction Temperature
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8555E.
G/L/OVDD + 20%
G/L/OVDD + 5%
VIH
G/L/OVDD
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tSYS1
Note:
1. Note that tSYS refers to the clock period associated with the SYSCLK signal.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
The MPC8555E core voltage must always be provided at nominal 1.2 V (see Table 2 for actual
recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with
respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to
GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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11
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8555E for the 3.3-V
signals, respectively.
11 ns
(Min)
+7.1 V
Overvoltage
Waveform
7.1 V p-to-p
(Min)
4 ns
(Max)
0V
4 ns
(Max)
62.5 ns
+3.6 V
7.1 V p-to-p
(Min)
Undervoltage
Waveform
–3.5 V
Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
2.1.4
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Driver Type
Local bus interface utilities signals
Programmable Output
Impedance (Ω)
Supply
Voltage
Notes
25
OV DD = 3.3 V
1
42 (default)
PCI signals
25
2
42 (default)
DDR signal
20
GV DD = 2.5 V
TSEC/10/100 signals
42
LVDD = 2.5/3.3 V
DUART, system control, I2C, JTAG
42
OV DD = 3.3 V
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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Power Characteristics
3
Power Characteristics
The estimated typical power dissipation for this family of PowerQUICC III devices is shown in Table 4.
Table 4. Power Dissipation(1) (2)
CCB Frequency (MHz)
Core Frequency (MHz)
VDD
Typical Power(3)(4) (W)
Maximum Power(5) (W)
200
400
1.2
4.9
6.6
500
1.2
5.2
7.0
600
1.2
5.5
7.3
533
1.2
5.4
7.2
667
1.2
5.9
7.7
800
1.2
6.3
9.1
667
1.2
6.0
7.9
833
1.2
6.5
9.3
1000(6)
1.3
9.6
12.8
267
333
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD.
2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance. Any customer design must take these considerations into account to ensure the maximum 105 degrees junction
temperature is not exceeded on this device.
3. Typical power is based on a nominal voltage of VDD = 1.2V, a nominal process, a junction temperature of Tj = 105° C, and a
Dhrystone 2.1 benchmark application.
4. Thermal solutions likely need to design to a value higher than Typical Power based on the end application, TA target, and I/O
power
5. Maximum power is based on a nominal voltage of VDD = 1.2V, worst case process, a junction temperature of Tj = 105° C, and
an artificial smoke test.
6. The nominal recommended VDD = 1.3V for this speed grade.
Notes:
1.
2.
3.
4.
5.
6.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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13
Power Characteristics
Table 5. Typical I/O Power Dissipation
Interface
DDR I/O
PCI I/O
Parameters
GV DD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V)
Unit
Comments
CCB = 200 MHz
0.46
—
—
—
W
—
CCB = 266 MHz
0.59
—
—
—
W
—
CCB = 300 MHz
0.66
—
—
—
W
—
CCB = 333 MHz
0.73
—
—
—
W
—
64b, 66 MHz
—
0.14
—
—
W
—
64b, 33 MHz
—
0.08
—
—
W
—
32b, 66 MHz
—
0.07
—
—
W
Multiply by 2 if using two 32b ports
32b, 33 MHz
—
0.04
—
—
W
32b, 167 MHz
—
0.30
—
—
W
—
32b, 133 MHz
—
0.24
—
—
W
—
32b, 83 MHz
—
0.16
—
—
W
—
32b, 66 MHz
—
0.13
—
—
W
—
32b, 33 MHz
—
0.07
—
—
W
—
MII
—
—
0.01
—
W
GMII or TBI
—
—
0.07
—
W
RGMII or RTBI
—
—
—
0.04
W
MII
—
0.015
—
—
W
—
RMII
—
0.013
—
—
W
—
HDLC 16 Mbps
—
0.009
—
—
W
—
UTOPIA-8 SPHY
—
0.06
—
—
W
—
UTOPIA-8 MPHY
—
0.1
—
—
W
—
UTOPIA-16 SPHY
—
0.094
—
—
W
—
UTOPIA-16 MPHY
—
0.135
—
—
W
—
CPM - SCC
HDLC 16 Mbps
—
0.004
—
—
W
—
TDMA or TDMB
Nibble Mode
—
0.01
—
—
W
—
TDMA or TDMB
Per Channel
—
0.005
—
—
W
Up to 4 TDM channels, multiply by
number of TDM channels.
Local Bus I/O
TSEC I/O
CPM - FCC
Multiply by number of interfaces
used.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
14
Freescale Semiconductor
Clock Timing
4
4.1
Clock Timing
System Clock Timing
Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8555E.
Table 6. SYSCLK AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
—
—
166
MHz
1
SYSCLK cycle time
tSYSCLK
6.0
—
—
ns
—
SYSCLK rise and fall time
tKH, tKL
0.6
1.0
1.2
ns
2
tKHK/tSYSCLK
40
—
60
%
3
—
—
—
+/- 150
ps
4, 5
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. For spread spectrum clocking, guidelines are ±1% of the input frequency with a maximum of 60 kHz of modulation regardless
of the input frequency.
4.2
TSEC Gigabit Reference Clock Timing
Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the
MPC8555E.
Table 7. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
fG125
—
125
—
MHz
—
EC_GTX_CLK125 cycle time
tG125
—
8
—
ns
—
EC_GTX_CLK125 rise time
tG125R
—
—
1.0
ns
1
EC_GTX_CLK125 fall time
tG125F
—
—
1.0
ns
1
%
1, 2
tG125H/tG125
EC_GTX_CLK125 duty cycle
GMII, TBI
RGMII, RTBI
—
45
47
55
53
Notes:
1. Timing is guaranteed by design and characterization.
2. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle
can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
15
RESET Initialization
4.3
Real Time Clock Timing
Table 8 provides the real time clock (RTC) AC timing specifications.
Table 8. RTC AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
RTC clock high time
tRTCH
2x
tCCB_CLK
—
—
ns
—
RTC clock low time
tRTCL
2x
tCCB_CLK
—
—
ns
—
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8555E. Table 9 provides the RESET initialization AC timing specifications.
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
—
μs
—
Minimum assertion time for SRESET
512
—
SYSCLKs
1
PLL input setup time with stable SYSCLK before HRESET
negation
100
—
μs
—
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
4
—
SYSCLKs
1
Input hold time for POR configs (including PLL config) with
respect to negation of HRESET
2
—
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
—
5
SYSCLKs
1
Notes:
1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8555E. See the MPC8555E
PowerQUICC™ III Integrated Communications Processor Reference Manual for more details.
Table 10 provides the PLL and DLL lock times.
Table 10. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs
—
DLL lock times
7680
122,880
CCB Clocks
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the
minimum and an 8:1 ratio results in the maximum.
2. The CCB clock is determined by the SYSCLK × platform PLL ratio.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
16
Freescale Semiconductor
DDR SDRAM
6
DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8555E.
6.1
DDR SDRAM DC Electrical Characteristics
Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8555E.
Table 11. DDR SDRAM DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GV DD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.18
V
—
Output leakage current
IOZ
–10
10
μA
4
Output high current (VOUT = 1.95 V)
IOH
–15.2
—
mA
—
Output low current (VOUT = 0.35 V)
IOL
15.2
—
mA
—
IVREF
—
5
μA
—
MVREF input leakage current
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
Table 12 provides the DDR capacitance.
Table 12. DDR SDRAM Capacitance
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, MSYNC_IN
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GV DD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) = 0.2 V.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
17
DDR SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 13 provides the input AC timing specifications for the DDR SDRAM interface.
Table 13. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF – 0.31
V
—
AC input high voltage
VIH
MV REF + 0.31
GVDD + 0.3
V
—
tDISKEW
—
ps
1
MDQS—MDQ/MECC input skew per
byte
For DDR = 333 MHz
For DDR < 266 MHz
750
1125
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0
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