MPC8568EPXAQGG

Freescale Semiconductor Technical Data Document Number: MPC8568EEC Rev. 1, 10/2010 MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications Due to feature similarities, this document covers both the MPC8568E and MPC8567E features. For simplicity, MPC8568 may only be mentioned throughout the document. The MPC8567E feature differences are as follows: • The MPC8567E PCI-Express supports x1/x2/x4, but does not have x8 support. • Does not have eTSEC1, eTSEC2, or TLU Note that both the MPC8568E and MPC8567E have their own pin assignment tables. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. © 2010 Freescale Semiconductor, Inc. All rights reserved. Contents MPC8568E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ethernet Interface and MII Management . . . . . . . . . . 26 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I 2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 61 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 HDLC, BISYNC, Transparent and Synchronous UART . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 System Design Information . . . . . . . . . . . . . . . . . . . 130 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 136 Document Revision History . . . . . . . . . . . . . . . . . . 138 MPC8568E Overview 1 MPC8568E Overview This section provides a high-level overview of MPC8568E features. Figure 1 shows the major functional units within the MPC8568E. DDR SDRAM 512-Kbyte L2 Cache/ SRAM DDR/DDR2/ Memory Controller Flash SDRAM ZBT RAM Local Bus Controller e500 Coherency Module MPC8568 e500 Core Core Complex Bus 32-Kbyte L1 Data Cache 32-Kbyte L1 Instruction Cache Table Lookup Unit Programmable Interrupt Controller (PIC) DUART I2C I2C Controller I2C I2C Controller QUICC Engine™ eTSEC 10/100/1Gb eTSEC Multi-User RAM Accelerators Baud Rate Generators Dual 32-bit RISC CP 10/100/1Gb Serial DMA & 2 Virtual DMAs XOR Engine SPI2 SPI1 UCC8 UCC7 UCC6 UCC5 Security Engine UCC4 Parallel I/O UCC3 MII, GMII, TBI, RTBI, RGMII, RMII PCI 32-bit 66 MHz 4-Channel DMA Controller UCC2 MII, GMII, TBI, RTBI, RGMII, RMII 4x/1x RapidIO and/or x4/x2/x1 PCI Express or x8 PCI Express 32-bit PCI Bus Interface UCC1 Serial Serial RapidIO and/or PCI Express OceaN Switch Fabric MCC IRQs Time Slot Assigner Serial Interface 8 TDM Ports 8 MII/ RMII 3 GMII/ 2 RGMII/TBI/RTBI 2 UL2/POS Figure 1. MPC8568E Block Diagram MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 2 Freescale Semiconductor MPC8568E Overview 1.1 • • • • • • • • • • • MPCP8568E Key Features High-performance, Power Architecture® e500v2 core with 36-bit physical addressing 512 Kbytes of level-2 cache QUICC Engine (QE) Integrated security engine with XOR acceleration Two integrated 10/100/1Gb enhanced three-speed Ethernet controllers (eTSECs) with TCP/IP acceleration and classification capabilities DDR/DDR2 memory controller Table lookup unit (TLU) to access application-defined routing topology and control tables 32-bit PCI controller A 1x/4x Serial RapidIO® and/or x1/x2/x4 PCI Express interface. If x8 PCI Express is needed, then RapidIO is not available due to the limitation of the pin multiplexing. Programmable interrupt controller (PIC) Four-channel DMA controller, two I2C controllers, DUART, and local bus controller (LBC) NOTE The MPC8568E and MPC8567E are also available without a security engine in a configuration known as the MPC8568 and MPC8567. All specifications other than those relating to security apply to the MPC8568 and MPC8567 exactly as described in this document. 1.2 1.2.1 MPC8568E Architecture Overview e500 Core and Memory Unit The MPC8568E contains a high-performance, 32-bit, Book E–enhanced e500v2 Power Architecture core. In addition to 36-bit physical addressing, this version of the e500 core includes the following: • Double-precision floating-point APU—Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs • Embedded vector and scalar single-precision floating-point APUs—Provide an instruction set for single-precision (32-bit) floating-point instructions The MPC8568E also contains 512 Kbytes of L2 cache/SRAM, as follows: • Eight-way set-associative cache organization with 32-byte cache lines • Flexible configuration (can be configured as part cache, part SRAM) • External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). • SRAM features include the following: — I/O devices access SRAM regions by marking transactions as snoopable (global). — Regions can reside at any aligned location in the memory map. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 3 MPC8568E Overview — Byte-accessible ECC uses read-modify-write transaction accesses for smaller-than-cache-line accesses. 1.2.2 e500 Coherency Module (ECM) and Address Map The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be routed or dispatched to target modules on the device. The MPC8568E supports a flexible 36-bit physical address map. Conceptually, the address map consists of local space and external address space. The local address map is supported by eight local access windows that define mapping within the local 36-bit (64-Gbyte) address space. The MPC8568E can be made part of a larger system address space through the mapping of translation windows. This functionality is included in the address translation and mapping units (ATMUs). Both inbound and outbound translation windows are provided. The ATMUs allows the MPC8568E to be part of larger address maps such as the PCI or PCI Express 64-bit address environment and the RapidIO environment. 1.2.3 • • • QUICC Engine Integrated 8-port L2 Ethernet switch — 8 connection ports of 10/100 Mbps MII/RMII & one CPU internal port — Each port supports four priority levels — Priority levels used with VLAN tags or IP TOS field to implement QoS — QoS types of traffic, such as voice, video, and data Includes support for the following protocols: — ATM SAR up to 622 Mbps (OC-12) full duplex, with ATM traffic shaping (ATF TM4.1) for up to 64K ATM connections — ATM AAL1 structured and unstructured Circuit Emulation Service (CES 2.0) — IMA and ATM Transmission convergence sub-layer — ATM OAM handling features compatible with ITU-T I.610 — PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs: 1661, 1662, 1990, 2686 and 3153 — IP termination support for IPv4 and IPv6 packets including TOS, TTL and header checksum processing — ATM (AAL2/AAL5) to Ethernet (IP) interworking — Extensive support for ATM statistics and Ethernet RMON/MIB statistics. — 256 channels of HDLC/Transparent or 128 channels of SS#7 Includes support for the following serial interfaces: — Two UL2/POS-PHY interfaces with 124 Multi-PHY addresses on UTOPIA interface each or 31 Multi-PHY addresses on the POS interface each. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 4 Freescale Semiconductor MPC8568E Overview — Three 1-Gbps Ethernet interfaces using three GMII, two RGMII/TBI/RTBI — Up to eight 10/100-Mbps Ethernet interfaces using MII or RMII — Up to eight T1/E1/J1/E3 or DS-3 serial interfaces 1.2.4 Integrated Security Engine (SEC) The SEC is a modular and scalable security core optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of the data. The version of the SEC used in the MPC8568E is specifically capable of performing single-pass security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i. • Optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP • Compatible with code written for the Freescale MPC8541E and MPC8555E devices • XOR engine for parity checking in RAID storage applications. • Four crypto-channels, each supporting multi-command descriptor chains • Cryptographic execution units: — PKEU—public key execution unit — DEU—Data Encryption Standard execution unit — AESU—Advanced Encryption Standard unit — AFEU—ARC four execution unit — MDEU—message digest execution unit — KEU—Kasumi execution unit — RNG—Random number generator 1.2.5 Enhanced Three-Speed Ethernet Controllers The MPC8568E has two on-chip enhanced three-speed Ethernet controllers (eTSECs). The eTSECs incorporate a media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps Ethernet/802.3 networks with MII, RMII, GMII, RGMII, TBI, and RTBI physical interfaces. The eTSECs include 2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions. The MPC8568E eTSECs support programmable CRC generation and checking, RMON statistics, and jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache to speed classification or other frame processing. They are IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab-compatible. The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models. Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with minimal change. Some of the key features of these controllers include: • Flexible configuration for multiple PHY interface configurations. Table 1 lists available configurations. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 5 MPC8568E Overview Table 1. Supported eTSEC1 and eTSEC2 Configurations1 Mode Option eTSEC1 eTSEC2 Ethernet standard interfaces TBI, GMII, or MII TBI, GMII, or MII Ethernet reduced interfaces RTBI, RGMII, or RMII RTBI, RGMII, or RMII FIFO and mixed interfaces 8-bit FIFO TBI, GMII, MII, RTBI, RGMII, RMII, or 8-bit FIFO TBI, GMII, MII, RTBI, RGMII, RMII, or 8-bit FIFO 8-bit FIFO 16-bit FIFO Not used/not available 1 Both interfaces must use the same voltage (2.5 or 3.3 V). • TCP/IP acceleration and QoS features: — IP v4 and IP v6 header recognition on receive — IP v4 header checksum verification and generation — TCP and UDP checksum verification and generation — Per-packet configurable acceleration — Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks, and ESP/AH IP-security headers — Supported in all FIFO modes — Transmission from up to eight physical queues — Reception to up to eight physical queues • Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex): — IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition) IEEE Std 802.1™ virtual local area network (VLAN) tags and priority VLAN insertion and deletion – Per-frame VLAN control word or default VLAN for each eTSEC – Extracted VLAN control word passed to software separately Programmable Ethernet preamble insertion and extraction of up to 7 bytes MAC address recognition Ability to force allocation of header information and buffer descriptors into L2 cache • • • • • 1.2.6 DDR SDRAM Controller The MPC8568E supports DDR SDRAM and DDR2 SDRAM. The memory interface controls main memory accesses and provides for a maximum of 16 Gbytes of main memory. The MPC8568E supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs or directly-attached memory devices. Sixteen multiplexed address signals provide for device densities of 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbits, 2 Gbits and 4 Gbits. Four chip select signals support MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 6 Freescale Semiconductor MPC8568E Overview up to four banks of memory. The MPC8568E supports bank sizes from 64 Mbytes to 4 Gbytes. Nine column address strobes (MDM[0:8]) are used to provide byte selection for memory bank writes. The MPC8568E can be configured to retain the currently active SDRAM page for pipelined burst accesses. Page mode support of up to 16 simultaneously open pages (32 for DDR2) can dramatically reduce access latencies for page hits. Depending on the memory system design and timing parameters, using page mode can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page. Using ECC, the MPC8568E detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble. The MPC8568E can invoke a level of system power management by asserting the MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode. 1.2.7 Table Lookup Unit (TLU) The table lookup unit (TLU) provides access to application-defined routing topology and control tables in external memory. It accesses an external memory array attached to the local bus controller (LBC). Communication between the CPU and the TLU occurs via messages passed through the TLU’s memory-mapped configuration and status registers. The TLU provides resources for efficient generation of table entry addresses in memory, hash generation of addresses, and binary table searching algorithms for both exact-match and longest-prefix-match strategies.It supports the following TLU complex table types: • Hash-Trie-Key table for hash-based exact-match algorithms • Chained-Hash table for partially indexed and hashed exact-match algorithms • Longest-prefix-match algorithm • Flat-Data table for retrieving search results and simple indexed algorithms 1.2.8 PCI Controller The MPC8568E supports one 32-bit PCI controller, which supports speeds of up to 66 MHz. Other features include: • Compatible with the PCI Local Bus Specification, Revision 2.2, supporting 32- and 64-bit addressing • Can function as host or agent bridge interface • As a master, supports read and write operations to PCI memory space, PCI I/O space, and PCI configuration space • Can generate PCI special-cycle and interrupt-acknowledge commands. As a target, it supports read and write operations to system memory as well as configuration accesses. • Supports PCI-to-memory and memory-to-PCI streaming, memory prefetching of PCI read accesses, and posting of processor-to-PCI and PCI-to-memory writes • PCI 3.3-V compatible with selectable hardware-enforced coherency MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 7 MPC8568E Overview 1.2.9 High Speed I/O Interfaces The MPC8568E supports two high-speed I/O interface standards: serial RapidIO and PCI Express. It can be configured as x1/x4 SRIO and 1x/2x/4x PCI Express simultaneously with the following limitation: • Both SRIO and PCI-Express are limited to use the same clock and are limited to 2.5G. • Spread spectrum clocking can not be used because SRIO doesn't support this (PCI-Express does support it). If x8 PCI Express is needed, then SRIO is not available due to the pin multiplex limitation. 1.2.10 Serial RapidIO The serial RapidIO interface is based on the RapidIO Interconnect Specification, Revision 1.2. RapidIO is a high-performance, point-to-point, low-pin-count, packet-switched system-level interconnect that can be used in a variety of applications as an open standard. The RapidIO architecture has a rich variety of features including high data bandwidth, low-latency capability, and support for high-performance I/O devices, as well as support for message-passing and software-managed programming models. Key features of the serial RapidIO interface unit include: • Support for RapidIO Interconnect Specification, Revision 1.2 (all transaction flows and priorities) • Both 1x and 4x LP-serial link interfaces, with transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane • Auto detection of 1x or 4x mode operation during port initialization • 34-bit addressing and up to 256-byte data payload • Receiver-controlled flow control • Support for RapidIO error injection The RapidIO messaging unit supports two inbox/outbox mailboxes (queues) for data and one doorbell message structure. Both chaining and direct modes are provided for the outbox, and messages can hold up to 16 packets of 256 bytes, or a total of 4 Kbytes. 1.2.11 PCI Express Interface The MPC8568E supports a PCI Express interface compatible with the PCI Express Base Specification Revision 1.0a. It is configurable at boot time to act as either root complex or endpoint.The physical layer of the PCI Express interface operates at a 2.5-Gbaud data rate per lane. Other features of the PCI Express interface include: • x8, x4, x2, and x1 link widths supported • Selectable operation as root complex or endpoint • Both 32- and 64-bit addressing and 256-byte maximum payload size • Full 64-bit decode with 32-bit wide windows MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 8 Freescale Semiconductor MPC8568E Overview 1.2.12 Programmable Interrupt Controller (PIC) The MPC8568E PIC implements the logic and programming structures of the OpenPIC architecture, providing for external interrupts (with fully nested interrupt delivery), message interrupts, internal-logic driven interrupts, and global high-resolution timers. Up to 16 programmable interrupt priority levels are supported. The PIC can be bypassed to allow use of an external interrupt controller. 1.2.13 DMA Controller, I2C, DUART, and Local Bus Controller The MPC8568E provides an integrated four-channel DMA controller, which can transfer data between any of its I/O or memory ports or between two devices or locations on the same port. The DMA controller also: • Allows chaining (both extended and direct) through local memory-mapped chain descriptors. • Scattering, gathering, and misaligned transfers are supported. In addition, stride transfers and complex transaction chaining are supported. • Local attributes such as snoop and L2 write stashing can be specified. There are two I2C controllers. These synchronous, multimaster buses can be connected to additional devices for expansion and system development. The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550 programming models. 16-byte FIFOs are supported for both the transmitter and the receiver. The MPC8568E local bus controller (LBC) port allows connections with a wide variety of external memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be programmed separately to access different types of devices. The general-purpose chip select machine (GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The user programmable machine (UPM) can be programmed to interface to synchronous devices or custom ASIC interfaces. The SDRAM controller provides access to standard SDRAM. Each chip select can be configured so that the associated chip interface can be controlled by the GPCM, UPM, or SDRAM controller. All may exist in the same system. The local bus controller supports the following features: • Multiplexed 32-bit address and data bus operating at up to 133 MHz • Eight chip selects support eight external slaves • Up to eight-beat burst transfers • 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller • Three protocol engines available on a per-chip-select basis • Parity support • Default boot ROM chip select with configurable bus width (8, 16, or 32 bits) • Supports zero-bus-turnaround (ZBT) RAM 1.2.14 Power Management In addition to low-voltage operation and dynamic power management, which automatically minimizes power consumption of blocks when they are idle, four power consumption modes are supported: full on, doze, nap, and sleep. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 9 Electrical Characteristics 1.2.15 System Performance Monitor The performance monitor facility supports eight 32-bit counters that can count up to 512 counter-specific events. It supports duration and quantity threshold counting and a burstiness feature that permits counting of burst events with a programmable time between bursts. 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8568E. This device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 2. Absolute Maximum Ratings 1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD –0.3 to 1.21 V — PLL supply voltage AVDD_PLAT, AVDD_CORE, AV DD_CE, AVDD_PCI, AV DD_LBIU, AVDD_SRDS –0.3 to 1.21 V — Core power supply for SerDes transceiver SCOREVDD –0.3 to 1.21 V — Pad power supply for SerDes transceiver XVDD –0.3 to 1.21 V — DDR and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75 –0.3 to 1.98 V — eTSEC1, eTSEC2 I/O Voltage LVDD –0.3 to 3.63 –0.3 to 2.75 V — QE UCC1/UCC2 Ethernet Interface I/O Voltage TVDD –0.3 to 3.63 –0.3 to 2.75 V — PCI, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD –0.3 to 3.63 V 3 Local bus I/O voltage BVDD –0.3 to 3.63 –0.3 to 2.75 V 3 MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 10 Freescale Semiconductor Electrical Characteristics Table 2. Absolute Maximum Ratings 1 (continued) Characteristic Input voltage Symbol Max Value MVIN –0.3 to (GVDD + 0.3) V 2, 5 DDR/DDR2 DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5 Three-speed Ethernet signals LVIN TVIN –0.3 to (LVDD + 0.3) –0.3 to (TVDD + 0.3) V 4, 5 Local bus signals BVIN –0.3 to (BVDD + 0.3) DUART, SYSCLK, system control and power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 5 PCI OVIN –0.3 to (OVDD + 0.3) V 6 TSTG –55 to 150 •C C — DDR/DDR2 DRAM signals Storage temperature range Unit Notes — Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 2. 2.1.2 Recommended Operating Conditions Table 3 provides the recommended operating conditions for this device. Note that the values in Table 3 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 3. Recommended Operating Conditions Symbol Recommended Value Core supply voltage VDD 1.1 V ± 55 mV V — PLL supply voltage AVDD_PLAT, AV DD_CORE, AVDD_CE, AVDD_PCI, AVDD_LBIU, AVDD_SRDS 1.1 V ± 55 mV V — Core power supply for SerDes transceiver SCOREVDD 1.1 V ± 55 mV V — Pad power supply for SerDes transceiver XVDD 1.1 V ± 55 mV V — DDR and DDR2 DRAM I/O voltage GVDD 2.5 V ± 125 mV 1.8 V ± 90 mV V — Characteristic Unit Notes MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 11 Electrical Characteristics Table 3. Recommended Operating Conditions (continued) Symbol Recommended Value Three-speed Ethernet I/O voltage LV DD TV DD 3.3 V ± 165 mV 2.5 V ± 125 mV V — PCI, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD 3.3 V ± 165 mV V — Local bus I/O voltage BVDD 3.3 V ± 165 mV 2.5 V ± 125 mV V — MVIN GND to GVDD V — MVREF GND to GVDD/2 V — Three-speed Ethernet signals LVIN TVIN GND to LVDD GND to TVDD V — Local bus signals BVIN GND to BVDD V — PCI, DUART, SYSCLK, system control and power management, I2C, and JTAG signals OVIN GND to OV DD V — Tj 0 to105 oC — Characteristic Input voltage DDR and DDR2 DRAM signals DDR and DDR2 DRAM reference Junction temperature range Unit Notes Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8568E. B/G/L/T/OVDD + 20% B/G/L/T/OVDD + 5% B/G/L/T/OVDD VIH GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tCLOCK1 Note: 1. Note that tCLOCK refers to the clock period associated with the respective interface For I2C and JTAG, tCLOCK references SYSCLK. For DDR, tCLOCK references MCLK. For eTSEC, tCLOCK references EC_GTX_CLK125. For LBIU, tCLOCK references LCLK. For PCI, tCLOCK references PCI_CLK or SYSCLK. For SerDes, tCLOCK references SD_REF_CLK. 2. Note that with the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3) Figure 2. Overshoot/Undershoot Voltage for BVDD/GVDD/LVDD/TVDD/OVDD MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 12 Freescale Semiconductor Electrical Characteristics The core voltage must always be provided at nominal 1.1V. (See Table 3 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard. 2.1.3 Output Driver Characteristics Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 4. Output Drive Capability Driver Type Programmable Output Impedance (Ω) Supply Voltage 25 25 BVDD = 3.3 V BVDD = 2.5 V 45(default) 45(default) BVDD = 3.3 V BVDD = 2.5 V 25 OVDD = 3.3 V 2 Local bus interface utilities signals PCI signals Notes 1 42 (default) DDR signal 20 GVDD = 2.5 V — DDR2 signal 16 32 (half strength mode) GVDD = 1.8 V — eTSEC 10/100/1000 signals 42 L/TVDD = 2.5/3.3 V — DUART, system control, JTAG 42 OVDD = 3.3 V — I2C 150 OVDD = 3.3 V — Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT[1] signal at reset. 2.2 Power Sequencing The MPC8568E requires its power rails to be applied in specific sequence in order to ensure proper device operation. These requirements are as follows for power up: 1. VDD, AVDD_n, BVDD, SCOREVDD, LVDD, TVDD, XVDD, OVDD 2. GVDD All supplies must be at their stable values within 50 ms. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 13 Power Characteristics NOTE Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required. 3 Power Characteristics The power dissipation of VDD for various core complex bus (CCB) versus the core and QE frequency for MPC8568E is shown in Table 5. Note that this is based on the design estimate only. More accurate power number will be available after we have done the measurement on the silicon. Table 5. MPC8568E Power Dissipation CCB Frequency Core Frequency QE Frequency Typical 65°C Typical 105°C Maximum Unit 400 800 400 8.7 12.0 13.0 W 400 1000 400 8.9 12.3 13.6 W 400 1200 400 11.3 15.7 16.9 W 533 1333 533 12.4 17.2 18.7 W Notes: 1. CCB Frequency is the SoC platform frequency which corresponds to DDR data rate. 2. Typical 65 °C based on VDD=1.1V, Tj=65. 3. Typical 105 °C based on VDD=1.1V, Tj=105. 4. Maximum based on VDD=1.1V, Tj=105. Table 6. Typical MPC8568E I/O Power Dissipation Interface Parameters Local Bus PCI BVDD OV DD LV DD 3.3 V 2.5 V TVDD 3.3 V XVDD Unit Comment 2.5 V 1.8 V 3.3 V 2.5 V 0.76 0.50 W 400 MHz 0.56 W 533 MHz 0.68 W Data rate 64-bit with ECC 60% utilization 333 MHz DDR/DDR2 GVDD 2.5 V 33 MHz, 32b 0.07 0.04 W — 66 MHz, 32b 0.13 0.07 W — 133 MHz, 32b 0.24 0.14 W — 33 MHz 0.04 W — 66 MHz 0.07 W — SRIO 4x, 3.125G 0.49 W — PCI Express 8x, 2.5G 0.71 W — MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 14 Freescale Semiconductor Input Clocks Table 6. Typical MPC8568E I/O Power Dissipation (continued) GVDD Interface 2.5 V eTSEC Ethernet BVDD LV DD Parameters 1.8 V 3.3 V 2.5 V OV DD 3.3 V QE UCC 2.5 V 3.3 V 2.5 V XVDD Unit Comment Multiply with number of the interfaces MII 0.01 W GMII/TBI 0.07 W RGMII/RTBI eTSEC FIFO I/O TVDD 0.04 W 16b, 200 MHz 0.20 W 16b, 155 MHz 0.16 W 8b, 200 MHz 0.11 W 8b, 155 MHz 0.08 W MII/RMII 0.01 W GMII/TBI 0.07 W RGMII/RTBI 0.04 Multiply with number of the interfaces Multiply with number of the interfaces W If UCC is programmed for other protocols, scale Ethernet power dissipation to the number of signals and the clock rate Note: This is the power for each individual interface. The power must be calculated for each interface being utilized. 4 Input Clocks 4.1 System Clock Timing Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8568E. Table 7. SYSCLK AC Timing Specifications At recommended operating conditions (see Table 3) with OVDD = 3.3 V ± 165 mV. Parameter/Condition Symbol Min Typical Max Unit Notes SYSCLK frequency fSYSCLK — — 166 MHz 1 SYSCLK cycle time tSYSCLK 6.0 — — ns — SYSCLK rise and fall time tKH, tKL 0.6 1.0 2.3 ns 2 tKHK/tSYSCLK 40 — 60 % 3 SYSCLK duty cycle MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 15 Input Clocks Table 7. SYSCLK AC Timing Specifications (continued) At recommended operating conditions (see Table 3) with OVDD = 3.3 V ± 165 mV. Parameter/Condition Symbol Min Typical Max Unit Notes — — — +/– 150 ps 4, 5 SYSCLK jitter Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 core frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 23.2, “CCB/SYSCLK PLL Ratio and Section 23.3, “e500 Core PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The SYSCLK driver’s closed loop jitter bandwidth should be