MPC8572ECPXAULB

NXP Semiconductors Technical Data Document Number: MPC8572EEC Rev. 7, 03/2016 MPC8572E PowerQUICC III Integrated Processor Hardware Specifications 1 Overview This section provides a high-level overview of the features of the MPC8572E processor. Figure 1 shows the major functional units within the MPC8572E. 1.1 Key Features The following list provides an overview of the MPC8572E feature set: • Two high-performance, 32-bit, Book E-enhanced cores that implement the Power Architecture® technology: — Each core is identical to the core within the MPC8572E processor. — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. — Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ¬© 2008-2011, 2014, 2016 NXP B.V. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18 DDR2 and DDR3 SDRAM Controller . . . . . . . . . . . 19 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 28 Ethernet Management Interface Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 50 Local Bus Controller (eLBC) . . . . . . . . . . . . . . . . . . 53 Programmable Interrupt Controller . . . . . . . . . . . . . 65 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 72 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Package Description . . . . . . . . . . . . . . . . . . . . . . . . 101 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 System Design Information . . . . . . . . . . . . . . . . . . 127 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 137 Document Revision History . . . . . . . . . . . . . . . . . . 139 Overview • • • the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. — Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. — Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. — 36-bit real addressing — Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte to 4-Gbyte page sizes. — Enhanced hardware and software debug support — Performance monitor facility that is similar to, but separate from, the MPC8572E performance monitor The e500 defines features that are not implemented on this device. It also generally defines some features that this device implements more specifically. An understanding of these differences can be critical to ensure proper operation. 1 Mbyte L2 cache/SRAM — Shared by both cores. — Flexible configuration and individually configurable per core. — Full ECC support on 64-bit boundary in both cache and SRAM modes — Cache mode supports instruction caching, data caching, or both. — External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). – 1, 2, or 4 ways can be configured for stashing only. — Eight-way set-associative cache organization (32-byte cache lines) — Supports locking entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions. — Global locking and Flash clearing done through writes to L2 configuration registers — Instruction and data locks can be Flash cleared separately. — Per-way allocation of cache region to a given processor. — SRAM features include the following: – 1, 2, 4, or 8 ways can be configured as SRAM. – I/O devices access SRAM regions by marking transactions as snoopable (global). – Regions can reside at any aligned location in the memory map. – Byte-accessible ECC is protected using read-modify-write transaction accesses for smaller-than-cache-line accesses. e500 coherency module (ECM) manages core and intrasystem transactions Address translation and mapping unit (ATMU) — Twelve local access windows define mapping within local 36-bit address space. — Inbound and outbound ATMUs map to larger external address spaces. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 2 NXP Semiconductors Overview – – – – • • Three inbound windows plus a configuration window on PCI Express Four inbound windows plus a default window on Serial RapidIO® Four outbound windows plus default translation for PCI Express Eight outbound windows plus default translation for Serial RapidIO with segmentation and sub-segmentation support Two 64-bit DDR2/DDR3 memory controllers — Programmable timing supporting DDR2 and DDR3 SDRAM — 64-bit data interface per controller — Four banks of memory supported, each up to 4 Gbytes, for a maximum of 16 Gbytes per controller — DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports — Full ECC support — Page mode support – Up to 32 simultaneous open pages for DDR2 or DDR3 — Contiguous or discontiguous memory mapping — Cache line, page, bank, and super-bank interleaving between memory controllers — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self-refresh SDRAM — On-die termination support when using DDR2 or DDR3 — Supports auto refreshing — On-the-fly power management using CKE signal — Registered DIMM support — Fast memory access through JTAG port — 1.8-V SSTL_1.8 compatible I/O — Support 1.5-V operation for DDR3. The detail is TBD pending on official release of appropriate industry specifications. — Support for battery-backed main memory Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture. — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts per processor with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller — Four global high resolution timers/counters per processor that can generate interrupts — Supports a variety of other internal interrupt sources MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 NXP Semiconductors 3 Overview • • — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing. — Interrupts can be routed to the e500 core’s standard or critical interrupt inputs. — Interrupt summary registers allow fast identification of interrupt source. Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE, SSL/TLS, SRTP, 802.16e, and 3GPP — Four crypto-channels, each supporting multi-command descriptor chains – Dynamic assignment of crypto-execution units through an integrated controller – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes — PKEU—public key execution unit – RSA and Diffie-Hellman; programmable field size up to 4096 bits – Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to 1023 bits — DEU—Data Encryption Standard execution unit – DES, 3DES – Two key (K1, K2, K1) or three key (K1, K2, K3) – ECB, CBC and OFB-64 modes for both DES and 3DES — AESU—Advanced Encryption Standard unit – Implements the Rijndael symmetric key cipher – ECB, CBC, CTR, CCM, GCM, CMAC, OFB-128, CFB-128, and LRW modes – 128-, 192-, and 256-bit key lengths — AFEU—ARC four execution unit – Implements a stream cipher compatible with the RC4 algorithm – 40- to 128-bit programmable key — MDEU—message digest execution unit – SHA-1 with 160-bit message digest – SHA-2 (SHA-256, SHA-384, SHA-512) – MD5 with 128-bit message digest – HMAC with all algorithms — KEU—Kasumi execution unit – Implements F8 algorithm for encryption and F9 algorithm for integrity checking – Also supports A5/3 and GEA-3 algorithms — RNG—random number generator — XOR engine for parity checking in RAID storage applications — CRC execution unit – CRC-32 and CRC-32C Pattern Matching Engine with DEFLATE decompression MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 4 NXP Semiconductors Overview • • • • • — Regular expression (regex) pattern matching – Built-in case insensitivity, wildcard support, no pattern explosion – Cross-packet pattern detection – Fast pattern database compilation and fast incremental updates – 16000 patterns, each up to 128 bytes in length – Patterns can be split into 256 sets, each of which can contain 16 subsets — Stateful rule engine enables hardware execution of state-aware logic when a pattern is found – Useful for contextual searches, multi-pattern signatures, or for performing additional checks after a pattern is found – Capable of capturing and utilizing data from the data stream (such as LENGTH field) and using that information in subsequent pattern searches (for example, positive match only if pattern is detected within the number of bytes specified in the LENGTH field) – 8192 stateful rules — Deflate engine – Supports decompression of DEFLATE compression format including zlib and gzip – Can work independently or in conjunction with the Pattern Matching Engine (that is decompressed data can be passed directly to the Pattern Matching Engine without further software involvement or memory copying) Two Table Lookup Units (TLU) — Hardware-based lookup engine offloads table searches from e500 cores — Longest prefix match, exact match, chained hash, and flat data table formats — Up to 32 tables, with each table up to 16M entries — 32-, 64-, 96-, or 128-bit keys Two I2C controllers — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus Boot sequencer — Optionally loads configuration data from serial ROM at reset the I2C interface — Can be used to initialize configuration registers and/or memory — Supports extended I2C addressing mode — Data integrity checked with preamble signature and CRC DUART — Two 4-wire interfaces (SIN, SOUT, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D Enhanced local bus controller (eLBC) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 NXP Semiconductors 5 Overview — — — — — • Multiplexed 32-bit address and data bus operating at up to 150 MHz Eight chip selects support eight external slaves Up to 8-beat burst transfers The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. Three protocol engines available on a per-chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – NAND Flash control machine (FCM) — Parity support — Default boot ROM chip select with configurable bus width (8, 16, or 32 bits) Four enhanced three-speed Ethernet controllers (eTSECs) — Three-speed support (10/100/1000 Mbps) — Four IEEE Std 802.3®, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab-compatible controllers — Support for various Ethernet physical interfaces: – 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, RGMII, and SGMII – 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII — Flexible configuration for multiple PHY interface configurations — TCP/IP acceleration and QoS features available – IP v4 and IP v6 header recognition on receive – IP v4 header checksum verification and generation – TCP and UDP checksum verification and generation – Per-packet configurable acceleration – Recognition of VLAN, stacked (Q-in-Q) VLAN, 802.2, PPPoE session, MPLS stacks, and ESP/AH IP-security headers – Supported in all FIFO modes — Quality of service support: – Transmission from up to eight physical queues – Reception to up to eight physical queues — Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex): – IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition) — Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE Std 802.1™ virtual local area network (VLAN) tags and priority — VLAN insertion and deletion – Per-frame VLAN control word or default VLAN for each eTSEC – Extracted VLAN control word passed to software separately — Retransmission following a collision MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 6 NXP Semiconductors Overview • • • — CRC generation and verification of inbound/outbound frames — Programmable Ethernet preamble insertion and extraction of up to 7 bytes — MAC address recognition: – Exact match on primary and virtual 48-bit unicast addresses – VRRP and HSRP support for seamless router fail-over – Up to 16 exact-match MAC addresses supported – Broadcast address (accept/reject) – Hash table match on up to 512 multicast addresses – Promiscuous mode — Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet programming models — RMON statistics support — 10-Kbyte internal transmit and 2-Kbyte receive FIFOs — Two MII management interfaces for control and status — Ability to force allocation of header information and buffer descriptors into L2 cache 10/100 Fast Ethernet controller (FEC) management interface — 10/100 Mbps full and half-duplex IEEE 802.3 MII for system management — Note: When enabled, the FEC occupies eTSEC3 and eTSEC4 parallel interface signals. In such a mode, eTSEC3 and eTSEC4 are only available through SGMII interfaces. OCeaN switch fabric — Full crossbar packet switch — Reorders packets from a source based on priorities — Reorders packets to bypass blocked packets — Implements starvation avoidance algorithms — Supports packets with payloads of up to 256 bytes Two integrated DMA controllers — Four DMA channels per controller — All channels accessible by the local masters — Extended DMA functions (advanced chaining and striding capability) — Misaligned transfer capability — Interrupt on completed segment, link, list, and error — Supports transfers to or from any local memory or I/O port — Selectable hardware-enforced coherency (snoop/no snoop) — Ability to start and flow control up to 4 (both Channel 0 and 1 for each DMA Controller) of the 8 total DMA channels from external 3-pin interface by the remote masters — The Channel 2 of DMA Controller 2 is only allowed to initiate and start a DMA transfer by the remote master, because only one of the 3-external pins (DMA2_DREQ[2]) is made available MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 NXP Semiconductors 7 Overview • • — Ability to launch DMA from single write transaction Serial RapidIO interface unit — Supports RapidIO Interconnect Specification, Revision 1.2 — Both 1x and 4x LP-serial link interfaces — Long- and short-haul electricals with selectable pre-compensation — Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane — Auto-detection of 1x- and 4x-mode operation during port initialization — Link initialization and synchronization — Large and small size transport information field support selectable at initialization time — 34-bit addressing — Up to 256 bytes data payload — All transaction flows and priorities — Atomic set/clr/inc/dec for read-modify-write operations — Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at a remote memory system — Receiver-controlled flow control — Error detection, recovery, and time-out for packets and control symbols as required by the RapidIO specification — Register and register bit extensions as described in part VIII (Error Management) of the RapidIO specification — Hardware recovery only — Register support is not required for software-mediated error recovery. — Accept-all mode of operation for fail-over support — Support for RapidIO error injection — Internal LP-serial and application interface-level loopback modes — Memory and PHY BIST for at-speed production test RapidIO–compliant message unit — 4 Kbytes of payload per message — Up to sixteen 256-byte segments per message — Two inbound data message structures within the inbox — Capable of receiving three letters at any mailbox — Two outbound data message structures within the outbox — Capable of sending three letters simultaneously — Single segment multicast to up to 32 devIDs — Chaining and direct modes in the outbox — Single inbound doorbell message structure — Facility to accept port-write messages MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 8 NXP Semiconductors Overview • • • • • • • Three PCI Express controllers — PCI Express 1.0a compatible — Supports x8, x4, x2, and x1 link widths (see following bullet for specific width configuration options) — Auto-detection of number of connected lanes — Selectable operation as root complex or endpoint — Both 32- and 64-bit addressing — 256-byte maximum payload size — Virtual channel 0 only — Full 64-bit decode with 36-bit wide windows Pin multiplexing for the high-speed I/O interfaces supports one of the following configurations: — Single x8/x4/x2/x1 PCI Express — Dual x4/x2/x1 PCI Express — Single x4/x2/x1 PCI Express and dual x2/x1 PCI Express — Single 1x/4x Serial RapidIO and single x4/x2/x1 PCI Express Power management — Supports power saving modes: doze, nap, and sleep — Employs dynamic power management, that automatically minimizes power consumption of blocks when they are idle System performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the eight counters — Supports duration and quantity threshold counting — Permits counting of burst events with a programmable time between bursts — Triggering and chaining capability — Ability to generate an interrupt on overflow System access port — Uses JTAG interface and a TAP controller to access entire system memory map — Supports 32-bit accesses to configuration registers — Supports cache-line burst accesses to main memory — Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download IEEE Std 1149.1™ compatible, JTAG boundary scan 1023 FC-PBGA package MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 NXP Semiconductors 9 Electrical Characteristics Figure 1 shows the MPC8572E block diagram. DDR2/3 SDRAM 64b DDR2/DDR3 Memory Controller DDR2/3 SDRAM 64b DDR2/DDR3 Memory Controller (NOR/NAND) Flash GPIO Enhanced Local Bus Controller e500 Core 32-Kbyte L1 Instruction Cache Security Engine XOR Engine Table Lookup Unit Table Lookup Unit IRQs MPC8572E Pattern Matching Deflate Engine Engine e500 Coherency Module 1-Mbyte L2 Cache/ SRAM Core Complex Bus e500 Core 32-Kbyte L1 Instruction Cache Programmable Interrupt Controller (PIC) Serial 32-Kbyte L1 Data Cache 32-Kbyte L1 Data Cache DUART I2C I2C Controller I2C I2C Controller MII, GMII, TBI, RTBI, RGMII, RMII, SGMII, FIFO MII, GMII, TBI, RTBI, RGMII, RMII, SGMII, FIFO MII, GMII, TBI, RTBI, RGMII, RMII, SGMII, FIFO RTBI, RGMII, RMII, SGMII MII eTSEC Serial RapidIO PCI Express OceaN Switch Fabric 10/100/1Gb 4x Serial RapidIO x8/x4/x2/x1 PCI Express Serial RapidIO Messaging Unit eTSEC 10/100/1Gb eTSEC 4-Channel DMA Controller External control 4-Channel DMA Controller External control 10/100/1Gb eTSEC 10/100/1Gb FEC Figure 1. MPC8572E Block Diagram 2 Electrical Characteristics This section provides the AC and DC electrical specifications for the MPC8572E. The MPC8572E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 10 NXP Semiconductors Electrical Characteristics 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings1 Characteristic Symbol Range Core supply voltage VDD –0.3 to 1.21 V — PLL supply voltage AVDD –0.3 to 1.21 V — Core power supply for SerDes transceivers SVDD –0.3 to 1.21 V — Pad power supply for SerDes transceivers XVDD –0.3 to 1.21 V — DDR SDRAM Controller I/O supply voltage DDR2 SDRAM Interface GVDD –0.3 to 1.98 V — DDR3 SDRAM Interface — –0.3 to 1.65 LVDD (for eTSEC1 and eTSEC2) –0.3 to 3.63 –0.3 to 2.75 V 2 TVDD (for eTSEC3 and eTSEC4, FEC) –0.3 to 3.63 –0.3 to 2.75 — 2 DUART, system control and power management, I2C, and JTAG I/O voltage OVDD –0.3 to 3.63 V — Local bus and GPIO I/O voltage BVDD –0.3 to 3.63 –0.3 to 2.75 –0.3 to 1.98 V — Input voltage MVIN –0.3 to (GVDD + 0.3) V 3 MVREFn –0.3 to (GVDD/2 + 0.3) V — Three-speed Ethernet signals LVIN TVIN –0.3 to (LVDD + 0.3) –0.3 to (TVDD + 0.3) V 3 Local bus and GPIO signals BVIN –0.3 to (BVDD + 0.3) — — DUART, SYSCLK, system control and power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 3 TSTG –55 to 150 °C — Three-speed Ethernet I/O, FEC management interface, MII management voltage DDR2 and DDR3 SDRAM interface signals DDR2 and DDR3 SDRAM interface reference Storage temperature range Unit Notes — Notes: 1. Functional operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. The 3.63V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V maximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on the recommended operating conditions per protocol. 3. (M,L,O)VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 NXP Semiconductors 11 Electrical Characteristics 2.1.2 Recommended Operating Conditions Table 2 provides the recommended operating conditions for this device. Note that the values shown are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Symbol Recommended Value Unit Notes Core supply voltage VDD 1.1 V ± 55 mV V — PLL supply voltage AVDD 1.1 V ± 55 mV V 1 Core power supply for SerDes transceivers SVDD 1.1 V ± 55 mV V — Pad power supply for SerDes transceivers XVDD 1.1 V ± 55 mV V — DDR SDRAM Controller I/O supply voltage GVDD 1.8 V ± 90 mV V — DDR2 SDRAM Interface DDR3 SDRAM Interface 1.5 V ± 75 mV — LVDD 3.3 V ± 165 mV 2.5 V ± 125 mV TVDD 3.3 V ± 165 mV 2.5 V ± 125 mV DUART, system control and power management, I2C, and JTAG I/O voltage OVDD 3.3 V ± 165 mV V 3 Local bus and GPIO I/O voltage BVDD 3.3 V ± 165 mV 2.5 V ± 125 mV 1.8 V ± 90 mV V — Input voltage MVIN GND to GVDD V 2 MVREFn GVDD/2 ± 1% V — Three-speed Ethernet signals LVIN TVIN GND to LVDD GND to TVDD V 4 Local bus and GPIO signals BVIN GND to BVDD V — Local bus, DUART, SYSCLK, Serial RapidIO, system control and power management, I2C, and JTAG signals OVIN GND to OVDD V 3 TJ 0 to 105 °C — Three-speed Ethernet I/O voltage DDR2 and DDR3 SDRAM Interface signals DDR2 and DDR3 SDRAM Interface reference Junction temperature range V 4 4 Notes: 1. This voltage is the input to the filter discussed in Section 21.2.1, “PLL Power Supply Filtering,” and not necessarily the voltage at the AVDD pin, that may be reduced from VDD by the filter. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 12 NXP Semiconductors Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8572E. T/B/G/L/OVDD + 20% T/B/G/L/OVDD + 5% T/B/G/L/OVDD VIH GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tCLOCK1 Note: tCLOCK refers to the clock period associated with the respective interface: For I2C and JTAG, tCLOCK references SYSCLK. For DDR, tCLOCK references MCLK. For eTSEC, tCLOCK references EC_GTX_CLK125. For eLBC, tCLOCK references LCLK. Figure 2. Overshoot/Undershoot Voltage for TVDD/BVDD/GVDD/LVDD/OVDD The core voltage must always be provided at nominal 1.1 V. (See Table 2 for actual recommended core voltage.) Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. TVDD, BVDD, OVDD, and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface uses differential receivers referenced by the externally supplied MVREFn signal (nominally set to GVDD/2) as is appropriate for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 NXP Semiconductors 13 Electrical Characteristics 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. Table 3. Output Drive Capability Programmable Output Impedance (Ω) Supply Voltage 25 35 BVDD = 3.3 V BVDD = 2.5 V 45(default) 45(default) 125 BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V DDR2 signal 18 36 (half strength mode) GVDD = 1.8 V 2 DDR3 signal 20 40 (half strength mode) GVDD = 1.5 V 2 eTSEC/10/100 signals 45 L/TVDD = 2.5/3.3 V — DUART, system control, JTAG 45 OVDD = 3.3 V — I2C 150 OVDD = 3.3 V — Driver Type Local bus interface utilities signals Notes 1 Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at Tj = 105°C and at GVDD (min). 2.2 Power Sequencing The MPC8572E requires its power rails to be applied in a specific sequence to ensure proper device operation. These requirements are as follows for power up: 1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD_SRDS1 and SVDD_SRDS2, TVDD, XVDD_SRDS1 and XVDD_SRDS2 2. GVDD All supplies must be at their stable values within 50 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. To guarantee MCKE low during power-on reset, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-on reset, then the sequencing for GVDD is not required. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 14 NXP Semiconductors Power Characteristics NOTE From a system standpoint, if any of the I/O power supplies ramp prior to the VDD core supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-on reset, and extra current may be drawn by the device. 3 Power Characteristics The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III devices with out the L in its part ordering is shown in Table 4. Table 4. MPC8572E Power Dissipation 1 CCB Frequency Core Frequency Typical-652 Typical-1053 Maximum4 Unit 533 1067 12.3 17.8 18.5 W 533 1200 12.3 17.8 18.5 W 533 1333 16.3 22.8 24.5 W 600 1500 17.3 23.9 25.9 W Notes: 1 This reflects the MPC8572E power dissipation excluding the power dissipation from B/G/L/O/T/XVDD rails. Typical-65 is based on VDD = 1.1 V, Tj = 65 °C, running Dhrystone. 3 Typical-105 is based on V DD = 1.1 V, Tj = 105 °C, running Dhrystone. 4 Maximum is based on VDD = 1.1 V, Tj = 105 °C, running a smoke test. 2 The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III devices with the L in its port ordering is shown in Table 5. Table 5. MPC8572EL Power Dissipation 1 CCB Frequency Core Frequency Typical-652 Typical-1053 Maximum4 Unit 533 1067 12 15 15.8 W 533 1200 12 15.5 16.3 W 533 1333 12 15.9 16.9 W 600 1500 13 18.7 20.0 W Notes: 1 This reflects the MPC8572E power dissipation excluding the power dissipation from B/G/L/O/T/XVDD rails. Typical-65 is based on VDD = 1.1 V, Tj = 65 °C, running Dhrystone. 3 Typical-105 is based on V DD = 1.1 V, Tj = 105 °C, running Dhrystone. 4 Maximum is based on VDD = 1.1 V, Tj = 105 °C, running a smoke test. 2 MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 NXP Semiconductors 15 Input Clocks 4 4.1 Input Clocks System Clock Timing Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8572E. Table 6. SYSCLK AC Timing Specifications At recommended operating conditions with OVDD of 3.3V ± 5%. Parameter/Condition Symbol Min Typical Max Unit Notes SYSCLK frequency fSYSCLK 33 — 133 MHz 1 SYSCLK cycle time tSYSCLK 7.5 — 30.3 ns — SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns 2 tKHK/tSYSCLK 40 — 60 % 3 — — — +/– 150 ps 4, 5, 6 SYSCLK duty cycle SYSCLK jitter Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies.Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The SYSCLK driver’s closed loop jitter bandwidth should be